diff options
104 files changed, 1883 insertions, 1218 deletions
@@ -364,7 +364,12 @@ endif endif DTC_FLAGS += -I dts -O dtb -DTC_CPPFLAGS += -P -nostdinc -Iinclude -Ifdts -undef -x assembler-with-cpp +DTC_CPPFLAGS += -P -nostdinc -Iinclude -Ifdts -undef \ + -x assembler-with-cpp $(DEFINES) + +ifeq ($(MEASURED_BOOT),1) +DTC_CPPFLAGS += -DMEASURED_BOOT -DBL2_HASH_SIZE=${TCG_DIGEST_SIZE} +endif ################################################################################ # Common sources and include directories @@ -826,7 +831,7 @@ $(eval $(call assert_boolean,SPMD_SPM_AT_SEL2)) $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT)) $(eval $(call assert_boolean,USE_COHERENT_MEM)) $(eval $(call assert_boolean,USE_DEBUGFS)) -$(eval $(call assert_boolean,USE_FCONF_BASED_IO)) +$(eval $(call assert_boolean,ARM_IO_IN_DTB)) $(eval $(call assert_boolean,USE_ROMLIB)) $(eval $(call assert_boolean,USE_TBBR_DEFS)) $(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY)) @@ -904,7 +909,7 @@ $(eval $(call add_define,SPMD_SPM_AT_SEL2)) $(eval $(call add_define,TRUSTED_BOARD_BOOT)) $(eval $(call add_define,USE_COHERENT_MEM)) $(eval $(call add_define,USE_DEBUGFS)) -$(eval $(call add_define,USE_FCONF_BASED_IO)) +$(eval $(call add_define,ARM_IO_IN_DTB)) $(eval $(call add_define,USE_ROMLIB)) $(eval $(call add_define,USE_TBBR_DEFS)) $(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY)) @@ -938,13 +943,18 @@ $(eval $(call add_define,USE_ARM_LINK)) endif # Generate and include sp_gen.mk if SPD is spmd and SP_LAYOUT_FILE is defined -ifdef SP_LAYOUT_FILE ifeq (${SPD},spmd) +ifdef SP_LAYOUT_FILE + ifeq (${SPMD_SPM_AT_SEL2},0) + $(error "SPMD with SPM at S-EL1 does not require SP_LAYOUT_FILE") + endif -include $(BUILD_PLAT)/sp_gen.mk FIP_DEPS += sp NEED_SP_PKG := yes else - $(error "SP_LAYOUT_FILE will be used only if SPD=spmd") + ifeq (${SPMD_SPM_AT_SEL2},1) + $(error "SPMD with SPM at S-EL2 require SP_LAYOUT_FILE") + endif endif endif diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index 9da2f9af9..e9478380c 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -371,12 +371,16 @@ tsp_args_t *tsp_smc_handler(uint64_t func, tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); INFO("TSP: cpu 0x%lx received %s smc 0x%llx\n", read_mpidr(), ((func >> 31) & 1) == 1 ? "fast" : "yielding", func); INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(), tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); + spin_unlock(&console_lock); +#endif /* Render secure services and obtain results here */ results[0] = arg1; diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst index f86280f76..f089a5ed6 100644 --- a/docs/change-log-upcoming.rst +++ b/docs/change-log-upcoming.rst @@ -20,15 +20,27 @@ New Features ^^^^^^^^^^^^ - Arm Architecture + - Add support for Armv8.4-SecEL2 extension through the SPCI defined SPMD/SPMC + components. + - Build option to support EL2 context save and restore in the secure world + (CTX_INCLUDE_EL2_REGS). - Example: "Add support for Branch Target Identification (BTI)" +- BL-specific + - Enhanced BL2 bootloader flow to load secure partitions based on firmware + configuration data (fconf). + - Build System - Add support for documentation build as a target in Makefile - Add ``COT`` build option to select the chain of trust to use when the Trusted Boot feature is enabled (default: ``tbbr``). + - Added creation and injection of secure partition packages into the FIP. + - Build option to support SPMC component loading and run at S-EL1 + or S-EL2 (SPMD_SPM_AT_SEL2). - CPU Support - Example: "cortex-a55: Workaround for erratum 1221012" + - Use Speculation Barrier instruction for v8.5+ cores - Drivers - Example: "console: Allow the console to register multiple times" @@ -36,6 +48,7 @@ New Features - Libraries - Example: "Introduce BTI support in Library at ROM (romlib)" - Add Firmware Configuration Framework (fconf). + - Add DebugFS functionality - New Platforms Support - Example: "qemu/qemu_sbsa: New platform support added for QEMU SBSA platform" @@ -43,6 +56,8 @@ New Features - Platforms - Example: "arm/common: Introduce wrapper functions to setup secure watchdog" - plat/arm: Add support for the new `dualroot` chain of trust. + - plat/arm/fvp: Add support for fconf in BL31 and SP_MIN. Populate power + domain desciptor dynamically by leveraging fconf APIs. - PSCI - Example: "Adding new optional PSCI hook ``pwr_domain_on_finish_late``" @@ -51,6 +66,10 @@ New Features - Example: "UBSAN support and handlers" - Add support for optional firmware encryption feature (experimental). - Introduce a new `dualroot` chain of trust. + - aarch32: stop speculative execution past exception returns. + +- SPCI + - Introduced the SPM Dispatcher (SPMD) component as a new standard service. - Tools - Example: "fiptool: Add support to build fiptool on Windows." @@ -84,6 +103,7 @@ Changed - Example: "Refactor SPSR initialisation code" - Tools + - sptool updated to accomodate building secure partition packages. - Example: "cert_create: Remove RSA PKCS#1 v1.5 support" diff --git a/docs/components/spci-manifest-binding.rst b/docs/components/spci-manifest-binding.rst new file mode 100644 index 000000000..66cca643b --- /dev/null +++ b/docs/components/spci-manifest-binding.rst @@ -0,0 +1,239 @@ +SPCI manifest binding to device tree +==================================== + +This document defines the nodes and properties used to define a partition, +according to the SPCI specification. + +Version 1.0 +----------- + +spci-manifest-partition +^^^^^^^^^^^^^^^^^^^^^^^ + +- compatible [mandatory] + - value type: <string> + - Must be the string "arm,spci-manifest-X.Y" which specifies the major and + minor versions fo the device tree binding for the SPCI manifest represented + by this node. The minor number is incremented if the binding changes in a + backwards compatible manner. + - X is an integer representing the major version number of this document. + - Y is an integer representing the minor version number of this document. + +- spci-version [mandatory] + - value type: <u32> + - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X, + 15:0 -> Y, where: + - X is the major version of PSA-FF-A expected by the partition at the SPCI + instance it will execute. + - Y is the minor version of PSA-FF-A expected by the partition at the SPCI + instance it will execute. + +- uuid [mandatory] + - value type: <prop-encoded-array> + - An array consisting of 4 <u32> values, identifying the UUID of the service + implemented by this partition. The UUID format is described in RFC 4122. + UUID can be shared by multiple instances of partitions that offer the same + service For example: + - If there are multiple instances of a Trusted OS, then the UUID can be + shared by all instances. + - The TEE driver in the HLOS can use the UUID with the + SPCI_PARTITION_INFO_GET interface to determine the: + - Number of Trusted OSs + - The partition ID of each instance of the Trusted OS + +- id + - value type: <u32> + - Pre-allocated partition ID. + +- auxiliary-id + - value type: <u32> + - Pre-allocated ID that could be used in memory management transactions. + +- description + - value type: <string> + - Name of the partition e.g. for debugging purposes. + +- execution-ctx-count [mandatory] + - value type: <u32> + - Number of vCPUs that a VM or SP wants to instantiate. + - In the absence of virtualization, this is the number of execution + contexts that a partition implements. + - If value of this field = 1 and number of PEs > 1 then the partition is + treated as UP & migrate capable. + - If the value of this field > 1 then the partition is treated as a MP + capable partition irrespective of the number of PEs. + +- exception-level [mandatory] + - value type: <u32> + - The target exception level for the partition: + - 0x0: EL1 + - 0x1: S_EL0 + - 0x2: S_EL1 + - 0x3: EL2 + - 0x4: Supervisor mode + - 0x5: Secure User mode + +- execution-state [mandatory] + - value type: <u32> + - The target execution state of the partition: + - 0: AArch64 + - 1: AArch32 + +- load-address + - value type: <u64> + - Physical base address of the partition in memory. Absence of this field + indicates that the partition is position independent and can be loaded at + any address chosen at boot time. + +- entrypoint-offset + - value type: <u64> + - Offset from the base of the partition's binary image to the entry point of + the partition. Absence of this field indicates that the entry point is at + offset 0x0 from the base of the partition's binary. + +- xlat-granule [mandatory] + - value type: <u32> + - Translation granule used with the partition: + - 0x0: 4k + - 0x1: 16k + - 0x2: 32k + +- boot-order + - value type: <u32> + - A unique number amongst all partitions that specifies if this partition + must be booted before others. The partition with the smaller number will be + booted first. + +- rx-tx-buffer + - value type: "memory-regions" node + - Specific "memory-regions" nodes that describe the RX/TX buffers expected + by the partition. + The "compatible" must be the string "arm,spci-manifest-rx_tx-buffer". + +- messaging-method [mandatory] + - value type: <u32> + - Specifies which messaging methods are supported by the partition: + - 0x0: direct messaging method + - 0x1: indirect messaging method + - 0x2: both direct and indirect messaging methods + +- has-primary-scheduler + - value type: <empty> + - Presence of this field indicates that the partition implements the primary + scheduler. If so, run-time EL must be EL1. + +- run-time-model + - value type: <u32> + - Run time model that the SPM must enforce for this SP: + - 0x0: Run to completion + - 0x1: Preemptible + +- time-slice-mem + - value type: <empty> + - Presence of this field indicates that the partition doesn't expect the + partition manager to time slice long running memory management functions. + +- gp-register-num + - value type: <u32> + - Presence of this field indicates that the partition expects the + spci_init_info structure to be passed in via the specified general purpose + register. + The field specifies the general purpose register number but not its width. + The width is derived from the partition's execution state, as specified in + the partition properties. For example, if the number value is 1 then the + general-purpose register used will be x1 in AArch64 state and w1 in AArch32 + state. + +- stream-endpoint-ids + - value type: <prop-encoded-array> + - List of <u32> tuples, identifying the IDs this partition is acting as + proxy for. + +memory-regions +-------------- + +- compatible [mandatory] + - value type: <string> + - Must be the string "arm,spci-manifest-memory-regions". + +- description + - value type: <string> + - Name of the memory region e.g. for debugging purposes. + +- pages-count [mandatory] + - value type: <u32> + - Count of pages of memory region as a multiple of the translation granule + size + +- attributes [mandatory] + - value type: <u32> + - ?? TO DEFINE + +- base-address + - value type: <u64> + - Base address of the region. The address must be aligned to the translation + granule size. + The address given may be a Physical Address (PA), Virtual Address (VA), or + Intermediate Physical Address (IPA). Refer to the SPCI specification for + more information on the restrictions around the address type. + If the base address is omitted then the partition manager must map a memory + region of the specified size into the partition's translation regime and + then communicate the region properties (including the base address chosen + by the partition manager) to the partition. + +device-regions +-------------- + +- compatible [mandatory] + - value type: <string> + - Must be the string "arm,spci-manifest-device-regions". + +- description + - value type: <string> + - Name of the device region e.g. for debugging purposes. + +- reg [mandatory] + - value type: <prop-encoded-array> + - A (address, num-pages) pair describing the device, where: + - address: The physical base address <u64> value of the device MMIO + region. + - num-pages: The <u32> number of pages of the region. The total size of + the region is this value multiplied by the translation granule size. + +- attributes [mandatory] + - value type: <u32> + - ?? TO DEFINE + +- smmu-id + - value type: <u32> + - On systems with multiple System Memory Management Units (SMMUs) this + identifier is used to inform the partition manager which SMMU the device is + upstream of. If the field is omitted then it is assumed that the device is + not upstream of any SMMU. + +- stream-ids [mandatory] + - value type: <prop-encoded-array> + - A list of (id, mem-manage) pair, where: + - id: A unique <u32> value amongst all devices assigned to the partition. + - mem-manage: A <u32> value used in memory management operations. + +- interrupts [mandatory] + - value type: <prop-encoded-array> + - A list of (id, attributes) pair describing the device interrupts, where: + - id: The <u32> interrupt IDs. + - attributes: A ?? TO DEFINE value, + containing the attributes for each interrupt ID: + - Interrupt type: SPI, PPI, SGI + - Interrupt configuration: Edge triggered, Level triggered + - Interrupt security state: Secure, Non-secure + - Interrupt priority value + - Target execution context/vCPU for each SPI + +- exclusive-access + - value type: <empty> + - Presence of this field implies that this endpoint must be granted exclusive + access and ownership of this devices's MMIO region. + +-------------- + +*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index f138feb4c..50cafcfa0 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -146,6 +146,12 @@ Common build options is on hardware that does not implement AArch32, or at least not at EL1 and higher ELs). Default value is 1. +- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore + operations when entering/exiting an EL2 execution context. This is of primary + interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). + This option must be equal to 1 (enabled) when ``SPD=spmd`` and + ``SPMD_SPM_AT_SEL2`` is set. + - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP registers to be included when saving and restoring the CPU context. Default is 0. @@ -536,8 +542,8 @@ Common build options - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be isolated on separate memory pages. This is a trade-off between security and memory usage. See "Isolating code and read-only data on separate memory - pages" section in :ref:`Firmware Design`. This flag is disabled by default and - affects all BL images. + pages" section in :ref:`Firmware Design`. This flag is disabled by default + and affects all BL images. - ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS sections of BL31 (.bss, stacks, page tables, and coherent memory) to be @@ -550,7 +556,9 @@ Common build options This build option is only valid if ``ARCH=aarch64``. The value should be the path to the directory containing the SPD source, relative to ``services/spd/``; the directory is expected to contain a makefile called - ``<spd-value>.mk``. + ``<spd-value>.mk``. The SPM Dispatcher standard service is located in + services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher + cannot be enabled when the ``SPM_MM`` option is enabled. - ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops @@ -558,13 +566,23 @@ Common build options firmware images have been loaded in memory, and the MMU and caches are turned off. Refer to the "Debugging options" section for more details. +- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM + Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC + component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 + extension. This is the default when enabling the SPM Dispatcher. When + disabled (0) it indicates the SPMC component runs at the S-EL1 execution + state. This latter configuration supports pre-Armv8.4 platforms (aka not + implementing the Armv8.4-SecEL2 extension). + - ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure - Partition Manager (SPM) implementation. The default value is ``0``. + Partition Manager (SPM) implementation. The default value is ``0`` + (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is + enabled (``SPD=spmd``). - ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the - description of secure partitions. Build system will parse this file and - package all secure partition blobs in FIP. This file not necessarily be - part of TF-A tree. Only avaialbe when ``SPD=spmd``. + description of secure partitions. The build system will parse this file and + package all secure partition blobs into the FIP. This file is not + necessarily part of TF-A tree. Only available when ``SPD=spmd``. - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles secure interrupts (caught through the FIQ line). Platforms can enable @@ -622,8 +640,8 @@ Common build options exposing a virtual filesystem interface through BL31 as a SiP SMC function. Default is 0. -- ``USE_FCONF_BASED_IO``: This flag determines whether to use IO based on the - firmware configuration framework. This allows moving the io_policies into a +- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the + firmware configuration framework. This will move the io_policies into a configuration device tree, instead of static structure in the code base. diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index d6572f507..2d17f122a 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -1117,7 +1117,7 @@ the log output. The implementation should be robust to future changes that increase the number of log levels. Function : plat_get_soc_version() -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: @@ -1132,7 +1132,7 @@ This function returns soc version which mainly consist of below fields soc_version[23:16] = JEP-106 identification code with parity bit for the SiP Function : plat_get_soc_revision() -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst index 372d38867..6c488b827 100644 --- a/docs/plat/hikey.rst +++ b/docs/plat/hikey.rst @@ -26,9 +26,6 @@ Code Locations - l-loader: `link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__ -- uefi-tools: - `link <https://git.linaro.org/uefi/uefi-tools.git>`__ - - atf-fastboot: `link <https://github.com/96boards-hikey/atf-fastboot/tree/master>`__ @@ -45,7 +42,6 @@ Build Procedure git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5 git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4 git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2 - git clone https://git.linaro.org/uefi/uefi-tools git clone https://github.com/96boards-hikey/atf-fastboot - Create the symbol link to OpenPlatformPkg in edk2. @@ -57,13 +53,12 @@ Build Procedure - Prepare AARCH64 && AARCH32 toolchain. Prepare python. -- If your hikey hardware is built by CircuitCo, update *uefi-tools/platform.config* first. *(optional)* - **Uncomment the below sentence. Otherwise, UEFI can't output messages on serial +- If your hikey hardware is built by CircuitCo, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dsc* first. *(optional)* console on hikey.** .. code:: shell - BUILDFLAGS=-DSERIAL_BASE=0xF8015000 + DEFINE SERIAL_BASE=0xF8015000 If your hikey hardware is built by LeMaker, nothing to do. @@ -71,19 +66,8 @@ Build Procedure .. code:: shell - BUILD_OPTION=DEBUG - export AARCH64_TOOLCHAIN=GCC5 - export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools - export EDK2_DIR=${BUILD_PATH}/edk2 - EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey/${BUILD_OPTION}_${AARCH64_TOOLCHAIN} - # Build fastboot for Trusted Firmware-A. It's used for recovery mode. - cd ${BUILD_PATH}/atf-fastboot - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=hikey DEBUG=1 - # Convert DEBUG/RELEASE to debug/release - FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]') - cd ${EDK2_DIR} - # Build UEFI & Trusted Firmware-A - ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey + cd {BUILD_PATH}/arm-trusted-firmware + sh ../l-loader/build_uefi.sh hikey - Generate l-loader.bin and partition table for aosp. The eMMC capacity is either 8GB or 4GB. Just change "aosp-8g" to "linux-8g" for debian. diff --git a/docs/plat/hikey960.rst b/docs/plat/hikey960.rst index 3d42a77c5..982c2c854 100644 --- a/docs/plat/hikey960.rst +++ b/docs/plat/hikey960.rst @@ -26,9 +26,6 @@ Code Locations - l-loader: `link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__ -- uefi-tools: - `link <https://git.linaro.org/uefi/uefi-tools.git>`__ - Build Procedure ~~~~~~~~~~~~~~~ @@ -42,7 +39,6 @@ Build Procedure git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5 git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4 git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2 - git clone https://git.linaro.org/uefi/uefi-tools - Create the symbol link to OpenPlatformPkg in edk2. @@ -53,13 +49,11 @@ Build Procedure - Prepare AARCH64 toolchain. -- If your hikey960 hardware is v1, update *uefi-tools/platform.config* first. *(optional)* - **Uncomment the below sentence. Otherwise, UEFI can't output messages on serial - console on hikey960 v1.** +- If your hikey960 hardware is v1, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dsc* first. *(optional)* .. code:: shell - BUILDFLAGS=-DSERIAL_BASE=0xFDF05000 + DEFINE SERIAL_BASE=0xFDF05000 If your hikey960 hardware is v2 or newer, nothing to do. @@ -67,14 +61,8 @@ Build Procedure .. code:: shell - BUILD_OPTION=DEBUG - export AARCH64_TOOLCHAIN=GCC5 - export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools - export EDK2_DIR=${BUILD_PATH}/edk2 - EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey960/${BUILD_OPTION}_${AARCH64_TOOLCHAIN} - cd ${EDK2_DIR} - # Build UEFI & Trusted Firmware-A - ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey960 + cd {BUILD_PATH}/arm-trusted-firmware + sh ../l-loader/build_uefi.sh hikey960 - Generate l-loader.bin and partition table. *Make sure that you're using the sgdisk in the l-loader directory.* diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk index 044b368bc..564a4c932 100644 --- a/drivers/auth/mbedtls/mbedtls_common.mk +++ b/drivers/auth/mbedtls/mbedtls_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -75,10 +75,19 @@ endif ifeq (${HASH_ALG}, sha384) TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA384 + MBEDTLS_MD_ID := MBEDTLS_MD_SHA384 + TPM_ALG_ID := TPM_ALG_SHA384 + TCG_DIGEST_SIZE := 48 else ifeq (${HASH_ALG}, sha512) - TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA512 + TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA512 + MBEDTLS_MD_ID := MBEDTLS_MD_SHA512 + TPM_ALG_ID := TPM_ALG_SHA512 + TCG_DIGEST_SIZE := 64 else TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA256 + MBEDTLS_MD_ID := MBEDTLS_MD_SHA256 + TPM_ALG_ID := TPM_ALG_SHA256 + TCG_DIGEST_SIZE := 32 endif ifeq (${TF_MBEDTLS_KEY_ALG},ecdsa) @@ -103,6 +112,11 @@ $(eval $(call add_define,TF_MBEDTLS_KEY_SIZE)) $(eval $(call add_define,TF_MBEDTLS_HASH_ALG_ID)) $(eval $(call add_define,TF_MBEDTLS_USE_AES_GCM)) +# Set definitions for measured boot driver +$(eval $(call add_define,MBEDTLS_MD_ID)) +$(eval $(call add_define,TPM_ALG_ID)) +$(eval $(call add_define,TCG_DIGEST_SIZE)) + $(eval $(call MAKE_LIB,mbedtls)) endif diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c index 4ae55fcc7..40cd4554f 100644 --- a/drivers/st/ddr/stm32mp1_ram.c +++ b/drivers/st/ddr/stm32mp1_ram.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -250,8 +250,9 @@ static int stm32mp1_ddr_setup(void) VERBOSE("%s : ram size(%x, %x)\n", __func__, (uint32_t)priv->info.base, (uint32_t)priv->info.size); - write_sctlr(read_sctlr() & ~SCTLR_C_BIT); - dcsw_op_all(DC_OP_CISW); + if (stm32mp_map_ddr_non_cacheable() != 0) { + panic(); + } uret = ddr_test_data_bus(); if (uret != 0U) { @@ -274,7 +275,9 @@ static int stm32mp1_ddr_setup(void) panic(); } - write_sctlr(read_sctlr() | SCTLR_C_BIT); + if (stm32mp_unmap_ddr() != 0) { + panic(); + } return 0; } diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c index b694fff6b..d2d7e06b7 100644 --- a/drivers/st/fmc/stm32_fmc2_nand.c +++ b/drivers/st/fmc/stm32_fmc2_nand.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -365,7 +365,7 @@ static int stm32_fmc2_ham_correct(uint8_t *buffer, uint8_t *eccbuffer, xor_ecc_2b = ecc[1] ^ eccbuffer[1]; xor_ecc_3b = ecc[2] ^ eccbuffer[2]; - xor_ecc.val = 0L; + xor_ecc.val = 0U; xor_ecc.bytes[2] = xor_ecc_3b; xor_ecc.bytes[1] = xor_ecc_2b; xor_ecc.bytes[0] = xor_ecc_1b; diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c index 413521b1e..3e377cd48 100644 --- a/drivers/st/io/io_stm32image.c +++ b/drivers/st/io/io_stm32image.c @@ -247,7 +247,7 @@ static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { int result; - uint8_t *local_buffer = (uint8_t *)buffer; + uint8_t *local_buffer; boot_api_image_header_t *header = (boot_api_image_header_t *)first_lba_buffer; @@ -255,6 +255,7 @@ static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer, assert(buffer != 0U); assert(length_read != NULL); + local_buffer = (uint8_t *)buffer; *length_read = 0U; while (*length_read == 0U) { diff --git a/drivers/st/spi/stm32_qspi.c b/drivers/st/spi/stm32_qspi.c index 188d2ff80..c5e4ea86e 100644 --- a/drivers/st/spi/stm32_qspi.c +++ b/drivers/st/spi/stm32_qspi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -12,6 +12,7 @@ #include <drivers/delay_timer.h> #include <drivers/spi_mem.h> #include <drivers/st/stm32_gpio.h> +#include <drivers/st/stm32_qspi.h> #include <drivers/st/stm32mp_reset.h> #include <lib/mmio.h> #include <lib/utils_def.h> @@ -172,9 +173,8 @@ static void stm32_qspi_write_fifo(uint8_t *val, uintptr_t addr) static int stm32_qspi_poll(const struct spi_mem_op *op) { void (*fifo)(uint8_t *val, uintptr_t addr); - uint32_t len = op->data.nbytes; + uint32_t len; uint8_t *buf; - uint64_t timeout; if (op->data.dir == SPI_MEM_DATA_IN) { fifo = stm32_qspi_read_fifo; @@ -185,7 +185,8 @@ static int stm32_qspi_poll(const struct spi_mem_op *op) buf = (uint8_t *)op->data.buf; for (len = op->data.nbytes; len != 0U; len--) { - timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US); + uint64_t timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US); + while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_FTF) == 0U) { if (timeout_elapsed(timeout)) { diff --git a/fdts/corstone700.dts b/fdts/corstone700.dts index c13d3b23e..851f5e625 100644 --- a/fdts/corstone700.dts +++ b/fdts/corstone700.dts @@ -15,8 +15,6 @@ chosen { bootargs = "console=ttyAMA0 \ - root=mtd:physmap-flash.0 \ - ro \ loglevel=9"; }; diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 7559de446..4fd746d5a 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -329,6 +329,11 @@ bl inv_dcache_range #endif + /* + * zeromem uses r12 whereas it is used to save previous BL arg3, + * save it in r7 + */ + mov r7, r12 ldr r0, =__BSS_START__ ldr r1, =__BSS_SIZE__ bl zeromem @@ -339,6 +344,9 @@ bl zeromem #endif + /* Restore r12 */ + mov r12, r7 + #if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) /* ----------------------------------------------------- * Copy data from ROM to RAM. diff --git a/include/bl32/payloads/tlk.h b/include/bl32/payloads/tlk.h index fe6f3528b..290f32923 100644 --- a/include/bl32/payloads/tlk.h +++ b/include/bl32/payloads/tlk.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,10 +24,12 @@ #define TLK_SS_REGISTER_HANDLER TLK_TOS_YIELD_FID(0x3) #define TLK_REGISTER_NS_DRAM_RANGES TLK_TOS_YIELD_FID(0x4) #define TLK_SET_ROOT_OF_TRUST TLK_TOS_YIELD_FID(0x5) +#define TLK_SET_BL_VERSION TLK_TOS_YIELD_FID(0x6) +#define TLK_LOCK_BL_INTERFACE TLK_TOS_YIELD_FID(0x7) +#define TLK_BL_RPMB_SERVICE TLK_TOS_YIELD_FID(0x8) #define TLK_RESUME_FID TLK_TOS_YIELD_FID(0x100) #define TLK_SYSTEM_SUSPEND TLK_TOS_YIELD_FID(0xE001) #define TLK_SYSTEM_RESUME TLK_TOS_YIELD_FID(0xE002) -#define TLK_SYSTEM_OFF TLK_TOS_YIELD_FID(0xE003) #define TLK_IRQ_FIRED TLK_TOS_YIELD_FID(0xE004) /* @@ -39,7 +42,6 @@ #define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31)) #define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31)) #define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31)) -#define TLK_SYSTEM_OFF_DONE (0x32000007 | (ULL(1) << 31)) #define TLK_IRQ_DONE (0x32000008 | (ULL(1) << 31)) /* diff --git a/include/drivers/raw_nand.h b/include/drivers/raw_nand.h index 18e4b73da..9018f0242 100644 --- a/include/drivers/raw_nand.h +++ b/include/drivers/raw_nand.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef DRIVERS_RAW_NAND_H #define DRIVERS_RAW_NAND_H +#include <cdefs.h> #include <stdint.h> #include <drivers/nand.h> diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index 02657a0fb..b98abdf4d 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -34,6 +34,11 @@ #define DENVER_CPU_PMSTATE_C7 U(0x7) #define DENVER_CPU_PMSTATE_MASK U(0xF) +/* ACTRL_ELx bits to enable dual execution*/ +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9) +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9) +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4) + #ifndef __ASSEMBLER__ /* Disable Dynamic Code Optimisation */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index e061950c8..0029658ac 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -183,7 +183,7 @@ #define CTX_SPSR_EL2 U(0xd0) #define CTX_SP_EL2 U(0xd8) #define CTX_TCR_EL2 U(0xe0) -#define CTX_TRFCR_EL2 U(0xe8) +#define CTX_TPIDR_EL2 U(0xe8) #define CTX_TTBR0_EL2 U(0xf0) #define CTX_VBAR_EL2 U(0xf8) #define CTX_VMPIDR_EL2 U(0x100) @@ -234,11 +234,13 @@ #define CTX_VSESR_EL2 U(0x228) #define CTX_VSTCR_EL2 U(0x230) #define CTX_VSTTBR_EL2 U(0x238) +#define CTX_TRFCR_EL2 U(0x240) // Starting with Armv8.5 -#define CTX_SCXTNUM_EL2 U(0x240) +#define CTX_SCXTNUM_EL2 U(0x248) /* Align to the next 16 byte boundary */ #define CTX_EL2_SYSREGS_END U(0x250) + #endif /* CTX_INCLUDE_EL2_REGS */ /******************************************************************************* diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index db38e556a..cfb27f7dc 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -173,7 +173,7 @@ typedef struct pmf_svc_desc { unsigned int tid, \ unsigned long long ts) \ { \ - CASSERT(_flags, select_proper_config); \ + CASSERT(_flags != 0, select_proper_config); \ PMF_VALIDATE_TID(_name, tid); \ uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ if (((_flags) & PMF_STORE_ENABLE) != 0) \ @@ -185,7 +185,7 @@ typedef struct pmf_svc_desc { unsigned int tid, \ unsigned long long ts) \ { \ - CASSERT(_flags, select_proper_config); \ + CASSERT(_flags != 0, select_proper_config); \ PMF_VALIDATE_TID(_name, tid); \ uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ if (((_flags) & PMF_STORE_ENABLE) != 0) \ diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h index 2dc94abe3..34bf07c0d 100644 --- a/include/plat/arm/common/arm_dyn_cfg_helpers.h +++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h @@ -14,4 +14,8 @@ int arm_dyn_tb_fw_cfg_init(void *dtb, int *node); int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size); +#if MEASURED_BOOT +int arm_set_bl2_hash_info(void *dtb, void *data); +#endif + #endif /* ARM_DYN_CFG_HELPERS_H */ diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index a84047aac..83d4c20ec 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -238,6 +238,11 @@ void arm_bl2_dyn_cfg_init(void); void arm_bl1_set_mbedtls_heap(void); int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); +#if MEASURED_BOOT +/* Measured boot related functions */ +void arm_bl1_set_bl2_hash(image_desc_t *image_desc); +#endif + /* * Free the memory storing initialization code only used during an images boot * time so it can be reclaimed for runtime data diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 30ad7b7d1..221f33e06 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -100,7 +100,7 @@ func el2_sysregs_context_save stp x10, x11, [x0, #CTX_SPSR_EL2] mrs x12, tcr_el2 - mrs x13, TRFCR_EL2 + mrs x13, tpidr_el2 stp x12, x13, [x0, #CTX_TCR_EL2] mrs x14, ttbr0_el2 @@ -204,11 +204,14 @@ func el2_sysregs_context_save mrs x16, vsttbr_el2 str x16, [x0, #CTX_VSTTBR_EL2] + + mrs x17, TRFCR_EL2 + str x17, [x0, #CTX_TRFCR_EL2] #endif #if ARM_ARCH_AT_LEAST(8, 5) - mrs x17, scxtnum_el2 - str x17, [x0, #CTX_SCXTNUM_EL2] + mrs x9, scxtnum_el2 + str x9, [x0, #CTX_SCXTNUM_EL2] #endif ret @@ -289,7 +292,7 @@ func el2_sysregs_context_restore ldp x12, x13, [x0, #CTX_TCR_EL2] msr tcr_el2, x12 - msr TRFCR_EL2, x13 + msr tpidr_el2, x13 ldp x14, x15, [x0, #CTX_TTBR0_EL2] msr ttbr0_el2, x14 @@ -391,11 +394,14 @@ func el2_sysregs_context_restore ldr x16, [x0, #CTX_VSTTBR_EL2] msr vsttbr_el2, x16 + + ldr x17, [x0, #CTX_TRFCR_EL2] + msr TRFCR_EL2, x17 #endif #if ARM_ARCH_AT_LEAST(8, 5) - ldr x17, [x0, #CTX_SCXTNUM_EL2] - msr scxtnum_el2, x17 + ldr x9, [x0, #CTX_SCXTNUM_EL2] + msr scxtnum_el2, x9 #endif ret diff --git a/lib/fconf/fconf.c b/lib/fconf/fconf.c index 9ce46354d..a5ec14300 100644 --- a/lib/fconf/fconf.c +++ b/lib/fconf/fconf.c @@ -33,7 +33,7 @@ void fconf_load_config(void) err = load_auth_image(TB_FW_CONFIG_ID, &arm_tb_fw_info); if (err != 0) { /* Return if FW_CONFIG is not loaded */ - VERBOSE("Failed to load FW_CONFIG\n"); + VERBOSE("FW_CONFIG not loaded, continuing without it\n"); return; } diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 03322db19..4e968e2d3 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -223,7 +223,7 @@ USE_COHERENT_MEM := 1 USE_DEBUGFS := 0 # Build option to fconf based io -USE_FCONF_BASED_IO := 0 +ARM_IO_IN_DTB := 0 # Build option to choose whether Trusted Firmware uses library at ROM USE_ROMLIB := 0 diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h index 0e204d0f0..702db770f 100644 --- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h +++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h @@ -29,9 +29,9 @@ #define SUNXI_SID_BASE 0x03006000 #define SUNXI_DMA_BASE 0x03002000 #define SUNXI_MSGBOX_BASE 0x03003000 -#define SUNXI_CCU_BASE 0x03010000 +#define SUNXI_CCU_BASE 0x03001000 #define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0xf00) -#define SUNXI_PIO_BASE 0x030b0000 +#define SUNXI_PIO_BASE 0x0300b000 #define SUNXI_TIMER_BASE 0x03009000 #define SUNXI_WDOG_BASE 0x030090a0 #define SUNXI_THS_BASE 0x05070400 diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk index 719884217..3a4d5e56d 100644 --- a/plat/arm/board/a5ds/platform.mk +++ b/plat/arm/board/a5ds/platform.mk @@ -41,6 +41,7 @@ BL1_SOURCES += drivers/io/io_fip.c \ plat/arm/common/arm_err.c \ plat/arm/board/a5ds/a5ds_err.c \ plat/arm/common/arm_io_storage.c \ + plat/arm/common/fconf/arm_fconf_io.c \ plat/arm/board/a5ds/${ARCH}/a5ds_helpers.S \ plat/arm/board/a5ds/a5ds_bl1_setup.c \ lib/aarch32/arm32_aeabi_divmod.c \ @@ -61,6 +62,7 @@ BL2_SOURCES += lib/aarch32/arm32_aeabi_divmod.c \ plat/arm/common/arm_err.c \ plat/arm/board/a5ds/a5ds_err.c \ plat/arm/common/arm_io_storage.c \ + plat/arm/common/fconf/arm_fconf_io.c \ plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \ plat/arm/common/arm_image_load.c \ common/desc_image_load.c \ diff --git a/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S b/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S new file mode 100644 index 000000000..f350455d5 --- /dev/null +++ b/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <platform_def.h> + + .globl plat_get_my_entrypoint + .globl plat_secondary_cold_boot_setup + .globl plat_is_my_cpu_primary + .globl platform_mem_init + .globl plat_my_core_pos + .globl plat_fpga_calc_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + +/* ----------------------------------------------------------------------- + * Indicate a cold boot for every CPU - warm boot is unsupported for the + * holding pen PSCI implementation. + * ----------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + mov x0, #0 + ret +endfunc plat_get_my_entrypoint + +/* ----------------------------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * ----------------------------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* + * Poll the CPU's hold entry until it indicates to jump + * to the entrypoint address. + */ + bl plat_my_core_pos + lsl x0, x0, #PLAT_FPGA_HOLD_ENTRY_SHIFT + ldr x1, =hold_base + ldr x2, =fpga_sec_entrypoint +poll_hold_entry: + ldr x3, [x1, x0] + cmp x3, #PLAT_FPGA_HOLD_STATE_GO + b.ne 1f + ldr x3, [x2] + br x3 +1: + wfe + b poll_hold_entry +endfunc plat_secondary_cold_boot_setup + +/* ----------------------------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary cpu + * ----------------------------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + mov_imm x1, MPIDR_AFFINITY_MASK + and x0, x0, x1 + cmp x0, #FPGA_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + +func platform_mem_init + ret +endfunc platform_mem_init + +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_fpga_calc_core_pos +endfunc plat_my_core_pos + +/* ----------------------------------------------------------------------- + * unsigned int plat_fpga_calc_core_pos(u_register_t mpidr) + * ----------------------------------------------------------------------- + */ +func plat_fpga_calc_core_pos + /* + * Check for MT bit in MPIDR, which may be either value for images + * running on the FPGA. + * + * If not set, shift MPIDR to left to make it look as if in a + * multi-threaded implementation. + */ + tst x0, #MPIDR_MT_MASK + lsl x3, x0, #MPIDR_AFFINITY_BITS + csel x3, x3, x0, eq + + /* Extract individual affinity fields from MPIDR */ + ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS + + /* Compute linear position */ + mov x4, #FPGA_MAX_CPUS_PER_CLUSTER + madd x1, x2, x4, x1 + mov x5, #FPGA_MAX_PE_PER_CPU + madd x0, x1, x5, x0 + ret +endfunc plat_fpga_calc_core_pos + +func plat_crash_console_init + mov_imm x0, PLAT_FPGA_CRASH_UART_BASE + mov_imm x1, PLAT_FPGA_CRASH_UART_CLK_IN_HZ + mov_imm x2, PLAT_FPGA_CONSOLE_BAUDRATE + b console_pl011_core_init +endfunc plat_crash_console_init + +func plat_crash_console_putc + mov_imm x1, PLAT_FPGA_CRASH_UART_BASE + b console_pl011_core_putc +endfunc plat_crash_console_putc + +func plat_crash_console_flush + mov_imm x0, PLAT_FPGA_CRASH_UART_BASE + b console_pl011_core_flush +endfunc plat_crash_console_flush diff --git a/plat/arm/board/arm_fpga/fpga_bl31_setup.c b/plat/arm/board/arm_fpga/fpga_bl31_setup.c new file mode 100644 index 000000000..d499379ee --- /dev/null +++ b/plat/arm/board/arm_fpga/fpga_bl31_setup.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <lib/mmio.h> +#include <drivers/generic_delay_timer.h> + +#include <plat/common/platform.h> +#include <platform_def.h> + +#include "fpga_private.h" + +static entry_point_info_t bl33_image_ep_info; + +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + return 0; +#endif +} + +uint32_t fpga_get_spsr_for_bl33_entry(void) +{ + return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +} + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + fpga_console_init(); + + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + + /* Set x0-x3 for the primary CPU as expected by the kernel */ + bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE; + bl33_image_ep_info.args.arg1 = 0U; + bl33_image_ep_info.args.arg2 = 0U; + bl33_image_ep_info.args.arg3 = 0U; +} + +void bl31_plat_arch_setup(void) +{ +} + +void bl31_platform_setup(void) +{ + /* Initialize the GIC driver, cpu and distributor interfaces */ + plat_fpga_gic_init(); + + /* Write frequency to CNTCRL and initialize timer */ + generic_delay_timer_init(); + mmio_write_32(FPGA_TIMER_BASE, ((1 << 8) | 1UL)); +} + +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + next_image_info = &bl33_image_ep_info; + + /* Only expecting BL33: the kernel will run in EL2NS */ + assert(type == NON_SECURE); + + /* None of the images can have 0x0 as the entrypoint */ + if (next_image_info->pc) { + return next_image_info; + } else { + return NULL; + } +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return FPGA_TIMER_FREQUENCY; +} + +void bl31_plat_enable_mmu(uint32_t flags) +{ + /* TODO: determine if MMU needs to be enabled */ +} diff --git a/plat/arm/board/arm_fpga/fpga_console.c b/plat/arm/board/arm_fpga/fpga_console.c new file mode 100644 index 000000000..b4ebf3424 --- /dev/null +++ b/plat/arm/board/arm_fpga/fpga_console.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <drivers/console.h> +#include <drivers/arm/pl011.h> + +#include <platform_def.h> + +static console_t console; + +void fpga_console_init(void) +{ + (void)console_pl011_register(PLAT_FPGA_BOOT_UART_BASE, + PLAT_FPGA_BOOT_UART_CLK_IN_HZ, + PLAT_FPGA_CONSOLE_BAUDRATE, + &console); + + console_set_scope(&console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME); +} diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h new file mode 100644 index 000000000..56ee1663d --- /dev/null +++ b/plat/arm/board/arm_fpga/fpga_def.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/utils_def.h> + +#ifndef FPGA_DEF_H +#define FPGA_DEF_H + +/* + * These are set to large values to account for images describing systems with + * larger cluster configurations. + * + * For cases where the number of clusters, cores or threads is smaller than a + * maximum value below, this does not affect the PSCI functionality as any PEs + * that are present will still be indexed appropriately regardless of any empty + * entries in the array used to represent the topology. + */ +#define FPGA_MAX_CLUSTER_COUNT 2 +#define FPGA_MAX_CPUS_PER_CLUSTER 8 +#define FPGA_MAX_PE_PER_CPU 4 + +#define FPGA_PRIMARY_CPU 0x0 + +/******************************************************************************* + * FPGA image memory map related constants + ******************************************************************************/ + +/* UART base address and clock frequency, as configured by the image */ +#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000 +#define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000 + +#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE +#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ + +#define FPGA_TIMER_FREQUENCY 10000000 +#define FPGA_TIMER_BASE 0x2a830000 + +#endif diff --git a/plat/arm/board/arm_fpga/fpga_gicv3.c b/plat/arm/board/arm_fpga/fpga_gicv3.c new file mode 100644 index 000000000..be1684e4b --- /dev/null +++ b/plat/arm/board/arm_fpga/fpga_gicv3.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <drivers/arm/gicv3.h> +#include <drivers/arm/gic_common.h> + +#include <plat/common/platform.h> +#include <platform_def.h> + +static const interrupt_prop_t fpga_interrupt_props[] = { + PLATFORM_G1S_PROPS(INTR_GROUP1S), + PLATFORM_G0_PROPS(INTR_GROUP0) +}; + +static uintptr_t fpga_rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr) +{ + return (unsigned int)plat_core_pos_by_mpidr(mpidr); +} + +static const gicv3_driver_data_t fpga_gicv3_driver_data = { + .gicd_base = GICD_BASE, + .gicr_base = GICR_BASE, + .interrupt_props = fpga_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props), + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = fpga_rdistif_base_addrs, + .mpidr_to_core_pos = fpga_mpidr_to_core_pos +}; + +void plat_fpga_gic_init(void) +{ + gicv3_driver_init(&fpga_gicv3_driver_data); + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +void fpga_pwr_gic_on_finish(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +void fpga_pwr_gic_off(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); + gicv3_rdistif_off(plat_my_core_pos()); +} diff --git a/plat/arm/board/arm_fpga/fpga_pm.c b/plat/arm/board/arm_fpga/fpga_pm.c new file mode 100644 index 000000000..4c372179f --- /dev/null +++ b/plat/arm/board/arm_fpga/fpga_pm.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <lib/psci/psci.h> +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> + +#include "fpga_private.h" +#include <platform_def.h> + +/* + * This is a basic PSCI implementation that allows secondary CPUs to be + * released from their initial state and continue to the warm boot entrypoint. + * + * The secondary CPUs are placed in a holding pen and released by calls + * to fpga_pwr_domain_on(mpidr), which updates the hold entry for the CPU + * specified by the mpidr argument - the (polling) target CPU will then branch + * to the BL31 warm boot sequence at the entrypoint address. + * + * Additionally, the secondary CPUs are kept in a low-power wfe() state + * (placed there at the end of each poll) and woken when necessary through + * calls to sev() in fpga_pwr_domain_on(mpidr), once the hold state for the + * relevant CPU has been updated. + * + * Hotplug is currently implemented using a wfi-loop, which removes the + * dependencies on any power controllers or other mechanism that is specific + * to the running system as specified by the FPGA image. + */ + +uint64_t hold_base[PLATFORM_CORE_COUNT]; +uintptr_t fpga_sec_entrypoint; + +/* + * Calls to the CPU specified by the mpidr will set its hold entry to a value + * indicating that it should stop polling and branch off to the warm entrypoint. + */ +static int fpga_pwr_domain_on(u_register_t mpidr) +{ + unsigned int pos = plat_core_pos_by_mpidr(mpidr); + unsigned long current_mpidr = read_mpidr_el1(); + + if (mpidr == current_mpidr) { + return PSCI_E_ALREADY_ON; + } + hold_base[pos] = PLAT_FPGA_HOLD_STATE_GO; + flush_dcache_range((uintptr_t)&hold_base[pos], sizeof(uint64_t)); + sev(); /* Wake any CPUs from wfe */ + + return PSCI_E_SUCCESS; +} + +void fpga_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + fpga_pwr_gic_on_finish(); +} + +static void fpga_pwr_domain_off(const psci_power_state_t *target_state) +{ + fpga_pwr_gic_off(); + + while (1) { + wfi(); + } +} + +static void fpga_cpu_standby(plat_local_state_t cpu_state) +{ + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + u_register_t scr = read_scr_el3(); + write_scr_el3(scr|SCR_IRQ_BIT); + dsb(); + wfi(); + write_scr_el3(scr); +} + +plat_psci_ops_t plat_fpga_psci_pm_ops = { + .pwr_domain_on = fpga_pwr_domain_on, + .pwr_domain_on_finish = fpga_pwr_domain_on_finish, + .pwr_domain_off = fpga_pwr_domain_off, + .cpu_standby = fpga_cpu_standby +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + fpga_sec_entrypoint = sec_entrypoint; + flush_dcache_range((uint64_t)&fpga_sec_entrypoint, + sizeof(fpga_sec_entrypoint)); + *psci_ops = &plat_fpga_psci_pm_ops; + return 0; +} diff --git a/plat/arm/board/arm_fpga/fpga_private.h b/plat/arm/board/arm_fpga/fpga_private.h new file mode 100644 index 000000000..7545bd17e --- /dev/null +++ b/plat/arm/board/arm_fpga/fpga_private.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FPGA_PRIVATE_H +#define FPGA_PRIVATE_H + +unsigned int plat_fpga_calc_core_pos(u_register_t mpidr); + +void fpga_console_init(void); + +void plat_fpga_gic_init(void); +void fpga_pwr_gic_on_finish(void); +void fpga_pwr_gic_off(void); + +#endif diff --git a/plat/arm/board/arm_fpga/fpga_topology.c b/plat/arm/board/arm_fpga/fpga_topology.c new file mode 100644 index 000000000..a705429ac --- /dev/null +++ b/plat/arm/board/arm_fpga/fpga_topology.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> + +#include "fpga_private.h" +#include <platform_def.h> + +static unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2]; + +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + int i; + /* + * The highest level is the system level. The next level is constituted + * by clusters and then cores in clusters. + * + * This description of the power domain topology is aligned with the CPU + * indices returned by the plat_core_pos_by_mpidr() and plat_my_core_pos() + * APIs. + */ + fpga_power_domain_tree_desc[0] = 1; + fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT; + + for (i = 0; i < FPGA_MAX_CLUSTER_COUNT; i++) { + fpga_power_domain_tree_desc[i + 2] = FPGA_MAX_CPUS_PER_CLUSTER; + } + + return fpga_power_domain_tree_desc; +} + +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id, thread_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { + return -1; + } + + if (mpidr & MPIDR_MT_MASK) { + thread_id = MPIDR_AFFLVL0_VAL(mpidr); + } else { + thread_id = 0; + } + + cpu_id = MPIDR_AFFLVL1_VAL(mpidr); + cluster_id = MPIDR_AFFLVL2_VAL(mpidr); + + if (cluster_id >= FPGA_MAX_CLUSTER_COUNT) { + return -1; + } else if (cpu_id >= FPGA_MAX_CPUS_PER_CLUSTER) { + return -1; + } else if (thread_id >= FPGA_MAX_PE_PER_CPU) { + return -1; + } + + /* + * The image running on the FPGA may or may not implement multithreading, + * and it shouldn't be assumed this is consistent across all CPUs. + * This ensures that any passed mpidr values reflect the status of the + * primary CPU's MT bit. + */ + mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); + + /* Calculate the correct core, catering for multi-threaded images */ + return (int) plat_fpga_calc_core_pos(mpidr); +} diff --git a/plat/arm/board/arm_fpga/include/plat_macros.S b/plat/arm/board/arm_fpga/include/plat_macros.S new file mode 100644 index 000000000..44cddeb36 --- /dev/null +++ b/plat/arm/board/arm_fpga/include/plat_macros.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +.macro plat_crash_print_regs +.endm + +#endif diff --git a/plat/arm/board/arm_fpga/include/platform_def.h b/plat/arm/board/arm_fpga/include/platform_def.h new file mode 100644 index 000000000..5c8aff691 --- /dev/null +++ b/plat/arm/board/arm_fpga/include/platform_def.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <plat/common/common_def.h> +#include <platform_def.h> +#include "../fpga_def.h" + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" + +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE UL(0x800) + +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +#define PLATFORM_CORE_COUNT \ + (FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU) + +#define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + 1 + +#if !ENABLE_PIE +#define BL31_BASE UL(0x80000000) +#define BL31_LIMIT UL(0x80100000) +#else +#define BL31_BASE UL(0x0) +#define BL31_LIMIT UL(0x01000000) +#endif + +#define GICD_BASE 0x30000000 +#define GICR_BASE 0x30040000 + +#define PLAT_SDEI_NORMAL_PRI 0x70 + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLATFORM_G1S_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +#define PLATFORM_G0_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 + +#define PLAT_FPGA_HOLD_ENTRY_SHIFT 3 +#define PLAT_FPGA_HOLD_STATE_WAIT 0 +#define PLAT_FPGA_HOLD_STATE_GO 1 + +#define PLAT_FPGA_CONSOLE_BAUDRATE 38400 + +#endif diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk new file mode 100644 index 000000000..b4f38fab4 --- /dev/null +++ b/plat/arm/board/arm_fpga/platform.mk @@ -0,0 +1,93 @@ +# +# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +RESET_TO_BL31 := 1 +ifeq (${RESET_TO_BL31}, 0) +$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") +endif + +ifeq (${ENABLE_PIE}, 1) +override SEPARATE_CODE_AND_RODATA := 1 +endif + +CTX_INCLUDE_AARCH32_REGS := 0 +ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) +$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") +endif + +ifeq (${TRUSTED_BOARD_BOOT}, 1) +$(error "TRUSTED_BOARD_BOOT must be disabled") +endif + +ifndef PRELOADED_BL33_BASE +$(error "PRELOADED_BL33_BASE is not set") +endif + +ifndef FPGA_PRELOADED_DTB_BASE +$(error "FPGA_PRELOADED_DTB_BASE is not set") +else +$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) +endif + +# Treating this as a memory-constrained port for now +USE_COHERENT_MEM := 0 + +# This can be overridden depending on CPU(s) used in the FPGA image +HW_ASSISTED_COHERENCY := 1 + +FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S + +# select a different set of CPU files, depending on whether we compile for +# hardware assisted coherency cores or not +ifeq (${HW_ASSISTED_COHERENCY}, 0) +# Cores used without DSU + FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + lib/cpus/aarch64/cortex_a73.S +else +# AArch64-only cores + FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ + lib/cpus/aarch64/cortex_a76ae.S \ + lib/cpus/aarch64/cortex_a77.S \ + lib/cpus/aarch64/neoverse_n1.S \ + lib/cpus/aarch64/neoverse_e1.S \ + lib/cpus/aarch64/neoverse_zeus.S \ + lib/cpus/aarch64/cortex_hercules.S \ + lib/cpus/aarch64/cortex_hercules_ae.S \ + lib/cpus/aarch64/cortex_a65.S \ + lib/cpus/aarch64/cortex_a65ae.S +# AArch64/AArch32 cores + FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a75.S +endif + +FPGA_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ + drivers/arm/gic/v3/gicdv3_helpers.c \ + drivers/arm/gic/v3/gicrv3_helpers.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/v3/gic600.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv3.c \ + plat/arm/board/arm_fpga/fpga_gicv3.c + +PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include + +PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S + +BL31_SOURCES += drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/arm/pl011/${ARCH}/pl011_console.S \ + plat/common/plat_psci_common.c \ + plat/arm/board/arm_fpga/fpga_pm.c \ + plat/arm/board/arm_fpga/fpga_topology.c \ + plat/arm/board/arm_fpga/fpga_console.c \ + plat/arm/board/arm_fpga/fpga_bl31_setup.c \ + ${FPGA_CPU_LIBS} \ + ${FPGA_GIC_SOURCES} + +all: bl31 diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts index 9a4a05799..98ea85760 100644 --- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts +++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts @@ -39,7 +39,7 @@ tos_fw-config { load-address = <0x0 0x04001200>; - max-size = <0x200>; + max-size = <0x1000>; id = <TOS_FW_CONFIG_ID>; }; @@ -67,6 +67,19 @@ */ mbedtls_heap_addr = <0x0 0x0>; mbedtls_heap_size = <0x0>; + +#if MEASURED_BOOT + /* BL2 image hash calculated by BL1 */ + bl2_hash_data = [ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +#if BL2_HASH_SIZE > 32 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +#if BL2_HASH_SIZE > 48 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +#endif /* > 48 */ +#endif /* > 32 */ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00]; +#endif /* MEASURED_BOOT */ }; /* @@ -75,6 +88,7 @@ * stored in machine order (little endian). * This will be fixed in future. */ +#if ARM_IO_IN_DTB arm-io_policies { fip-handles { compatible = "arm,io-fip-handle"; @@ -99,15 +113,16 @@ nt_fw_content_cert_uuid = <0xf3c1c48e 0x11e4635d 0xee87a9a7 0xa73fb240>; }; }; +#endif /* ARM_IO_IN_DTB */ secure-partitions { compatible = "arm,sp"; - cactus { + cactus-primary { uuid = <0x1e67b5b4 0xe14f904a 0x13fb1fb8 0xcbdae1da>; load-address = <0x7000000>; }; - ivy { + cactus-secondary { uuid = <0x092358d1 0xb94723f0 0x64447c82 0xc88f57f5>; load-address = <0x7100000>; }; diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts index db3fb5510..79c4c07f6 100644 --- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts +++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts @@ -6,7 +6,7 @@ /dts-v1/; / { - compatible = "spci-core-manifest-1.0"; + compatible = "arm,spci-core-manifest-1.0"; attribute { spmc_id = <0x8000>; @@ -16,4 +16,52 @@ load_address = <0x0 0x6000000>; entrypoint = <0x0 0x6000000>; }; + + chosen { + linux,initrd-start = <0>; + linux,initrd-end = <0>; + }; + + hypervisor { + compatible = "hafnium,hafnium"; + vm1 { + is_spci_partition; + debug_name = "cactus-primary"; + load-addr = <0x7000000>; + }; + vm2 { + is_spci_partition; + debug_name = "cactus-secondary"; + load-addr = <0x7100000>; + vcpu_count = <2>; + mem_size = <1048576>; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x2>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <0xc>; + phandle = <0x2>; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x6000000 0x2000000>; /* Trusted DRAM */ + }; }; diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c index 8f6170daa..d13cc81f3 100644 --- a/plat/arm/board/fvp/fvp_bl1_setup.c +++ b/plat/arm/board/fvp/fvp_bl1_setup.c @@ -1,9 +1,12 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> + +#include <bl1/bl1.h> #include <common/tbbr/tbbr_img_def.h> #include <drivers/arm/smmu_v3.h> #include <drivers/arm/sp805.h> @@ -64,3 +67,52 @@ __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved) while (1) wfi(); } + +#if MEASURED_BOOT +/* + * Implementation for bl1_plat_handle_post_image_load(). This function + * populates the default arguments to BL2. The BL2 memory layout structure + * is allocated and the calculated layout is populated in arg1 to BL2. + */ +int bl1_plat_handle_post_image_load(unsigned int image_id) +{ + meminfo_t *bl2_tzram_layout; + meminfo_t *bl1_tzram_layout; + image_desc_t *image_desc; + entry_point_info_t *ep_info; + + if (image_id != BL2_IMAGE_ID) { + return 0; + } + + /* Get the image descriptor */ + image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); + assert(image_desc != NULL); + + /* Calculate BL2 hash and set it in TB_FW_CONFIG */ + arm_bl1_set_bl2_hash(image_desc); + + /* Get the entry point info */ + ep_info = &image_desc->ep_info; + + /* Find out how much free trusted ram remains after BL1 load */ + bl1_tzram_layout = bl1_plat_sec_mem_layout(); + + /* + * Create a new layout of memory for BL2 as seen by BL1 i.e. + * tell it the amount of total and free memory available. + * This layout is created at the first free address visible + * to BL2. BL2 will read the memory layout before using its + * memory for other purposes. + */ + bl2_tzram_layout = (meminfo_t *)bl1_tzram_layout->total_base; + + bl1_calc_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); + + ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout; + + VERBOSE("BL1: BL2 memory layout address = %p\n", + (void *)bl2_tzram_layout); + return 0; +} +#endif /* MEASURED_BOOT */ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 4e20632c9..e64c4d4cf 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -10,11 +10,6 @@ FVP_USE_GIC_DRIVER := FVP_GICV3 # Use the SP804 timer instead of the generic one FVP_USE_SP804_TIMER := 0 -# Use fconf based io for FVP -ifeq ($(BL2_AT_EL3), 0) -USE_FCONF_BASED_IO := 1 -endif - # Default cluster count for FVP FVP_CLUSTER_COUNT := 2 diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk index 7883719b0..9ada86bf1 100644 --- a/plat/arm/board/fvp_ve/platform.mk +++ b/plat/arm/board/fvp_ve/platform.mk @@ -42,6 +42,7 @@ BL1_SOURCES += drivers/arm/sp805/sp805.c \ plat/arm/common/arm_err.c \ plat/arm/board/fvp_ve/fvp_ve_err.c \ plat/arm/common/arm_io_storage.c \ + plat/arm/common/fconf/arm_fconf_io.c \ drivers/cfi/v2m/v2m_flash.c \ plat/arm/board/fvp_ve/${ARCH}/fvp_ve_helpers.S \ plat/arm/board/fvp_ve/fvp_ve_bl1_setup.c \ @@ -63,6 +64,7 @@ BL2_SOURCES += plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c \ plat/arm/common/arm_err.c \ plat/arm/board/fvp_ve/fvp_ve_err.c \ plat/arm/common/arm_io_storage.c \ + plat/arm/common/fconf/arm_fconf_io.c \ plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \ plat/arm/common/arm_image_load.c \ common/desc_image_load.c \ diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index d9fc84e8c..6c3f64fb6 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -205,7 +205,7 @@ int arm_bl2_handle_post_image_load(unsigned int image_id) ******************************************************************************/ int arm_bl2_plat_handle_post_image_load(unsigned int image_id) { -#if defined(SPD_spmd) +#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 /* For Secure Partitions we don't need post processing */ if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && (image_id < MAX_NUMBER_IDS)) { diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 65f6bf3c3..3b0c39d4b 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -177,14 +177,12 @@ include lib/xlat_tables_v2/xlat_tables.mk PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} endif -ifeq (${USE_FCONF_BASED_IO}, 0) -ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c -else -ARM_IO_SOURCES += plat/arm/common/arm_fconf_io_storage.c \ +ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c \ plat/arm/common/fconf/arm_fconf_io.c ifeq (${SPD},spmd) -ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c -endif + ifeq (${SPMD_SPM_AT_SEL2},1) + ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c + endif endif BL1_SOURCES += drivers/io/io_fip.c \ diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c index df7530733..ffa2a64d8 100644 --- a/plat/arm/common/arm_dyn_cfg.c +++ b/plat/arm/common/arm_dyn_cfg.c @@ -15,6 +15,10 @@ #include <common/tbbr/tbbr_img_def.h> #if TRUSTED_BOARD_BOOT #include <drivers/auth/mbedtls/mbedtls_config.h> +#if MEASURED_BOOT +#include <drivers/auth/crypto_mod.h> +#include <mbedtls/md.h> +#endif #endif #include <lib/fconf/fconf.h> #include <lib/fconf/fconf_dyn_cfg_getter.h> @@ -87,7 +91,7 @@ void arm_bl1_set_mbedtls_heap(void) * the default heap's address and size. */ - /* fconf FW_CONFIG and TB_FW_CONFIG are currently the same DTB*/ + /* fconf FW_CONFIG and TB_FW_CONFIG are currently the same DTB */ tb_fw_cfg_dtb = FCONF_GET_PROPERTY(fconf, dtb, base_addr); if ((tb_fw_cfg_dtb != 0UL) && (mbedtls_heap_addr != NULL)) { @@ -100,15 +104,68 @@ void arm_bl1_set_mbedtls_heap(void) ERROR("BL1: unable to write shared Mbed TLS heap information to DTB\n"); panic(); } +#if !MEASURED_BOOT /* * Ensure that the info written to the DTB is visible to other * images. It's critical because BL2 won't be able to proceed * without the heap info. + * + * In MEASURED_BOOT case flushing is done in + * arm_bl1_set_bl2_hash() function which is called after heap + * information is written in the DTB. */ flush_dcache_range(tb_fw_cfg_dtb, fdt_totalsize(dtb)); +#endif /* !MEASURED_BOOT */ } } +#if MEASURED_BOOT +/* + * Puts the BL2 hash data to TB_FW_CONFIG DTB. + * Executed only from BL1. + */ +void arm_bl1_set_bl2_hash(image_desc_t *image_desc) +{ + unsigned char hash_data[MBEDTLS_MD_MAX_SIZE]; + image_info_t image_info = image_desc->image_info; + uintptr_t tb_fw_cfg_dtb; + int err; + + /* fconf FW_CONFIG and TB_FW_CONFIG are currently the same DTB */ + tb_fw_cfg_dtb = FCONF_GET_PROPERTY(fconf, dtb, base_addr); + + /* + * If tb_fw_cfg_dtb==NULL then DTB is not present for the current + * platform. As such, we cannot write to the DTB at all and pass + * measured data. + */ + if (tb_fw_cfg_dtb == 0UL) { + panic(); + } + + /* Calculate hash */ + err = crypto_mod_calc_hash(MBEDTLS_MD_ID, + (void *)image_info.image_base, + image_info.image_size, hash_data); + if (err != 0) { + ERROR("BL1: unable to calculate BL2 hash\n"); + panic(); + } + + err = arm_set_bl2_hash_info((void *)tb_fw_cfg_dtb, hash_data); + if (err < 0) { + ERROR("BL1: unable to write BL2 hash data to DTB\n"); + panic(); + } + + /* + * Ensure that the info written to the DTB is visible to other + * images. It's critical because BL2 won't be able to proceed + * without the heap info and its hash data. + */ + flush_dcache_range(tb_fw_cfg_dtb, fdt_totalsize((void *)tb_fw_cfg_dtb)); +} +#endif /* MEASURED_BOOT */ #endif /* TRUSTED_BOARD_BOOT */ /* diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c index 909c4a671..f110e3bb6 100644 --- a/plat/arm/common/arm_dyn_cfg_helpers.c +++ b/plat/arm/common/arm_dyn_cfg_helpers.c @@ -15,6 +15,12 @@ #define DTB_PROP_MBEDTLS_HEAP_ADDR "mbedtls_heap_addr" #define DTB_PROP_MBEDTLS_HEAP_SIZE "mbedtls_heap_size" +#if MEASURED_BOOT +#define DTB_PROP_BL2_HASH_DATA "bl2_hash_data" + +static int dtb_root = -1; +#endif /* MEASURED_BOOT */ + /******************************************************************************* * Validate the tb_fw_config is a valid DTB file and returns the node offset * to "arm,tb_fw" property. @@ -57,17 +63,18 @@ int arm_dyn_tb_fw_cfg_init(void *dtb, int *node) * * Returns: * 0 = success - * 1 = error + * -1 = error */ int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size) { - int err, dtb_root; - +#if !MEASURED_BOOT + int dtb_root; +#endif /* * Verify that the DTB is valid, before attempting to write to it, * and get the DTB root node. */ - err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root); + int err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root); if (err < 0) { ERROR("Invalid TB_FW_CONFIG loaded. Unable to get root node\n"); return -1; @@ -98,3 +105,26 @@ int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size) return 0; } + +#if MEASURED_BOOT +/* + * This function writes the BL2 hash data in HW_FW_CONFIG DTB. + * When it is called, it is guaranteed that a DTB is available. + * + * This function is supposed to be called only by BL1. + * + * Returns: + * 0 = success + * < 0 = error + */ +int arm_set_bl2_hash_info(void *dtb, void *data) +{ + assert(dtb_root >= 0); + + /* + * Write the BL2 hash data in the DTB. + */ + return fdtw_write_inplace_bytes(dtb, dtb_root, DTB_PROP_BL2_HASH_DATA, + TCG_DIGEST_SIZE, data); +} +#endif /* MEASURED_BOOT */ diff --git a/plat/arm/common/arm_fconf_io_storage.c b/plat/arm/common/arm_fconf_io_storage.c deleted file mode 100644 index 6fcfbd6fb..000000000 --- a/plat/arm/common/arm_fconf_io_storage.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2015-2020, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> - -#include <common/debug.h> -#include <drivers/io/io_driver.h> -#include <drivers/io/io_fip.h> -#include <drivers/io/io_memmap.h> -#include <drivers/io/io_storage.h> -#include <lib/utils.h> - -#include <plat/arm/common/arm_fconf_getter.h> -#include <plat/arm/common/arm_fconf_io_storage.h> -#include <plat/arm/common/plat_arm.h> -#include <plat/common/platform.h> -#include <platform_def.h> - -/* IO devices */ -static const io_dev_connector_t *fip_dev_con; -uintptr_t fip_dev_handle; -static const io_dev_connector_t *memmap_dev_con; -uintptr_t memmap_dev_handle; - -/* Weak definitions may be overridden in specific ARM standard platform */ -#pragma weak plat_arm_io_setup -#pragma weak plat_arm_get_alt_image_source - -int open_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - /* See if a Firmware Image Package is available */ - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using FIP\n"); - io_close(local_image_handle); - } - } - return result; -} - -int open_memmap(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(memmap_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using Memmap\n"); - io_close(local_image_handle); - } - } - return result; -} - -int arm_io_setup(void) -{ - int io_result; - - io_result = register_io_dev_fip(&fip_dev_con); - if (io_result < 0) { - return io_result; - } - - io_result = register_io_dev_memmap(&memmap_dev_con); - if (io_result < 0) { - return io_result; - } - - /* Open connections to devices and cache the handles */ - io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, - &fip_dev_handle); - if (io_result < 0) { - return io_result; - } - - io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, - &memmap_dev_handle); - - return io_result; -} - -void plat_arm_io_setup(void) -{ - int err; - - err = arm_io_setup(); - if (err < 0) { - panic(); - } -} - -int plat_arm_get_alt_image_source( - unsigned int image_id __unused, - uintptr_t *dev_handle __unused, - uintptr_t *image_spec __unused) -{ - /* By default do not try an alternative */ - return -ENOENT; -} - -/* Return an IO device handle and specification which can be used to access - * an image. Use this to enforce platform load policy */ -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < MAX_NUMBER_IDS); - - policy = FCONF_GET_PROPERTY(arm, io_policies, image_id); - result = policy->check(policy->image_spec); - if (result == 0) { - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - } else { - VERBOSE("Trying alternative IO\n"); - result = plat_arm_get_alt_image_source(image_id, dev_handle, - image_spec); - } - - return result; -} - -/* - * See if a Firmware Image Package is available, - * by checking if TOC is valid or not. - */ -bool arm_io_is_toc_valid(void) -{ - return (io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID) == 0); -} diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c index 593199d46..ed7f1f5a5 100644 --- a/plat/arm/common/arm_image_load.c +++ b/plat/arm/common/arm_image_load.c @@ -32,11 +32,11 @@ void plat_flush_next_bl_params(void) next_bl_params_cpy_ptr); } -#if defined(SPD_spmd) +#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 /******************************************************************************* * This function appends Secure Partitions to list of loadable images. ******************************************************************************/ -void plat_add_sp_images_load_info(struct bl_load_info *load_info) +static void plat_add_sp_images_load_info(struct bl_load_info *load_info) { bl_load_info_node_t *node_info = load_info->head; unsigned int index = 0; @@ -78,7 +78,7 @@ void plat_add_sp_images_load_info(struct bl_load_info *load_info) ******************************************************************************/ struct bl_load_info *plat_get_bl_image_load_info(void) { -#if defined(SPD_spmd) +#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 bl_load_info_t *bl_load_info; bl_load_info = get_bl_load_info_from_mem_params_desc(); diff --git a/plat/arm/common/arm_io_storage.c b/plat/arm/common/arm_io_storage.c index f5d8a414d..6fcfbd6fb 100644 --- a/plat/arm/common/arm_io_storage.c +++ b/plat/arm/common/arm_io_storage.c @@ -1,13 +1,10 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> -#include <string.h> - -#include <platform_def.h> #include <common/debug.h> #include <drivers/io/io_driver.h> @@ -15,249 +12,24 @@ #include <drivers/io/io_memmap.h> #include <drivers/io/io_storage.h> #include <lib/utils.h> + +#include <plat/arm/common/arm_fconf_getter.h> +#include <plat/arm/common/arm_fconf_io_storage.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> -#include <tools_share/firmware_image_package.h> +#include <platform_def.h> /* IO devices */ static const io_dev_connector_t *fip_dev_con; -static uintptr_t fip_dev_handle; +uintptr_t fip_dev_handle; static const io_dev_connector_t *memmap_dev_con; -static uintptr_t memmap_dev_handle; - -static const io_block_spec_t fip_block_spec = { - .offset = PLAT_ARM_FIP_BASE, - .length = PLAT_ARM_FIP_MAX_SIZE -}; - -static const io_uuid_spec_t bl2_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, -}; - -static const io_uuid_spec_t scp_bl2_uuid_spec = { - .uuid = UUID_SCP_FIRMWARE_SCP_BL2, -}; - -static const io_uuid_spec_t bl31_uuid_spec = { - .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, -}; - -static const io_uuid_spec_t bl32_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32, -}; - -static const io_uuid_spec_t bl32_extra1_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, -}; - -static const io_uuid_spec_t bl32_extra2_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -static const io_uuid_spec_t tb_fw_config_uuid_spec = { - .uuid = UUID_TB_FW_CONFIG, -}; - -static const io_uuid_spec_t hw_config_uuid_spec = { - .uuid = UUID_HW_CONFIG, -}; - -static const io_uuid_spec_t soc_fw_config_uuid_spec = { - .uuid = UUID_SOC_FW_CONFIG, -}; - -static const io_uuid_spec_t tos_fw_config_uuid_spec = { - .uuid = UUID_TOS_FW_CONFIG, -}; - -static const io_uuid_spec_t nt_fw_config_uuid_spec = { - .uuid = UUID_NT_FW_CONFIG, -}; - -#if TRUSTED_BOARD_BOOT -static const io_uuid_spec_t tb_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FW_CERT, -}; - -static const io_uuid_spec_t trusted_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_KEY_CERT, -}; - -static const io_uuid_spec_t scp_fw_key_cert_uuid_spec = { - .uuid = UUID_SCP_FW_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { - .uuid = UUID_SOC_FW_KEY_CERT, -}; - -static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, -}; - -static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, -}; - -static const io_uuid_spec_t scp_fw_cert_uuid_spec = { - .uuid = UUID_SCP_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t soc_fw_cert_uuid_spec = { - .uuid = UUID_SOC_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t tos_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t nt_fw_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, -}; -#endif /* TRUSTED_BOARD_BOOT */ - - -static int open_fip(const uintptr_t spec); -static int open_memmap(const uintptr_t spec); - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -/* By default, ARM platforms load images from the FIP */ -static const struct plat_io_policy policies[] = { - [FIP_IMAGE_ID] = { - &memmap_dev_handle, - (uintptr_t)&fip_block_spec, - open_memmap - }, - [BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl2_uuid_spec, - open_fip - }, - [SCP_BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&scp_bl2_uuid_spec, - open_fip - }, - [BL31_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl31_uuid_spec, - open_fip - }, - [BL32_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_uuid_spec, - open_fip - }, - [BL32_EXTRA1_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra1_uuid_spec, - open_fip - }, - [BL32_EXTRA2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra2_uuid_spec, - open_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl33_uuid_spec, - open_fip - }, - [TB_FW_CONFIG_ID] = { - &fip_dev_handle, - (uintptr_t)&tb_fw_config_uuid_spec, - open_fip - }, - [HW_CONFIG_ID] = { - &fip_dev_handle, - (uintptr_t)&hw_config_uuid_spec, - open_fip - }, - [SOC_FW_CONFIG_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_config_uuid_spec, - open_fip - }, - [TOS_FW_CONFIG_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_config_uuid_spec, - open_fip - }, - [NT_FW_CONFIG_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_config_uuid_spec, - open_fip - }, -#if TRUSTED_BOARD_BOOT - [TRUSTED_BOOT_FW_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tb_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&trusted_key_cert_uuid_spec, - open_fip - }, - [SCP_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&scp_fw_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_key_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_key_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_key_cert_uuid_spec, - open_fip - }, - [SCP_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&scp_fw_cert_uuid_spec, - open_fip - }, - [SOC_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_cert_uuid_spec, - open_fip - }, -#endif /* TRUSTED_BOARD_BOOT */ -}; - +uintptr_t memmap_dev_handle; /* Weak definitions may be overridden in specific ARM standard platform */ #pragma weak plat_arm_io_setup #pragma weak plat_arm_get_alt_image_source - -static int open_fip(const uintptr_t spec) +int open_fip(const uintptr_t spec) { int result; uintptr_t local_image_handle; @@ -274,8 +46,7 @@ static int open_fip(const uintptr_t spec) return result; } - -static int open_memmap(const uintptr_t spec) +int open_memmap(const uintptr_t spec) { int result; uintptr_t local_image_handle; @@ -291,7 +62,6 @@ static int open_memmap(const uintptr_t spec) return result; } - int arm_io_setup(void) { int io_result; @@ -346,9 +116,9 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, int result; const struct plat_io_policy *policy; - assert(image_id < ARRAY_SIZE(policies)); + assert(image_id < MAX_NUMBER_IDS); - policy = &policies[image_id]; + policy = FCONF_GET_PROPERTY(arm, io_policies, image_id); result = policy->check(policy->image_spec); if (result == 0) { *image_spec = policy->image_spec; @@ -370,4 +140,3 @@ bool arm_io_is_toc_valid(void) { return (io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID) == 0); } - diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c index 017af79a5..6ebc467ed 100644 --- a/plat/arm/common/fconf/arm_fconf_io.c +++ b/plat/arm/common/fconf/arm_fconf_io.c @@ -25,8 +25,31 @@ const io_block_spec_t fip_block_spec = { const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = { [BL2_IMAGE_ID] = {UUID_TRUSTED_BOOT_FIRMWARE_BL2}, [TB_FW_CONFIG_ID] = {UUID_TB_FW_CONFIG}, +#if !ARM_IO_IN_DTB + [SCP_BL2_IMAGE_ID] = {UUID_SCP_FIRMWARE_SCP_BL2}, + [BL31_IMAGE_ID] = {UUID_EL3_RUNTIME_FIRMWARE_BL31}, + [BL32_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32}, + [BL32_EXTRA1_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32_EXTRA1}, + [BL32_EXTRA2_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32_EXTRA2}, + [BL33_IMAGE_ID] = {UUID_NON_TRUSTED_FIRMWARE_BL33}, + [HW_CONFIG_ID] = {UUID_HW_CONFIG}, + [SOC_FW_CONFIG_ID] = {UUID_SOC_FW_CONFIG}, + [TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG}, + [NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG}, +#endif /* ARM_IO_IN_DTB */ #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT}, +#if !ARM_IO_IN_DTB + [TRUSTED_KEY_CERT_ID] = {UUID_TRUSTED_KEY_CERT}, + [SCP_FW_KEY_CERT_ID] = {UUID_SCP_FW_KEY_CERT}, + [SOC_FW_KEY_CERT_ID] = {UUID_SOC_FW_KEY_CERT}, + [TRUSTED_OS_FW_KEY_CERT_ID] = {UUID_TRUSTED_OS_FW_KEY_CERT}, + [NON_TRUSTED_FW_KEY_CERT_ID] = {UUID_NON_TRUSTED_FW_KEY_CERT}, + [SCP_FW_CONTENT_CERT_ID] = {UUID_SCP_FW_CONTENT_CERT}, + [SOC_FW_CONTENT_CERT_ID] = {UUID_SOC_FW_CONTENT_CERT}, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = {UUID_TRUSTED_OS_FW_CONTENT_CERT}, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = {UUID_NON_TRUSTED_FW_CONTENT_CERT}, +#endif /* ARM_IO_IN_DTB */ #endif /* TRUSTED_BOARD_BOOT */ }; @@ -47,12 +70,111 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { (uintptr_t)&arm_uuid_spec[TB_FW_CONFIG_ID], open_fip }, +#if !ARM_IO_IN_DTB + [SCP_BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[SCP_BL2_IMAGE_ID], + open_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[BL31_IMAGE_ID], + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[BL32_IMAGE_ID], + open_fip + }, + [BL32_EXTRA1_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[BL32_EXTRA1_IMAGE_ID], + open_fip + }, + [BL32_EXTRA2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[BL32_EXTRA2_IMAGE_ID], + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[BL33_IMAGE_ID], + open_fip + }, + [HW_CONFIG_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[HW_CONFIG_ID], + open_fip + }, + [SOC_FW_CONFIG_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[SOC_FW_CONFIG_ID], + open_fip + }, + [TOS_FW_CONFIG_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[TOS_FW_CONFIG_ID], + open_fip + }, + [NT_FW_CONFIG_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID], + open_fip + }, +#endif /* ARM_IO_IN_DTB */ #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = { &fip_dev_handle, (uintptr_t)&arm_uuid_spec[TRUSTED_BOOT_FW_CERT_ID], open_fip }, +#if !ARM_IO_IN_DTB + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[TRUSTED_KEY_CERT_ID], + open_fip + }, + [SCP_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[SCP_FW_KEY_CERT_ID], + open_fip + }, + [SOC_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[SOC_FW_KEY_CERT_ID], + open_fip + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[TRUSTED_OS_FW_KEY_CERT_ID], + open_fip + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[NON_TRUSTED_FW_KEY_CERT_ID], + open_fip + }, + [SCP_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[SCP_FW_CONTENT_CERT_ID], + open_fip + }, + [SOC_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[SOC_FW_CONTENT_CERT_ID], + open_fip + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[TRUSTED_OS_FW_CONTENT_CERT_ID], + open_fip + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[NON_TRUSTED_FW_CONTENT_CERT_ID], + open_fip + }, +#endif /* ARM_IO_IN_DTB */ #endif /* TRUSTED_BOARD_BOOT */ }; @@ -138,6 +260,8 @@ int fconf_populate_arm_io_policies(uintptr_t config) return 0; } +#if ARM_IO_IN_DTB FCONF_REGISTER_POPULATOR(TB_FW, arm_io, fconf_populate_arm_io_policies); +#endif /* ARM_IO_IN_DTB */ #endif /* IMAGE_BL2 */ diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index 9a482d0c0..8c8b2311d 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -56,7 +56,7 @@ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 /* * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page @@ -141,7 +141,7 @@ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ ARM_SHARED_RAM_BASE, \ ARM_SHARED_RAM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE \ + MT_NON_CACHEABLE | MT_RW | MT_SECURE \ ) #define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \ diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c index fcb7e1f9f..a4aed004d 100644 --- a/plat/arm/css/sgi/sgi_bl31_setup.c +++ b/plat/arm/css/sgi/sgi_bl31_setup.c @@ -75,7 +75,7 @@ scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id) { if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM || sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM) { - if (channel_id >= sizeof(rd_n1e1_edge_scmi_plat_info)) + if (channel_id >= ARRAY_SIZE(rd_n1e1_edge_scmi_plat_info)) panic(); return &rd_n1e1_edge_scmi_plat_info[channel_id]; } diff --git a/plat/imx/common/include/imx8_iomux.h b/plat/imx/common/include/imx8_iomux.h index 0e93d9800..264c295bb 100644 --- a/plat/imx/common/include/imx8_iomux.h +++ b/plat/imx/common/include/imx8_iomux.h @@ -7,19 +7,19 @@ #ifndef IMX8_IOMUX_H #define IMX8_IOMUX_H -#define PADRING_IFMUX_EN_SHIFT 31 -#define PADRING_IFMUX_EN_MASK (1 << PADRING_IFMUX_EN_SHIFT) -#define PADRING_GP_EN_SHIFT 30 -#define PADRING_GP_EN_MASK (1 << PADRING_GP_EN_SHIFT) -#define PADRING_IFMUX_SHIFT 27 -#define PADRING_IFMUX_MASK (0x7 << PADRING_IFMUX_SHIFT) -#define PADRING_CONFIG_SHIFT 25 -#define PADRING_CONFIG_MASK (0x3 << PADRING_CONFIG_SHIFT) -#define PADRING_LPCONFIG_SHIFT 23 -#define PADRING_LPCONFIG_MASK (0x3 << PADRING_LPCONFIG_SHIFT) -#define PADRING_PULL_SHIFT 5 -#define PADRING_PULL_MASK (0x3 << PADRING_PULL_SHIFT) -#define PADRING_DSE_SHIFT 0 -#define PADRING_DSE_MASK (0x7 << PADRING_DSE_SHIFT) +#define PADRING_IFMUX_EN_SHIFT U(31) +#define PADRING_IFMUX_EN_MASK (U(0x1) << PADRING_IFMUX_EN_SHIFT) +#define PADRING_GP_EN_SHIFT U(30) +#define PADRING_GP_EN_MASK (U(0x1) << PADRING_GP_EN_SHIFT) +#define PADRING_IFMUX_SHIFT U(27) +#define PADRING_IFMUX_MASK (U(0x7) << PADRING_IFMUX_SHIFT) +#define PADRING_CONFIG_SHIFT U(25) +#define PADRING_CONFIG_MASK (U(0x3) << PADRING_CONFIG_SHIFT) +#define PADRING_LPCONFIG_SHIFT U(23) +#define PADRING_LPCONFIG_MASK (U(0x3) << PADRING_LPCONFIG_SHIFT) +#define PADRING_PULL_SHIFT U(5) +#define PADRING_PULL_MASK (U(0x3) << PADRING_PULL_SHIFT) +#define PADRING_DSE_SHIFT U(0) +#define PADRING_DSE_MASK (U(0x7) << PADRING_DSE_SHIFT) #endif /* IMX8_IOMUX_H */ diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c index cffb140fb..4ca6a5db4 100644 --- a/plat/imx/imx8qm/imx8qm_bl31_setup.c +++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c @@ -44,6 +44,22 @@ static entry_point_info_t bl33_image_ep_info; (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) +#if defined(IMX_USE_UART0) +#define IMX_RES_UART SC_R_UART_0 +#define IMX_PAD_UART_RX SC_P_UART0_RX +#define IMX_PAD_UART_TX SC_P_UART0_TX +#define IMX_PAD_UART_RTS_B SC_P_UART0_RTS_B +#define IMX_PAD_UART_CTS_B SC_P_UART0_CTS_B +#elif defined(IMX_USE_UART1) +#define IMX_RES_UART SC_R_UART_1 +#define IMX_PAD_UART_RX SC_P_UART1_RX +#define IMX_PAD_UART_TX SC_P_UART1_TX +#define IMX_PAD_UART_RTS_B SC_P_UART1_RTS_B +#define IMX_PAD_UART_CTS_B SC_P_UART1_CTS_B +#else +#error "Provide proper UART number in IMX_DEBUG_UART" +#endif + const static int imx8qm_cci_map[] = { CLUSTER0_CCI_SLVAE_IFACE, CLUSTER1_CCI_SLVAE_IFACE @@ -79,7 +95,7 @@ static void lpuart32_serial_setbrg(unsigned int base, int baudrate) if (baudrate == 0) panic(); - sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); + sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); baud_diff = baudrate; osr = 0; @@ -301,16 +317,17 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, panic(); #if DEBUG_CONSOLE_A53 - sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(ipc_handle, IMX_RES_UART, + SC_PM_PW_MODE_ON); sc_pm_clock_rate_t rate = 80000000; - sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); - sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false); + sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); + sc_pm_clock_enable(ipc_handle, IMX_RES_UART, 2, true, false); /* configure UART pads */ - sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL); - sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL); - sc_pad_set(ipc_handle, SC_P_UART0_RTS_B, UART_PAD_CTRL); - sc_pad_set(ipc_handle, SC_P_UART0_CTS_B, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_RX, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_TX, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_RTS_B, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_CTS_B, UART_PAD_CTRL); lpuart32_serial_init(IMX_BOOT_UART_BASE); #endif diff --git a/plat/imx/imx8qm/include/platform_def.h b/plat/imx/imx8qm/include/platform_def.h index b54943da0..671c77f76 100644 --- a/plat/imx/imx8qm/include/platform_def.h +++ b/plat/imx/imx8qm/include/platform_def.h @@ -40,12 +40,22 @@ #define PLAT_CCI_BASE 0x52090000 #define CLUSTER0_CCI_SLVAE_IFACE 3 #define CLUSTER1_CCI_SLVAE_IFACE 4 + +/* UART */ +#if defined(IMX_USE_UART0) #define IMX_BOOT_UART_BASE 0x5a060000 +#elif defined(IMX_USE_UART1) +#define IMX_BOOT_UART_BASE 0x5a070000 +#else +#error "Provide proper UART number in IMX_DEBUG_UART" +#endif + #define IMX_BOOT_UART_BAUDRATE 115200 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 #define IMX_CONSOLE_BAUDRATE 115200 + #define SC_IPC_BASE 0x5d1b0000 #define IMX_GPT_LPCG_BASE 0x5d540000 #define IMX_GPT_BASE 0x5d140000 @@ -64,7 +74,6 @@ #define MAX_XLAT_TABLES 8 #define MAX_MMAP_REGIONS 12 -#define DEBUG_CONSOLE 0 -#define DEBUG_CONSOLE_A53 0 +#define DEBUG_CONSOLE_A53 DEBUG_CONSOLE #endif /* PLATFORM_DEF_H */ diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk index 5ba9c3f7b..20ee05be9 100644 --- a/plat/imx/imx8qm/platform.mk +++ b/plat/imx/imx8qm/platform.mk @@ -43,3 +43,9 @@ ERRATA_A72_859971 := 1 ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 + +IMX_DEBUG_UART ?= 0 +$(eval $(call add_define,IMX_USE_UART${IMX_DEBUG_UART})) + +DEBUG_CONSOLE ?= 0 +$(eval $(call add_define,DEBUG_CONSOLE)) diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 7cba3a449..5f01416d8 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -39,6 +39,7 @@ .globl plat_crash_console_init .globl plat_crash_console_putc .globl plat_crash_console_flush + .weak plat_core_pos_by_mpidr .globl tegra_secure_entrypoint .globl plat_reset_handler @@ -140,17 +141,14 @@ endfunc plat_is_my_cpu_primary * unsigned int plat_my_core_pos(void); * * result: CorePos = CoreId + (ClusterId * cpus per cluster) + * Registers clobbered: x0, x8 * ---------------------------------------------------------- */ func plat_my_core_pos + mov x8, x30 mrs x0, mpidr_el1 - and x1, x0, #MPIDR_CPU_MASK - and x0, x0, #MPIDR_CLUSTER_MASK - lsr x0, x0, #MPIDR_AFFINITY_BITS - mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER - mul x0, x0, x2 - add x0, x1, x0 - ret + bl plat_core_pos_by_mpidr + ret x8 endfunc plat_my_core_pos /* ----------------------------------------------------- @@ -273,6 +271,42 @@ _end: mov x0, x20 ret endfunc plat_reset_handler + /* ------------------------------------------------------ + * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) + * + * This function implements a part of the critical + * interface between the psci generic layer and the + * platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error + * code (-1) is returned in case the MPIDR is invalid. + * + * Clobbers: x0-x3 + * ------------------------------------------------------ + */ +func plat_core_pos_by_mpidr + lsr x1, x0, #MPIDR_AFF0_SHIFT + and x1, x1, #MPIDR_AFFLVL_MASK /* core id */ + lsr x2, x0, #MPIDR_AFF1_SHIFT + and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */ + + /* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */ + mov x0, #-1 + cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1) + b.gt 1f + + /* cluster_id >= PLATFORM_CLUSTER_COUNT */ + cmp x2, #(PLATFORM_CLUSTER_COUNT - 1) + b.gt 1f + + /* CorePos = CoreId + (ClusterId * cpus per cluster) */ + mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER + mul x3, x3, x2 + add x0, x1, x3 + +1: + ret +endfunc plat_core_pos_by_mpidr + /* ---------------------------------------- * Secure entrypoint function for CPU boot * ---------------------------------------- diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c index 57daf6aeb..d964fc001 100644 --- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c +++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c @@ -8,6 +8,7 @@ #include <assert.h> #include <common/debug.h> #include <errno.h> +#include <stdbool.h> #include <stddef.h> #include <string.h> diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c index 92fa273b5..c3f95db4d 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -117,7 +117,8 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start, ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */ non_overlap_area_start, /* VA */ non_overlap_area_size, /* size */ - MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ + MT_NS | MT_RW | MT_EXECUTE_NEVER | + MT_NON_CACHEABLE); /* attrs */ assert(ret == 0); zeromem((void *)non_overlap_area_start, non_overlap_area_size); diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index a53f66078..5555f5df3 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -159,69 +159,7 @@ void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) */ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) { - uint32_t index; - uint32_t total_128kb_blocks = size_in_bytes >> 17; - uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; - uint32_t val; - - INFO("Configuring TrustZone SRAM Memory Carveout\n"); - - /* - * Reset the access configuration registers to restrict access - * to the TZRAM aperture - */ - for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0; - index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); - index += 4U) { - tegra_mc_write_32(index, 0); - } - - /* - * Enable CPU access configuration registers to access the TZRAM aperture - */ - if (!tegra_chipid_is_t186()) { - val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0); - val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW; - tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val); - } - - /* - * Set the TZRAM base. TZRAM base must be 4k aligned, at least. - */ - assert((phys_base & (uint64_t)0xFFF) == 0U); - tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base); - tegra_mc_write_32(MC_TZRAM_BASE_HI, - (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK); - - /* - * Set the TZRAM size - * - * total size = (number of 128KB blocks) + (number of remaining 4KB - * blocks) - * - */ - val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | - total_128kb_blocks; - tegra_mc_write_32(MC_TZRAM_SIZE, val); - - /* - * Lock the configuration settings by disabling TZ-only lock - * and locking the configuration against any future changes - * at all. - */ - val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG); - val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT; - val |= MC_GSC_LOCK_CFG_SETTINGS_BIT; - if (!tegra_chipid_is_t186()) { - val |= MC_GSC_ENABLE_CPU_SECURE_BIT; - } - tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val); - - /* - * MCE propagates the security configuration values across the - * CCPLEX. - */ - mce_update_gsc_tzram(); + ; /* do nothing */ } /* @@ -348,7 +286,8 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start, ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */ non_overlap_area_start, /* VA */ non_overlap_area_size, /* size */ - MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ + MT_NS | MT_RW | MT_EXECUTE_NEVER | + MT_NON_CACHEABLE); /* attrs */ assert(ret == 0); zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size); diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 46686c368..269afb196 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -39,15 +39,8 @@ * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ - IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); -static const uint64_t BL31_RW_END = BL_END; -static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; -static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; -static const uint64_t TEXT_START = BL_CODE_BASE; -static const uint64_t TEXT_END = BL_CODE_END; - extern uint64_t tegra_bl31_phys_base; static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; @@ -314,15 +307,12 @@ void bl31_plat_runtime_setup(void) void bl31_plat_arch_setup(void) { uint64_t rw_start = BL31_RW_START; - uint64_t rw_size = BL31_RW_END - BL31_RW_START; - uint64_t rodata_start = BL31_RODATA_BASE; - uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; - uint64_t code_base = TEXT_START; - uint64_t code_size = TEXT_END - TEXT_START; + uint64_t rw_size = BL_END - BL31_RW_START; + uint64_t rodata_start = BL_RO_DATA_BASE; + uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE; + uint64_t code_base = BL_CODE_BASE; + uint64_t code_size = BL_CODE_END - BL_CODE_BASE; const mmap_region_t *plat_mmio_map = NULL; -#if USE_COHERENT_MEM - uint32_t coh_start, coh_size; -#endif const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); /* @@ -349,15 +339,6 @@ void bl31_plat_arch_setup(void) code_size, MT_CODE | MT_SECURE); -#if USE_COHERENT_MEM - coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); - coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; - - mmap_add_region(coh_start, coh_start, - coh_size, - (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE); -#endif - /* map TZDRAM used by BL31 as coherent memory */ if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { mmap_add_region(params_from_bl2->tzdram_base, diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index 50c9592f1..c946a7597 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -6,8 +6,7 @@ PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \ -Iplat/nvidia/tegra/include/lib \ - -Iplat/nvidia/tegra/include \ - -Iplat/nvidia/tegra/include/${TARGET_SOC} + -Iplat/nvidia/tegra/include include lib/xlat_tables_v2/xlat_tables.mk PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} @@ -32,5 +31,4 @@ BL31_SOURCES += drivers/delay_timer/delay_timer.c \ ${COMMON_DIR}/tegra_io_storage.c \ ${COMMON_DIR}/tegra_platform.c \ ${COMMON_DIR}/tegra_pm.c \ - ${COMMON_DIR}/tegra_sip_calls.c \ - ${COMMON_DIR}/tegra_topology.c + ${COMMON_DIR}/tegra_sip_calls.c diff --git a/plat/nvidia/tegra/common/tegra_gicv2.c b/plat/nvidia/tegra/common/tegra_gicv2.c index 293df8d4f..012107e3b 100644 --- a/plat/nvidia/tegra/common/tegra_gicv2.c +++ b/plat/nvidia/tegra/common/tegra_gicv2.c @@ -1,20 +1,23 @@ /* * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> - #include <platform_def.h> #include <common/bl_common.h> #include <drivers/arm/gicv2.h> #include <lib/utils.h> +#include <plat/common/platform.h> #include <tegra_private.h> #include <tegra_def.h> +static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT]; + /****************************************************************************** * Tegra common helper to setup the GICv2 driver data. *****************************************************************************/ @@ -33,6 +36,8 @@ void tegra_gic_setup(const interrupt_prop_t *interrupt_props, tegra_gic_data.gicc_base = TEGRA_GICC_BASE; tegra_gic_data.interrupt_props = interrupt_props; tegra_gic_data.interrupt_props_num = interrupt_props_num; + tegra_gic_data.target_masks = tegra_target_masks; + tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks); gicv2_driver_init(&tegra_gic_data); } @@ -43,6 +48,7 @@ void tegra_gic_init(void) { gicv2_distif_init(); gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); } @@ -61,5 +67,6 @@ void tegra_gic_cpuif_deactivate(void) void tegra_gic_pcpu_init(void) { gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); } diff --git a/plat/nvidia/tegra/common/tegra_topology.c b/plat/nvidia/tegra/common/tegra_topology.c deleted file mode 100644 index 205b05165..000000000 --- a/plat/nvidia/tegra/common/tegra_topology.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <platform_def.h> - -#include <arch.h> -#include <lib/psci/psci.h> -#include <plat/common/platform.h> - -#pragma weak plat_core_pos_by_mpidr - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int32_t plat_core_pos_by_mpidr(u_register_t mpidr) -{ - u_register_t cluster_id, cpu_id; - int32_t result; - - cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & - (u_register_t)MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & - (u_register_t)MPIDR_AFFLVL_MASK; - - /* CorePos = CoreId + (ClusterId * cpus per cluster) */ - result = (int32_t)cpu_id + ((int32_t)cluster_id * - PLATFORM_MAX_CPUS_PER_CLUSTER); - - if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) { - result = PSCI_E_NOT_PRESENT; - } - - /* - * Validate cpu_id by checking whether it represents a CPU in - * one of the two clusters present on the platform. - */ - if (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER) { - result = PSCI_E_NOT_PRESENT; - } - - return result; -} diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h index 54336b044..e5ab600b4 100644 --- a/plat/nvidia/tegra/include/drivers/flowctrl.h +++ b/plat/nvidia/tegra/include/drivers/flowctrl.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +10,8 @@ #include <lib/mmio.h> +#include <stdbool.h> + #include <tegra_def.h> #define FLOWCTRL_HALT_CPU0_EVENTS (0x0U) diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h index 4470b6b8b..5f1bb4f28 100644 --- a/plat/nvidia/tegra/include/drivers/mce.h +++ b/plat/nvidia/tegra/include/drivers/mce.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,7 +69,6 @@ int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, int mce_update_reset_vector(void); int mce_update_gsc_videomem(void); int mce_update_gsc_tzdram(void); -int mce_update_gsc_tzram(void); __dead2 void mce_enter_ccplex_state(uint32_t state_idx); void mce_update_cstate_info(const mce_cstate_info_t *cstate); void mce_verify_firmware_version(void); diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index eb55def4a..91a24ca7e 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +13,19 @@ #include <tegra_def.h> +/******************************************************************************* + * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1 + ******************************************************************************/ +#if !SEPARATE_CODE_AND_RODATA +#error "SEPARATE_CODE_AND_RODATA should be set to 1" +#endif + +/* + * Platform binary types for linking + */ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + /* * Platform binary types for linking */ @@ -33,7 +47,7 @@ #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ - PLATFORM_CLUSTER_COUNT + 1) + PLATFORM_CLUSTER_COUNT + U(1)) /******************************************************************************* * Platform console related constants @@ -72,4 +86,5 @@ #define MAX_IO_DEVICES U(0) #define MAX_IO_HANDLES U(0) + #endif /* PLATFORM_DEF_H */ diff --git a/plat/nvidia/tegra/include/t186/tegra186_private.h b/plat/nvidia/tegra/include/t186/tegra186_private.h index 60174ab54..4514e1477 100644 --- a/plat/nvidia/tegra/include/t186/tegra186_private.h +++ b/plat/nvidia/tegra/include/t186/tegra186_private.h @@ -7,10 +7,6 @@ #ifndef TEGRA186_PRIVATE_H #define TEGRA186_PRIVATE_H -void tegra186_cpu_reset_handler(void); -uint64_t tegra186_get_cpu_reset_handler_base(void); -uint64_t tegra186_get_cpu_reset_handler_size(void); -uint64_t tegra186_get_mc_ctx_offset(void); -void tegra186_set_system_suspend_entry(void); +uint64_t tegra186_get_mc_ctx_size(void); #endif /* TEGRA186_PRIVATE_H */ diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index dc0644514..e39f9cad6 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -10,6 +10,12 @@ #include <lib/utils_def.h> /******************************************************************************* + * Chip specific cluster and cpu numbers + ******************************************************************************/ +#define PLATFORM_CLUSTER_COUNT U(4) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) + +/******************************************************************************* * Chip specific page table and MMU setup constants ******************************************************************************/ #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index ad3cee4b4..f72c9cf3c 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -47,6 +47,8 @@ typedef struct plat_params_from_bl2 { uint64_t sc7entry_fw_size; /* System Suspend Entry Firmware base address */ uint64_t sc7entry_fw_base; + /* Enable dual execution */ + uint8_t enable_ccplex_lock_step; } plat_params_from_bl2_t; /******************************************************************************* diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk index d0ed5d57a..87588202c 100644 --- a/plat/nvidia/tegra/platform.mk +++ b/plat/nvidia/tegra/platform.mk @@ -13,7 +13,7 @@ $(eval $(call add_define,CRASH_REPORTING)) # enable assert() for release/debug builds ENABLE_ASSERTIONS := 1 -PLAT_LOG_LEVEL_ASSERT := 40 +PLAT_LOG_LEVEL_ASSERT := 50 $(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT)) # enable dynamic memory mapping @@ -40,7 +40,7 @@ OVERRIDE_LIBC := 1 # Flag to enable WDT FIQ interrupt handling for Tegra SoCs # prior to Tegra186 -ENABLE_WDT_LEGACY_FIQ_HANDLING ?= 0 +ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING ?= 0 # Flag to allow relocation of BL32 image to TZDRAM during boot RELOCATE_BL32_IMAGE ?= 0 @@ -48,7 +48,7 @@ RELOCATE_BL32_IMAGE ?= 0 include plat/nvidia/tegra/common/tegra_common.mk include ${SOC_DIR}/platform_${TARGET_SOC}.mk -$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING)) +$(eval $(call add_define,ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING)) $(eval $(call add_define,RELOCATE_BL32_IMAGE)) # modify BUILD_PLAT to point to SoC specific build directory diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk index 183e1889c..16bd0ead2 100644 --- a/plat/nvidia/tegra/soc/t132/platform_t132.mk +++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -20,6 +20,9 @@ $(eval $(call add_define,MAX_XLAT_TABLES)) MAX_MMAP_REGIONS := 8 $(eval $(call add_define,MAX_MMAP_REGIONS)) +# platform files +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132 + BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index 9e42b2bcb..54d3b2ccd 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -386,14 +387,6 @@ int32_t mce_update_gsc_tzdram(void) } /******************************************************************************* - * Handler to update carveout values for TZ SysRAM aperture - ******************************************************************************/ -int32_t mce_update_gsc_tzram(void) -{ - return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM); -} - -/******************************************************************************* * Handler to shutdown/reset the entire system ******************************************************************************/ __dead2 void mce_enter_ccplex_state(uint32_t state_idx) diff --git a/plat/nvidia/tegra/soc/t186/drivers/se/se.c b/plat/nvidia/tegra/soc/t186/drivers/se/se.c index dfb9de882..25f8cd028 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/se/se.c +++ b/plat/nvidia/tegra/soc/t186/drivers/se/se.c @@ -12,7 +12,6 @@ #include <bpmp_ipc.h> #include <pmc.h> #include <security_engine.h> -#include <tegra186_private.h> #include <tegra_private.h> #include "se_private.h" diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c index 09377bb09..4eb68e44a 100644 --- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c @@ -10,8 +10,8 @@ #include <mce.h> #include <memctrl_v2.h> -#include <tegra_mc_def.h> #include <tegra186_private.h> +#include <tegra_mc_def.h> #include <tegra_platform.h> #include <tegra_private.h> @@ -21,29 +21,6 @@ extern uint64_t tegra_bl31_phys_base; * Array to hold stream_id override config register offsets ******************************************************************************/ const static uint32_t tegra186_streamid_override_regs[] = { - MC_STREAMID_OVERRIDE_CFG_PTCR, - MC_STREAMID_OVERRIDE_CFG_AFIR, - MC_STREAMID_OVERRIDE_CFG_HDAR, - MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD, - MC_STREAMID_OVERRIDE_CFG_SATAR, - MC_STREAMID_OVERRIDE_CFG_MPCORER, - MC_STREAMID_OVERRIDE_CFG_NVENCSWR, - MC_STREAMID_OVERRIDE_CFG_AFIW, - MC_STREAMID_OVERRIDE_CFG_HDAW, - MC_STREAMID_OVERRIDE_CFG_MPCOREW, - MC_STREAMID_OVERRIDE_CFG_SATAW, - MC_STREAMID_OVERRIDE_CFG_ISPRA, - MC_STREAMID_OVERRIDE_CFG_ISPWA, - MC_STREAMID_OVERRIDE_CFG_ISPWB, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, - MC_STREAMID_OVERRIDE_CFG_TSECSRD, - MC_STREAMID_OVERRIDE_CFG_TSECSWR, - MC_STREAMID_OVERRIDE_CFG_GPUSRD, - MC_STREAMID_OVERRIDE_CFG_GPUSWR, MC_STREAMID_OVERRIDE_CFG_SDMMCRA, MC_STREAMID_OVERRIDE_CFG_SDMMCRAA, MC_STREAMID_OVERRIDE_CFG_SDMMCR, @@ -52,47 +29,6 @@ const static uint32_t tegra186_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_SDMMCWAA, MC_STREAMID_OVERRIDE_CFG_SDMMCW, MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, - MC_STREAMID_OVERRIDE_CFG_VICSRD, - MC_STREAMID_OVERRIDE_CFG_VICSWR, - MC_STREAMID_OVERRIDE_CFG_VIW, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD, - MC_STREAMID_OVERRIDE_CFG_NVDECSWR, - MC_STREAMID_OVERRIDE_CFG_APER, - MC_STREAMID_OVERRIDE_CFG_APEW, - MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, - MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, - MC_STREAMID_OVERRIDE_CFG_SESRD, - MC_STREAMID_OVERRIDE_CFG_SESWR, - MC_STREAMID_OVERRIDE_CFG_ETRR, - MC_STREAMID_OVERRIDE_CFG_ETRW, - MC_STREAMID_OVERRIDE_CFG_TSECSRDB, - MC_STREAMID_OVERRIDE_CFG_TSECSWRB, - MC_STREAMID_OVERRIDE_CFG_GPUSRD2, - MC_STREAMID_OVERRIDE_CFG_GPUSWR2, - MC_STREAMID_OVERRIDE_CFG_AXISR, - MC_STREAMID_OVERRIDE_CFG_AXISW, - MC_STREAMID_OVERRIDE_CFG_EQOSR, - MC_STREAMID_OVERRIDE_CFG_EQOSW, - MC_STREAMID_OVERRIDE_CFG_UFSHCR, - MC_STREAMID_OVERRIDE_CFG_UFSHCW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, - MC_STREAMID_OVERRIDE_CFG_BPMPR, - MC_STREAMID_OVERRIDE_CFG_BPMPW, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, - MC_STREAMID_OVERRIDE_CFG_AONR, - MC_STREAMID_OVERRIDE_CFG_AONW, - MC_STREAMID_OVERRIDE_CFG_AONDMAR, - MC_STREAMID_OVERRIDE_CFG_AONDMAW, - MC_STREAMID_OVERRIDE_CFG_SCER, - MC_STREAMID_OVERRIDE_CFG_SCEW, - MC_STREAMID_OVERRIDE_CFG_SCEDMAR, - MC_STREAMID_OVERRIDE_CFG_SCEDMAW, - MC_STREAMID_OVERRIDE_CFG_APEDMAR, - MC_STREAMID_OVERRIDE_CFG_APEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, - MC_STREAMID_OVERRIDE_CFG_VICSRD1, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 }; /******************************************************************************* @@ -711,13 +647,6 @@ tegra_mc_settings_t *tegra_get_mc_settings(void) void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) { uint32_t val; - uint64_t src_base_tzdram; - const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); - uint64_t src_len_in_bytes = BL31_END - BL31_START; - - /* base address of BL3-1 source in TZDRAM */ - src_base_tzdram = params_from_bl2->tzdram_base + - tegra186_get_cpu_reset_handler_size(); /* * Setup the Memory controller to allow only secure accesses to @@ -747,15 +676,6 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val); /* - * save tzdram_addr_lo and ATF-size, this would be used in SC7-RF to - * generate SHA256. - */ - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO, - (uint32_t)src_base_tzdram); - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI, - (uint32_t)src_len_in_bytes); - - /* * MCE propagates the security configuration values across the * CCPLEX. */ diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 179dd9654..6f58427b3 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -134,8 +134,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); /* save MC context to TZDRAM */ - mc_ctx_base = params_from_bl2->tzdram_base + - tegra186_get_mc_ctx_offset(); + mc_ctx_base = params_from_bl2->tzdram_base; tegra_mc_save_context((uintptr_t)mc_ctx_base); /* Prepare for system suspend */ @@ -158,9 +157,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); - /* set system suspend state for house-keeping */ - tegra186_set_system_suspend_entry(); - } else { ; /* do nothing */ } @@ -289,7 +285,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { val = params_from_bl2->tzdram_base + - tegra186_get_cpu_reset_handler_size(); + tegra186_get_mc_ctx_size(); /* Initialise communication channel with BPMP */ assert(tegra_bpmp_ipc_init() == 0); @@ -316,10 +312,19 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta * BL3-1 over to TZDRAM. */ val = params_from_bl2->tzdram_base + - tegra186_get_cpu_reset_handler_size(); + tegra186_get_mc_ctx_size(); memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)BL31_END - (uintptr_t)BL31_BASE); + /* + * Save code base and size; this would be used by SC7-RF to + * verify binary + */ + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO, + (uint32_t)val); + mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI, + (uint32_t)src_len_in_bytes); + ret = tegra_bpmp_ipc_disable_clock(TEGRA186_CLK_SE); if (ret != 0) { ERROR("Failed to disable clock\n"); diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c index 16508093e..fbb550af9 100644 --- a/plat/nvidia/tegra/soc/t186/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,56 +12,30 @@ #include <lib/mmio.h> #include <mce.h> -#include <tegra186_private.h> #include <tegra_def.h> #include <tegra_private.h> -#define MISCREG_AA64_RST_LOW 0x2004U -#define MISCREG_AA64_RST_HIGH 0x2008U - #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU #define CPU_RESET_MODE_AA64 1U -extern void memcpy16(void *dest, const void *src, unsigned int length); - /******************************************************************************* * Setup secondary CPU vectors ******************************************************************************/ void plat_secondary_setup(void) { uint32_t addr_low, addr_high; - const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); - uint64_t cpu_reset_handler_base, cpu_reset_handler_size; INFO("Setting up secondary CPU boot\n"); - /* - * The BL31 code resides in the TZSRAM which loses state - * when we enter System Suspend. Copy the wakeup trampoline - * code to TZDRAM to help us exit from System Suspend. - */ - cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base(); - cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size(); - (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base, - (const void *)(uintptr_t)cpu_reset_handler_base, - cpu_reset_handler_size); - /* TZDRAM base will be used as the "resume" address */ - addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; - addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); - - /* write lower 32 bits first, then the upper 11 bits */ - mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); - mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); + addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64; + addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU); /* save reset vector to be used during SYSTEM_SUSPEND exit */ mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, addr_low); mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, addr_high); - - /* update reset vector address to the CCPLEX */ - (void)mce_update_reset_vector(); } diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S index 818c24b49..2fc2046d0 100644 --- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S @@ -12,135 +12,30 @@ #include <plat/common/common_def.h> #include <tegra_def.h> -#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7 -#define TEGRA186_STATE_SYSTEM_RESUME 0x600D #define TEGRA186_MC_CTX_SIZE 0x93 - .globl tegra186_cpu_reset_handler - -/* CPU reset handler routine */ -func tegra186_cpu_reset_handler _align=4 - /* check if we are exiting system suspend state */ - adr x0, __tegra186_system_suspend_state - ldr x1, [x0] - mov x2, #TEGRA186_STATE_SYSTEM_SUSPEND - lsl x2, x2, #16 - add x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND - cmp x1, x2 - bne boot_cpu - - /* set system resume state */ - mov x1, #TEGRA186_STATE_SYSTEM_RESUME - lsl x1, x1, #16 - mov x2, #TEGRA186_STATE_SYSTEM_RESUME - add x1, x1, x2 - str x1, [x0] - dsb sy - - /* prepare to relocate to TZSRAM */ - mov x0, #BL31_BASE - adr x1, __tegra186_cpu_reset_handler_end - adr x2, __tegra186_cpu_reset_handler_data - ldr x2, [x2, #8] - - /* memcpy16 */ -m_loop16: - cmp x2, #16 - b.lt m_loop1 - ldp x3, x4, [x1], #16 - stp x3, x4, [x0], #16 - sub x2, x2, #16 - b m_loop16 - /* copy byte per byte */ -m_loop1: - cbz x2, boot_cpu - ldrb w3, [x1], #1 - strb w3, [x0], #1 - subs x2, x2, #1 - b.ne m_loop1 - -boot_cpu: - adr x0, __tegra186_cpu_reset_handler_data - ldr x0, [x0] - br x0 -endfunc tegra186_cpu_reset_handler + .globl tegra186_get_mc_ctx_size /* - * Tegra186 reset data (offset 0x0 - 0x430) + * Tegra186 reset data (offset 0x0 - 0x420) * - * 0x000: secure world's entrypoint - * 0x008: BL31 size (RO + RW) - * 0x00C: MC context start - * 0x42C: MC context end + * 0x000: MC context start + * 0x420: MC context end */ .align 4 - .type __tegra186_cpu_reset_handler_data, %object - .globl __tegra186_cpu_reset_handler_data -__tegra186_cpu_reset_handler_data: - .quad tegra_secure_entrypoint - .quad __BL31_END__ - BL31_BASE - - .globl __tegra186_system_suspend_state -__tegra186_system_suspend_state: - .quad 0 - - .align 4 - .globl __tegra186_mc_context __tegra186_mc_context: .rept TEGRA186_MC_CTX_SIZE .quad 0 .endr - .size __tegra186_cpu_reset_handler_data, \ - . - __tegra186_cpu_reset_handler_data .align 4 - .globl __tegra186_cpu_reset_handler_end -__tegra186_cpu_reset_handler_end: - - .globl tegra186_get_cpu_reset_handler_size - .globl tegra186_get_cpu_reset_handler_base - .globl tegra186_get_mc_ctx_offset - .globl tegra186_set_system_suspend_entry - -/* return size of the CPU reset handler */ -func tegra186_get_cpu_reset_handler_size - adr x0, __tegra186_cpu_reset_handler_end - adr x1, tegra186_cpu_reset_handler - sub x0, x0, x1 - ret -endfunc tegra186_get_cpu_reset_handler_size - -/* return the start address of the CPU reset handler */ -func tegra186_get_cpu_reset_handler_base - adr x0, tegra186_cpu_reset_handler - ret -endfunc tegra186_get_cpu_reset_handler_base +__tegra186_mc_context_end: /* return the size of the MC context */ -func tegra186_get_mc_ctx_offset - adr x0, __tegra186_mc_context - adr x1, tegra186_cpu_reset_handler +func tegra186_get_mc_ctx_size + adr x0, __tegra186_mc_context_end + adr x1, __tegra186_mc_context sub x0, x0, x1 ret -endfunc tegra186_get_mc_ctx_offset - -/* set system suspend state before SC7 entry */ -func tegra186_set_system_suspend_entry - mov x0, #TEGRA_MC_BASE - mov x3, #MC_SECURITY_CFG3_0 - ldr w1, [x0, x3] - lsl x1, x1, #32 - mov x3, #MC_SECURITY_CFG0_0 - ldr w2, [x0, x3] - orr x3, x1, x2 /* TZDRAM base */ - adr x0, __tegra186_system_suspend_state - adr x1, tegra186_cpu_reset_handler - sub x2, x0, x1 /* offset in TZDRAM */ - mov x0, #TEGRA186_STATE_SYSTEM_SUSPEND - lsl x0, x0, #16 - add x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND - str x0, [x3, x2] /* set value in TZDRAM */ - dsb sy - ret -endfunc tegra186_set_system_suspend_entry +endfunc tegra186_get_mc_ctx_size diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk index d79155f31..a5341236d 100644 --- a/plat/nvidia/tegra/soc/t186/platform_t186.mk +++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk @@ -14,7 +14,7 @@ $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) RESET_TO_BL31 := 1 -PROGRAMMABLE_RESET_ADDRESS := 1 +PROGRAMMABLE_RESET_ADDRESS := 0 COLD_BOOT_SINGLE_CPU := 1 @@ -37,7 +37,8 @@ MAX_MMAP_REGIONS := 27 $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files -PLAT_INCLUDES += -I${SOC_DIR}/drivers/include +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \ + -I${SOC_DIR}/drivers/include BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 9ccb82382..7a68a4303 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -7,6 +7,8 @@ #ifndef T194_NVG_H #define T194_NVG_H +#include <lib/utils_def.h> + /** * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). * Official documentation for this interface is included as part @@ -20,7 +22,7 @@ */ enum { TEGRA_NVG_VERSION_MAJOR = U(6), - TEGRA_NVG_VERSION_MINOR = U(6) + TEGRA_NVG_VERSION_MINOR = U(7) }; typedef enum { @@ -71,6 +73,9 @@ typedef enum { TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = U(77), TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = U(78), TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = U(79), + TEGRA_NVG_CHANNEL_RT_SAFE_MASK = U(80), + TEGRA_NVG_CHANNEL_RT_WINDOW_US = U(81), + TEGRA_NVG_CHANNEL_RT_FWD_PROGRESS_US = U(82), TEGRA_NVG_CHANNEL_LAST_INDEX } tegra_nvg_channel_id_t; @@ -153,7 +158,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_power_perf_channel_t { + struct { uint32_t perf_per_watt : U(1); uint32_t reserved_31_1 : U(31); uint32_t reserved_63_32 : U(32); @@ -162,7 +167,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_power_modes_channel_t { + struct { uint32_t low_battery : U(1); uint32_t reserved_1_1 : U(1); uint32_t battery_save : U(1); @@ -182,7 +187,7 @@ typedef union nvg_channel_1_data_u { typedef union { uint64_t flat; - struct nvg_ccplex_cache_control_channel_t { + struct { uint32_t gpu_ways : U(5); uint32_t reserved_7_5 : U(3); uint32_t gpu_only_ways : U(5); @@ -203,7 +208,7 @@ typedef union nvg_channel_2_data_u { typedef union { uint64_t flat; - struct nvg_wake_time_channel_t { + struct { uint32_t wake_time : U(32); uint32_t reserved_63_32 : U(32); } bits; @@ -211,7 +216,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_cstate_info_channel_t { + struct { uint32_t cluster_state : U(3); uint32_t reserved_6_3 : U(4); uint32_t update_cluster : U(1); @@ -242,7 +247,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_lower_bound_channel_t { + struct { uint32_t crossover_value : U(32); uint32_t reserved_63_32 : U(32); } bits; @@ -250,7 +255,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_cstate_stat_query_channel_t { + struct { uint32_t unit_id : U(4); uint32_t reserved_15_4 : U(12); uint32_t stat_id : U(16); @@ -260,7 +265,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_num_cores_channel_t { + struct { uint32_t num_cores : U(4); uint32_t reserved_31_4 : U(28); uint32_t reserved_63_32 : U(32); @@ -269,7 +274,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_unique_logical_id_channel_t { + struct { uint32_t unique_core_id : U(3); uint32_t reserved_31_3 : U(29); uint32_t reserved_63_32 : U(32); @@ -278,7 +283,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_logical_to_physical_mappings_channel_t { + struct { uint32_t lcore0_pcore_id : U(4); uint32_t lcore1_pcore_id : U(4); uint32_t lcore2_pcore_id : U(4); @@ -306,7 +311,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_is_sc7_allowed_channel_t { + struct { uint32_t is_sc7_allowed : U(1); uint32_t reserved_31_1 : U(31); uint32_t reserved_63_32 : U(32); @@ -315,7 +320,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_core_online_channel_t { + struct { uint32_t core_id : U(4); uint32_t reserved_31_4 : U(28); uint32_t reserved_63_32 : U(32); @@ -324,7 +329,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_cc3_control_channel_t { + struct { uint32_t freq_req : U(9); uint32_t reserved_30_9 : U(22); uint32_t enable : U(1); @@ -374,7 +379,7 @@ typedef enum { typedef union { uint64_t flat; - struct nvg_update_ccplex_gsc_channel_t { + struct { uint32_t gsc_enum : U(16); uint32_t reserved_31_16 : U(16); uint32_t reserved_63_32 : U(32); @@ -411,7 +416,7 @@ typedef union { typedef union { uint64_t flat; - struct nvg_hsm_error_ctrl_channel_t { + struct { uint32_t uncorr : U(1); uint32_t corr : U(1); uint32_t reserved_31_2 : U(30); diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 00c671bcc..7edd7a09e 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -116,25 +116,6 @@ int32_t mce_update_gsc_tzdram(void) } /******************************************************************************* - * Handler to update carveout values for TZ SysRAM aperture - ******************************************************************************/ -int32_t mce_update_gsc_tzram(void) -{ - int32_t ret; - - /* - * MCE firmware is not running on simulation platforms. - */ - if (mce_firmware_not_supported()) { - ret = -EINVAL; - } else { - ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM); - } - - return ret; -} - -/******************************************************************************* * Handler to issue the UPDATE_CSTATE_INFO request ******************************************************************************/ void mce_update_cstate_info(const mce_cstate_info_t *cstate) diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c index ccdc94d13..31b0e2678 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c +++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c @@ -23,12 +23,11 @@ /******************************************************************************* * Constants and Macros ******************************************************************************/ -#define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF) -#define INT_STATUS_SW_CLEAR U(0xFFFFFFFF) -#define MAX_TIMEOUT_MS U(100) /* Timeout in 100ms */ -#define NUM_SE_REGS_TO_SAVE U(4) +#define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF) +#define INT_STATUS_SW_CLEAR U(0xFFFFFFFF) +#define MAX_TIMEOUT_MS U(1000) /* Max. timeout of 1s */ +#define NUM_SE_REGS_TO_SAVE U(4) -#define SE0_MAX_BUSY_TIMEOUT_MS U(100) /* 100ms Timeout Expired */ #define BYTES_IN_WORD U(4) #define SHA256_MAX_HASH_RESULT U(7) #define SHA256_DST_SIZE U(32) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 2d5f8e3c6..9a4d22e68 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -12,150 +12,6 @@ #include <tegra_platform.h> /******************************************************************************* - * Array to hold stream_id override config register offsets - ******************************************************************************/ -const static uint32_t tegra194_streamid_override_regs[] = { - MC_STREAMID_OVERRIDE_CFG_PTCR, - MC_STREAMID_OVERRIDE_CFG_HDAR, - MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD, - MC_STREAMID_OVERRIDE_CFG_SATAR, - MC_STREAMID_OVERRIDE_CFG_MPCORER, - MC_STREAMID_OVERRIDE_CFG_NVENCSWR, - MC_STREAMID_OVERRIDE_CFG_HDAW, - MC_STREAMID_OVERRIDE_CFG_MPCOREW, - MC_STREAMID_OVERRIDE_CFG_SATAW, - MC_STREAMID_OVERRIDE_CFG_ISPRA, - MC_STREAMID_OVERRIDE_CFG_ISPFALR, - MC_STREAMID_OVERRIDE_CFG_ISPWA, - MC_STREAMID_OVERRIDE_CFG_ISPWB, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR, - MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR, - MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW, - MC_STREAMID_OVERRIDE_CFG_TSECSRD, - MC_STREAMID_OVERRIDE_CFG_TSECSWR, - MC_STREAMID_OVERRIDE_CFG_SDMMCRA, - MC_STREAMID_OVERRIDE_CFG_SDMMCR, - MC_STREAMID_OVERRIDE_CFG_SDMMCRAB, - MC_STREAMID_OVERRIDE_CFG_SDMMCWA, - MC_STREAMID_OVERRIDE_CFG_SDMMCW, - MC_STREAMID_OVERRIDE_CFG_SDMMCWAB, - MC_STREAMID_OVERRIDE_CFG_VICSRD, - MC_STREAMID_OVERRIDE_CFG_VICSWR, - MC_STREAMID_OVERRIDE_CFG_VIW, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD, - MC_STREAMID_OVERRIDE_CFG_NVDECSWR, - MC_STREAMID_OVERRIDE_CFG_APER, - MC_STREAMID_OVERRIDE_CFG_APEW, - MC_STREAMID_OVERRIDE_CFG_NVJPGSRD, - MC_STREAMID_OVERRIDE_CFG_NVJPGSWR, - MC_STREAMID_OVERRIDE_CFG_SESRD, - MC_STREAMID_OVERRIDE_CFG_SESWR, - MC_STREAMID_OVERRIDE_CFG_AXIAPR, - MC_STREAMID_OVERRIDE_CFG_AXIAPW, - MC_STREAMID_OVERRIDE_CFG_ETRR, - MC_STREAMID_OVERRIDE_CFG_ETRW, - MC_STREAMID_OVERRIDE_CFG_TSECSRDB, - MC_STREAMID_OVERRIDE_CFG_TSECSWRB, - MC_STREAMID_OVERRIDE_CFG_AXISR, - MC_STREAMID_OVERRIDE_CFG_AXISW, - MC_STREAMID_OVERRIDE_CFG_EQOSR, - MC_STREAMID_OVERRIDE_CFG_EQOSW, - MC_STREAMID_OVERRIDE_CFG_UFSHCR, - MC_STREAMID_OVERRIDE_CFG_UFSHCW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR, - MC_STREAMID_OVERRIDE_CFG_BPMPR, - MC_STREAMID_OVERRIDE_CFG_BPMPW, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAR, - MC_STREAMID_OVERRIDE_CFG_BPMPDMAW, - MC_STREAMID_OVERRIDE_CFG_AONR, - MC_STREAMID_OVERRIDE_CFG_AONW, - MC_STREAMID_OVERRIDE_CFG_AONDMAR, - MC_STREAMID_OVERRIDE_CFG_AONDMAW, - MC_STREAMID_OVERRIDE_CFG_SCER, - MC_STREAMID_OVERRIDE_CFG_SCEW, - MC_STREAMID_OVERRIDE_CFG_SCEDMAR, - MC_STREAMID_OVERRIDE_CFG_SCEDMAW, - MC_STREAMID_OVERRIDE_CFG_APEDMAR, - MC_STREAMID_OVERRIDE_CFG_APEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1, - MC_STREAMID_OVERRIDE_CFG_VICSRD1, - MC_STREAMID_OVERRIDE_CFG_NVDECSRD1, - MC_STREAMID_OVERRIDE_CFG_VIFALR, - MC_STREAMID_OVERRIDE_CFG_VIFALW, - MC_STREAMID_OVERRIDE_CFG_DLA0RDA, - MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB, - MC_STREAMID_OVERRIDE_CFG_DLA0WRA, - MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB, - MC_STREAMID_OVERRIDE_CFG_DLA1RDA, - MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB, - MC_STREAMID_OVERRIDE_CFG_DLA1WRA, - MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB, - MC_STREAMID_OVERRIDE_CFG_PVA0RDA, - MC_STREAMID_OVERRIDE_CFG_PVA0RDB, - MC_STREAMID_OVERRIDE_CFG_PVA0RDC, - MC_STREAMID_OVERRIDE_CFG_PVA0WRA, - MC_STREAMID_OVERRIDE_CFG_PVA0WRB, - MC_STREAMID_OVERRIDE_CFG_PVA0WRC, - MC_STREAMID_OVERRIDE_CFG_PVA1RDA, - MC_STREAMID_OVERRIDE_CFG_PVA1RDB, - MC_STREAMID_OVERRIDE_CFG_PVA1RDC, - MC_STREAMID_OVERRIDE_CFG_PVA1WRA, - MC_STREAMID_OVERRIDE_CFG_PVA1WRB, - MC_STREAMID_OVERRIDE_CFG_PVA1WRC, - MC_STREAMID_OVERRIDE_CFG_RCER, - MC_STREAMID_OVERRIDE_CFG_RCEW, - MC_STREAMID_OVERRIDE_CFG_RCEDMAR, - MC_STREAMID_OVERRIDE_CFG_RCEDMAW, - MC_STREAMID_OVERRIDE_CFG_NVENC1SRD, - MC_STREAMID_OVERRIDE_CFG_NVENC1SWR, - MC_STREAMID_OVERRIDE_CFG_PCIE0R, - MC_STREAMID_OVERRIDE_CFG_PCIE0W, - MC_STREAMID_OVERRIDE_CFG_PCIE1R, - MC_STREAMID_OVERRIDE_CFG_PCIE1W, - MC_STREAMID_OVERRIDE_CFG_PCIE2AR, - MC_STREAMID_OVERRIDE_CFG_PCIE2AW, - MC_STREAMID_OVERRIDE_CFG_PCIE3R, - MC_STREAMID_OVERRIDE_CFG_PCIE3W, - MC_STREAMID_OVERRIDE_CFG_PCIE4R, - MC_STREAMID_OVERRIDE_CFG_PCIE4W, - MC_STREAMID_OVERRIDE_CFG_PCIE5R, - MC_STREAMID_OVERRIDE_CFG_PCIE5W, - MC_STREAMID_OVERRIDE_CFG_ISPFALW, - MC_STREAMID_OVERRIDE_CFG_DLA0RDA1, - MC_STREAMID_OVERRIDE_CFG_DLA1RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA0RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA0RDB1, - MC_STREAMID_OVERRIDE_CFG_PVA1RDA1, - MC_STREAMID_OVERRIDE_CFG_PVA1RDB1, - MC_STREAMID_OVERRIDE_CFG_PCIE5R1, - MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, - MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, - MC_STREAMID_OVERRIDE_CFG_ISPRA1, - MC_STREAMID_OVERRIDE_CFG_PCIE0R1, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1, - MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR, - MC_STREAMID_OVERRIDE_CFG_MIU0R, - MC_STREAMID_OVERRIDE_CFG_MIU0W, - MC_STREAMID_OVERRIDE_CFG_MIU1R, - MC_STREAMID_OVERRIDE_CFG_MIU1W, - MC_STREAMID_OVERRIDE_CFG_MIU2R, - MC_STREAMID_OVERRIDE_CFG_MIU2W, - MC_STREAMID_OVERRIDE_CFG_MIU3R, - MC_STREAMID_OVERRIDE_CFG_MIU3W, - MC_STREAMID_OVERRIDE_CFG_MIU4R, - MC_STREAMID_OVERRIDE_CFG_MIU4W, - MC_STREAMID_OVERRIDE_CFG_MIU5R, - MC_STREAMID_OVERRIDE_CFG_MIU5W, - MC_STREAMID_OVERRIDE_CFG_MIU6R, - MC_STREAMID_OVERRIDE_CFG_MIU6W, - MC_STREAMID_OVERRIDE_CFG_MIU7R, - MC_STREAMID_OVERRIDE_CFG_MIU7W -}; - -/******************************************************************************* * Array to hold the security configs for stream IDs ******************************************************************************/ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { @@ -571,8 +427,6 @@ static mc_regs_t *tegra194_get_mc_system_suspend_ctx(void) * Struct to hold the memory controller settings ******************************************************************************/ static tegra_mc_settings_t tegra194_mc_settings = { - .streamid_override_cfg = tegra194_streamid_override_regs, - .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), .streamid_security_cfg = tegra194_streamid_sec_cfgs, .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), .get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index d92025b8b..ce5815b46 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -368,7 +368,11 @@ int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) { + const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step; uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; + cpu_context_t *ctx = cm_get_context(NON_SECURE); + uint64_t actlr_elx; /* * Reset power state info for CPUs when onlining, we set @@ -377,6 +381,10 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) * will re-init this info from non-secure software when the * core come online. */ + actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1)); + actlr_elx &= ~DENVER_CPU_PMSTATE_MASK; + actlr_elx |= DENVER_CPU_PMSTATE_C1; + write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); /* * Check if we are exiting from deep sleep and restore SE @@ -446,13 +454,23 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) mmio_write_32(TEGRA_XUSB_PADCTL_BASE + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); } + } - /* - * Reset power state info for the last core doing SC7 - * entry and exit, we set deepest power state as CC7 - * and SC7 for SC7 entry which may not be requested by - * non-secure SW which controls idle states. - */ + /* + * Enable dual execution optimized translations for all ELx. + */ + if (enable_ccplex_lock_step != 0U) { + actlr_elx = read_actlr_el3(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3; + write_actlr_el3(actlr_elx); + + actlr_elx = read_actlr_el2(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2; + write_actlr_el2(actlr_elx); + + actlr_elx = read_actlr_el1(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1; + write_actlr_el1(actlr_elx); } return PSCI_E_SUCCESS; diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 235fba43c..82555403e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -201,6 +201,10 @@ void plat_enable_console(int32_t id) ******************************************************************************/ void plat_early_platform_setup(void) { + const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); + uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step; + uint64_t actlr_elx; + /* sanity check MCE firmware compatibility */ mce_verify_firmware_version(); @@ -250,6 +254,23 @@ void plat_early_platform_setup(void) mmio_write_32(TEGRA_XUSB_PADCTL_BASE + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); } + + /* + * Enable dual execution optimized translations for all ELx. + */ + if (enable_ccplex_lock_step != 0U) { + actlr_elx = read_actlr_el3(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3; + write_actlr_el3(actlr_elx); + + actlr_elx = read_actlr_el2(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2; + write_actlr_el2(actlr_elx); + + actlr_elx = read_actlr_el1(); + actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1; + write_actlr_el1(actlr_elx); + } } /* Secure IRQs for Tegra194 */ diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 33694a16d..884762de7 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -16,11 +16,13 @@ #include <common/runtime_svc.h> #include <tegra_private.h> #include <tegra_platform.h> +#include <smmu.h> #include <stdbool.h> /******************************************************************************* * Tegra194 SiP SMCs ******************************************************************************/ +#define TEGRA_SIP_GET_SMMU_PER 0xC200FF00U /******************************************************************************* * This function is responsible for handling all T194 SiP calls @@ -34,13 +36,43 @@ int32_t plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - int32_t ret = -ENOTSUP; + int32_t ret = 0; + uint32_t i, smmu_per[6] = {0}; + uint32_t num_smmu_devices = plat_get_num_smmu_devices(); + uint64_t per[3] = {0ULL}; - (void)smc_fid; (void)x1; (void)x4; (void)cookie; (void)flags; + switch (smc_fid) { + case TEGRA_SIP_GET_SMMU_PER: + + /* make sure we dont go past the array length */ + assert(num_smmu_devices <= ARRAY_SIZE(smmu_per)); + + /* read all supported SMMU_PER records */ + for (i = 0U; i < num_smmu_devices; i++) { + smmu_per[i] = tegra_smmu_read_32(i, SMMU_GSR0_PER); + } + + /* pack results into 3 64bit variables. */ + per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U); + per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U); + per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U); + + /* provide the results via X1-X3 CPU registers */ + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]); + + break; + + default: + ret = -ENOTSUP; + break; + } + return ret; } diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 78766fcbe..c02128ccc 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -24,12 +24,6 @@ COLD_BOOT_SINGLE_CPU := 1 TZDRAM_BASE := 0x40000000 $(eval $(call add_define,TZDRAM_BASE)) -PLATFORM_CLUSTER_COUNT := 4 -$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) - -PLATFORM_MAX_CPUS_PER_CLUSTER := 2 -$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) - MAX_XLAT_TABLES := 25 $(eval $(call add_define,MAX_XLAT_TABLES)) @@ -37,7 +31,8 @@ MAX_MMAP_REGIONS := 30 $(eval $(call add_define,MAX_MMAP_REGIONS)) # platform files -PLAT_INCLUDES += -I${SOC_DIR}/drivers/include +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \ + -I${SOC_DIR}/drivers/include BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c index 635018dbc..48608583d 100644 --- a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c +++ b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c @@ -927,17 +927,12 @@ static void tegra_se_enable_clocks(void) val &= ~ENTROPY_RESET_BIT; mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_W, val); - if (!tegra_chipid_is_t210_b01()) { - - /* - * T210 SE clock source is turned off in kernel, to simplify - * SE clock source setting, we switch SE clock source to - * CLK_M, SE_CLK_DIVISOR = 0. T210 B01 SE clock source is - * always on, so don't need this setting. - */ - mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE, - SE_CLK_SRC_CLK_M); - } + /* + * Switch SE clock source to CLK_M, to make sure SE clock + * is on when saving SE context + */ + mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE, + SE_CLK_SRC_CLK_M); /* Enable SE clock */ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V); diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c index f29e624ea..7f73ea506 100644 --- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -534,6 +534,13 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) } /* + * Mark this CPU as ON in the cpu_powergate_mask[], + * so that we use Flow Controller for all subsequent + * power ups. + */ + cpu_powergate_mask[plat_my_core_pos()] = 1; + + /* * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's * used for power management and boot purposes. Inform the BPMP that * we have completed the cluster power up. @@ -561,7 +568,6 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) /* Turn on CPU using flow controller or PMC */ if (cpu_powergate_mask[cpu] == 0) { tegra_pmc_cpu_on(cpu); - cpu_powergate_mask[cpu] = 1; } else { tegra_fc_cpu_on(cpu); } diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index ba827a073..14e3324a8 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -23,10 +23,10 @@ $(eval $(call add_define,MAX_XLAT_TABLES)) MAX_MMAP_REGIONS := 16 $(eval $(call add_define,MAX_MMAP_REGIONS)) -ENABLE_WDT_LEGACY_FIQ_HANDLING := 1 -$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING)) +ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1 -PLAT_INCLUDES += -I${SOC_DIR}/drivers/se +PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \ + -I${SOC_DIR}/drivers/se BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/cortex_a53.S \ diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index 4f8567979..27ddab0c8 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -87,4 +87,8 @@ void stm32mp_io_setup(void); */ int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer); +/* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */ +int stm32mp_map_ddr_non_cacheable(void); +int stm32mp_unmap_ddr(void); + #endif /* STM32MP_COMMON_H */ diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c index afa87f487..9af156457 100644 --- a/plat/st/common/stm32mp_common.c +++ b/plat/st/common/stm32mp_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,7 @@ #include <arch_helpers.h> #include <common/debug.h> #include <drivers/st/stm32mp_clkfunc.h> +#include <lib/xlat_tables/xlat_tables_v2.h> #include <plat/common/platform.h> uintptr_t plat_get_ns_image_entrypoint(void) @@ -151,3 +152,16 @@ int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) return 0; } + +int stm32mp_map_ddr_non_cacheable(void) +{ + return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, + STM32MP_DDR_MAX_SIZE, + MT_NON_CACHEABLE | MT_RW | MT_NS); +} + +int stm32mp_unmap_ddr(void) +{ + return mmap_remove_dynamic_region(STM32MP_DDR_BASE, + STM32MP_DDR_MAX_SIZE); +} diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c index 4fa796f0c..acb323cf2 100644 --- a/plat/st/common/stm32mp_dt.c +++ b/plat/st/common/stm32mp_dt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -92,6 +92,7 @@ uint8_t fdt_get_status(int node) return status; } +#if ENABLE_ASSERTIONS /******************************************************************************* * This function returns the address cells from the node parent. * Returns: @@ -100,7 +101,7 @@ uint8_t fdt_get_status(int node) * - a default value if undefined #address-cells property as per libfdt * implementation. ******************************************************************************/ -int fdt_get_node_parent_address_cells(int node) +static int fdt_get_node_parent_address_cells(int node) { int parent; @@ -120,7 +121,7 @@ int fdt_get_node_parent_address_cells(int node) * - a default value if undefined #size-cells property as per libfdt * implementation. ******************************************************************************/ -int fdt_get_node_parent_size_cells(int node) +static int fdt_get_node_parent_size_cells(int node) { int parent; @@ -131,6 +132,7 @@ int fdt_get_node_parent_size_cells(int node) return fdt_size_cells(fdt, parent); } +#endif /******************************************************************************* * This function reads a value of a node property (generic use of fdt @@ -467,7 +469,7 @@ uint32_t dt_get_pwr_vdd_voltage(void) } pwr_regulators_node = fdt_subnode_offset(fdt, node, "pwr-regulators"); - if (node < 0) { + if (pwr_regulators_node < 0) { INFO("%s: Cannot read pwr-regulators node in DT\n", __func__); return 0; } diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index 024dbe076..652765ce1 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -130,6 +130,7 @@ void bl2_el3_early_platform_setup(u_register_t arg0, void bl2_platform_setup(void) { int ret; + uint32_t ddr_ns_size; if (dt_pmic_status() > 0) { initialize_pmic(); @@ -141,8 +142,24 @@ void bl2_platform_setup(void) panic(); } + ddr_ns_size = stm32mp_get_ddr_ns_size(); + assert(ddr_ns_size > 0U); + + /* Map non secure DDR for BL33 load, now with cacheable attribute */ + ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, + ddr_ns_size, MT_MEMORY | MT_RW | MT_NS); + assert(ret == 0); + #ifdef AARCH32_SP_OPTEE INFO("BL2 runs OP-TEE setup\n"); + + /* Map secure DDR for OP-TEE paged area */ + ret = mmap_add_dynamic_region(STM32MP_DDR_BASE + ddr_ns_size, + STM32MP_DDR_BASE + ddr_ns_size, + STM32MP_DDR_S_SIZE, + MT_MEMORY | MT_RW | MT_SECURE); + assert(ret == 0); + /* Initialize tzc400 after DDR initialization */ stm32mp1_security_setup(); #else @@ -166,14 +183,6 @@ void bl2_el3_plat_arch_setup(void) MT_CODE | MT_SECURE); #ifdef AARCH32_SP_OPTEE - /* OP-TEE image needs post load processing: keep RAM read/write */ - mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() - - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE, - STM32MP_DDR_BASE + dt_get_ddr_size() - - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE, - STM32MP_DDR_S_SIZE, - MT_MEMORY | MT_RW | MT_SECURE); - mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, STM32MP_OPTEE_SIZE, MT_MEMORY | MT_RW | MT_SECURE); @@ -181,19 +190,12 @@ void bl2_el3_plat_arch_setup(void) /* Prevent corruption of preloaded BL32 */ mmap_add_region(BL32_BASE, BL32_BASE, BL32_LIMIT - BL32_BASE, - MT_MEMORY | MT_RO | MT_SECURE); - + MT_RO_DATA | MT_SECURE); #endif - /* Map non secure DDR for BL33 load and DDR training area restore */ - mmap_add_region(STM32MP_DDR_BASE, - STM32MP_DDR_BASE, - STM32MP_DDR_MAX_SIZE, - MT_MEMORY | MT_RW | MT_NS); - /* Prevent corruption of preloaded Device Tree */ mmap_add_region(DTB_BASE, DTB_BASE, DTB_LIMIT - DTB_BASE, - MT_MEMORY | MT_RO | MT_SECURE); + MT_RO_DATA | MT_SECURE); configure_mmu(); @@ -351,8 +353,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); assert(paged_mem_params != NULL); paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + - (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - - STM32MP_DDR_SHMEM_SIZE); + stm32mp_get_ddr_ns_size(); paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h index e38fca012..2da64acbc 100644 --- a/plat/st/stm32mp1/include/stm32mp1_private.h +++ b/plat/st/stm32mp1/include/stm32mp1_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,4 +21,5 @@ void stm32mp1_syscfg_init(void); void stm32mp1_syscfg_enable_io_compensation(void); void stm32mp1_syscfg_disable_io_compensation(void); +uint32_t stm32mp_get_ddr_ns_size(void); #endif /* STM32MP1_PRIVATE_H */ diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c index a52db6cac..6d7af741a 100644 --- a/plat/st/stm32mp1/plat_image_load.c +++ b/plat/st/stm32mp1/plat_image_load.c @@ -1,9 +1,11 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <platform_def.h> + #include <common/desc_image_load.h> #include <plat/common/platform.h> @@ -21,6 +23,13 @@ void plat_flush_next_bl_params(void) ******************************************************************************/ bl_load_info_t *plat_get_bl_image_load_info(void) { + bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID); + uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size(); + + /* Max size is non-secure DDR end address minus image_base */ + bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size - + bl33->image_info.image_base; + return get_bl_load_info_from_mem_params_desc(); } diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index bd1a16bf7..5ce7a9c4f 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -11,6 +11,11 @@ USE_COHERENT_MEM := 0 STM32_TF_VERSION ?= 0 +# Enable dynamic memory mapping +PLAT_XLAT_TABLES_DYNAMIC := 1 +$(eval $(call assert_boolean,PLAT_XLAT_TABLES_DYNAMIC)) +$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) + # Not needed for Cortex-A7 WORKAROUND_CVE_2017_5715:= 0 @@ -152,8 +157,6 @@ STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) STM32_TF_LINKERFILE := ${BUILD_PLAT}/stm32mp1.ld -BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 - # Variables for use with stm32image STM32IMAGEPATH ?= tools/stm32image STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT} diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 5dc520625..fc776ae8b 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,6 +62,9 @@ #ifdef AARCH32_SP_OPTEE #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ +#else +#define STM32MP_DDR_S_SIZE U(0) +#define STM32MP_DDR_SHMEM_SIZE U(0) #endif /* DDR power initializations */ diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index e2dcd2af7..ac4519575 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -365,3 +365,24 @@ uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) return BSEC_OK; } #endif + +/* Get the non-secure DDR size */ +uint32_t stm32mp_get_ddr_ns_size(void) +{ + static uint32_t ddr_ns_size; + uint32_t ddr_size; + + if (ddr_ns_size != 0U) { + return ddr_ns_size; + } + + ddr_size = dt_get_ddr_size(); + if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || + (ddr_size > STM32MP_DDR_MAX_SIZE)) { + panic(); + } + + ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); + + return ddr_ns_size; +} diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c index 61db2e7c7..3a29ba966 100644 --- a/plat/st/stm32mp1/stm32mp1_security.c +++ b/plat/st/stm32mp1/stm32mp1_security.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,29 +35,30 @@ static void init_tzc400(void) { unsigned long long region_base, region_top; unsigned long long ddr_base = STM32MP_DDR_BASE; - unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size(); - unsigned long long ddr_top = ddr_base + (ddr_size - 1U); + unsigned long long ddr_ns_size = + (unsigned long long)stm32mp_get_ddr_ns_size(); + unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U); tzc400_init(STM32MP1_TZC_BASE); tzc400_disable_filters(); -#ifdef AARCH32_SP_OPTEE /* * Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the * same configuration to all filters in the TZC. */ region_base = ddr_base; - region_top = ddr_top - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE; + region_top = ddr_ns_top; tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1, region_base, region_top, TZC_REGION_S_NONE, TZC_REGION_NSEC_ALL_ACCESS_RDWR); +#ifdef AARCH32_SP_OPTEE /* Region 2 set to cover all secure DRAM. */ region_base = region_top + 1U; - region_top = ddr_top - STM32MP_DDR_SHMEM_SIZE; + region_top += STM32MP_DDR_S_SIZE; tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 2, region_base, region_top, @@ -66,24 +67,12 @@ static void init_tzc400(void) /* Region 3 set to cover non-secure shared memory DRAM. */ region_base = region_top + 1U; - region_top = ddr_top; + region_top += STM32MP_DDR_SHMEM_SIZE; tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 3, region_base, region_top, TZC_REGION_S_NONE, TZC_REGION_NSEC_ALL_ACCESS_RDWR); -#else - /* - * Region 1 set to cover all DRAM at 0xC000_0000. Apply the - * same configuration to all filters in the TZC. - */ - region_base = ddr_base; - region_top = ddr_top; - tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1, - region_base, - region_top, - TZC_REGION_S_NONE, - TZC_REGION_NSEC_ALL_ACCESS_RDWR); #endif /* Raise an exception if a NS device tries to access secure memory */ diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c index 32ae8ecc9..ecac43522 100644 --- a/services/spd/tlkd/tlkd_main.c +++ b/services/spd/tlkd/tlkd_main.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -271,6 +272,9 @@ static uintptr_t tlkd_smc_handler(uint32_t smc_fid, case TLK_TA_LAUNCH_OP: case TLK_TA_SEND_EVENT: case TLK_RESUME_FID: + case TLK_SET_BL_VERSION: + case TLK_LOCK_BL_INTERFACE: + case TLK_BL_RPMB_SERVICE: if (!ns) SMC_RET1(handle, SMC_UNK); @@ -429,7 +433,6 @@ static uintptr_t tlkd_smc_handler(uint32_t smc_fid, */ case TLK_SUSPEND_DONE: case TLK_RESUME_DONE: - case TLK_SYSTEM_OFF_DONE: if (ns) SMC_RET1(handle, SMC_UNK); diff --git a/services/spd/tlkd/tlkd_pm.c b/services/spd/tlkd/tlkd_pm.c index 7d1959bce..ed5bf7761 100644 --- a/services/spd/tlkd/tlkd_pm.c +++ b/services/spd/tlkd/tlkd_pm.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -98,29 +99,6 @@ static void cpu_resume_handler(u_register_t suspend_level) } /******************************************************************************* - * System is about to be reset. Inform the SP to allow any book-keeping - ******************************************************************************/ -static void system_off_handler(void) -{ - int cpu = read_mpidr() & MPIDR_CPU_MASK; - gp_regs_t *gp_regs; - - /* TLK runs only on CPU0 */ - if (cpu != 0) - return; - - /* pass system off/reset events to TLK */ - gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); - write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_OFF); - - /* - * Enter the SP. We do not care about the return value because we - * must continue with the shutdown anyway. - */ - (void)tlkd_synchronous_sp_entry(&tlk_ctx); -} - -/******************************************************************************* * Structure populated by the Dispatcher to be given a chance to perform any * bookkeeping before PSCI executes a power mgmt. operation. ******************************************************************************/ @@ -128,6 +106,4 @@ const spd_pm_ops_t tlkd_pm_ops = { .svc_migrate_info = cpu_migrate_info, .svc_suspend = cpu_suspend_handler, .svc_suspend_finish = cpu_resume_handler, - .svc_system_off = system_off_handler, - .svc_system_reset = system_off_handler }; diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c index ba2f4a6e4..b10da7679 100644 --- a/services/spd/trusty/trusty.c +++ b/services/spd/trusty/trusty.c @@ -413,7 +413,7 @@ static int32_t trusty_setup(void) /* Get trusty's entry point info */ ep_info = bl31_plat_get_next_image_ep_info(SECURE); if (ep_info == NULL) { - INFO("Trusty image missing.\n"); + VERBOSE("Trusty image missing.\n"); return -1; } @@ -466,7 +466,7 @@ static int32_t trusty_setup(void) trusty_fiq_handler, flags); if (ret != 0) { - ERROR("trusty: failed to register fiq handler, ret = %d\n", ret); + VERBOSE("trusty: failed to register fiq handler, ret = %d\n", ret); } if (aarch32) { |