diff options
26 files changed, 508 insertions, 97 deletions
diff --git a/common/bl_common.c b/common/bl_common.c index 4e76dd3e6..61f031bfd 100644 --- a/common/bl_common.c +++ b/common/bl_common.c @@ -265,7 +265,7 @@ void bl_handle_pauth(void) * system registers. Pointer authentication can't be enabled here or the * authentication will fail when returning from this function. */ - assert(is_armv8_3_pauth_api_present()); + assert(is_armv8_3_pauth_apa_api_present()); uint64_t *apiakey = plat_init_apiakey(); diff --git a/docs/interrupt-framework-design.rst b/docs/interrupt-framework-design.rst index 52d1ed41b..58130cde0 100644 --- a/docs/interrupt-framework-design.rst +++ b/docs/interrupt-framework-design.rst @@ -89,8 +89,9 @@ incorrect as they conflict with the requirements mentioned in Section 1. The following sub-sections describe all the possible routing models and specify which ones are valid or invalid. EL3 interrupts are currently supported only for GIC version 3.0 (Arm GICv3) and only the Secure-EL1 and Non-secure interrupt -types are supported for GIC version 2.0 (Arm GICv2) (See 1.2). The terminology -used in the following sub-sections is explained below. +types are supported for GIC version 2.0 (Arm GICv2) (see `Assumptions in +Interrupt Management Framework`_). The terminology used in the following +sub-sections is explained below. #. **CSS**. Current Security State. ``0`` when secure and ``1`` when non-secure @@ -230,8 +231,8 @@ The framework makes the following assumptions to simplify its implementation. Both aspects of interrupt management involve various components in the secure software stack spanning from EL3 to Secure-EL1. These components are described -in the section 2.1. The framework stores information associated with each type -of interrupt in the following data structure. +in the section `Software components`_. The framework stores information +associated with each type of interrupt in the following data structure. .. code:: c @@ -244,11 +245,11 @@ of interrupt in the following data structure. The ``flags`` field stores the routing model for the interrupt type in bits[1:0]. Bit[0] stores the routing model when execution is in the secure state. Bit[1] stores the routing model when execution is in the non-secure -state. As mentioned in Section 1.2.2, a value of ``0`` implies that the interrupt -should be targeted to the FEL. A value of ``1`` implies that it should be targeted -to EL3. The remaining bits are reserved and SBZ. The helper macro -``set_interrupt_rm_flag()`` should be used to set the bits in the ``flags`` -parameter. +state. As mentioned in Section `Routing model`_, a value of ``0`` implies that +the interrupt should be targeted to the FEL. A value of ``1`` implies that it +should be targeted to EL3. The remaining bits are reserved and SBZ. The helper +macro ``set_interrupt_rm_flag()`` should be used to set the bits in the +``flags`` parameter. The ``scr_el3[2]`` field also stores the routing model but as a mapping of the model in the ``flags`` field to the corresponding bit in the ``SCR_EL3`` for each @@ -302,8 +303,9 @@ briefly described below. Interrupt registration ---------------------- -This section describes in detail the role of each software component (see 2.1) -during the registration of a handler for an interrupt type. +This section describes in detail the role of each software component (see +`Software components`_) during the registration of a handler for an interrupt +type. EL3 runtime firmware ~~~~~~~~~~~~~~~~~~~~ @@ -395,6 +397,8 @@ runtime firmware is responsible for programming the routing model. The SPD is responsible for ensuring that the routing model has been adhered to upon receiving an interrupt. +.. _spd-int-registration: + Secure payload dispatcher ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -487,6 +491,8 @@ requirements mentioned earlier. if (rc) panic(); +.. _sp-int-registration: + Secure payload ~~~~~~~~~~~~~~ @@ -512,10 +518,10 @@ The interrupt handling framework implemented by the SP should support one or both these interrupt handling models depending upon the chosen routing model. The following list briefly describes how the choice of a valid routing model -(See 1.2.3) effects the implementation of the Secure-EL1 IHF. If the choice of -the interrupt routing model is not known to the SPD service at compile time, -then the SP should pass this information to the SPD service at runtime during -its initialisation phase. +(see `Valid routing models`_) effects the implementation of the Secure-EL1 +IHF. If the choice of the interrupt routing model is not known to the SPD +service at compile time, then the SP should pass this information to the SPD +service at runtime during its initialisation phase. As mentioned earlier, an Arm GICv2 system is considered and it is assumed that the FIQ signal is used to generate Secure-EL1 interrupts and the IRQ signal @@ -584,7 +590,10 @@ Test secure payload behavior ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is -described in Section 2.2.2. It is known to the TSPD service at build time. +described in Section `Secure Payload Dispatcher`__. It is known to the TSPD +service at build time. + +.. __: #spd-int-registration The TSP implements an entrypoint (``tsp_sel1_intr_entry()``) for handling Secure-EL1 interrupts taken in non-secure state and routed through the TSPD service @@ -599,13 +608,14 @@ VBAR_EL1. It caters for the asynchronous handling model. The TSP also programs the Secure Physical Timer in the Arm Generic Timer block to raise a periodic interrupt (every half a second) for the purpose of testing -interrupt management across all the software components listed in 2.1 +interrupt management across all the software components listed in `Software +components`_. Interrupt handling ------------------ This section describes in detail the role of each software component (see -Section 2.1) in handling an interrupt of a particular type. +Section `Software components`_) in handling an interrupt of a particular type. EL3 runtime firmware ~~~~~~~~~~~~~~~~~~~~ @@ -769,7 +779,7 @@ invoked. will be trashed, which is the ``ELR_EL3`` and ``SPSR_EL3``, in order to be able to re-enter TSP for Secure-EL1 interrupt processing. It does not need to save any other secure context since the TSP is expected to preserve it - (see Section 2.2.2.1). + (see section `Test secure payload dispatcher behavior`_). #. It restores the system register context for the secure state by calling ``cm_el1_sysregs_context_restore(SECURE);``. @@ -823,21 +833,21 @@ interrupt may preempt Secure execution. It should be noted that while TSP is preempted, the TSPD only allows entry into the TSP either for Secure-EL1 interrupt handling or for resuming the preempted ``yielding`` SMC in response to the ``TSP_FID_RESUME`` SMC from the normal world. -(See Section 3). - -The non-secure interrupt triggered in Secure-EL1 during ``yielding`` SMC processing -can be routed to either EL3 or Secure-EL1 and is controlled by build option -``TSP_NS_INTR_ASYNC_PREEMPT`` (see Section 2.2.2.1). If the build option is set, -the TSPD will set the routing model for the non-secure interrupt to be routed to -EL3 from secure state i.e. **TEL3=1, CSS=0** and registers -``tspd_ns_interrupt_handler()`` as the non-secure interrupt handler. The -``tspd_ns_interrupt_handler()`` on being invoked ensures that the interrupt -originated from the secure state and disables routing of non-secure interrupts -from secure state to EL3. This is to prevent further preemption (by a non-secure -interrupt) when TSP is reentered for handling Secure-EL1 interrupts that -triggered while execution was in the normal world. The -``tspd_ns_interrupt_handler()`` then invokes ``tspd_handle_sp_preemption()`` for -further handling. +(See Section `Implication of preempted SMC on Non-Secure Software`_). + +The non-secure interrupt triggered in Secure-EL1 during ``yielding`` SMC +processing can be routed to either EL3 or Secure-EL1 and is controlled by build +option ``TSP_NS_INTR_ASYNC_PREEMPT`` (see Section `Test secure payload +dispatcher behavior`_). If the build option is set, the TSPD will set the +routing model for the non-secure interrupt to be routed to EL3 from secure state +i.e. **TEL3=1, CSS=0** and registers ``tspd_ns_interrupt_handler()`` as the +non-secure interrupt handler. The ``tspd_ns_interrupt_handler()`` on being +invoked ensures that the interrupt originated from the secure state and disables +routing of non-secure interrupts from secure state to EL3. This is to prevent +further preemption (by a non-secure interrupt) when TSP is reentered for +handling Secure-EL1 interrupts that triggered while execution was in the normal +world. The ``tspd_ns_interrupt_handler()`` then invokes +``tspd_handle_sp_preemption()`` for further handling. If the ``TSP_NS_INTR_ASYNC_PREEMPT`` build option is zero (default), the default routing model for non-secure interrupt in secure state is in effect @@ -866,10 +876,11 @@ invoked: #. ``SMC_PREEMPTED`` is set in x0 and return to non secure state after restoring non secure context. -The Normal World is expected to resume the TSP after the ``yielding`` SMC preemption -by issuing an SMC with ``TSP_FID_RESUME`` as the function identifier (see section 3). -The TSPD service takes the following actions in ``tspd_smc_handler()`` function -upon receiving this SMC: +The Normal World is expected to resume the TSP after the ``yielding`` SMC +preemption by issuing an SMC with ``TSP_FID_RESUME`` as the function identifier +(see section `Implication of preempted SMC on Non-Secure Software`_). The TSPD +service takes the following actions in ``tspd_smc_handler()`` function upon +receiving this SMC: #. It ensures that the call originated from the non secure state. An assertion is raised otherwise. @@ -898,16 +909,18 @@ Secure payload The SP should implement one or both of the synchronous and asynchronous interrupt handling models depending upon the interrupt routing model it has -chosen (as described in 2.2.3). +chosen (as described in section `Secure Payload`__). + +.. __: #sp-int-registration In the synchronous model, it should begin handling a Secure-EL1 interrupt after receiving control from the SPD service at an entrypoint agreed upon during build time or during the registration phase. Before handling the interrupt, the SP should save any Secure-EL1 system register context which is needed for resuming -normal execution in the SP later e.g. ``SPSR_EL1,``\ ELR_EL1\`. After handling the -interrupt, the SP could return control back to the exception level and security -state where the interrupt was originally taken from. The SP should use an SMC32 -or SMC64 to ask the SPD service to do this. +normal execution in the SP later e.g. ``SPSR_EL1``, ``ELR_EL1``. After handling +the interrupt, the SP could return control back to the exception level and +security state where the interrupt was originally taken from. The SP should use +an SMC32 or SMC64 to ask the SPD service to do this. In the asynchronous model, the Secure Payload is responsible for handling non-secure and Secure-EL1 interrupts at the IRQ and FIQ vectors in its exception @@ -922,8 +935,9 @@ Test secure payload behavior The TSPD hands control of a Secure-EL1 interrupt to the TSP at the ``tsp_sel1_intr_entry()``. The TSP handles the interrupt while ensuring that the -handover agreement described in Section 2.2.2.1 is maintained. It updates some -statistics by calling ``tsp_update_sync_sel1_intr_stats()``. It then calls +handover agreement described in Section `Test secure payload dispatcher +behavior`_ is maintained. It updates some statistics by calling +``tsp_update_sync_sel1_intr_stats()``. It then calls ``tsp_common_int_handler()`` which. #. Checks whether the interrupt is the secure physical timer interrupt. It @@ -947,18 +961,19 @@ The TSP handles interrupts under the asynchronous model as follows. #. Secure-EL1 interrupts are handled by calling the ``tsp_common_int_handler()`` function. The function has been described above. -#. Non-secure interrupts are handled by by calling the ``tsp_common_int_handler()`` +#. Non-secure interrupts are handled by calling the ``tsp_common_int_handler()`` function which ends up invoking ``tsp_handle_preemption()`` and issuing an SMC64 with ``TSP_PREEMPTED`` as the function identifier. Execution resumes at - the instruction that follows this SMC instruction when the TSPD hands - control to the TSP in response to an SMC with ``TSP_FID_RESUME`` as the - function identifier from the non-secure state (see section 2.3.2.4). + the instruction that follows this SMC instruction when the TSPD hands control + to the TSP in response to an SMC with ``TSP_FID_RESUME`` as the function + identifier from the non-secure state (see section `Test secure payload + dispatcher non-secure interrupt handling`_). -#. .. rubric:: Other considerations - :name: other-considerations +Other considerations +-------------------- Implication of preempted SMC on Non-Secure Software ---------------------------------------------------- +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A ``yielding`` SMC call to Secure payload can be preempted by a non-secure interrupt and the execution can return to the non-secure world for handling @@ -1001,7 +1016,7 @@ TSP by returning ``SMC_UNK`` error. -------------- -*Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* .. _Porting Guide: ./porting-guide.rst .. _SMC calling convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c index d7f088094..d85e4a51b 100644 --- a/drivers/renesas/rcar/pwrc/pwrc.c +++ b/drivers/renesas/rcar/pwrc/pwrc.c @@ -309,7 +309,7 @@ void rcar_pwrc_clusteroff(uint64_t mpidr) c = rcar_pwrc_get_mpidr_cluster(mpidr); dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR; - if (RCAR_PRODUCT_M3 == product && cut <= RCAR_M3_CUT_VER11) + if (RCAR_PRODUCT_M3 == product && cut < RCAR_CUT_VER30) goto done; if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20) @@ -383,7 +383,7 @@ static void __attribute__ ((section(".system_ram"))) product = reg & RCAR_PRODUCT_MASK; cut = reg & RCAR_CUT_MASK; - if (product == RCAR_PRODUCT_M3) + if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30) goto self_refresh; if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20) @@ -450,7 +450,7 @@ self_refresh: mmio_write_32(DBSC4_REG_DBRFEN, 0U); rcar_micro_delay(1U); - if (product == RCAR_PRODUCT_M3) + if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30) return; if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index f4bfdde1c..f88de8301 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -2094,7 +2094,9 @@ static void dbsc_regset(void) /* DBTR16 */ /* WDQL : tphy_wrlat + tphy_wrdata */ tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); - /* DQENLTNCY : tphy_wrlat = WL-2 */ + /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0 + * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0 + */ tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); /* DQL : tphy_rdlat + trdata_en */ /* it is not important for dbsc */ @@ -2417,7 +2419,7 @@ static void dbsc_regset_post(void) /* periodic dram zqcal and phy ctrl update enable */ mmio_write_32(DBSC_DBCALCNF, 0x01000010); if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) { + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { #if RCAR_DRAM_SPLIT == 2 @@ -4216,7 +4218,7 @@ int32_t rcar_dram_init(void) } if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) { + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); @@ -4351,7 +4353,7 @@ int32_t rcar_dram_init(void) foreach_vch(ch) mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) { + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index 8040d939b..43978c26c 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#define BOARDNUM 18 +#define BOARDNUM 19 #define BOARD_JUDGE_AUTO #ifdef BOARD_JUDGE_AUTO @@ -1322,7 +1322,58 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} } } - } + }, +/* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */ + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0x04}, + 0x00543210, + 0x3201, + {0x70612543, 0x43251670, 0x45326170, 0x10672534}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0x04}, + 0x00543210, + 0x2310, + {0x01327654, 0x34526107, 0x35421670, 0x70615324}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, }; void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div) @@ -1567,9 +1618,12 @@ static uint32_t _board_judge(void) } else if (Prr_Product == PRR_PRODUCT_M3N) { /* RENESAS SALVATOR-X (M3-N/SIP) */ brd = 11; - } else if (Prr_Product == PRR_PRODUCT_M3) { + } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W/SIP) */ brd = 0; + } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) { + /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ + brd = 18; } } #endif diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index d72959b32..6a3d1c078 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_DDR_VERSION "rev.0.34" +#define RCAR_DDR_VERSION "rev.0.35rc01" #define DRAM_CH_CNT (0x04) #define SLICE_CNT (0x04) #define CS_CNT (0x02) diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c index 2f62bb290..e33005f5e 100644 --- a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c +++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c @@ -1396,6 +1396,10 @@ void pfc_init_h3_v1(void) mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); +#if (RCAR_GEN3_ULCB == 1) + mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU); +#else mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); +#endif mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); } diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c index 116fd82ca..fd9be5980 100644 --- a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c +++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c @@ -1444,6 +1444,10 @@ void pfc_init_h3_v2(void) mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); +#if (RCAR_GEN3_ULCB == 1) + mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU); +#else mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); +#endif mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); } diff --git a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c index fc12cd6ed..3bb560ffa 100644 --- a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c +++ b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c @@ -1526,6 +1526,10 @@ void pfc_init_m3(void) mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); +#if (RCAR_GEN3_ULCB == 1) + mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU); +#else mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); +#endif mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); } diff --git a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c index 07f08fa0d..408d8793f 100644 --- a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c +++ b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c @@ -1432,6 +1432,10 @@ void pfc_init_m3n(void) mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); +#if (RCAR_GEN3_ULCB == 1) + mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU); +#else mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); +#endif mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); } diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c new file mode 100644 index 000000000..319e3934e --- /dev/null +++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <common/debug.h> + +#include "../qos_common.h" +#include "../qos_reg.h" +#include "qos_init_m3_v30.h" + +#define RCAR_QOS_VERSION "rev.0.1" + +#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U) +#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U) + +#define QOSWT_TIME_BANK0 (20000000U) //unit:ns + +#define QOSWT_WTEN_ENABLE (0x1U) + +#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 (SL_INIT_SSLOTCLK_M3_30 - 0x5U) + +#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U) +#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U) +#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) +#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT)) + +#define QOSWT_WTSET0_REQ_SSLOT0 (5U) +#define WT_BASE_SUB_SLOT_NUM0 (12U) +#define QOSWT_WTSET0_PERIOD0_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U) +#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U) +#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U) + +#define QOSWT_WTSET1_PERIOD1_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U) +#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U) +#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U) + +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT + +/* Same as M3 Ver.1.1 default setting */ +#if RCAR_REF_INT == RCAR_REF_DEFAULT +#include "qos_init_m3_v11_mstat195.h" +#else +#include "qos_init_m3_v11_mstat390.h" +#endif + +#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE + +/* Same as M3 Ver.1.1 default setting */ +#if RCAR_REF_INT == RCAR_REF_DEFAULT +#include "qos_init_m3_v11_qoswt195.h" +#else +#include "qos_init_m3_v11_qoswt390.h" +#endif + +#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ +#endif + +static void dbsc_setting(void) +{ + uint32_t md=0; + + /* Register write enable */ + io_write_32(DBSC_DBSYSCNT0, 0x00001234U); + + /* BUFCAM settings */ + io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1 + io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2 + io_write_32(DBSC_DBCAM0CNF3, 0x00000000); //dbcam0cnf3 + io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0 + io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0 + io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0 + + md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17; + + switch (md) { + case 0x0: + /* DDR3200 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) + /* DDR2800 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) + /* DDR2400 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) + /* DDR1600 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + } + + /* QoS Settings */ + io_write_32(DBSC_DBSCHQOS00, 0x00000F00); + io_write_32(DBSC_DBSCHQOS01, 0x00000B00); + io_write_32(DBSC_DBSCHQOS02, 0x00000000); + io_write_32(DBSC_DBSCHQOS03, 0x00000000); + io_write_32(DBSC_DBSCHQOS40, 0x00000300); + io_write_32(DBSC_DBSCHQOS41, 0x000002F0); + io_write_32(DBSC_DBSCHQOS42, 0x00000200); + io_write_32(DBSC_DBSCHQOS43, 0x00000100); + io_write_32(DBSC_DBSCHQOS90, 0x00000100); + io_write_32(DBSC_DBSCHQOS91, 0x000000F0); + io_write_32(DBSC_DBSCHQOS92, 0x000000A0); + io_write_32(DBSC_DBSCHQOS93, 0x00000040); + io_write_32(DBSC_DBSCHQOS120, 0x00000040); + io_write_32(DBSC_DBSCHQOS121, 0x00000030); + io_write_32(DBSC_DBSCHQOS122, 0x00000020); + io_write_32(DBSC_DBSCHQOS123, 0x00000010); + io_write_32(DBSC_DBSCHQOS130, 0x00000100); + io_write_32(DBSC_DBSCHQOS131, 0x000000F0); + io_write_32(DBSC_DBSCHQOS132, 0x000000A0); + io_write_32(DBSC_DBSCHQOS133, 0x00000040); + io_write_32(DBSC_DBSCHQOS140, 0x000000C0); + io_write_32(DBSC_DBSCHQOS141, 0x000000B0); + io_write_32(DBSC_DBSCHQOS142, 0x00000080); + io_write_32(DBSC_DBSCHQOS143, 0x00000040); + io_write_32(DBSC_DBSCHQOS150, 0x00000040); + io_write_32(DBSC_DBSCHQOS151, 0x00000030); + io_write_32(DBSC_DBSCHQOS152, 0x00000020); + io_write_32(DBSC_DBSCHQOS153, 0x00000010); + + /* Register write protect */ + io_write_32(DBSC_DBSYSCNT0, 0x00000000U); +} + +void qos_init_m3_v30(void) +{ + dbsc_setting(); + + /* DRAM Split Address mapping */ +#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH + #if RCAR_LSI == RCAR_M3 + #error "Don't set DRAM Split 4ch(M3)" + #else + ERROR("DRAM Split 4ch not supported.(M3)"); + panic(); + #endif +#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ + (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) + NOTICE("BL2: DRAM Split is 2ch\n"); + io_write_32(AXI_ADSPLCR0, 0x00000000U); + io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1DU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR2, 0x00001004U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#else + NOTICE("BL2: DRAM Split is OFF\n"); +#endif + +#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT + NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); +#endif + +#if RCAR_REF_INT == RCAR_REF_DEFAULT + NOTICE("BL2: DRAM refresh interval 1.95 usec\n"); +#else + NOTICE("BL2: DRAM refresh interval 3.9 usec\n"); +#endif + +#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE + NOTICE("BL2: Periodic Write DQ Training\n"); +#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + + io_write_32(QOSCTRL_RAS, 0x00000044U); + io_write_64(QOSCTRL_DANN, 0x0404020002020201UL); + io_write_32(QOSCTRL_DANT, 0x0020100AU); + io_write_32(QOSCTRL_FSS, 0x0000000AU); + io_write_32(QOSCTRL_INSFC, 0x06330001U); + io_write_32(QOSCTRL_EARLYR, 0x00000001U); + io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */ + + /* GPU Boost Mode */ + io_write_32(QOSCTRL_STATGEN0, 0x00000001U); + + io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30); + io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16))); + + { + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { + io_write_64(QOSBW_FIX_QOS_BANK0 + i*8, + mstat_fix[i]); + io_write_64(QOSBW_FIX_QOS_BANK1 + i*8, + mstat_fix[i]); + } + for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { + io_write_64(QOSBW_BE_QOS_BANK0 + i*8, + mstat_be[i]); + io_write_64(QOSBW_BE_QOS_BANK1 + i*8, + mstat_be[i]); + } +#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE + for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { + io_write_64(QOSWT_FIX_WTQOS_BANK0 + i*8, + qoswt_fix[i]); + io_write_64(QOSWT_FIX_WTQOS_BANK1 + i*8, + qoswt_fix[i]); + } + for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { + io_write_64(QOSWT_BE_WTQOS_BANK0 + i*8, + qoswt_be[i]); + io_write_64(QOSWT_BE_WTQOS_BANK1 + i*8, + qoswt_be[i]); + } +#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + } + + /* RT bus Leaf setting */ + io_write_32(RT_ACT0, 0x00000000U); + io_write_32(RT_ACT1, 0x00000000U); + + /* CCI bus Leaf setting */ + io_write_32(CPU_ACT0, 0x00000003U); + io_write_32(CPU_ACT1, 0x00000003U); + io_write_32(CPU_ACT2, 0x00000003U); + io_write_32(CPU_ACT3, 0x00000003U); + + io_write_32(QOSCTRL_RAEN, 0x00000001U); + +#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE + /* re-write training setting */ + io_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN)); + io_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_M3_30 << 16) | (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0)); + io_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_M3_30 << 16) | (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1)); + + io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE); +#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + + io_write_32(QOSCTRL_STATQC, 0x00000001U); +#else + NOTICE("BL2: QoS is None\n"); + + io_write_32(QOSCTRL_RAEN, 0x00000001U); +#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ +} diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.h b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.h new file mode 100644 index 000000000..a89d51252 --- /dev/null +++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef QOS_INIT_H_M3_V30__ +#define QOS_INIT_H_M3_V30__ + +void qos_init_m3_v30(void); + +#endif /* QOS_INIT_H_M3_V30__ */ diff --git a/drivers/staging/renesas/rcar/qos/qos.mk b/drivers/staging/renesas/rcar/qos/qos.mk index 153d1d817..9fabc56f8 100644 --- a/drivers/staging/renesas/rcar/qos/qos.mk +++ b/drivers/staging/renesas/rcar/qos/qos.mk @@ -12,6 +12,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO}) BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c + BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_H3}) @@ -26,6 +27,7 @@ else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_M3}) BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c + BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c endif ifeq (${RCAR_LSI},${RCAR_M3N}) BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c @@ -61,9 +63,13 @@ else BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c else ifeq (${LSI_CUT},11) BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c - else -# LSI_CUT 11 or later + else ifeq (${LSI_CUT},13) BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c + else ifeq (${LSI_CUT},30) + BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c + else +# LSI_CUT 30 or later + BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c endif endif ifeq (${RCAR_LSI},${RCAR_M3N}) diff --git a/drivers/staging/renesas/rcar/qos/qos_common.h b/drivers/staging/renesas/rcar/qos/qos_common.h index 9bad424fb..89dcf06d6 100644 --- a/drivers/staging/renesas/rcar/qos/qos_common.h +++ b/drivers/staging/renesas/rcar/qos/qos_common.h @@ -78,12 +78,16 @@ /* define used for M3 */ #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ #define SUB_SLOT_CYCLE_M3_11 (0x84U) /* 132 */ +#define SUB_SLOT_CYCLE_M3_30 (0x84U) /* 132 */ #else /* REF 3.9usec */ #define SUB_SLOT_CYCLE_M3_11 (0x108U) /* 264 */ +#define SUB_SLOT_CYCLE_M3_30 (0x108U) /* 264 */ #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ #define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U) +#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 -1U) #define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ +#define QOSWT_WTSET0_CYCLE_M3_30 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ #endif #define OPERATING_FREQ (400U) /* MHz */ diff --git a/drivers/staging/renesas/rcar/qos/qos_init.c b/drivers/staging/renesas/rcar/qos/qos_init.c index be4487aa3..affd42502 100644 --- a/drivers/staging/renesas/rcar/qos/qos_init.c +++ b/drivers/staging/renesas/rcar/qos/qos_init.c @@ -18,6 +18,7 @@ #include "H3/qos_init_h3_v30.h" #include "M3/qos_init_m3_v10.h" #include "M3/qos_init_m3_v11.h" +#include "M3/qos_init_m3_v30.h" #include "M3N/qos_init_m3n_v10.h" #endif #if RCAR_LSI == RCAR_H3 /* H3 */ @@ -32,6 +33,7 @@ #if RCAR_LSI == RCAR_M3 /* M3 */ #include "M3/qos_init_m3_v10.h" #include "M3/qos_init_m3_v11.h" +#include "M3/qos_init_m3_v30.h" #endif #if RCAR_LSI == RCAR_M3N /* M3N */ #include "M3N/qos_init_m3n_v10.h" @@ -51,6 +53,7 @@ #define PRR_PRODUCT_10 (0x00U) #define PRR_PRODUCT_11 (0x01U) #define PRR_PRODUCT_20 (0x10U) +#define PRR_PRODUCT_21 (0x11U) #define PRR_PRODUCT_30 (0x20U) #if !(RCAR_LSI == RCAR_E3) @@ -127,10 +130,13 @@ void rcar_qos_init(void) case PRR_PRODUCT_10: qos_init_m3_v10(); break; - case PRR_PRODUCT_20: /* M3 Cut 11 */ - default: + case PRR_PRODUCT_21: /* M3 Cut 13 */ qos_init_m3_v11(); break; + case PRR_PRODUCT_30: /* M3 Cut 30 */ + default: + qos_init_m3_v30(); + break; } #else PRR_PRODUCT_ERR(reg); @@ -210,13 +216,27 @@ void rcar_qos_init(void) PRR_PRODUCT_ERR(reg); } qos_init_m3_v10(); +#elif RCAR_LSI_CUT == RCAR_CUT_11 + /* M3 Cut 11 */ + if ((PRR_PRODUCT_M3 | PRR_PRODUCT_20) + != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + qos_init_m3_v11(); +#elif RCAR_LSI_CUT == RCAR_CUT_13 + /* M3 Cut 13 */ + if ((PRR_PRODUCT_M3 | PRR_PRODUCT_21) + != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + qos_init_m3_v11(); #else - /* M3 Cut 11 or later */ + /* M3 Cut 30 or later */ if ((PRR_PRODUCT_M3) != (reg & (PRR_PRODUCT_MASK))) { PRR_PRODUCT_ERR(reg); } - qos_init_m3_v11(); + qos_init_m3_v30(); #endif #elif RCAR_LSI == RCAR_M3N /* M3N */ /* M3N Cut 10 or later */ @@ -277,6 +297,8 @@ uint32_t get_refperiod(void) case PRR_PRODUCT_10: break; case PRR_PRODUCT_20: /* M3 Cut 11 */ + case PRR_PRODUCT_21: /* M3 Cut 13 */ + case PRR_PRODUCT_30: /* M3 Cut 30 */ default: refperiod = REFPERIOD_CYCLE; break; @@ -308,7 +330,9 @@ uint32_t get_refperiod(void) #if RCAR_LSI_CUT == RCAR_CUT_10 /* M3 Cut 10 */ #else - /* M3 Cut 11 or later */ + /* M3 Cut 11 */ + /* M3 Cut 13 */ + /* M3 Cut 30 or later */ refperiod = REFPERIOD_CYCLE; #endif #elif RCAR_LSI == RCAR_M3N /* for M3N */ diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 495ecb3a2..6af1d0397 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -34,10 +34,12 @@ static inline bool is_armv8_3_pauth_present(void) return (read_id_aa64isar1_el1() & mask) != 0U; } -static inline bool is_armv8_3_pauth_api_present(void) +static inline bool is_armv8_3_pauth_apa_api_present(void) { - return ((read_id_aa64isar1_el1() >> ID_AA64ISAR1_API_SHIFT) & - ID_AA64ISAR1_API_MASK) != 0U; + uint64_t mask = (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | + (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); + + return (read_id_aa64isar1_el1() & mask) != 0U; } static inline bool is_armv8_4_ttst_present(void) diff --git a/maintainers.rst b/maintainers.rst index 9f38b3341..a1ad137fe 100644 --- a/maintainers.rst +++ b/maintainers.rst @@ -188,6 +188,8 @@ Renesas rcar-gen3 platform port ------------------------------- :M: Jorge Ramirez-Ortiz <jramirez@baylibre.com> :G: `ldts`_ +:M: Marek Vasut <marek.vasut@gmail.com> +:G: `marex`_ :F: docs/plat/rcar-gen3.rst :F: plat/renesas/rcar :F: drivers/renesas/rcar @@ -263,6 +265,7 @@ Xilinx platform port .. _JackyBai: https://github.com/JackyBai .. _jenswi-linaro: https://github.com/jenswi-linaro .. _ldts: https://github.com/ldts +.. _marex: https://github.com/marex .. _niej: https://github.com/niej .. _kostapr: https://github.com/kostapr .. _masahir0y: https://github.com/masahir0y diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h index e9b96dd46..c75f2132b 100644 --- a/plat/arm/css/sgi/include/sgi_variant.h +++ b/plat/arm/css/sgi/include/sgi_variant.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,9 +10,9 @@ /* SSC_VERSION values for SGI575 */ #define SGI575_SSC_VER_PART_NUM 0x0783 -/* SID Version values for SGI-Clark */ -#define SGI_CLARK_SID_VER_PART_NUM 0x0786 -#define SGI_CLARK_HELIOS_CONFIG_ID 0x2 +/* SID Version values for RD-N1E1-Edge */ +#define RD_N1E1_EDGE_SID_VER_PART_NUM 0x0786 +#define RD_E1_EDGE_CONFIG_ID 0x2 /* Structure containing SGI platform variant information */ typedef struct sgi_platform_info { diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c index bfcb521a3..8fa5b01b2 100644 --- a/plat/arm/css/sgi/sgi_bl31_setup.c +++ b/plat/arm/css/sgi/sgi_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ static scmi_channel_plat_info_t sgi575_scmi_plat_info = { .ring_doorbell = &mhu_ring_doorbell, }; -static scmi_channel_plat_info_t sgi_clark_scmi_plat_info = { +static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info = { .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), .db_preserve_mask = 0xfffffffe, @@ -37,8 +37,8 @@ static scmi_channel_plat_info_t sgi_clark_scmi_plat_info = { scmi_channel_plat_info_t *plat_css_get_scmi_info() { - if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM) - return &sgi_clark_scmi_plat_info; + if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) + return &rd_n1e1_edge_scmi_plat_info; else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) return &sgi575_scmi_plat_info; else @@ -65,9 +65,9 @@ void bl31_platform_setup(void) const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) { - /* For SGI-Clark.Helios platform only CPU ON/OFF is supported */ - if ((sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM) && - (sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID)) { + /* For RD-E1-Edge platform only CPU ON/OFF is supported */ + if ((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) && + (sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) { ops->cpu_standby = NULL; ops->system_off = NULL; ops->system_reset = NULL; diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c index dafaf40bf..f9dbdefe9 100644 --- a/plat/arm/css/sgi/sgi_topology.c +++ b/plat/arm/css/sgi/sgi_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,8 +21,8 @@ const unsigned char sgi_pd_tree_desc[] = { CSS_SGI_MAX_CPUS_PER_CLUSTER }; -/* SGI-Clark.Helios platform consists of 16 physical CPUS and 32 threads */ -const unsigned char sgi_clark_helios_pd_tree_desc[] = { +/* RD-E1-Edge platform consists of 16 physical CPUS and 32 threads */ +const unsigned char rd_e1_edge_pd_tree_desc[] = { PLAT_ARM_CLUSTER_COUNT, CSS_SGI_MAX_CPUS_PER_CLUSTER, CSS_SGI_MAX_CPUS_PER_CLUSTER, @@ -49,9 +49,9 @@ const unsigned char sgi_clark_helios_pd_tree_desc[] = { ******************************************************************************/ const unsigned char *plat_get_power_domain_tree_desc(void) { - if (sgi_plat_info.platform_id == SGI_CLARK_SID_VER_PART_NUM && - sgi_plat_info.config_id == SGI_CLARK_HELIOS_CONFIG_ID) - return sgi_clark_helios_pd_tree_desc; + if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM && + sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID) + return rd_e1_edge_pd_tree_desc; else return sgi_pd_tree_desc; } diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index b18edd96d..99fa9807a 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -84,6 +84,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); } + /* config CAAM JRaMID set MID to Cortex A */ + mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); + mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); + mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); + #if DEBUG_CONSOLE static console_uart_t console; diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index 4957582ad..5c5b0a5f9 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -119,3 +119,8 @@ #define DEBUG_CONSOLE 0 #define IMX_WDOG_B_RESET #define PLAT_IMX8M 1 + +#define CAAM_JR0MID U(0x30900010) +#define CAAM_JR1MID U(0x30900018) +#define CAAM_JR2MID U(0x30900020) +#define CAAM_NS_MID U(0x1) diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 2debbf94e..350df127a 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -236,7 +236,7 @@ void bl2_plat_flush_bl31_params(void) product = reg & RCAR_PRODUCT_MASK; cut = reg & RCAR_CUT_MASK; - if (product == RCAR_PRODUCT_M3) + if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut) goto tlb; if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) @@ -693,8 +693,17 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, break; } - if (RCAR_PRODUCT_M3_CUT11 == product_cut) { - NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str); + if ((RCAR_PRODUCT_M3 == product) && + (RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) { + if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) { + /* M3 Ver.1.1 or Ver.1.2 */ + NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", + str); + } else { + NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", + str, + (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); + } } else { major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; major = major + RCAR_MAJOR_OFFSET; diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index 3bb03f2e5..6bbd6fa7b 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -154,7 +154,7 @@ #define RCAR_PRODUCT_M3N U(0x00005500) #define RCAR_PRODUCT_E3 U(0x00005700) #define RCAR_CUT_VER10 U(0x00000000) -#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N Ver.1.1 */ +#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N/E3 Ver.1.1 */ #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ #define RCAR_CUT_VER20 U(0x00000010) #define RCAR_CUT_VER30 U(0x00000020) @@ -164,6 +164,7 @@ #define RCAR_MAJOR_SHIFT U(4) #define RCAR_MINOR_SHIFT U(0) #define RCAR_MAJOR_OFFSET U(1) +#define RCAR_M3_MINOR_OFFSET U(2) #define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | U(0x00)) /* 1.0 */ #define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | U(0x01)) /* 1.1 */ #define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | U(0x10)) /* 2.0 */ diff --git a/plat/renesas/rcar/include/rcar_version.h b/plat/renesas/rcar/include/rcar_version.h index 5c8805c2e..e43632407 100644 --- a/plat/renesas/rcar/include/rcar_version.h +++ b/plat/renesas/rcar/include/rcar_version.h @@ -9,7 +9,7 @@ #include <arch_helpers.h> -#define VERSION_OF_RENESAS "2.0.0" +#define VERSION_OF_RENESAS "2.0.1" #define VERSION_OF_RENESAS_MAXLEN (128) extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]; diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk index 97d6ddc7b..715b8ae17 100644 --- a/plat/renesas/rcar/platform.mk +++ b/plat/renesas/rcar/platform.mk @@ -38,10 +38,12 @@ $(eval $(call add_define,RCAR_H3N)) $(eval $(call add_define,RCAR_AUTO)) RCAR_CUT_10:=0 RCAR_CUT_11:=1 +RCAR_CUT_13:=3 RCAR_CUT_20:=10 RCAR_CUT_30:=20 $(eval $(call add_define,RCAR_CUT_10)) $(eval $(call add_define,RCAR_CUT_11)) +$(eval $(call add_define,RCAR_CUT_13)) $(eval $(call add_define,RCAR_CUT_20)) $(eval $(call add_define,RCAR_CUT_30)) @@ -98,6 +100,10 @@ else RCAR_LSI_CUT:=0 else ifeq (${LSI_CUT},11) RCAR_LSI_CUT:=1 + else ifeq (${LSI_CUT},13) + RCAR_LSI_CUT:=3 + else ifeq (${LSI_CUT},30) + RCAR_LSI_CUT:=20 else $(error "Error: ${LSI_CUT} is not supported.") endif @@ -130,6 +136,8 @@ else # disable compatible function. ifeq (${LSI_CUT},10) RCAR_LSI_CUT:=0 + else ifeq (${LSI_CUT},11) + RCAR_LSI_CUT:=1 else $(error "Error: ${LSI_CUT} is not supported.") endif |