diff options
| -rw-r--r-- | plat/intel/soc/agilex/bl31_plat_setup.c | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index 375483dd4..13099b40f 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -11,8 +11,10 @@ #include <common/bl_common.h> #include <drivers/arm/gicv2.h> #include <drivers/ti/uart/uart_16550.h> +#include <lib/mmio.h> #include <lib/xlat_tables/xlat_tables.h> +#include "socfpga_private.h" static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -44,23 +46,33 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void *from_bl2 = (void *) arg0; bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; - assert(params_from_bl2 != NULL); - assert(params_from_bl2->h.type == PARAM_BL_PARAMS); - assert(params_from_bl2->h.version >= VERSION_2); /* * Copy BL32 (if populated by BL31) and BL33 entry point information. * They are stored in Secure RAM, in BL31's address space. */ - bl_params_node_t *bl_params = params_from_bl2->head; + if (params_from_bl2->h.type == PARAM_BL_PARAMS && + params_from_bl2->h.version >= VERSION_2) { + + bl_params_node_t *bl_params = params_from_bl2->head; + + while (bl_params) { + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; - while (bl_params) { - if (bl_params->image_id == BL33_IMAGE_ID) - bl33_image_ep_info = *bl_params->ep_info; + bl_params = bl_params->next_params_info; + } + } else { + struct socfpga_bl31_params *arg_from_bl2 = + (struct socfpga_bl31_params *) from_bl2; - bl_params = bl_params->next_params_info; + assert(arg_from_bl2->h.type == PARAM_BL31); + assert(arg_from_bl2->h.version >= VERSION_1); + + bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; + bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; } SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); } @@ -91,6 +103,10 @@ void bl31_platform_setup(void) gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); + + /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ + mmio_write_64(PLAT_CPU_RELEASE_ADDR, + (uint64_t)plat_secondary_cpus_bl31_entry); } const mmap_region_t plat_agilex_mmap[] = { |