diff options
| -rw-r--r-- | docs/firmware-design.rst | 8 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cpu_macros.S | 22 |
2 files changed, 20 insertions, 10 deletions
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst index 4f51ff1d3..299654fc2 100644 --- a/docs/firmware-design.rst +++ b/docs/firmware-design.rst @@ -2549,10 +2549,8 @@ This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when Armv8.2-A ~~~~~~~~~ -This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 8 and -``ARM_ARCH_MINOR`` >= 2. - -- The Common not Private (CnP) bit is enabled to indicate that multiple +- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the + Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple Processing Elements in the same Inner Shareable domain use the same translation table entries for a given stage of translation for a particular translation regime. @@ -2647,7 +2645,7 @@ References -------------- -*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* .. _Reset Design: ./reset-design.rst .. _Porting Guide: ./porting-guide.rst diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index b907668b3..044aacaf4 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #define CPU_MACROS_S #include <arch.h> +#include <assert_macros.S> #include <lib/cpus/errata_report.h> #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ @@ -263,11 +264,22 @@ mrs \_reg, id_aa64pfr0_el1 ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH /* - * If the field equals to 1 then branch targets trained in one - * context cannot affect speculative execution in a different context. + * If the field equals 1, branch targets trained in one context cannot + * affect speculative execution in a different context. + * + * If the field equals 2, it means that the system is also aware of + * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we + * expect users of the registers to do the right thing. + * + * Only apply mitigations if the value of this field is 0. */ - cmp \_reg, #1 - beq \_label +#if ENABLE_ASSERTIONS + cmp \_reg, #3 /* Only values 0 to 2 are expected */ + ASM_ASSERT(lo) +#endif + + cmp \_reg, #0 + bne \_label .endm /* |