diff options
| -rw-r--r-- | lib/cpus/aarch32/cpu_helpers.S | 5 | ||||
| -rw-r--r-- | plat/arm/common/arm_bl2_setup.c | 14 | ||||
| -rw-r--r-- | plat/arm/common/sp_min/arm_sp_min.mk | 7 | ||||
| -rw-r--r-- | plat/common/plat_gicv2.c | 2 | ||||
| -rw-r--r-- | plat/qemu/platform.mk | 4 | ||||
| -rw-r--r-- | plat/qemu/qemu_gic.c | 68 | ||||
| -rw-r--r-- | plat/qemu/sp_min/sp_min-qemu.mk | 4 |
7 files changed, 30 insertions, 74 deletions
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S index 72e42c674..ddc080842 100644 --- a/lib/cpus/aarch32/cpu_helpers.S +++ b/lib/cpus/aarch32/cpu_helpers.S @@ -206,7 +206,8 @@ endfunc cpu_rev_var_hs */ .globl print_errata_status func print_errata_status - push {r4, lr} + /* r12 is pushed only for the sake of 8-byte stack alignment */ + push {r4, r5, r12, lr} #ifdef IMAGE_BL1 /* * BL1 doesn't have per-CPU data. So retrieve the CPU operations @@ -241,6 +242,6 @@ func print_errata_status blxne r4 1: #endif - pop {r4, pc} + pop {r4, r5, r12, pc} endfunc print_errata_status #endif diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 5d83118a8..906ed197a 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -24,6 +24,20 @@ /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); +/* + * Check that BL2_BASE is atleast a page over ARM_BL_RAM_BASE. The page is for + * `meminfo_t` data structure and TB_FW_CONFIG passed from BL1. Not needed + * when BL2 is compiled for BL_AT_EL3 as BL2 doesn't need any info from BL1 and + * BL2 is loaded at base of usable SRAM. + */ +#if BL2_AT_EL3 +#define BL1_MEMINFO_OFFSET 0x0 +#else +#define BL1_MEMINFO_OFFSET PAGE_SIZE +#endif + +CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows); + /* Weak definitions may be overridden in specific ARM standard platform */ #pragma weak bl2_early_platform_setup #pragma weak bl2_platform_setup diff --git a/plat/arm/common/sp_min/arm_sp_min.mk b/plat/arm/common/sp_min/arm_sp_min.mk index e6792ca59..edab8843c 100644 --- a/plat/arm/common/sp_min/arm_sp_min.mk +++ b/plat/arm/common/sp_min/arm_sp_min.mk @@ -5,6 +5,13 @@ # # SP MIN source files common to ARM standard platforms + +# Skip building BL1 and BL2 if RESET_TO_SP_MIN flag is set. +ifeq (${RESET_TO_SP_MIN},1) + BL1_SOURCES = + BL2_SOURCES = +endif + BL32_SOURCES += plat/arm/common/arm_pm.c \ plat/arm/common/arm_topology.c \ plat/arm/common/sp_min/arm_sp_min_setup.c \ diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c index 38e1a61e7..ca6c03b01 100644 --- a/plat/common/plat_gicv2.c +++ b/plat/common/plat_gicv2.c @@ -134,6 +134,8 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, type == INTR_TYPE_EL3 || type == INTR_TYPE_NS); + assert(sec_state_is_valid(security_state)); + /* Non-secure interrupts are signaled on the IRQ line always */ if (type == INTR_TYPE_NS) return __builtin_ctz(SCR_IRQ_BIT); diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk index 334fbe485..26633c24c 100644 --- a/plat/qemu/platform.mk +++ b/plat/qemu/platform.mk @@ -150,12 +150,12 @@ BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ drivers/arm/gic/v2/gicv2_helpers.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/common/gic_common.c \ + plat/common/plat_gicv2.c \ plat/common/plat_psci_common.c \ plat/qemu/qemu_pm.c \ plat/qemu/topology.c \ plat/qemu/aarch64/plat_helpers.S \ - plat/qemu/qemu_bl31_setup.c \ - plat/qemu/qemu_gic.c + plat/qemu/qemu_bl31_setup.c endif # Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images diff --git a/plat/qemu/qemu_gic.c b/plat/qemu/qemu_gic.c deleted file mode 100644 index 41b5eb45c..000000000 --- a/plat/qemu/qemu_gic.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <bl_common.h> -#include <gicv2.h> -#include <interrupt_mgmt.h> - -uint32_t plat_ic_get_pending_interrupt_id(void) -{ - return gicv2_get_pending_interrupt_id(); -} - -uint32_t plat_ic_get_pending_interrupt_type(void) -{ - return gicv2_get_pending_interrupt_type(); -} - -uint32_t plat_ic_acknowledge_interrupt(void) -{ - return gicv2_acknowledge_interrupt(); -} - -uint32_t plat_ic_get_interrupt_type(uint32_t id) -{ - uint32_t group; - - group = gicv2_get_interrupt_group(id); - - /* Assume that all secure interrupts are S-EL1 interrupts */ - if (!group) - return INTR_TYPE_S_EL1; - else - return INTR_TYPE_NS; - -} - -void plat_ic_end_of_interrupt(uint32_t id) -{ - gicv2_end_of_interrupt(id); -} - -uint32_t plat_interrupt_type_to_line(uint32_t type, - uint32_t security_state) -{ - assert(type == INTR_TYPE_S_EL1 || - type == INTR_TYPE_EL3 || - type == INTR_TYPE_NS); - - assert(sec_state_is_valid(security_state)); - - /* Non-secure interrupts are signalled on the IRQ line always */ - if (type == INTR_TYPE_NS) - return __builtin_ctz(SCR_IRQ_BIT); - - /* - * Secure interrupts are signalled using the IRQ line if the FIQ_EN - * bit is not set else they are signalled using the FIQ line. - */ - if (gicv2_is_fiq_enabled()) - return __builtin_ctz(SCR_FIQ_BIT); - else - return __builtin_ctz(SCR_IRQ_BIT); -} - diff --git a/plat/qemu/sp_min/sp_min-qemu.mk b/plat/qemu/sp_min/sp_min-qemu.mk index 5e8875b10..e93a0c231 100644 --- a/plat/qemu/sp_min/sp_min-qemu.mk +++ b/plat/qemu/sp_min/sp_min-qemu.mk @@ -6,7 +6,6 @@ BL32_SOURCES += plat/qemu/sp_min/sp_min_setup.c \ plat/qemu/aarch32/plat_helpers.S \ - plat/qemu/qemu_gic.c \ plat/qemu/qemu_pm.c \ plat/qemu/topology.c @@ -14,7 +13,8 @@ BL32_SOURCES += lib/cpus/aarch32/aem_generic.S \ lib/cpus/aarch32/cortex_a15.S BL32_SOURCES += plat/common/aarch32/platform_mp_stack.S \ - plat/common/plat_psci_common.c + plat/common/plat_psci_common.c \ + plat/common/plat_gicv2.c BL32_SOURCES += drivers/arm/gic/v2/gicv2_helpers.c \ |