diff options
142 files changed, 2072 insertions, 1657 deletions
@@ -255,7 +255,7 @@ ASFLAGS_aarch64 = $(march64-directive) # General warnings WARNINGS := -Wall -Wmissing-include-dirs -Wunused \ -Wdisabled-optimization -Wvla -Wshadow \ - -Wno-unused-parameter + -Wno-unused-parameter -Wredundant-decls # Additional warnings # Level 1 @@ -274,7 +274,6 @@ WARNING3 += -Wcast-qual WARNING3 += -Wconversion WARNING3 += -Wpacked WARNING3 += -Wpointer-arith -WARNING3 += -Wredundant-decls WARNING3 += -Wswitch-default ifeq (${W},1) @@ -452,18 +451,30 @@ ifeq (${ARM_ARCH_MAJOR},7) include make_helpers/armv7-a-cpus.mk endif -ifeq ($(ENABLE_PIE),1) - TF_CFLAGS += -fpie - ifneq ($(findstring gcc,$(notdir $(LD))),) - TF_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker - else - TF_LDFLAGS += -pie --no-dynamic-linker - endif +PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT}) +ifneq ($(PIE_FOUND),) + TF_CFLAGS += -fno-PIE +endif + +ifneq ($(findstring gcc,$(notdir $(LD))),) + PIE_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker else - PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT}) - ifneq ($(PIE_FOUND),) - TF_CFLAGS += -fno-PIE - endif + PIE_LDFLAGS += -pie --no-dynamic-linker +endif + +ifeq ($(ENABLE_PIE),1) +ifeq ($(BL2_AT_EL3),1) +ifneq ($(BL2_IN_XIP_MEM),1) + BL2_CFLAGS += -fpie + BL2_LDFLAGS += $(PIE_LDFLAGS) +endif +endif + BL31_CFLAGS += -fpie + BL31_LDFLAGS += $(PIE_LDFLAGS) +ifeq ($(ARCH),aarch64) + BL32_CFLAGS += -fpie + BL32_LDFLAGS += $(PIE_LDFLAGS) +endif endif # Include the CPU specific operations makefile, which provides default @@ -592,6 +603,14 @@ ifeq ($(CTX_INCLUDE_MTE_REGS),1) endif endif +ifeq ($(MEASURED_BOOT),1) + ifneq (${TRUSTED_BOARD_BOOT},1) + $(error MEASURED_BOOT requires TRUSTED_BOARD_BOOT=1") + else + $(info MEASURED_BOOT is an experimental feature) + endif +endif + ################################################################################ # Process platform overrideable behaviour ################################################################################ @@ -739,6 +758,7 @@ $(eval $(call assert_boolean,GENERATE_COT)) $(eval $(call assert_boolean,GICV2_G0_FOR_EL3)) $(eval $(call assert_boolean,HANDLE_EA_EL3_FIRST)) $(eval $(call assert_boolean,HW_ASSISTED_COHERENCY)) +$(eval $(call assert_boolean,MEASURED_BOOT)) $(eval $(call assert_boolean,NS_TIMER_SWITCH)) $(eval $(call assert_boolean,OVERRIDE_LIBC)) $(eval $(call assert_boolean,PL011_GENERIC_UART)) @@ -805,6 +825,7 @@ $(eval $(call add_define,GICV2_G0_FOR_EL3)) $(eval $(call add_define,HANDLE_EA_EL3_FIRST)) $(eval $(call add_define,HW_ASSISTED_COHERENCY)) $(eval $(call add_define,LOG_LEVEL)) +$(eval $(call add_define,MEASURED_BOOT)) $(eval $(call add_define,NS_TIMER_SWITCH)) $(eval $(call add_define,PL011_GENERIC_UART)) $(eval $(call add_define,PLAT_${PLAT})) diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index 9bba6eef3..9dc9e6cd5 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -202,7 +202,7 @@ debug_loop: ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] - eret + exception_return endfunc smc_handler64 unexpected_sync_exception: diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S index f97121ef0..4eab39cd3 100644 --- a/bl2/aarch64/bl2_el3_entrypoint.S +++ b/bl2/aarch64/bl2_el3_entrypoint.S @@ -1,9 +1,11 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <platform_def.h> + #include <arch.h> #include <asm_macros.S> #include <common/bl_common.h> @@ -13,6 +15,12 @@ .globl bl2_el3_run_image .globl bl2_run_next_image +#if BL2_IN_XIP_MEM +#define FIXUP_SIZE 0 +#else +#define FIXUP_SIZE ((BL2_LIMIT) - (BL2_BASE)) +#endif + func bl2_entrypoint /* Save arguments x0-x3 from previous Boot loader */ mov x20, x0 @@ -27,7 +35,7 @@ func bl2_entrypoint _init_memory=1 \ _init_c_runtime=1 \ _exception_vectors=bl2_el3_exceptions \ - _pie_fixup_size=0 + _pie_fixup_size=FIXUP_SIZE /* --------------------------------------------- * Restore parameters of boot rom @@ -95,5 +103,5 @@ func bl2_run_next_image ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] - eret + exception_return endfunc bl2_run_next_image diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S index dc398eb02..b6570ee3e 100644 --- a/bl2/bl2_el3.ld.S +++ b/bl2/bl2_el3.ld.S @@ -69,6 +69,16 @@ SECTIONS KEEP(*(cpu_ops)) __CPU_OPS_END__ = .; + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >ROM @@ -100,6 +110,16 @@ SECTIONS KEEP(*(.img_parser_lib_descs)) __PARSER_LIB_DESCS_END__ = .; + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + *(.vectors) __RO_END_UNALIGNED__ = .; /* @@ -139,6 +159,17 @@ SECTIONS __DATA_RAM_END__ = .; } >RAM AT>ROM + /* + * .rela.dyn needs to come after .data for the read-elf utility to parse + * this section correctly. Ensure 8-byte alignment so that the fields of + * RELA data structure are aligned. + */ + . = ALIGN(8); + __RELA_START__ = .; + .rela.dyn . : { + } >RAM + __RELA_END__ = .; + stacks (NOLOAD) : { __STACKS_START__ = .; *(tzfw_normal_stacks) @@ -195,6 +226,10 @@ SECTIONS __RW_END__ = .; __BL2_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + #if BL2_IN_XIP_MEM __BL2_RAM_START__ = ADDR(.data); __BL2_RAM_END__ = .; diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 51f5b7b34..7f739a9aa 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -456,7 +456,7 @@ smc_unknown: smc_prohibited: ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] mov x0, #SMC_UNK - eret + exception_return #if DEBUG rt_svc_fw_critical_error: diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 42227f0f3..c7185a893 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -339,6 +339,10 @@ SECTIONS __RW_END__ = .; __BL31_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") #endif } diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 1d3ec21a7..ebc5c2c3d 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,9 +1,11 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <platform_def.h> + #include <arch.h> #include <asm_macros.S> #include <bl32/tsp/tsp.h> @@ -46,6 +48,24 @@ func tsp_entrypoint _align=3 +#if ENABLE_PIE + /* + * ------------------------------------------------------------ + * If PIE is enabled fixup the Global descriptor Table only + * once during primary core cold boot path. + * + * Compile time base address, required for fixup, is calculated + * using "pie_fixup" label present within first page. + * ------------------------------------------------------------ + */ + pie_fixup: + ldr x0, =pie_fixup + and x0, x0, #~(PAGE_SIZE - 1) + mov_imm x1, (BL32_LIMIT - BL32_BASE) + add x1, x1, x0 + bl fixup_gdt_reloc +#endif /* ENABLE_PIE */ + /* --------------------------------------------- * Set the exception vector to something sane. * --------------------------------------------- diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index ad4b64887..4c6a56a59 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,7 +64,7 @@ smc #0 interrupt_exit_\label: restore_caller_regs_and_lr - eret + exception_return .endm .globl tsp_exceptions diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index e9a1df168..592e24557 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,6 +36,17 @@ SECTIONS .rodata . : { __RODATA_START__ = .; *(.rodata*) + + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >RAM @@ -45,7 +56,19 @@ SECTIONS *tsp_entrypoint.o(.text*) *(.text*) *(.rodata*) + + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + *(.vectors) + __RO_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked as @@ -69,6 +92,17 @@ SECTIONS __DATA_END__ = .; } >RAM + /* + * .rela.dyn needs to come after .data for the read-elf utility to parse + * this section correctly. Ensure 8-byte alignment so that the fields of + * RELA data structure are aligned. + */ + . = ALIGN(8); + __RELA_START__ = .; + .rela.dyn . : { + } >RAM + __RELA_END__ = .; + #ifdef TSP_PROGBITS_LIMIT ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.") #endif @@ -129,6 +163,10 @@ SECTIONS __RW_END__ = .; __BL32_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + __BSS_SIZE__ = SIZEOF(.bss); #if USE_COHERENT_MEM __COHERENT_RAM_UNALIGNED_SIZE__ = diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst index 9aba95450..52b1c03e8 100644 --- a/docs/components/secure-partition-manager-design.rst +++ b/docs/components/secure-partition-manager-design.rst @@ -119,7 +119,7 @@ Interface). This will be referred to as the *Standalone MM Secure Partition* in the rest of this document. To enable SPM support in TF-A, the source code must be compiled with the build -flag ``ENABLE_SPM=1``, along with ``EL3_EXCEPTION_HANDLING=1``. On Arm +flag ``SPM_MM=1``, along with ``EL3_EXCEPTION_HANDLING=1``. On Arm platforms the build option ``ARM_BL31_IN_DRAM`` must be set to 1. Also, the location of the binary that contains the BL32 image (``BL32=path/to/image.bin``) must be specified. @@ -133,7 +133,7 @@ image in the FIP: .. code:: shell BL32=path/to/standalone/mm/sp BL33=path/to/bl33.bin \ - make PLAT=fvp ENABLE_SPM=1 ARM_BL31_IN_DRAM=1 fip all + make PLAT=fvp SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ARM_BL31_IN_DRAM=1 all fip Describing Secure Partition resources ------------------------------------- diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 7fa027f42..f3096b418 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -324,6 +324,11 @@ architecture that can be enabled by the platform as desired. as recommended in section "4.7 Non-Temporal Loads/Stores" of the `Cortex-A57 Software Optimization Guide`_. +- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last + level cache(LLC) is present in the system, and that the DataSource field + on the master CHI interface indicates when data is returned from the LLC. + This is used to control how the LL_CACHE* PMU events count. + -------------- *Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index d7bb0449e..b702c34de 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -213,7 +213,7 @@ Common build options - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) support within generic code in TF-A. This option is currently only supported - in BL31. Default is 0. + in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. - ``ENABLE_PMF``: Boolean option to enable support for optional Performance Measurement Framework(PMF). Default is 0. @@ -387,6 +387,11 @@ Common build options All log output up to and including the selected log level is compiled into the build. The default value is 40 in debug builds and 20 in release builds. +- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot + feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set. + This option defaults to 0 and is an experimental feature in the stage of + development. + - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the Non-Trusted World private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst index 95c89a8b2..57a363bc9 100644 --- a/docs/plat/xilinx-versal.rst +++ b/docs/plat/xilinx-versal.rst @@ -33,3 +33,11 @@ Xilinx Versal platform specific build options * `VERSAL_PLATFORM`: Select the platform. Options: - `versal_virt` : Versal Virtual platform + +# PLM->TF-A Parameter Passing +------------------------------ +The PLM populates a data structure with image information for the TF-A. The TF-A +uses that data to hand off to the loaded images. The address of the handoff +data structure is passed in the ```PMC_GLOBAL_GLOB_GEN_STORAGE4``` register. +The register is free to be used by other software once the TF-A is bringing up +further firmware images. diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c index 5e5ac2b03..110c5045f 100644 --- a/drivers/auth/crypto_mod.c +++ b/drivers/auth/crypto_mod.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -103,3 +103,24 @@ int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, return crypto_lib_desc.verify_hash(data_ptr, data_len, digest_info_ptr, digest_info_len); } + +#if MEASURED_BOOT +/* + * Calculate a hash + * + * Parameters: + * + * alg: message digest algorithm + * data_ptr, data_len: data to be hashed + * output: resulting hash + */ +int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output) +{ + assert(data_ptr != NULL); + assert(data_len != 0); + assert(output != NULL); + + return crypto_lib_desc.calc_hash(alg, data_ptr, data_len, output); +} +#endif /* MEASURED_BOOT */ diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c index 33420fbbd..04fbc648b 100644 --- a/drivers/auth/mbedtls/mbedtls_crypto.c +++ b/drivers/auth/mbedtls/mbedtls_crypto.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -205,7 +205,32 @@ static int verify_hash(void *data_ptr, unsigned int data_len, return CRYPTO_SUCCESS; } +#if MEASURED_BOOT +/* + * Calculate a hash + * + * output points to the computed hash + */ +int calc_hash(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output) +{ + const mbedtls_md_info_t *md_info; + + md_info = mbedtls_md_info_from_type((mbedtls_md_type_t)alg); + if (md_info == NULL) { + return CRYPTO_ERR_HASH; + } + + /* Calculate the hash of the data */ + return mbedtls_md(md_info, data_ptr, data_len, output); +} +#endif /* MEASURED_BOOT */ + /* * Register crypto library descriptor */ +#if MEASURED_BOOT +REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash); +#else REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash); +#endif /* MEASURED_BOOT */ diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index 79e0ad7f3..a7d5a3dd6 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -218,4 +218,13 @@ ret .endm + /* + * Macro for mitigating against speculative execution beyond ERET. + */ + .macro exception_return + eret + dsb nsh + isb + .endm + #endif /* ASM_MACROS_S */ diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 896a03f0a..77fb1f679 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -106,6 +106,7 @@ IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END); IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END); #endif +IMPORT_SYM(uintptr_t, __RW_END__, BL_END); #if defined(IMAGE_BL1) IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END); diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h index 3a4210569..f211035d7 100644 --- a/include/drivers/auth/crypto_mod.h +++ b/include/drivers/auth/crypto_mod.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,6 +37,13 @@ typedef struct crypto_lib_desc_s { /* Verify a hash. Return one of the 'enum crypto_ret_value' options */ int (*verify_hash)(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); + +#if MEASURED_BOOT + /* Calculate a hash. Return hash value */ + int (*calc_hash)(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output); +#endif /* MEASURED_BOOT */ + } crypto_lib_desc_t; /* Public functions */ @@ -48,7 +55,21 @@ int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); +#if MEASURED_BOOT +int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, + unsigned int data_len, unsigned char *output); + /* Macro to register a cryptographic library */ +#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ + _calc_hash) \ + const crypto_lib_desc_t crypto_lib_desc = { \ + .name = _name, \ + .init = _init, \ + .verify_signature = _verify_signature, \ + .verify_hash = _verify_hash, \ + .calc_hash = _calc_hash \ + } +#else #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash) \ const crypto_lib_desc_t crypto_lib_desc = { \ .name = _name, \ @@ -56,6 +77,7 @@ int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, .verify_signature = _verify_signature, \ .verify_hash = _verify_hash \ } +#endif /* MEASURED_BOOT */ extern const crypto_lib_desc_t crypto_lib_desc; diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index fa733ce1b..b50befa8d 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,6 +35,7 @@ #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) +#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) /******************************************************************************* * CPU Auxiliary Control register specific definitions. diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 868667ebc..baefa4676 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -85,7 +85,7 @@ bic x3, x2, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE csel x3, x3, x1, eq msr CORTEX_A76_CPUACTLR2_EL1, x3 - eret /* ERET implies ISB */ + exception_return /* exception_return contains ISB */ .endif 1: /* diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index faf53a848..d537ed6a8 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -465,6 +465,13 @@ func neoverse_n1_reset_func msr CPUAMCNTENSET_EL0, x0 #endif +#if NEOVERSE_N1_EXTERNAL_LLC + /* Some system may have External LLC, core needs to be made aware */ + mrs x0, NEOVERSE_N1_CPUECTLR_EL1 + orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT + msr NEOVERSE_N1_CPUECTLR_EL1, x0 +#endif + #if ERRATA_DSU_936184 bl errata_dsu_936184_wa #endif @@ -553,7 +560,7 @@ func neoverse_n1_errata_ic_trap_handler */ esb #endif - eret + exception_return 1: ret endfunc neoverse_n1_errata_ic_trap_handler diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S index 9277cc624..5134ee3f1 100644 --- a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S +++ b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -48,7 +48,7 @@ vector_base wa_cve_2017_5715_mmu_vbar ccmp w0, w1, #0, eq /* Static predictor will predict a fall through */ bne 1f - eret + exception_return 1: .endif diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index c9b9b387e..e3bfc2f2e 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -20,6 +20,10 @@ WORKAROUND_CVE_2017_5715 ?=1 WORKAROUND_CVE_2018_3639 ?=1 DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0 +# Flag to indicate internal or external Last level cache +# By default internal +NEOVERSE_N1_EXTERNAL_LLC ?=0 + # Process SKIP_A57_L1_FLUSH_PWR_DWN flag $(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) $(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) @@ -43,6 +47,9 @@ $(eval $(call add_define,WORKAROUND_CVE_2018_3639)) $(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639)) $(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639)) +$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC)) +$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC)) + ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0) ifeq (${WORKAROUND_CVE_2018_3639},0) $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1") @@ -240,7 +247,7 @@ ERRATA_HERCULES_1688305 ?=0 # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. -ERRATA_N1_1043202 ?=1 +ERRATA_N1_1043202 ?=0 # Flag to apply erratum 1073348 workaround during reset. This erratum applies # only to revision r0p0 and r1p0 of the Neoverse N1 cpu. @@ -280,7 +287,7 @@ ERRATA_N1_1275112 ?=0 # Flag to apply erratum 1315703 workaround during reset. This erratum applies # to revisions before r3p1 of the Neoverse N1 cpu. -ERRATA_N1_1315703 ?=1 +ERRATA_N1_1315703 ?=0 # Flag to apply erratum 1542419 workaround during reset. This erratum applies # to revisions r3p0 - r4p0 of the Neoverse N1 cpu. diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 1bbd61005..9bd25bac9 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -534,6 +534,6 @@ func el3_exit */ esb #endif - eret + exception_return endfunc el3_exit diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c index 3c0865b81..b2259e5f3 100644 --- a/lib/xlat_tables_v2/xlat_tables_core.c +++ b/lib/xlat_tables_v2/xlat_tables_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -688,10 +688,10 @@ static int mmap_add_region_check(const xlat_ctx_t *ctx, const mmap_region_t *mm) if ((base_pa > end_pa) || (base_va > end_va)) return -ERANGE; - if ((base_va + (uintptr_t)size - (uintptr_t)1) > ctx->va_max_address) + if (end_va > ctx->va_max_address) return -ERANGE; - if ((base_pa + (unsigned long long)size - 1ULL) > ctx->pa_max_address) + if (end_pa > ctx->pa_max_address) return -ERANGE; /* Check that there is space in the ctx->mmap array */ diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 6b72cfd0d..1fa26cc2b 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -412,6 +412,7 @@ bl${1}_dirs: | ${OBJ_DIRS} $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES),$(1))) $(eval $(call MAKE_LD,$(LINKERFILE),$(BL_LINKERFILE),$(1))) +$(eval BL_LDFLAGS := $(BL$(call uppercase,$(1))_LDFLAGS)) ifeq ($(USE_ROMLIB),1) $(ELF): romlib.bin @@ -427,7 +428,7 @@ else $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -xc -c - -o $(BUILD_DIR)/build_message.o endif ifneq ($(findstring armlink,$(notdir $(LD))),) - $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) --entry=bl${1}_entrypoint \ + $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) --entry=bl${1}_entrypoint \ --predefine="-D__LINKER__=$(__LINKER__)" \ --predefine="-DTF_CFLAGS=$(TF_CFLAGS)" \ --map --list="$(MAPFILE)" --scatter=${PLAT_DIR}/scat/bl${1}.scat \ @@ -438,7 +439,7 @@ else ifneq ($(findstring gcc,$(notdir $(LD))),) -Wl,-T$(LINKERFILE) $(BUILD_DIR)/build_message.o \ $(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) else - $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) -Map=$(MAPFILE) \ + $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Map=$(MAPFILE) \ --script $(LINKERFILE) $(BUILD_DIR)/build_message.o \ $(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) endif diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 53832c561..4af1da6b2 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -139,6 +139,9 @@ HW_ASSISTED_COHERENCY := 0 # Set the default algorithm for the generation of Trusted Board Boot keys KEY_ALG := rsa +# Option to build TF with Measured Boot support +MEASURED_BOOT := 0 + # NS timer register save and restore NS_TIMER_SWITCH := 0 diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index 4de8b0bc4..32a7c0408 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -40,17 +40,17 @@ #define PLAT_MAX_OFF_STATE U(2) #define PLAT_MAX_PWR_LVL U(2) -#define PLAT_NUM_PWR_DOMAINS (1 + \ +#define PLAT_NUM_PWR_DOMAINS (U(1) + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) -#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_MAX_CPUS_PER_CLUSTER) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_MMAP_REGIONS 4 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk index db41e0eda..43c37ffc1 100644 --- a/plat/arm/board/rde1edge/platform.mk +++ b/plat/arm/board/rde1edge/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, Arm Limited. All rights reserved. +# Copyright (c) 2018-2020, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -24,6 +24,7 @@ BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \ BL31_SOURCES += ${SGI_CPU_SOURCES} \ ${RDE1EDGE_BASE}/rde1edge_plat.c \ + ${RDE1EDGE_BASE}/rde1edge_topology.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/rde1edge/rde1edge_topology.c b/plat/arm/board/rde1edge/rde1edge_topology.c new file mode 100644 index 000000000..0b56f208a --- /dev/null +++ b/plat/arm/board/rde1edge/rde1edge_topology.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat/arm/common/plat_arm.h> + +/****************************************************************************** + * The power domain tree descriptor. + ******************************************************************************/ +static const unsigned char rde1edge_pd_tree_desc[] = { + PLAT_ARM_CLUSTER_COUNT, + CSS_SGI_MAX_CPUS_PER_CLUSTER, + CSS_SGI_MAX_CPUS_PER_CLUSTER +}; + +/****************************************************************************** + * This function returns the topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return rde1edge_pd_tree_desc; +} + +/******************************************************************************* + * The array mapping platform core position (implemented by plat_my_core_pos()) + * to the SCMI power domain ID implemented by SCP. + ******************************************************************************/ +const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 +}; diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk index b44c70a3b..ca1e95eaf 100644 --- a/plat/arm/board/rdn1edge/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -24,6 +24,7 @@ BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \ BL31_SOURCES += ${SGI_CPU_SOURCES} \ ${RDN1EDGE_BASE}/rdn1edge_plat.c \ + ${RDN1EDGE_BASE}/rdn1edge_topology.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/rdn1edge/rdn1edge_topology.c b/plat/arm/board/rdn1edge/rdn1edge_topology.c new file mode 100644 index 000000000..687ae3595 --- /dev/null +++ b/plat/arm/board/rdn1edge/rdn1edge_topology.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat/arm/common/plat_arm.h> + +/****************************************************************************** + * The power domain tree descriptor. + ******************************************************************************/ +static const unsigned char rdn1edge_pd_tree_desc[] = { + PLAT_ARM_CLUSTER_COUNT, + CSS_SGI_MAX_CPUS_PER_CLUSTER, + CSS_SGI_MAX_CPUS_PER_CLUSTER +}; + +/******************************************************************************* + * This function returns the topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return rdn1edge_pd_tree_desc; +} + +/******************************************************************************* + * The array mapping platform core position (implemented by plat_my_core_pos()) + * to the SCMI power domain ID implemented by SCP. + ******************************************************************************/ +const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { + 0, 1, 2, 3, 4, 5, 6, 7 +}; diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk index b9fa0995d..ce2717fe0 100644 --- a/plat/arm/board/sgi575/platform.mk +++ b/plat/arm/board/sgi575/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -24,6 +24,7 @@ BL2_SOURCES += ${SGI575_BASE}/sgi575_plat.c \ BL31_SOURCES += ${SGI_CPU_SOURCES} \ ${SGI575_BASE}/sgi575_plat.c \ + ${SGI575_BASE}/sgi575_topology.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c diff --git a/plat/arm/board/sgi575/sgi575_topology.c b/plat/arm/board/sgi575/sgi575_topology.c new file mode 100644 index 000000000..f7c385673 --- /dev/null +++ b/plat/arm/board/sgi575/sgi575_topology.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat/arm/common/plat_arm.h> + +/****************************************************************************** + * The power domain tree descriptor. + ******************************************************************************/ +static const unsigned char sgi575_pd_tree_desc[] = { + PLAT_ARM_CLUSTER_COUNT, + CSS_SGI_MAX_CPUS_PER_CLUSTER, + CSS_SGI_MAX_CPUS_PER_CLUSTER +}; + +/******************************************************************************* + * This function returns the topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return sgi575_pd_tree_desc; +} + +/******************************************************************************* + * The array mapping platform core position (implemented by plat_my_core_pos()) + * to the SCMI power domain ID implemented by SCP. + ******************************************************************************/ +const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { + 0, 1, 2, 3, 4, 5, 6, 7 +}; diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c index 7aa9e40d3..1c3b5bfc8 100644 --- a/plat/arm/css/sgi/sgi_topology.c +++ b/plat/arm/css/sgi/sgi_topology.c @@ -1,62 +1,14 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <plat/arm/common/plat_arm.h> -#include <plat/common/platform.h> -#include <sgi_variant.h> - -/* Topology */ /* - * The power domain tree descriptor. The cluster power domains are - * arranged so that when the PSCI generic code creates the power domain tree, - * the indices of the CPU power domain nodes it allocates match the linear - * indices returned by plat_core_pos_by_mpidr(). + * Common topology related methods for SGI and RD based platforms */ -const unsigned char sgi_pd_tree_desc[] = { - PLAT_ARM_CLUSTER_COUNT, - CSS_SGI_MAX_CPUS_PER_CLUSTER, - CSS_SGI_MAX_CPUS_PER_CLUSTER -}; - -/* RD-E1-Edge platform consists of 16 physical CPUS and 32 threads */ -const unsigned char rd_e1_edge_pd_tree_desc[] = { - PLAT_ARM_CLUSTER_COUNT, - CSS_SGI_MAX_CPUS_PER_CLUSTER, - CSS_SGI_MAX_CPUS_PER_CLUSTER, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU, - CSS_SGI_MAX_PE_PER_CPU -}; - -/******************************************************************************* - * This function returns the topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM && - sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID) - return rd_e1_edge_pd_tree_desc; - else - return sgi_pd_tree_desc; -} - /******************************************************************************* * This function returns the core count within the cluster corresponding to * `mpidr`. @@ -66,15 +18,7 @@ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) return CSS_SGI_MAX_CPUS_PER_CLUSTER; } -/******************************************************************************* - * The array mapping platform core position (implemented by plat_my_core_pos()) - * to the SCMI power domain ID implemented by SCP. - ******************************************************************************/ -const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = { - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 -}; - +#if ARM_PLAT_MT /****************************************************************************** * Return the number of PE's supported by the CPU. *****************************************************************************/ @@ -82,3 +26,4 @@ unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr) { return CSS_SGI_MAX_PE_PER_CPU; } +#endif diff --git a/plat/arm/css/sgm/sgm-common.mk b/plat/arm/css/sgm/sgm-common.mk index 34e78b2f4..ac34450a7 100644 --- a/plat/arm/css/sgm/sgm-common.mk +++ b/plat/arm/css/sgm/sgm-common.mk @@ -4,6 +4,8 @@ # SPDX-License-Identifier: BSD-3-Clause # +CSS_USE_SCMI_SDS_DRIVER := 1 + CSS_SGM_BASE := plat/arm/css/sgm PLAT_INCLUDES := -I${CSS_SGM_BASE}/include diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h index 2537ac66b..04ea71f67 100644 --- a/plat/hisilicon/hikey/include/platform_def.h +++ b/plat/hisilicon/hikey/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,13 +28,13 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CORE_COUNT_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_CORE_COUNT_PER_CLUSTER) #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ - PLATFORM_CLUSTER_COUNT + 1) + PLATFORM_CLUSTER_COUNT + U(1)) #define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_OFF_STATE U(2) diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h index f6edad668..215eebe1b 100644 --- a/plat/hisilicon/hikey960/include/platform_def.h +++ b/plat/hisilicon/hikey960/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,12 +25,12 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CORE_COUNT_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ PLATFORM_CORE_COUNT_PER_CLUSTER) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ PLATFORM_CLUSTER_COUNT + 1) #define PLAT_MAX_RET_STATE U(1) diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h index 9783f8d2d..ce0fbbca0 100644 --- a/plat/hisilicon/poplar/include/platform_def.h +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,9 +34,9 @@ #define BOOT_EMMC_NAME "l-loader.bin" #define PLATFORM_CACHE_LINE_SIZE (64) -#define PLATFORM_CLUSTER_COUNT (1) -#define PLATFORM_CORE_COUNT (4) -#define PLATFORM_MAX_CPUS_PER_CLUSTER (4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT U(4) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) /* IO framework user */ #define MAX_IO_DEVICES (4) diff --git a/plat/imx/imx7/picopi/include/platform_def.h b/plat/imx/imx7/picopi/include/platform_def.h index 1af1d0cfc..141571c67 100644 --- a/plat/imx/imx7/picopi/include/platform_def.h +++ b/plat/imx/imx7/picopi/include/platform_def.h @@ -13,15 +13,15 @@ #define PLATFORM_STACK_SIZE 0x1000 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 2 -#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT -#define PICOPI_PRIMARY_CPU 0 +#define PICOPI_PRIMARY_CPU U(0) -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h index 4f719083e..4afcb5497 100644 --- a/plat/imx/imx7/warp7/include/platform_def.h +++ b/plat/imx/imx7/warp7/include/platform_def.h @@ -13,15 +13,15 @@ #define PLATFORM_STACK_SIZE 0x1000 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 2 -#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ PLATFORM_CLUSTER1_CORE_COUNT) -#define WARP7_PRIMARY_CPU 0 +#define WARP7_PRIMARY_CPU U(0) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index fc35dac14..56caab7ce 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -10,11 +10,11 @@ #define PLATFORM_STACK_SIZE 0xB00 #define CACHE_WRITEBACK_GRANULE 64 -#define PLAT_PRIMARY_CPU 0x0 -#define PLATFORM_MAX_CPU_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) #define IMX_PWR_LVL0 MPIDR_AFFLVL0 diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index 9aa759fd3..9db3a137a 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -10,11 +10,11 @@ #define PLATFORM_STACK_SIZE 0x800 #define CACHE_WRITEBACK_GRANULE 64 -#define PLAT_PRIMARY_CPU 0x0 -#define PLATFORM_MAX_CPU_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) #define IMX_PWR_LVL0 MPIDR_AFFLVL0 diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c index c76de6461..9232cbc2d 100644 --- a/plat/imx/imx8qm/imx8qm_bl31_setup.c +++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,12 +27,13 @@ #include <sci/sci.h> #include <sec_rsrc.h> -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); -IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); -IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); +static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE; +static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END; +static const unsigned long BL31_RO_START = BL_CODE_BASE; +static const unsigned long BL31_RO_END = BL_CODE_END; +static const unsigned long BL31_RW_END = BL_END; + IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); -IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; diff --git a/plat/imx/imx8qm/include/platform_def.h b/plat/imx/imx8qm/include/platform_def.h index 138a4e1d3..b54943da0 100644 --- a/plat/imx/imx8qm/include/platform_def.h +++ b/plat/imx/imx8qm/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,11 +15,11 @@ #define PLATFORM_STACK_SIZE 0X400 #define CACHE_WRITEBACK_GRANULE 64 -#define PLAT_PRIMARY_CPU 0x0 -#define PLATFORM_MAX_CPU_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(2) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ PLATFORM_CLUSTER1_CORE_COUNT) diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c index bfe405284..58c82ce60 100644 --- a/plat/imx/imx8qx/imx8qx_bl31_setup.c +++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,12 +27,13 @@ #include <sci/sci.h> #include <sec_rsrc.h> -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); -IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); -IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); +static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE; +static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END; +static const unsigned long BL31_RO_START = BL_CODE_BASE; +static const unsigned long BL31_RO_END = BL_CODE_END; +static const unsigned long BL31_RW_END = BL_END; + IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); -IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; diff --git a/plat/imx/imx8qx/include/platform_def.h b/plat/imx/imx8qx/include/platform_def.h index 108627f66..41475ffeb 100644 --- a/plat/imx/imx8qx/include/platform_def.h +++ b/plat/imx/imx8qx/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,12 +15,12 @@ #define PLATFORM_STACK_SIZE 0x400 #define CACHE_WRITEBACK_GRANULE 64 -#define PLAT_PRIMARY_CPU 0x0 -#define PLATFORM_MAX_CPU_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CORE_COUNT 4 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT U(4) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PWR_DOMAIN_AT_MAX_LVL U(1) #define PLAT_MAX_PWR_LVL U(2) diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index 86b7ab88f..9587d4859 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -18,13 +18,13 @@ #include "agilex_clock_manager.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" -#include "agilex_reset_manager.h" -#include "agilex_system_manager.h" #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" #include "socfpga_handoff.h" #include "socfpga_mailbox.h" #include "socfpga_private.h" +#include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" #include "wdt/watchdog.h" @@ -74,7 +74,10 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, socfpga_delay_timer_init(); init_ncore_ccu(); init_hard_memory_controller(); - enable_ns_bridge_access(); + mailbox_init(); + + if (!intel_mailbox_is_fpga_not_ready()) + socfpga_bridges_enable(); } @@ -107,8 +110,6 @@ void bl2_el3_plat_arch_setup(void) info.mmc_dev_type = MMC_IS_SD; info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; - mailbox_init(); - switch (boot_source) { case BOOT_SOURCE_SDMMC: dw_mmc_init(¶ms, &info); diff --git a/plat/intel/soc/agilex/include/agilex_memory_controller.h b/plat/intel/soc/agilex/include/agilex_memory_controller.h index 419bd2eff..3746d92fc 100644 --- a/plat/intel/soc/agilex/include/agilex_memory_controller.h +++ b/plat/intel/soc/agilex/include/agilex_memory_controller.h @@ -24,9 +24,6 @@ #define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ (((value) & 0x00000060) >> 5) -#define AGX_RSTMGR_BRGMODRST 0xffd1102c -#define AGX_RSTMGR_BRGMODRST_DDRSCH 0x00000040 - #define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 #define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 #define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218 diff --git a/plat/intel/soc/agilex/include/agilex_reset_manager.h b/plat/intel/soc/agilex/include/agilex_reset_manager.h deleted file mode 100644 index a1b6297c1..000000000 --- a/plat/intel/soc/agilex/include/agilex_reset_manager.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AGX_RESETMANAGER_H -#define AGX_RESETMANAGER_H - -#define AGX_RSTMGR_HDSKEN 0xffd11010 -#define AGX_RSTMGR_PER0MODRST 0xffd11024 -#define AGX_RSTMGR_PER1MODRST 0xffd11028 -#define AGX_RSTMGR_BRGMODRST 0xffd1102c - -#define AGX_RSTMGR_PER0MODRST_EMAC0 0x00000001 -#define AGX_RSTMGR_PER0MODRST_EMAC1 0x00000002 -#define AGX_RSTMGR_PER0MODRST_EMAC2 0x00000004 -#define AGX_RSTMGR_PER0MODRST_USB0 0x00000008 -#define AGX_RSTMGR_PER0MODRST_USB1 0x00000010 -#define AGX_RSTMGR_PER0MODRST_NAND 0x00000020 -#define AGX_RSTMGR_PER0MODRST_SDMMC 0x00000080 -#define AGX_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 -#define AGX_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 -#define AGX_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 -#define AGX_RSTMGR_PER0MODRST_USB0OCP 0x00000800 -#define AGX_RSTMGR_PER0MODRST_USB1OCP 0x00001000 -#define AGX_RSTMGR_PER0MODRST_NANDOCP 0x00002000 -#define AGX_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 -#define AGX_RSTMGR_PER0MODRST_DMA 0x00010000 -#define AGX_RSTMGR_PER0MODRST_SPIM0 0x00020000 -#define AGX_RSTMGR_PER0MODRST_SPIM1 0x00040000 -#define AGX_RSTMGR_PER0MODRST_SPIS0 0x00080000 -#define AGX_RSTMGR_PER0MODRST_SPIS1 0x00100000 -#define AGX_RSTMGR_PER0MODRST_DMAOCP 0x00200000 -#define AGX_RSTMGR_PER0MODRST_EMACPTP 0x00400000 -#define AGX_RSTMGR_PER0MODRST_DMAIF0 0x01000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF1 0x02000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF2 0x04000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF3 0x08000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF4 0x10000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF5 0x20000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF6 0x40000000 -#define AGX_RSTMGR_PER0MODRST_DMAIF7 0x80000000 - -#define AGX_RSTMGR_PER1MODRST_WATCHDOG0 0x1 -#define AGX_RSTMGR_PER1MODRST_WATCHDOG1 0x2 -#define AGX_RSTMGR_PER1MODRST_WATCHDOG2 0x4 -#define AGX_RSTMGR_PER1MODRST_WATCHDOG3 0x8 -#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 -#define AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 -#define AGX_RSTMGR_PER1MODRST_SPTIMER0 0x00000040 -#define AGX_RSTMGR_PER1MODRST_SPTIMER1 0x00000080 -#define AGX_RSTMGR_PER1MODRST_I2C0 0x00000100 -#define AGX_RSTMGR_PER1MODRST_I2C1 0x00000200 -#define AGX_RSTMGR_PER1MODRST_I2C2 0x00000400 -#define AGX_RSTMGR_PER1MODRST_I2C3 0x00000800 -#define AGX_RSTMGR_PER1MODRST_I2C4 0x00001000 -#define AGX_RSTMGR_PER1MODRST_UART0 0x00010000 -#define AGX_RSTMGR_PER1MODRST_UART1 0x00020000 -#define AGX_RSTMGR_PER1MODRST_GPIO0 0x01000000 -#define AGX_RSTMGR_PER1MODRST_GPIO1 0x02000000 - -#define AGX_RSTMGR_HDSKEN_FPGAHSEN 0x00000004 -#define AGX_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 -#define AGX_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 -#define AGX_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 -#define AGX_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 -#define AGX_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 - -#define AGX_RSTMGR_BRGMODRST_SOC2FPGA 0x1 -#define AGX_RSTMGR_BRGMODRST_LWHPS2FPGA 0x2 -#define AGX_RSTMGR_BRGMODRST_FPGA2SOC 0x4 -#define AGX_RSTMGR_BRGMODRST_MPFE 0x40 - -void deassert_peripheral_reset(void); -void config_hps_hs_before_warm_reset(void); - -#endif - diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h deleted file mode 100644 index be2953664..000000000 --- a/plat/intel/soc/agilex/include/agilex_system_manager.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AGX_SYSTEMMANAGER_H -#define AGX_SYSTEMMANAGER_H - -#define AGX_FIREWALL_SOC2FPGA 0xffd21200 -#define AGX_FIREWALL_LWSOC2FPGA 0xffd21300 - -#define AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000 -#define AGX_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004 -#define AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c -#define AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010 -#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c -#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020 -#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024 -#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028 -#define AGX_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c -#define AGX_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030 -#define AGX_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034 -#define AGX_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040 -#define AGX_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044 -#define AGX_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048 -#define AGX_NOC_FW_L4_PER_SCR_I2C0 0xffd21050 -#define AGX_NOC_FW_L4_PER_SCR_I2C1 0xffd21054 -#define AGX_NOC_FW_L4_PER_SCR_I2C2 0xffd21058 -#define AGX_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c -#define AGX_NOC_FW_L4_PER_SCR_I2C4 0xffd21060 -#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064 -#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068 -#define AGX_NOC_FW_L4_PER_SCR_UART0 0xffd2106c -#define AGX_NOC_FW_L4_PER_SCR_UART1 0xffd21070 - -#define AGX_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108 -#define AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c -#define AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110 -#define AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114 -#define AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118 -#define AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c -#define AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120 -#define AGX_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c -#define AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130 -#define AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134 -#define AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138 -#define AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140 -#define AGX_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144 -#define AGX_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148 -#define AGX_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c -#define AGX_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154 -#define AGX_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158 -#define AGX_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c -#define AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160 -#define AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164 -#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168 -#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c -#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170 -#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174 -#define AGX_NOC_FW_L4_SYS_SCR_DAP 0xffd21178 -#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190 -#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194 - -#define AGX_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 -#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 - -#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x)) -#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 -#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 -#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 - -#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 -#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) - -void enable_ns_bridge_access(void); - -#endif diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index a346cb5f8..b4e09210f 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -16,8 +16,13 @@ /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 -#define SOCFPGA_RSTMGR_OFST 0xffd11000 -#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020 +#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 +#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 + +#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 +#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 +#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 +#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 #endif /* PLAT_SOCFPGA_DEF_H */ diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index ef02a8dfb..f47c3f113 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -38,14 +38,14 @@ BL2_SOURCES += \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ plat/intel/soc/agilex/soc/agilex_memory_controller.c \ plat/intel/soc/agilex/soc/agilex_pinmux.c \ - plat/intel/soc/agilex/soc/agilex_reset_manager.c \ - plat/intel/soc/agilex/soc/agilex_system_manager.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c \ + plat/intel/soc/common/soc/socfpga_system_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ plat/intel/soc/common/drivers/ccu/ncore_ccu.c @@ -60,6 +60,7 @@ BL31_SOURCES += \ plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/common/socfpga_topology.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c index 96b669cfd..c6c48baea 100644 --- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c @@ -11,8 +11,8 @@ #include <lib/mmio.h> #include "agilex_clock_manager.h" -#include "agilex_system_manager.h" #include "socfpga_handoff.h" +#include "socfpga_system_manager.h" uint32_t wait_pll_lock(void) @@ -261,9 +261,9 @@ void config_clkmgr_handoff(handoff *hoff_ptr) CLKMGR_PERPLL_EN_RESET); /* Pass clock source frequency into scratch register */ - mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1), + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), hoff_ptr->hps_osc_clk_h); - mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2), + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), hoff_ptr->fpga_clk_hz); } @@ -275,14 +275,14 @@ uint32_t get_ref_clk(uint32_t pllglob) switch (CLKMGR_PSRC(pllglob)) { case CLKMGR_PLLGLOB_PSRC_EOSC1: - scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1); + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); ref_clk = mmio_read_32(scr_reg); break; case CLKMGR_PLLGLOB_PSRC_INTOSC: ref_clk = CLKMGR_INTOSC_HZ; break; case CLKMGR_PLLGLOB_PSRC_F2S: - scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2); + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); ref_clk = mmio_read_32(scr_reg); break; default: diff --git a/plat/intel/soc/agilex/soc/agilex_reset_manager.c b/plat/intel/soc/agilex/soc/agilex_reset_manager.c deleted file mode 100644 index 65d2029df..000000000 --- a/plat/intel/soc/agilex/soc/agilex_reset_manager.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <lib/mmio.h> - -#include "agilex_reset_manager.h" - -void deassert_peripheral_reset(void) -{ - mmio_clrbits_32(AGX_RSTMGR_PER1MODRST, - AGX_RSTMGR_PER1MODRST_WATCHDOG0 | - AGX_RSTMGR_PER1MODRST_WATCHDOG1 | - AGX_RSTMGR_PER1MODRST_WATCHDOG2 | - AGX_RSTMGR_PER1MODRST_WATCHDOG3 | - AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 | - AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 | - AGX_RSTMGR_PER1MODRST_SPTIMER0 | - AGX_RSTMGR_PER1MODRST_SPTIMER1 | - AGX_RSTMGR_PER1MODRST_I2C0 | - AGX_RSTMGR_PER1MODRST_I2C1 | - AGX_RSTMGR_PER1MODRST_I2C2 | - AGX_RSTMGR_PER1MODRST_I2C3 | - AGX_RSTMGR_PER1MODRST_I2C4 | - AGX_RSTMGR_PER1MODRST_UART0 | - AGX_RSTMGR_PER1MODRST_UART1 | - AGX_RSTMGR_PER1MODRST_GPIO0 | - AGX_RSTMGR_PER1MODRST_GPIO1); - - mmio_clrbits_32(AGX_RSTMGR_PER0MODRST, - AGX_RSTMGR_PER0MODRST_EMAC0OCP | - AGX_RSTMGR_PER0MODRST_EMAC1OCP | - AGX_RSTMGR_PER0MODRST_EMAC2OCP | - AGX_RSTMGR_PER0MODRST_USB0OCP | - AGX_RSTMGR_PER0MODRST_USB1OCP | - AGX_RSTMGR_PER0MODRST_NANDOCP | - AGX_RSTMGR_PER0MODRST_SDMMCOCP | - AGX_RSTMGR_PER0MODRST_DMAOCP); - - mmio_clrbits_32(AGX_RSTMGR_PER0MODRST, - AGX_RSTMGR_PER0MODRST_EMAC0 | - AGX_RSTMGR_PER0MODRST_EMAC1 | - AGX_RSTMGR_PER0MODRST_EMAC2 | - AGX_RSTMGR_PER0MODRST_USB0 | - AGX_RSTMGR_PER0MODRST_USB1 | - AGX_RSTMGR_PER0MODRST_NAND | - AGX_RSTMGR_PER0MODRST_SDMMC | - AGX_RSTMGR_PER0MODRST_DMA | - AGX_RSTMGR_PER0MODRST_SPIM0 | - AGX_RSTMGR_PER0MODRST_SPIM1 | - AGX_RSTMGR_PER0MODRST_SPIS0 | - AGX_RSTMGR_PER0MODRST_SPIS1 | - AGX_RSTMGR_PER0MODRST_EMACPTP | - AGX_RSTMGR_PER0MODRST_DMAIF0 | - AGX_RSTMGR_PER0MODRST_DMAIF1 | - AGX_RSTMGR_PER0MODRST_DMAIF2 | - AGX_RSTMGR_PER0MODRST_DMAIF3 | - AGX_RSTMGR_PER0MODRST_DMAIF4 | - AGX_RSTMGR_PER0MODRST_DMAIF5 | - AGX_RSTMGR_PER0MODRST_DMAIF6 | - AGX_RSTMGR_PER0MODRST_DMAIF7); - - mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, - AGX_RSTMGR_BRGMODRST_MPFE); -} - -void config_hps_hs_before_warm_reset(void) -{ - uint32_t or_mask = 0; - - or_mask |= AGX_RSTMGR_HDSKEN_SDRSELFREFEN; - or_mask |= AGX_RSTMGR_HDSKEN_FPGAHSEN; - or_mask |= AGX_RSTMGR_HDSKEN_ETRSTALLEN; - or_mask |= AGX_RSTMGR_HDSKEN_L2FLUSHEN; - or_mask |= AGX_RSTMGR_HDSKEN_L3NOC_DBG; - or_mask |= AGX_RSTMGR_HDSKEN_DEBUG_L3NOC; - - mmio_setbits_32(AGX_RSTMGR_HDSKEN, or_mask); -} - diff --git a/plat/intel/soc/agilex/soc/agilex_system_manager.c b/plat/intel/soc/agilex/soc/agilex_system_manager.c deleted file mode 100644 index 88e895d66..000000000 --- a/plat/intel/soc/agilex/soc/agilex_system_manager.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <lib/mmio.h> -#include <lib/utils_def.h> - -#include "agilex_system_manager.h" - -void enable_nonsecure_access(void) -{ - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC, - DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL); - - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL); - - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL); - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL); - - mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL); -} - -void enable_ns_bridge_access(void) -{ - mmio_write_32(AGX_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL); - mmio_write_32(AGX_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL); -} diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 8d04479df..8a681e69d 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -57,13 +57,13 @@ #define PLAT_MAX_PWR_LVL 1 #define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_OFF_STATE 2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) /* Interrupt related constant */ diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index c5f2fbe77..c4b9e5967 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -120,5 +120,6 @@ void mailbox_reset_cold(void); void mailbox_clear_response(void); uint32_t intel_mailbox_get_config_status(uint32_t cmd); +int intel_mailbox_is_fpga_not_ready(void); #endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/common/include/socfpga_reset_manager.h b/plat/intel/soc/common/include/socfpga_reset_manager.h index 3fbf242f4..637f8dfe5 100644 --- a/plat/intel/soc/common/include/socfpga_reset_manager.h +++ b/plat/intel/soc/common/include/socfpga_reset_manager.h @@ -7,12 +7,102 @@ #ifndef SOCFPGA_RESETMANAGER_H #define SOCFPGA_RESETMANAGER_H -#define SOCFPGA_RSTMGR_STAT 0xffd11000 -#define SOCFPGA_RSTMGR_HDSKEN 0xffd11010 -#define SOCFPGA_RSTMGR_COLDMODRST 0xffd11034 -#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0xffd11064 +#include "socfpga_plat_def.h" -#define SOCFPGA_RSTMGR_HDSKEN_SET 0x0000010D -#define SOCFPGA_RSTMGR_SDMWARMRST 0x00000002 + +/* Register Mapping */ + +#define SOCFPGA_RSTMGR_STAT 0x000 +#define SOCFPGA_RSTMGR_HDSKEN 0x010 +#define SOCFPGA_RSTMGR_MPUMODRST 0x020 +#define SOCFPGA_RSTMGR_PER0MODRST 0x024 +#define SOCFPGA_RSTMGR_PER1MODRST 0x028 +#define SOCFPGA_RSTMGR_BRGMODRST 0x02c +#define SOCFPGA_RSTMGR_COLDMODRST 0x034 +#define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064 + +/* Field Mapping */ + +#define RSTMGR_PER0MODRST_EMAC0 0x00000001 +#define RSTMGR_PER0MODRST_EMAC1 0x00000002 +#define RSTMGR_PER0MODRST_EMAC2 0x00000004 +#define RSTMGR_PER0MODRST_USB0 0x00000008 +#define RSTMGR_PER0MODRST_USB1 0x00000010 +#define RSTMGR_PER0MODRST_NAND 0x00000020 +#define RSTMGR_PER0MODRST_SDMMC 0x00000080 +#define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 +#define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 +#define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 +#define RSTMGR_PER0MODRST_USB0OCP 0x00000800 +#define RSTMGR_PER0MODRST_USB1OCP 0x00001000 +#define RSTMGR_PER0MODRST_NANDOCP 0x00002000 +#define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 +#define RSTMGR_PER0MODRST_DMA 0x00010000 +#define RSTMGR_PER0MODRST_SPIM0 0x00020000 +#define RSTMGR_PER0MODRST_SPIM1 0x00040000 +#define RSTMGR_PER0MODRST_SPIS0 0x00080000 +#define RSTMGR_PER0MODRST_SPIS1 0x00100000 +#define RSTMGR_PER0MODRST_DMAOCP 0x00200000 +#define RSTMGR_PER0MODRST_EMACPTP 0x00400000 +#define RSTMGR_PER0MODRST_DMAIF0 0x01000000 +#define RSTMGR_PER0MODRST_DMAIF1 0x02000000 +#define RSTMGR_PER0MODRST_DMAIF2 0x04000000 +#define RSTMGR_PER0MODRST_DMAIF3 0x08000000 +#define RSTMGR_PER0MODRST_DMAIF4 0x10000000 +#define RSTMGR_PER0MODRST_DMAIF5 0x20000000 +#define RSTMGR_PER0MODRST_DMAIF6 0x40000000 +#define RSTMGR_PER0MODRST_DMAIF7 0x80000000 + +#define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001 +#define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002 +#define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004 +#define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008 +#define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 +#define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 +#define RSTMGR_PER1MODRST_SPTIMER0 0x00000040 +#define RSTMGR_PER1MODRST_SPTIMER1 0x00000080 +#define RSTMGR_PER1MODRST_I2C0 0x00000100 +#define RSTMGR_PER1MODRST_I2C1 0x00000200 +#define RSTMGR_PER1MODRST_I2C2 0x00000400 +#define RSTMGR_PER1MODRST_I2C3 0x00000800 +#define RSTMGR_PER1MODRST_I2C4 0x00001000 +#define RSTMGR_PER1MODRST_UART0 0x00010000 +#define RSTMGR_PER1MODRST_UART1 0x00020000 +#define RSTMGR_PER1MODRST_GPIO0 0x01000000 +#define RSTMGR_PER1MODRST_GPIO1 0x02000000 + +#define RSTMGR_HDSKEN_FPGAHSEN 0x00000004 +#define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 +#define RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 +#define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 +#define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 +#define RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 + +#define RSTMGR_BRGMODRST_SOC2FPGA 0x1 +#define RSTMGR_BRGMODRST_LWHPS2FPGA 0x2 +#define RSTMGR_BRGMODRST_FPGA2SOC 0x4 +#define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 +#define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 +#define RSTMGR_BRGMODRST_MPFE 0x40 +#define RSTMGR_BRGMODRST_DDRSCH 0x40 + +/* Definitions */ + +#define RSTMGR_L2_MODRST 0x0100 +#define RSTMGR_HDSKEN_SET 0x010D + +/* Macros */ + +#define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE \ + + (SOCFPGA_RSTMGR_##_reg)) +#define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) + +/* Function Declarations */ + +void deassert_peripheral_reset(void); +void config_hps_hs_before_warm_reset(void); + +int socfpga_bridges_enable(void); +int socfpga_bridges_disable(void); #endif /* SOCFPGA_RESETMANAGER_H */ diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h new file mode 100644 index 000000000..68e30b894 --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_system_manager.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOCFPGA_SYSTEMMANAGER_H +#define SOCFPGA_SYSTEMMANAGER_H + +#include "socfpga_plat_def.h" + +/* System Manager Register Map */ + +#define SOCFPGA_SYSMGR_SDMMC 0x28 + +#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc +#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0 +#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4 + +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 + +/* Field Masking */ + +#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) + +#define IDLE_DATA_LWSOC2FPGA BIT(0) +#define IDLE_DATA_SOC2FPGA BIT(4) +#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) + +#define SCR_AXI_AP_MASK BIT(24) +#define SCR_FPGA2SOC_MASK BIT(16) +#define SCR_MPU_MASK BIT(0) +#define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ + | SCR_MPU_MASK) +#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 + +/* Macros */ + +#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + + (SOCFPGA_SYSMGR_##_reg)) + +#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ + + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) + +#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ + + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) + +/* L3 Interconnect Register Map */ +#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 +#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 +#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c +#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 +#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 +#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 +#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c +#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 +#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 +#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c +#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 + +#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 + +#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 +#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 + +void enable_ns_peripheral_access(void); +void enable_ns_bridge_access(void); + +#endif /* SOCFPGA_SYSTEMMANAGER_H */ diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index eb35c4a08..8d7c1d663 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -316,3 +316,13 @@ uint32_t intel_mailbox_get_config_status(uint32_t cmd) return MBOX_CFGSTAT_STATE_CONFIG; } + +int intel_mailbox_is_fpga_not_ready(void) +{ + int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); + + if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG) + ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + + return ret; +} diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c new file mode 100644 index 000000000..32604c914 --- /dev/null +++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <errno.h> +#include <lib/mmio.h> + +#include "socfpga_mailbox.h" +#include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" + + +void deassert_peripheral_reset(void) +{ + mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST), + RSTMGR_FIELD(PER1, WATCHDOG0) | + RSTMGR_FIELD(PER1, WATCHDOG1) | + RSTMGR_FIELD(PER1, WATCHDOG2) | + RSTMGR_FIELD(PER1, WATCHDOG3) | + RSTMGR_FIELD(PER1, L4SYSTIMER0) | + RSTMGR_FIELD(PER1, L4SYSTIMER1) | + RSTMGR_FIELD(PER1, SPTIMER0) | + RSTMGR_FIELD(PER1, SPTIMER1) | + RSTMGR_FIELD(PER1, I2C0) | + RSTMGR_FIELD(PER1, I2C1) | + RSTMGR_FIELD(PER1, I2C2) | + RSTMGR_FIELD(PER1, I2C3) | + RSTMGR_FIELD(PER1, I2C4) | + RSTMGR_FIELD(PER1, UART0) | + RSTMGR_FIELD(PER1, UART1) | + RSTMGR_FIELD(PER1, GPIO0) | + RSTMGR_FIELD(PER1, GPIO1)); + + mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), + RSTMGR_FIELD(PER0, EMAC0OCP) | + RSTMGR_FIELD(PER0, EMAC1OCP) | + RSTMGR_FIELD(PER0, EMAC2OCP) | + RSTMGR_FIELD(PER0, USB0OCP) | + RSTMGR_FIELD(PER0, USB1OCP) | + RSTMGR_FIELD(PER0, NANDOCP) | + RSTMGR_FIELD(PER0, SDMMCOCP) | + RSTMGR_FIELD(PER0, DMAOCP)); + + mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), + RSTMGR_FIELD(PER0, EMAC0) | + RSTMGR_FIELD(PER0, EMAC1) | + RSTMGR_FIELD(PER0, EMAC2) | + RSTMGR_FIELD(PER0, USB0) | + RSTMGR_FIELD(PER0, USB1) | + RSTMGR_FIELD(PER0, NAND) | + RSTMGR_FIELD(PER0, SDMMC) | + RSTMGR_FIELD(PER0, DMA) | + RSTMGR_FIELD(PER0, SPIM0) | + RSTMGR_FIELD(PER0, SPIM1) | + RSTMGR_FIELD(PER0, SPIS0) | + RSTMGR_FIELD(PER0, SPIS1) | + RSTMGR_FIELD(PER0, EMACPTP) | + RSTMGR_FIELD(PER0, DMAIF0) | + RSTMGR_FIELD(PER0, DMAIF1) | + RSTMGR_FIELD(PER0, DMAIF2) | + RSTMGR_FIELD(PER0, DMAIF3) | + RSTMGR_FIELD(PER0, DMAIF4) | + RSTMGR_FIELD(PER0, DMAIF5) | + RSTMGR_FIELD(PER0, DMAIF6) | + RSTMGR_FIELD(PER0, DMAIF7)); + +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX + mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), + RSTMGR_FIELD(BRG, MPFE)); +#endif +} + +void config_hps_hs_before_warm_reset(void) +{ + uint32_t or_mask = 0; + + or_mask |= RSTMGR_HDSKEN_SDRSELFREFEN; + or_mask |= RSTMGR_HDSKEN_FPGAHSEN; + or_mask |= RSTMGR_HDSKEN_ETRSTALLEN; + or_mask |= RSTMGR_HDSKEN_L2FLUSHEN; + or_mask |= RSTMGR_HDSKEN_L3NOC_DBG; + or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC; + + mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask); +} + +static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match) +{ + int time_out = 1000; + + while (time_out--) { + if ((mmio_read_32(addr) & mask) == match) { + return 0; + } + } + return -ETIMEDOUT; +} + +int socfpga_bridges_enable(void) +{ + /* Clear idle request */ + mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0); + + /* De-assert all bridges */ + mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0); + + /* Wait until idle ack becomes 0 */ + return poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), + IDLE_DATA_MASK, 0); +} + +int socfpga_bridges_disable(void) +{ + /* Set idle request */ + mmio_write_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), ~0); + + /* Enable NOC timeout */ + mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); + + /* Wait until each idle ack bit toggle to 1 */ + if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), + IDLE_DATA_MASK, IDLE_DATA_MASK)) + return -ETIMEDOUT; + + /* Wait until each idle status bit toggle to 1 */ + if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS), + IDLE_DATA_MASK, IDLE_DATA_MASK)) + return -ETIMEDOUT; + + /* Assert all bridges */ +#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 + mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), + ~(RSTMGR_FIELD(BRG, DDRSCH) | RSTMGR_FIELD(BRG, FPGA2SOC))); +#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX + mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), + ~(RSTMGR_FIELD(BRG, MPFE) | RSTMGR_FIELD(BRG, FPGA2SOC))); +#endif + + /* Disable NOC timeout */ + mmio_clrbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); + + return 0; +} diff --git a/plat/intel/soc/common/soc/socfpga_system_manager.c b/plat/intel/soc/common/soc/socfpga_system_manager.c new file mode 100644 index 000000000..a64053ca6 --- /dev/null +++ b/plat/intel/soc/common/soc/socfpga_system_manager.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> +#include <lib/utils_def.h> + +#include "socfpga_system_manager.h" + +void enable_nonsecure_access(void) +{ + enable_ns_peripheral_access(); + enable_ns_bridge_access(); +} + +void enable_ns_peripheral_access(void) +{ + mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_REGISTER), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_DATA), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_READ_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_WRITE_ECC), + DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(USB0_REGISTER), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(USB1_REGISTER), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(USB0_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(USB1_ECC), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER1), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_SLAVE0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_SLAVE1), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC1), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC2), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC0RX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC0TX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC1RX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC1TX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC2RX_ECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC2TX_ECC), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(SDMMC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(SDMMC_ECC), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO1), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C1), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C2), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C3), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(I2C4), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(SP_TIMER1), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_PER_SCR(UART0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_PER_SCR(UART1), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(DMA_ECC), DISABLE_L4_FIREWALL); + + + mmio_write_32(SOCFPGA_L4_SYS_SCR(OCRAM_ECC), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(CLK_MGR), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(IO_MGR), DISABLE_L4_FIREWALL); + + + mmio_write_32(SOCFPGA_L4_SYS_SCR(RST_MGR), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(SYS_MGR), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(OSC0_TIMER), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(OSC1_TIMER), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG0), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG1), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG2), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG3), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(DAP), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_PROBES), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL); + +#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 + mmio_clrbits_32(SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0, 0x03); + mmio_clrbits_32(SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0, 0x03); + + mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3)); +#endif + +} + +void enable_ns_bridge_access(void) +{ + mmio_write_32(SOCFPGA_SOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL); + mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL); +} diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index 1ba48eae1..d8a6c1980 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -47,7 +47,7 @@ int socfpga_pwr_domain_on(u_register_t mpidr) mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); /* release core reset */ - mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); + mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); return PSCI_E_SUCCESS; } @@ -78,7 +78,7 @@ void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state) __func__, i, target_state->pwr_domain_state[i]); /* assert core reset */ - mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); + mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); } @@ -117,7 +117,7 @@ void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state) __func__, i, target_state->pwr_domain_state[i]); /* release core reset */ - mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); + mmio_clrbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); } /******************************************************************************* @@ -148,13 +148,13 @@ static int socfpga_system_reset2(int is_vendor, int reset_type, mmio_write_32(L2_RESET_DONE_REG, L2_RESET_DONE_STATUS); /* Increase timeout */ - mmio_write_32(SOCFPGA_RSTMGR_HDSKTIMEOUT, 0xffffff); + mmio_write_32(SOCFPGA_RSTMGR(HDSKTIMEOUT), 0xffffff); /* Enable handshakes */ - mmio_setbits_32(SOCFPGA_RSTMGR_HDSKEN, SOCFPGA_RSTMGR_HDSKEN_SET); + mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET); /* Reset L2 module */ - mmio_setbits_32(SOCFPGA_RSTMGR_COLDMODRST, 0x100); + mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100); while (1) wfi(); diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index ce88fb489..41dae9e76 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -11,6 +11,7 @@ #include <tools_share/uuid.h> #include "socfpga_mailbox.h" +#include "socfpga_reset_manager.h" #include "socfpga_sip_svc.h" /* Number of SiP Calls implemented */ @@ -27,6 +28,7 @@ static int rcv_id; static int max_blocks; static uint32_t bytes_per_block; static uint32_t blocks_submitted; +static int is_partial_reconfig; struct fpga_config_info { uint32_t addr; @@ -93,9 +95,14 @@ static int intel_fpga_sdm_write_all(void) return 0; } -static uint32_t intel_mailbox_fpga_config_isdone(void) +static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) { - uint32_t ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); + uint32_t ret; + + if (query_type == 1) + ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); + else + ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); if (ret) { if (ret == MBOX_CFGSTAT_STATE_CONFIG) @@ -104,6 +111,12 @@ static uint32_t intel_mailbox_fpga_config_isdone(void) return INTEL_SIP_SMC_STATUS_ERROR; } + if (query_type != 1) { + /* full reconfiguration */ + if (!is_partial_reconfig) + socfpga_bridges_enable(); /* Enable bridge */ + } + return INTEL_SIP_SMC_STATUS_OK; } @@ -191,6 +204,8 @@ static int intel_fpga_config_start(uint32_t config_type) uint32_t response[3]; int status = 0; + is_partial_reconfig = config_type; + mailbox_clear_response(); mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); @@ -220,6 +235,12 @@ static int intel_fpga_config_start(uint32_t config_type) send_id = 0; rcv_id = 0; + /* full reconfiguration */ + if (!is_partial_reconfig) { + /* Disable bridge */ + socfpga_bridges_disable(); + } + return 0; } @@ -368,7 +389,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, SMC_UUID_RET(handle, intl_svc_uid); case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: - status = intel_mailbox_fpga_config_isdone(); + status = intel_mailbox_fpga_config_isdone(x1); SMC_RET4(handle, status, 0, 0, 0); case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 85a60d651..7d183db0d 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -19,11 +19,11 @@ #include "socfpga_handoff.h" #include "socfpga_mailbox.h" #include "socfpga_private.h" +#include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" #include "s10_clock_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" -#include "s10_reset_manager.h" -#include "s10_system_manager.h" #include "wdt/watchdog.h" @@ -72,6 +72,10 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, socfpga_delay_timer_init(); init_hard_memory_controller(); + mailbox_init(); + + if (!intel_mailbox_is_fpga_not_ready()) + socfpga_bridges_enable(); } diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 29bd1763f..29f57c467 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -17,11 +17,12 @@ #include <platform_def.h> #include "socfpga_private.h" -#include "s10_reset_manager.h" +#include "socfpga_reset_manager.h" +#include "socfpga_system_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" #include "s10_clock_manager.h" -#include "s10_system_manager.h" + static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; diff --git a/plat/intel/soc/stratix10/include/s10_memory_controller.h b/plat/intel/soc/stratix10/include/s10_memory_controller.h index ad7cb9db1..155b2795e 100644 --- a/plat/intel/soc/stratix10/include/s10_memory_controller.h +++ b/plat/intel/soc/stratix10/include/s10_memory_controller.h @@ -22,8 +22,6 @@ #define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ (((value) & 0x00000060) >> 5) -#define S10_RSTMGR_BRGMODRST 0xffd1102c -#define S10_RSTMGR_BRGMODRST_DDRSCH 0x00000040 #define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 #define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 diff --git a/plat/intel/soc/stratix10/include/s10_reset_manager.h b/plat/intel/soc/stratix10/include/s10_reset_manager.h deleted file mode 100644 index 731a8ddb6..000000000 --- a/plat/intel/soc/stratix10/include/s10_reset_manager.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __S10_RESETMANAGER_H__ -#define __S10_RESETMANAGER_H__ - -#define S10_RSTMGR_PER0MODRST 0xffd11024 -#define S10_RSTMGR_PER1MODRST 0xffd11028 -#define S10_RSTMGR_HDSKEN 0xffd11010 - -#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001 -#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002 -#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004 -#define S10_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 -#define S10_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 -#define S10_RSTMGR_PER0MODRST_DMAOCP 0x00200000 -#define S10_RSTMGR_PER0MODRST_DMA 0x00010000 -#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001 -#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002 -#define S10_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 -#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004 -#define S10_RSTMGR_PER0MODRST_EMACPTP 0x00400000 -#define S10_RSTMGR_PER0MODRST_NANDOCP 0x00002000 -#define S10_RSTMGR_PER0MODRST_NAND 0x00000020 -#define S10_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 -#define S10_RSTMGR_PER0MODRST_SDMMC 0x00000080 -#define S10_RSTMGR_PER0MODRST_SPIM0 0x00020000 -#define S10_RSTMGR_PER0MODRST_SPIM1 0x00040000 -#define S10_RSTMGR_PER0MODRST_SPIS0 0x00080000 -#define S10_RSTMGR_PER0MODRST_SPIS1 0x00100000 -#define S10_RSTMGR_PER0MODRST_USB0OCP 0x00000800 -#define S10_RSTMGR_PER0MODRST_USB0 0x00000008 -#define S10_RSTMGR_PER0MODRST_USB1OCP 0x00001000 -#define S10_RSTMGR_PER0MODRST_USB1 0x00000010 - -#define S10_RSTMGR_PER1MODRST_WATCHDOG0 0x1 -#define S10_RSTMGR_PER1MODRST_WATCHDOG1 0x2 -#define S10_RSTMGR_PER1MODRST_WATCHDOG2 0x4 -#define S10_RSTMGR_PER1MODRST_WATCHDOG3 0x8 -#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000 -#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000 -#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000 -#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000 -#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100 -#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100 -#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200 -#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200 -#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400 -#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400 -#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800 -#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800 -#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000 -#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000 -#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 -#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 -#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040 -#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040 -#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080 -#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080 -#define S10_RSTMGR_PER1MODRST_UART0 0x00010000 -#define S10_RSTMGR_PER1MODRST_UART0 0x00010000 -#define S10_RSTMGR_PER1MODRST_UART1 0x00020000 -#define S10_RSTMGR_PER1MODRST_UART1 0x00020000 -#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 -#define S10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 -#define S10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004 -#define S10_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 -#define S10_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 - -#define S10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 -#define S10_RSTMGR_PER0MODRST_DMAIF0 0x01000000 -#define S10_RSTMGR_PER0MODRST_DMAIF1 0x02000000 -#define S10_RSTMGR_PER0MODRST_DMAIF2 0x04000000 -#define S10_RSTMGR_PER0MODRST_DMAIF3 0x08000000 -#define S10_RSTMGR_PER0MODRST_DMAIF4 0x10000000 -#define S10_RSTMGR_PER0MODRST_DMAIF5 0x20000000 -#define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000 -#define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000 - -void deassert_peripheral_reset(void); -void config_hps_hs_before_warm_reset(void); - -#endif - diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h deleted file mode 100644 index 4abfedb56..000000000 --- a/plat/intel/soc/stratix10/include/s10_system_manager.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000 -#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004 -#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c -#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010 -#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c -#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020 -#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024 -#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028 -#define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c -#define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030 -#define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034 -#define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040 -#define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044 -#define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048 -#define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050 -#define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054 -#define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058 -#define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c -#define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060 -#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064 -#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068 -#define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c -#define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070 - -#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108 -#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c -#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110 -#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114 -#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118 -#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c -#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120 -#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c -#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130 -#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134 -#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138 -#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140 -#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144 -#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148 -#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c -#define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154 -#define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158 -#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c -#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160 -#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164 -#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168 -#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c -#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170 -#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174 -#define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178 -#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190 -#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194 - -#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 -#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 - -#define S10_SYSMGR_CORE(x) (0xffd12000 + (x)) -#define SYSMGR_MMC 0x28 -#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0) -#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 -#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 -#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 - - -#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) - diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index ab723f79d..9dc51514c 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -15,8 +15,14 @@ /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 -#define SOCFPGA_RSTMGR_OFST 0xffd11000 -#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020 +#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 +#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 + +#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 +#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 +#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 +#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 + #endif /* PLATSOCFPGA_DEF_H */ diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index e7251c428..efbab24b3 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -38,14 +38,14 @@ BL2_SOURCES += \ plat/intel/soc/stratix10/soc/s10_clock_manager.c \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ plat/intel/soc/stratix10/soc/s10_pinmux.c \ - plat/intel/soc/stratix10/soc/s10_reset_manager.c \ - plat/intel/soc/stratix10/soc/s10_system_manager.c \ plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ plat/intel/soc/common/socfpga_storage.c \ plat/intel/soc/common/soc/socfpga_handoff.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c \ + plat/intel/soc/common/soc/socfpga_system_manager.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c @@ -59,6 +59,7 @@ BL31_SOURCES += \ plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/common/socfpga_topology.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c index e4ff7acf2..1e092dec4 100644 --- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c @@ -12,8 +12,8 @@ #include <platform_def.h> #include "s10_clock_manager.h" -#include "s10_system_manager.h" #include "socfpga_handoff.h" +#include "socfpga_system_manager.h" void wait_pll_lock(void) @@ -190,9 +190,9 @@ void config_clkmgr_handoff(handoff *hoff_ptr) ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK); /* Pass clock source frequency into scratch register */ - mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1), + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), hoff_ptr->hps_osc_clk_h); - mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2), + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), hoff_ptr->fpga_clk_hz); } @@ -205,14 +205,14 @@ uint32_t get_ref_clk(uint32_t pllglob) switch (ALT_CLKMGR_PSRC(pllglob)) { case ALT_CLKMGR_PLLGLOB_PSRC_EOSC1: - scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1); + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); ref_clk = mmio_read_32(scr_reg); break; case ALT_CLKMGR_PLLGLOB_PSRC_INTOSC: ref_clk = ALT_CLKMGR_INTOSC_HZ; break; case ALT_CLKMGR_PLLGLOB_PSRC_F2S: - scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2); + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); ref_clk = mmio_read_32(scr_reg); break; default: diff --git a/plat/intel/soc/stratix10/soc/s10_memory_controller.c b/plat/intel/soc/stratix10/soc/s10_memory_controller.c index cb4525149..ac756abac 100644 --- a/plat/intel/soc/stratix10/soc/s10_memory_controller.c +++ b/plat/intel/soc/stratix10/soc/s10_memory_controller.c @@ -15,6 +15,7 @@ #include <string.h> #include "s10_memory_controller.h" +#include "socfpga_reset_manager.h" #define ALT_CCU_NOC_DI_SET_MSK 0x10 @@ -184,7 +185,7 @@ int init_hard_memory_controller(void) return status; } - mmio_clrbits_32(S10_RSTMGR_BRGMODRST, S10_RSTMGR_BRGMODRST_DDRSCH); + mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_FIELD(BRG, DDRSCH)); status = mem_calibration(); if (status) { diff --git a/plat/intel/soc/stratix10/soc/s10_reset_manager.c b/plat/intel/soc/stratix10/soc/s10_reset_manager.c deleted file mode 100644 index 8b7420bf1..000000000 --- a/plat/intel/soc/stratix10/soc/s10_reset_manager.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <arch_helpers.h> -#include <assert.h> -#include <common/bl_common.h> -#include <common/debug.h> -#include <drivers/arm/gicv2.h> -#include <drivers/console.h> -#include <lib/mmio.h> -#include <plat/common/platform.h> -#include <platform_def.h> -#include "s10_reset_manager.h" - -void deassert_peripheral_reset(void) -{ - mmio_clrbits_32(S10_RSTMGR_PER1MODRST, - S10_RSTMGR_PER1MODRST_WATCHDOG0 | - S10_RSTMGR_PER1MODRST_WATCHDOG1 | - S10_RSTMGR_PER1MODRST_WATCHDOG2 | - S10_RSTMGR_PER1MODRST_WATCHDOG3 | - S10_RSTMGR_PER1MODRST_L4SYSTIMER0 | - S10_RSTMGR_PER1MODRST_L4SYSTIMER1 | - S10_RSTMGR_PER1MODRST_SPTIMER0 | - S10_RSTMGR_PER1MODRST_SPTIMER1 | - S10_RSTMGR_PER1MODRST_I2C0 | - S10_RSTMGR_PER1MODRST_I2C1 | - S10_RSTMGR_PER1MODRST_I2C2 | - S10_RSTMGR_PER1MODRST_I2C3 | - S10_RSTMGR_PER1MODRST_I2C4 | - S10_RSTMGR_PER1MODRST_UART0 | - S10_RSTMGR_PER1MODRST_UART1 | - S10_RSTMGR_PER1MODRST_GPIO0 | - S10_RSTMGR_PER1MODRST_GPIO1); - - mmio_clrbits_32(S10_RSTMGR_PER0MODRST, - S10_RSTMGR_PER0MODRST_EMAC0OCP | - S10_RSTMGR_PER0MODRST_EMAC1OCP | - S10_RSTMGR_PER0MODRST_EMAC2OCP | - S10_RSTMGR_PER0MODRST_USB0OCP | - S10_RSTMGR_PER0MODRST_USB1OCP | - S10_RSTMGR_PER0MODRST_NANDOCP | - S10_RSTMGR_PER0MODRST_SDMMCOCP | - S10_RSTMGR_PER0MODRST_DMAOCP); - - mmio_clrbits_32(S10_RSTMGR_PER0MODRST, - S10_RSTMGR_PER0MODRST_EMAC0 | - S10_RSTMGR_PER0MODRST_EMAC1 | - S10_RSTMGR_PER0MODRST_EMAC2 | - S10_RSTMGR_PER0MODRST_USB0 | - S10_RSTMGR_PER0MODRST_USB1 | - S10_RSTMGR_PER0MODRST_NAND | - S10_RSTMGR_PER0MODRST_SDMMC | - S10_RSTMGR_PER0MODRST_DMA | - S10_RSTMGR_PER0MODRST_SPIM0 | - S10_RSTMGR_PER0MODRST_SPIM1 | - S10_RSTMGR_PER0MODRST_SPIS0 | - S10_RSTMGR_PER0MODRST_SPIS1 | - S10_RSTMGR_PER0MODRST_EMACPTP | - S10_RSTMGR_PER0MODRST_DMAIF0 | - S10_RSTMGR_PER0MODRST_DMAIF1 | - S10_RSTMGR_PER0MODRST_DMAIF2 | - S10_RSTMGR_PER0MODRST_DMAIF3 | - S10_RSTMGR_PER0MODRST_DMAIF4 | - S10_RSTMGR_PER0MODRST_DMAIF5 | - S10_RSTMGR_PER0MODRST_DMAIF6 | - S10_RSTMGR_PER0MODRST_DMAIF7); - -} - -void config_hps_hs_before_warm_reset(void) -{ - uint32_t or_mask = 0; - - or_mask |= S10_RSTMGR_HDSKEN_SDRSELFREFEN; - or_mask |= S10_RSTMGR_HDSKEN_FPGAHSEN; - or_mask |= S10_RSTMGR_HDSKEN_ETRSTALLEN; - or_mask |= S10_RSTMGR_HDSKEN_L2FLUSHEN; - or_mask |= S10_RSTMGR_HDSKEN_L3NOC_DBG; - or_mask |= S10_RSTMGR_HDSKEN_DEBUG_L3NOC; - - mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask); -} - diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c deleted file mode 100644 index a2ed5a3ed..000000000 --- a/plat/intel/soc/stratix10/soc/s10_system_manager.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <lib/mmio.h> -#include <lib/utils_def.h> -#include "s10_system_manager.h" - -void enable_nonsecure_access(void) -{ - mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC, - DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL); - - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL); - - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL); - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL); - - mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL); - - mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03); - mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03); - - mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3)); - -} - diff --git a/plat/layerscape/board/ls1043/include/platform_def.h b/plat/layerscape/board/ls1043/include/platform_def.h index b6130001c..8b0a94ae3 100644 --- a/plat/layerscape/board/ls1043/include/platform_def.h +++ b/plat/layerscape/board/ls1043/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,18 +19,18 @@ #define FIRMWARE_WELCOME_STR_LS1043_BL32 "Welcome to LS1043 BL32 Phase, TSP\n" /* Required platform porting definitions */ -#define PLAT_PRIMARY_CPU 0x0 +#define PLAT_PRIMARY_CPU U(0x0) #define PLAT_MAX_PWR_LVL LS_PWR_LVL1 -#define PLATFORM_CORE_COUNT 4 +#define PLATFORM_CORE_COUNT U(4) #define COUNTER_FREQUENCY 25000000 /* 25MHz */ /* * Required LS standard platform porting definitions */ -#define PLAT_LS_CLUSTER_COUNT 1 -#define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX 4 -#define LS1043_CLUSTER_COUNT 1 -#define LS1043_MAX_CPUS_PER_CLUSTER 4 +#define PLAT_LS_CLUSTER_COUNT U(1) +#define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX U(4) +#define LS1043_CLUSTER_COUNT U(1) +#define LS1043_MAX_CPUS_PER_CLUSTER U(4) #define LS_DRAM1_BASE 0x80000000 #define LS_DRAM2_BASE 0x880000000 diff --git a/plat/marvell/a3700/common/include/platform_def.h b/plat/marvell/a3700/common/include/platform_def.h index 591f04585..e6660d407 100644 --- a/plat/marvell/a3700/common/include/platform_def.h +++ b/plat/marvell/a3700/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2016-2019 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -78,7 +78,7 @@ (PLAT_MARVELL_ATF_LOAD_ADDR + 0x20000) #define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000 -#define PLAT_MARVELL_CLUSTER_CORE_COUNT 2 +#define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2) /* DRAM[2MB..66MB] is used as Trusted ROM */ #define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR /* 64 MB TODO: reduce this to minimum needed according to fip image size*/ diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h index b9c2e0ed7..ec1c9036c 100644 --- a/plat/marvell/a8k/common/include/platform_def.h +++ b/plat/marvell/a8k/common/include/platform_def.h @@ -86,8 +86,8 @@ #define PLAT_MARVELL_NORTHB_COUNT 1 -#define PLAT_MARVELL_CLUSTER_COUNT 2 -#define PLAT_MARVELL_CLUSTER_CORE_COUNT 2 +#define PLAT_MARVELL_CLUSTER_COUNT U(2) +#define PLAT_MARVELL_CLUSTER_CORE_COUNT U(2) #define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \ PLAT_MARVELL_CLUSTER_CORE_COUNT) diff --git a/plat/mediatek/mt6795/include/platform_def.h b/plat/mediatek/mt6795/include/platform_def.h index 301610d4c..b353a3d3b 100644 --- a/plat/mediatek/mt6795/include/platform_def.h +++ b/plat/mediatek/mt6795/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -145,13 +145,13 @@ #define PLAT_MAX_OFF_STATE U(2) #define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/mediatek/mt8173/include/platform_def.h b/plat/mediatek/mt8173/include/platform_def.h index 205e26387..22129db13 100644 --- a/plat/mediatek/mt8173/include/platform_def.h +++ b/plat/mediatek/mt8173/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,13 +40,13 @@ #define PLAT_MAX_PWR_LVL U(2) #define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_OFF_STATE U(2) -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(2) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h index ad81a3331..49a0f805e 100644 --- a/plat/mediatek/mt8183/include/platform_def.h +++ b/plat/mediatek/mt8183/include/platform_def.h @@ -268,13 +268,13 @@ INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ #define PLAT_MAX_OFF_STATE U(2) #define PLATFORM_CACHE_LINE_SIZE 64 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c index 68b450e52..ae899c424 100644 --- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c +++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> #include <bpmp_ipc.h> -#include <debug.h> +#include <common/debug.h> #include <drivers/delay_timer.h> #include <errno.h> #include <lib/mmio.h> diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c index 4212eca1d..57daf6aeb 100644 --- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c +++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch_helpers.h> #include <assert.h> -#include <debug.h> +#include <common/debug.h> #include <errno.h> #include <stddef.h> #include <string.h> diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index 25fd84cdc..cbe3377b0 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -42,11 +42,12 @@ extern void memcpy16(void *dest, const void *src, unsigned int length); ******************************************************************************/ IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); -IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END); -IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE); -IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END); -IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START); -IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END); + +static const uint64_t BL31_RW_END = BL_END; +static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; +static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; +static const uint64_t TEXT_START = BL_CODE_BASE; +static const uint64_t TEXT_END = BL_CODE_END; extern uint64_t tegra_bl31_phys_base; diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index a98aa2da8..df1d65630 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -54,6 +54,11 @@ #define MISCREG_PFCFG U(0x200C) /******************************************************************************* + * Tegra General Purpose Centralised DMA constants + ******************************************************************************/ +#define TEGRA_GPCDMA_BASE U(0x02610000) + +/******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ #define TEGRA_MC_STREAMID_BASE U(0x02C00000) @@ -127,6 +132,18 @@ #define TEGRA_UARTG_BASE U(0x0C290000) /******************************************************************************* + * XUSB PADCTL + ******************************************************************************/ +#define TEGRA_XUSB_PADCTL_BASE U(0x03520000) +#define TEGRA_XUSB_PADCTL_SIZE U(0x10000) +#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) +#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) + +/******************************************************************************* * Tegra Fuse Controller related constants ******************************************************************************/ #define TEGRA_FUSE_BASE U(0x03820000) @@ -152,6 +169,14 @@ #define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) /******************************************************************************* + * Tegra HSP doorbell #0 constants + ******************************************************************************/ +#define TEGRA_HSP_DBELL_BASE U(0x03C90000) +#define HSP_DBELL_1_ENABLE U(0x104) +#define HSP_DBELL_3_TRIGGER U(0x300) +#define HSP_DBELL_3_ENABLE U(0x304) + +/******************************************************************************* * Tegra hardware synchronization primitives for the SPE engine ******************************************************************************/ #define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000) @@ -172,6 +197,7 @@ * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE U(0x0C390000) +#define SECURE_SCRATCH_RSV75 U(0x2BC) #define SECURE_SCRATCH_RSV81_LO U(0x2EC) #define SECURE_SCRATCH_RSV81_HI U(0x2F0) #define SECURE_SCRATCH_RSV97 U(0x36C) @@ -180,8 +206,14 @@ #define SECURE_SCRATCH_RSV109_LO U(0x3CC) #define SECURE_SCRATCH_RSV109_HI U(0x3D0) -#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV81_LO -#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV81_HI +#define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 +#define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF) +#define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0) +#define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000) +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16) +#define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 #define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO #define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI @@ -207,6 +239,13 @@ #define TEGRA_TZRAM_SIZE U(0x40000) /******************************************************************************* + * Tegra CCPLEX-BPMP IPC constants + ******************************************************************************/ +#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000) +#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000) +#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */ + +/******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ #define TEGRA_CAR_RESET_BASE U(0x20000000) @@ -214,18 +253,8 @@ #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C) #define GPU_RESET_BIT (U(1) << 0) #define GPU_SET_BIT (U(1) << 0) - -/******************************************************************************* - * XUSB PADCTL - ******************************************************************************/ -#define TEGRA_XUSB_PADCTL_BASE U(0x3520000) -#define TEGRA_XUSB_PADCTL_SIZE U(0x10000) -#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) -#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) +#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) +#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) /******************************************************************************* * XUSB STREAMIDs diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 09dcce3c0..34bdd7557 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -18,14 +18,14 @@ #define MC_CLIENT_ORDER_ID_27 U(0x2a6c) #define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U #define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4) -#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (1U << 4) +#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (2U << 4) #define MC_CLIENT_ORDER_ID_28 U(0x2a70) #define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U #define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4) #define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4) #define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) -#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12) +#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (1U << 12) #define mc_client_order_id(val, id, client) \ ((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \ @@ -53,6 +53,11 @@ #define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28) #define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28) +#define MC_HUB_PC_VC_ID_12 U(0x2aa8) +#define MC_HUB_PC_VC_ID_12_RESET_VAL 0x11001011U +#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID_MASK (0x3U << 12) +#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID (VC_NISO << 12) + #define mc_hub_vc_id(val, id, client) \ ((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \ MC_HUB_PC_VC_ID_##id##_##client##_VC_ID) @@ -105,7 +110,7 @@ #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17) @@ -531,7 +536,10 @@ #define MC_CLIENT_HOTRESET_STATUS2 0x1898U #define MC_COALESCE_CTRL 0x2930U -#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31) +#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31) +#define MC_COALESCE_CONFIG_6_0 0x294cU +#define MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED (1U << 8) +#define MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED (1U << 14) /******************************************************************************* * Tegra TSA Controller constants @@ -649,5 +657,29 @@ #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) +#define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK (ULL(0x3) << 15) +#define TSA_CONFIG_CSW_SO_DEV_HUB2 (ULL(2) << 15) + +#define REORDER_DEPTH_LIMIT 16 +#define TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK (ULL(0x7FF) << 21) +#define reorder_depth_limit(limit) (ULL(limit) << 21) + +#define tsa_read_32(client) \ + mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client) + +#define mc_set_tsa_hub2(val, client) \ + { \ + mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ + ((val & ~TSA_CONFIG_CSW_SO_DEV_HUBID_MASK) | \ + TSA_CONFIG_CSW_SO_DEV_HUB2)); \ + } + +#define mc_set_tsa_depth_limit(limit, client) \ + { \ + uint32_t val = mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client); \ + mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ + ((val & ~TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK) | \ + reorder_depth_limit(limit))); \ + } #endif /* TEGRA_MC_DEF_H */ diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h index 9741d084f..1fe3aad39 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h @@ -45,10 +45,6 @@ /* declarations for NVG handler functions */ uint64_t nvg_get_version(void); -int32_t nvg_enable_power_perf_mode(void); -int32_t nvg_disable_power_perf_mode(void); -int32_t nvg_enable_power_saver_modes(void); -int32_t nvg_disable_power_saver_modes(void); void nvg_set_wake_time(uint32_t wake_time); void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask); @@ -57,19 +53,19 @@ uint64_t nvg_get_cstate_stat_query_value(void); int32_t nvg_is_sc7_allowed(void); int32_t nvg_online_core(uint32_t core); int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); -int32_t nvg_roc_clean_cache(void); -int32_t nvg_roc_flush_cache(void); -int32_t nvg_roc_clean_cache_trbits(void); int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); +int32_t nvg_roc_clean_cache_trbits(void); +void nvg_enable_strict_checking_mode(void); +void nvg_system_shutdown(void); +void nvg_system_reboot(void); + +/* declarations for assembly functions */ void nvg_set_request_data(uint64_t req, uint64_t data); void nvg_set_request(uint64_t req); uint64_t nvg_get_result(void); uint64_t nvg_cache_clean(void); uint64_t nvg_cache_clean_inval(void); uint64_t nvg_cache_inval_all(void); -void nvg_enable_strict_checking_mode(void); -void nvg_system_shutdown(void); -void nvg_system_reboot(void); /* MCE helper functions */ void mce_enable_strict_checking(void); diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 06cbb4a2e..ccc46655a 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -20,61 +20,65 @@ */ enum { TEGRA_NVG_VERSION_MAJOR = 6, - TEGRA_NVG_VERSION_MINOR = 4 + TEGRA_NVG_VERSION_MINOR = 6 }; typedef enum { - TEGRA_NVG_CHANNEL_VERSION = 0, - TEGRA_NVG_CHANNEL_POWER_PERF = 1, - TEGRA_NVG_CHANNEL_POWER_MODES = 2, - TEGRA_NVG_CHANNEL_WAKE_TIME = 3, - TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, - TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, - TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, - TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, - TEGRA_NVG_CHANNEL_SHUTDOWN = 42, - TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, - TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, - TEGRA_NVG_CHANNEL_CC3_CTRL = 45, - TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, - TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, - TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, - TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, - TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, - TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, - TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, - TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, - TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, - TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, - TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, - TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, - TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, - TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, - TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, + TEGRA_NVG_CHANNEL_VERSION = 0, + TEGRA_NVG_CHANNEL_POWER_PERF = 1, + TEGRA_NVG_CHANNEL_POWER_MODES = 2, + TEGRA_NVG_CHANNEL_WAKE_TIME = 3, + TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, + TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, + TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, + TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, + TEGRA_NVG_CHANNEL_NUM_CORES = 20, + TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID = 21, + TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING = 22, + TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR = 23, + TEGRA_NVG_CHANNEL_SHUTDOWN = 42, + TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, + TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, + TEGRA_NVG_CHANNEL_CC3_CTRL = 45, + TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, + TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, + TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, + TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, + TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, + TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, + TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, + TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, + TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, + TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, + TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, TEGRA_NVG_CHANNEL_LAST_INDEX } tegra_nvg_channel_id_t; typedef enum { - NVG_STAT_QUERY_SC7_ENTRIES = 1, - NVG_STAT_QUERY_CC6_ENTRIES = 6, - NVG_STAT_QUERY_CG7_ENTRIES = 7, + NVG_STAT_QUERY_SC7_ENTRIES = 1, + NVG_STAT_QUERY_CC6_ENTRIES = 6, + NVG_STAT_QUERY_CG7_ENTRIES = 7, NVG_STAT_QUERY_C6_ENTRIES = 10, NVG_STAT_QUERY_C7_ENTRIES = 14, NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, @@ -113,7 +117,13 @@ typedef enum { } tegra_nvg_core_sleep_state_t; typedef enum { + TEGRA_NVG_SHUTDOWN = 0U, + TEGRA_NVG_REBOOT = 1U +} tegra_nvg_shutdown_reboot_state_t; + +typedef enum { TEGRA_NVG_CLUSTER_CC0 = 0, + TEGRA_NVG_CLUSTER_AUTO_CC1 = 1, TEGRA_NVG_CLUSTER_CC6 = 6 } tegra_nvg_cluster_sleep_state_t; @@ -128,11 +138,6 @@ typedef enum { TEGRA_NVG_SYSTEM_SC8 = 8 } tegra_nvg_system_sleep_state_t; -typedef enum { - TEGRA_NVG_SHUTDOWN = 0U, - TEGRA_NVG_REBOOT = 1U, -} tegra_nvg_shutdown_reboot_state_t; - // --------------------------------------------------------------------------- // NVG Data subformats // --------------------------------------------------------------------------- @@ -206,18 +211,31 @@ typedef union { typedef union { uint64_t flat; struct nvg_cstate_info_channel_t { - uint32_t cluster_state : 3; - uint32_t reserved_6_3 : 4; - uint32_t update_cluster : 1; - uint32_t cg_cstate : 3; - uint32_t reserved_14_11 : 4; - uint32_t update_cg : 1; - uint32_t system_cstate : 4; - uint32_t reserved_22_20 : 3; - uint32_t update_system : 1; - uint32_t reserved_30_24 : 7; - uint32_t update_wake_mask : 1; - uint32_t wake_mask : 32; + uint32_t cluster_state : 3; + uint32_t reserved_6_3 : 4; + uint32_t update_cluster : 1; + uint32_t cg_cstate : 3; + uint32_t reserved_14_11 : 4; + uint32_t update_cg : 1; + uint32_t system_cstate : 4; + uint32_t reserved_22_20 : 3; + uint32_t update_system : 1; + uint32_t reserved_30_24 : 7; + uint32_t update_wake_mask : 1; + union { + uint32_t flat : 32; + struct { + uint32_t vfiq : 1; + uint32_t virq : 1; + uint32_t fiq : 1; + uint32_t irq : 1; + uint32_t serror : 1; + uint32_t reserved_10_5 : 6; + uint32_t fiqout : 1; + uint32_t irqout : 1; + uint32_t reserved_31_13 : 19; + } carmel; + } wake_mask; } bits; } nvg_cstate_info_channel_t; @@ -241,6 +259,52 @@ typedef union { typedef union { uint64_t flat; + struct nvg_num_cores_channel_t { + uint32_t num_cores : 4; + uint32_t reserved_31_4 : 28; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_num_cores_channel_t; + +typedef union { + uint64_t flat; + struct nvg_unique_logical_id_channel_t { + uint32_t unique_core_id : 3; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_unique_logical_id_channel_t; + +typedef union { + uint64_t flat; + struct nvg_logical_to_physical_mappings_channel_t { + uint32_t lcore0_pcore_id : 4; + uint32_t lcore1_pcore_id : 4; + uint32_t lcore2_pcore_id : 4; + uint32_t lcore3_pcore_id : 4; + uint32_t lcore4_pcore_id : 4; + uint32_t lcore5_pcore_id : 4; + uint32_t lcore6_pcore_id : 4; + uint32_t lcore7_pcore_id : 4; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_logical_to_physical_mappings_channel_t; + +typedef union { + uint64_t flat; + struct nvg_logical_to_mpidr_channel_write_t { + uint32_t lcore_id : 3; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; + } write; + struct nvg_logical_to_mpidr_channel_read_t { + uint32_t mpidr : 32; + uint32_t reserved_63_32 : 32; + } read; +} nvg_logical_to_mpidr_channel_t; + +typedef union { + uint64_t flat; struct nvg_is_sc7_allowed_channel_t { uint32_t is_sc7_allowed : 1; uint32_t reserved_31_1 : 31; @@ -260,50 +324,50 @@ typedef union { typedef union { uint64_t flat; struct nvg_cc3_control_channel_t { - uint32_t freq_req : 8; - uint32_t reserved_30_8 : 23; + uint32_t freq_req : 9; + uint32_t reserved_30_9 : 22; uint32_t enable : 1; uint32_t reserved_63_32 : 32; } bits; } nvg_cc3_control_channel_t; typedef enum { - TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, - TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, - TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, - TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, - TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, - TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, - TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, - TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, - TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, - TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, - TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, - TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, - TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, - TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, - TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, - TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, + TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, + TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, + TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, + TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, + TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, + TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, + TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, + TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, + TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX } tegra_nvg_channel_update_gsc_gsc_enum_t; @@ -335,4 +399,26 @@ typedef union { } bits; } nvg_shutdown_t; +typedef union { + uint64_t flat; + struct nvg_debug_config_channel_t { + uint32_t enter_debug_state_on_mca : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_debug_config_t; + +typedef union { + uint64_t flat; + struct nvg_hsm_error_ctrl_channel_t { + uint32_t uncorr : 1; + uint32_t corr : 1; + uint32_t reserved_31_2 : 30; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_hsm_error_ctrl_channel_t; + +extern nvg_debug_config_t nvg_debug_config; + #endif + diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index a095fdd07..1012cdf11 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -31,54 +31,6 @@ uint64_t nvg_get_version(void) } /* - * Enable the perf per watt mode. - * - * NVGDATA[0]: SW(RW), 1 = enable perf per watt mode - */ -int32_t nvg_enable_power_perf_mode(void) -{ - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U); - - return 0; -} - -/* - * Disable the perf per watt mode. - * - * NVGDATA[0]: SW(RW), 0 = disable perf per watt mode - */ -int32_t nvg_disable_power_perf_mode(void) -{ - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U); - - return 0; -} - -/* - * Enable the battery saver mode. - * - * NVGDATA[2]: SW(RW), 1 = enable battery saver mode - */ -int32_t nvg_enable_power_saver_modes(void) -{ - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U); - - return 0; -} - -/* - * Disable the battery saver mode. - * - * NVGDATA[2]: SW(RW), 0 = disable battery saver mode - */ -int32_t nvg_disable_power_saver_modes(void) -{ - nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U); - - return 0; -} - -/* * Set the expected wake time in TSC ticks for the next low-power state the * core enters. * @@ -198,48 +150,6 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) } /* - * Cache clean operation for all CCPLEX caches. - */ -int32_t nvg_roc_clean_cache(void) -{ - int32_t ret = 0; - - /* check if cache flush through mts is supported */ - if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & - ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { - if (nvg_cache_clean() == 0U) { - ERROR("%s: failed\n", __func__); - ret = -ENODEV; - } - } else { - ret = -ENOTSUP; - } - - return ret; -} - -/* - * Cache clean and invalidate operation for all CCPLEX caches. - */ -int32_t nvg_roc_flush_cache(void) -{ - int32_t ret = 0; - - /* check if cache flush through mts is supported */ - if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) & - ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) { - if (nvg_cache_clean_inval() == 0U) { - ERROR("%s: failed\n", __func__); - ret = -ENODEV; - } - } else { - ret = -ENOTSUP; - } - - return ret; -} - -/* * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches. */ int32_t nvg_roc_clean_cache_trbits(void) diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c index a9f461071..3a2e959d0 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c +++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,7 @@ #include <stdbool.h> #include <arch_helpers.h> +#include <bpmp_ipc.h> #include <common/debug.h> #include <drivers/delay_timer.h> #include <lib/mmio.h> @@ -181,6 +182,12 @@ int32_t tegra_se_suspend(void) { int32_t ret = 0; + /* initialise communication channel with BPMP */ + assert(tegra_bpmp_ipc_init() == 0); + + /* Enable SE clock before SE context save */ + tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); + /* save SE registers */ se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT); se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL); @@ -193,6 +200,9 @@ int32_t tegra_se_suspend(void) ERROR("%s: context save failed (%d)\n", __func__, ret); } + /* Disable SE clock after SE context save */ + tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); + return ret; } @@ -201,6 +211,12 @@ int32_t tegra_se_suspend(void) */ void tegra_se_resume(void) { + /* initialise communication channel with BPMP */ + assert(tegra_bpmp_ipc_init() == 0); + + /* Enable SE clock before SE context restore */ + tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE); + /* * When TZ takes over after System Resume, TZ should first reconfigure * SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT, @@ -211,4 +227,7 @@ void tegra_se_resume(void) mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]); mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]); mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]); + + /* Disable SE clock after SE context restore */ + tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE); } diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 57186503b..bb1dd6706 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -130,6 +130,7 @@ const static uint32_t tegra194_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, MC_STREAMID_OVERRIDE_CFG_ISPRA1, + MC_STREAMID_OVERRIDE_CFG_PCIE0R1, MC_STREAMID_OVERRIDE_CFG_MIU0R, MC_STREAMID_OVERRIDE_CFG_MIU0W, MC_STREAMID_OVERRIDE_CFG_MIU1R, @@ -259,6 +260,7 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), @@ -269,38 +271,6 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE), }; -/******************************************************************************* - * Array to hold the transaction override configs - ******************************************************************************/ -const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = { - mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR), - mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR), - mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR), - mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR), - mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(APEW, CGID_TAG_ADR), - mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR), - mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR), - mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR), - mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR), - mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR), - mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR), - mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR), - mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(AONW, CGID_TAG_ADR), - mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR), - mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR), -}; - /* To be called by common memctrl_v2.c */ static void tegra194_memctrl_reconfig_mss_clients(void) { @@ -381,18 +351,52 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_tsa_w_passthrough(AXISW); mc_set_tsa_w_passthrough(BPMPDMAW); mc_set_tsa_w_passthrough(BPMPW); + mc_set_tsa_w_passthrough(EQOSW); mc_set_tsa_w_passthrough(ETRW); - mc_set_tsa_w_passthrough(SCEDMAW); mc_set_tsa_w_passthrough(RCEDMAW); mc_set_tsa_w_passthrough(RCEW); + mc_set_tsa_w_passthrough(SCEDMAW); + mc_set_tsa_w_passthrough(SCEW); mc_set_tsa_w_passthrough(SDMMCW); mc_set_tsa_w_passthrough(SDMMCWA); mc_set_tsa_w_passthrough(SDMMCWAB); + mc_set_tsa_w_passthrough(SESWR); mc_set_tsa_w_passthrough(TSECSWR); mc_set_tsa_w_passthrough(TSECSWRB); mc_set_tsa_w_passthrough(UFSHCW); mc_set_tsa_w_passthrough(VICSWR); mc_set_tsa_w_passthrough(VIFALW); + /* + * set HUB2 as SO_DEV_HUBID + */ + reg_val = tsa_read_32(PCIE0W); + mc_set_tsa_hub2(reg_val, PCIE0W); + reg_val = tsa_read_32(PCIE1W); + mc_set_tsa_hub2(reg_val, PCIE1W); + reg_val = tsa_read_32(PCIE2AW); + mc_set_tsa_hub2(reg_val, PCIE2AW); + reg_val = tsa_read_32(PCIE3W); + mc_set_tsa_hub2(reg_val, PCIE3W); + reg_val = tsa_read_32(PCIE4W); + mc_set_tsa_hub2(reg_val, PCIE4W); + reg_val = tsa_read_32(SATAW); + mc_set_tsa_hub2(reg_val, SATAW); + reg_val = tsa_read_32(XUSB_DEVW); + mc_set_tsa_hub2(reg_val, XUSB_DEVW); + reg_val = tsa_read_32(XUSB_HOSTW); + mc_set_tsa_hub2(reg_val, XUSB_HOSTW); + + /* + * Hw Bug: 200385660, 200394107 + * PCIE datapath hangs when there are more than 28 outstanding + * requests on data backbone for x1 controller. This is seen + * on third party PCIE IP, C1 - PCIE1W, C2 - PCIE2AW and C3 - PCIE3W. + * + * Setting Reorder depth limit, 16 which is < 28. + */ + mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE1W); + mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE2AW); + mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE3W); /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3 * ISO clients(DISP, VI, EQOS) should never snoop caches and @@ -423,114 +427,164 @@ static void tegra194_memctrl_reconfig_mss_clients(void) * - MMIO's can be early acked and AXI ensures dev memory ordering, * Client ensures read/write direction change ordering. * - See Bug 200312466 for more details. - * - * CGID_TAG_ADR is only present from T186 A02. As this code is common - * between A01 and A02, tegra_memctrl_set_overrides() programs - * CGID_TAG_ADR for the necessary clients on A02. */ - mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); - mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); - mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); + mc_set_txn_override(AONDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(APEDMAR, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEDMAW, CGID_TAG_ADR, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AXISR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AXISW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(EQOSR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(EQOSW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ETRR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ETRW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(HOST1XDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(MPCORER, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MPCOREW, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(NVDISPLAYR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(NVDISPLAYR1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(PCIE0R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + if (tegra_platform_is_silicon()) { + mc_set_txn_override(PCIE2AR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE2AW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5W, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + } + mc_set_txn_override(PTCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(RCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SATAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SATAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SCEDMAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEDMAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCER, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCRAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCWAB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + /* + * TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled. + */ + mc_set_txn_override(SESRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SESWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(TSECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(UFSHCR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(UFSHCW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VIFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(VIFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(XUSB_DEVR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_DEVW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(AXIAPR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AXIAPW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1FALRDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1FALWRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(HDAR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(HDAW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ISPFALR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPFALW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPRA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPWA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPWB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSRD1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVJPGSRD, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVJPGSWR, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDA1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDB1, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRA, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRB, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRC, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VIW, CGID_TAG_ADR, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + if (tegra_platform_is_silicon()) { - mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU0R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU0W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU1R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU1W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU2R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU2W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU3R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU3W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU4R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU4W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU5R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU5W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU6R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU6W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU7R, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(MIU7W, CGID_TAG_ADR, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); } + /* - * At this point, ordering can occur at ROC. So, remove PCFIFO's + * At this point, ordering can occur at SCF. So, remove PCFIFO's * control over ordering requests. * * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for * boot and strongly ordered MSS clients */ - /* SATAW is ordered client */ - reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL | - mc_set_pcfifo_ordered_boot_so_mss(1, SATAW); - tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val); - reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR); - /* XUSB_DEVW has PCFIFO enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & @@ -554,7 +608,7 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) & mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); /* EQOSW has PCFIFO order enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW); + reg_val |= mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & @@ -566,10 +620,6 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) & mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) & mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W); - /* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) | - mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) | - mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL & @@ -603,6 +653,9 @@ static void tegra194_memctrl_reconfig_mss_clients(void) reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC); tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val); + reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_12_RESET_VAL, 12, UFSHCPC2); + tegra_mc_write_32(MC_HUB_PC_VC_ID_12, reg_val); + wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); @@ -614,6 +667,15 @@ static void tegra194_memctrl_reconfig_mss_clients(void) reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE; tegra_mc_write_32(MC_COALESCE_CTRL, reg_val); + + /* + * WAR to hardware bug 1953865: Coalescer must be disabled + * for PVA0RDC and PVA1RDC interfaces. + */ + reg_val = tegra_mc_read_32(MC_COALESCE_CONFIG_6_0); + reg_val &= ~(MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED | + MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED); + tegra_mc_write_32(MC_COALESCE_CONFIG_6_0, reg_val); } /******************************************************************************* @@ -624,8 +686,6 @@ static tegra_mc_settings_t tegra194_mc_settings = { .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), .streamid_security_cfg = tegra194_streamid_sec_cfgs, .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), - .txn_override_cfg = tegra194_txn_override_cfgs, - .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_txn_override_cfgs), .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients }; diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index b7e370336..cc8be128a 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -251,6 +251,8 @@ static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t * /* Enable CC6 state and turn off wake mask */ cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6; + cstate_info.ccplex = (uint32_t)TEGRA_NVG_CG_CG7; + cstate_info.system_state_force = 1; cstate_info.update_wake_mask = 1U; mce_update_cstate_info(&cstate_info); @@ -428,18 +430,21 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) * in above registers to support both virtualization and * non-virtualization platforms */ - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { + + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + } /* * Reset power state info for the last core doing SC7 diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 3b582444c..912dcc6f9 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -64,13 +64,15 @@ const uint8_t *plat_get_power_domain_tree_desc(void) * Table of regions to map using the MMU. */ static const mmap_region_t tegra_mmap[] = { - MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #if !ENABLE_CONSOLE_SPE MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ @@ -80,35 +82,37 @@ static const mmap_region_t tegra_mmap[] = { MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #endif - MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ + MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #if ENABLE_CONSOLE_SPE - MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), #endif - MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ + MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ + MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */ - (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), - MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */ + MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), {0} }; @@ -231,18 +235,21 @@ void plat_early_platform_setup(void) * above registers to support both virtualization and * non-virtualization platforms */ - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); - mmio_write_32(TEGRA_XUSB_PADCTL_BASE + - XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { + + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); + mmio_write_32(TEGRA_XUSB_PADCTL_BASE + + XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); + } } /* Secure IRQs for Tegra194 */ @@ -272,9 +279,12 @@ void plat_gic_setup(void) ******************************************************************************/ struct tegra_bl31_params *plat_get_bl31_params(void) { - uint32_t val; + uint64_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); + val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & + SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT; + val <<= 32; + val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); return (struct tegra_bl31_params *)(uintptr_t)val; } @@ -284,9 +294,12 @@ struct tegra_bl31_params *plat_get_bl31_params(void) ******************************************************************************/ plat_params_from_bl2_t *plat_get_bl31_plat_params(void) { - uint32_t val; + uint64_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); + val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT; + val <<= 32; + val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); return (plat_params_from_bl2_t *)(uintptr_t)val; } diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 640ef4deb..3b4a3803c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -139,6 +139,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { mc_make_sid_security_cfg(NVENCSRD1), mc_make_sid_security_cfg(NVENC1SRD1), mc_make_sid_security_cfg(ISPRA1), + mc_make_sid_security_cfg(PCIE0R1), mc_make_sid_security_cfg(MIU0R), mc_make_sid_security_cfg(MIU0W), mc_make_sid_security_cfg(MIU1R), @@ -262,6 +263,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { mc_make_sid_override_cfg(NVENCSRD1), mc_make_sid_override_cfg(NVENC1SRD1), mc_make_sid_override_cfg(ISPRA1), + mc_make_sid_override_cfg(PCIE0R1), mc_make_sid_override_cfg(MIU0R), mc_make_sid_override_cfg(MIU0W), mc_make_sid_override_cfg(MIU1R), diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index 696a5774e..540c2019c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ #define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7 #define TEGRA194_STATE_SYSTEM_RESUME 0x600D -#define TEGRA194_SMMU_CTX_SIZE 0x80B +#define TEGRA194_SMMU_CTX_SIZE 0x80D .align 4 .globl tegra194_cpu_reset_handler diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index f114b7e5b..78766fcbe 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -5,12 +5,15 @@ # # platform configs -ENABLE_CONSOLE_SPE := 0 +ENABLE_CONSOLE_SPE := 1 $(eval $(call add_define,ENABLE_CONSOLE_SPE)) -ENABLE_STRICT_CHECKING_MODE := 1 +ENABLE_STRICT_CHECKING_MODE := 1 $(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE)) +USE_GPC_DMA := 1 +$(eval $(call add_define,USE_GPC_DMA)) + RESET_TO_BL31 := 1 PROGRAMMABLE_RESET_ADDRESS := 1 @@ -38,6 +41,9 @@ PLAT_INCLUDES += -I${SOC_DIR}/drivers/include BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ + ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \ + ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \ + ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \ ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ ${COMMON_DIR}/drivers/smmu/smmu.c \ ${SOC_DIR}/drivers/mce/mce.c \ diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index c6b4db506..cce992ff9 100644 --- a/plat/qemu/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -18,20 +18,20 @@ #define PLATFORM_STACK_SIZE 0x1000 #if ARM_ARCH_MAJOR == 7 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #else -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(2) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #endif #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ PLATFORM_CLUSTER1_CORE_COUNT) -#define QEMU_PRIMARY_CPU 0 +#define QEMU_PRIMARY_CPU U(0) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h index 333b21cc1..f44b9f6e0 100644 --- a/plat/qemu/qemu_sbsa/include/platform_def.h +++ b/plat/qemu/qemu_sbsa/include/platform_def.h @@ -15,14 +15,14 @@ #define PLATFORM_STACK_SIZE 0x1000 -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 -#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(2) #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ PLATFORM_CLUSTER1_CORE_COUNT) -#define QEMU_PRIMARY_CPU 0 +#define QEMU_PRIMARY_CPU U(0) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/rcar/aarch64/plat_helpers.S index 61dd62287..138d98807 100644 --- a/plat/renesas/rcar/aarch64/plat_helpers.S +++ b/plat/renesas/rcar/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -189,7 +189,7 @@ func bl2_enter_bl31 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] msr elr_el3, x0 msr spsr_el3, x1 - eret + exception_return endfunc bl2_enter_bl31 /* ----------------------------------------------------- diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index 193d80e70..578892eb3 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,12 +39,19 @@ #include "rcar_version.h" #include "rom_api.h" -IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE) -IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT) +#if RCAR_BL2_DCACHE == 1 +/* + * Following symbols are only used during plat_arch_setup() only + * when RCAR_BL2_DCACHE is enabled. + */ +static const uint64_t BL2_RO_BASE = BL_CODE_BASE; +static const uint64_t BL2_RO_LIMIT = BL_CODE_END; #if USE_COHERENT_MEM -IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE) -IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT) +static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; +static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; +#endif + #endif extern void plat_rcar_gic_driver_init(void); diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c index bd83c415e..7bc0d8e27 100644 --- a/plat/renesas/rcar/bl31_plat_setup.c +++ b/plat/renesas/rcar/bl31_plat_setup.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,12 +22,12 @@ #include "rcar_private.h" #include "rcar_version.h" -IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE) -IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT) +static const uint64_t BL31_RO_BASE = BL_CODE_BASE; +static const uint64_t BL31_RO_LIMIT = BL_CODE_END; #if USE_COHERENT_MEM -IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE) -IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT) +static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; +static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; #endif extern void plat_rcar_gic_driver_init(void); diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h index 2f4f672a0..a11f84f42 100644 --- a/plat/rockchip/px30/include/platform_def.h +++ b/plat/rockchip/px30/include/platform_def.h @@ -39,10 +39,10 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) diff --git a/plat/rockchip/rk3288/include/platform_def.h b/plat/rockchip/rk3288/include/platform_def.h index e24aeffac..85ec3fb88 100644 --- a/plat/rockchip/rk3288/include/platform_def.h +++ b/plat/rockchip/rk3288/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,11 +36,11 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index e9eb3fafb..6579756e0 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -37,9 +37,9 @@ #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 #define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h index 2abd56b0b..12115b4f0 100644 --- a/plat/rockchip/rk3368/include/platform_def.h +++ b/plat/rockchip/rk3368/include/platform_def.h @@ -37,13 +37,13 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(4) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h index 2861a7dd4..78269b632 100644 --- a/plat/rockchip/rk3399/include/platform_def.h +++ b/plat/rockchip/rk3399/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,13 +38,13 @@ #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 2 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(2) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h index 7e54b39d8..7158bfaf3 100644 --- a/plat/socionext/synquacer/include/platform_def.h +++ b/plat/socionext/synquacer/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,8 +11,8 @@ #include <plat/common/common_def.h> /* CPU topology */ -#define PLAT_MAX_CORES_PER_CLUSTER 2 -#define PLAT_CLUSTER_COUNT 12 +#define PLAT_MAX_CORES_PER_CLUSTER U(2) +#define PLAT_CLUSTER_COUNT U(12) #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ PLAT_MAX_CORES_PER_CLUSTER) diff --git a/plat/socionext/uniphier/include/platform_def.h b/plat/socionext/uniphier/include/platform_def.h index d4db3f5b0..7c6341d14 100644 --- a/plat/socionext/uniphier/include/platform_def.h +++ b/plat/socionext/uniphier/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,8 +17,8 @@ #define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT)) /* topology */ -#define UNIPHIER_MAX_CPUS_PER_CLUSTER 4 -#define UNIPHIER_CLUSTER_COUNT 2 +#define UNIPHIER_MAX_CPUS_PER_CLUSTER U(4) +#define UNIPHIER_CLUSTER_COUNT U(2) #define PLATFORM_CORE_COUNT \ ((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT)) @@ -28,28 +28,43 @@ #define PLAT_MAX_OFF_STATE U(2) #define PLAT_MAX_RET_STATE U(1) -#define BL2_BASE ULL(0x80000000) -#define BL2_LIMIT ULL(0x80080000) +#define UNIPHIER_BL2_OFFSET UL(0x00000000) +#define UNIPHIER_BL2_MAX_SIZE UL(0x00080000) -/* 0x80080000-0x81000000: reserved for DSP */ +/* 0x00080000-0x01000000: reserved for DSP */ -#define UNIPHIER_SEC_DRAM_BASE 0x81000000ULL -#define UNIPHIER_SEC_DRAM_LIMIT 0x82000000ULL -#define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \ - (UNIPHIER_SEC_DRAM_BASE)) +#define UNIPHIER_BL31_OFFSET UL(0x01000000) +#define UNIPHIER_BL31_MAX_SIZE UL(0x00080000) -#define BL31_BASE ULL(0x81000000) -#define BL31_LIMIT ULL(0x81080000) +#define UNIPHIER_BL32_OFFSET UL(0x01080000) +#define UNIPHIER_BL32_MAX_SIZE UL(0x00100000) -#define BL32_BASE ULL(0x81080000) -#define BL32_LIMIT ULL(0x81180000) +/* + * The link addresses are determined by UNIPHIER_MEM_BASE + offset. + * When ENABLE_PIE is set, all the TF images can be loaded anywhere, so + * UNIPHIER_MEM_BASE is arbitrary. + * + * When ENABLE_PIE is unset, UNIPHIER_MEM_BASE should be chosen so that + * BL2_BASE matches to the physical address where BL2 is loaded, that is, + * UNIPHIER_MEM_BASE should be the base address of the DRAM region. + */ +#define UNIPHIER_MEM_BASE UL(0x00000000) + +#define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET) +#define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE) + +#define BL31_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL31_OFFSET) +#define BL31_LIMIT (BL31_BASE + UNIPHIER_BL31_MAX_SIZE) + +#define BL32_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL32_OFFSET) +#define BL32_LIMIT (BL32_BASE + UNIPHIER_BL32_MAX_SIZE) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_XLAT_TABLES_DYNAMIC 1 -#define MAX_XLAT_TABLES 7 -#define MAX_MMAP_REGIONS 7 +#define MAX_XLAT_TABLES 9 +#define MAX_MMAP_REGIONS 13 #define MAX_IO_HANDLES 2 #define MAX_IO_DEVICES 2 diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index d31fbe88f..8e96b68bb 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -10,6 +10,10 @@ override PROGRAMMABLE_RESET_ADDRESS := 1 override USE_COHERENT_MEM := 1 override ENABLE_SVE_FOR_NS := 0 +# Disabling ENABLE_PIE saves memory footprint a lot, but you need to adjust +# UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses. +override ENABLE_PIE := 1 + # Cortex-A53 revision r0p4-51rel0 # needed for LD20, unneeded for LD11, PXs3 (no ACE) ERRATA_A53_855873 := 1 diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c index 0b232e067..4f58b683c 100644 --- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c +++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,8 +11,6 @@ #include "../uniphier.h" -#define BL32_SIZE ((BL32_END) - (BL32_BASE)) - void tsp_early_platform_setup(void) { uniphier_console_setup(); @@ -24,6 +22,6 @@ void tsp_platform_setup(void) void tsp_plat_arch_setup(void) { - uniphier_mmap_setup(BL32_BASE, BL32_SIZE, NULL); + uniphier_mmap_setup(); enable_mmu_el1(0); } diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h index 648c2b94c..729dc5caa 100644 --- a/plat/socionext/uniphier/uniphier.h +++ b/plat/socionext/uniphier/uniphier.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,24 +36,25 @@ unsigned int uniphier_get_boot_master(unsigned int soc); void uniphier_console_setup(void); -int uniphier_emmc_init(uintptr_t *block_dev_spec); -int uniphier_nand_init(uintptr_t *block_dev_spec); -int uniphier_usb_init(unsigned int soc, uintptr_t *block_dev_spec); +struct io_block_dev_spec; +int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec); +int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec); +int uniphier_usb_init(unsigned int soc, + struct io_block_dev_spec **block_dev_spec); -int uniphier_io_setup(unsigned int soc); +int uniphier_io_setup(unsigned int soc, uintptr_t mem_base); +void uniphier_init_image_descs(uintptr_t mem_base); struct image_info; struct image_info *uniphier_get_image_info(unsigned int image_id); int uniphier_scp_is_running(void); -void uniphier_scp_start(void); +void uniphier_scp_start(uint32_t scp_base); void uniphier_scp_open_com(void); void uniphier_scp_system_off(void); void uniphier_scp_system_reset(void); -struct mmap_region; -void uniphier_mmap_setup(uintptr_t total_base, size_t total_size, - const struct mmap_region *mmap); +void uniphier_mmap_setup(void); void uniphier_cci_init(unsigned int soc); void uniphier_cci_enable(void); @@ -67,25 +68,4 @@ void uniphier_gic_pcpu_init(void); unsigned int uniphier_calc_core_pos(u_register_t mpidr); -#define UNIPHIER_NS_DRAM_BASE 0x84000000 -#define UNIPHIER_NS_DRAM_LIMIT 0x85000000 -#define UNIPHIER_NS_DRAM_SIZE ((UNIPHIER_NS_DRAM_LIMIT) - \ - (UNIPHIER_NS_DRAM_BASE)) - -#define UNIPHIER_BL33_BASE (UNIPHIER_NS_DRAM_BASE) -#define UNIPHIER_BL33_MAX_SIZE 0x00100000 - -#define UNIPHIER_SCP_BASE ((UNIPHIER_BL33_BASE) + \ - (UNIPHIER_BL33_MAX_SIZE)) -#define UNIPHIER_SCP_MAX_SIZE 0x00020000 - -#define UNIPHIER_BLOCK_BUF_BASE ((UNIPHIER_SCP_BASE) + \ - (UNIPHIER_SCP_MAX_SIZE)) -#define UNIPHIER_BLOCK_BUF_SIZE 0x00100000 - -#define UNIPHIER_IMAGE_BUF_BASE ((UNIPHIER_BLOCK_BUF_BASE) + \ - (UNIPHIER_BLOCK_BUF_SIZE)) -#define UNIPHIER_IMAGE_BUF_SIZE ((UNIPHIER_NS_DRAM_LIMIT) - \ - (UNIPHIER_IMAGE_BUF_BASE)) - #endif /* UNIPHIER_H */ diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 787b3ac3d..11d837cf4 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,8 +21,10 @@ #include "uniphier.h" -#define BL2_SIZE ((BL2_END) - (BL2_BASE)) +#define UNIPHIER_IMAGE_BUF_OFFSET 0x04300000UL +#define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL +static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE; static int uniphier_bl2_kick_scp; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, @@ -31,32 +33,25 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, uniphier_console_setup(); } -static const struct mmap_region uniphier_bl2_mmap[] = { - /* for BL31, BL32 */ - MAP_REGION_FLAT(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE, - MT_MEMORY | MT_RW | MT_SECURE), - /* for SCP, BL33 */ - MAP_REGION_FLAT(UNIPHIER_NS_DRAM_BASE, UNIPHIER_NS_DRAM_SIZE, - MT_MEMORY | MT_RW | MT_NS), - { .size = 0 }, -}; - void bl2_el3_plat_arch_setup(void) { unsigned int soc; int skip_scp = 0; int ret; - uniphier_mmap_setup(BL2_BASE, BL2_SIZE, uniphier_bl2_mmap); + uniphier_mmap_setup(); enable_mmu_el3(0); + /* add relocation offset (run-time-address - link-address) */ + uniphier_mem_base += BL_CODE_BASE - BL2_BASE; + soc = uniphier_get_soc_id(); if (soc == UNIPHIER_SOC_UNKNOWN) { ERROR("unsupported SoC\n"); plat_error_handler(-ENOTSUP); } - ret = uniphier_io_setup(soc); + ret = uniphier_io_setup(soc, uniphier_mem_base); if (ret) { ERROR("failed to setup io devices\n"); plat_error_handler(ret); @@ -119,28 +114,47 @@ bl_params_t *plat_get_next_bl_params(void) void bl2_plat_preload_setup(void) { #ifdef UNIPHIER_DECOMPRESS_GZIP - image_decompress_init(UNIPHIER_IMAGE_BUF_BASE, - UNIPHIER_IMAGE_BUF_SIZE, - gunzip); + uintptr_t buf_base = uniphier_mem_base + UNIPHIER_IMAGE_BUF_OFFSET; + int ret; + + ret = mmap_add_dynamic_region(buf_base, buf_base, + UNIPHIER_IMAGE_BUF_SIZE, + MT_MEMORY | MT_RW | MT_NS); + if (ret) + plat_error_handler(ret); + + image_decompress_init(buf_base, UNIPHIER_IMAGE_BUF_SIZE, gunzip); #endif + + uniphier_init_image_descs(uniphier_mem_base); } int bl2_plat_handle_pre_image_load(unsigned int image_id) { + struct image_info *image_info; + int ret; + + image_info = uniphier_get_image_info(image_id); + + ret = mmap_add_dynamic_region(image_info->image_base, + image_info->image_base, + image_info->image_max_size, + MT_MEMORY | MT_RW | MT_NS); + if (ret) + return ret; + #ifdef UNIPHIER_DECOMPRESS_GZIP - image_decompress_prepare(uniphier_get_image_info(image_id)); + image_decompress_prepare(image_info); #endif return 0; } int bl2_plat_handle_post_image_load(unsigned int image_id) { + struct image_info *image_info = uniphier_get_image_info(image_id); #ifdef UNIPHIER_DECOMPRESS_GZIP - struct image_info *image_info; int ret; - image_info = uniphier_get_image_info(image_id); - if (!(image_info->h.attr & IMAGE_ATTRIB_SKIP_LOADING)) { ret = image_decompress(uniphier_get_image_info(image_id)); if (ret) @@ -149,7 +163,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) #endif if (image_id == SCP_BL2_IMAGE_ID && uniphier_bl2_kick_scp) - uniphier_scp_start(); + uniphier_scp_start(image_info->image_base); return 0; } diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c index 440e6aa11..47f2378bc 100644 --- a/plat/socionext/uniphier/uniphier_bl31_setup.c +++ b/plat/socionext/uniphier/uniphier_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,8 +19,6 @@ #include "uniphier.h" -#define BL31_SIZE ((BL31_END) - (BL31_BASE)) - static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -81,6 +79,6 @@ void bl31_platform_setup(void) void bl31_plat_arch_setup(void) { - uniphier_mmap_setup(BL31_BASE, BL31_SIZE, NULL); + uniphier_mmap_setup(); enable_mmu_el3(0); } diff --git a/plat/socionext/uniphier/uniphier_emmc.c b/plat/socionext/uniphier/uniphier_emmc.c index 4ac1f5108..d666ba781 100644 --- a/plat/socionext/uniphier/uniphier_emmc.c +++ b/plat/socionext/uniphier/uniphier_emmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -225,11 +225,7 @@ static size_t uniphier_emmc_read(int lba, uintptr_t buf, size_t size) return ret ? 0 : size; } -static const struct io_block_dev_spec uniphier_emmc_dev_spec = { - .buffer = { - .offset = UNIPHIER_BLOCK_BUF_BASE, - .length = UNIPHIER_BLOCK_BUF_SIZE, - }, +static struct io_block_dev_spec uniphier_emmc_dev_spec = { .ops = { .read = uniphier_emmc_read, }, @@ -278,7 +274,7 @@ static int uniphier_emmc_hw_init(void) return 0; } -int uniphier_emmc_init(uintptr_t *block_dev_spec) +int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec) { int ret; @@ -286,7 +282,7 @@ int uniphier_emmc_init(uintptr_t *block_dev_spec) if (ret) return ret; - *block_dev_spec = (uintptr_t)&uniphier_emmc_dev_spec; + *block_dev_spec = &uniphier_emmc_dev_spec; return 0; } diff --git a/plat/socionext/uniphier/uniphier_image_desc.c b/plat/socionext/uniphier/uniphier_image_desc.c index 817029a2c..8c232ba31 100644 --- a/plat/socionext/uniphier/uniphier_image_desc.c +++ b/plat/socionext/uniphier/uniphier_image_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,13 +13,19 @@ #include "uniphier.h" +#define UNIPHIER_BL33_OFFSET 0x04000000UL +#define UNIPHIER_BL33_MAX_SIZE 0x00100000UL + +#define UNIPHIER_SCP_OFFSET 0x04100000UL +#define UNIPHIER_SCP_MAX_SIZE 0x00020000UL + static struct bl_mem_params_node uniphier_image_descs[] = { { .image_id = SCP_BL2_IMAGE_ID, SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = UNIPHIER_SCP_BASE, + .image_info.image_base = UNIPHIER_SCP_OFFSET, .image_info.image_max_size = UNIPHIER_SCP_MAX_SIZE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, @@ -33,13 +39,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + .image_info.image_base = UNIPHIER_BL31_OFFSET, + .image_info.image_max_size = UNIPHIER_BL31_MAX_SIZE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, entry_point_info_t, SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, + .ep_info.pc = UNIPHIER_BL31_OFFSET, .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), @@ -55,13 +61,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + .image_info.image_base = UNIPHIER_BL32_OFFSET, + .image_info.image_max_size = UNIPHIER_BL32_MAX_SIZE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + .ep_info.pc = UNIPHIER_BL32_OFFSET, .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), @@ -73,13 +79,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = { SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t, 0), - .image_info.image_base = UNIPHIER_BL33_BASE, + .image_info.image_base = UNIPHIER_BL33_OFFSET, .image_info.image_max_size = UNIPHIER_BL33_MAX_SIZE, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), - .ep_info.pc = UNIPHIER_BL33_BASE, + .ep_info.pc = UNIPHIER_BL33_OFFSET, .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), @@ -88,6 +94,21 @@ static struct bl_mem_params_node uniphier_image_descs[] = { }; REGISTER_BL_IMAGE_DESCS(uniphier_image_descs) +/* + * image_info.image_base and ep_info.pc are the offset from the memory base. + * When ENABLE_PIE is set, we never know the real memory base at link-time. + * Fix-up the addresses by adding the run-time detected base. + */ +void uniphier_init_image_descs(uintptr_t mem_base) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(uniphier_image_descs); i++) { + uniphier_image_descs[i].image_info.image_base += mem_base; + uniphier_image_descs[i].ep_info.pc += mem_base; + } +} + struct image_info *uniphier_get_image_info(unsigned int image_id) { struct bl_mem_params_node *desc; diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c index b456bc538..89c8718b4 100644 --- a/plat/socionext/uniphier/uniphier_io_storage.c +++ b/plat/socionext/uniphier/uniphier_io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,6 +26,9 @@ #define UNIPHIER_OCM_REGION_BASE 0x30000000ULL #define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL +#define UNIPHIER_BLOCK_BUF_OFFSET 0x04200000UL +#define UNIPHIER_BLOCK_BUF_SIZE 0x00100000UL + static const io_dev_connector_t *uniphier_fip_dev_con; static uintptr_t uniphier_fip_dev_handle; @@ -189,17 +192,29 @@ static const struct uniphier_io_policy uniphier_io_policies[] = { #endif }; -static int uniphier_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec) +static int uniphier_io_block_setup(size_t fip_offset, + struct io_block_dev_spec *block_dev_spec, + size_t buffer_offset) { int ret; uniphier_fip_spec.offset = fip_offset; + block_dev_spec->buffer.offset = buffer_offset; + block_dev_spec->buffer.length = UNIPHIER_BLOCK_BUF_SIZE; + + ret = mmap_add_dynamic_region(block_dev_spec->buffer.offset, + block_dev_spec->buffer.offset, + block_dev_spec->buffer.length, + MT_MEMORY | MT_RW | MT_NS); + if (ret) + return ret; + ret = register_io_dev_block(&uniphier_backend_dev_con); if (ret) return ret; - return io_dev_open(uniphier_backend_dev_con, block_dev_spec, + return io_dev_open(uniphier_backend_dev_con, (uintptr_t)block_dev_spec, &uniphier_backend_dev_handle); } @@ -234,38 +249,38 @@ static int uniphier_io_fip_setup(void) return io_dev_open(uniphier_fip_dev_con, 0, &uniphier_fip_dev_handle); } -static int uniphier_io_emmc_setup(unsigned int soc_id) +static int uniphier_io_emmc_setup(unsigned int soc_id, size_t buffer_offset) { - uintptr_t block_dev_spec; + struct io_block_dev_spec *block_dev_spec; int ret; ret = uniphier_emmc_init(&block_dev_spec); if (ret) return ret; - return uniphier_io_block_setup(0x20000, block_dev_spec); + return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset); } -static int uniphier_io_nand_setup(unsigned int soc_id) +static int uniphier_io_nand_setup(unsigned int soc_id, size_t buffer_offset) { - uintptr_t block_dev_spec; + struct io_block_dev_spec *block_dev_spec; int ret; ret = uniphier_nand_init(&block_dev_spec); if (ret) return ret; - return uniphier_io_block_setup(0x20000, block_dev_spec); + return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset); } -static int uniphier_io_nor_setup(unsigned int soc_id) +static int uniphier_io_nor_setup(unsigned int soc_id, size_t buffer_offset) { return uniphier_io_memmap_setup(0x70000); } -static int uniphier_io_usb_setup(unsigned int soc_id) +static int uniphier_io_usb_setup(unsigned int soc_id, size_t buffer_offset) { - uintptr_t block_dev_spec; + struct io_block_dev_spec *block_dev_spec; int ret; /* use ROM API for loading images from USB storage */ @@ -292,19 +307,19 @@ static int uniphier_io_usb_setup(unsigned int soc_id) if (ret) return ret; - return uniphier_io_block_setup(0x20000, block_dev_spec); + return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset); } -static int (* const uniphier_io_setup_table[])(unsigned int) = { +static int (* const uniphier_io_setup_table[])(unsigned int, size_t) = { [UNIPHIER_BOOT_DEVICE_EMMC] = uniphier_io_emmc_setup, [UNIPHIER_BOOT_DEVICE_NAND] = uniphier_io_nand_setup, [UNIPHIER_BOOT_DEVICE_NOR] = uniphier_io_nor_setup, [UNIPHIER_BOOT_DEVICE_USB] = uniphier_io_usb_setup, }; -int uniphier_io_setup(unsigned int soc_id) +int uniphier_io_setup(unsigned int soc_id, uintptr_t mem_base) { - int (*io_setup)(unsigned int soc_id); + int (*io_setup)(unsigned int soc_id, size_t buffer_offset); unsigned int boot_dev; int ret; @@ -313,7 +328,7 @@ int uniphier_io_setup(unsigned int soc_id) return -EINVAL; io_setup = uniphier_io_setup_table[boot_dev]; - ret = io_setup(soc_id); + ret = io_setup(soc_id, mem_base + UNIPHIER_BLOCK_BUF_OFFSET); if (ret) return ret; diff --git a/plat/socionext/uniphier/uniphier_nand.c b/plat/socionext/uniphier/uniphier_nand.c index 27e10e4b7..3925177ed 100644 --- a/plat/socionext/uniphier/uniphier_nand.c +++ b/plat/socionext/uniphier/uniphier_nand.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -224,10 +224,6 @@ static size_t uniphier_nand_read(int lba, uintptr_t buf, size_t size) } static struct io_block_dev_spec uniphier_nand_dev_spec = { - .buffer = { - .offset = UNIPHIER_BLOCK_BUF_BASE, - .length = UNIPHIER_BLOCK_BUF_SIZE, - }, .ops = { .read = uniphier_nand_read, }, @@ -259,7 +255,7 @@ static int uniphier_nand_hw_init(struct uniphier_nand *nand) return 0; } -int uniphier_nand_init(uintptr_t *block_dev_spec) +int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec) { int ret; @@ -269,7 +265,7 @@ int uniphier_nand_init(uintptr_t *block_dev_spec) uniphier_nand_dev_spec.block_size = uniphier_nand.page_size; - *block_dev_spec = (uintptr_t)&uniphier_nand_dev_spec; + *block_dev_spec = &uniphier_nand_dev_spec; return 0; } diff --git a/plat/socionext/uniphier/uniphier_scp.c b/plat/socionext/uniphier/uniphier_scp.c index c608a255a..8a12d5d8d 100644 --- a/plat/socionext/uniphier/uniphier_scp.c +++ b/plat/socionext/uniphier/uniphier_scp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -28,11 +28,11 @@ int uniphier_scp_is_running(void) return mmio_read_32(UNIPHIER_STMBE2COM) == UNIPHIER_SCP_READY_MAGIC; } -void uniphier_scp_start(void) +void uniphier_scp_start(uint32_t scp_base) { uint32_t tmp; - mmio_write_32(UNIPHIER_STMBE2COM + 4, UNIPHIER_SCP_BASE); + mmio_write_32(UNIPHIER_STMBE2COM + 4, scp_base); mmio_write_32(UNIPHIER_STMBE2COM, UNIPHIER_SCP_READY_MAGIC); do { diff --git a/plat/socionext/uniphier/uniphier_usb.c b/plat/socionext/uniphier/uniphier_usb.c index ef7079a5f..7469ad1cc 100644 --- a/plat/socionext/uniphier/uniphier_usb.c +++ b/plat/socionext/uniphier/uniphier_usb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -158,17 +158,14 @@ static size_t uniphier_usb_read(int lba, uintptr_t buf, size_t size) } static struct io_block_dev_spec uniphier_usb_dev_spec = { - .buffer = { - .offset = UNIPHIER_BLOCK_BUF_BASE, - .length = UNIPHIER_BLOCK_BUF_SIZE, - }, .ops = { .read = uniphier_usb_read, }, .block_size = 512, }; -int uniphier_usb_init(unsigned int soc, uintptr_t *block_dev_spec) +int uniphier_usb_init(unsigned int soc, + struct io_block_dev_spec **block_dev_spec) { const struct uniphier_usb_rom_param *param; @@ -180,7 +177,7 @@ int uniphier_usb_init(unsigned int soc, uintptr_t *block_dev_spec) __uniphier_usb_read = param->read; - *block_dev_spec = (uintptr_t)&uniphier_usb_dev_spec; + *block_dev_spec = &uniphier_usb_dev_spec; return 0; } diff --git a/plat/socionext/uniphier/uniphier_xlat_setup.c b/plat/socionext/uniphier/uniphier_xlat_setup.c index 0faebc993..18d2f9e93 100644 --- a/plat/socionext/uniphier/uniphier_xlat_setup.c +++ b/plat/socionext/uniphier/uniphier_xlat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,13 +12,12 @@ #define UNIPHIER_REG_REGION_BASE 0x50000000ULL #define UNIPHIER_REG_REGION_SIZE 0x20000000ULL -void uniphier_mmap_setup(uintptr_t total_base, size_t total_size, - const struct mmap_region *mmap) +void uniphier_mmap_setup(void) { VERBOSE("Trusted RAM seen by this BL image: %p - %p\n", - (void *)total_base, (void *)(total_base + total_size)); - mmap_add_region(total_base, total_base, - total_size, + (void *)BL_CODE_BASE, (void *)BL_END); + mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, + round_up(BL_END, PAGE_SIZE) - BL_CODE_BASE, MT_MEMORY | MT_RW | MT_SECURE); /* remap the code section */ @@ -40,9 +39,5 @@ void uniphier_mmap_setup(uintptr_t total_base, size_t total_size, UNIPHIER_REG_REGION_SIZE, MT_DEVICE | MT_RW | MT_SECURE); - /* additional regions if needed */ - if (mmap) - mmap_add(mmap); - init_xlat_tables(); } diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h index 450a9d404..27ba6f7f9 100644 --- a/plat/st/stm32mp1/include/platform_def.h +++ b/plat/st/stm32mp1/include/platform_def.h @@ -41,7 +41,7 @@ #define STM32MP_PRIMARY_CPU U(0x0) #define STM32MP_SECONDARY_CPU U(0x1) -#define PLATFORM_CLUSTER_COUNT ULL(1) +#define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT U(2) #define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ diff --git a/plat/st/stm32mp1/include/stm32mp1_boot_device.h b/plat/st/stm32mp1/include/stm32mp1_boot_device.h deleted file mode 100644 index a74598395..000000000 --- a/plat/st/stm32mp1/include/stm32mp1_boot_device.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STM32MP1_BOOT_DEVICE_H -#define STM32MP1_BOOT_DEVICE_H - -#include <drivers/raw_nand.h> -#include <drivers/spi_nand.h> -#include <drivers/spi_nor.h> - -int plat_get_raw_nand_data(struct rawnand_device *device); -int plat_get_spi_nand_data(struct spinand_device *device); -int plat_get_nor_data(struct nor_device *device); - -#endif /* STM32MP1_BOOT_DEVICE_H */ diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c index 2d8eccff7..997335d0d 100644 --- a/plat/st/stm32mp1/stm32mp1_boot_device.c +++ b/plat/st/stm32mp1/stm32mp1_boot_device.c @@ -7,6 +7,9 @@ #include <errno.h> #include <drivers/nand.h> +#include <drivers/raw_nand.h> +#include <drivers/spi_nand.h> +#include <drivers/spi_nor.h> #include <lib/utils.h> #include <plat/common/platform.h> diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 11b01ab88..5dc520625 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -23,7 +23,6 @@ #include <stm32mp_common.h> #include <stm32mp_dt.h> #include <stm32mp_shres_helpers.h> -#include <stm32mp1_boot_device.h> #include <stm32mp1_dbgmcu.h> #include <stm32mp1_private.h> #endif diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h index 490b975f4..0d451167e 100644 --- a/plat/ti/k3/board/generic/include/board_def.h +++ b/plat/ti/k3/board/generic/include/board_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,10 @@ #include <lib/utils_def.h> /* The ports must be in order and contiguous */ -#define K3_CLUSTER0_CORE_COUNT 2 -#define K3_CLUSTER1_CORE_COUNT 2 -#define K3_CLUSTER2_CORE_COUNT 2 -#define K3_CLUSTER3_CORE_COUNT 2 +#define K3_CLUSTER0_CORE_COUNT U(2) +#define K3_CLUSTER1_CORE_COUNT U(2) +#define K3_CLUSTER2_CORE_COUNT U(2) +#define K3_CLUSTER3_CORE_COUNT U(2) /* * This RAM will be used for the bootloader including code, bss, and stacks. @@ -27,5 +27,6 @@ #define PLAT_PROC_START_ID 32 #define PLAT_PROC_DEVICE_START_ID 202 +#define PLAT_CLUSTER_DEVICE_START_ID 198 #endif /* BOARD_DEF_H */ diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c index ac33278a9..e390efee6 100644 --- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c +++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c @@ -20,32 +20,10 @@ #include "ti_sci_protocol.h" #include "ti_sci.h" -/** - * struct ti_sci_desc - Description of SoC integration - * @host_id: Host identifier representing the compute entity - * @max_msg_size: Maximum size of data per message that can be handled - */ -struct ti_sci_desc { - uint8_t host_id; - int max_msg_size; -}; - -/** - * struct ti_sci_info - Structure representing a TI SCI instance - * @desc: SoC description for this instance - * @seq: Seq id used for verification for tx and rx message - */ -struct ti_sci_info { - const struct ti_sci_desc desc; - uint8_t seq; -}; - -static struct ti_sci_info info = { - .desc = { - .host_id = TI_SCI_HOST_ID, - .max_msg_size = TI_SCI_MAX_MESSAGE_SIZE, - }, -}; +#if USE_COHERENT_MEM +__section("tzfw_coherent_mem") +#endif +static uint8_t message_sequence; /** * struct ti_sci_xfer - Structure representing a message flow @@ -82,16 +60,16 @@ static int ti_sci_setup_one_xfer(uint16_t msg_type, uint32_t msg_flags, struct ti_sci_msg_hdr *hdr; /* Ensure we have sane transfer sizes */ - if (rx_message_size > info.desc.max_msg_size || - tx_message_size > info.desc.max_msg_size || + if (rx_message_size > TI_SCI_MAX_MESSAGE_SIZE || + tx_message_size > TI_SCI_MAX_MESSAGE_SIZE || rx_message_size < sizeof(*hdr) || tx_message_size < sizeof(*hdr)) return -ERANGE; hdr = (struct ti_sci_msg_hdr *)tx_buf; - hdr->seq = ++info.seq; + hdr->seq = ++message_sequence; hdr->type = msg_type; - hdr->host = info.desc.host_id; + hdr->host = TI_SCI_HOST_ID; hdr->flags = msg_flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED; xfer->tx_message.buf = tx_buf; @@ -131,7 +109,7 @@ static inline int ti_sci_get_response(struct ti_sci_xfer *xfer, hdr = (struct ti_sci_msg_hdr *)msg->buf; /* Sanity check for message response */ - if (hdr->seq == info.seq) + if (hdr->seq == message_sequence) break; else WARN("Message with sequence ID %u is not expected\n", hdr->seq); @@ -141,9 +119,9 @@ static inline int ti_sci_get_response(struct ti_sci_xfer *xfer, return -EINVAL; } - if (msg->len > info.desc.max_msg_size) { + if (msg->len > TI_SCI_MAX_MESSAGE_SIZE) { ERROR("Unable to handle %lu xfer (max %d)\n", - msg->len, info.desc.max_msg_size); + msg->len, TI_SCI_MAX_MESSAGE_SIZE); return -EINVAL; } @@ -425,13 +403,13 @@ int ti_sci_device_put_no_wait(uint32_t id) int ret; /* Ensure we have sane transfer size */ - if (sizeof(req) > info.desc.max_msg_size) + if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE) return -ERANGE; hdr = (struct ti_sci_msg_hdr *)&req; - hdr->seq = ++info.seq; + hdr->seq = ++message_sequence; hdr->type = TI_SCI_MSG_SET_DEVICE_STATE; - hdr->host = info.desc.host_id; + hdr->host = TI_SCI_HOST_ID; /* Setup with NORESPONSE flag to keep response queue clean */ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE; @@ -1408,13 +1386,13 @@ int ti_sci_proc_set_boot_ctrl_no_wait(uint8_t proc_id, int ret; /* Ensure we have sane transfer size */ - if (sizeof(req) > info.desc.max_msg_size) + if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE) return -ERANGE; hdr = (struct ti_sci_msg_hdr *)&req; - hdr->seq = ++info.seq; + hdr->seq = ++message_sequence; hdr->type = TISCI_MSG_SET_PROC_BOOT_CTRL; - hdr->host = info.desc.host_id; + hdr->host = TI_SCI_HOST_ID; /* Setup with NORESPONSE flag to keep response queue clean */ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE; @@ -1650,13 +1628,13 @@ int ti_sci_proc_wait_boot_status_no_wait(uint8_t proc_id, int ret; /* Ensure we have sane transfer size */ - if (sizeof(req) > info.desc.max_msg_size) + if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE) return -ERANGE; hdr = (struct ti_sci_msg_hdr *)&req; - hdr->seq = ++info.seq; + hdr->seq = ++message_sequence; hdr->type = TISCI_MSG_WAIT_PROC_BOOT_STATUS; - hdr->host = info.desc.host_id; + hdr->host = TI_SCI_HOST_ID; /* Setup with NORESPONSE flag to keep response queue clean */ hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE; diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h index a921e512a..2d23f9a9c 100644 --- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h +++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h @@ -563,8 +563,13 @@ struct ti_sci_msg_req_set_proc_boot_config { uint32_t config_flags_clear; } __packed; +/* ARMV8 Control Flags */ +#define PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM 0x00000001 +#define PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS 0x00000002 +#define PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ 0x00000100 + /* R5 Control Flags */ -#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 +#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 /** * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags @@ -618,6 +623,8 @@ struct ti_sci_msg_req_get_proc_boot_status { /* ARMv8 Status Flags */ #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002 +#define PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE 0x00000010 +#define PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 0x00000020 /* R5 Status Flags */ #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001 diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index de9cefe5b..cf0a21d01 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -17,6 +17,10 @@ #include <k3_gicv3.h> #include <ti_sci.h> +#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) +#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) +#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) + uintptr_t k3_sec_entrypoint; static void k3_cpu_standby(plat_local_state_t cpu_state) @@ -37,30 +41,40 @@ static void k3_cpu_standby(plat_local_state_t cpu_state) static int k3_pwr_domain_on(u_register_t mpidr) { - int core_id, proc, device, ret; + int core, proc_id, device_id, ret; - core_id = plat_core_pos_by_mpidr(mpidr); - if (core_id < 0) { - ERROR("Could not get target core id: %d\n", core_id); + core = plat_core_pos_by_mpidr(mpidr); + if (core < 0) { + ERROR("Could not get target core id: %d\n", core); return PSCI_E_INTERN_FAIL; } - proc = PLAT_PROC_START_ID + core_id; - device = PLAT_PROC_DEVICE_START_ID + core_id; + proc_id = PLAT_PROC_START_ID + core; + device_id = PLAT_PROC_DEVICE_START_ID + core; - ret = ti_sci_proc_request(proc); + ret = ti_sci_proc_request(proc_id); if (ret) { ERROR("Request for processor failed: %d\n", ret); return PSCI_E_INTERN_FAIL; } - ret = ti_sci_proc_set_boot_cfg(proc, k3_sec_entrypoint, 0, 0); + ret = ti_sci_proc_set_boot_cfg(proc_id, k3_sec_entrypoint, 0, 0); if (ret) { ERROR("Request to set core boot address failed: %d\n", ret); return PSCI_E_INTERN_FAIL; } - ret = ti_sci_device_get(device); + /* sanity check these are off before starting a core */ + ret = ti_sci_proc_set_boot_ctrl(proc_id, + 0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ | + PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS | + PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM); + if (ret) { + ERROR("Request to clear boot configuration failed: %d\n", ret); + return PSCI_E_INTERN_FAIL; + } + + ret = ti_sci_device_get(device_id); if (ret) { ERROR("Request to start core failed: %d\n", ret); return PSCI_E_INTERN_FAIL; @@ -71,17 +85,35 @@ static int k3_pwr_domain_on(u_register_t mpidr) void k3_pwr_domain_off(const psci_power_state_t *target_state) { - int core_id, proc, device, ret; + int core, cluster, proc_id, device_id, cluster_id, ret; + + /* At very least the local core should be powering down */ + assert(CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); /* Prevent interrupts from spuriously waking up this cpu */ k3_gic_cpuif_disable(); - core_id = plat_my_core_pos(); - proc = PLAT_PROC_START_ID + core_id; - device = PLAT_PROC_DEVICE_START_ID + core_id; + core = plat_my_core_pos(); + cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); + proc_id = PLAT_PROC_START_ID + core; + device_id = PLAT_PROC_DEVICE_START_ID + core; + cluster_id = PLAT_CLUSTER_DEVICE_START_ID + (cluster * 2); + + /* + * If we are the last core in the cluster then we take a reference to + * the cluster device so that it does not get shutdown before we + * execute the entire cluster L2 cleaning sequence below. + */ + if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { + ret = ti_sci_device_get(cluster_id); + if (ret) { + ERROR("Request to get cluster failed: %d\n", ret); + return; + } + } /* Start by sending wait for WFI command */ - ret = ti_sci_proc_wait_boot_status_no_wait(proc, + ret = ti_sci_proc_wait_boot_status_no_wait(proc_id, /* * Wait maximum time to give us the best chance to get * to WFI before this command timeouts @@ -95,11 +127,72 @@ void k3_pwr_domain_off(const psci_power_state_t *target_state) } /* Now queue up the core shutdown request */ - ret = ti_sci_device_put_no_wait(device); + ret = ti_sci_device_put_no_wait(device_id); if (ret) { ERROR("Sending core shutdown message failed (%d)\n", ret); return; } + + /* If our cluster is not going down we stop here */ + if (CLUSTER_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) + return; + + /* set AINACTS */ + ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id, + PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS, 0); + if (ret) { + ERROR("Sending set control message failed (%d)\n", ret); + return; + } + + /* set L2FLUSHREQ */ + ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id, + PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ, 0); + if (ret) { + ERROR("Sending set control message failed (%d)\n", ret); + return; + } + + /* wait for L2FLUSHDONE*/ + ret = ti_sci_proc_wait_boot_status_no_wait(proc_id, + UINT8_MAX, 2, UINT8_MAX, UINT8_MAX, + PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE, 0, 0, 0); + if (ret) { + ERROR("Sending wait message failed (%d)\n", ret); + return; + } + + /* clear L2FLUSHREQ */ + ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id, + 0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ); + if (ret) { + ERROR("Sending set control message failed (%d)\n", ret); + return; + } + + /* set ACINACTM */ + ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id, + PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM, 0); + if (ret) { + ERROR("Sending set control message failed (%d)\n", ret); + return; + } + + /* wait for STANDBYWFIL2 */ + ret = ti_sci_proc_wait_boot_status_no_wait(proc_id, + UINT8_MAX, 2, UINT8_MAX, UINT8_MAX, + PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2, 0, 0, 0); + if (ret) { + ERROR("Sending wait message failed (%d)\n", ret); + return; + } + + /* Now queue up the cluster shutdown request */ + ret = ti_sci_device_put_no_wait(cluster_id); + if (ret) { + ERROR("Sending cluster shutdown message failed (%d)\n", ret); + return; + } } void k3_pwr_domain_on_finish(const psci_power_state_t *target_state) diff --git a/plat/xilinx/common/include/plat_startup.h b/plat/xilinx/common/include/plat_startup.h new file mode 100644 index 000000000..66e793373 --- /dev/null +++ b/plat/xilinx/common/include/plat_startup.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_STARTUP_H +#define PLAT_STARTUP_H + +/* For FSBL handover */ +enum fsbl_handoff { + FSBL_HANDOFF_SUCCESS = 0, + FSBL_HANDOFF_NO_STRUCT, + FSBL_HANDOFF_INVAL_STRUCT, + FSBL_HANDOFF_TOO_MANY_PARTS +}; + +enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32_image_ep_info, + entry_point_info_t *bl33_image_ep_info, + uint64_t atf_handoff_addr); + +#endif /* PLAT_STARTUP_H */ diff --git a/plat/xilinx/zynqmp/plat_startup.c b/plat/xilinx/common/plat_startup.c index cd2c3bac6..8c9a049dd 100644 --- a/plat/xilinx/zynqmp/plat_startup.c +++ b/plat/xilinx/common/plat_startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,10 +8,8 @@ #include <arch_helpers.h> #include <common/debug.h> -#include <lib/mmio.h> -#include <plat_private.h> +#include <plat_startup.h> -#include "zynqmp_def.h" /* * ATFHandoffParams @@ -147,6 +145,7 @@ static int get_fsbl_estate(const struct xfsbl_partition *partition) * Populates the bl32 and bl33 image info structures * @bl32: BL32 image info structure * @bl33: BL33 image info structure + * atf_handoff_addr: ATF handoff address * * Process the handoff paramters from the FSBL and populate the BL32 and BL33 * image info structures accordingly. @@ -154,12 +153,11 @@ static int get_fsbl_estate(const struct xfsbl_partition *partition) * Return: Return the status of the handoff. The value will be from the * fsbl_handoff enum. */ -enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32, entry_point_info_t *bl33) +enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32, + entry_point_info_t *bl33, + uint64_t atf_handoff_addr) { - uint64_t atf_handoff_addr; const struct xfsbl_atf_handoff_params *ATFHandoffParams; - - atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); assert((atf_handoff_addr < BL31_BASE) || (atf_handoff_addr > (uint64_t)&__BL31_END__)); if (!atf_handoff_addr) { diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 825421e29..2fa847658 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,11 +67,3 @@ unsigned int plat_get_syscnt_freq2(void) return VERSAL_CPU_CLOCK; } -uintptr_t plat_get_ns_image_entrypoint(void) -{ -#ifdef PRELOADED_BL33_BASE - return PRELOADED_BL33_BASE; -#else - return PLAT_VERSAL_NS_IMAGE_OFFSET; -#endif -} diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c index 6b56307af..a5cf05e9a 100644 --- a/plat/xilinx/versal/bl31_versal_setup.c +++ b/plat/xilinx/versal/bl31_versal_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,8 +13,12 @@ #include <common/debug.h> #include <drivers/arm/pl011.h> #include <drivers/console.h> +#include <lib/mmio.h> #include <lib/xlat_tables/xlat_tables.h> #include <plat/common/platform.h> +#include <versal_def.h> +#include <plat_private.h> +#include <plat_startup.h> static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -37,6 +41,18 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) } /* + * Set the build time defaults,if we can't find any config data. + */ +static inline void bl31_set_default_config(void) +{ + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + +/* * Perform any BL31 specific platform actions. Here is an opportunity to copy * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they * are lost (potentially). This needs to be done before the MMU is initialized @@ -45,6 +61,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { + uint64_t atf_handoff_addr; /* Initialize the console to provide early debug support */ int rc = console_pl011_register(VERSAL_UART_BASE, @@ -76,12 +93,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); - /* use build time defaults in JTAG boot mode */ - bl32_image_ep_info.pc = BL32_BASE; - bl32_image_ep_info.spsr = 0; - bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); - bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); + atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); + enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, + &bl33_image_ep_info, + atf_handoff_addr); + if (ret == FSBL_HANDOFF_NO_STRUCT) { + bl31_set_default_config(); + } else if (ret != FSBL_HANDOFF_SUCCESS) { + panic(); + } NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h index bcc7a9364..4cdaea219 100644 --- a/plat/xilinx/versal/include/platform_def.h +++ b/plat/xilinx/versal/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ /* Size of cacheable stacks */ #define PLATFORM_STACK_SIZE 0x440 -#define PLATFORM_CORE_COUNT 2 +#define PLATFORM_CORE_COUNT U(2) #define PLAT_MAX_PWR_LVL 1 #define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_OFF_STATE 2 @@ -56,9 +56,9 @@ * BL33 specific defines. ******************************************************************************/ #ifndef PRELOADED_BL33_BASE -# define PLAT_VERSAL_NS_IMAGE_OFFSET 0x8000000 +# define PLAT_ARM_NS_IMAGE_BASE 0x8000000 #else -# define PLAT_VERSAL_NS_IMAGE_OFFSET PRELOADED_BL33_BASE +# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE #endif /******************************************************************************* diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index 94bd321b8..9a9b7c017 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -121,6 +121,10 @@ #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 +/* PMC registers and bitfields */ +#define PMC_GLOBAL_BASE 0xF1110000 +#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40) + /* IPI registers and bitfields */ #define IPI0_REG_BASE 0xFF330000 #define IPI0_TRIG_BIT (1 << 2) diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index 7a8bfa31a..1e231cce8 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -55,6 +55,7 @@ PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ drivers/arm/pl011/aarch64/pl011_console.S \ plat/common/aarch64/crash_console_helpers.S \ plat/arm/common/arm_cci.c \ + plat/arm/common/arm_common.c \ plat/common/plat_gicv3.c \ plat/xilinx/versal/aarch64/versal_helpers.S \ plat/xilinx/versal/aarch64/versal_common.c @@ -64,6 +65,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ lib/cpus/aarch64/cortex_a72.S \ plat/common/plat_psci_common.c \ plat/xilinx/common/ipi.c \ + plat/xilinx/common/plat_startup.c \ plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ plat/xilinx/common/pm_service/pm_ipi.c \ plat/xilinx/versal/bl31_versal_setup.c \ diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 285a4eb8b..6e0e811d4 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,8 +13,11 @@ #include <drivers/console.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> +#include <lib/mmio.h> +#include <plat_startup.h> #include <plat_private.h> +#include <zynqmp_def.h> static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -57,6 +60,7 @@ static inline void bl31_set_default_config(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { + uint64_t atf_handoff_addr; /* Register the console to provide early debug support */ static console_cdns_t bl31_boot_console; (void)console_cdns_register(ZYNQMP_UART_BASE, @@ -86,12 +90,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); + if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { bl31_set_default_config(); } else { /* use parameters from FSBL */ enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, - &bl33_image_ep_info); + &bl33_image_ep_info, + atf_handoff_addr); if (ret == FSBL_HANDOFF_NO_STRUCT) bl31_set_default_config(); else if (ret != FSBL_HANDOFF_SUCCESS) diff --git a/plat/xilinx/zynqmp/include/plat_private.h b/plat/xilinx/zynqmp/include/plat_private.h index 8bdf42967..288cc5301 100644 --- a/plat/xilinx/zynqmp/include/plat_private.h +++ b/plat/xilinx/zynqmp/include/plat_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,13 +21,6 @@ unsigned int zynqmp_calc_core_pos(u_register_t mpidr); unsigned int zynqmp_get_uart_clk(void); unsigned int zynqmp_get_bootmode(void); -/* For FSBL handover */ -enum fsbl_handoff { - FSBL_HANDOFF_SUCCESS = 0, - FSBL_HANDOFF_NO_STRUCT, - FSBL_HANDOFF_INVAL_STRUCT, - FSBL_HANDOFF_TOO_MANY_PARTS, -}; #if ZYNQMP_WDT_RESTART /* @@ -37,7 +30,4 @@ enum fsbl_handoff { int request_intr_type_el3(uint32_t, interrupt_type_handler_t); #endif -enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32_image_ep_info, - entry_point_info_t *bl33_image_ep_info); - #endif /* PLAT_PRIVATE_H */ diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index 7b062fcaa..27968409e 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,8 +21,8 @@ /* Size of cacheable stacks */ #define PLATFORM_STACK_SIZE 0x440 -#define PLATFORM_CORE_COUNT 4 -#define PLAT_NUM_POWER_DOMAINS 5 +#define PLATFORM_CORE_COUNT U(4) +#define PLAT_NUM_POWER_DOMAINS U(5) #define PLAT_MAX_PWR_LVL U(1) #define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_OFF_STATE U(2) diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index de4bf3a0b..44f20f69f 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -82,10 +82,10 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/common/plat_psci_common.c \ plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ plat/xilinx/common/pm_service/pm_ipi.c \ + plat/xilinx/common/plat_startup.c \ plat/xilinx/zynqmp/bl31_zynqmp_setup.c \ plat/xilinx/zynqmp/plat_psci.c \ plat/xilinx/zynqmp/plat_zynqmp.c \ - plat/xilinx/zynqmp/plat_startup.c \ plat/xilinx/zynqmp/plat_topology.c \ plat/xilinx/zynqmp/sip_svc_setup.c \ plat/xilinx/zynqmp/pm_service/pm_svc_main.c \ diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c index a900057e8..4b8dfb614 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -1477,6 +1477,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { }, [PINCTRL_PIN_26] = { .groups = &((uint16_t []) { + PINCTRL_GRP_ETHERNET0_0, PINCTRL_GRP_GEMTSU0_0, PINCTRL_GRP_NAND0_1_CE, PINCTRL_GRP_PMU0_0, diff --git a/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S b/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S index dab615012..be4084cfb 100644 --- a/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S +++ b/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -87,7 +87,7 @@ vector_entry SynchronousExceptionA64, .spm_shim_exceptions do_smc: mrs x30, tpidr_el1 smc #0 - eret + exception_return /* AArch64 system instructions trap are handled as a panic for now */ handle_sys_trap: |