diff options
| -rw-r--r-- | drivers/marvell/mochi/cp110_setup.c | 6 | ||||
| -rw-r--r-- | include/drivers/marvell/mochi/cp110_setup.h | 1 | ||||
| -rw-r--r-- | plat/marvell/a8k/common/mss/mss_a8k.mk | 3 | ||||
| -rw-r--r-- | plat/marvell/a8k/common/mss/mss_bl2_setup.c | 6 | ||||
| -rw-r--r-- | plat/marvell/common/mss/mss_scp_bootloader.c | 37 |
5 files changed, 44 insertions, 9 deletions
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index b4b4e0c82..7186f9857 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -303,7 +303,7 @@ static void cp110_axi_attr_init(uintptr_t base) DOMAIN_SYSTEM_SHAREABLE); } -static void amb_bridge_init(uintptr_t base) +void cp110_amb_init(uintptr_t base) { uint32_t reg; @@ -399,7 +399,7 @@ void cp110_init(uintptr_t cp110_base, uint32_t stream_id) cp110_stream_id_init(cp110_base, stream_id); /* Open AMB bridge for comphy for CP0 & CP1*/ - amb_bridge_init(cp110_base); + cp110_amb_init(cp110_base); /* Reset RTC if needed */ cp110_rtc_init(cp110_base); @@ -411,7 +411,7 @@ void cp110_ble_init(uintptr_t cp110_base) #if PCI_EP_SUPPORT INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); - amb_bridge_init(cp110_base); + cp110_amb_init(cp110_base); /* Configure PCIe clock */ cp110_pcie_clk_cfg(cp110_base); diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h index 3686257d3..f8cd26b12 100644 --- a/include/drivers/marvell/mochi/cp110_setup.h +++ b/include/drivers/marvell/mochi/cp110_setup.h @@ -51,5 +51,6 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base) void cp110_init(uintptr_t cp110_base, uint32_t stream_id); void cp110_ble_init(uintptr_t cp110_base); +void cp110_amb_init(uintptr_t base); #endif /* CP110_SETUP_H */ diff --git a/plat/marvell/a8k/common/mss/mss_a8k.mk b/plat/marvell/a8k/common/mss/mss_a8k.mk index 58f23d8dd..efd03c5a2 100644 --- a/plat/marvell/a8k/common/mss/mss_a8k.mk +++ b/plat/marvell/a8k/common/mss/mss_a8k.mk @@ -8,7 +8,8 @@ PLAT_MARVELL := plat/marvell A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss -BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c +BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c \ + $(MARVELL_MOCHI_DRV) BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c index 728ee54a0..09b8446fa 100644 --- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c @@ -74,6 +74,12 @@ static int bl2_plat_mmap_init(void) /* Set the default target id to PIDI */ mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID); + /* Open AMB bridge required for MG access */ + cp110_amb_init(MVEBU_CP_REGS_BASE(0)); + + if (CP_COUNT == 2) + cp110_amb_init(MVEBU_CP_REGS_BASE(1)); + return 0; } diff --git a/plat/marvell/common/mss/mss_scp_bootloader.c b/plat/marvell/common/mss/mss_scp_bootloader.c index 7e442c615..2f1c46f47 100644 --- a/plat/marvell/common/mss/mss_scp_bootloader.c +++ b/plat/marvell/common/mss/mss_scp_bootloader.c @@ -42,6 +42,8 @@ #define MSS_HANDSHAKE_TIMEOUT 50 +#define MG_CM3_SRAM_BASE(CP) (MVEBU_CP_REGS_BASE(CP) + 0x100000) + static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) { int timeout = MSS_HANDSHAKE_TIMEOUT; @@ -59,6 +61,28 @@ static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) return 0; } +static int mg_image_load(uintptr_t src_addr, uint32_t size, uintptr_t mg_regs) +{ + if (size > MG_SRAM_SIZE) { + ERROR("image is too big to fit into MG CM3 memory\n"); + return 1; + } + + NOTICE("Loading MG image from address 0x%lx Size 0x%x to MG at 0x%lx\n", + src_addr, size, mg_regs); + + /* Copy image to MG CM3 SRAM */ + memcpy((void *)mg_regs, (void *)src_addr, size); + + /* + * Don't release MG CM3 from reset - it will be done by next step + * bootloader (e.g. U-Boot), when appriopriate device-tree setup (which + * has enabeld 802.3. auto-neg) will be choosen. + */ + + return 0; +} + static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs) { uint32_t i, loop_num, timeout; @@ -225,12 +249,15 @@ static int load_img_to_cm3(enum cm3_t cm3_type, } break; case MG_CP0: - /* TODO: */ - NOTICE("Load image to CP0 MG not supported\n"); - break; case MG_CP1: - /* TODO: */ - NOTICE("Load image to CP1 MG not supported\n"); + cp_index = cm3_type - MG_CP0; + NOTICE("Load image to CP%d MG\n", cp_index); + ret = mg_image_load(single_img, image_size, + MG_CM3_SRAM_BASE(cp_index)); + if (ret != 0) { + ERROR("SCP Image load failed\n"); + return -1; + } break; default: ERROR("SCP_BL2 wrong img format (cm3_type=%d)\n", cm3_type); |