diff options
| -rw-r--r-- | Makefile | 28 | ||||
| -rw-r--r-- | docs/change-log.rst | 4 | ||||
| -rw-r--r-- | docs/components/fconf.rst | 3 | ||||
| -rw-r--r-- | docs/components/index.rst | 1 | ||||
| -rw-r--r-- | docs/components/spci-manifest-binding.rst | 14 | ||||
| -rw-r--r-- | docs/getting_started/build-options.rst | 5 | ||||
| -rw-r--r-- | docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml | 6 | ||||
| -rw-r--r-- | docs/resources/diagrams/plantuml/fconf_bl2_populate.puml | 6 | ||||
| -rw-r--r-- | make_helpers/defaults.mk | 5 | ||||
| -rw-r--r-- | plat/socionext/uniphier/platform.mk | 7 | ||||
| -rw-r--r-- | plat/socionext/uniphier/tsp/uniphier_tsp_setup.c | 2 | ||||
| -rw-r--r-- | plat/socionext/uniphier/uniphier_bl2_setup.c | 1 | ||||
| -rw-r--r-- | plat/socionext/uniphier/uniphier_bl31_setup.c | 2 | ||||
| -rw-r--r-- | plat/socionext/uniphier/uniphier_xlat_setup.c | 15 |
14 files changed, 87 insertions, 12 deletions
@@ -187,6 +187,34 @@ march64-directive = -march=armv8.${ARM_ARCH_MINOR}-a endif endif +# Memory tagging is supported in architecture Armv8.5-A AArch64 and onwards +ifeq ($(ARCH), aarch64) +ifeq ($(shell test $(ARM_ARCH_MAJOR) -gt 8; echo $$?),0) +mem_tag_arch_support = yes +else ifeq ($(shell test $(ARM_ARCH_MAJOR) -eq 8 -a $(ARM_ARCH_MINOR) -ge 5; \ + echo $$?),0) +mem_tag_arch_support = yes +endif +endif + +# Enabled required option for memory stack tagging. Currently, these options are +# enabled only for clang and armclang compiler. +ifeq (${SUPPORT_STACK_MEMTAG},yes) +ifdef mem_tag_arch_support +ifneq ( ,$(filter $(notdir $(CC)),armclang clang)) +march64-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a+memtag +ifeq ($(notdir $(CC)),armclang) +TF_CFLAGS += -mmemtag-stack +else ifeq ($(notdir $(CC)),clang) +TF_CFLAGS += -fsanitize=memtag +endif +endif +else +$(error "Error: stack memory tagging is not supported for architecture \ + ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a") +endif +endif + ifneq ($(findstring armclang,$(notdir $(CC))),) TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive) TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi $(march64-directive) diff --git a/docs/change-log.rst b/docs/change-log.rst index cf5b57ac6..7e072a930 100644 --- a/docs/change-log.rst +++ b/docs/change-log.rst @@ -17,6 +17,7 @@ New Features - Enable Memory Tagging Extension (MTE) support in both secure and non-secure worlds + - Adds support for the new Memory Tagging Extension arriving in ARMv8.5. MTE support is now enabled by default on systems that support it at EL0. @@ -84,6 +85,7 @@ New Features - gicv3: Enabled multi-socket GIC redistributor frame discovery and migrated ARM platforms to the new API + - Adds ``gicv3_rdistif_probe`` function that delegates the responsibility of discovering the corresponding redistributor base frame to each CPU itself. @@ -2841,7 +2843,7 @@ releases of TF-A. -------------- -*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.* .. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf .. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501 diff --git a/docs/components/fconf.rst b/docs/components/fconf.rst index 385660083..7352ac37a 100644 --- a/docs/components/fconf.rst +++ b/docs/components/fconf.rst @@ -107,6 +107,7 @@ As mentioned above, properties are logically grouped around namespaces and sub-namespaces. The following concepts should be considered when adding new properties/namespaces. The framework differentiates two types of properties: + - Properties used inside common code. - Properties used inside platform specific code. @@ -114,6 +115,7 @@ The first category applies to properties being part of the firmware and shared across multiple platforms. They should be globally accessible and defined inside the ``lib/fconf`` directory. The namespace must be chosen to reflect the feature/data abstracted. + Example: - |TBBR| related properties: tbbr.cot.bl2_id - Dynamic configuration information: dyn_cfg.dtb_info.hw_config_id @@ -123,6 +125,7 @@ within the framework: Platform specific properties. They must be accessed only within the platform API and are defined only inside the platform scope. The namespace must contain the platform name under which the properties defined belong. + Example: - Arm io framework: arm.io_policies.bl31_id diff --git a/docs/components/index.rst b/docs/components/index.rst index ae78b2bd1..49986ca00 100644 --- a/docs/components/index.rst +++ b/docs/components/index.rst @@ -17,4 +17,5 @@ Components romlib-design sdei secure-partition-manager-design + spci-manifest-binding xlat-tables-lib-v2-design diff --git a/docs/components/spci-manifest-binding.rst b/docs/components/spci-manifest-binding.rst index 66cca643b..584816911 100644 --- a/docs/components/spci-manifest-binding.rst +++ b/docs/components/spci-manifest-binding.rst @@ -16,6 +16,7 @@ spci-manifest-partition minor versions fo the device tree binding for the SPCI manifest represented by this node. The minor number is incremented if the binding changes in a backwards compatible manner. + - X is an integer representing the major version number of this document. - Y is an integer representing the minor version number of this document. @@ -23,6 +24,7 @@ spci-manifest-partition - value type: <u32> - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X, 15:0 -> Y, where: + - X is the major version of PSA-FF-A expected by the partition at the SPCI instance it will execute. - Y is the minor version of PSA-FF-A expected by the partition at the SPCI @@ -34,10 +36,12 @@ spci-manifest-partition implemented by this partition. The UUID format is described in RFC 4122. UUID can be shared by multiple instances of partitions that offer the same service For example: + - If there are multiple instances of a Trusted OS, then the UUID can be shared by all instances. - The TEE driver in the HLOS can use the UUID with the SPCI_PARTITION_INFO_GET interface to determine the: + - Number of Trusted OSs - The partition ID of each instance of the Trusted OS @@ -56,6 +60,7 @@ spci-manifest-partition - execution-ctx-count [mandatory] - value type: <u32> - Number of vCPUs that a VM or SP wants to instantiate. + - In the absence of virtualization, this is the number of execution contexts that a partition implements. - If value of this field = 1 and number of PEs > 1 then the partition is @@ -66,6 +71,7 @@ spci-manifest-partition - exception-level [mandatory] - value type: <u32> - The target exception level for the partition: + - 0x0: EL1 - 0x1: S_EL0 - 0x2: S_EL1 @@ -76,6 +82,7 @@ spci-manifest-partition - execution-state [mandatory] - value type: <u32> - The target execution state of the partition: + - 0: AArch64 - 1: AArch32 @@ -94,6 +101,7 @@ spci-manifest-partition - xlat-granule [mandatory] - value type: <u32> - Translation granule used with the partition: + - 0x0: 4k - 0x1: 16k - 0x2: 32k @@ -113,6 +121,7 @@ spci-manifest-partition - messaging-method [mandatory] - value type: <u32> - Specifies which messaging methods are supported by the partition: + - 0x0: direct messaging method - 0x1: indirect messaging method - 0x2: both direct and indirect messaging methods @@ -125,6 +134,7 @@ spci-manifest-partition - run-time-model - value type: <u32> - Run time model that the SPM must enforce for this SP: + - 0x0: Run to completion - 0x1: Preemptible @@ -195,6 +205,7 @@ device-regions - reg [mandatory] - value type: <prop-encoded-array> - A (address, num-pages) pair describing the device, where: + - address: The physical base address <u64> value of the device MMIO region. - num-pages: The <u32> number of pages of the region. The total size of @@ -214,15 +225,18 @@ device-regions - stream-ids [mandatory] - value type: <prop-encoded-array> - A list of (id, mem-manage) pair, where: + - id: A unique <u32> value amongst all devices assigned to the partition. - mem-manage: A <u32> value used in memory management operations. - interrupts [mandatory] - value type: <prop-encoded-array> - A list of (id, attributes) pair describing the device interrupts, where: + - id: The <u32> interrupt IDs. - attributes: A ?? TO DEFINE value, containing the attributes for each interrupt ID: + - Interrupt type: SPI, PPI, SGI - Interrupt configuration: Edge triggered, Level triggered - Interrupt security state: Secure, Non-secure diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 69e103d38..e1c6c8f80 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -667,6 +667,11 @@ Common build options cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0. +- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory + tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The + default value of this flag is ``no``. Note this option must be enabled only + for ARM architecture greater than Armv8.5-A. + GICv3 driver options -------------------- diff --git a/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml b/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml index c36e54423..e613eefd0 100644 --- a/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml +++ b/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml @@ -24,9 +24,9 @@ arm_bl1_setup -> fconf : fconf_load_config() activate fconf note over fconf create and populate an - image_desc_t for TB_FW_CONFIG + image_desc_t for FW_CONFIG end note - fconf -> bl_common : load_auth_image(TB_FW_CONFIG_ID, &image_info) + fconf -> bl_common : load_auth_image(FW_CONFIG_ID, &image_info) activate bl_common note over bl_common load and auth image from fip @@ -42,7 +42,7 @@ activate fconf fconf <- plat_bl1_common : BL2_IMAGE_DESC note over fconf set ep_info.args.arg0 of BL2_IMAGE_DESC - to TB_FW_CONFIG base address + to FW_CONFIG base address end note arm_bl1_setup <- fconf deactivate fconf diff --git a/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml b/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml index 98a3ff19b..881f25343 100644 --- a/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml +++ b/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml @@ -20,12 +20,12 @@ end box bl2_entrypoint -> bl2_main : bl2_setup() bl2_main -> arm_bl2_setup : bl2_early_platform_setup2(\n\t arg0, arg1, arg2, arg3) note over arm_bl2_setup - arg0 = tb_fw_config + arg0 = fw_config arg1 = mem_layout end note -arm_bl2_setup -> arm_bl2_setup : arm_bl2_early_platform_setup(\n\t tb_fw_config, mem_layout) +arm_bl2_setup -> arm_bl2_setup : arm_bl2_early_platform_setup(\n\t fw_config, mem_layout) activate arm_bl2_setup - arm_bl2_setup -> fconf: fconf_polulate(tb_fw_config) + arm_bl2_setup -> fconf: fconf_polulate("TB_FW", fw_config) activate fconf fconf -> fconf_tbbr_getter: fconf_populate_tbbr_dyn_config(uintptr_t dtb) note over fconf_tbbr_getter: read tbbr propeties from dtb diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 4e968e2d3..590a800a6 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -288,3 +288,8 @@ ENABLE_LTO := 0 # S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. # Default is 0. CTX_INCLUDE_EL2_REGS := 0 + +# Enable Memory tag extension which is supported for architecture greater +# than Armv8.5-A +# By default it is set to "no" +SUPPORT_STACK_MEMTAG := no diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index 0fcef1d2c..3f8a1f864 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -14,6 +14,13 @@ override ENABLE_SVE_FOR_NS := 0 # UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses. override ENABLE_PIE := 1 +ALLOW_RO_XLAT_TABLES := 1 + +ifeq ($(ALLOW_RO_XLAT_TABLES),1) +BL31_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 +BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1 +endif + # Cortex-A53 revision r0p4-51rel0 # needed for LD20, unneeded for LD11, PXs3 (no ACE) ERRATA_A53_855873 := 1 diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c index 091a6f7a9..4bbb2595c 100644 --- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c +++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c @@ -9,7 +9,6 @@ #include <platform_def.h> #include <common/bl_common.h> -#include <lib/xlat_tables/xlat_mmu_helpers.h> #include <plat/common/platform.h> #include "../uniphier.h" @@ -32,5 +31,4 @@ void tsp_platform_setup(void) void tsp_plat_arch_setup(void) { uniphier_mmap_setup(uniphier_soc); - enable_mmu_el1(0); } diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c index 7a7f78681..679f14d0a 100644 --- a/plat/socionext/uniphier/uniphier_bl2_setup.c +++ b/plat/socionext/uniphier/uniphier_bl2_setup.c @@ -44,7 +44,6 @@ void bl2_el3_plat_arch_setup(void) int ret; uniphier_mmap_setup(uniphier_soc); - enable_mmu_el3(0); /* add relocation offset (run-time-address - link-address) */ uniphier_mem_base += BL_CODE_BASE - BL2_BASE; diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c index f2f0b298a..c2baebde9 100644 --- a/plat/socionext/uniphier/uniphier_bl31_setup.c +++ b/plat/socionext/uniphier/uniphier_bl31_setup.c @@ -14,7 +14,6 @@ #include <common/debug.h> #include <drivers/console.h> #include <lib/mmio.h> -#include <lib/xlat_tables/xlat_mmu_helpers.h> #include <plat/common/platform.h> #include "uniphier.h" @@ -87,5 +86,4 @@ void bl31_platform_setup(void) void bl31_plat_arch_setup(void) { uniphier_mmap_setup(uniphier_soc); - enable_mmu_el3(0); } diff --git a/plat/socionext/uniphier/uniphier_xlat_setup.c b/plat/socionext/uniphier/uniphier_xlat_setup.c index 66c7834f5..5043f4b59 100644 --- a/plat/socionext/uniphier/uniphier_xlat_setup.c +++ b/plat/socionext/uniphier/uniphier_xlat_setup.c @@ -10,6 +10,7 @@ #include <common/debug.h> #include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> #include "uniphier.h" @@ -63,4 +64,18 @@ void uniphier_mmap_setup(unsigned int soc) MT_DEVICE | MT_RW | MT_SECURE); init_xlat_tables(); + + enable_mmu(0); + +#if PLAT_RO_XLAT_TABLES + { + int ret; + + ret = xlat_make_tables_readonly(); + if (ret) { + ERROR("Failed to make translation tables read-only."); + plat_error_handler(ret); + } + } +#endif } |