diff options
31 files changed, 531 insertions, 384 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 0d1077cbd..58e8afbd2 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -170,15 +170,12 @@ func bl31_warm_entrypoint * enter coherency (as CPUs already are); and there's no reason to have * caches disabled either. */ - mov x0, #DISABLE_DCACHE - bl bl31_plat_enable_mmu - #if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY - mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_C_BIT - msr sctlr_el3, x0 - isb + mov x0, xzr +#else + mov x0, #DISABLE_DCACHE #endif + bl bl31_plat_enable_mmu bl psci_warmboot_entrypoint diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 87ef3f36e..d6853cc40 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -298,20 +298,17 @@ func sp_min_warm_entrypoint * enter coherency (as CPUs already are); and there's no reason to have * caches disabled either. */ +#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY + mov r0, #0 +#else mov r0, #DISABLE_DCACHE +#endif bl bl32_plat_enable_mmu #if SP_MIN_WITH_SECURE_FIQ route_fiq_to_sp_min r0 #endif -#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY - ldcopr r0, SCTLR - orr r0, r0, #SCTLR_C_BIT - stcopr r0, SCTLR - isb -#endif - bl sp_min_warm_boot bl smc_get_next_ctx /* r0 points to `smc_ctx_t` */ diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 489183c52..5d9da8578 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -247,41 +247,13 @@ func tsp_cpu_on_entry bl plat_set_my_stack /* -------------------------------------------- - * Enable the MMU with the DCache disabled. It - * is safe to use stacks allocated in normal - * memory as a result. All memory accesses are - * marked nGnRnE when the MMU is disabled. So - * all the stack writes will make it to memory. - * All memory accesses are marked Non-cacheable - * when the MMU is enabled but D$ is disabled. - * So used stack memory is guaranteed to be - * visible immediately after the MMU is enabled - * Enabling the DCache at the same time as the - * MMU can lead to speculatively fetched and - * possibly stale stack memory being read from - * other caches. This can lead to coherency - * issues. + * Enable MMU and D-caches together. * -------------------------------------------- */ - mov x0, #DISABLE_DCACHE + mov x0, #0 bl bl32_plat_enable_mmu /* --------------------------------------------- - * Enable the Data cache now that the MMU has - * been enabled. The stack has been unwound. It - * will be written first before being read. This - * will invalidate any stale cache lines resi- - * -dent in other caches. We assume that - * interconnect coherency has been enabled for - * this cluster by EL3 firmware. - * --------------------------------------------- - */ - mrs x0, sctlr_el1 - orr x0, x0, #SCTLR_C_BIT - msr sctlr_el1, x0 - isb - - /* --------------------------------------------- * Enter C runtime to perform any remaining * book keeping * --------------------------------------------- diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst index e3500c27b..8aa762278 100644 --- a/docs/firmware-design.rst +++ b/docs/firmware-design.rst @@ -306,6 +306,8 @@ On Arm platforms, BL1 performs the following platform initializations: - If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then load it to the platform defined address and make it available to BL2 via ``arg0``. +- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U + and NS-BL2U firmware update images. Firmware Update detection and execution ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index a737cf4e6..5462cc1ec 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -1997,6 +1997,25 @@ state. This function must return a pointer to the ``entry_point_info`` structure (that was copied during ``bl31_early_platform_setup()``) if the image exists. It should return NULL otherwise. +Function : bl31_plat_enable_mmu [optional] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uint32_t + Return : void + +This function enables the MMU. The boot code calls this function with MMU and +caches disabled. This function should program necessary registers to enable +translation, and upon return, the MMU on the calling PE must be enabled. + +The function must honor flags passed in the first argument. These flags are +defined by the translation library, and can be found in the file +``include/lib/xlat_tables/xlat_mmu_helpers.h``. + +On DynamIQ systems, this function must not use stack while enabling MMU, which +is how the function in xlat table library version 2 is implementated. + Function : plat\_get\_syscnt\_freq2() [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/user-guide.rst b/docs/user-guide.rst index a40615dbf..68a74edd5 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -454,6 +454,10 @@ Common build options management operations. This option defaults to 0 and if it is enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. + Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of + translation library (xlat tables v2) must be used; version 1 of translation + library is not supported. + - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 runtime software in AArch32 mode, which is required to run AArch32 on Juno. By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in diff --git a/include/common/aarch32/asm_macros.S b/include/common/aarch32/asm_macros.S index 74322228e..f7d0595e1 100644 --- a/include/common/aarch32/asm_macros.S +++ b/include/common/aarch32/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,20 @@ #include <asm_macros_common.S> #include <spinlock.h> +/* + * TLBI instruction with type specifier that implements the workaround for + * errata 813419 of Cortex-A57. + */ +#if ERRATA_A57_813419 +#define TLB_INVALIDATE(_reg, _coproc) \ + stcopr _reg, _coproc; \ + dsb ish; \ + stcopr _reg, _coproc +#else +#define TLB_INVALIDATE(_reg, _coproc) \ + stcopr _reg, _coproc +#endif + #define WORD_SIZE 4 /* diff --git a/include/common/aarch64/asm_macros.S b/include/common/aarch64/asm_macros.S index 7c8e643d1..5b050455c 100644 --- a/include/common/aarch64/asm_macros.S +++ b/include/common/aarch64/asm_macros.S @@ -10,6 +10,20 @@ #include <asm_macros_common.S> #include <spinlock.h> +/* + * TLBI instruction with type specifier that implements the workaround for + * errata 813419 of Cortex-A57. + */ +#if ERRATA_A57_813419 +#define TLB_INVALIDATE(_type) \ + tlbi _type; \ + dsb ish; \ + tlbi _type +#else +#define TLB_INVALIDATE(_type) \ + tlbi _type +#endif + .macro func_prologue stp x29, x30, [sp, #-0x10]! diff --git a/include/common/ep_info.h b/include/common/ep_info.h index 3c2fe4443..99a03906b 100644 --- a/include/common/ep_info.h +++ b/include/common/ep_info.h @@ -29,33 +29,38 @@ /* The following are used to set/get image attributes. */ #define PARAM_EP_SECURITY_MASK U(0x1) +/* Secure or Non-secure image */ #define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) #define SET_SECURITY_STATE(x, security) \ ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) -#define EP_EE_MASK U(0x2) -#define EP_EE_SHIFT 1 -#define EP_EE_LITTLE U(0x0) -#define EP_EE_BIG U(0x2) -#define EP_GET_EE(x) (x & EP_EE_MASK) -#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) - -#define EP_ST_MASK U(0x4) -#define EP_ST_DISABLE U(0x0) -#define EP_ST_ENABLE U(0x4) -#define EP_GET_ST(x) (x & EP_ST_MASK) -#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) - -#define EP_EXE_MASK U(0x8) -#define NON_EXECUTABLE U(0x0) -#define EXECUTABLE U(0x8) -#define EP_GET_EXE(x) (x & EP_EXE_MASK) -#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) - +/* Endianness of the image. */ +#define EP_EE_MASK U(0x2) +#define EP_EE_SHIFT U(1) +#define EP_EE_LITTLE U(0x0) +#define EP_EE_BIG U(0x2) +#define EP_GET_EE(x) ((x) & EP_EE_MASK) +#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) + +/* Enable or disable access to the secure timer from secure images. */ +#define EP_ST_MASK U(0x4) +#define EP_ST_DISABLE U(0x0) +#define EP_ST_ENABLE U(0x4) +#define EP_GET_ST(x) ((x) & EP_ST_MASK) +#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) + +/* Determine if an image is executable or not. */ +#define EP_EXE_MASK U(0x8) +#define NON_EXECUTABLE U(0x0) +#define EXECUTABLE U(0x8) +#define EP_GET_EXE(x) ((x) & EP_EXE_MASK) +#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) + +/* Flag to indicate the first image that is executed. */ #define EP_FIRST_EXE_MASK U(0x10) #define EP_FIRST_EXE U(0x10) -#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) -#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) +#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) +#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) #ifndef __ASSEMBLY__ diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index 910341a72..a940b63b5 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -340,7 +340,7 @@ /* * TTBR definitions */ -#define TTBR_CNP_BIT 0x1 +#define TTBR_CNP_BIT U(0x1) /* * CTR definitions diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 7335103b1..1bdf3c4b0 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -127,8 +127,8 @@ * expected. */ #define ARM_ARCH_AT_LEAST(_maj, _min) \ - ((ARM_ARCH_MAJOR > _maj) || \ - ((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min))) + ((ARM_ARCH_MAJOR > (_maj)) || \ + ((ARM_ARCH_MAJOR == (_maj)) && (ARM_ARCH_MINOR >= (_min)))) /* * Import an assembly or linker symbol as a C expression with the specified diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h index 779531770..b6c53e267 100644 --- a/include/lib/xlat_tables/xlat_mmu_helpers.h +++ b/include/lib/xlat_tables/xlat_mmu_helpers.h @@ -48,10 +48,15 @@ #ifdef AARCH32 /* AArch32 specific translation table API */ void enable_mmu_secure(unsigned int flags); + +void enable_mmu_direct(unsigned int flags); #else /* AArch64 specific translation table APIs */ void enable_mmu_el1(unsigned int flags); void enable_mmu_el3(unsigned int flags); + +void enable_mmu_direct_el1(unsigned int flags); +void enable_mmu_direct_el3(unsigned int flags); #endif /* AARCH32 */ int xlat_arch_is_granule_size_supported(size_t size); diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 98f00d715..4dc2c5ec7 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,12 +8,12 @@ #define __XLAT_TABLES_V2_H__ #include <xlat_tables_defs.h> +#include <xlat_tables_v2_helpers.h> #ifndef __ASSEMBLY__ #include <stddef.h> #include <stdint.h> #include <xlat_mmu_helpers.h> -#include <xlat_tables_v2_helpers.h> /* * Default granularity size for an mmap_region_t. diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h index de1c2d4bf..e1ea2b64f 100644 --- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h +++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,13 @@ #error "Do not include this header file directly. Include xlat_tables_v2.h instead." #endif +/* Offsets into mmu_cfg_params array. All parameters are 32 bits wide. */ +#define MMU_CFG_MAIR0 0 +#define MMU_CFG_TCR 1 +#define MMU_CFG_TTBR0_LO 2 +#define MMU_CFG_TTBR0_HI 3 +#define MMU_CFG_PARAM_MAX 4 + #ifndef __ASSEMBLY__ #include <cassert.h> @@ -24,6 +31,9 @@ #include <xlat_tables_arch.h> #include <xlat_tables_defs.h> +/* Parameters of register values required when enabling MMU */ +extern uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; + /* Forward declaration */ struct mmap_region; @@ -162,6 +172,8 @@ struct xlat_ctx { .initialized = 0, \ } +#endif /*__ASSEMBLY__*/ + #if AARCH64 /* @@ -187,6 +199,4 @@ struct xlat_ctx { #endif /* AARCH64 */ -#endif /*__ASSEMBLY__*/ - #endif /* __XLAT_TABLES_V2_HELPERS_H__ */ diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c index 720d4461d..dd639397a 100644 --- a/lib/xlat_tables/aarch32/xlat_tables.c +++ b/lib/xlat_tables/aarch32/xlat_tables.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -130,3 +130,8 @@ void enable_mmu_secure(unsigned int flags) /* Ensure the MMU enable takes effect immediately */ isb(); } + +void enable_mmu_direct(unsigned int flags) +{ + enable_mmu_secure(flags); +} diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c index a72c6454c..5717516a4 100644 --- a/lib/xlat_tables/aarch64/xlat_tables.c +++ b/lib/xlat_tables/aarch64/xlat_tables.c @@ -181,6 +181,11 @@ void init_xlat_tables(void) \ /* Ensure the MMU enable takes effect immediately */ \ isb(); \ + } \ + \ + void enable_mmu_direct_el##_el(unsigned int flags) \ + { \ + enable_mmu_el##_el(flags); \ } /* Define EL1 and EL3 variants of the function enabling the MMU */ diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h index 50d6bd59c..810c48e1a 100644 --- a/lib/xlat_tables/xlat_tables_private.h +++ b/lib/xlat_tables/xlat_tables_private.h @@ -11,6 +11,10 @@ #include <platform_def.h> #include <xlat_tables_arch.h> +#if HW_ASSISTED_COHERENCY +#error xlat tables v2 must be used with HW_ASSISTED_COHERENCY +#endif + /* * If the platform hasn't defined a physical and a virtual address space size * default to ADDR_SPACE_SIZE. diff --git a/lib/xlat_tables_v2/aarch32/enable_mmu.S b/lib/xlat_tables_v2/aarch32/enable_mmu.S new file mode 100644 index 000000000..97cdde751 --- /dev/null +++ b/lib/xlat_tables_v2/aarch32/enable_mmu.S @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <assert_macros.S> +#include <xlat_tables_v2.h> + + .global enable_mmu_direct + +func enable_mmu_direct + /* Assert that MMU is turned off */ +#if ENABLE_ASSERTIONS + ldcopr r1, SCTLR + tst r1, #SCTLR_M_BIT + ASM_ASSERT(eq) +#endif + + /* Invalidate TLB entries */ + TLB_INVALIDATE(r0, TLBIALL) + + mov r3, r0 + ldr r0, =mmu_cfg_params + + /* MAIR0 */ + ldr r1, [r0, #(MMU_CFG_MAIR0 << 2)] + stcopr r1, MAIR0 + + /* TTBCR */ + ldr r2, [r0, #(MMU_CFG_TCR << 2)] + stcopr r2, TTBCR + + /* TTBR0 */ + ldr r1, [r0, #(MMU_CFG_TTBR0_LO << 2)] + ldr r2, [r0, #(MMU_CFG_TTBR0_HI << 2)] + stcopr16 r1, r2, TTBR0_64 + + /* TTBR1 is unused right now; set it to 0. */ + mov r1, #0 + mov r2, #0 + stcopr16 r1, r2, TTBR1_64 + + /* + * Ensure all translation table writes have drained into memory, the TLB + * invalidation is complete, and translation register writes are + * committed before enabling the MMU + */ + dsb ish + isb + + /* Enable enable MMU by honoring flags */ + ldcopr r1, SCTLR + ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT) + orr r1, r1, r2 + + /* Clear C bit if requested */ + tst r3, #DISABLE_DCACHE + bicne r1, r1, #SCTLR_C_BIT + + stcopr r1, SCTLR + isb + + bx lr +endfunc enable_mmu_direct diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c index f66f802f3..94dcf578a 100644 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,8 @@ #error ARMv7 target does not support LPAE MMU descriptors #endif +uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; + /* * Returns 1 if the provided granule size is supported, 0 otherwise. */ @@ -109,22 +111,16 @@ int xlat_arch_current_el(void) * Function for enabling the MMU in Secure PL1, assuming that the page tables * have already been created. ******************************************************************************/ -void enable_mmu_arch(unsigned int flags, - uint64_t *base_table, +void setup_mmu_cfg(unsigned int flags, + const uint64_t *base_table, unsigned long long max_pa, uintptr_t max_va) { - u_register_t mair0, ttbcr, sctlr; + u_register_t mair0, ttbcr; uint64_t ttbr0; assert(IS_IN_SECURE()); - sctlr = read_sctlr(); - assert((sctlr & SCTLR_M_BIT) == 0); - - /* Invalidate TLBs at the current exception level */ - tlbiall(); - /* Set attributes in the right indices of the MAIR */ mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, @@ -185,30 +181,9 @@ void enable_mmu_arch(unsigned int flags, ttbr0 |= TTBR_CNP_BIT; #endif - /* Now program the relevant system registers */ - write_mair0(mair0); - write_ttbcr(ttbcr); - write64_ttbr0(ttbr0); - write64_ttbr1(0); - - /* - * Ensure all translation table writes have drained - * into memory, the TLB invalidation is complete, - * and translation register writes are committed - * before enabling the MMU - */ - dsbish(); - isb(); - - sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; - - if (flags & DISABLE_DCACHE) - sctlr &= ~SCTLR_C_BIT; - else - sctlr |= SCTLR_C_BIT; - - write_sctlr(sctlr); - - /* Ensure the MMU enable takes effect immediately */ - isb(); + /* Now populate MMU configuration */ + mmu_cfg_params[MMU_CFG_MAIR0] = mair0; + mmu_cfg_params[MMU_CFG_TCR] = ttbcr; + mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr0; + mmu_cfg_params[MMU_CFG_TTBR0_HI] = ttbr0 >> 32; } diff --git a/lib/xlat_tables_v2/aarch64/enable_mmu.S b/lib/xlat_tables_v2/aarch64/enable_mmu.S new file mode 100644 index 000000000..a72c7fae5 --- /dev/null +++ b/lib/xlat_tables_v2/aarch64/enable_mmu.S @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <assert_macros.S> +#include <xlat_tables_v2.h> + + .global enable_mmu_direct_el1 + .global enable_mmu_direct_el3 + + /* Macros to read and write to system register for a given EL. */ + .macro _msr reg_name, el, gp_reg + msr \reg_name\()_el\()\el, \gp_reg + .endm + + .macro _mrs gp_reg, reg_name, el + mrs \gp_reg, \reg_name\()_el\()\el + .endm + + .macro define_mmu_enable_func el + func enable_mmu_direct_\()el\el +#if ENABLE_ASSERTIONS + _mrs x1, sctlr, \el + tst x1, #SCTLR_M_BIT + ASM_ASSERT(eq) +#endif + + /* Invalidate TLB entries */ + .if \el == 1 + TLB_INVALIDATE(vmalle1) + .else + .if \el == 3 + TLB_INVALIDATE(alle3) + .else + .error "EL must be 1 or 3" + .endif + .endif + + mov x7, x0 + ldr x0, =mmu_cfg_params + + /* MAIR */ + ldr w1, [x0, #(MMU_CFG_MAIR0 << 2)] + _msr mair, \el, x1 + + /* TCR */ + ldr w2, [x0, #(MMU_CFG_TCR << 2)] + _msr tcr, \el, x2 + + /* TTBR */ + ldr w3, [x0, #(MMU_CFG_TTBR0_LO << 2)] + ldr w4, [x0, #(MMU_CFG_TTBR0_HI << 2)] + orr x3, x3, x4, lsl #32 + _msr ttbr0, \el, x3 + + /* + * Ensure all translation table writes have drained into memory, the TLB + * invalidation is complete, and translation register writes are + * committed before enabling the MMU + */ + dsb ish + isb + + /* Set and clear required fields of SCTLR */ + _mrs x4, sctlr, \el + mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT + orr x4, x4, x5 + + /* Additionally, amend SCTLR fields based on flags */ + bic x5, x4, #SCTLR_C_BIT + tst x7, #DISABLE_DCACHE + csel x4, x5, x4, ne + + _msr sctlr, \el, x4 + isb + + ret + endfunc enable_mmu_direct_\()el\el + .endm + + /* + * Define MMU-enabling functions for EL1 and EL3: + * + * enable_mmu_direct_el1 + * enable_mmu_direct_el3 + */ + define_mmu_enable_func 1 + define_mmu_enable_func 3 diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index c501e7074..71b9c8fae 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -16,6 +16,8 @@ #include <xlat_tables_v2.h> #include "../xlat_tables_private.h" +uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; + /* * Returns 1 if the provided granule size is supported, 0 otherwise. */ @@ -183,70 +185,13 @@ int xlat_arch_current_el(void) return el; } -/******************************************************************************* - * Macro generating the code for the function enabling the MMU in the given - * exception level, assuming that the pagetables have already been created. - * - * _el: Exception level at which the function will run - * _tlbi_fct: Function to invalidate the TLBs at the current - * exception level - ******************************************************************************/ -#define DEFINE_ENABLE_MMU_EL(_el, _tlbi_fct) \ - static void enable_mmu_internal_el##_el(int flags, \ - uint64_t mair, \ - uint64_t tcr, \ - uint64_t ttbr) \ - { \ - uint32_t sctlr = read_sctlr_el##_el(); \ - assert((sctlr & SCTLR_M_BIT) == 0); \ - \ - /* Invalidate TLBs at the current exception level */ \ - _tlbi_fct(); \ - \ - write_mair_el##_el(mair); \ - write_tcr_el##_el(tcr); \ - \ - /* Set TTBR bits as well */ \ - if (ARM_ARCH_AT_LEAST(8, 2)) { \ - /* Enable CnP bit so as to share page tables */ \ - /* with all PEs. This is mandatory for */ \ - /* ARMv8.2 implementations. */ \ - ttbr |= TTBR_CNP_BIT; \ - } \ - write_ttbr0_el##_el(ttbr); \ - \ - /* Ensure all translation table writes have drained */ \ - /* into memory, the TLB invalidation is complete, */ \ - /* and translation register writes are committed */ \ - /* before enabling the MMU */ \ - dsbish(); \ - isb(); \ - \ - sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ - if (flags & DISABLE_DCACHE) \ - sctlr &= ~SCTLR_C_BIT; \ - else \ - sctlr |= SCTLR_C_BIT; \ - \ - write_sctlr_el##_el(sctlr); \ - \ - /* Ensure the MMU enable takes effect immediately */ \ - isb(); \ - } - -/* Define EL1 and EL3 variants of the function enabling the MMU */ -#if IMAGE_EL == 1 -DEFINE_ENABLE_MMU_EL(1, tlbivmalle1) -#elif IMAGE_EL == 3 -DEFINE_ENABLE_MMU_EL(3, tlbialle3) -#endif - -void enable_mmu_arch(unsigned int flags, - uint64_t *base_table, +void setup_mmu_cfg(unsigned int flags, + const uint64_t *base_table, unsigned long long max_pa, uintptr_t max_va) { uint64_t mair, ttbr, tcr; + uintptr_t virtual_addr_space_size; /* Set attributes in the right indices of the MAIR. */ mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); @@ -256,27 +201,25 @@ void enable_mmu_arch(unsigned int flags, ttbr = (uint64_t) base_table; /* - * Set TCR bits as well. - */ - - /* * Limit the input address ranges and memory region sizes translated * using TTBR0 to the given virtual address space size. */ - assert(max_va < UINTPTR_MAX); - uintptr_t virtual_addr_space_size = max_va + 1; + assert(max_va < ((uint64_t) UINTPTR_MAX)); + + virtual_addr_space_size = max_va + 1; assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); + /* * __builtin_ctzll(0) is undefined but here we are guaranteed that * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. */ - tcr = 64 - __builtin_ctzll(virtual_addr_space_size); + tcr = (uint64_t) 64 - __builtin_ctzll(virtual_addr_space_size); /* * Set the cacheability and shareability attributes for memory * associated with translation table walks. */ - if (flags & XLAT_TABLE_NC) { + if ((flags & XLAT_TABLE_NC) != 0) { /* Inner & outer non-cacheable non-shareable. */ tcr |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; @@ -299,10 +242,23 @@ void enable_mmu_arch(unsigned int flags, * translated using TTBR1_EL1. */ tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); - enable_mmu_internal_el1(flags, mair, tcr, ttbr); #elif IMAGE_EL == 3 assert(IS_IN_EL(3)); tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); - enable_mmu_internal_el3(flags, mair, tcr, ttbr); #endif + + mmu_cfg_params[MMU_CFG_MAIR0] = (uint32_t) mair; + mmu_cfg_params[MMU_CFG_TCR] = (uint32_t) tcr; + + /* Set TTBR bits as well */ + if (ARM_ARCH_AT_LEAST(8, 2)) { + /* + * Enable CnP bit so as to share page tables with all PEs. This + * is mandatory for ARMv8.2 implementations. + */ + ttbr |= TTBR_CNP_BIT; + } + + mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr; + mmu_cfg_params[MMU_CFG_TTBR0_HI] = (uint32_t) (ttbr >> 32); } diff --git a/lib/xlat_tables_v2/xlat_tables.mk b/lib/xlat_tables_v2/xlat_tables.mk index 06dd844a2..1e70f37f7 100644 --- a/lib/xlat_tables_v2/xlat_tables.mk +++ b/lib/xlat_tables_v2/xlat_tables.mk @@ -1,10 +1,11 @@ # -# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # XLAT_TABLES_LIB_SRCS := $(addprefix lib/xlat_tables_v2/, \ + ${ARCH}/enable_mmu.S \ ${ARCH}/xlat_tables_arch.c \ xlat_tables_internal.c) diff --git a/lib/xlat_tables_v2/xlat_tables_internal.c b/lib/xlat_tables_v2/xlat_tables_internal.c index 5beb51e90..7f1d3958a 100644 --- a/lib/xlat_tables_v2/xlat_tables_internal.c +++ b/lib/xlat_tables_v2/xlat_tables_internal.c @@ -802,7 +802,7 @@ void mmap_add_region_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm) * that there is free space. */ assert(mm_last->size == 0U); - + /* Make room for new region by moving other regions up by one place */ mm_destination = mm_cursor + 1; memmove(mm_destination, mm_cursor, @@ -1313,22 +1313,25 @@ void init_xlat_tables(void) void enable_mmu_secure(unsigned int flags) { - enable_mmu_arch(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, + setup_mmu_cfg(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, tf_xlat_ctx.va_max_address); + enable_mmu_direct(flags); } #else void enable_mmu_el1(unsigned int flags) { - enable_mmu_arch(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, + setup_mmu_cfg(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, tf_xlat_ctx.va_max_address); + enable_mmu_direct_el1(flags); } void enable_mmu_el3(unsigned int flags) { - enable_mmu_arch(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, + setup_mmu_cfg(flags, tf_xlat_ctx.base_table, MAX_PHYS_ADDR, tf_xlat_ctx.va_max_address); + enable_mmu_direct_el3(flags); } #endif /* AARCH32 */ diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h index 157dd0396..777189fb0 100644 --- a/lib/xlat_tables_v2/xlat_tables_private.h +++ b/lib/xlat_tables_v2/xlat_tables_private.h @@ -81,7 +81,7 @@ int xlat_arch_current_el(void); unsigned long long xlat_arch_get_max_supported_pa(void); /* Enable MMU and configure it to use the specified translation tables. */ -void enable_mmu_arch(unsigned int flags, uint64_t *base_table, +void setup_mmu_cfg(unsigned int flags, const uint64_t *base_table, unsigned long long max_pa, uintptr_t max_va); /* diff --git a/maintainers.rst b/maintainers.rst index 2dd20acac..94bb5d318 100644 --- a/maintainers.rst +++ b/maintainers.rst @@ -7,190 +7,168 @@ parts of the codebase is delegated to the sub-maintainers listed below. An acknowledgement from these sub-maintainers may be required before the maintainers merge a contribution. -Maintainers ------------ - -Dan Handley (dan.handley@arm.com, `danh-arm`_) - -David Cunado (david.cunado@arm.com, `davidcunado-arm`_) - -OPTEE and QEMU platform sub-maintainer --------------------------------------- - -Jens Wiklander (jens.wiklander@linaro.org, `jenswi-linaro`_) - -Files: - -- docs/plat/qemu.rst -- docs/spd/optee-dispatcher.rst -- services/spd/opteed/\* -- plat/qemu/\* - -TLK/Trusty SPDs and NVidia platforms sub-maintainer ---------------------------------------------------- - -Varun Wadekar (vwadekar@nvidia.com, `vwadekar`_) - -Files: - -- docs/plat/nvidia-tegra.rst -- docs/spd/tlk-dispatcher.rst -- docs/spd/trusty-dispatcher.rst -- include/bl32/payloads/tlk.h -- include/lib/cpus/aarch64/denver.h -- lib/cpus/aarch64/denver.S -- services/spd/tlkd/\* -- services/spd/trusty/\* -- plat/nvidia/\* - -eMMC/UFS drivers and HiSilicon HiKey and HiKey960 platform sub-maintainer -------------------------------------------------------------------------- - -Haojian Zhuang (haojian.zhuang@linaro.org, `hzhuang1`_) - -Files: - -- docs/plat/hikey.rst -- docs/plat/hikey960.rst -- drivers/emmc/\* -- drivers/partition/\* -- drivers/synopsys/emmc/\* -- drivers/synopsys/ufs/\* -- drivers/ufs/\* -- include/drivers/dw\_ufs.h -- include/drivers/emmc.h -- include/drivers/ufs.h -- include/drivers/synopsys/dw\_mmc.h -- plat/hisilicon/hikey/\* -- plat/hisilicon/hikey960/\* - -Allwinner ARMv8 platform sub-maintainer ---------------------------------------- - -Andre Przywara (andre.przywara@arm.com, `Andre-ARM`_) - -Files: - -- docs/plat/allwinner.rst -- plat/allwinner/\* - -HiSilicon Poplar platform sub-maintainer ----------------------------------------- - -Shawn Guo (shawn.guo@linaro.org, `shawnguo2`_) - -Files: - -- docs/plat/poplar.rst -- plat/hisilicon/poplar/\* - -MediaTek platform sub-maintainer --------------------------------- - -Yidi Lin (林以廸 yidi.lin@mediatek.com, `mtk09422`_) - -Files: - -- plat/mediatek/\* - -NXP QorIQ Layerscape platform sub-maintainer --------------------------------------- -Jiafei Pan (jiafei.pan@nxp.com, `qoriq-open-source`_) - -Files: - -- docs/plat/ls1043a.rst -- plat/layerscape/\* - -NXP i.MX 8 platform sub-maintainer --------------------------------------- - -Anson Huang (Anson.Huang@nxp.com, `Anson-Huang`_) - -Files: - -- docs/plat/imx8.rst -- plat/imx/\* - -Raspberry Pi 3 platform sub-maintainer --------------------------------------- - -Antonio Niño Díaz (antonio.ninodiaz@arm.com, `antonio-nino-diaz-arm`_) - -Files: - -- docs/plat/rpi3.rst -- plat/rpi3/\* - -RockChip platform sub-maintainer --------------------------------- - -Tony Xie (tony.xie@rock-chips.com, `TonyXie06`_ -or `rockchip-linux`_) - -Files: - -- plat/rockchip/\* - -Synquacer platform sub-maintainer ---------------------------------- - -Sumit Garg (sumit.garg@linaro.org, `b49020`_) - -Files: - -- docs/plat/synquacer.rst -- plat/socionext/synquacer/\* - -Texas Instruments platform sub-maintainer ------------------------------------------ - -Andrew F. Davis (afd@ti.com, `glneo`_) - -Files: - -- docs/plat/ti-k3.rst -- plat/ti/\* - -UniPhier platform sub-maintainer --------------------------------- - -Masahiro Yamada (yamada.masahiro@socionext.com, `masahir0y`_) - -Files: - -- docs/plat/socionext-uniphier.rst -- plat/socionext/uniphier/\* - -Xilinx platform sub-maintainer +Main maintainers +---------------- +:M: Dan Handley <dan.handley@arm.com> +:G: `danh-arm`_ +:M: Dimitris Papastamos <dimitrs.papastamos@arm.com> +:G: `dp-arm`_ +:M: Soby Mathew <soby.mathew@arm.com> +:G: `soby-mathew`_ + +Allwinner ARMv8 platform port +----------------------------- +:M: Andre Przywara <andre.przywara@arm.com> +:G: `Andre-ARM`_ +:F: docs/plat/allwinner.rst +:F: plat/allwinner/ + +Armv7-A architecture port +------------------------- +:M: Etienne Carriere <etienne.carriere@linaro.org> +:G: `etienne-lms`_ + +eMMC/UFS drivers +---------------- +:M: Haojian Zhuang <haojian.zhuang@linaro.org> +:G: `hzhuang1`_ +:F: drivers/emmc/ +:F: drivers/partition/ +:F: drivers/synopsys/emmc/ +:F: drivers/synopsys/ufs/ +:F: drivers/ufs/ +:F: include/drivers/dw_ufs.h +:F: include/drivers/emmc.h +:F: include/drivers/ufs.h +:F: include/drivers/synopsys/dw_mmc.h + +HiSilicon HiKey and HiKey960 platform ports +------------------------------------------- +:M: Haojian Zhuang <haojian.zhuang@linaro.org> +:G: `hzhuang1`_ +:F: docs/plat/hikey.rst +:F: docs/plat/hikey960.rst +:F: plat/hisilicon/hikey/ +:F: plat/hisilicon/hikey960/ + +HiSilicon Poplar platform port ------------------------------ - -Siva Durga Prasad Paladugu (siva.durga.paladugu@xilinx.com, `sivadur`_) - -Files: - -- docs/plat/xilinx-zynqmp.rst -- plat/xilinx/\* - -Armv7-A architecture sub-maintainer +:M: Shawn Guo <shawn.guo@linaro.org> +:G: `shawnguo2`_ +:F: docs/plat/poplar.rst +:F: plat/hisilicon/poplar/ + +MediaTek platform ports +----------------------- +:M: Yidi Lin (林以廸) <yidi.lin@mediatek.com> +:G: `mtk09422`_ +:F: plat/mediatek/ + +NVidia platform ports +--------------------- +:M: Varun Wadekar <vwadekar@nvidia.com> +:G: `vwadekar`_ +:F: docs/plat/nvidia-tegra.rst +:F: include/lib/cpus/aarch64/denver.h +:F: lib/cpus/aarch64/denver.S +:F: plat/nvidia/ + +NXP QorIQ Layerscape platform ports ----------------------------------- +:M: Jiafei Pan <jiafei.pan@nxp.com> +:G: `qoriq-open-source`_ +:F: docs/plat/ls1043a.rst +:F: plat/layerscape/ + +NXP i.MX 8 platform port +------------------------ +:M: Anson Huang <Anson.Huang@nxp.com> +:G: `Anson-Huang`_ +:F: docs/plat/imx8.rst +:F: plat/imx/ + +OP-TEE dispatcher +----------------- +:M: Jens Wiklander <jens.wiklander@linaro.org> +:G: `jenswi-linaro`_ +:F: docs/spd/optee-dispatcher.rst +:F: services/spd/opteed/ + +QEMU platform port +------------------ +:M: Jens Wiklander <jens.wiklander@linaro.org> +:G: `jenswi-linaro`_ +:F: docs/plat/qemu.rst +:F: plat/qemu/ + +Raspberry Pi 3 platform port +---------------------------- +:M: Antonio Niño Díaz <antonio.ninodiaz@arm.com> +:G: `antonio-nino-diaz-arm`_ +:F: docs/plat/rpi3.rst +:F: plat/rpi3/ + +RockChip platform port +---------------------- +:M: Tony Xie <tony.xie@rock-chips.com> +:G: `TonyXie06`_ +:G: `rockchip-linux`_ +:F: plat/rockchip/ + +Synquacer platform port +----------------------- +:M: Sumit Garg <sumit.garg@linaro.org> +:G: `b49020`_ +:F: docs/plat/synquacer.rst +:F: plat/socionext/synquacer/ + +Texas Instruments platform port +------------------------------- +:M: Andrew F. Davis <afd@ti.com> +:G: `glneo`_ +:F: docs/plat/ti-k3.rst +:F: plat/ti/ + +TLK/Trusty secure payloads +-------------------------- +:M: Varun Wadekar <vwadekar@nvidia.com> +:G: `vwadekar`_ +:F: docs/spd/tlk-dispatcher.rst +:F: docs/spd/trusty-dispatcher.rst +:F: include/bl32/payloads/tlk.h +:F: services/spd/tlkd/ +:F: services/spd/trusty/ + +UniPhier platform port +---------------------- +:M: Masahiro Yamada <yamada.masahiro@socionext.com> +:G: `masahir0y`_ +:F: docs/plat/socionext-uniphier.rst +:F: plat/socionext/uniphier/ + +Xilinx platform port +-------------------- +:M: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> +:G: `sivadur`_ +:F: docs/plat/xilinx-zynqmp.rst +:F: plat/xilinx/ -Etienne Carriere (etienne.carriere@linaro.org, `etienne-lms`_) - +.. _Andre-ARM: https://github.com/Andre-ARM +.. _Anson-Huang: https://github.com/Anson-Huang .. _antonio-nino-diaz-arm: https://github.com/antonio-nino-diaz-arm +.. _b49020: https://github.com/b49020 .. _danh-arm: https://github.com/danh-arm -.. _davidcunado-arm: https://github.com/davidcunado-arm -.. _jenswi-linaro: https://github.com/jenswi-linaro -.. _vwadekar: https://github.com/vwadekar +.. _dp-arm: https://github.com/dp-arm +.. _etienne-lms: https://github.com/etienne-lms +.. _glneo: https://github.com/glneo .. _hzhuang1: https://github.com/hzhuang1 -.. _shawnguo2: https://github.com/shawnguo2 +.. _jenswi-linaro: https://github.com/jenswi-linaro .. _masahir0y: https://github.com/masahir0y .. _mtk09422: https://github.com/mtk09422 -.. _TonyXie06: https://github.com/TonyXie06 -.. _glneo: https://github.com/glneo -.. _sivadur: https://github.com/sivadur -.. _rockchip-linux: https://github.com/rockchip-linux -.. _etienne-lms: https://github.com/etienne-lms .. _qoriq-open-source: https://github.com/qoriq-open-source -.. _Andre-ARM: https://github.com/Andre-ARM -.. _b49020: https://github.com/b49020 +.. _rockchip-linux: https://github.com/rockchip-linux +.. _shawnguo2: https://github.com/shawnguo2 +.. _sivadur: https://github.com/sivadur +.. _soby-mathew: https://github.com/soby-mathew +.. _TonyXie06: https://github.com/TonyXie06 +.. _vwadekar: https://github.com/vwadekar diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index e5e730417..d141f647e 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -118,6 +118,12 @@ void arm_bl1_platform_setup(void) #if LOAD_IMAGE_V2 arm_load_tb_fw_config(); #endif + /* + * Allow access to the System counter timer module and program + * counter frequency for non secure images during FWU + */ + arm_configure_sys_timer(); + write_cntfrq_el0(plat_get_syscnt_freq2()); } void bl1_platform_setup(void) diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index 409ae55a2..5f2972cc4 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -18,8 +18,6 @@ * provide typical implementations that may be re-used by multiple * platforms but may also be overridden by a platform if required. */ -#pragma weak bl31_plat_enable_mmu -#pragma weak bl32_plat_enable_mmu #pragma weak bl31_plat_runtime_setup #if !ERROR_DEPRECATED #pragma weak plat_get_syscnt_freq2 @@ -33,16 +31,6 @@ #pragma weak plat_ea_handler -void bl31_plat_enable_mmu(uint32_t flags) -{ - enable_mmu_el3(flags); -} - -void bl32_plat_enable_mmu(uint32_t flags) -{ - enable_mmu_el1(flags); -} - void bl31_plat_runtime_setup(void) { #if MULTI_CONSOLE_API diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S index 033a12f8e..a413f5fd1 100644 --- a/plat/common/aarch64/platform_helpers.S +++ b/plat/common/aarch64/platform_helpers.S @@ -17,6 +17,8 @@ .weak plat_disable_acp .weak bl1_plat_prepare_exit .weak plat_panic_handler + .weak bl31_plat_enable_mmu + .weak bl32_plat_enable_mmu #if !ENABLE_PLAT_COMPAT .globl platform_get_core_pos @@ -164,3 +166,23 @@ func plat_panic_handler wfi b plat_panic_handler endfunc plat_panic_handler + + /* ----------------------------------------------------- + * void bl31_plat_enable_mmu(uint32_t flags); + * + * Enable MMU in BL31. + * ----------------------------------------------------- + */ +func bl31_plat_enable_mmu + b enable_mmu_direct_el3 +endfunc bl31_plat_enable_mmu + + /* ----------------------------------------------------- + * void bl32_plat_enable_mmu(uint32_t flags); + * + * Enable MMU in BL32. + * ----------------------------------------------------- + */ +func bl32_plat_enable_mmu + b enable_mmu_direct_el1 +endfunc bl32_plat_enable_mmu diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index 91602c8c1..4d6428b5c 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -17,12 +17,18 @@ uintptr_t k3_sec_entrypoint; static void k3_cpu_standby(plat_local_state_t cpu_state) { - /* - * Enter standby state - * dsb is good practice before using wfi to enter low power states - */ + unsigned int scr; + + scr = read_scr_el3(); + /* Enable the Non secure interrupt to wake the CPU */ + write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); + isb(); + /* dsb is good practice before using wfi to enter low power states */ dsb(); + /* Enter standby state */ wfi(); + /* Restore SCR */ + write_scr_el3(scr); } static int k3_pwr_domain_on(u_register_t mpidr) diff --git a/plat/ti/k3/common/k3_topology.c b/plat/ti/k3/common/k3_topology.c index a77c8f34c..d7ac0a589 100644 --- a/plat/ti/k3/common/k3_topology.c +++ b/plat/ti/k3/common/k3_topology.c @@ -9,6 +9,7 @@ /* The power domain tree descriptor */ static unsigned char power_domain_tree_desc[] = { + PLATFORM_SYSTEM_COUNT, PLATFORM_CLUSTER_COUNT, K3_CLUSTER0_CORE_COUNT, #if K3_CLUSTER1_MSMC_PORT != UNUSED diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h index 8856af2ca..ebc9c4770 100644 --- a/plat/ti/k3/include/platform_def.h +++ b/plat/ti/k3/include/platform_def.h @@ -62,9 +62,10 @@ #define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 /******************************************************************************* * Memory layout constants |