diff options
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 3 | ||||
| -rw-r--r-- | docs/getting_started/user-guide.rst | 6 | ||||
| -rw-r--r-- | docs/maintainers.rst | 23 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 3 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 4 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 37 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 | ||||
| -rw-r--r-- | lib/psci/psci_common.c | 36 | ||||
| -rw-r--r-- | lib/psci/psci_off.c | 14 | ||||
| -rw-r--r-- | lib/psci/psci_private.h | 6 | ||||
| -rw-r--r-- | lib/psci/psci_suspend.c | 21 | ||||
| -rw-r--r-- | plat/arm/common/sp_min/arm_sp_min.mk | 6 | ||||
| -rw-r--r-- | plat/ti/k3/common/k3_psci.c | 18 | ||||
| -rw-r--r-- | plat/ti/k3/common/plat_common.mk | 8 | ||||
| -rw-r--r-- | readme.rst | 2 |
15 files changed, 126 insertions, 69 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 07983a901..6b524c24c 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -226,6 +226,9 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + DSU Errata Workarounds ---------------------- diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 1a4df03d4..02f8c5faa 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -401,6 +401,8 @@ Common build options for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this flag has to be enabled. 0 is the default. +- ``E``: Boolean option to make warnings into errors. Default is 1. + - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of the normal boot flow. It must specify the entry point address of the EL3 payload. Please refer to the "Booting an EL3 payload" section for more @@ -785,6 +787,10 @@ Common build options Defaults to a string formed by concatenating the version number, build type and build string. +- ``W``: Warning level. Some compiler warning options of interest have been + regrouped and put in the root Makefile. This flag can take the values 0 to 3, + each level enabling more warning options. Default is 0. + - ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on the CPU after warm boot. This is applicable for platforms which do not require interconnect programming to enable cache coherency (eg: single diff --git a/docs/maintainers.rst b/docs/maintainers.rst index 5449faa20..098fc5f5b 100644 --- a/docs/maintainers.rst +++ b/docs/maintainers.rst @@ -11,10 +11,16 @@ Main maintainers ---------------- :M: Dan Handley <dan.handley@arm.com> :G: `danh-arm`_ -:M: Dimitris Papastamos <dimitrs.papastamos@arm.com> -:G: `dp-arm`_ :M: Soby Mathew <soby.mathew@arm.com> :G: `soby-mathew`_ +:M: Sandrine Bailleux <sandrine.bailleux@arm.com> +:G: `sandrine-bailleux-arm`_ +:M: Alexei Fedorov <alexei.fedorov@arm.com> +:G: `AlexeiFedorov`_ +:M: Paul Beesley <paul.beesley@arm.com> +:G: `pbeesley-arm`_ +:M: John Tsichritzis <john.tsichritzis@arm.com> +:G: `jts-arm`_ Allwinner ARMv8 platform port ----------------------------- @@ -260,28 +266,33 @@ Xilinx platform port :F: docs/plat/xilinx-zynqmp.rst :F: plat/xilinx/ +.. _AlexeiFedorov: https://github.com/AlexeiFedorov .. _Andre-ARM: https://github.com/Andre-ARM .. _Anson-Huang: https://github.com/Anson-Huang .. _bryanodonoghue: https://github.com/bryanodonoghue .. _b49020: https://github.com/b49020 .. _danh-arm: https://github.com/danh-arm -.. _dp-arm: https://github.com/dp-arm .. _etienne-lms: https://github.com/etienne-lms .. _glneo: https://github.com/glneo +.. _grandpaul: https://github.com/grandpaul .. _hzhuang1: https://github.com/hzhuang1 .. _JackyBai: https://github.com/JackyBai .. _jenswi-linaro: https://github.com/jenswi-linaro +.. _jts-arm: https://github.com/jts-arm +.. _jwerner-chromium: https://github.com/jwerner-chromium +.. _kostapr: https://github.com/kostapr .. _ldts: https://github.com/ldts .. _marex: https://github.com/marex -.. _niej: https://github.com/niej -.. _kostapr: https://github.com/kostapr .. _masahir0y: https://github.com/masahir0y .. _mmind: https://github.com/mmind .. _mtk09422: https://github.com/mtk09422 +.. _niej: https://github.com/niej .. _npoushin: https://github.com/npoushin +.. _pbeesley-arm: https://github.com/pbeesley-arm .. _qoriq-open-source: https://github.com/qoriq-open-source .. _remi-triplefault: https://github.com/repk .. _rockchip-linux: https://github.com/rockchip-linux +.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm .. _shawnguo2: https://github.com/shawnguo2 .. _sivadur: https://github.com/sivadur .. _smaeul: https://github.com/smaeul @@ -290,5 +301,3 @@ Xilinx platform port .. _TonyXie06: https://github.com/TonyXie06 .. _vwadekar: https://github.com/vwadekar .. _Yann-lms: https://github.com/Yann-lms -.. _grandpaul: https://github.com/grandpaul -.. _jwerner-chromium: https://github.com/jwerner-chromium diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index ed5f136dd..b66aeb8a0 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -35,7 +35,8 @@ ******************************************************************************/ #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 6fd3c53fd..b105de26b 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -279,13 +279,11 @@ endfunc cortex_a53_reset_func func cortex_a53_core_pwr_dwn mov x18, x30 -#if !TI_AM65X_WORKAROUND /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache -#endif /* --------------------------------------------- * Flush L1 caches. @@ -305,13 +303,11 @@ endfunc cortex_a53_core_pwr_dwn func cortex_a53_cluster_pwr_dwn mov x18, x30 -#if !TI_AM65X_WORKAROUND /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache -#endif /* --------------------------------------------- * Flush L1 caches. diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index dadaf98b4..d685b7e9b 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -21,7 +21,7 @@ #endif /* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata + * Errata Workaround for Neoverse N1 Erratum 1043202. * This applies to revision r0p0 and r1p0 of Neoverse N1. * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. @@ -75,6 +75,35 @@ func neoverse_n1_disable_speculative_loads ret endfunc neoverse_n1_disable_speculative_loads +/* -------------------------------------------------- + * Errata Workaround for Neoverse N1 Erratum 1315703. + * This applies to revision <= r3p0 of Neoverse N1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n1_1315703_wa + /* Compare x0 against revision r3p1 */ + mov x17, x30 + bl check_errata_1315703 + cbz x0, 1f + + mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 + orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 + msr NEOVERSE_N1_CPUACTLR2_EL1, x0 + isb + +1: + ret x17 +endfunc errata_n1_1315703_wa + +func check_errata_1315703 + /* Applies to everything <= r3p0. */ + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1315703 + func neoverse_n1_reset_func mov x19, x30 @@ -94,6 +123,11 @@ func neoverse_n1_reset_func bl errata_n1_1043202_wa #endif +#if ERRATA_N1_1315703 + mov x0, x18 + bl errata_n1_1315703_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -146,6 +180,7 @@ func neoverse_n1_errata_report * checking functions of each errata. */ report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 + report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 599e11ed5..db4537528 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -238,6 +238,10 @@ ERRATA_A76_1286807 ?=0 # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=1 +# Flag to apply erratum 1315703 workaround during reset. This erratum applies +# to revisions before r3p1 of the Neoverse N1 cpu. +ERRATA_N1_1315703 ?=1 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -427,6 +431,10 @@ $(eval $(call add_define,ERRATA_A76_1286807)) $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) +# Process ERRATA_N1_1315703 flag +$(eval $(call assert_boolean,ERRATA_N1_1315703)) +$(eval $(call add_define,ERRATA_N1_1315703)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 2928c33e5..3f5e9893b 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -568,35 +568,35 @@ unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info) } /******************************************************************************* - * This function is passed a cpu_index and the highest level in the topology - * tree that the operation should be applied to. It picks up locks in order of - * increasing power domain level in the range specified. + * This function is passed the highest level in the topology tree that the + * operation should be applied to and a list of node indexes. It picks up locks + * from the node index list in order of increasing power domain level in the + * range specified. ******************************************************************************/ -void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx) +void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, + const unsigned int *parent_nodes) { - unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + unsigned int parent_idx; unsigned int level; /* No locking required for level 0. Hence start locking from level 1 */ for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) { + parent_idx = parent_nodes[level - 1U]; psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]); - parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; } } /******************************************************************************* - * This function is passed a cpu_index and the highest level in the topology - * tree that the operation should be applied to. It releases the locks in order - * of decreasing power domain level in the range specified. + * This function is passed the highest level in the topology tree that the + * operation should be applied to and a list of node indexes. It releases the + * locks in order of decreasing power domain level in the range specified. ******************************************************************************/ -void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx) +void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, + const unsigned int *parent_nodes) { - unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0}; + unsigned int parent_idx; unsigned int level; - /* Get the parent nodes */ - psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); - /* Unlock top down. No unlocking required for level 0. */ for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) { parent_idx = parent_nodes[level - 1U]; @@ -764,6 +764,7 @@ void psci_warmboot_entrypoint(void) { unsigned int end_pwrlvl; int cpu_idx = (int) plat_my_core_pos(); + unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; /* @@ -781,12 +782,15 @@ void psci_warmboot_entrypoint(void) */ end_pwrlvl = get_power_on_target_pwrlvl(); + /* Get the parent nodes */ + psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); + /* * This function acquires the lock corresponding to each power level so * that by the time all locks are taken, the system topology is snapshot * and state management can be done safely. */ - psci_acquire_pwr_domain_locks(end_pwrlvl, cpu_idx); + psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); psci_get_target_local_pwr_states(end_pwrlvl, &state_info); @@ -831,7 +835,7 @@ void psci_warmboot_entrypoint(void) * This loop releases the lock corresponding to each power level * in the reverse order to which they were acquired. */ - psci_release_pwr_domain_locks(end_pwrlvl, cpu_idx); + psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); } /******************************************************************************* diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c index ac03e0596..e8cd8feb0 100644 --- a/lib/psci/psci_off.c +++ b/lib/psci/psci_off.c @@ -45,6 +45,7 @@ int psci_do_cpu_off(unsigned int end_pwrlvl) int rc = PSCI_E_SUCCESS; int idx = (int) plat_my_core_pos(); psci_power_state_t state_info; + unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; /* * This function must only be called on platforms where the @@ -56,11 +57,20 @@ int psci_do_cpu_off(unsigned int end_pwrlvl) psci_set_power_off_state(&state_info); /* + * Get the parent nodes here, this is important to do before we + * initiate the power down sequence as after that point the core may + * have exited coherency and its cache may be disabled, any access to + * shared memory after that (such as the parent node lookup in + * psci_cpu_pd_nodes) can cause coherency issues on some platforms. + */ + psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes); + + /* * This function acquires the lock corresponding to each power * level so that by the time all locks are taken, the system topology * is snapshot and state management can be done safely. */ - psci_acquire_pwr_domain_locks(end_pwrlvl, idx); + psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); /* * Call the cpu off handler registered by the Secure Payload Dispatcher @@ -122,7 +132,7 @@ exit: * Release the locks corresponding to each power level in the * reverse order to which they were acquired. */ - psci_release_pwr_domain_locks(end_pwrlvl, idx); + psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); /* * Check if all actions needed to safely power down this cpu have diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index 68ec7fb66..bbcc5cfe7 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h @@ -274,8 +274,10 @@ void psci_get_parent_pwr_domain_nodes(int cpu_idx, unsigned int *node_index); void psci_do_state_coordination(unsigned int end_pwrlvl, psci_power_state_t *state_info); -void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx); -void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx); +void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, + const unsigned int *parent_nodes); +void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, + const unsigned int *parent_nodes); int psci_validate_suspend_req(const psci_power_state_t *state_info, unsigned int is_power_down_state); unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c index 8a752c1a1..6d5c099fb 100644 --- a/lib/psci/psci_suspend.c +++ b/lib/psci/psci_suspend.c @@ -28,10 +28,13 @@ static void psci_suspend_to_standby_finisher(int cpu_idx, unsigned int end_pwrlvl) { + unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; psci_power_state_t state_info; - psci_acquire_pwr_domain_locks(end_pwrlvl, - cpu_idx); + /* Get the parent nodes */ + psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); + + psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); /* * Find out which retention states this CPU has exited from until the @@ -57,8 +60,7 @@ static void psci_suspend_to_standby_finisher(int cpu_idx, */ psci_set_pwr_domains_to_run(end_pwrlvl); - psci_release_pwr_domain_locks(end_pwrlvl, - cpu_idx); + psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); } /******************************************************************************* @@ -156,6 +158,7 @@ void psci_cpu_suspend_start(const entry_point_info_t *ep, { int skip_wfi = 0; int idx = (int) plat_my_core_pos(); + unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; /* * This function must only be called on platforms where the @@ -164,13 +167,15 @@ void psci_cpu_suspend_start(const entry_point_info_t *ep, assert((psci_plat_pm_ops->pwr_domain_suspend != NULL) && (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)); + /* Get the parent nodes */ + psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes); + /* * This function acquires the lock corresponding to each power * level so that by the time all locks are taken, the system topology * is snapshot and state management can be done safely. */ - psci_acquire_pwr_domain_locks(end_pwrlvl, - idx); + psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); /* * We check if there are any pending interrupts after the delay @@ -214,8 +219,8 @@ exit: * Release the locks corresponding to each power level in the * reverse order to which they were acquired. */ - psci_release_pwr_domain_locks(end_pwrlvl, - idx); + psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); + if (skip_wfi == 1) return; diff --git a/plat/arm/common/sp_min/arm_sp_min.mk b/plat/arm/common/sp_min/arm_sp_min.mk index edab8843c..dbd451ce6 100644 --- a/plat/arm/common/sp_min/arm_sp_min.mk +++ b/plat/arm/common/sp_min/arm_sp_min.mk @@ -1,15 +1,16 @@ # -# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # # SP MIN source files common to ARM standard platforms -# Skip building BL1 and BL2 if RESET_TO_SP_MIN flag is set. +# Skip building BL1, BL2 and BL2U if RESET_TO_SP_MIN flag is set. ifeq (${RESET_TO_SP_MIN},1) BL1_SOURCES = BL2_SOURCES = + BL2U_SOURCES = endif BL32_SOURCES += plat/arm/common/arm_pm.c \ @@ -17,4 +18,3 @@ BL32_SOURCES += plat/arm/common/arm_pm.c \ plat/arm/common/sp_min/arm_sp_min_setup.c \ plat/common/aarch32/platform_mp_stack.S \ plat/common/plat_psci_common.c - diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index c7754e994..de9cefe5b 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -17,11 +17,6 @@ #include <k3_gicv3.h> #include <ti_sci.h> -#ifdef TI_AM65X_WORKAROUND -/* Need to flush psci internal locks before shutdown or their values are lost */ -#include "../../../../lib/psci/psci_private.h" -#endif - uintptr_t k3_sec_entrypoint; static void k3_cpu_standby(plat_local_state_t cpu_state) @@ -115,16 +110,6 @@ void k3_pwr_domain_on_finish(const psci_power_state_t *target_state) k3_gic_cpuif_enable(); } -#ifdef TI_AM65X_WORKAROUND -static void __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t - *target_state) -{ - flush_cpu_data(psci_svc_cpu_data); - flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks)); - psci_power_down_wfi(); -} -#endif - static void __dead2 k3_system_reset(void) { /* Send the system reset request to system firmware */ @@ -154,9 +139,6 @@ static const plat_psci_ops_t k3_plat_psci_ops = { .pwr_domain_on = k3_pwr_domain_on, .pwr_domain_off = k3_pwr_domain_off, .pwr_domain_on_finish = k3_pwr_domain_on_finish, -#ifdef TI_AM65X_WORKAROUND - .pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi, -#endif .system_reset = k3_system_reset, .validate_power_state = k3_validate_power_state, .validate_ns_entrypoint = k3_validate_ns_entrypoint diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index 2e5f58453..83e9c62a0 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -12,8 +12,8 @@ COLD_BOOT_SINGLE_CPU := 1 PROGRAMMABLE_RESET_ADDRESS:= 1 # System coherency is managed in hardware -HW_ASSISTED_COHERENCY := 1 -USE_COHERENT_MEM := 0 +WARMBOOT_ENABLE_DCACHE_EARLY := 1 +USE_COHERENT_MEM := 1 # A53 erratum for SoC. (enable them all) ERRATA_A53_826319 := 1 @@ -28,10 +28,6 @@ ERRATA_A72_859971 := 1 # Split out RO data into a non-executable section SEPARATE_CODE_AND_RODATA := 1 -# Leave the caches enabled on core powerdown path -TI_AM65X_WORKAROUND := 1 -$(eval $(call add_define,TI_AM65X_WORKAROUND)) - MULTI_CONSOLE_API := 1 TI_16550_MDR_QUIRK := 1 $(eval $(call add_define,TI_16550_MDR_QUIRK)) diff --git a/readme.rst b/readme.rst index 684641997..84c8020bb 100644 --- a/readme.rst +++ b/readme.rst @@ -222,7 +222,7 @@ All the above platforms have been tested with `Linaro Release 18.04`_. This release also contains the following platform support: -- Allwinner sun50i_a64 and sun50i_h6 +- Allwinner sun50i (A64, H5, and H6) SoCs - Amlogic Meson S905 (GXBB) - Amlogic Meson S905x (GXL) - Arm Juno Software Development Platform |