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-rw-r--r--drivers/arm/gic/v3/gic600_multichip_private.h14
-rw-r--r--include/arch/aarch32/arch_helpers.h4
-rw-r--r--include/arch/aarch64/arch_helpers.h1
-rw-r--r--include/lib/coreboot.h23
-rw-r--r--lib/coreboot/coreboot_table.c32
-rw-r--r--lib/locks/bakery/bakery_lock_normal.c21
-rw-r--r--lib/xlat_tables_v2/xlat_tables_private.h5
-rw-r--r--plat/arm/board/fvp/fvp_def.h10
-rw-r--r--plat/arm/board/fvp/include/platform_def.h2
-rw-r--r--plat/arm/board/fvp/platform.mk13
-rw-r--r--plat/arm/board/juno/include/platform_def.h2
-rw-r--r--plat/arm/board/rddaniel/platform.mk3
-rw-r--r--plat/arm/css/sgi/include/sgi_base_platform_def.h2
-rw-r--r--plat/arm/css/sgm/include/sgm_base_platform_def.h2
-rw-r--r--plat/brcm/board/stingray/platform.mk2
15 files changed, 105 insertions, 31 deletions
diff --git a/drivers/arm/gic/v3/gic600_multichip_private.h b/drivers/arm/gic/v3/gic600_multichip_private.h
index b0217b6d4..fe4134cba 100644
--- a/drivers/arm/gic/v3/gic600_multichip_private.h
+++ b/drivers/arm/gic/v3/gic600_multichip_private.h
@@ -24,11 +24,21 @@
/* GIC600 GICD multichip related shifts */
#define GICD_CHIPRx_ADDR_SHIFT 16
-#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10
-#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5
#define GICD_CHIPSR_RTS_SHIFT 4
#define GICD_DCHIPR_RT_OWNER_SHIFT 4
+/*
+ * If GIC v4 extension is enabled, then use SPI macros specific to GIC-Clayton.
+ * Other shifts and mask remains same between GIC-600 and GIC-Clayton.
+ */
+#if GIC_ENABLE_V4_EXTN
+#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 9
+#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 3
+#else
+#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10
+#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5
+#endif
+
#define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0)
#define GICD_CHIPSR_RTS_STATE_UPDATING U(1)
#define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2)
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index cbac84b93..a90b2a54c 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#define ARCH_HELPERS_H
#include <cdefs.h>
+#include <stdbool.h>
#include <stdint.h>
#include <string.h>
@@ -178,6 +179,7 @@ static inline void _op ## _type(u_register_t v) \
void flush_dcache_range(uintptr_t addr, size_t size);
void clean_dcache_range(uintptr_t addr, size_t size);
void inv_dcache_range(uintptr_t addr, size_t size);
+bool is_dcache_enabled(void);
void dcsw_op_louis(u_register_t op_type);
void dcsw_op_all(u_register_t op_type);
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 7c30758d0..669a1403c 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -226,6 +226,7 @@ DEFINE_SYSOP_PARAM_FUNC(xpaci)
void flush_dcache_range(uintptr_t addr, size_t size);
void clean_dcache_range(uintptr_t addr, size_t size);
void inv_dcache_range(uintptr_t addr, size_t size);
+bool is_dcache_enabled(void);
void dcsw_op_louis(u_register_t op_type);
void dcsw_op_all(u_register_t op_type);
diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h
index 88212c315..dda3173a2 100644
--- a/include/lib/coreboot.h
+++ b/include/lib/coreboot.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,6 +19,27 @@ typedef struct {
} coreboot_serial_t;
extern coreboot_serial_t coreboot_serial;
+#define COREBOOT_MAX_MEMRANGES 32 /* libpayload also uses this limit */
+
+typedef struct __packed {
+ uint64_t start;
+ uint64_t size;
+ uint32_t type;
+} coreboot_memrange_t;
+extern coreboot_memrange_t coreboot_memranges[COREBOOT_MAX_MEMRANGES];
+
+typedef enum {
+ CB_MEM_NONE = 0, /* coreboot will never report this */
+ CB_MEM_RAM = 1,
+ CB_MEM_RESERVED = 2,
+ CB_MEM_ACPI = 3,
+ CB_MEM_NVS = 4,
+ CB_MEM_UNUSABLE = 5,
+ CB_MEM_VENDOR_RSVD = 6,
+ CB_MEM_TABLE = 16,
+} coreboot_memory_t;
+
+coreboot_memory_t coreboot_get_memory_type(uintptr_t address);
void coreboot_table_setup(void *base);
#endif /* COREBOOT_H */
diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c
index 253fac2ac..c4cd1d752 100644
--- a/lib/coreboot/coreboot_table.c
+++ b/lib/coreboot/coreboot_table.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,6 +29,7 @@ typedef struct {
} cb_header_t;
typedef enum {
+ CB_TAG_MEMORY = 0x1,
CB_TAG_SERIAL = 0xf,
CB_TAG_CBMEM_CONSOLE = 0x17,
} cb_tag_t;
@@ -37,11 +38,13 @@ typedef struct {
uint32_t tag;
uint32_t size;
union {
+ coreboot_memrange_t memranges[COREBOOT_MAX_MEMRANGES];
coreboot_serial_t serial;
uint64_t uint64;
};
} cb_entry_t;
+coreboot_memrange_t coreboot_memranges[COREBOOT_MAX_MEMRANGES];
coreboot_serial_t coreboot_serial;
/*
@@ -86,6 +89,23 @@ static void setup_cbmem_console(uintptr_t baseaddr)
CONSOLE_FLAG_CRASH);
}
+coreboot_memory_t coreboot_get_memory_type(uintptr_t address)
+{
+ int i;
+
+ for (i = 0; i < COREBOOT_MAX_MEMRANGES; i++) {
+ coreboot_memrange_t *range = &coreboot_memranges[i];
+
+ if (range->type == CB_MEM_NONE)
+ break; /* end of table reached */
+ if (address >= range->start &&
+ address - range->start < range->size)
+ return range->type;
+ }
+
+ return CB_MEM_NONE;
+}
+
void coreboot_table_setup(void *base)
{
cb_header_t *header = base;
@@ -99,6 +119,7 @@ void coreboot_table_setup(void *base)
ptr = base + header->header_bytes;
for (i = 0; i < header->table_entries; i++) {
+ size_t size;
cb_entry_t *entry = ptr;
if (ptr - base >= header->header_bytes + header->table_bytes) {
@@ -107,6 +128,15 @@ void coreboot_table_setup(void *base)
}
switch (read_le32(&entry->tag)) {
+ case CB_TAG_MEMORY:
+ size = read_le32(&entry->size) -
+ offsetof(cb_entry_t, memranges);
+ if (size > sizeof(coreboot_memranges)) {
+ ERROR("Need to truncate coreboot memranges!\n");
+ size = sizeof(coreboot_memranges);
+ }
+ memcpy(&coreboot_memranges, &entry->memranges, size);
+ break;
case CB_TAG_SERIAL:
memcpy(&coreboot_serial, &entry->serial,
sizeof(coreboot_serial));
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 0605fceb9..7d35dea66 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -84,7 +84,7 @@ static inline void read_cache_op(uintptr_t addr, bool cached)
/* Helper function to check if the lock is acquired */
static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info,
- int is_cached)
+ bool is_cached)
{
/*
* Even though lock data is updated only by the owning cpu and
@@ -99,7 +99,7 @@ static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info,
}
static unsigned int bakery_get_ticket(bakery_lock_t *lock,
- unsigned int me, int is_cached)
+ unsigned int me, bool is_cached)
{
unsigned int my_ticket, their_ticket;
unsigned int they;
@@ -164,17 +164,14 @@ static unsigned int bakery_get_ticket(bakery_lock_t *lock,
void bakery_lock_get(bakery_lock_t *lock)
{
- unsigned int they, me, is_cached;
+ unsigned int they, me;
unsigned int my_ticket, my_prio, their_ticket;
bakery_info_t *their_bakery_info;
unsigned int their_bakery_data;
+ bool is_cached;
me = plat_my_core_pos();
-#ifdef __aarch64__
- is_cached = read_sctlr_el3() & SCTLR_C_BIT;
-#else
- is_cached = read_sctlr() & SCTLR_C_BIT;
-#endif
+ is_cached = is_dcache_enabled();
/* Get a ticket */
my_ticket = bakery_get_ticket(lock, me, is_cached);
@@ -232,11 +229,7 @@ void bakery_lock_get(bakery_lock_t *lock)
void bakery_lock_release(bakery_lock_t *lock)
{
bakery_info_t *my_bakery_info;
-#ifdef __aarch64__
- unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT;
-#else
- unsigned int is_cached = read_sctlr() & SCTLR_C_BIT;
-#endif
+ bool is_cached = is_dcache_enabled();
my_bakery_info = get_bakery_info(plat_my_core_pos(), lock);
diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h
index 70ef39523..863470cf3 100644
--- a/lib/xlat_tables_v2/xlat_tables_private.h
+++ b/lib/xlat_tables_v2/xlat_tables_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -99,9 +99,6 @@ unsigned long long xlat_arch_get_max_supported_pa(void);
*/
bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
-/* Returns true if the data cache is enabled at the current EL. */
-bool is_dcache_enabled(void);
-
/*
* Returns minimum virtual address space size supported by the architecture
*/
diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
index 909b68717..c5d156858 100644
--- a/plat/arm/board/fvp/fvp_def.h
+++ b/plat/arm/board/fvp/fvp_def.h
@@ -52,10 +52,18 @@
#define DEVICE1_BASE UL(0x2e000000)
#define DEVICE1_SIZE UL(0x1A00000)
#else
-/* GICv2 and GICv3 mapping: GICD + CORE_COUNT * 128KB */
#define DEVICE1_BASE BASE_GICD_BASE
+
+#if GIC_ENABLE_V4_EXTN
+/* GICv4 mapping: GICD + CORE_COUNT * 256KB */
+#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
+ (PLATFORM_CORE_COUNT * 0x40000))
+#else
+/* GICv2 and GICv3 mapping: GICD + CORE_COUNT * 128KB */
#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
(PLATFORM_CORE_COUNT * 0x20000))
+#endif /* GIC_ENABLE_V4_EXTN */
+
#define NSRAM_BASE UL(0x2e000000)
#define NSRAM_SIZE UL(0x10000)
#endif
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 1f569c250..1ed307429 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -120,7 +120,7 @@
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION)
#else
-# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION)
+# define PLAT_ARM_MAX_BL2_SIZE (UL(0x12000) - FVP_BL2_ROMLIB_OPTIMIZATION)
#endif
#if RESET_TO_BL31
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 784369024..04cebcac3 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -50,12 +50,12 @@ $(eval $(call add_define,FVP_INTERCONNECT_DRIVER))
# Choose the GIC sources depending upon the how the FVP will be invoked
ifeq (${FVP_USE_GIC_DRIVER},$(filter ${FVP_USE_GIC_DRIVER},FVP_GICV3 FVP_GIC600))
+
+ # GIC500 is the default option in case GICV3_IMPL is not set
ifeq (${FVP_USE_GIC_DRIVER}, FVP_GIC600)
GICV3_IMPL := GIC600
endif
-# GIC500 is the default option in case GICV3_IMPL is not set
-
GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
# Include GICv3 driver files
@@ -66,6 +66,15 @@ FVP_GIC_SOURCES := ${GICV3_SOURCES} \
plat/arm/common/arm_gicv3.c
else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
+
+# No GICv4 extension
+GIC_ENABLE_V4_EXTN := 0
+$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
+
+# No support for extended PPI and SPI range
+GIC_EXT_INTID := 0
+$(eval $(call add_define,GIC_EXT_INTID))
+
FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index b44639528..43c267d08 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -139,7 +139,7 @@
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#endif
#else
-# define PLAT_ARM_MAX_BL2_SIZE (UL(0xF000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
+# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#endif
/*
diff --git a/plat/arm/board/rddaniel/platform.mk b/plat/arm/board/rddaniel/platform.mk
index ca2647418..94a3928f8 100644
--- a/plat/arm/board/rddaniel/platform.mk
+++ b/plat/arm/board/rddaniel/platform.mk
@@ -3,6 +3,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+# RD-Daniel platform uses GIC-Clayton which is based on GICv4.1
+GIC_ENABLE_V4_EXTN := 1
+
include plat/arm/css/sgi/sgi-common.mk
RDDANIEL_BASE = plat/arm/board/rddaniel
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index 8c8b2311d..3b8d56585 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -77,7 +77,7 @@
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x11000
+# define PLAT_ARM_MAX_BL2_SIZE 0x14000
#endif
/*
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
index 0ac0c2b3c..12fa07f3c 100644
--- a/plat/arm/css/sgm/include/sgm_base_platform_def.h
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -187,7 +187,7 @@
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x11000
+# define PLAT_ARM_MAX_BL2_SIZE 0x12000
#endif
/*
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk
index 20ebcddc3..c5509bb6b 100644
--- a/plat/brcm/board/stingray/platform.mk
+++ b/plat/brcm/board/stingray/platform.mk
@@ -70,7 +70,7 @@ $(eval $(call add_define,USE_DDR))
endif
ifeq (${BOARD_CFG},)
-BOARD_CFG := bcm958742k
+BOARD_CFG := bcm958742t
endif
# Use PAXB
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-16 02:17:25 +0000