diff options
27 files changed, 395 insertions, 62 deletions
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index aca16d677..856ea9f62 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -90,7 +90,7 @@ void bl31_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, * function calls runtime_svc_init() which initializes all registered runtime * services. The run time services would setup enough context for the core to * switch to the next exception level. When this function returns, the core will - * switch to the programmed exception level via. an ERET. + * switch to the programmed exception level via an ERET. ******************************************************************************/ void bl31_main(void) { diff --git a/bl31/ehf.c b/bl31/ehf.c index 1bcebee53..745f165d4 100644 --- a/bl31/ehf.c +++ b/bl31/ehf.c @@ -314,9 +314,9 @@ static void *ehf_entering_normal_world(const void *arg) /* * Program Priority Mask to the original Non-secure priority such that - * Non-secure interrupts may preempt Secure execution, viz. during Yielding SMC - * calls. The 'preempt_ret_code' parameter indicates the Yielding SMC's return - * value in case the call was preempted. + * Non-secure interrupts may preempt Secure execution (for example, during + * Yielding SMC calls). The 'preempt_ret_code' parameter indicates the Yielding + * SMC's return value in case the call was preempted. * * This API is expected to be invoked before delegating a yielding SMC to Secure * EL1. I.e. within the window of secure execution after Non-secure context is @@ -360,7 +360,7 @@ void ehf_allow_ns_preemption(uint64_t preempt_ret_code) /* * Return whether Secure execution has explicitly allowed Non-secure interrupts - * to preempt itself, viz. during Yielding SMC calls. + * to preempt itself (for example, during Yielding SMC calls). */ unsigned int ehf_is_ns_preemption_allowed(void) { diff --git a/docs/arm-sip-service.rst b/docs/arm-sip-service.rst index 9f0e26615..6cdac8357 100644 --- a/docs/arm-sip-service.rst +++ b/docs/arm-sip-service.rst @@ -4,7 +4,7 @@ Arm SiP Service This document enumerates and describes the Arm SiP (Silicon Provider) services. SiP services are non-standard, platform-specific services offered by the silicon -implementer or platform provider. They are accessed via. ``SMC`` ("SMC calls") +implementer or platform provider. They are accessed via ``SMC`` ("SMC calls") instruction executed from Exception Levels below EL3. SMC calls for SiP services: diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index e185aa176..81738d8c2 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -164,6 +164,30 @@ For Cortex-A72, the following errata build flags are defined : - ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. +For Cortex-A73, the following errata build flags are defined : + +- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 + CPU. This needs to be enabled only for revision <= r0p1 of the CPU. + +For Cortex-A75, the following errata build flags are defined : + +- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + +- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + +For Cortex-A76, the following errata build flags are defined : + +- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r1p0 of the CPU. + +- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + +- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + DSU Errata Workarounds ---------------------- diff --git a/docs/exception-handling.rst b/docs/exception-handling.rst index dbcd4bca8..b7cd69d4c 100644 --- a/docs/exception-handling.rst +++ b/docs/exception-handling.rst @@ -233,7 +233,7 @@ Note: The ``ARRAY_SIZE()`` macro therefore should be used to determine the size of array. -Finally, this array of descriptors is exposed to |EHF| via. the +Finally, this array of descriptors is exposed to |EHF| via the ``EHF_REGISTER_PRIORITIES()`` macro. Refer to the `Interrupt handling example`_ for usage. See also: `Interrupt @@ -379,8 +379,8 @@ Activating and Deactivating priorities A priority level is said to be *active* when an exception of that priority is being handled: for interrupts, this is implied when the interrupt is -acknowledged; for non-interrupt exceptions, viz. SErrors or `SDEI explicit -dispatches`__, this has to be done via. calling ``ehf_activate_priority()``. See +acknowledged; for non-interrupt exceptions, such as SErrors or `SDEI explicit +dispatches`__, this has to be done via calling ``ehf_activate_priority()``. See `Run-time flow`_. .. __: sdei.rst#explicit-dispatch-of-events @@ -388,7 +388,7 @@ dispatches`__, this has to be done via. calling ``ehf_activate_priority()``. See Conversely, when the dispatcher has reached a logical resolution for the cause of the exception, the corresponding priority level ought to be deactivated. As above, for interrupts, this is implied when the interrupt is EOId in the GIC; -for other exceptions, this has to be done via. calling +for other exceptions, this has to be done via calling ``ehf_deactivate_priority()``. Thanks to `different provisions`__ for exception delegation, there are @@ -405,7 +405,7 @@ potentially more than one work flow for deactivation: - The dispatcher has to delegate the execution to lower ELs, and the cause of the exception can be considered resolved only when the lower EL returns - signals complete (via. an ``SMC``) at a future point in time. The following + signals complete (via an ``SMC``) at a future point in time. The following sequence ensues: #. The dispatcher calls ``setjmp()`` to setup a jump point, and arranges to @@ -414,7 +414,7 @@ potentially more than one work flow for deactivation: #. Through the ensuing ``ERET`` from runtime firmware, execution is delegated to a lower EL. - #. The lower EL completes its execution, and signals completion via. an + #. The lower EL completes its execution, and signals completion via an ``SMC``. #. The ``SMC`` is handled by the same dispatcher that handled the exception @@ -597,7 +597,7 @@ world ones. The platform further assigns relative priorities amongst Secure dispatchers through |EHF|. As mentioned in `Partitioning priority levels`_, interrupts targeting distinct -dispatchers fall in distinct priority levels. Because they're routed via. the +dispatchers fall in distinct priority levels. Because they're routed via the GIC, interrupt delivery to the PE is subject to GIC prioritisation rules. In particular, when an interrupt is being handled by the PE (i.e., the interrupt is in *Active* state), only interrupts of higher priority are signalled to the PE, diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst index ead7297d9..266de2795 100644 --- a/docs/firmware-design.rst +++ b/docs/firmware-design.rst @@ -1282,9 +1282,9 @@ interrupt configuration during the driver initialisation. Secure interrupt configuration are specified in an array of secure interrupt properties. In this scheme, in both GICv2 and GICv3 driver data structures, the ``interrupt_props`` member points to an array of interrupt properties. Each -element of the array specifies the interrupt number and its configuration, viz. -priority, group, configuration. Each element of the array shall be populated by -the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: +element of the array specifies the interrupt number and its attributes +(priority, group, configuration). Each element of the array shall be populated +by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: - 10-bit interrupt number, @@ -1439,7 +1439,7 @@ C run time. Therefore it must follow AAPCS, and must not use stack. CPU drivers that apply errata workaround can optionally implement an assembly function that report the status of errata workarounds pertaining to that CPU. -For a driver that registers the CPU, for example, ``cpux`` via. ``declare_cpu_ops`` +For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` macro, the errata reporting function, if it exists, must be named ``cpux_errata_report``. This function will always be called with MMU enabled; it must follow AAPCS and may use stack. diff --git a/docs/platform-interrupt-controller-API.rst b/docs/platform-interrupt-controller-API.rst index 230a99055..ad68709a3 100644 --- a/docs/platform-interrupt-controller-API.rst +++ b/docs/platform-interrupt-controller-API.rst @@ -22,7 +22,7 @@ Function: unsigned int plat_ic_get_running_priority(void); [optional] This API should return the priority of the interrupt the PE is currently servicing. This must be be called only after an interrupt has already been -acknowledged via. ``plat_ic_acknowledge_interrupt``. +acknowledged via ``plat_ic_acknowledge_interrupt``. In the case of Arm standard platforms using GIC, the *Running Priority Register* is read to determine the priority of the interrupt. diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index c3df389f8..3ea86b04f 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -1936,7 +1936,7 @@ handler (if present) is called for the CPU power domain. The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to describe composite power states specific to a platform. The PSCI implementation -defines a generic representation of the power-state parameter viz which is an +defines a generic representation of the power-state parameter, which is an array of local power states where each index corresponds to a power domain level. Each entry contains the local power state the power domain at that power level could enter. It depends on the ``validate_power_state()`` handler to diff --git a/docs/ras.rst b/docs/ras.rst index cea74e9af..ac4d019f1 100644 --- a/docs/ras.rst +++ b/docs/ras.rst @@ -15,10 +15,10 @@ Serviceability (RAS) extensions. RAS is a mandatory extension for Armv8.2 and later CPUs, and also an optional extension to the base Armv8.0 architecture. In conjunction with the |EHF|, support for RAS extension enables firmware-first -paradigm for handling platform errors, in which exceptions resulting from -errors—viz. Synchronous External Abort (SEA), Asynchronous External Abort -(signalled as SErrors), Fault Handling and Error Recovery interrupts are routed -to and handled in EL3. The |EHF| document mentions various `error handling +paradigm for handling platform errors: exceptions resulting from errors are +routed to and handled in EL3. Said errors are Synchronous External Abort (SEA), +Asynchronous External Abort (signalled as SErrors), Fault Handling and Error +Recovery interrupts. The |EHF| document mentions various `error handling use-cases`__. .. __: exception-handling.rst#delegation-use-cases @@ -66,7 +66,7 @@ through one one of the notification mechanisms—SEAs, SErrors, or interrupts. R nodes contain one or more error records, which are registers through which the nodes advertise various properties of the signalled error. Arm recommends that error records are implemented in the Standard Error Record format. The RAS -architecture allows for error records to be accessible via. system or +architecture allows for error records to be accessible via system or memory-mapped registers. The platform should enumerate the error records providing for each of them: @@ -121,7 +121,7 @@ The error handler must have the following prototype: int probe_data, const struct err_handler_data *const data); The ``data`` constant parameter describes the various properties of the error, -viz. the reason for the error, exception syndrome, and also ``flags``, +including the reason for the error, exception syndrome, and also ``flags``, ``cookie``, and ``handle`` parameters from the `top-level exception handler`__. .. __: interrupt-framework-design.rst#el3-interrupts diff --git a/docs/sdei.rst b/docs/sdei.rst index 531145f87..c52481706 100644 --- a/docs/sdei.rst +++ b/docs/sdei.rst @@ -142,7 +142,7 @@ Event flags describe the properties of the event. They are bit maps that can be .. __: `Defining events`_ - ``SDEI_MAPF_DYNAMIC``: Marks the event as dynamic. Dynamic events can be - bound to (or released from) any Non-secure interrupt at runtime via. the + bound to (or released from) any Non-secure interrupt at runtime via the ``SDEI_INTERRUPT_BIND`` and ``SDEI_INTERRUPT_RELEASE`` calls. - ``SDEI_MAPF_BOUND``: Marks the event as statically bound to an interrupt. @@ -226,7 +226,7 @@ Explicit dispatch of events Typically, an SDEI event dispatch is caused by the PE receiving interrupts that are bound to an SDEI event. However, there are cases where the Secure world requires dispatch of an SDEI event as a direct or indirect result of a past -activity, viz. receiving a Secure interrupt or an exception. +activity, such as receiving a Secure interrupt or an exception. The SDEI dispatcher implementation provides ``sdei_dispatch_event()`` API for this purpose. The API has the following signature: diff --git a/docs/user-guide.rst b/docs/user-guide.rst index b42012757..b602956aa 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -548,13 +548,13 @@ Common build options - ``KEY_ALG``: This build flag enables the user to select the algorithm to be used for generating the PKCS keys and subsequent signing of the certificate. - It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is - the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is - retained only for compatibility. The default value of this flag is ``rsa`` - which is the TBBR compliant PKCS#1 RSA 2.1 scheme. + It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option + ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR + compliant and is retained only for compatibility. The default value of this + flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. - ``HASH_ALG``: This build flag enables the user to select the secure hash - algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``. + algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. The default value of this flag is ``sha256``. - ``LDFLAGS``: Extra user options appended to the linkers' command line in @@ -619,14 +619,14 @@ Common build options does not need to be implemented in this case. - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats - possible for the PSCI power-state parameter viz original and extended - State-ID formats. This flag if set to 1, configures the generic PSCI layer - to use the extended format. The default value of this flag is 0, which - means by default the original power-state format is used by the PSCI - implementation. This flag should be specified by the platform makefile - and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND - smc function id. When this option is enabled on Arm platforms, the - option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well. + possible for the PSCI power-state parameter: original and extended State-ID + formats. This flag if set to 1, configures the generic PSCI layer to use the + extended format. The default value of this flag is 0, which means by default + the original power-state format is used by the PSCI implementation. This flag + should be specified by the platform makefile and it governs the return value + of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is + enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be + set to 1 as well. - ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 diff --git a/drivers/arm/css/scpi/css_scpi.c b/drivers/arm/css/scpi/css_scpi.c index 4b73265ad..c56b7c41b 100644 --- a/drivers/arm/css/scpi/css_scpi.c +++ b/drivers/arm/css/scpi/css_scpi.c @@ -169,7 +169,7 @@ void scpi_set_css_power_state(unsigned int mpidr, * In response to the query, SCP returns power states of all CPUs in all * clusters of the system. The returned response is then filtered based on the * supplied MPIDR. Power states of requested cluster and CPUs within are updated - * via. supplied non-NULL pointer arguments. + * via supplied non-NULL pointer arguments. * * Returns 0 on success, or -1 on errors. */ @@ -223,7 +223,7 @@ int scpi_get_css_power_state(unsigned int mpidr, unsigned int *cpu_state_p, if (CLUSTER_ID(power_state) != cluster) goto exit; - /* Update power state via. pointers */ + /* Update power state via pointers */ if (cluster_state_p) *cluster_state_p = CLUSTER_POWER_STATE(power_state); if (cpu_state_p) diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index c5d4fe1c3..c5bced00d 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -279,8 +279,8 @@ unsigned int gicv2_get_running_priority(void) /******************************************************************************* * This function sets the GICv2 target mask pattern for the current PE. The PE * target mask is used to translate linear PE index (returned by platform core - * position) to a bit mask used when targeting interrupts to a PE, viz. when - * raising SGIs and routing SPIs. + * position) to a bit mask used when targeting interrupts to a PE (for example + * when raising SGIs and routing SPIs). ******************************************************************************/ void gicv2_set_pe_target_mask(unsigned int proc_num) { diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index f796ae868..debe8722c 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -255,6 +255,7 @@ #define SCTLR_NTWE_BIT (ULL(1) << 18) #define SCTLR_WXN_BIT (ULL(1) << 19) #define SCTLR_UWXN_BIT (ULL(1) << 20) +#define SCTLR_IESB_BIT (ULL(1) << 21) #define SCTLR_E0E_BIT (ULL(1) << 24) #define SCTLR_EE_BIT (ULL(1) << 25) #define SCTLR_UCI_BIT (ULL(1) << 26) @@ -786,6 +787,10 @@ /* MPAM register definitions */ #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) +#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) + +#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) +#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 3b401805a..61b2b737b 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -31,4 +31,6 @@ #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3) +#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2 + #endif /* CORTEX_A73_H */ diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 5779d7bab..c2af8cad9 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -18,9 +18,15 @@ #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) + /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) + #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) diff --git a/include/lib/el3_runtime/pubsub.h b/include/lib/el3_runtime/pubsub.h index eb9128656..9c303f548 100644 --- a/include/lib/el3_runtime/pubsub.h +++ b/include/lib/el3_runtime/pubsub.h @@ -49,7 +49,7 @@ /* * Have the function func called back when the specified event happens. This * macro places the function address into the pubsub section, which is picked up - * and invoked by the invoke_pubsubs() function via. the PUBLISH_EVENT* macros. + * and invoked by the invoke_pubsubs() function via the PUBLISH_EVENT* macros. * * The extern declaration is there to satisfy MISRA C-2012 rule 8.4. */ diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h index 9f6b2905f..98daab601 100644 --- a/include/lib/extensions/ras.h +++ b/include/lib/extensions/ras.h @@ -106,7 +106,7 @@ struct err_handler_data { */ uint32_t syndrome; - /* For errors signalled via. interrupt, the raw interrupt ID; otherwise, 0. */ + /* For errors signalled via interrupt, the raw interrupt ID; otherwise, 0. */ unsigned int interrupt; }; @@ -129,7 +129,7 @@ struct err_record_info { union { struct { /* - * For a group accessed via. memory-mapped register, + * For a group accessed via memory-mapped register, * base address of the page hosting error records, and * the size of the record group. */ @@ -141,7 +141,7 @@ struct err_record_info { struct { /* - * For error records accessed via. system register, index of + * For error records accessed via system register, index of * the error record. */ unsigned int idx_start; diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S index 772b0be79..6cfa4b523 100644 --- a/lib/cpus/aarch64/cortex_a73.S +++ b/lib/cpus/aarch64/cortex_a73.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,7 +35,47 @@ func cortex_a73_disable_smp ret endfunc cortex_a73_disable_smp + /* --------------------------------------------------- + * Errata Workaround for Cortex A73 Errata #855423. + * This applies only to revision <= r0p1 of Cortex A73. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------- + */ +func errata_a73_855423_wa + /* + * Compare x0 against revision r0p1 + */ + mov x17, x30 + bl check_errata_855423 + cbz x0, 1f + mrs x1, CORTEX_A73_IMP_DEF_REG2 + orr x1, x1, #(1 << 7) + msr CORTEX_A73_IMP_DEF_REG2, x1 + isb +1: + ret x17 +endfunc errata_a73_855423_wa + +func check_errata_855423 + mov x1, #0x01 + b cpu_rev_var_ls +endfunc check_errata_855423 + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A73. + * ------------------------------------------------- + */ + func cortex_a73_reset_func + mov x19, x30 + bl cpu_get_rev_var + +#if ERRATA_A73_855423 + bl errata_a73_855423_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 cpu_check_csv2 x0, 1f adr x0, wa_cve_2017_5715_bpiall_vbar @@ -60,7 +100,7 @@ func cortex_a73_reset_func orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT msr CORTEX_A73_CPUECTLR_EL1, x0 isb - ret + ret x19 endfunc cortex_a73_reset_func func cortex_a73_core_pwr_dwn @@ -160,6 +200,7 @@ func cortex_a73_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A73_855423, cortex_a73, 855423 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715 report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639 diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index e121b7da8..204018890 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,8 +10,81 @@ #include <cpuamu.h> #include <cpu_macros.S> + /* -------------------------------------------------- + * Errata Workaround for Cortex A75 Errata #764081. + * This applies only to revision r0p0 of Cortex A75. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a75_764081_wa + /* + * Compare x0 against revision r0p0 + */ + mov x17, x30 + bl check_errata_764081 + cbz x0, 1f + mrs x1, sctlr_el3 + orr x1, x1 ,#SCTLR_IESB_BIT + msr sctlr_el3, x1 + isb +1: + ret x17 +endfunc errata_a75_764081_wa + +func check_errata_764081 + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_764081 + + /* -------------------------------------------------- + * Errata Workaround for Cortex A75 Errata #790748. + * This applies only to revision r0p0 of Cortex A75. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a75_790748_wa + /* + * Compare x0 against revision r0p0 + */ + mov x17, x30 + bl check_errata_790748 + cbz x0, 1f + mrs x1, CORTEX_A75_CPUACTLR_EL1 + orr x1, x1 ,#(1 << 13) + msr CORTEX_A75_CPUACTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a75_790748_wa + +func check_errata_790748 + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_790748 + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A75. + * ------------------------------------------------- + */ func cortex_a75_reset_func mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A75_764081 + mov x0, x18 + bl errata_a75_764081_wa +#endif + +#if ERRATA_A75_790748 + mov x0, x18 + bl errata_a75_790748_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 cpu_check_csv2 x0, 1f adr x0, wa_cve_2017_5715_bpiall_vbar @@ -109,6 +182,8 @@ func cortex_a75_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A75_764081, cortex_a75, 764081 + report_errata ERRATA_A75_790748, cortex_a75, 790748 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 27db74e41..ac513432f 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -189,6 +189,90 @@ vector_entry cortex_a76_serror_aarch32 b serror_aarch32 end_vector_entry cortex_a76_serror_aarch32 + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1073348. + * This applies only to revision <= r1p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1073348_wa + /* + * Compare x0 against revision r1p0 + */ + mov x17, x30 + bl check_errata_1073348 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUACTLR_EL1 + orr x1, x1 ,#CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION + msr CORTEX_A76_CPUACTLR_EL1, x1 + isb +1: + ret x17 + endfunc errata_a76_1073348_wa + +func check_errata_1073348 + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1073348 + + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1130799. + * This applies only to revision <= r2p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1130799_wa + /* + * Compare x0 against revision r2p0 + */ + mov x17, x30 + bl check_errata_1130799 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUACTLR2_EL1 + orr x1, x1 ,#(1 << 59) + msr CORTEX_A76_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1130799_wa + +func check_errata_1130799 + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_1130799 + + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1220197. + * This applies only to revision <= r2p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1220197_wa +/* + * Compare x0 against revision r2p0 + */ + mov x17, x30 + bl check_errata_1220197 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUECTLR_EL1 + orr x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 + msr CORTEX_A76_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1220197_wa + +func check_errata_1220197 + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_1220197 + func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 mov x0, #ERRATA_APPLIES @@ -206,8 +290,30 @@ func cortex_a76_disable_wa_cve_2018_3639 ret endfunc cortex_a76_disable_wa_cve_2018_3639 + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A76. + * Shall clobber: x0-x19 + * ------------------------------------------------- + */ func cortex_a76_reset_func mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A76_1073348 + mov x0, x18 + bl errata_a76_1073348_wa +#endif + +#if ERRATA_A76_1130799 + mov x0, x18 + bl errata_a76_1130799_wa +#endif + +#if ERRATA_A76_1220197 + mov x0, x18 + bl errata_a76_1220197_wa +#endif #if WORKAROUND_CVE_2018_3639 /* If the PE implements SSBS, we don't need the dynamic workaround */ @@ -271,6 +377,9 @@ func cortex_a76_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A76_1073348, cortex_a76, 1073348 + report_errata ERRATA_A76_1130799, cortex_a76, 1130799 + report_errata ERRATA_A76_1220197, cortex_a76, 1220197 report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639 report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 3dfb66f9b..2d3984e10 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -159,6 +159,30 @@ ERRATA_A57_859972 ?=0 # only to revision <= r0p3 of the Cortex A72 cpu. ERRATA_A72_859971 ?=0 +# Flag to apply erratum 855423 workaround during reset. This erratum applies +# only to revision <= r0p1 of the Cortex A73 cpu. +ERRATA_A73_855423 ?=0 + +# Flag to apply erratum 764081 workaround during reset. This erratum applies +# only to revision <= r0p0 of the Cortex A75 cpu. +ERRATA_A75_764081 ?=0 + +# Flag to apply erratum 790748 workaround during reset. This erratum applies +# only to revision <= r0p0 of the Cortex A75 cpu. +ERRATA_A75_790748 ?=0 + +# Flag to apply erratum 1073348 workaround during reset. This erratum applies +# only to revision <= r1p0 of the Cortex A76 cpu. +ERRATA_A76_1073348 ?=0 + +# Flag to apply erratum 1130799 workaround during reset. This erratum applies +# only to revision <= r2p0 of the Cortex A76 cpu. +ERRATA_A76_1130799 ?=0 + +# Flag to apply erratum 1220197 workaround during reset. This erratum applies +# only to revision <= r2p0 of the Cortex A76 cpu. +ERRATA_A76_1220197 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=1 @@ -268,6 +292,30 @@ $(eval $(call add_define,ERRATA_A57_859972)) $(eval $(call assert_boolean,ERRATA_A72_859971)) $(eval $(call add_define,ERRATA_A72_859971)) +# Process ERRATA_A73_855423 flag +$(eval $(call assert_boolean,ERRATA_A73_855423)) +$(eval $(call add_define,ERRATA_A73_855423)) + +# Process ERRATA_A75_764081 flag +$(eval $(call assert_boolean,ERRATA_A75_764081)) +$(eval $(call add_define,ERRATA_A75_764081)) + +# Process ERRATA_A75_790748 flag +$(eval $(call assert_boolean,ERRATA_A75_790748)) +$(eval $(call add_define,ERRATA_A75_790748)) + +# Process ERRATA_A76_1073348 flag +$(eval $(call assert_boolean,ERRATA_A76_1073348)) +$(eval $(call add_define,ERRATA_A76_1073348)) + +# Process ERRATA_A76_1130799 flag +$(eval $(call assert_boolean,ERRATA_A76_1130799)) +$(eval $(call add_define,ERRATA_A76_1130799)) + +# Process ERRATA_A76_1220197 flag +$(eval $(call assert_boolean,ERRATA_A76_1220197)) +$(eval $(call add_define,ERRATA_A76_1220197)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 4489e908b..4371cb2b2 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -456,7 +456,7 @@ func restore_gp_registers endfunc restore_gp_registers /* ----------------------------------------------------- - * Restore general purpose registers (including x30), and exit EL3 via. ERET to + * Restore general purpose registers (including x30), and exit EL3 via ERET to * a lower exception level. * ----------------------------------------------------- */ diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 83f6e4895..89d7ed682 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -187,6 +187,14 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; } +#if ERRATA_A75_764081 + /* + * If workaround of errata 764081 for Cortex-A75 is used then set + * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. + */ + sctlr_elx |= SCTLR_IESB_BIT; +#endif + /* * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 * and other EL2 registers are set up by cm_prepare_ns_entry() as they @@ -319,6 +327,14 @@ void cm_prepare_el3_exit(uint32_t security_state) CTX_SCTLR_EL1); sctlr_elx &= SCTLR_EE_BIT; sctlr_elx |= SCTLR_EL2_RES1; +#if ERRATA_A75_764081 + /* + * If workaround of errata 764081 for Cortex-A75 is used + * then set SCTLR_EL2.IESB to enable Implicit Error + * Synchronization Barrier. + */ + sctlr_elx |= SCTLR_IESB_BIT; +#endif write_sctlr_el2(sctlr_elx); } else if (el_implemented(2) != EL_IMPL_NONE) { el2_unused = true; diff --git a/lib/extensions/mpam/mpam.c b/lib/extensions/mpam/mpam.c index 016670790..e794f013b 100644 --- a/lib/extensions/mpam/mpam.c +++ b/lib/extensions/mpam/mpam.c @@ -31,11 +31,19 @@ void mpam_enable(bool el2_unused) /* * If EL2 is implemented but unused, disable trapping to EL2 when lower * ELs access their own MPAM registers. + * If EL2 is implemented and used, enable trapping to EL2. */ if (el2_unused) { write_mpam2_el2(0); if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U) write_mpamhcr_el2(0); + } else { + write_mpam2_el2(MPAM2_EL2_TRAPMPAM0EL1 | + MPAM2_EL2_TRAPMPAM1EL1); + + if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U) { + write_mpamhcr_el2(MPAMHCR_EL2_TRAP_MPAMIDR_EL1); + } } } diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 819abcd18..be84f7791 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -140,8 +140,7 @@ PL011_GENERIC_UART := 0 # The platform Makefile is free to override this value. PROGRAMMABLE_RESET_ADDRESS := 0 -# Flag used to choose the power state format viz Extended State-ID or the -# Original format. +# Flag used to choose the power state format: Extended State-ID or Original PSCI_EXTENDED_STATE_ID := 0 # Enable RAS support diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S index 972a118a4..f9780e80c 100644 --- a/plat/common/aarch64/platform_mp_stack.S +++ b/plat/common/aarch64/platform_mp_stack.S @@ -14,13 +14,13 @@ .weak plat_set_my_stack /* --------------------------------------------------------------------- - * When the compatility layer is disabled, the new platform APIs - * viz plat_get_my_stack() and plat_set_my_stack() are - * supported by the platform and the previous APIs platform_get_stack() - * and platform_set_stack() are defined in terms of new APIs making use - * of the fact that they are only ever invoked for the current CPU. - * This is to enable components of Trusted Firmware like SPDs using the - * old platform APIs to continue to work. + * When the compatility layer is disabled, the platform APIs + * plat_get_my_stack() and plat_set_my_stack() are supported by the + * platform and the previous APIs platform_get_stack() and + * platform_set_stack() are defined in terms of new APIs making use of + * the fact that they are only ever invoked for the current CPU. This + * is to enable components of Trusted Firmware like SPDs using the old + * platform APIs to continue to work. * -------------------------------------------------------------------- */ |