diff options
90 files changed, 1343 insertions, 2390 deletions
@@ -204,6 +204,18 @@ LD = $(LINKER) AS = $(CC) -c -x assembler-with-cpp $(TF_CFLAGS_$(ARCH)) CPP = $(CC) -E PP = $(CC) -E +else ifneq ($(findstring gcc,$(notdir $(CC))),) +TF_CFLAGS_aarch32 = $(march32-directive) +TF_CFLAGS_aarch64 = $(march64-directive) +ifeq ($(ENABLE_LTO),1) + # Enable LTO only for aarch64 + ifeq (${ARCH},aarch64) + LTO_CFLAGS = -flto + # Use gcc as a wrapper for the ld, recommended for LTO + LINKER := ${CROSS_COMPILE}gcc + endif +endif +LD = $(LINKER) else TF_CFLAGS_aarch32 = $(march32-directive) TF_CFLAGS_aarch64 = $(march64-directive) @@ -240,7 +252,6 @@ WARNING1 += -Wmissing-declarations WARNING1 += -Wmissing-format-attribute WARNING1 += -Wmissing-prototypes WARNING1 += -Wold-style-definition -WARNING1 += -Wunused-const-variable # Level 2 WARNING2 := -Waggregate-return @@ -285,8 +296,9 @@ CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \ -ffreestanding -Wa,--fatal-warnings TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ - -ffreestanding -fno-builtin -std=gnu99 \ - -Os -ffunction-sections -fdata-sections + -ffunction-sections -fdata-sections \ + -ffreestanding -fno-builtin -fno-common \ + -Os -std=gnu99 ifeq (${SANITIZE_UB},on) TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover @@ -301,11 +313,28 @@ GCC_V_OUTPUT := $(shell $(CC) -v 2>&1) ifneq ($(findstring armlink,$(notdir $(LD))),) TF_LDFLAGS += --diag_error=warning --lto_level=O1 TF_LDFLAGS += --remove --info=unused,unusedsymbols +TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) +else ifneq ($(findstring gcc,$(notdir $(LD))),) +# Pass ld options with Wl or Xlinker switches +TF_LDFLAGS += -Wl,--fatal-warnings -O1 +TF_LDFLAGS += -Wl,--gc-sections +ifeq ($(ENABLE_LTO),1) + ifeq (${ARCH},aarch64) + TF_LDFLAGS += -flto -fuse-linker-plugin + endif +endif +# GCC automatically adds fix-cortex-a53-843419 flag when used to link +# which breaks some builds, so disable if errata fix is not explicitly enabled +ifneq (${ERRATA_A53_843419},1) + TF_LDFLAGS += -mno-fix-cortex-a53-843419 +endif +TF_LDFLAGS += -nostdlib +TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH))) else TF_LDFLAGS += --fatal-warnings -O1 TF_LDFLAGS += --gc-sections -endif TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) +endif DTC_FLAGS += -I dts -O dtb DTC_CPPFLAGS += -nostdinc -Iinclude -undef -x assembler-with-cpp @@ -406,7 +435,11 @@ endif ifeq ($(ENABLE_PIE),1) TF_CFLAGS += -fpie - TF_LDFLAGS += -pie --no-dynamic-linker + ifneq ($(findstring gcc,$(notdir $(LD))),) + TF_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker + else + TF_LDFLAGS += -pie --no-dynamic-linker + endif else PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT}) ifneq ($(PIE_FOUND),) @@ -624,6 +657,13 @@ SPTOOL ?= ${SPTOOLPATH}/sptool${BIN_EXT} # Variables for use with ROMLIB ROMLIBPATH ?= lib/romlib +# Variable for use with Python +PYTHON ?= python3 + +# Variables for use with PRINT_MEMORY_MAP +PRINT_MEMORY_MAP_PATH ?= tools/memory +PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py + ################################################################################ # Include BL specific makefiles ################################################################################ @@ -796,7 +836,7 @@ endif # Build targets ################################################################################ -.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs +.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs memmap .SUFFIXES: all: msg_start @@ -990,6 +1030,10 @@ ${SPTOOL}: romlib.bin: libraries ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all +# Call print_memory_map tool +memmap: all + ${Q}${PYTHON} $(PRINT_MEMORY_MAP) $(BUILD_PLAT) + cscope: @echo " CSCOPE" ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files @@ -1029,6 +1073,7 @@ help: @echo " fiptool Build the Firmware Image Package (FIP) creation tool" @echo " sptool Build the Secure Partition Package creation tool" @echo " dtbs Build the Device Tree Blobs (if required for the platform)" + @echo " memmap Print the memory map of the built binaries" @echo "" @echo "Note: most build targets require PLAT to be set to a specific platform." @echo "" diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index 855add347..00f27184d 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -30,7 +30,8 @@ func bl1_entrypoint _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ - _exception_vectors=bl1_exceptions + _exception_vectors=bl1_exceptions \ + _pie_fixup_size=0 /* -------------------------------------------------------------------- * Perform BL1 setup diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index c4f6b99fc..877af8e01 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl1_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -72,8 +72,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl1_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -114,7 +114,7 @@ SECTIONS */ .data . : ALIGN(16) { __DATA_RAM_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_RAM_END__ = .; } >RAM AT>ROM @@ -131,7 +131,7 @@ SECTIONS */ .bss : ALIGN(16) { __BSS_START__ = .; - *(.bss*) + *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) __BSS_END__ = .; } >RAM diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S index 6fe2dd923..f97121ef0 100644 --- a/bl2/aarch64/bl2_el3_entrypoint.S +++ b/bl2/aarch64/bl2_el3_entrypoint.S @@ -26,7 +26,8 @@ func bl2_entrypoint _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ - _exception_vectors=bl2_el3_exceptions + _exception_vectors=bl2_el3_exceptions \ + _pie_fixup_size=0 /* --------------------------------------------- * Restore parameters of boot rom diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index 30cdf7d78..6230562ed 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl2_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -59,8 +59,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl2_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -93,7 +93,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S index 82b51a862..dc398eb02 100644 --- a/bl2/bl2_el3.ld.S +++ b/bl2/bl2_el3.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,7 +44,7 @@ SECTIONS *bl2_el3_entrypoint.o(.text*) *(.text.asm.*) __TEXT_RESIDENT_END__ = .; - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -52,7 +52,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -82,8 +82,8 @@ SECTIONS *bl2_el3_entrypoint.o(.text*) *(.text.asm.*) __TEXT_RESIDENT_END__ = .; - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* * Ensure 8-byte alignment for cpu_ops so that its fields are also @@ -135,7 +135,7 @@ SECTIONS */ .data . : { __DATA_RAM_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_RAM_END__ = .; } >RAM AT>ROM diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S index 8d4984fbf..8d257cee9 100644 --- a/bl2u/bl2u.ld.S +++ b/bl2u/bl2u.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl2u_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -44,7 +44,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >RAM @@ -52,8 +52,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl2u_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) *(.vectors) __RO_END_UNALIGNED__ = .; @@ -80,7 +80,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 1ad26e4fe..74b0993f3 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -32,17 +32,6 @@ func bl31_entrypoint mov x22, x2 mov x23, x3 - /* -------------------------------------------------------------------- - * If PIE is enabled, fixup the Global descriptor Table and dynamic - * relocations - * -------------------------------------------------------------------- - */ -#if ENABLE_PIE - mov_imm x0, BL31_BASE - mov_imm x1, BL31_LIMIT - bl fixup_gdt_reloc -#endif /* ENABLE_PIE */ - #if !RESET_TO_BL31 /* --------------------------------------------------------------------- * For !RESET_TO_BL31 systems, only the primary CPU ever reaches @@ -59,7 +48,8 @@ func bl31_entrypoint _secondary_cold_boot=0 \ _init_memory=0 \ _init_c_runtime=1 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=BL31_LIMIT - BL31_BASE #else /* --------------------------------------------------------------------- @@ -74,7 +64,8 @@ func bl31_entrypoint _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=BL31_LIMIT - BL31_BASE /* --------------------------------------------------------------------- * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so @@ -174,7 +165,8 @@ func bl31_warm_entrypoint _secondary_cold_boot=0 \ _init_memory=0 \ _init_c_runtime=0 \ - _exception_vectors=runtime_exceptions + _exception_vectors=runtime_exceptions \ + _pie_fixup_size=0 /* * We're about to enable MMU and participate in PSCI state coordination. diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index c7d587cb0..708ee329f 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -33,7 +33,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl31_entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -41,7 +41,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -87,8 +87,8 @@ SECTIONS ro . : { __RO_START__ = .; *bl31_entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); @@ -179,7 +179,7 @@ SECTIONS */ .data . : { __DATA_START__ = .; - *(.data*) + *(SORT_BY_ALIGNMENT(.data*)) __DATA_END__ = .; } >RAM @@ -211,7 +211,7 @@ SECTIONS */ .bss (NOLOAD) : ALIGN(16) { __BSS_START__ = .; - *(.bss*) + *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) #if !USE_COHERENT_MEM /* diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index fded1e0c9..051586bc3 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -196,6 +196,10 @@ Common build options builds, but this behaviour can be overridden in each platform's Makefile or in the build command line. + - ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) + support in GCC for TF-A. This option is currently only supported for + AArch64. Default is 0. + - ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM feature. MPAM is an optional Armv8.4 extension that enables various memory system components and resources to define partitions; software running at diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst index bc9e35b4f..02ff38bef 100644 --- a/docs/plat/nvidia-tegra.rst +++ b/docs/plat/nvidia-tegra.rst @@ -1,6 +1,17 @@ NVIDIA Tegra ============ +- .. rubric:: T194 + :name: t194 + +T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor +configuration. The Carmel cores support the ARM Architecture version 8.2, +executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel +processors are organized as four dual-core clusters, where each cluster has +a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects +these processor complexes and allows heterogeneous multi-processing with all +eight cores if required. + - .. rubric:: T186 :name: t186 @@ -78,9 +89,10 @@ their dispatchers in the image without changing any makefiles. These are the supported Trusted OS' by Tegra platforms. -Tegra132: TLK -Tegra210: TLK and Trusty -Tegra186: Trusty +- Tegra132: TLK +- Tegra210: TLK and Trusty +- Tegra186: Trusty +- Tegra194: Trusty Scatter files ------------- @@ -98,7 +110,7 @@ Preparing the BL31 image to run on Tegra SoCs .. code:: shell CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ - TARGET_SOC=<target-soc e.g. t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd> + TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd> bl31 Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>`` diff --git a/drivers/arm/sbsa/sbsa.c b/drivers/arm/sbsa/sbsa.c index 6f00a6019..79c6f2620 100644 --- a/drivers/arm/sbsa/sbsa.c +++ b/drivers/arm/sbsa/sbsa.c @@ -4,11 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include <plat/common/platform.h> +#include <assert.h> +#include <stdint.h> #include <drivers/arm/sbsa.h> #include <lib/mmio.h> -#include <stdint_.h> -#include <assert.h> +#include <plat/common/platform.h> void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) { diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 378e827ce..b14b7b66e 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -232,11 +232,18 @@ * * _exception_vectors: * Address of the exception vectors to program in the VBAR_EL3 register. + * + * _pie_fixup_size: + * Size of memory region to fixup Global Descriptor Table (GDT). + * + * A non-zero value is expected when firmware needs GDT to be fixed-up. + * * ----------------------------------------------------------------------------- */ .macro el3_entrypoint_common \ _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ - _init_memory, _init_c_runtime, _exception_vectors + _init_memory, _init_c_runtime, _exception_vectors, \ + _pie_fixup_size .if \_init_sctlr /* ------------------------------------------------------------- @@ -283,6 +290,26 @@ do_cold_boot: .endif /* _warm_boot_mailbox */ + .if \_pie_fixup_size +#if ENABLE_PIE + /* + * ------------------------------------------------------------ + * If PIE is enabled fixup the Global descriptor Table only + * once during primary core cold boot path. + * + * Compile time base address, required for fixup, is calculated + * using "pie_fixup" label present within first page. + * ------------------------------------------------------------ + */ + pie_fixup: + ldr x0, =pie_fixup + and x0, x0, #~(PAGE_SIZE - 1) + mov_imm x1, \_pie_fixup_size + add x1, x1, x0 + bl fixup_gdt_reloc +#endif /* ENABLE_PIE */ + .endif /* _pie_fixup_size */ + /* --------------------------------------------------------------------- * Set the exception vectors. * --------------------------------------------------------------------- diff --git a/include/lib/libc/aarch32/stddef_.h b/include/lib/libc/aarch32/stddef_.h index 1babfade3..36dc20bd4 100644 --- a/include/lib/libc/aarch32/stddef_.h +++ b/include/lib/libc/aarch32/stddef_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,4 @@ typedef unsigned int size_t; #define SIZET_ #endif -#ifndef _PTRDIFF_T -typedef long ptrdiff_t; -#define _PTRDIFF_T -#endif - #endif /* STDDEF__H */ diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h deleted file mode 100644 index 4f494859f..000000000 --- a/include/lib/libc/aarch32/stdint_.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define INT8_MAX 0x7F -#define INT8_MIN (-INT8_MAX - 1) -#define UINT8_MAX 0xFFU - -#define INT16_MAX 0x7FFF -#define INT16_MIN (-INT16_MAX - 1) -#define UINT16_MAX 0xFFFFU - -#define INT32_MAX 0x7FFFFFFF -#define INT32_MIN (-INT32_MAX - 1) -#define UINT32_MAX 0xFFFFFFFFU - -#define INT64_MAX 0x7FFFFFFFFFFFFFFFLL -#define INT64_MIN (-INT64_MAX - 1LL) -#define UINT64_MAX 0xFFFFFFFFFFFFFFFFULL - -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define UINT_LEAST8_MAX UINT8_MAX - -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define UINT_LEAST16_MAX UINT16_MAX - -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define UINT_LEAST32_MAX UINT32_MAX - -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -#define INT_FAST8_MIN INT32_MIN -#define INT_FAST8_MAX INT32_MAX -#define UINT_FAST8_MAX UINT32_MAX - -#define INT_FAST16_MIN INT32_MIN -#define INT_FAST16_MAX INT32_MAX -#define UINT_FAST16_MAX UINT32_MAX - -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define UINT_FAST32_MAX UINT32_MAX - -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST64_MAX UINT64_MAX - -#define INTPTR_MIN INT32_MIN -#define INTPTR_MAX INT32_MAX -#define UINTPTR_MAX UINT32_MAX - -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -#define PTRDIFF_MIN INT32_MIN -#define PTRDIFF_MAX INT32_MAX - -#define SIZE_MAX UINT32_MAX - -#define INT8_C(x) x -#define INT16_C(x) x -#define INT32_C(x) x -#define INT64_C(x) x ## LL - -#define UINT8_C(x) x -#define UINT16_C(x) x -#define UINT32_C(x) x ## U -#define UINT64_C(x) x ## ULL - -#define INTMAX_C(x) x ## LL -#define UINTMAX_C(x) x ## ULL - -typedef signed char int8_t; -typedef short int16_t; -typedef int int32_t; -typedef long long int64_t; - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; - -typedef signed char int8_least_t; -typedef short int16_least_t; -typedef int int32_least_t; -typedef long long int64_least_t; - -typedef unsigned char uint8_least_t; -typedef unsigned short uint16_least_t; -typedef unsigned int uint32_least_t; -typedef unsigned long long uint64_least_t; - -typedef int int8_fast_t; -typedef int int16_fast_t; -typedef int int32_fast_t; -typedef long long int64_fast_t; - -typedef unsigned int uint8_fast_t; -typedef unsigned int uint16_fast_t; -typedef unsigned int uint32_fast_t; -typedef unsigned long long uint64_fast_t; - -typedef long intptr_t; -typedef unsigned long uintptr_t; - -typedef long long intmax_t; -typedef unsigned long long uintmax_t; - -typedef long register_t; -typedef unsigned long u_register_t; diff --git a/include/lib/libc/aarch32/stdio_.h b/include/lib/libc/aarch32/stdio_.h index 50d3cc2ed..5e49425cb 100644 --- a/include/lib/libc/aarch32/stdio_.h +++ b/include/lib/libc/aarch32/stdio_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,6 @@ #ifndef STDIO__H #define STDIO__H -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - #ifndef SSIZET_ typedef int ssize_t; #define SSIZET_ diff --git a/include/lib/libc/aarch32/stdlib_.h b/include/lib/libc/aarch32/stdlib_.h deleted file mode 100644 index 9c07857a5..000000000 --- a/include/lib/libc/aarch32/stdlib_.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STDLIB__H -#define STDLIB__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -#define EXIT_FAILURE 1 -#define EXIT_SUCCESS 0 - -#endif /* STDLIB__H */ diff --git a/include/lib/libc/aarch32/string_.h b/include/lib/libc/aarch32/string_.h deleted file mode 100644 index 4e139b0db..000000000 --- a/include/lib/libc/aarch32/string_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STRING__H -#define STRING__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -#endif /* STRING__H */ diff --git a/include/lib/libc/aarch32/time_.h b/include/lib/libc/aarch32/time_.h deleted file mode 100644 index a9169c293..000000000 --- a/include/lib/libc/aarch32/time_.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TIME__H -#define TIME__H - -#ifndef SIZET_ -typedef unsigned int size_t; -#define SIZET_ -#endif - -typedef long int time_t; - -#endif /* TIME__H */ diff --git a/include/lib/libc/aarch64/stddef_.h b/include/lib/libc/aarch64/stddef_.h index b7d8209af..6ecc6067c 100644 --- a/include/lib/libc/aarch64/stddef_.h +++ b/include/lib/libc/aarch64/stddef_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,4 @@ typedef unsigned long size_t; #define SIZET_ #endif -#ifndef _PTRDIFF_T -typedef long ptrdiff_t; -#define _PTRDIFF_T -#endif - #endif /* STDDEF__H */ diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h deleted file mode 100644 index b17a435b0..000000000 --- a/include/lib/libc/aarch64/stdint_.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define INT8_MAX 0x7F -#define INT8_MIN (-INT8_MAX - 1) -#define UINT8_MAX 0xFFU - -#define INT16_MAX 0x7FFF -#define INT16_MIN (-INT16_MAX - 1) -#define UINT16_MAX 0xFFFFU - -#define INT32_MAX 0x7FFFFFFF -#define INT32_MIN (-INT32_MAX - 1) -#define UINT32_MAX 0xFFFFFFFFU - -#define INT64_MAX 0x7FFFFFFFFFFFFFFFLL -#define INT64_MIN (-INT64_MAX - 1LL) -#define UINT64_MAX 0xFFFFFFFFFFFFFFFFULL - -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define UINT_LEAST8_MAX UINT8_MAX - -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define UINT_LEAST16_MAX UINT16_MAX - -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define UINT_LEAST32_MAX UINT32_MAX - -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -#define INT_FAST8_MIN INT32_MIN -#define INT_FAST8_MAX INT32_MAX -#define UINT_FAST8_MAX UINT32_MAX - -#define INT_FAST16_MIN INT32_MIN -#define INT_FAST16_MAX INT32_MAX -#define UINT_FAST16_MAX UINT32_MAX - -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define UINT_FAST32_MAX UINT32_MAX - -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST64_MAX UINT64_MAX - -#define INTPTR_MIN INT64_MIN -#define INTPTR_MAX INT64_MAX -#define UINTPTR_MAX UINT64_MAX - -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -#define PTRDIFF_MIN INT64_MIN -#define PTRDIFF_MAX INT64_MAX - -#define SIZE_MAX UINT64_MAX - -#define INT8_C(x) x -#define INT16_C(x) x -#define INT32_C(x) x -#define INT64_C(x) x ## LL - -#define UINT8_C(x) x -#define UINT16_C(x) x -#define UINT32_C(x) x ## U -#define UINT64_C(x) x ## ULL - -#define INTMAX_C(x) x ## L -#define UINTMAX_C(x) x ## ULL - -typedef signed char int8_t; -typedef short int16_t; -typedef int int32_t; -typedef long long int64_t; - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; - -typedef signed char int8_least_t; -typedef short int16_least_t; -typedef int int32_least_t; -typedef long long int64_least_t; - -typedef unsigned char uint8_least_t; -typedef unsigned short uint16_least_t; -typedef unsigned int uint32_least_t; -typedef unsigned long long uint64_least_t; - -typedef int int8_fast_t; -typedef int int16_fast_t; -typedef int int32_fast_t; -typedef long long int64_fast_t; - -typedef unsigned int uint8_fast_t; -typedef unsigned int uint16_fast_t; -typedef unsigned int uint32_fast_t; -typedef unsigned long long uint64_fast_t; - -typedef long intptr_t; -typedef unsigned long uintptr_t; - -typedef long intmax_t; -typedef unsigned long uintmax_t; - -typedef long register_t; -typedef unsigned long u_register_t; - -typedef __int128 int128_t; -typedef unsigned __int128 uint128_t; diff --git a/include/lib/libc/aarch64/stdio_.h b/include/lib/libc/aarch64/stdio_.h index 09b0172dd..afaeadc21 100644 --- a/include/lib/libc/aarch64/stdio_.h +++ b/include/lib/libc/aarch64/stdio_.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,6 @@ #ifndef STDIO__H #define STDIO__H -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - #ifndef SSIZET_ typedef long ssize_t; #define SSIZET_ diff --git a/include/lib/libc/aarch64/stdlib_.h b/include/lib/libc/aarch64/stdlib_.h deleted file mode 100644 index 81a39d14a..000000000 --- a/include/lib/libc/aarch64/stdlib_.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STDLIB__H -#define STDLIB__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -#define EXIT_FAILURE 1 -#define EXIT_SUCCESS 0 - -#endif /* STDLIB__H */ diff --git a/include/lib/libc/aarch64/string_.h b/include/lib/libc/aarch64/string_.h deleted file mode 100644 index 71c51a6cd..000000000 --- a/include/lib/libc/aarch64/string_.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STRING__H -#define STRING__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -#endif /* STRING__H */ diff --git a/include/lib/libc/aarch64/time_.h b/include/lib/libc/aarch64/time_.h deleted file mode 100644 index 68ab1b8dd..000000000 --- a/include/lib/libc/aarch64/time_.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef TIME__H -#define TIME__H - -#ifndef SIZET_ -typedef unsigned long size_t; -#define SIZET_ -#endif - -typedef long int time_t; - -#endif /* TIME__H */ diff --git a/include/lib/libc/stddef.h b/include/lib/libc/stddef.h index c9957bdb1..58a519e52 100644 --- a/include/lib/libc/stddef.h +++ b/include/lib/libc/stddef.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -13,6 +13,11 @@ #include <stddef_.h> +#ifndef _PTRDIFF_T +typedef long ptrdiff_t; +#define _PTRDIFF_T +#endif + #ifndef NULL #define NULL ((void *) 0) #endif diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h index d44a973f1..80b3e965d 100644 --- a/include/lib/libc/stdint.h +++ b/include/lib/libc/stdint.h @@ -4,13 +4,135 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef STDINT_H #define STDINT_H -#include <stdint_.h> +#include <limits.h> + +#define INT8_MAX CHAR_MAX +#define INT8_MIN CHAR_MIN +#define UINT8_MAX UCHAR_MAX + +#define INT16_MAX SHRT_MAX +#define INT16_MIN SHRT_MIN +#define UINT16_MAX USHRT_MAX + +#define INT32_MAX INT_MAX +#define INT32_MIN INT_MIN +#define UINT32_MAX UINT_MAX + +#define INT64_MAX LLONG_MAX +#define INT64_MIN LLONG_MIN +#define UINT64_MAX ULLONG_MAX + +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST8_MAX INT8_MAX +#define UINT_LEAST8_MAX UINT8_MAX + +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST16_MAX INT16_MAX +#define UINT_LEAST16_MAX UINT16_MAX + +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST32_MAX INT32_MAX +#define UINT_LEAST32_MAX UINT32_MAX + +#define INT_LEAST64_MIN INT64_MIN +#define INT_LEAST64_MAX INT64_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST8_MAX INT32_MAX +#define UINT_FAST8_MAX UINT32_MAX + +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST16_MAX INT32_MAX +#define UINT_FAST16_MAX UINT32_MAX + +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST32_MAX INT32_MAX +#define UINT_FAST32_MAX UINT32_MAX + +#define INT_FAST64_MIN INT64_MIN +#define INT_FAST64_MAX INT64_MAX +#define UINT_FAST64_MAX UINT64_MAX + +#define INTPTR_MIN LONG_MIN +#define INTPTR_MAX LONG_MAX +#define UINTPTR_MAX ULONG_MAX + +#define INTMAX_MIN LLONG_MIN +#define INTMAX_MAX LLONG_MAX +#define UINTMAX_MAX ULLONG_MAX + +#define PTRDIFF_MIN LONG_MIN +#define PTRDIFF_MAX LONG_MAX + +#define SIZE_MAX UINT64_MAX + +#define INT8_C(x) x +#define INT16_C(x) x +#define INT32_C(x) x +#define INT64_C(x) x ## LL + +#define UINT8_C(x) x +#define UINT16_C(x) x +#define UINT32_C(x) x ## U +#define UINT64_C(x) x ## ULL + +#define INTMAX_C(x) x ## LL +#define UINTMAX_C(x) x ## ULL + +typedef signed char int8_t; +typedef short int16_t; +typedef int int32_t; +typedef long long int64_t; + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; + +typedef signed char int8_least_t; +typedef short int16_least_t; +typedef int int32_least_t; +typedef long long int64_least_t; + +typedef unsigned char uint8_least_t; +typedef unsigned short uint16_least_t; +typedef unsigned int uint32_least_t; +typedef unsigned long long uint64_least_t; + +typedef int int8_fast_t; +typedef int int16_fast_t; +typedef int int32_fast_t; +typedef long long int64_fast_t; + +typedef unsigned int uint8_fast_t; +typedef unsigned int uint16_fast_t; +typedef unsigned int uint32_fast_t; +typedef unsigned long long uint64_fast_t; + +typedef long intptr_t; +typedef unsigned long uintptr_t; + +/* +* Conceptually, these are supposed to be the largest integers representable in C, +* but GCC and Clang define them as long long for compatibility. +*/ +typedef long long intmax_t; +typedef unsigned long long uintmax_t; + +typedef long register_t; +typedef unsigned long u_register_t; + +#ifdef __aarch64__ +typedef __int128 int128_t; +typedef unsigned __int128 uint128_t; +#endif /* __aarch64__ */ #endif /* STDINT_H */ diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h index 3d9323efa..2d9e6557b 100644 --- a/include/lib/libc/stdio.h +++ b/include/lib/libc/stdio.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ @@ -12,12 +12,9 @@ #define STDIO_H #include <cdefs.h> +#include <stddef.h> #include <stdio_.h> -#ifndef NULL -#define NULL ((void *) 0) -#endif - #define EOF -1 int printf(const char *fmt, ...) __printflike(1, 2); diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h index edd6265f5..24e7bae2f 100644 --- a/include/lib/libc/stdlib.h +++ b/include/lib/libc/stdlib.h @@ -4,18 +4,17 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef STDLIB_H #define STDLIB_H -#include <stdlib_.h> +#include <stddef.h> -#ifndef NULL -#define NULL ((void *) 0) -#endif +#define EXIT_FAILURE 1 +#define EXIT_SUCCESS 0 #define _ATEXIT_MAX 1 diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h index ee6eeacef..71774b0c8 100644 --- a/include/lib/libc/string.h +++ b/include/lib/libc/string.h @@ -4,18 +4,14 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef STRING_H #define STRING_H -#include <string_.h> - -#ifndef NULL -#define NULL ((void *) 0) -#endif +#include <stddef.h> void *memcpy(void *dst, const void *src, size_t len); void *memmove(void *dst, const void *src, size_t len); @@ -23,6 +19,7 @@ int memcmp(const void *s1, const void *s2, size_t len); int strcmp(const char *s1, const char *s2); int strncmp(const char *s1, const char *s2, size_t n); void *memchr(const void *src, int c, size_t len); +void *memrchr(const void *src, int c, size_t len); char *strchr(const char *s, int c); void *memset(void *dst, int val, size_t count); size_t strlen(const char *s); diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h index 71d3e7ec9..c1c95e586 100644 --- a/include/lib/libc/time.h +++ b/include/lib/libc/time.h @@ -4,17 +4,15 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, ARM Limited and Contributors. * All rights reserved. */ #ifndef TIME_H #define TIME_H -#include <time_.h> +#include <stddef.h> -#ifndef NULL -#define NULL ((void *) 0) -#endif +typedef long int time_t; #endif /* TIME_H */ diff --git a/include/plat/arm/common/arm_reclaim_init.ld.S b/include/plat/arm/common/arm_reclaim_init.ld.S index 8f22170fe..b5bf47365 100644 --- a/include/plat/arm/common/arm_reclaim_init.ld.S +++ b/include/plat/arm/common/arm_reclaim_init.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,10 +27,9 @@ SECTIONS "BL31 init has exceeded progbits limit.") #endif -#if RECLAIM_INIT_CODE ASSERT(__INIT_CODE_END__ <= __STACKS_END__, "Init code ends past the end of the stacks") -#endif + } #endif /* ARM_RECLAIM_INIT_LD_S */ diff --git a/lib/libc/libc.mk b/lib/libc/libc.mk index e1b5560f8..93d30d035 100644 --- a/lib/libc/libc.mk +++ b/lib/libc/libc.mk @@ -12,6 +12,7 @@ LIBC_SRCS := $(addprefix lib/libc/, \ memcmp.c \ memcpy.c \ memmove.c \ + memrchr.c \ memset.c \ printf.c \ putchar.c \ diff --git a/lib/libc/memrchr.c b/lib/libc/memrchr.c new file mode 100644 index 000000000..01caef3ae --- /dev/null +++ b/lib/libc/memrchr.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <string.h> + +#undef memrchr + +void *memrchr(const void *src, int c, size_t len) +{ + const unsigned char *s = src + (len - 1); + + while (len--) { + if (*s == (unsigned char)c) { + return (void*) s; + } + + s--; + } + + return NULL; +} diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 7c42be7e5..ea1a01de9 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -43,6 +43,7 @@ const spd_pm_ops_t *psci_spd_pm; static plat_local_state_t psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; +unsigned int psci_plat_core_count; /******************************************************************************* * Arrays that hold the platform's power domain tree information for state @@ -161,7 +162,7 @@ unsigned int psci_is_last_on_cpu(void) { unsigned int cpu_idx, my_idx = plat_my_core_pos(); - for (cpu_idx = 0; cpu_idx < (unsigned int)PLATFORM_CORE_COUNT; + for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { if (cpu_idx == my_idx) { assert(psci_get_aff_info_state() == AFF_STATE_ON); @@ -208,7 +209,7 @@ static void psci_set_req_local_pwr_state(unsigned int pwrlvl, { assert(pwrlvl > PSCI_CPU_PWR_LVL); if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && - (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) { + (cpu_idx < psci_plat_core_count)) { psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state; } } @@ -220,10 +221,10 @@ void __init psci_init_req_local_pwr_states(void) { /* Initialize the requested state of all non CPU power domains as OFF */ unsigned int pwrlvl; - int core; + unsigned int core; for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) { - for (core = 0; core < PLATFORM_CORE_COUNT; core++) { + for (core = 0; core < psci_plat_core_count; core++) { psci_req_local_pwr_states[pwrlvl][core] = PLAT_MAX_OFF_STATE; } @@ -244,7 +245,7 @@ static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, assert(pwrlvl > PSCI_CPU_PWR_LVL); if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && - (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) { + (cpu_idx < psci_plat_core_count)) { return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx]; } else return NULL; @@ -888,7 +889,7 @@ int psci_spd_migrate_info(u_register_t *mpidr) void psci_print_power_domain_map(void) { #if LOG_LEVEL >= LOG_LEVEL_INFO - int idx; + unsigned int idx; plat_local_state_t state; plat_local_state_type_t state_type; @@ -900,7 +901,7 @@ void psci_print_power_domain_map(void) }; INFO("PSCI Power Domain Map:\n"); - for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT); + for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count); idx++) { state_type = find_local_state_type( psci_non_cpu_pd_nodes[idx].local_state); @@ -912,7 +913,7 @@ void psci_print_power_domain_map(void) psci_non_cpu_pd_nodes[idx].local_state); } - for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) { + for (idx = 0; idx < psci_plat_core_count; idx++) { state = psci_get_cpu_local_state_by_idx(idx); state_type = find_local_state_type(state); INFO(" CPU Node : MPID 0x%llx, parent_node %d," diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index b49847c95..0f25e6563 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h @@ -251,6 +251,7 @@ extern const plat_psci_ops_t *psci_plat_pm_ops; extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; extern unsigned int psci_caps; +extern unsigned int psci_plat_core_count; /******************************************************************************* * SPD's power management hooks registered with PSCI diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index 853f9157c..becb54709 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c @@ -84,11 +84,12 @@ static void __init psci_init_pwr_domain_node(unsigned char node_idx, *******************************************************************************/ static void __init psci_update_pwrlvl_limits(void) { - int j, cpu_idx; + unsigned int cpu_idx; + int j; unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; unsigned int temp_index[PLAT_MAX_PWR_LVL]; - for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { + for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { psci_get_parent_pwr_domain_nodes(cpu_idx, (unsigned int)PLAT_MAX_PWR_LVL, temp_index); @@ -109,7 +110,8 @@ static void __init psci_update_pwrlvl_limits(void) * informs the number of root power domains. The parent nodes of the root nodes * will point to an invalid entry(-1). ******************************************************************************/ -static void __init populate_power_domain_tree(const unsigned char *topology) +static unsigned int __init populate_power_domain_tree(const unsigned char + *topology) { unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl; unsigned int node_index = 0U, num_children; @@ -160,7 +162,8 @@ static void __init populate_power_domain_tree(const unsigned char *topology) } /* Validate the sanity of array exported by the platform */ - assert((int) j == PLATFORM_CORE_COUNT); + assert(j <= (unsigned int)PLATFORM_CORE_COUNT); + return j; } /******************************************************************************* @@ -199,7 +202,7 @@ int __init psci_setup(const psci_lib_args_t *lib_args) topology_tree = plat_get_power_domain_tree_desc(); /* Populate the power domain arrays using the platform topology map */ - populate_power_domain_tree(topology_tree); + psci_plat_core_count = populate_power_domain_tree(topology_tree); /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ psci_update_pwrlvl_limits(); diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index b89d87ea6..47f3ebd86 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -236,7 +236,7 @@ $(eval BL_CFLAGS := $(BL$(call uppercase,$(3))_CFLAGS)) $(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs $$(ECHO) " CC $$<" - $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@ + $$(Q)$$(CC) $$(LTO_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@ -include $(DEP) @@ -433,6 +433,10 @@ ifneq ($(findstring armlink,$(notdir $(LD))),) --map --list="$(MAPFILE)" --scatter=${PLAT_DIR}/scat/bl${1}.scat \ $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) \ $(BUILD_DIR)/build_message.o $(OBJS) +else ifneq ($(findstring gcc,$(notdir $(LD))),) + $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) -Wl,-Map=$(MAPFILE) \ + -Wl,-T$(LINKERFILE) $(BUILD_DIR)/build_message.o \ + $(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) else $$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) -Map=$(MAPFILE) \ --script $(LINKERFILE) $(BUILD_DIR)/build_message.o \ diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index b7fb173b1..348b3e52b 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -239,3 +239,6 @@ SANITIZE_UB := off # implementation variant using the ARMv8.1-LSE compare-and-swap instruction. # Default: disabled USE_SPINLOCK_CAS := 0 + +# Enable Link Time Optimization +ENABLE_LTO := 0 diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 07a37167f..d48ff56dc 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -191,6 +191,7 @@ static const struct axp_regulator { {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3}, {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5}, + {"dldo4", 700, 3300, 100, NO_SPLIT, 0x18, 0x12, 6}, {"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2}, {} }; diff --git a/plat/arm/board/fvp/include/plat.ld.S b/plat/arm/board/fvp/include/plat.ld.S index f024f551a..7c8bf0655 100644 --- a/plat/arm/board/fvp/include/plat.ld.S +++ b/plat/arm/board/fvp/include/plat.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,9 @@ #define PLAT_LD_S #include <plat/arm/common/arm_tzc_dram.ld.S> + +#if RECLAIM_INIT_CODE #include <plat/arm/common/arm_reclaim_init.ld.S> +#endif /* RECLAIM_INIT_CODE */ #endif /* PLAT_LD_S */ diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c index 9a5364952..aafb190d5 100644 --- a/plat/arm/common/arm_dyn_cfg.c +++ b/plat/arm/common/arm_dyn_cfg.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> #include <string.h> +#include <libfdt.h> #include <platform_def.h> @@ -21,8 +22,6 @@ /* Variable to store the address to TB_FW_CONFIG passed from BL1 */ static void *tb_fw_cfg_dtb; -static size_t tb_fw_cfg_dtb_size; - #if TRUSTED_BOARD_BOOT @@ -110,7 +109,7 @@ void arm_bl1_set_mbedtls_heap(void) * without the heap info. */ flush_dcache_range((uintptr_t)tb_fw_cfg_dtb, - tb_fw_cfg_dtb_size); + fdt_totalsize(tb_fw_cfg_dtb)); } } @@ -146,7 +145,6 @@ void arm_load_tb_fw_config(void) /* At this point we know that a DTB is indeed available */ config_base = arm_tb_fw_info.image_info.image_base; tb_fw_cfg_dtb = (void *)config_base; - tb_fw_cfg_dtb_size = (size_t)arm_tb_fw_info.image_info.image_max_size; /* The BL2 ep_info arg0 is modified to point to TB_FW_CONFIG */ desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); diff --git a/plat/imx/common/include/imx_caam.h b/plat/imx/common/include/imx_caam.h index 335bd0f8b..61005b51c 100644 --- a/plat/imx/common/include/imx_caam.h +++ b/plat/imx/common/include/imx_caam.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef IMX_CAAM_H #define IMX_CAAM_H +#include <cdefs.h> #include <stdint.h> #include <arch.h> #include <imx_regs.h> diff --git a/plat/imx/common/include/imx_snvs.h b/plat/imx/common/include/imx_snvs.h index 0b3d1085f..565c451dd 100644 --- a/plat/imx/common/include/imx_snvs.h +++ b/plat/imx/common/include/imx_snvs.h @@ -1,11 +1,12 @@ /* - * Copyright (C) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (C) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef IMX_SNVS_H #define IMX_SNVS_H +#include <cdefs.h> #include <stdint.h> #include <arch.h> diff --git a/plat/imx/common/include/sci/sci_ipc.h b/plat/imx/common/include/sci/sci_ipc.h index 1167ea367..39e9012bc 100644 --- a/plat/imx/common/include/sci/sci_ipc.h +++ b/plat/imx/common/include/sci/sci_ipc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,6 +62,6 @@ void sc_ipc_read(sc_ipc_t ipc, void *data); */ void sc_ipc_write(sc_ipc_t ipc, void *data); -sc_ipc_t ipc_handle; +extern sc_ipc_t ipc_handle; #endif /* SCI_IPC_H */ diff --git a/plat/imx/common/sci/ipc.c b/plat/imx/common/sci/ipc.c index 6491ca575..576911925 100644 --- a/plat/imx/common/sci/ipc.c +++ b/plat/imx/common/sci/ipc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,8 @@ #include <sci/sci_rpc.h> #include "imx8_mu.h" +sc_ipc_t ipc_handle; + DEFINE_BAKERY_LOCK(sc_ipc_bakery_lock); #define sc_ipc_lock_init() bakery_lock_init(&sc_ipc_bakery_lock) #define sc_ipc_lock() bakery_lock_get(&sc_ipc_bakery_lock) diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index e9ab92850..86b7ab88f 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -14,20 +14,17 @@ #include <drivers/synopsys/dw_mmc.h> #include <drivers/ti/uart/uart_16550.h> #include <lib/xlat_tables/xlat_tables.h> -#include <platform_def.h> -#include <socfpga_private.h> #include "agilex_clock_manager.h" -#include "agilex_handoff.h" -#include "agilex_mailbox.h" #include "agilex_memory_controller.h" #include "agilex_pinmux.h" -#include "agilex_private.h" #include "agilex_reset_manager.h" #include "agilex_system_manager.h" - #include "ccu/ncore_ccu.h" #include "qspi/cadence_qspi.h" +#include "socfpga_handoff.h" +#include "socfpga_mailbox.h" +#include "socfpga_private.h" #include "wdt/watchdog.h" @@ -59,7 +56,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, generic_delay_timer_init(); - if (agilex_get_handoff(&reverse_handoff_ptr)) + if (socfpga_get_handoff(&reverse_handoff_ptr)) return; config_pinmux(&reverse_handoff_ptr); boot_source = reverse_handoff_ptr.boot_source; diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index c8765e857..375483dd4 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -12,7 +12,6 @@ #include <drivers/arm/gicv2.h> #include <drivers/ti/uart/uart_16550.h> #include <lib/xlat_tables/xlat_tables.h> -#include <platform_def.h> static entry_point_info_t bl32_image_ep_info; @@ -67,15 +66,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, } static const interrupt_prop_t s10_interrupt_props[] = { - PLAT_INTEL_AGX_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), - PLAT_INTEL_AGX_G0_IRQ_PROPS(GICV2_INTR_GROUP0) + PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), + PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) }; static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; static const gicv2_driver_data_t plat_gicv2_gic_data = { - .gicd_base = PLAT_INTEL_AGX_GICD_BASE, - .gicc_base = PLAT_INTEL_AGX_GICC_BASE, + .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, + .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, .interrupt_props = s10_interrupt_props, .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), .target_masks = target_mask_array, @@ -104,7 +103,7 @@ const mmap_region_t plat_agilex_mmap[] = { MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), - {0}, + {0} }; /******************************************************************************* @@ -126,7 +125,7 @@ void bl31_plat_arch_setup(void) BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE), #endif - {0}, + {0} }; setup_page_tables(bl_regions, plat_agilex_mmap); diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h index 0822290aa..8af6a60bc 100644 --- a/plat/intel/soc/agilex/include/agilex_clock_manager.h +++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h @@ -7,7 +7,7 @@ #ifndef CLOCKMANAGER_H #define CLOCKMANAGER_H -#include "agilex_handoff.h" +#include "socfpga_handoff.h" /* Clock Manager Registers */ #define CLKMGR_OFFSET 0xffd10000 diff --git a/plat/intel/soc/agilex/include/agilex_pinmux.h b/plat/intel/soc/agilex/include/agilex_pinmux.h index e6a7b341d..fe01062c0 100644 --- a/plat/intel/soc/agilex/include/agilex_pinmux.h +++ b/plat/intel/soc/agilex/include/agilex_pinmux.h @@ -12,7 +12,7 @@ #define AGX_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300 #define AGX_PINMUX_IO0_DELAY 0xffd13400 -#include "agilex_handoff.h" +#include "socfpga_handoff.h" void config_pinmux(handoff *handoff); diff --git a/plat/intel/soc/agilex/include/agilex_private.h b/plat/intel/soc/agilex/include/agilex_private.h deleted file mode 100644 index fc0e9fddf..000000000 --- a/plat/intel/soc/agilex/include/agilex_private.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AGX_PRIVATE_H -#define AGX_PRIVATE_H - -#define AGX_MMC_REG_BASE 0xff808000 - -#define EMMC_DESC_SIZE (1<<20) -#define EMMC_INIT_PARAMS(base, clk) \ - { .bus_width = MMC_BUS_WIDTH_4, \ - .clk_rate = (clk), \ - .desc_base = (base), \ - .desc_size = EMMC_DESC_SIZE, \ - .flags = 0, \ - .reg_base = AGX_MMC_REG_BASE \ - } - -typedef enum { - BOOT_SOURCE_FPGA = 0, - BOOT_SOURCE_SDMMC, - BOOT_SOURCE_NAND, - BOOT_SOURCE_RSVD, - BOOT_SOURCE_QSPI -} boot_source_type; - -void enable_nonsecure_access(void); -void socfpga_io_setup(int boot_source); - -#endif diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h new file mode 100644 index 000000000..a346cb5f8 --- /dev/null +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SOCFPGA_DEF_H +#define PLAT_SOCFPGA_DEF_H + +#include <platform_def.h> + +/* Platform Setting */ +#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX + +/* Register Mapping */ +#define SOCFPGA_MMC_REG_BASE 0xff808000 + +#define SOCFPGA_RSTMGR_OFST 0xffd11000 +#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020 + +#endif /* PLAT_SOCFPGA_DEF_H */ + diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index d1ea62915..ef02a8dfb 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -4,7 +4,7 @@ # # SPDX-License-Identifier: BSD-3-Clause # -# + PLAT_INCLUDES := \ -Iplat/intel/soc/agilex/include/ \ -Iplat/intel/soc/common/drivers/ \ @@ -25,48 +25,41 @@ PLAT_BL_COMMON_SOURCES := \ BL2_SOURCES += \ common/desc_image_load.c \ - drivers/partition/partition.c \ - drivers/partition/gpt.c \ - drivers/arm/pl061/pl061_gpio.c \ drivers/mmc/mmc.c \ - drivers/synopsys/emmc/dw_mmc.c \ + drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ drivers/io/io_storage.c \ drivers/io/io_block.c \ drivers/io/io_fip.c \ - drivers/gpio/gpio.c \ - drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ + drivers/partition/partition.c \ + drivers/partition/gpt.c \ + drivers/synopsys/emmc/dw_mmc.c \ lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/agilex/bl2_plat_setup.c \ - plat/intel/soc/agilex/socfpga_storage.c \ - plat/intel/soc/common/bl2_plat_mem_params_desc.c \ - plat/intel/soc/agilex/soc/agilex_reset_manager.c \ - plat/intel/soc/agilex/soc/agilex_handoff.c \ plat/intel/soc/agilex/soc/agilex_clock_manager.c \ - plat/intel/soc/agilex/soc/agilex_pinmux.c \ plat/intel/soc/agilex/soc/agilex_memory_controller.c \ + plat/intel/soc/agilex/soc/agilex_pinmux.c \ + plat/intel/soc/agilex/soc/agilex_reset_manager.c \ + plat/intel/soc/agilex/soc/agilex_system_manager.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ plat/intel/soc/common/socfpga_image_load.c \ - plat/intel/soc/agilex/soc/agilex_system_manager.c \ - plat/intel/soc/agilex/soc/agilex_mailbox.c \ + plat/intel/soc/common/socfpga_storage.c \ + plat/intel/soc/common/soc/socfpga_handoff.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c \ plat/intel/soc/common/drivers/ccu/ncore_ccu.c BL31_SOURCES += \ drivers/arm/cci/cci.c \ - lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ - plat/intel/soc/agilex/socfpga_sip_svc.c \ plat/intel/soc/agilex/bl31_plat_setup.c \ - plat/intel/soc/agilex/socfpga_psci.c \ + plat/intel/soc/common/socfpga_psci.c \ + plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/common/socfpga_topology.c \ - plat/intel/soc/common/socfpga_delay_timer.c \ - plat/intel/soc/agilex/soc/agilex_reset_manager.c \ - plat/intel/soc/agilex/soc/agilex_pinmux.c \ - plat/intel/soc/agilex/soc/agilex_clock_manager.c \ - plat/intel/soc/agilex/soc/agilex_handoff.c \ - plat/intel/soc/agilex/soc/agilex_mailbox.c + plat/intel/soc/common/soc/socfpga_mailbox.c \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c index 06891ff93..96b669cfd 100644 --- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c @@ -11,8 +11,8 @@ #include <lib/mmio.h> #include "agilex_clock_manager.h" -#include "agilex_handoff.h" #include "agilex_system_manager.h" +#include "socfpga_handoff.h" uint32_t wait_pll_lock(void) diff --git a/plat/intel/soc/common/aarch64/platform_common.c b/plat/intel/soc/common/aarch64/platform_common.c index 6d3d817d6..b79a63c86 100644 --- a/plat/intel/soc/common/aarch64/platform_common.c +++ b/plat/intel/soc/common/aarch64/platform_common.c @@ -8,7 +8,8 @@ #include <arch_helpers.h> #include <platform_def.h> #include <plat/common/platform.h> -#include <socfpga_private.h> + +#include "socfpga_private.h" unsigned int plat_get_syscnt_freq2(void) diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c index ac8218ecd..fce816b65 100644 --- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c +++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c @@ -10,7 +10,6 @@ #include <lib/mmio.h> #include "ncore_ccu.h" -#include <platform_def.h> uint32_t poll_active_bit(uint32_t dir); diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c index 0fd11ec78..d7cd71bec 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c @@ -13,7 +13,6 @@ #include <drivers/console.h> #include "cadence_qspi.h" -#include <platform_def.h> #define LESS(a, b) (((a) < (b)) ? (a) : (b)) #define MORE(a, b) (((a) > (b)) ? (a) : (b)) diff --git a/plat/intel/soc/common/drivers/wdt/watchdog.c b/plat/intel/soc/common/drivers/wdt/watchdog.c index 0f89b4fd3..651189b12 100644 --- a/plat/intel/soc/common/drivers/wdt/watchdog.c +++ b/plat/intel/soc/common/drivers/wdt/watchdog.c @@ -6,7 +6,6 @@ #include <common/debug.h> #include <lib/mmio.h> -#include <platform_def.h> #include "watchdog.h" diff --git a/plat/intel/soc/agilex/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 277862a30..e57aafb6a 100644 --- a/plat/intel/soc/agilex/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -13,6 +13,8 @@ #include <common/tbbr/tbbr_img_def.h> #include <plat/common/common_def.h> +#define PLAT_SOCFPGA_STRATIX10 1 +#define PLAT_SOCFPGA_AGILEX 2 #define PLAT_CPUID_RELEASE 0xffe1b000 #define PLAT_SEC_ENTRY 0xffe1b008 @@ -27,7 +29,7 @@ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 -/* Agilex supports up to 124GB RAM */ +/* SoCFPGA supports up to 124GB RAM */ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) @@ -56,18 +58,18 @@ /* Interrupt related constant */ -#define INTEL_AGX_IRQ_SEC_PHY_TIMER 29 +#define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 -#define INTEL_AGX_IRQ_SEC_SGI_0 8 -#define INTEL_AGX_IRQ_SEC_SGI_1 9 -#define INTEL_AGX_IRQ_SEC_SGI_2 10 -#define INTEL_AGX_IRQ_SEC_SGI_3 11 -#define INTEL_AGX_IRQ_SEC_SGI_4 12 -#define INTEL_AGX_IRQ_SEC_SGI_5 13 -#define INTEL_AGX_IRQ_SEC_SGI_6 14 -#define INTEL_AGX_IRQ_SEC_SGI_7 15 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 -#define TSP_IRQ_SEC_PHY_TIMER INTEL_AGX_IRQ_SEC_PHY_TIMER +#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER #define TSP_SEC_MEM_BASE BL32_BASE #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) /******************************************************************************* @@ -158,35 +160,35 @@ #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) #define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) -#define PLAT_INTEL_AGX_GICD_BASE PLAT_GICD_BASE -#define PLAT_INTEL_AGX_GICC_BASE PLAT_GICC_BASE +#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE +#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE /* * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 * terminology. On a GICv2 system or mode, the lists will be merged and treated * as Group 0 interrupts. */ -#define PLAT_INTEL_AGX_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE) - -#define PLAT_INTEL_AGX_G0_IRQ_PROPS(grp) +#define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) + +#define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) #define MAX_IO_HANDLES 4 #define MAX_IO_DEVICES 4 diff --git a/plat/intel/soc/agilex/include/agilex_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h index 201640611..889d13767 100644 --- a/plat/intel/soc/agilex/include/agilex_handoff.h +++ b/plat/intel/soc/common/include/socfpga_handoff.h @@ -15,6 +15,8 @@ #define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ #define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ +#include <socfpga_plat_def.h> + typedef struct handoff_t { /* header */ uint32_t header_magic; @@ -47,6 +49,44 @@ typedef struct handoff_t { uint32_t pinmux_iodelay_array[96]; /* offset, value */ /* clock configuration */ + +#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 + uint32_t clock_magic; + uint32_t clock_length; + uint32_t _pad_0x588_0x590[2]; + uint32_t main_pll_mpuclk; + uint32_t main_pll_nocclk; + uint32_t main_pll_cntr2clk; + uint32_t main_pll_cntr3clk; + uint32_t main_pll_cntr4clk; + uint32_t main_pll_cntr5clk; + uint32_t main_pll_cntr6clk; + uint32_t main_pll_cntr7clk; + uint32_t main_pll_cntr8clk; + uint32_t main_pll_cntr9clk; + uint32_t main_pll_nocdiv; + uint32_t main_pll_pllglob; + uint32_t main_pll_fdbck; + uint32_t main_pll_pllc0; + uint32_t main_pll_pllc1; + uint32_t _pad_0x5cc_0x5d0[1]; + uint32_t per_pll_cntr2clk; + uint32_t per_pll_cntr3clk; + uint32_t per_pll_cntr4clk; + uint32_t per_pll_cntr5clk; + uint32_t per_pll_cntr6clk; + uint32_t per_pll_cntr7clk; + uint32_t per_pll_cntr8clk; + uint32_t per_pll_cntr9clk; + uint32_t per_pll_emacctl; + uint32_t per_pll_gpiodiv; + uint32_t per_pll_pllglob; + uint32_t per_pll_fdbck; + uint32_t per_pll_pllc0; + uint32_t per_pll_pllc1; + uint32_t hps_osc_clk_h; + uint32_t fpga_clk_hz; +#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX uint32_t clock_magic; uint32_t clock_length; uint32_t _pad_0x588_0x590[2]; @@ -80,7 +120,7 @@ typedef struct handoff_t { uint32_t hps_osc_clk_h; uint32_t fpga_clk_hz; uint32_t _pad_0x604_0x610[3]; - +#endif /* misc configuration */ uint32_t misc_magic; uint32_t misc_length; @@ -89,7 +129,7 @@ typedef struct handoff_t { } handoff; int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); -int agilex_get_handoff(handoff *hoff_ptr); +int socfpga_get_handoff(handoff *hoff_ptr); #endif diff --git a/plat/intel/soc/agilex/include/agilex_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index cd8be2894..db4c84104 100644 --- a/plat/intel/soc/agilex/include/agilex_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef AGX_MBOX_H -#define AGX_MBOX_H +#ifndef SOCFPGA_MBOX_H +#define SOCFPGA_MBOX_H #include <lib/utils_def.h> @@ -124,4 +124,4 @@ int mailbox_read_response(int job_id, uint32_t *response); int mailbox_get_qspi_clock(void); void mailbox_reset_cold(void); -#endif +#endif /* SOCFPGA_MBOX_H */ diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h index 6ab14090f..375484443 100644 --- a/plat/intel/soc/common/include/socfpga_private.h +++ b/plat/intel/soc/common/include/socfpga_private.h @@ -4,12 +4,38 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef PLATFORM_PRIVATE_H -#define PLATFORM_PRIVATE_H +#ifndef SOCFPGA_PRIVATE_H +#define SOCFPGA_PRIVATE_H + +#include "socfpga_plat_def.h" + +#define EMMC_DESC_SIZE (1<<20) + +#define EMMC_INIT_PARAMS(base, clk) \ + { .bus_width = MMC_BUS_WIDTH_4, \ + .clk_rate = (clk), \ + .desc_base = (base), \ + .desc_size = EMMC_DESC_SIZE, \ + .flags = 0, \ + .reg_base = SOCFPGA_MMC_REG_BASE \ + } + +typedef enum { + BOOT_SOURCE_FPGA = 0, + BOOT_SOURCE_SDMMC, + BOOT_SOURCE_NAND, + BOOT_SOURCE_RSVD, + BOOT_SOURCE_QSPI +} boot_source_type; /******************************************************************************* * Function and variable prototypes ******************************************************************************/ + +void enable_nonsecure_access(void); + +void socfpga_io_setup(int boot_source); + void socfgpa_configure_mmu_el3(unsigned long total_base, unsigned long total_size, unsigned long ro_start, @@ -36,4 +62,4 @@ uint32_t socfpga_get_spsr_for_bl33_entry(void); unsigned long socfpga_get_ns_image_entrypoint(void); -#endif /* PLATFORM_PRIVATE_H */ +#endif /* SOCFPGA_PRIVATE_H */ diff --git a/plat/intel/soc/agilex/soc/agilex_handoff.c b/plat/intel/soc/common/soc/socfpga_handoff.c index a458686f1..4bb3a9619 100644 --- a/plat/intel/soc/agilex/soc/agilex_handoff.c +++ b/plat/intel/soc/common/soc/socfpga_handoff.c @@ -4,15 +4,14 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include <platform_def.h> #include <string.h> -#include "agilex_handoff.h" +#include "socfpga_handoff.h" #define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \ (((x) & 0x0000FF00) << 8) | ((x) << 24)) -int agilex_get_handoff(handoff *reverse_hoff_ptr) +int socfpga_get_handoff(handoff *reverse_hoff_ptr) { int i; uint32_t *buffer; diff --git a/plat/intel/soc/agilex/soc/agilex_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index ebfea6148..27838bfe7 100644 --- a/plat/intel/soc/agilex/soc/agilex_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -7,7 +7,7 @@ #include <lib/mmio.h> #include <common/debug.h> -#include "agilex_mailbox.h" +#include "socfpga_mailbox.h" static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, int len) diff --git a/plat/intel/soc/agilex/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index 12060ef08..e29836173 100644 --- a/plat/intel/soc/agilex/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -11,13 +11,11 @@ #include <lib/psci/psci.h> #include <plat/common/platform.h> -#include "agilex_reset_manager.h" -#include "agilex_mailbox.h" +#include "socfpga_mailbox.h" +#include "socfpga_plat_def.h" -#define AGX_RSTMGR_OFST 0xffd11000 -#define AGX_RSTMGR_MPUMODRST_OFST 0x20 -uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; +uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; /******************************************************************************* @@ -50,8 +48,7 @@ int socfpga_pwr_domain_on(u_register_t mpidr) *cpuid_release = cpu_id; /* release core reset */ - mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); + mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); return PSCI_E_SUCCESS; } @@ -81,8 +78,7 @@ void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); /* assert core reset */ - mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); + mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); } @@ -121,8 +117,7 @@ void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state) __func__, i, target_state->pwr_domain_state[i]); /* release core reset */ - mmio_clrbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); + mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id); } /******************************************************************************* @@ -137,9 +132,6 @@ static void __dead2 socfpga_system_off(void) static void __dead2 socfpga_system_reset(void) { - INFO("assert Peripheral from Reset\r\n"); - - deassert_peripheral_reset(); mailbox_reset_cold(); while (1) @@ -191,7 +183,7 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, const struct plat_psci_ops **psci_ops) { /* Save warm boot entrypoint.*/ - *agilex_sec_entry = sec_entrypoint; + *socfpga_sec_entry = sec_entrypoint; *psci_ops = &socfpga_psci_pm_ops; return 0; diff --git a/plat/intel/soc/agilex/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index 6a1c957c3..88750d771 100644 --- a/plat/intel/soc/agilex/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -9,7 +9,7 @@ #include <common/runtime_svc.h> #include <tools_share/uuid.h> -#include "agilex_mailbox.h" +#include "socfpga_mailbox.h" /* Number of SiP Calls implemented */ #define SIP_NUM_CALLS 0x3 @@ -360,7 +360,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid, } DECLARE_RT_SVC( - agilex_sip_svc, + socfpga_sip_svc, OEN_SIP_START, OEN_SIP_END, SMC_TYPE_FAST, @@ -369,7 +369,7 @@ DECLARE_RT_SVC( ); DECLARE_RT_SVC( - agilex_sip_svc_std, + socfpga_sip_svc_std, OEN_SIP_START, OEN_SIP_END, SMC_TYPE_YIELD, diff --git a/plat/intel/soc/agilex/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c index 76dd81f75..a2f2c184c 100644 --- a/plat/intel/soc/agilex/socfpga_storage.c +++ b/plat/intel/soc/common/socfpga_storage.c @@ -19,7 +19,7 @@ #include <lib/mmio.h> #include <tools_share/firmware_image_package.h> -#include "agilex_private.h" +#include "socfpga_private.h" #define PLAT_FIP_BASE (0) #define PLAT_FIP_MAX_SIZE (0x1000000) diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index f24bbdec4..85a60d651 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -1,37 +1,29 @@ /* * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch.h> #include <arch_helpers.h> -#include <drivers/arm/gicv2.h> - -#include <drivers/generic_delay_timer.h> -#include <drivers/console.h> -#include <drivers/ti/uart/uart_16550.h> #include <common/bl_common.h> #include <common/debug.h> #include <common/desc_image_load.h> -#include <errno.h> -#include <drivers/io/io_storage.h> -#include <common/image_decompress.h> -#include <plat/common/platform.h> -#include <platform_def.h> -#include <socfpga_private.h> +#include <drivers/generic_delay_timer.h> #include <drivers/synopsys/dw_mmc.h> -#include <lib/mmio.h> +#include <drivers/ti/uart/uart_16550.h> #include <lib/xlat_tables/xlat_tables.h> -#include "s10_memory_controller.h" -#include "s10_reset_manager.h" +#include "qspi/cadence_qspi.h" +#include "socfpga_handoff.h" +#include "socfpga_mailbox.h" +#include "socfpga_private.h" #include "s10_clock_manager.h" -#include "s10_handoff.h" +#include "s10_memory_controller.h" #include "s10_pinmux.h" -#include "stratix10_private.h" -#include "include/s10_mailbox.h" -#include "qspi/cadence_qspi.h" +#include "s10_reset_manager.h" +#include "s10_system_manager.h" #include "wdt/watchdog.h" @@ -63,7 +55,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, generic_delay_timer_init(); - if (s10_get_handoff(&reverse_handoff_ptr)) + if (socfpga_get_handoff(&reverse_handoff_ptr)) return; config_pinmux(&reverse_handoff_ptr); boot_source = reverse_handoff_ptr.boot_source; @@ -115,7 +107,7 @@ void bl2_el3_plat_arch_setup(void) switch (boot_source) { case BOOT_SOURCE_SDMMC: dw_mmc_init(¶ms, &info); - stratix10_io_setup(boot_source); + socfpga_io_setup(boot_source); break; case BOOT_SOURCE_QSPI: @@ -124,7 +116,7 @@ void bl2_el3_plat_arch_setup(void) cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); - stratix10_io_setup(boot_source); + socfpga_io_setup(boot_source); break; default: diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 7c9833b33..a133f82cb 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -1,29 +1,22 @@ /* * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include <assert.h> #include <arch.h> #include <arch_helpers.h> +#include <assert.h> #include <common/bl_common.h> -#include <common/debug.h> -#include <drivers/console.h> -#include <drivers/delay_timer.h> -#include <drivers/arm/gic_common.h> #include <drivers/arm/gicv2.h> #include <drivers/ti/uart/uart_16550.h> -#include <drivers/generic_delay_timer.h> -#include <drivers/arm/gicv2.h> -#include <s10_mailbox.h> #include <lib/xlat_tables/xlat_tables.h> #include <lib/mmio.h> #include <plat/common/platform.h> #include <platform_def.h> -#include "stratix10_private.h" -#include "s10_handoff.h" +#include "socfpga_private.h" #include "s10_reset_manager.h" #include "s10_memory_controller.h" #include "s10_pinmux.h" @@ -82,15 +75,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, } static const interrupt_prop_t s10_interrupt_props[] = { - PLAT_INTEL_S10_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), - PLAT_INTEL_S10_G0_IRQ_PROPS(GICV2_INTR_GROUP0) + PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), + PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) }; static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; static const gicv2_driver_data_t plat_gicv2_gic_data = { - .gicd_base = PLAT_INTEL_S10_GICD_BASE, - .gicc_base = PLAT_INTEL_S10_GICC_BASE, + .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, + .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, .interrupt_props = s10_interrupt_props, .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), .target_masks = target_mask_array, diff --git a/plat/intel/soc/stratix10/include/platform_def.h b/plat/intel/soc/stratix10/include/platform_def.h deleted file mode 100644 index a753acd20..000000000 --- a/plat/intel/soc/stratix10/include/platform_def.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PLATFORM_DEF_H__ -#define __PLATFORM_DEF_H__ - -#include <arch.h> -#include <common/bl_common.h> -#include <common/interrupt_props.h> -#include <common/tbbr/tbbr_img_def.h> -#include <drivers/arm/gic_common.h> -#include <plat/common/common_def.h> - - -#define PLAT_CPUID_RELEASE 0xffe1b000 -#define PLAT_SEC_ENTRY 0xffe1b008 - -/* Define next boot image name and offset */ -#define PLAT_NS_IMAGE_OFFSET 0x50000 -#define PLAT_HANDOFF_OFFSET 0xFFE3F000 - -/******************************************************************************* - * Platform binary types for linking - ******************************************************************************/ -#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" -#define PLATFORM_LINKER_ARCH aarch64 - -/* Stratix 10 supports up to 124GB RAM */ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) - - -/******************************************************************************* - * Generic platform constants - ******************************************************************************/ -#define PLAT_PRIMARY_CPU 0 -#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 - -/* Size of cacheable stacks */ -#define PLATFORM_STACK_SIZE 0x2000 - -/* PSCI related constant */ -#define PLAT_NUM_POWER_DOMAINS 5 -#define PLAT_MAX_PWR_LVL 1 -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 2 -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CLUSTER_COUNT 1 -#define PLATFORM_CLUSTER0_CORE_COUNT 4 -#define PLATFORM_CLUSTER1_CORE_COUNT 0 -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ - PLATFORM_CLUSTER0_CORE_COUNT) -#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 - -/* Interrupt related constant */ - -#define INTEL_S10_IRQ_SEC_PHY_TIMER 29 - -#define INTEL_S10_IRQ_SEC_SGI_0 8 -#define INTEL_S10_IRQ_SEC_SGI_1 9 -#define INTEL_S10_IRQ_SEC_SGI_2 10 -#define INTEL_S10_IRQ_SEC_SGI_3 11 -#define INTEL_S10_IRQ_SEC_SGI_4 12 -#define INTEL_S10_IRQ_SEC_SGI_5 13 -#define INTEL_S10_IRQ_SEC_SGI_6 14 -#define INTEL_S10_IRQ_SEC_SGI_7 15 - -#define TSP_IRQ_SEC_PHY_TIMER INTEL_S10_IRQ_SEC_PHY_TIMER -#define TSP_SEC_MEM_BASE BL32_BASE -#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) -/******************************************************************************* - * Platform memory map related constants - ******************************************************************************/ -#define DRAM_BASE (0x0) -#define DRAM_SIZE (0x80000000) - -#define OCRAM_BASE (0xFFE00000) -#define OCRAM_SIZE (0x00040000) - -#define MEM64_BASE (0x0100000000) -#define MEM64_SIZE (0x1F00000000) - -#define DEVICE1_BASE (0x80000000) -#define DEVICE1_SIZE (0x60000000) - -#define DEVICE2_BASE (0xF7000000) -#define DEVICE2_SIZE (0x08E00000) - -#define DEVICE3_BASE (0xFFFC0000) -#define DEVICE3_SIZE (0x00008000) - -#define DEVICE4_BASE (0x2000000000) -#define DEVICE4_SIZE (0x0100000000) - -/******************************************************************************* - * BL31 specific defines. - ******************************************************************************/ -/* - * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if - * present). BL31_BASE is calculated using the current BL3-1 debug size plus a - * little space for growth. - */ - - -#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" - -#define BL1_RO_BASE (0xffe00000) -#define BL1_RO_LIMIT (0xffe0f000) -#define BL1_RW_BASE (0xffe10000) -#define BL1_RW_LIMIT (0xffe1ffff) -#define BL1_RW_SIZE (0x14000) - -#define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) - -#define BL31_BASE (0xffe1c000) -#define BL31_LIMIT (0xffe3bfff) - -/******************************************************************************* - * Platform specific page table and MMU setup constants - ******************************************************************************/ -#define MAX_XLAT_TABLES 8 -#define MAX_MMAP_REGIONS 16 - -/******************************************************************************* - * Declarations and constants to access the mailboxes safely. Each mailbox is - * aligned on the biggest cache line size in the platform. This is known only - * to the platform as it might have a combination of integrated and external - * caches. Such alignment ensures that two maiboxes do not sit on the same cache - * line at any cache level. They could belong to different cpus/clusters & - * get written while being protected by different locks causing corruption of - * a valid mailbox address. - ******************************************************************************/ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -#define PLAT_GIC_BASE (0xFFFC0000) -#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) -#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) -#define PLAT_GICR_BASE 0 - -/******************************************************************************* - * UART related constants - ******************************************************************************/ -#define PLAT_UART0_BASE (0xFFC02000) -#define PLAT_UART1_BASE (0xFFC02100) - -#define CRASH_CONSOLE_BASE PLAT_UART0_BASE - -#define PLAT_BAUDRATE (115200) -#define PLAT_UART_CLOCK (100000000) - -/******************************************************************************* - * System counter frequency related constants - ******************************************************************************/ -#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) -#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) - -#define PLAT_INTEL_S10_GICD_BASE PLAT_GICD_BASE -#define PLAT_INTEL_S10_GICC_BASE PLAT_GICC_BASE - -/* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - grp, GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE) - -#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp) - -#define MAX_IO_HANDLES 4 -#define MAX_IO_DEVICES 4 -#define MAX_IO_BLOCK_DEVICES 2 - - -#endif /* __PLATFORM_DEF_H__ */ - diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h index c800b9cf7..acc700a07 100644 --- a/plat/intel/soc/stratix10/include/s10_clock_manager.h +++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h @@ -7,7 +7,7 @@ #ifndef __CLOCKMANAGER_H__ #define __CLOCKMANAGER_H__ -#include "s10_handoff.h" +#include "socfpga_handoff.h" #define ALT_CLKMGR 0xffd10000 diff --git a/plat/intel/soc/stratix10/include/s10_handoff.h b/plat/intel/soc/stratix10/include/s10_handoff.h deleted file mode 100644 index 1cc8d09d2..000000000 --- a/plat/intel/soc/stratix10/include/s10_handoff.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HANDOFF_H_ -#define _HANDOFF_H_ - -#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ -#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ -#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ -#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ -#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ -#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ -#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ - -typedef struct handoff_t { - /* header */ - uint32_t header_magic; - uint32_t header_device; - uint32_t _pad_0x08_0x10[2]; - - /* pinmux configuration - select */ - uint32_t pinmux_sel_magic; - uint32_t pinmux_sel_length; - uint32_t _pad_0x18_0x20[2]; - uint32_t pinmux_sel_array[96]; /* offset, value */ - - /* pinmux configuration - io control */ - uint32_t pinmux_io_magic; - uint32_t pinmux_io_length; - uint32_t _pad_0x1a8_0x1b0[2]; - uint32_t pinmux_io_array[96]; /* offset, value */ - - /* pinmux configuration - use fpga switch */ - uint32_t pinmux_fpga_magic; - uint32_t pinmux_fpga_length; - uint32_t _pad_0x338_0x340[2]; - uint32_t pinmux_fpga_array[42]; /* offset, value */ - uint32_t _pad_0x3e8_0x3f0[2]; - - /* pinmux configuration - io delay */ - uint32_t pinmux_delay_magic; - uint32_t pinmux_delay_length; - uint32_t _pad_0x3f8_0x400[2]; - uint32_t pinmux_iodelay_array[96]; /* offset, value */ - - /* clock configuration */ - uint32_t clock_magic; - uint32_t clock_length; - uint32_t _pad_0x588_0x590[2]; - uint32_t main_pll_mpuclk; - uint32_t main_pll_nocclk; - uint32_t main_pll_cntr2clk; - uint32_t main_pll_cntr3clk; - uint32_t main_pll_cntr4clk; - uint32_t main_pll_cntr5clk; - uint32_t main_pll_cntr6clk; - uint32_t main_pll_cntr7clk; - uint32_t main_pll_cntr8clk; - uint32_t main_pll_cntr9clk; - uint32_t main_pll_nocdiv; - uint32_t main_pll_pllglob; - uint32_t main_pll_fdbck; - uint32_t main_pll_pllc0; - uint32_t main_pll_pllc1; - uint32_t _pad_0x5cc_0x5d0[1]; - uint32_t per_pll_cntr2clk; - uint32_t per_pll_cntr3clk; - uint32_t per_pll_cntr4clk; - uint32_t per_pll_cntr5clk; - uint32_t per_pll_cntr6clk; - uint32_t per_pll_cntr7clk; - uint32_t per_pll_cntr8clk; - uint32_t per_pll_cntr9clk; - uint32_t per_pll_emacctl; - uint32_t per_pll_gpiodiv; - uint32_t per_pll_pllglob; - uint32_t per_pll_fdbck; - uint32_t per_pll_pllc0; - uint32_t per_pll_pllc1; - uint32_t hps_osc_clk_h; - uint32_t fpga_clk_hz; - - /* misc configuration */ - uint32_t misc_magic; - uint32_t misc_length; - uint32_t _pad_0x618_0x620[2]; - uint32_t boot_source; -} handoff; - -int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); -int s10_get_handoff(handoff *hoff_ptr); - -#endif - - diff --git a/plat/intel/soc/stratix10/include/s10_mailbox.h b/plat/intel/soc/stratix10/include/s10_mailbox.h deleted file mode 100644 index 554c26566..000000000 --- a/plat/intel/soc/stratix10/include/s10_mailbox.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __S10_MBOX__ -#define __S10_MBOX__ - -#define MBOX_OFFSET 0xffa30000 - -#define MBOX_ATF_CLIENT_ID 0x1 -#define MBOX_JOB_ID 0x1 - -/* Mailbox interrupt flags and masks */ -#define MBOX_INT_FLAG_COE 0x1 -#define MBOX_INT_FLAG_RIE 0x2 -#define MBOX_INT_FLAG_UAE 0x100 -#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) -#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<4))) - -/* Mailbox response and status */ -#define MBOX_RESP_BUFFER_SIZE 16 -#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) -#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) -#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) -#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) -#define MBOX_STATUS_UA_MASK (1<<8) - -/* Mailbox command and response */ -#define MBOX_CMD_FREE_OFFSET 0x14 -#define MBOX_CMD_BUFFER_SIZE 32 -#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) -#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) -#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) -#define MBOX_INDIRECT (1 << 11) -#define MBOX_INSUFFICIENT_BUFFER -2 -#define MBOX_CIN 0x00 -#define MBOX_ROUT 0x04 -#define MBOX_URG 0x08 -#define MBOX_INT 0x0C -#define MBOX_COUT 0x20 -#define MBOX_RIN 0x24 -#define MBOX_STATUS 0x2C -#define MBOX_CMD_BUFFER 0x40 -#define MBOX_RESP_BUFFER 0xC0 - -#define MBOX_RESP_BUFFER_SIZE 16 -#define MBOX_RESP_OK 0 -#define MBOX_RESP_INVALID_CMD 1 -#define MBOX_RESP_UNKNOWN_BR 2 -#define MBOX_RESP_UNKNOWN 3 -#define MBOX_RESP_NOT_CONFIGURED 256 - -/* Mailbox SDM doorbell */ -#define MBOX_DOORBELL_TO_SDM 0x400 -#define MBOX_DOORBELL_FROM_SDM 0x480 - -/* Mailbox QSPI commands */ -#define MBOX_CMD_RESTART 2 -#define MBOX_CMD_QSPI_OPEN 50 -#define MBOX_CMD_QSPI_CLOSE 51 -#define MBOX_CMD_QSPI_DIRECT 59 -#define MBOX_CMD_GET_IDCODE 16 -#define MBOX_CMD_QSPI_SET_CS 52 - -/* Mailbox REBOOT commands */ -#define MBOX_CMD_REBOOT_HPS 71 - -/* Generic error handling */ -#define MBOX_TIMEOUT -2047 -#define MBOX_NO_RESPONSE -2 -#define MBOX_WRONG_ID -3 - -/* Mailbox status */ -#define RECONFIG_STATUS_STATE 0 -#define RECONFIG_STATUS_PIN_STATUS 2 -#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 -#define PIN_STATUS_NSTATUS (1U << 31) -#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) -#define SOFTFUNC_STATUS_INIT_DONE (1 << 1) -#define SOFTFUNC_STATUS_CONF_DONE (1 << 0) -#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 - -/* SMC function IDs for SiP Service queries */ -#define SIP_SVC_CALL_COUNT 0x8200ff00 -#define SIP_SVC_UID 0x8200ff01 -#define SIP_SVC_VERSION 0x8200ff03 - -/* SiP Service Calls version numbers */ -#define SIP_SVC_VERSION_MAJOR 0 -#define SIP_SVC_VERSION_MINOR 1 - -/* Mailbox reconfiguration commands */ -#define MBOX_RECONFIG 6 -#define MBOX_RECONFIG_DATA 8 -#define MBOX_RECONFIG_STATUS 9 - -/* Sip get memory */ -#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001 -#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005 -#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004 -#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002 -#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003 -#define INTEL_SIP_SMC_STATUS_OK 0 -#define INTEL_SIP_SMC_STATUS_ERROR 0x4 -#define INTEL_SIP_SMC_STATUS_BUSY 0x1 -#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 -#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x1000 -#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216 - -void mailbox_set_int(int interrupt_input); -int mailbox_init(void); -void mailbox_set_qspi_close(void); -void mailbox_set_qspi_open(void); -void mailbox_set_qspi_direct(void); -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response); -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent); -int mailbox_read_response(int job_id, uint32_t *response); -int mailbox_get_qspi_clock(void); -void mailbox_reset_cold(void); - -#endif diff --git a/plat/intel/soc/stratix10/include/s10_pinmux.h b/plat/intel/soc/stratix10/include/s10_pinmux.h index a1ba29ef9..82367d74f 100644 --- a/plat/intel/soc/stratix10/include/s10_pinmux.h +++ b/plat/intel/soc/stratix10/include/s10_pinmux.h @@ -12,7 +12,7 @@ #define S10_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300 #define S10_PINMUX_IO0_DELAY 0xffd13400 -#include "s10_handoff.h" +#include "socfpga_handoff.h" void config_pinmux(handoff *handoff); diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h new file mode 100644 index 000000000..ab723f79d --- /dev/null +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SOCFPGA_DEF_H +#define PLAT_SOCFPGA_DEF_H + +#include <platform_def.h> + +/* Platform Setting */ +#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 + +/* Register Mapping */ +#define SOCFPGA_MMC_REG_BASE 0xff808000 + +#define SOCFPGA_RSTMGR_OFST 0xffd11000 +#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020 + +#endif /* PLATSOCFPGA_DEF_H */ + diff --git a/plat/intel/soc/stratix10/include/stratix10_private.h b/plat/intel/soc/stratix10/include/stratix10_private.h deleted file mode 100644 index 85aff3aa7..000000000 --- a/plat/intel/soc/stratix10/include/stratix10_private.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __S10_PRIVATE_H__ -#define __S10_PRIVATE_H__ - -#define S10_MMC_REG_BASE 0xff808000 - -#define EMMC_DESC_SIZE (1<<20) -#define EMMC_INIT_PARAMS(base, clk) \ - { .bus_width = MMC_BUS_WIDTH_4, \ - .clk_rate = (clk), \ - .desc_base = (base), \ - .desc_size = EMMC_DESC_SIZE, \ - .flags = 0, \ - .reg_base = S10_MMC_REG_BASE, \ - \ - } - -typedef enum { - BOOT_SOURCE_FPGA = 0, - BOOT_SOURCE_SDMMC, - BOOT_SOURCE_NAND, - BOOT_SOURCE_RSVD, - BOOT_SOURCE_QSPI, -} boot_source_type; - -void enable_nonsecure_access(void); -void stratix10_io_setup(int boot_source); - -#endif diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c deleted file mode 100644 index f4a970e75..000000000 --- a/plat/intel/soc/stratix10/plat_psci.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch_helpers.h> -#include <assert.h> -#include <common/debug.h> -#include <errno.h> -#include <lib/mmio.h> -#include <drivers/arm/gic_common.h> -#include <drivers/arm/gicv2.h> -#include <plat/common/platform.h> -#include <lib/psci/psci.h> - -#include "platform_def.h" -#include "s10_reset_manager.h" -#include "s10_mailbox.h" - -#define S10_RSTMGR_OFST 0xffd11000 -#define S10_RSTMGR_MPUMODRST_OFST 0x20 - -uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY; -uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE; - -/******************************************************************************* - * plat handler called when a CPU is about to enter standby. - ******************************************************************************/ -void plat_cpu_standby(plat_local_state_t cpu_state) -{ - /* - * Enter standby state - * dsb is good practice before using wfi to enter low power states - */ - VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); - dsb(); - wfi(); -} - -/******************************************************************************* - * plat handler called when a power domain is about to be turned on. The - * mpidr determines the CPU to be turned on. - ******************************************************************************/ -int plat_pwr_domain_on(u_register_t mpidr) -{ - unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); - - VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); - - if (cpu_id == -1) - return PSCI_E_INTERN_FAIL; - - *cpuid_release = cpu_id; - - /* release core reset */ - mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); - return PSCI_E_SUCCESS; -} - -/******************************************************************************* - * plat handler called when a power domain is about to be turned off. The - * target_state encodes the power state that each level should transition to. - ******************************************************************************/ -void plat_pwr_domain_off(const psci_power_state_t *target_state) -{ - unsigned int cpu_id = plat_my_core_pos(); - - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* TODO: Prevent interrupts from spuriously waking up this cpu */ - /* gicv2_cpuif_disable(); */ - - /* assert core reset */ - mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); -} - -/******************************************************************************* - * plat handler called when a power domain is about to be suspended. The - * target_state encodes the power state that each level should transition to. - ******************************************************************************/ -void plat_pwr_domain_suspend(const psci_power_state_t *target_state) -{ - unsigned int cpu_id = plat_my_core_pos(); - - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - /* assert core reset */ - mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); - -} - -/******************************************************************************* - * plat handler called when a power domain has just been powered on after - * being turned off earlier. The target_state encodes the low power state that - * each level has woken up from. - ******************************************************************************/ -void plat_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* Program the gic per-cpu distributor or re-distributor interface */ - gicv2_pcpu_distif_init(); - gicv2_set_pe_target_mask(plat_my_core_pos()); - - /* Enable the gic cpu interface */ - gicv2_cpuif_enable(); -} - -/******************************************************************************* - * plat handler called when a power domain has just been powered on after - * having been suspended earlier. The target_state encodes the low power state - * that each level has woken up from. - * TODO: At the moment we reuse the on finisher and reinitialize the secure - * context. Need to implement a separate suspend finisher. - ******************************************************************************/ -void plat_pwr_domain_suspend_finish(const psci_power_state_t *target_state) -{ - unsigned int cpu_id = plat_my_core_pos(); - - for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) - VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", - __func__, i, target_state->pwr_domain_state[i]); - - /* release core reset */ - mmio_clrbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST, - 1 << cpu_id); -} - -/******************************************************************************* - * plat handlers to shutdown/reboot the system - ******************************************************************************/ -static void __dead2 plat_system_off(void) -{ - wfi(); - ERROR("System Off: operation not handled.\n"); - panic(); -} - -static void __dead2 plat_system_reset(void) -{ - INFO("assert Peripheral from Reset\r\n"); - - deassert_peripheral_reset(); - mailbox_reset_cold(); - - while (1) - wfi(); -} - -int plat_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) -{ - VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); - - return PSCI_E_SUCCESS; -} - -int plat_validate_ns_entrypoint(unsigned long ns_entrypoint) -{ - VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint); - return PSCI_E_SUCCESS; -} - -void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) -{ - req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; - req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; -} - -/******************************************************************************* - * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard - * platform layer will take care of registering the handlers with PSCI. - ******************************************************************************/ -const plat_psci_ops_t plat_psci_pm_ops = { - .cpu_standby = plat_cpu_standby, - .pwr_domain_on = plat_pwr_domain_on, - .pwr_domain_off = plat_pwr_domain_off, - .pwr_domain_suspend = plat_pwr_domain_suspend, - .pwr_domain_on_finish = plat_pwr_domain_on_finish, - .pwr_domain_suspend_finish = plat_pwr_domain_suspend_finish, - .system_off = plat_system_off, - .system_reset = plat_system_reset, - .validate_power_state = plat_validate_power_state, - .validate_ns_entrypoint = plat_validate_ns_entrypoint, - .get_sys_suspend_power_state = plat_get_sys_suspend_power_state -}; - -/******************************************************************************* - * Export the platform specific power ops. - ******************************************************************************/ -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const struct plat_psci_ops **psci_ops) -{ - /* Save warm boot entrypoint.*/ - *stratix10_sec_entry = sec_entrypoint; - - *psci_ops = &plat_psci_pm_ops; - return 0; -} diff --git a/plat/intel/soc/stratix10/plat_sip_svc.c b/plat/intel/soc/stratix10/plat_sip_svc.c deleted file mode 100644 index 2c2332ba9..000000000 --- a/plat/intel/soc/stratix10/plat_sip_svc.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <common/debug.h> -#include <common/runtime_svc.h> -#include <lib/mmio.h> -#include <s10_mailbox.h> -#include <tools_share/uuid.h> - -/* Number of SiP Calls implemented */ -#define SIP_NUM_CALLS 0x3 - -/* Total buffer the driver can hold */ -#define FPGA_CONFIG_BUFFER_SIZE 4 - -int current_block; -int current_buffer; -int current_id = 1; -int max_blocks; -uint32_t bytes_per_block; -uint32_t blocks_submitted; -uint32_t blocks_completed; - -struct fpga_config_info { - uint32_t addr; - int size; - int size_written; - uint32_t write_requested; - int subblocks_sent; - int block_number; -}; - -/* SiP Service UUID */ -DEFINE_SVC_UUID2(intl_svc_uid, - 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, - 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); - -uint64_t plat_sip_handler(uint32_t smc_fid, - uint64_t x1, - uint64_t x2, - uint64_t x3, - uint64_t x4, - void *cookie, - void *handle, - uint64_t flags) -{ - ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); - SMC_RET1(handle, SMC_UNK); -} - -struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; - -static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) -{ - uint32_t args[3]; - - while (max_blocks > 0 && buffer->size > buffer->size_written) { - if (buffer->size - buffer->size_written <= - bytes_per_block) { - args[0] = (1<<8); - args[1] = buffer->addr + buffer->size_written; - args[2] = buffer->size - buffer->size_written; - buffer->size_written += - buffer->size - buffer->size_written; - buffer->subblocks_sent++; - mailbox_send_cmd_async(0x4, - MBOX_RECONFIG_DATA, - args, 3, 0); - current_buffer++; - current_buffer %= FPGA_CONFIG_BUFFER_SIZE; - } else { - args[0] = (1<<8); - args[1] = buffer->addr + buffer->size_written; - args[2] = bytes_per_block; - buffer->size_written += bytes_per_block; - mailbox_send_cmd_async(0x4, - MBOX_RECONFIG_DATA, - args, 3, 0); - buffer->subblocks_sent++; - } - max_blocks--; - } -} - -static int intel_fpga_sdm_write_all(void) -{ - int i; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) - intel_fpga_sdm_write_buffer( - &fpga_config_buffers[current_buffer]); - - return 0; -} - -uint32_t intel_mailbox_fpga_config_isdone(void) -{ - uint32_t args[2]; - uint32_t response[6]; - int status; - - status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0, - response); - - if (status < 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (response[RECONFIG_STATUS_STATE] && - response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS)) - return INTEL_SIP_SMC_STATUS_ERROR; - - if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_SEU_ERROR) - return INTEL_SIP_SMC_STATUS_ERROR; - - if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_CONF_DONE) && - (response[RECONFIG_STATUS_SOFTFUNC_STATUS] & - SOFTFUNC_STATUS_INIT_DONE)) - return INTEL_SIP_SMC_STATUS_OK; - - return INTEL_SIP_SMC_STATUS_ERROR; -} - -static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) -{ - int i; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (fpga_config_buffers[i].block_number == current_block) { - fpga_config_buffers[i].subblocks_sent--; - if (fpga_config_buffers[i].subblocks_sent == 0 - && fpga_config_buffers[i].size <= - fpga_config_buffers[i].size_written) { - fpga_config_buffers[i].write_requested = 0; - current_block++; - *buffer_addr_completed = - fpga_config_buffers[i].addr; - return 0; - } - } - } - - return -1; -} - -unsigned int address_in_ddr(uint32_t *addr) -{ - if (((unsigned long long)addr > DRAM_BASE) && - ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE)) - return 0; - - return -1; -} - -int intel_fpga_config_completed_write(uint32_t *completed_addr, - uint32_t *count) -{ - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - *count = 0; - int resp_len = 0; - uint32_t resp[5]; - int all_completed = 1; - int count_check = 0; - - if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - for (count_check = 0; count_check < 3; count_check++) - if (address_in_ddr(&completed_addr[*count + count_check]) != 0) - return INTEL_SIP_SMC_STATUS_ERROR; - - resp_len = mailbox_read_response(0x4, resp); - - while (resp_len >= 0 && *count < 3) { - max_blocks++; - if (mark_last_buffer_xfer_completed( - &completed_addr[*count]) == 0) - *count = *count + 1; - else - break; - resp_len = mailbox_read_response(0x4, resp); - } - - if (*count <= 0) { - if (resp_len != MBOX_NO_RESPONSE && - resp_len != MBOX_TIMEOUT && resp_len != 0) { - return INTEL_SIP_SMC_STATUS_ERROR; - } - - *count = 0; - } - - intel_fpga_sdm_write_all(); - - if (*count > 0) - status = INTEL_SIP_SMC_STATUS_OK; - else if (*count == 0) - status = INTEL_SIP_SMC_STATUS_BUSY; - - for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (fpga_config_buffers[i].write_requested != 0) { - all_completed = 0; - break; - } - } - - if (all_completed == 1) - return INTEL_SIP_SMC_STATUS_OK; - - return status; -} - -int intel_fpga_config_start(uint32_t config_type) -{ - uint32_t response[3]; - int status = 0; - - status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0, - response); - - if (status < 0) - return status; - - max_blocks = response[0]; - bytes_per_block = response[1]; - - for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - fpga_config_buffers[i].size = 0; - fpga_config_buffers[i].size_written = 0; - fpga_config_buffers[i].addr = 0; - fpga_config_buffers[i].write_requested = 0; - fpga_config_buffers[i].block_number = 0; - fpga_config_buffers[i].subblocks_sent = 0; - } - - blocks_submitted = 0; - current_block = 0; - current_buffer = 0; - - return 0; -} - - -uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) -{ - int i = 0; - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - - if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE) - status = INTEL_SIP_SMC_STATUS_REJECTED; - - if (mem + size > DRAM_BASE + DRAM_SIZE) - status = INTEL_SIP_SMC_STATUS_REJECTED; - - for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { - if (!fpga_config_buffers[i].write_requested) { - fpga_config_buffers[i].addr = mem; - fpga_config_buffers[i].size = size; - fpga_config_buffers[i].size_written = 0; - fpga_config_buffers[i].write_requested = 1; - fpga_config_buffers[i].block_number = - blocks_submitted++; - fpga_config_buffers[i].subblocks_sent = 0; - break; - } - } - - - if (i == FPGA_CONFIG_BUFFER_SIZE) { - status = INTEL_SIP_SMC_STATUS_REJECTED; - return status; - } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) { - status = INTEL_SIP_SMC_STATUS_BUSY; - } - - intel_fpga_sdm_write_all(); - - return status; -} - -/* - * This function is responsible for handling all SiP calls from the NS world - */ - -uintptr_t sip_smc_handler(uint32_t smc_fid, - u_register_t x1, - u_register_t x2, - u_register_t x3, - u_register_t x4, - void *cookie, - void *handle, - u_register_t flags) -{ - uint32_t status = INTEL_SIP_SMC_STATUS_OK; - uint32_t completed_addr[3]; - uint32_t count = 0; - - switch (smc_fid) { - case SIP_SVC_UID: - /* Return UID to the caller */ - SMC_UUID_RET(handle, intl_svc_uid); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: - status = intel_mailbox_fpga_config_isdone(); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: - SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, - INTEL_SIP_SMC_FPGA_CONFIG_ADDR, - INTEL_SIP_SMC_FPGA_CONFIG_SIZE - - INTEL_SIP_SMC_FPGA_CONFIG_ADDR); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_START: - status = intel_fpga_config_start(x1); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: - status = intel_fpga_config_write(x1, x2); - SMC_RET4(handle, status, 0, 0, 0); - break; - case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: - status = intel_fpga_config_completed_write(completed_addr, - &count); - switch (count) { - case 1: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], 0, 0); - break; - case 2: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], - completed_addr[1], 0); - break; - case 3: - SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, - completed_addr[0], - completed_addr[1], - completed_addr[2]); - break; - case 0: - SMC_RET4(handle, status, 0, 0, 0); - break; - default: - SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); - } - break; - - default: - return plat_sip_handler(smc_fid, x1, x2, x3, x4, - cookie, handle, flags); - } -} - -DECLARE_RT_SVC( - s10_sip_svc, - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_FAST, - NULL, - sip_smc_handler -); - -DECLARE_RT_SVC( - s10_sip_svc_std, - OEN_SIP_START, - OEN_SIP_END, - SMC_TYPE_YIELD, - NULL, - sip_smc_handler -); diff --git a/plat/intel/soc/stratix10/plat_storage.c b/plat/intel/soc/stratix10/plat_storage.c deleted file mode 100644 index 0b8b9cd2a..000000000 --- a/plat/intel/soc/stratix10/plat_storage.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch_helpers.h> -#include <assert.h> -#include <common/debug.h> -#include <drivers/mmc.h> -#include <tools_share/firmware_image_package.h> -#include <drivers/io/io_block.h> -#include <drivers/io/io_driver.h> -#include <drivers/io/io_fip.h> -#include <drivers/io/io_memmap.h> -#include <drivers/io/io_storage.h> -#include <lib/mmio.h> -#include <drivers/partition/partition.h> -#include <lib/semihosting.h> -#include <string.h> -#include <lib/utils.h> -#include <common/tbbr/tbbr_img_def.h> -#include "platform_def.h" -#include "stratix10_private.h" - -#define STRATIX10_FIP_BASE (0) -#define STRATIX10_FIP_MAX_SIZE (0x1000000) -#define STRATIX10_MMC_DATA_BASE (0xffe3c000) -#define STRATIX10_MMC_DATA_SIZE (0x2000) -#define STRATIX10_QSPI_DATA_BASE (0x3C00000) -#define STRATIX10_QSPI_DATA_SIZE (0x1000000) - - -static const io_dev_connector_t *fip_dev_con; -static const io_dev_connector_t *boot_dev_con; - -static uintptr_t fip_dev_handle; -static uintptr_t boot_dev_handle; - -static const io_uuid_spec_t bl2_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, -}; - -static const io_uuid_spec_t bl31_uuid_spec = { - .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -uintptr_t a2_lba_offset; -const char a2[] = {0xa2, 0x0}; - -static const io_block_spec_t gpt_block_spec = { - .offset = 0, - .length = MMC_BLOCK_SIZE -}; - -static int check_fip(const uintptr_t spec); -static int check_dev(const uintptr_t spec); - -static io_block_dev_spec_t boot_dev_spec; -static int (*register_io_dev)(const io_dev_connector_t **); - -static io_block_spec_t fip_spec = { - .offset = STRATIX10_FIP_BASE, - .length = STRATIX10_FIP_MAX_SIZE, -}; - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -static const struct plat_io_policy policies[] = { - [FIP_IMAGE_ID] = { - &boot_dev_handle, - (uintptr_t)&fip_spec, - check_dev - }, - [BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl2_uuid_spec, - check_fip - }, - [BL31_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl31_uuid_spec, - check_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t) &bl33_uuid_spec, - check_fip - }, - [GPT_IMAGE_ID] = { - &boot_dev_handle, - (uintptr_t) &gpt_block_spec, - check_dev - }, -}; - -static int check_dev(const uintptr_t spec) -{ - int result; - uintptr_t local_handle; - - result = io_dev_init(boot_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(boot_dev_handle, spec, &local_handle); - if (result == 0) - io_close(local_handle); - } - return result; -} - -static int check_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) - io_close(local_image_handle); - } - return result; -} - -void stratix10_io_setup(int boot_source) -{ - int result; - - switch (boot_source) { - case BOOT_SOURCE_SDMMC: - register_io_dev = ®ister_io_dev_block; - boot_dev_spec.buffer.offset = STRATIX10_MMC_DATA_BASE; - boot_dev_spec.buffer.length = MMC_BLOCK_SIZE; - boot_dev_spec.ops.read = mmc_read_blocks; - boot_dev_spec.ops.write = mmc_write_blocks; - boot_dev_spec.block_size = MMC_BLOCK_SIZE; - break; - - case BOOT_SOURCE_QSPI: - register_io_dev = ®ister_io_dev_memmap; - fip_spec.offset = fip_spec.offset + STRATIX10_QSPI_DATA_BASE; - break; - - default: - ERROR("Unsupported boot source\n"); - panic(); - break; - } - - result = (*register_io_dev)(&boot_dev_con); - assert(result == 0); - - result = register_io_dev_fip(&fip_dev_con); - assert(result == 0); - - result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec, - &boot_dev_handle); - assert(result == 0); - - result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); - assert(result == 0); - - if (boot_source == BOOT_SOURCE_SDMMC) { - partition_init(GPT_IMAGE_ID); - fip_spec.offset = get_partition_entry(a2)->start; - } - - (void)result; -} - -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - result = policy->check(policy->image_spec); - assert(result == 0); - - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - - return result; -} diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 34674b0cd..e7251c428 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -1,5 +1,6 @@ # # Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -10,61 +11,54 @@ PLAT_INCLUDES := \ -Iplat/intel/soc/common/include/ PLAT_BL_COMMON_SOURCES := \ - lib/xlat_tables/xlat_tables_common.c \ - lib/xlat_tables/aarch64/xlat_tables.c \ drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/ti/uart/aarch64/16550_console.S \ + lib/xlat_tables/aarch64/xlat_tables.c \ + lib/xlat_tables/xlat_tables_common.c \ + plat/common/plat_gicv2.c \ plat/intel/soc/common/aarch64/platform_common.c \ plat/intel/soc/common/aarch64/plat_helpers.S BL2_SOURCES += \ - drivers/partition/partition.c \ - drivers/partition/gpt.c \ - drivers/arm/pl061/pl061_gpio.c \ + common/desc_image_load.c \ drivers/mmc/mmc.c \ - drivers/synopsys/emmc/dw_mmc.c \ + drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ drivers/io/io_storage.c \ drivers/io/io_block.c \ drivers/io/io_fip.c \ - drivers/gpio/gpio.c \ - drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ + drivers/partition/partition.c \ + drivers/partition/gpt.c \ + drivers/synopsys/emmc/dw_mmc.c \ + lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/stratix10/bl2_plat_setup.c \ - plat/intel/soc/stratix10/plat_storage.c \ - plat/intel/soc/common/bl2_plat_mem_params_desc.c \ - plat/intel/soc/stratix10/soc/s10_reset_manager.c \ - plat/intel/soc/stratix10/soc/s10_handoff.c \ plat/intel/soc/stratix10/soc/s10_clock_manager.c \ - plat/intel/soc/stratix10/soc/s10_pinmux.c \ plat/intel/soc/stratix10/soc/s10_memory_controller.c \ + plat/intel/soc/stratix10/soc/s10_pinmux.c \ + plat/intel/soc/stratix10/soc/s10_reset_manager.c \ + plat/intel/soc/stratix10/soc/s10_system_manager.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ plat/intel/soc/common/socfpga_delay_timer.c \ - lib/cpus/aarch64/cortex_a53.S \ plat/intel/soc/common/socfpga_image_load.c \ - plat/intel/soc/stratix10/soc/s10_system_manager.c \ - common/desc_image_load.c \ - plat/intel/soc/stratix10/soc/s10_mailbox.c \ + plat/intel/soc/common/socfpga_storage.c \ + plat/intel/soc/common/soc/socfpga_handoff.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ plat/intel/soc/common/drivers/wdt/watchdog.c -BL31_SOURCES += drivers/arm/cci/cci.c \ +BL31_SOURCES += \ + drivers/arm/cci/cci.c \ + lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a53.S \ - plat/common/plat_psci_common.c \ - plat/intel/soc/stratix10/plat_sip_svc.c \ - plat/intel/soc/stratix10/bl31_plat_setup.c \ - plat/intel/soc/stratix10/plat_psci.c \ - plat/intel/soc/common/socfpga_topology.c \ - plat/intel/soc/common/socfpga_delay_timer.c \ - plat/intel/soc/stratix10/soc/s10_reset_manager.c\ - plat/intel/soc/stratix10/soc/s10_pinmux.c \ - plat/intel/soc/stratix10/soc/s10_clock_manager.c\ - plat/intel/soc/stratix10/soc/s10_handoff.c \ - plat/intel/soc/stratix10/soc/s10_mailbox.c + plat/common/plat_psci_common.c \ + plat/intel/soc/stratix10/bl31_plat_setup.c \ + plat/intel/soc/common/socfpga_psci.c \ + plat/intel/soc/common/socfpga_sip_svc.c \ + plat/intel/soc/common/socfpga_topology.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c index ed65c2ba8..e4ff7acf2 100644 --- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c @@ -12,8 +12,8 @@ #include <platform_def.h> #include "s10_clock_manager.h" -#include "s10_handoff.h" #include "s10_system_manager.h" +#include "socfpga_handoff.h" void wait_pll_lock(void) diff --git a/plat/intel/soc/stratix10/soc/s10_handoff.c b/plat/intel/soc/stratix10/soc/s10_handoff.c deleted file mode 100644 index 1a4d5c326..000000000 --- a/plat/intel/soc/stratix10/soc/s10_handoff.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <arch_helpers.h> -#include <drivers/arm/gicv2.h> -#include <assert.h> -#include <common/bl_common.h> -#include <lib/mmio.h> -#include <string.h> -#include <plat/common/platform.h> -#include <platform_def.h> - -#include "s10_handoff.h" - -#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \ - (((x) & 0x0000FF00) << 8) | ((x) << 24)) - -int s10_get_handoff(handoff *reverse_hoff_ptr) -{ - int i; - uint32_t *buffer; - handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET; - - memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff)); - buffer = (uint32_t *)reverse_hoff_ptr; - - /* convert big indian to little indian */ - for (i = 0; i < sizeof(handoff) / 4; i++) - buffer[i] = SWAP_UINT32(buffer[i]); - - if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER) - return -1; - if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL) - return -1; - if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR) - return -1; - if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA) - return -1; - if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY) - return -1; - - return 0; -} diff --git a/plat/intel/soc/stratix10/soc/s10_mailbox.c b/plat/intel/soc/stratix10/soc/s10_mailbox.c deleted file mode 100644 index 00a07f33a..000000000 --- a/plat/intel/soc/stratix10/soc/s10_mailbox.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <lib/mmio.h> -#include <common/debug.h> -#include "s10_mailbox.h" - -static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args, - int len) -{ - uint32_t cmd_free_offset; - int i; - - cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN); - - if (cmd_free_offset >= MBOX_CMD_BUFFER_SIZE) { - INFO("Insufficient buffer in mailbox\n"); - return MBOX_INSUFFICIENT_BUFFER; - } - - - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4), - header_cmd); - - - for (i = 0; i < len; i++) { - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + - (cmd_free_offset++ * 4), args[i]); - } - - cmd_free_offset %= MBOX_CMD_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset); - - return 0; -} - -int mailbox_read_response(int job_id, uint32_t *response) -{ - int rin = 0; - int rout = 0; - int response_length = 0; - int resp = 0; - int total_resp_len = 0; - int timeout = 100000; - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - if (timeout-- < 0) - return MBOX_NO_RESPONSE; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - - rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - - while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); - - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) { - return MBOX_WRONG_ID; - } - - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -resp; - } - response_length = MBOX_RESP_LEN(resp); - - while (response_length) { - - response_length--; - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (response) { - *(response + total_resp_len) = resp; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; - } - - return MBOX_NO_RESPONSE; -} - - -int mailbox_poll_response(int job_id, int urgent, uint32_t *response) -{ - int timeout = 80000; - int rin = 0; - int rout = 0; - int response_length = 0; - int resp = 0; - int total_resp_len = 0; - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); - - while (1) { - while (timeout > 0 && - mmio_read_32(MBOX_OFFSET + - MBOX_DOORBELL_FROM_SDM) != 1) { - timeout--; - } - - if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { - INFO("Timed out waiting for SDM"); - return MBOX_TIMEOUT; - } - - mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); - - if (urgent & 1) { - if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & - MBOX_STATUS_UA_MASK) ^ - (urgent & MBOX_STATUS_UA_MASK)) { - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - return 0; - } - - mmio_write_32(MBOX_OFFSET + MBOX_URG, 0); - INFO("Error: Mailbox did not get UA"); - return -1; - } - - rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); - rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); - - while (rout != rin) { - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + ((rout++)*4)); - - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - - if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || - MBOX_RESP_JOB_ID(resp) != job_id) - continue; - - if (MBOX_RESP_ERR(resp) > 0) { - INFO("Error in response: %x\n", resp); - return -MBOX_RESP_ERR(resp); - } - response_length = MBOX_RESP_LEN(resp); - - while (response_length) { - - response_length--; - resp = mmio_read_32(MBOX_OFFSET + - MBOX_RESP_BUFFER + - (rout)*4); - if (response) { - *(response + total_resp_len) = resp; - total_resp_len++; - } - rout++; - rout %= MBOX_RESP_BUFFER_SIZE; - mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); - } - return total_resp_len; - } - } -} - -void mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent) -{ - if (urgent) - mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); - - fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - MBOX_CMD_LEN_CMD(len) | - MBOX_INDIRECT | - cmd, args, len); -} - -int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, - int len, int urgent, uint32_t *response) -{ - int status; - - if (urgent) { - urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) & - MBOX_STATUS_UA_MASK; - mmio_write_32(MBOX_OFFSET + MBOX_URG, 1); - } - - status = fill_mailbox_circular_buffer( - MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) | - MBOX_JOB_ID_CMD(job_id) | - cmd, args, len); - - if (status) - return status; - - return mailbox_poll_response(job_id, urgent, response); -} - -void mailbox_set_int(int interrupt) -{ - - mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) | - MBOX_UAE_BIT(interrupt)); -} - - -void mailbox_set_qspi_open(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, 0); -} - -void mailbox_set_qspi_direct(void) -{ - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); -} - -void mailbox_set_qspi_close(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, 0); -} - -int mailbox_get_qspi_clock(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, 0); -} - -void mailbox_qspi_set_cs(int device_select) -{ - uint32_t cs_setting = device_select; - - /* QSPI device select settings at 31:28 */ - cs_setting = (cs_setting << 28); - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting, - 1, 0, 0); -} - -void mailbox_reset_cold(void) -{ - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, 0); -} - -int mailbox_init(void) -{ - int status = 0; - - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, 0); - - if (status) - return status; - - mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - - return 0; -} - diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 1a9ba0a84..67f5abbd2 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -10,6 +10,12 @@ #include <lib/utils_def.h> /******************************************************************************* + * Chip specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) + +/******************************************************************************* * These values are used by the PSCI implementation during the `CPU_SUSPEND` * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' * parameter. diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h new file mode 100644 index 000000000..e0444c160 --- /dev/null +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -0,0 +1,650 @@ +/* + * Copyright (c) 2019, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __TEGRA_MC_DEF_H__ +#define __TEGRA_MC_DEF_H__ + +/******************************************************************************* + * Memory Controller Order_id registers + ******************************************************************************/ +#define MC_CLIENT_ORDER_ID_9 U(0x2a24) +#define MC_CLIENT_ORDER_ID_9_RESET_VAL 0x00000000U +#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_MASK (0x3U << 12) +#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_ORDER_ID (3U << 12) + +#define MC_CLIENT_ORDER_ID_27 U(0x2a6c) +#define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U +#define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4) +#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (1U << 4) + +#define MC_CLIENT_ORDER_ID_28 U(0x2a70) +#define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U +#define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4) +#define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4) +#define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) +#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12) + +#define mc_client_order_id(id, client) \ + (~MC_CLIENT_ORDER_ID_##id##_##client##_MASK | \ + MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID) + +/******************************************************************************* + * Memory Controller's VC ID configuration registers + ******************************************************************************/ +#define VC_NISO 0U +#define VC_SISO 1U +#define VC_ISO 2U + +#define MC_HUB_PC_VC_ID_0 U(0x2a78) +#define MC_HUB_PC_VC_ID_0_RESET_VAL 0x00020100U +#define MC_HUB_PC_VC_ID_0_APB_VC_ID_MASK (0x3U << 8) +#define MC_HUB_PC_VC_ID_0_APB_VC_ID (VC_NISO << 8) + +#define MC_HUB_PC_VC_ID_2 U(0x2a80) +#define MC_HUB_PC_VC_ID_2_RESET_VAL 0x10001000U +#define MC_HUB_PC_VC_ID_2_SD_VC_ID_MASK (0x3U << 28) +#define MC_HUB_PC_VC_ID_2_SD_VC_ID (VC_NISO << 28) + +#define MC_HUB_PC_VC_ID_4 U(0x2a88) +#define MC_HUB_PC_VC_ID_4_RESET_VAL 0x10020011U +#define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28) +#define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28) + +#define mc_hub_vc_id(id, client) \ + (~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK | \ + MC_HUB_PC_VC_ID_##id##_##client##_VC_ID) + +/******************************************************************************* + * Memory Controller's PCFIFO client configuration registers + ******************************************************************************/ +#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U + +#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U +#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20200000U +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_ORDERED (1U << 29) +#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29) + +#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U +#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x00002800U +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_ORDERED (1U << 13) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_UNORDERED (0U << 21) +#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_MASK (1U << 21) + +#define MC_PCFIFO_CLIENT_CONFIG3 0xddcU +#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0x08000080U +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_UNORDERED (0U << 4) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_MASK (1U << 4) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_UNORDERED (0U << 6) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_MASK (1U << 6) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_UNORDERED (0U << 13) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_MASK (1U << 13) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_UNORDERED (0U << 27) +#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_MASK (1U << 27) + +#define MC_PCFIFO_CLIENT_CONFIG4 0xde0U +#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0x5552a022U +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_UNORDERED (0U << 7) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_UNORDERED (0U << 20) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_MASK (1U << 20) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_UNORDERED (0U << 24) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_MASK (1U << 24) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_UNORDERED (0U << 28) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_MASK (1U << 28) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30) + +#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U +#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0x20000001U +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0) +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0) +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_UNORDERED (0U << 30) +#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_MASK (1U << 30) + +#define MC_PCFIFO_CLIENT_CONFIG6 0xb90U +#define MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL 0xaa280000U +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_UNORDERED (0U << 19) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_MASK (1U << 19) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_UNORDERED (0U << 21) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_MASK (1U << 21) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_UNORDERED (0U << 25) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_MASK (1U << 25) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_ORDERED (1U << 27) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_MASK (1U << 27) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_ORDERED (1U << 29) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_MASK (1U << 29) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_ORDERED (1U << 31) +#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_MASK (1U << 31) + +#define MC_PCFIFO_CLIENT_CONFIG7 0xaccU +#define MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL 0x0000000aU +#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_UNORDERED (0U << 1) +#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_MASK (1U << 1) +#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_UNORDERED (0U << 3) +#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_MASK (1U << 3) + +/******************************************************************************* + * StreamID to indicate no SMMU translations (requests to be steered on the + * SMMU bypass path) + ******************************************************************************/ +#define MC_STREAM_ID_MAX 0x7FU + +/******************************************************************************* + * Stream ID Override Config registers + ******************************************************************************/ +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U +#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xe0U +#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3f8U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U +#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5f0U +#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U +#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4f8U +#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U +#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2a0U +#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5f8U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U +#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1c8U +#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U +#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U +#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U +#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U +#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6d8U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U +#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U +#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U +#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1e8U +#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U +#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6f0U +#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U +#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4e8U +#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xb0U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U +#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U +#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U +#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6e8U +#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U +#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U +#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U +#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4d0U +#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U +#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U +#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xa8U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U +#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U +#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6a8U +#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2a8U +#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U +#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3f0U +#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4c8U +#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4d8U +#define MC_STREAMID_OVERRIDE_CFG_MIU5W 0x7e8U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6b0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U +#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6c8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U +#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U +#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U +#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U +#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U +#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U +#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U +#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6a0U +#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U +#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3c8U +#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U +#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U +#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U +#define MC_STREAMID_OVERRIDE_CFG_APER 0x3d0U +#define MC_STREAMID_OVERRIDE_CFG_MIU7R 0x8U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7c8U +#define MC_STREAMID_OVERRIDE_CFG_MIU7W 0x10U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U +#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4c0U +#define MC_STREAMID_OVERRIDE_CFG_MIU4W 0x598U +#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1a8U +#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4a0U +#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U +#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U +#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U +#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U +#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U +#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4b0U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7d8U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U +#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U +#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U +#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U +#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U +#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6b8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6c0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6f8U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U +#define MC_STREAMID_OVERRIDE_CFG_MIU6W 0x7f8U +#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6d0U +#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7d0U +#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U +#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U +#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U +#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U +#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U +#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4b8U +#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4a8U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U +#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5e8U +#define MC_STREAMID_OVERRIDE_CFG_MIU6R 0x7f0U +#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U +#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3c0U +#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U +#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U +#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U +#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U +#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4f0U +#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3d8U +#define MC_STREAMID_OVERRIDE_CFG_MIU5R 0x7e0U +#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U +#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U +#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U +#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0U +#define MC_STREAMID_OVERRIDE_CFG_MIU4R 0x590U +#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U +#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5e0U +#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6e0U +#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U +#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U +#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4e0U +#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U +#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U +#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xf8U +#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U +#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U +#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U +#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U +#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U + +/******************************************************************************* + * Macro to calculate Security cfg register addr from StreamID Override register + ******************************************************************************/ +#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t)) + +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4) + +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8) + +#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12) +#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12) + +/******************************************************************************* + * Memory Controller transaction override config registers + ******************************************************************************/ +#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U +#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624U +#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dcU +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644U +#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U +#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U +#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162cU +#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654U +#define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4U +#define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4U +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784U +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4U +#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178cU +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774U +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bcU +#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U +#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U +#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714U +#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U +#define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fcU +#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179cU +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764U +#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U +#define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008U +#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U +#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4U +#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dcU +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176cU +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166cU +#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U +#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U +#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ecU +#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4U +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674U +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164cU +#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U +#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548U +#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16ccU +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17ccU +#define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010U +#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U +#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580U +#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158cU +#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U +#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U +#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U +#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U +#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U +#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U +#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634U +#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U +#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U +#define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228U +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175cU +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4U +#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664U +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174cU +#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U +#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U +#define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410U +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4U +#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724U +#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U +#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578U +#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694U +#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170cU +#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U +#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U +#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U +#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U +#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4U +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614U +#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U +#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161cU +#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U +#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169cU +#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U +#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604U +#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4U +#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4U +#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540U +#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171cU +#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U +#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538U +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160cU +#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ecU +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fcU +#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fcU +#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530U +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165cU +#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U +#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U +#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U +#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U +#define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418U +#define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594U +#define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159cU +#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U +#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U +#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U +#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754U +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684U +#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168cU +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4U +#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794U +#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16acU +#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U +#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U +#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U +#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U +#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177cU +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163cU +#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167cU +#define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ecU +#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U +#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570U +#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U +#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U +#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704U +#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U + +#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0) +#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4) +#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12) + +/******************************************************************************* + * Non-SO_DEV transactions override values for CGID_TAG bitfield for the + * MC_TXN_OVERRIDE_CONFIG_{module} registers + ******************************************************************************/ +#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U +#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U +#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U +#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U +#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL + +/******************************************************************************* + * Memory Controller Reset Control registers + ******************************************************************************/ +#define MC_CLIENT_HOTRESET_CTRL0 0x200U +#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U +#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0) +#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6) +#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7) +#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8) +#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9) +#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11) +#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15) +#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17) +#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18) +#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19) +#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20) +#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22) +#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29) +#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30) +#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31) +#define MC_CLIENT_HOTRESET_STATUS0 0x204U +#define MC_CLIENT_HOTRESET_CTRL1 0x970U +#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U +#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0) +#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2) +#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5) +#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6) +#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7) +#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8) +#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12) +#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13) +#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 17) +#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 18) +#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 19) +#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 20) +#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 21) +#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 22) +#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 23) +#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1U << 26) +#define MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB (1U << 31) +#define MC_CLIENT_HOTRESET_STATUS1 0x974U +#define MC_CLIENT_HOTRESET_CTRL2 0x97cU +#define MC_CLIENT_HOTRESET_CTRL2_RESET_VAL 0U +#define MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB (1U << 0) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB (1U << 2) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB (1U << 4) +#define MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB (1U << 9) +#define MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB (1U << 10) +#define MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB (1U << 11) +#define MC_CLIENT_HOTRESET_CTRL2_APEDMA_FLUSH_ENB (1U << 14) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB (1U << 16) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB (1U << 17) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB (1U << 22) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB (1U << 23) +#define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25) +#define MC_CLIENT_HOTRESET_STATUS2 0x1898U + +/******************************************************************************* + * Tegra TSA Controller constants + ******************************************************************************/ +#define TEGRA_TSA_BASE U(0x02000000) + +#define TSA_CONFIG_STATIC0_CSR_RESET_R 0x20000000U +#define TSA_CONFIG_STATIC0_CSW_RESET_W 0x20001000U +#define TSA_CONFIG_STATIC0_CSW_RESET_SO_DEV 0x20001000U + +#define TSA_CONFIG_STATIC0_CSW_PCIE1W 0x1004U +#define TSA_CONFIG_STATIC0_CSW_PCIE2AW 0x1008U +#define TSA_CONFIG_STATIC0_CSW_PCIE3W 0x100cU +#define TSA_CONFIG_STATIC0_CSW_PCIE4W 0x1028U +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x2004U +#define TSA_CONFIG_STATIC0_CSR_SATAR 0x2010U +#define TSA_CONFIG_STATIC0_CSW_SATAW 0x2014U +#define TSA_CONFIG_STATIC0_CSW_PCIE0W 0x2020U +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x202cU +#define TSA_CONFIG_STATIC0_CSW_NVENC1SWR 0x3004U +#define TSA_CONFIG_STATIC0_CSW_NVENCSWR 0x3010U +#define TSA_CONFIG_STATIC0_CSW_NVDEC1SWR 0x4004U +#define TSA_CONFIG_STATIC0_CSR_ISPFALR 0x4010U +#define TSA_CONFIG_STATIC0_CSW_ISPWA 0x4014U +#define TSA_CONFIG_STATIC0_CSW_ISPWB 0x4018U +#define TSA_CONFIG_STATIC0_CSW_ISPFALW 0x401cU +#define TSA_CONFIG_STATIC0_CSW_NVDECSWR 0x5004U +#define TSA_CONFIG_STATIC0_CSR_EQOSR 0x5010U +#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x5014U +#define TSA_CONFIG_STATIC0_CSR_SDMMCRAB 0x5020U +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5024U +#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6004U +#define TSA_CONFIG_STATIC0_CSR_SDMMCR 0x6010U +#define TSA_CONFIG_STATIC0_CSR_SDMMCRA 0x6014U +#define TSA_CONFIG_STATIC0_CSW_SDMMCW 0x6018U +#define TSA_CONFIG_STATIC0_CSW_SDMMCWA 0x601cU +#define TSA_CONFIG_STATIC0_CSR_RCER 0x6030U +#define TSA_CONFIG_STATIC0_CSR_RCEDMAR 0x6034U +#define TSA_CONFIG_STATIC0_CSW_RCEW 0x6038U +#define TSA_CONFIG_STATIC0_CSW_RCEDMAW 0x603cU +#define TSA_CONFIG_STATIC0_CSR_SCER 0x6050U +#define TSA_CONFIG_STATIC0_CSR_SCEDMAR 0x6054U +#define TSA_CONFIG_STATIC0_CSW_SCEW 0x6058U +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x605cU +#define TSA_CONFIG_STATIC0_CSR_AXIAPR 0x7004U +#define TSA_CONFIG_STATIC0_CSR_ETRR 0x7008U +#define TSA_CONFIG_STATIC0_CSR_HOST1XDMAR 0x700cU +#define TSA_CONFIG_STATIC0_CSW_AXIAPW 0x7010U +#define TSA_CONFIG_STATIC0_CSW_ETRW 0x7014U +#define TSA_CONFIG_STATIC0_CSR_NVJPGSRD 0x8004U +#define TSA_CONFIG_STATIC0_CSW_NVJPGSWR 0x8008U +#define TSA_CONFIG_STATIC0_CSR_AXISR 0x8014U +#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8018U +#define TSA_CONFIG_STATIC0_CSR_BPMPR 0x9004U +#define TSA_CONFIG_STATIC0_CSR_BPMPDMAR 0x9008U +#define TSA_CONFIG_STATIC0_CSW_BPMPW 0x900cU +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9010U +#define TSA_CONFIG_STATIC0_CSR_SESRD 0x9024U +#define TSA_CONFIG_STATIC0_CSR_TSECSRD 0x9028U +#define TSA_CONFIG_STATIC0_CSR_TSECSRDB 0x902cU +#define TSA_CONFIG_STATIC0_CSW_SESWR 0x9030U +#define TSA_CONFIG_STATIC0_CSW_TSECSWR 0x9034U +#define TSA_CONFIG_STATIC0_CSW_TSECSWRB 0x9038U +#define TSA_CONFIG_STATIC0_CSW_PCIE5W 0xb004U +#define TSA_CONFIG_STATIC0_CSW_VICSWR 0xc004U +#define TSA_CONFIG_STATIC0_CSR_APER 0xd004U +#define TSA_CONFIG_STATIC0_CSR_APEDMAR 0xd008U +#define TSA_CONFIG_STATIC0_CSW_APEW 0xd00cU +#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xd010U +#define TSA_CONFIG_STATIC0_CSR_HDAR 0xf004U +#define TSA_CONFIG_STATIC0_CSW_HDAW 0xf008U +#define TSA_CONFIG_STATIC0_CSR_NVDISPLAYR 0xf014U +#define TSA_CONFIG_STATIC0_CSR_VIFALR 0x10004U +#define TSA_CONFIG_STATIC0_CSW_VIW 0x10008U +#define TSA_CONFIG_STATIC0_CSW_VIFALW 0x1000cU +#define TSA_CONFIG_STATIC0_CSR_AONR 0x12004U +#define TSA_CONFIG_STATIC0_CSR_AONDMAR 0x12008U +#define TSA_CONFIG_STATIC0_CSW_AONW 0x1200cU +#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0x12010U +#define TSA_CONFIG_STATIC0_CSR_PCIE1R 0x14004U +#define TSA_CONFIG_STATIC0_CSR_PCIE2AR 0x14008U +#define TSA_CONFIG_STATIC0_CSR_PCIE3R 0x1400cU +#define TSA_CONFIG_STATIC0_CSR_PCIE4R 0x14028U +#define TSA_CONFIG_STATIC0_CSR_XUSB_DEVR 0x15004U +#define TSA_CONFIG_STATIC0_CSR_XUSB_HOSTR 0x15010U +#define TSA_CONFIG_STATIC0_CSR_UFSHCR 0x16004U +#define TSA_CONFIG_STATIC0_CSW_DLA1WRA 0x18004U +#define TSA_CONFIG_STATIC0_CSR_DLA1FALRDB 0x18010U +#define TSA_CONFIG_STATIC0_CSW_DLA1FALWRB 0x18014U +#define TSA_CONFIG_STATIC0_CSW_DLA0WRA 0x19004U +#define TSA_CONFIG_STATIC0_CSR_DLA0FALRDB 0x19010U +#define TSA_CONFIG_STATIC0_CSW_DLA0FALWRB 0x19014U +#define TSA_CONFIG_STATIC0_CSR_PVA1RDC 0x1a004U +#define TSA_CONFIG_STATIC0_CSW_PVA1WRC 0x1a008U +#define TSA_CONFIG_STATIC0_CSW_PVA1WRA 0x1a014U +#define TSA_CONFIG_STATIC0_CSW_PVA1WRB 0x1a020U +#define TSA_CONFIG_STATIC0_CSW_PVA0WRB 0x1b004U +#define TSA_CONFIG_STATIC0_CSR_PVA0RDC 0x1b010U +#define TSA_CONFIG_STATIC0_CSW_PVA0WRC 0x1b014U +#define TSA_CONFIG_STATIC0_CSW_PVA0WRA 0x1b020U +#define TSA_CONFIG_STATIC0_CSR_NVENC1SRD 0x1d004U +#define TSA_CONFIG_STATIC0_CSR_NVENCSRD 0x1d010U +#define TSA_CONFIG_STATIC0_CSR_NVDEC1SRD 0x1e004U +#define TSA_CONFIG_STATIC0_CSR_ISPRA 0x1e010U +#define TSA_CONFIG_STATIC0_CSR_NVDECSRD 0x1f004U +#define TSA_CONFIG_STATIC0_CSR_PCIE0R 0x21004U +#define TSA_CONFIG_STATIC0_CSR_PCIE5R 0x23004U +#define TSA_CONFIG_STATIC0_CSR_VICSRD 0x24004U +#define TSA_CONFIG_STATIC0_CSR_DLA1RDA 0x26004U +#define TSA_CONFIG_STATIC0_CSR_DLA0RDA 0x27004U +#define TSA_CONFIG_STATIC0_CSR_PVA1RDA 0x28004U +#define TSA_CONFIG_STATIC0_CSR_PVA1RDB 0x28010U +#define TSA_CONFIG_STATIC0_CSR_PVA0RDB 0x29004U +#define TSA_CONFIG_STATIC0_CSR_PVA0RDA 0x29010U + +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) + +#endif /* __TEGRA_MC_DEF_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index 948fadec9..1188a3b81 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -66,10 +66,10 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state, << TEGRA194_WAKE_TIME_SHIFT; /* - * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that - * the correct value is read in tegra_soc_pwr_domain_suspend(), which - * is called with caches disabled. It is possible to read a stale value - * from DRAM in that function, because the L2 cache is not flushed + * Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure + * that the correct value is read in tegra_soc_pwr_domain_suspend(), + * which is called with caches disabled. It is possible to read a stale + * value from DRAM in that function, because the L2 cache is not flushed * unless the cluster is entering CC6/CC7. */ clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], @@ -125,7 +125,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7; ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, - percpu_data[cpu].wake_time, 0); + t19x_percpu_data[cpu].wake_time, 0); assert(ret == 0); } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 1696d5910..640ef4deb 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -270,143 +270,8 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { mc_make_sid_override_cfg(MIU2W), mc_make_sid_override_cfg(MIU3R), mc_make_sid_override_cfg(MIU3W), - smmu_make_gnsr0_nsec_cfg(CR0), - smmu_make_gnsr0_sec_cfg(IDR0), - smmu_make_gnsr0_sec_cfg(IDR1), - smmu_make_gnsr0_sec_cfg(IDR2), - smmu_make_gnsr0_nsec_cfg(GFSR), - smmu_make_gnsr0_nsec_cfg(GFSYNR0), - smmu_make_gnsr0_nsec_cfg(GFSYNR1), - smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), - smmu_make_gnsr0_nsec_cfg(PIDR2), - smmu_make_smrg_group(0), - smmu_make_smrg_group(1), - smmu_make_smrg_group(2), - smmu_make_smrg_group(3), - smmu_make_smrg_group(4), - smmu_make_smrg_group(5), - smmu_make_smrg_group(6), - smmu_make_smrg_group(7), - smmu_make_smrg_group(8), - smmu_make_smrg_group(9), - smmu_make_smrg_group(10), - smmu_make_smrg_group(11), - smmu_make_smrg_group(12), - smmu_make_smrg_group(13), - smmu_make_smrg_group(14), - smmu_make_smrg_group(15), - smmu_make_smrg_group(16), - smmu_make_smrg_group(17), - smmu_make_smrg_group(18), - smmu_make_smrg_group(19), - smmu_make_smrg_group(20), - smmu_make_smrg_group(21), - smmu_make_smrg_group(22), - smmu_make_smrg_group(23), - smmu_make_smrg_group(24), - smmu_make_smrg_group(25), - smmu_make_smrg_group(26), - smmu_make_smrg_group(27), - smmu_make_smrg_group(28), - smmu_make_smrg_group(29), - smmu_make_smrg_group(30), - smmu_make_smrg_group(31), - smmu_make_smrg_group(32), - smmu_make_smrg_group(33), - smmu_make_smrg_group(34), - smmu_make_smrg_group(35), - smmu_make_smrg_group(36), - smmu_make_smrg_group(37), - smmu_make_smrg_group(38), - smmu_make_smrg_group(39), - smmu_make_smrg_group(40), - smmu_make_smrg_group(41), - smmu_make_smrg_group(42), - smmu_make_smrg_group(43), - smmu_make_smrg_group(44), - smmu_make_smrg_group(45), - smmu_make_smrg_group(46), - smmu_make_smrg_group(47), - smmu_make_smrg_group(48), - smmu_make_smrg_group(49), - smmu_make_smrg_group(50), - smmu_make_smrg_group(51), - smmu_make_smrg_group(52), - smmu_make_smrg_group(53), - smmu_make_smrg_group(54), - smmu_make_smrg_group(55), - smmu_make_smrg_group(56), - smmu_make_smrg_group(57), - smmu_make_smrg_group(58), - smmu_make_smrg_group(59), - smmu_make_smrg_group(60), - smmu_make_smrg_group(61), - smmu_make_smrg_group(62), - smmu_make_smrg_group(63), - smmu_make_cb_group(0), - smmu_make_cb_group(1), - smmu_make_cb_group(2), - smmu_make_cb_group(3), - smmu_make_cb_group(4), - smmu_make_cb_group(5), - smmu_make_cb_group(6), - smmu_make_cb_group(7), - smmu_make_cb_group(8), - smmu_make_cb_group(9), - smmu_make_cb_group(10), - smmu_make_cb_group(11), - smmu_make_cb_group(12), - smmu_make_cb_group(13), - smmu_make_cb_group(14), - smmu_make_cb_group(15), - smmu_make_cb_group(16), - smmu_make_cb_group(17), - smmu_make_cb_group(18), - smmu_make_cb_group(19), - smmu_make_cb_group(20), - smmu_make_cb_group(21), - smmu_make_cb_group(22), - smmu_make_cb_group(23), - smmu_make_cb_group(24), - smmu_make_cb_group(25), - smmu_make_cb_group(26), - smmu_make_cb_group(27), - smmu_make_cb_group(28), - smmu_make_cb_group(29), - smmu_make_cb_group(30), - smmu_make_cb_group(31), - smmu_make_cb_group(32), - smmu_make_cb_group(33), - smmu_make_cb_group(34), - smmu_make_cb_group(35), - smmu_make_cb_group(36), - smmu_make_cb_group(37), - smmu_make_cb_group(38), - smmu_make_cb_group(39), - smmu_make_cb_group(40), - smmu_make_cb_group(41), - smmu_make_cb_group(42), - smmu_make_cb_group(43), - smmu_make_cb_group(44), - smmu_make_cb_group(45), - smmu_make_cb_group(46), - smmu_make_cb_group(47), - smmu_make_cb_group(48), - smmu_make_cb_group(49), - smmu_make_cb_group(50), - smmu_make_cb_group(51), - smmu_make_cb_group(52), - smmu_make_cb_group(53), - smmu_make_cb_group(54), - smmu_make_cb_group(55), - smmu_make_cb_group(56), - smmu_make_cb_group(57), - smmu_make_cb_group(58), - smmu_make_cb_group(59), - smmu_make_cb_group(60), - smmu_make_cb_group(61), - smmu_make_cb_group(62), - smmu_make_cb_group(63), + smmu_make_cfg(TEGRA_SMMU0_BASE), + smmu_make_cfg(TEGRA_SMMU2_BASE), smmu_bypass_cfg, /* TBU settings */ _END_OF_TABLE_, }; diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index 33c7e6f78..696a5774e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -12,7 +12,7 @@ #define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7 #define TEGRA194_STATE_SYSTEM_RESUME 0x600D -#define TEGRA194_SMMU_CTX_SIZE 0x490 +#define TEGRA194_SMMU_CTX_SIZE 0x80B .align 4 .globl tegra194_cpu_reset_handler diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h index 9b8ccfca6..283b60641 100644 --- a/plat/rockchip/px30/px30_def.h +++ b/plat/rockchip/px30/px30_def.h @@ -54,6 +54,9 @@ #define UART2_BASE 0xff160000 #define UART2_SIZE SIZE_K(64) +#define UART3_BASE 0xff168000 +#define UART3_SIZE SIZE_K(64) + #define UART5_BASE 0xff178000 #define UART5_SIZE SIZE_K(64) diff --git a/tools/memory/print_memory_map.py b/tools/memory/print_memory_map.py new file mode 100755 index 000000000..35cccd38c --- /dev/null +++ b/tools/memory/print_memory_map.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2019, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +import re +import os +import sys +import operator + +# List of folder/map to parse +bl_images = ['bl1', 'bl2', 'bl31'] + +# List of symbols to search for +blx_symbols = ['__BL1_RAM_START__', '__BL1_RAM_END__', + '__BL2_END__', + '__BL31_END__', + '__TEXT_START__', '__TEXT_END__', + '__RODATA_START__', '__RODATA_END__', + '__DATA_START__', '__DATA_END__', + '__STACKS_START__', '__STACKS_END__', + '__BSS_END', + ] + +# Regex to extract address from map file +address_pattern = re.compile(r"\b0x\w*") + +# List of found element: [address, symbol, file] +address_list = [] + +# Get the directory from command line or use a default one +if len(sys.argv) >= 2: + build_dir = sys.argv[1] +else: + build_dir = 'build/fvp/debug' + +# Extract all the required symbols from the map files +for image in bl_images: + file_path = os.path.join(build_dir, image, '{}.map'.format(image)) + if os.path.isfile(file_path): + with open (file_path, 'rt') as mapfile: + for line in mapfile: + for symbol in blx_symbols: + if line.find(symbol) > 0 and line.find("ASSERT") < 0: + # Extract address from line + match = address_pattern.search(line) + if match: + address_list.append([match.group(0), symbol, image]) + +# Sort by address +address_list.sort(key=operator.itemgetter(0)) + +# Generate memory view +print('{:-^87}'.format('Memory Map from: ' + build_dir)) +for address in reversed(address_list): + if "bl1" in address[2]: + print(address[0], '+{:-^20}+ |{:^20}| |{:^20}|'.format(address[1], '', '')) + elif "bl2" in address[2]: + print(address[0], '|{:^20}| +{:-^20}+ |{:^20}|'.format('', address[1], '')) + elif "bl31" in address[2]: + print(address[0], '|{:^20}| |{:^20}| +{:-^20}+'.format('', '', address[1])) + else: + print(address[0], '|{:^20}| |{:^20}| +{:-^20}+'.format('', '', address[1])) + +print('{:^20}{:_^20} {:_^20} {:_^20}'.format('', '', '', '')) +print('{:^20}{:^20} {:^20} {:^20}'.format('address', 'bl1', 'bl2', 'bl31')) |