diff options
51 files changed, 4522 insertions, 30 deletions
diff --git a/.gitignore b/.gitignore index 341308ca9..6b1e05774 100644 --- a/.gitignore +++ b/.gitignore @@ -22,6 +22,7 @@ tools/cert_create/src/**/*.o tools/cert_create/cert_create tools/cert_create/cert_create.exe tools/marvell/doimage/doimage +tools/meson/doimage tools/stm32image/*.o tools/stm32image/stm32image tools/stm32image/stm32image.exe diff --git a/docs/plat/meson-gxl.rst b/docs/plat/meson-gxl.rst new file mode 100644 index 000000000..feac2dd07 --- /dev/null +++ b/docs/plat/meson-gxl.rst @@ -0,0 +1,27 @@ +Trusted Firmware-A for Amlogic Meson S905x (GXL) +================================================ + +The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running at +1.5Ghz. It also contains a Cortex-M3 used as SCP. + +This port is a minimal implementation of BL31 capable of booting mainline U-Boot +and Linux: + +- SCPI support. +- Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0 + can't be turned off, so there is a workaround to hide this from the caller. +- GICv2 driver set up. +- Basic SIP services (read efuse data, enable/disable JTAG). + +In order to build it: + +:: + + CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxl + +This port has been tested on a Lepotato. After building it, follow the +instructions in the `gxlimg repository` or `U-Boot repository`_, replacing the +mentioned **bl31.img** by the one built from this port. + +.. _gxlimg repository: https://github.com/repk/gxlimg/blob/master/README +.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/board/amlogic/p212/README.libretech-cc diff --git a/drivers/meson/gxl/crypto/sha_dma.c b/drivers/meson/gxl/crypto/sha_dma.c new file mode 100644 index 000000000..565099c4a --- /dev/null +++ b/drivers/meson/gxl/crypto/sha_dma.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2019, Remi Pommarel <repk@triplefau.lt> + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <arch_helpers.h> +#include <lib/mmio.h> +#include <crypto/sha_dma.h> + +#define AML_SHA_DMA_BASE 0xc883e000 + +#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) +#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) + +#define ASD_MODE_SHA224 0x7 +#define ASD_MODE_SHA256 0x6 + +/* SHA DMA descriptor */ +struct asd_desc { + uint32_t cfg; + uint32_t src; + uint32_t dst; +}; +#define ASD_DESC_GET(x, msk, off) (((x) >> (off)) & (msk)) +#define ASD_DESC_SET(x, v, msk, off) \ + ((x) = ((x) & ~((msk) << (off))) | (((v) & (msk)) << (off))) + +#define ASD_DESC_LEN_OFF 0 +#define ASD_DESC_LEN_MASK 0x1ffff +#define ASD_DESC_LEN(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) +#define ASD_DESC_LEN_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LEN_MASK, ASD_DESC_LEN_OFF)) + +#define ASD_DESC_IRQ_OFF 17 +#define ASD_DESC_IRQ_MASK 0x1 +#define ASD_DESC_IRQ(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) +#define ASD_DESC_IRQ_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_IRQ_MASK, ASD_DESC_IRQ_OFF)) + +#define ASD_DESC_EOD_OFF 18 +#define ASD_DESC_EOD_MASK 0x1 +#define ASD_DESC_EOD(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) +#define ASD_DESC_EOD_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_EOD_MASK, ASD_DESC_EOD_OFF)) + +#define ASD_DESC_LOOP_OFF 19 +#define ASD_DESC_LOOP_MASK 0x1 +#define ASD_DESC_LOOP(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) +#define ASD_DESC_LOOP_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_LOOP_MASK, ASD_DESC_LOOP_OFF)) + +#define ASD_DESC_MODE_OFF 20 +#define ASD_DESC_MODE_MASK 0xf +#define ASD_DESC_MODE(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) +#define ASD_DESC_MODE_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_MODE_MASK, ASD_DESC_MODE_OFF)) + +#define ASD_DESC_BEGIN_OFF 24 +#define ASD_DESC_BEGIN_MASK 0x1 +#define ASD_DESC_BEGIN(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) +#define ASD_DESC_BEGIN_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BEGIN_MASK, ASD_DESC_BEGIN_OFF)) + +#define ASD_DESC_END_OFF 25 +#define ASD_DESC_END_MASK 0x1 +#define ASD_DESC_END(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) +#define ASD_DESC_END_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_END_MASK, ASD_DESC_END_OFF)) + +#define ASD_DESC_OP_OFF 26 +#define ASD_DESC_OP_MASK 0x2 +#define ASD_DESC_OP(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) +#define ASD_DESC_OP_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OP_MASK, ASD_DESC_OP_OFF)) + +#define ASD_DESC_ENCONLY_OFF 28 +#define ASD_DESC_ENCONLY_MASK 0x1 +#define ASD_DESC_ENCONLY(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) +#define ASD_DESC_ENCONLY_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ENCONLY_MASK, ASD_DESC_ENCONLY_OFF)) + +#define ASD_DESC_BLOCK_OFF 29 +#define ASD_DESC_BLOCK_MASK 0x1 +#define ASD_DESC_BLOCK(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) +#define ASD_DESC_BLOCK_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_BLOCK_MASK, ASD_DESC_BLOCK_OFF)) + +#define ASD_DESC_ERR_OFF 30 +#define ASD_DESC_ERR_MASK 0x1 +#define ASD_DESC_ERR(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) +#define ASD_DESC_ERR_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF)) + +#define ASD_DESC_OWNER_OFF 31 +#define ASD_DESC_OWNER_MASK 0x1 +#define ASD_DESC_OWNER(d) \ + (ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) +#define ASD_DESC_OWNER_SET(d, v) \ + (ASD_DESC_SET((d)->cfg, v, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF)) + +static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len, + int finalize) +{ + /* Make it cache line size aligned ? */ + struct asd_desc desc = { + .src = (uint32_t)(uintptr_t)data, + .dst = (uint32_t)(uintptr_t)ctx->digest, + }; + + /* Check data address is 32bit compatible */ + assert((uintptr_t)data == (uintptr_t)desc.src); + assert((uintptr_t)ctx->digest == (uintptr_t)desc.dst); + assert((uintptr_t)&desc == (uintptr_t)&desc); + + ASD_DESC_LEN_SET(&desc, len); + ASD_DESC_OWNER_SET(&desc, 1); + ASD_DESC_ENCONLY_SET(&desc, 1); + ASD_DESC_EOD_SET(&desc, 1); + if (ctx->started == 0) { + ASD_DESC_BEGIN_SET(&desc, 1); + ctx->started = 1; + } + if (finalize) { + ASD_DESC_END_SET(&desc, 1); + ctx->started = 0; + } + if (ctx->mode == ASM_SHA224) + ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA224); + else + ASD_DESC_MODE_SET(&desc, ASD_MODE_SHA256); + + flush_dcache_range((uintptr_t)&desc, sizeof(desc)); + flush_dcache_range((uintptr_t)data, len); + + mmio_write_32(AML_SHA_DMA_STATUS, 0xf); + mmio_write_32(AML_SHA_DMA_DESC, ((uintptr_t)&desc) | 2); + while (mmio_read_32(AML_SHA_DMA_STATUS) == 0) + continue; + flush_dcache_range((uintptr_t)ctx->digest, SHA256_HASHSZ); +} + +void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len) +{ + size_t nr; + + if (ctx->blocksz) { + nr = MIN(len, SHA256_BLOCKSZ - ctx->blocksz); + memcpy(ctx->block + ctx->blocksz, data, nr); + ctx->blocksz += nr; + len -= nr; + data += nr; + } + + if (ctx->blocksz == SHA256_BLOCKSZ) { + asd_compute_sha(ctx, ctx->block, SHA256_BLOCKSZ, 0); + ctx->blocksz = 0; + } + + asd_compute_sha(ctx, data, len & ~(SHA256_BLOCKSZ - 1), 0); + data += len & ~(SHA256_BLOCKSZ - 1); + + if (len & (SHA256_BLOCKSZ - 1)) { + nr = len & (SHA256_BLOCKSZ - 1); + memcpy(ctx->block + ctx->blocksz, data, nr); + ctx->blocksz += nr; + } +} + +void asd_sha_finalize(struct asd_ctx *ctx) +{ + asd_compute_sha(ctx, ctx->block, ctx->blocksz, 1); +} diff --git a/drivers/renesas/rcar/board/board.c b/drivers/renesas/rcar/board/board.c index f15e06bc0..8c4eec24c 100644 --- a/drivers/renesas/rcar/board/board.c +++ b/drivers/renesas/rcar/board/board.c @@ -14,7 +14,9 @@ #include "board.h" #ifndef BOARD_DEFAULT -#if (RCAR_LSI == RCAR_E3) +#if (RCAR_LSI == RCAR_D3) +#define BOARD_DEFAULT (BOARD_DRAAK << BOARD_CODE_SHIFT) +#elif (RCAR_LSI == RCAR_E3) #define BOARD_DEFAULT (BOARD_EBISU << BOARD_CODE_SHIFT) #else #define BOARD_DEFAULT (BOARD_SALVATOR_X << BOARD_CODE_SHIFT) @@ -32,6 +34,7 @@ #define SK_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } +#define DR_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } #define KK_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU } const char *g_board_tbl[] = { @@ -42,6 +45,7 @@ const char *g_board_tbl[] = { [BOARD_EBISU_4D] = "Ebisu-4D", [BOARD_KRIEK] = "Kriek", [BOARD_EBISU] = "Ebisu", + [BOARD_DRAAK] = "Draak", [BOARD_UNKNOWN] = "unknown" }; @@ -55,6 +59,7 @@ int32_t rcar_get_board_type(uint32_t *type, uint32_t *rev) [BOARD_SALVATOR_X] = SX_ID, [BOARD_EBISU_4D] = EB4_ID, [BOARD_EBISU] = EB_ID, + [BOARD_DRAAK] = DR_ID, [BOARD_KRIEK] = KK_ID, }; static uint8_t board_id = BOARD_ID_UNKNOWN; diff --git a/drivers/renesas/rcar/board/board.h b/drivers/renesas/rcar/board/board.h index 7bb2a0626..05c4e8aa1 100644 --- a/drivers/renesas/rcar/board/board.h +++ b/drivers/renesas/rcar/board/board.h @@ -15,7 +15,8 @@ #define BOARD_EBISU (0x08) #define BOARD_STARTER_KIT_PRE (0x0B) #define BOARD_EBISU_4D (0x0DU) -#define BOARD_UNKNOWN (BOARD_EBISU_4D + 1U) +#define BOARD_DRAAK (0x0EU) +#define BOARD_UNKNOWN (BOARD_DRAAK + 1U) #define BOARD_REV_UNKNOWN (0xFF) diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c index d85e4a51b..8bea1b51d 100644 --- a/drivers/renesas/rcar/pwrc/pwrc.c +++ b/drivers/renesas/rcar/pwrc/pwrc.c @@ -737,6 +737,12 @@ uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr) return c; } +#if RCAR_LSI == RCAR_D3 +uint32_t rcar_pwrc_get_cpu_num(uint32_t c) +{ + return 1; +} +#else uint32_t rcar_pwrc_get_cpu_num(uint32_t c) { uint32_t reg = mmio_read_32(RCAR_PRR); @@ -768,6 +774,7 @@ count_ca57: done: return count; } +#endif int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr) { diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/rcar/rom/rom_api.c index be38fbff3..6f448a5aa 100644 --- a/drivers/renesas/rcar/rom/rom_api.c +++ b/drivers/renesas/rcar/rom/rom_api.c @@ -19,7 +19,7 @@ typedef uint32_t(*rom_get_lcs_api_f) (uint32_t *lcs); #define OLD_API_TABLE1 (0U) /* H3 Ver.1.0/Ver.1.1 */ #define OLD_API_TABLE2 (1U) /* H3 Ver.2.0 */ #define OLD_API_TABLE3 (2U) /* M3 Ver.1.0 */ -#define NEW_API_TABLE (3U) /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */ +#define NEW_API_TABLE (3U) /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */ #define API_TABLE_MAX (4U) /* table max */ /* Later than H3 Ver.2.0 */ @@ -66,7 +66,7 @@ uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert, 0xEB10DD64U, /* H3 Ver.1.0/Ver.1.1 */ 0xEB116ED4U, /* H3 Ver.2.0 */ 0xEB1102FCU, /* M3 Ver.1.0 */ - 0xEB100180U /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */ + 0xEB100180U /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */ }; rom_secure_boot_api_f secure_boot; uint32_t index; @@ -83,7 +83,7 @@ uint32_t rcar_rom_get_lcs(uint32_t *lcs) 0xEB10DFE0U, /* H3 Ver.1.0/Ver.1.1 */ 0xEB117150U, /* H3 Ver.2.0 */ 0xEB110578U, /* M3 Ver.1.0 */ - 0xEB10018CU /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */ + 0xEB10018CU /* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */ }; rom_get_lcs_api_f get_lcs; uint32_t index; diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S index 09dc90b8d..19b32e32b 100644 --- a/drivers/renesas/rcar/scif/scif.S +++ b/drivers/renesas/rcar/scif/scif.S @@ -17,6 +17,7 @@ #define PRR_CUT_MASK (0x000000FF) #define PRR_PRODUCT_H3_VER_10 (0x00004F00) #define PRR_PRODUCT_E3 (0x00005700) +#define PRR_PRODUCT_D3 (0x00005800) /* module stop */ #define CPG_BASE (0xE6150000) @@ -60,6 +61,7 @@ SCSMR_STOP_1 + \ SCSMR_CKS_DIV1) #define SCBRR_115200BPS (17) +#define SCBRR_115200BPSON (16) #define SCBRR_115200BPS_E3_SSCG (15) #define SCBRR_230400BPS (8) @@ -192,22 +194,29 @@ func console_core_init cmp w1, w2 beq 3f and w1, w1, #PRR_PRODUCT_MASK + mov w2, #PRR_PRODUCT_D3 + cmp w1, w2 + beq 4f + and w1, w1, #PRR_PRODUCT_MASK mov w2, #PRR_PRODUCT_E3 cmp w1, w2 - bne 4f + bne 5f ldr x1, =RST_MODEMR ldr w1, [x1] and w1, w1, #MODEMR_MD12 mov w2, #MODEMR_MD12 cmp w1, w2 - bne 4f + bne 5f mov w1, #SCBRR_115200BPS_E3_SSCG b 2f -4: +5: mov w1, #SCBRR_115200BPS b 2f +4: + mov w1, #SCBRR_115200BPSON + b 2f 3: mov w1, #SCBRR_230400BPS 2: diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c index 7793ae500..8b2943cc6 100644 --- a/drivers/renesas/rcar/watchdog/swdt.c +++ b/drivers/renesas/rcar/watchdog/swdt.c @@ -49,7 +49,11 @@ extern void gicd_set_icenabler(uintptr_t base, unsigned int id); #define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU) #define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U) +#if RCAR_LSI == RCAR_D3 +#define WTCNT_COUNT_8p13k (0x10000U - 40760U) +#else #define WTCNT_COUNT_8p13k (0x10000U - 40687U) +#endif #define WTCNT_COUNT_8p13k_H3VER10 (0x10000U - 20343U) #define WTCNT_COUNT_8p22k (0x10000U - 41115U) #define WTCNT_COUNT_7p81k (0x10000U - 39062U) diff --git a/drivers/staging/renesas/rcar/ddr/ddr.mk b/drivers/staging/renesas/rcar/ddr/ddr.mk index ef134132a..a73d227dd 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr.mk +++ b/drivers/staging/renesas/rcar/ddr/ddr.mk @@ -6,8 +6,10 @@ ifeq (${RCAR_LSI},${RCAR_E3}) include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk + BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c +else ifeq (${RCAR_LSI},${RCAR_D3}) + include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk else include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk + BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c endif - -BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h new file mode 100644 index 000000000..e157ab1ce --- /dev/null +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Revision history + * + * rev.0.01 2017/05/22 New + */ + +#ifndef BOOT_INIT_DRAM_REGDEF_D3_H_ +#define BOOT_INIT_DRAM_REGDEF_D3_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BIT0 0x00000001U +#define BIT30 0x40000000U + +/* DBSC registers */ + +#define DBSC_D3_DBSYSCONF1 0xE6790004U +#define DBSC_D3_DBPHYCONF0 0xE6790010U +#define DBSC_D3_DBKIND 0xE6790020U +#define DBSC_D3_DBMEMCONF00 0xE6790030U +#define DBSC_D3_DBMEMCONF01 0xE6790034U +#define DBSC_D3_DBMEMCONF02 0xE6790038U +#define DBSC_D3_DBMEMCONF03 0xE679003CU +#define DBSC_D3_DBMEMCONF10 0xE6790040U +#define DBSC_D3_DBMEMCONF11 0xE6790044U +#define DBSC_D3_DBMEMCONF12 0xE6790048U +#define DBSC_D3_DBMEMCONF13 0xE679004CU +#define DBSC_D3_DBMEMCONF20 0xE6790050U +#define DBSC_D3_DBMEMCONF21 0xE6790054U +#define DBSC_D3_DBMEMCONF22 0xE6790058U +#define DBSC_D3_DBMEMCONF23 0xE679005CU +#define DBSC_D3_DBMEMCONF30 0xE6790060U +#define DBSC_D3_DBMEMCONF31 0xE6790064U +#define DBSC_D3_DBMEMCONF32 0xE6790068U +#define DBSC_D3_DBMEMCONF33 0xE679006CU +#define DBSC_D3_DBSYSCNT0 0xE6790100U +#define DBSC_D3_DBSVCR1 0xE6790104U +#define DBSC_D3_DBSTATE0 0xE6790108U +#define DBSC_D3_DBSTATE1 0xE679010CU +#define DBSC_D3_DBINTEN 0xE6790180U +#define DBSC_D3_DBINTSTAT0 0xE6790184U +#define DBSC_D3_DBACEN 0xE6790200U +#define DBSC_D3_DBRFEN 0xE6790204U +#define DBSC_D3_DBCMD 0xE6790208U +#define DBSC_D3_DBWAIT 0xE6790210U +#define DBSC_D3_DBSYSCTRL0 0xE6790280U +#define DBSC_D3_DBTR0 0xE6790300U +#define DBSC_D3_DBTR1 0xE6790304U +#define DBSC_D3_DBTR2 0xE6790308U +#define DBSC_D3_DBTR3 0xE679030CU +#define DBSC_D3_DBTR4 0xE6790310U +#define DBSC_D3_DBTR5 0xE6790314U +#define DBSC_D3_DBTR6 0xE6790318U +#define DBSC_D3_DBTR7 0xE679031CU +#define DBSC_D3_DBTR8 0xE6790320U +#define DBSC_D3_DBTR9 0xE6790324U +#define DBSC_D3_DBTR10 0xE6790328U +#define DBSC_D3_DBTR11 0xE679032CU +#define DBSC_D3_DBTR12 0xE6790330U +#define DBSC_D3_DBTR13 0xE6790334U +#define DBSC_D3_DBTR14 0xE6790338U +#define DBSC_D3_DBTR15 0xE679033CU +#define DBSC_D3_DBTR16 0xE6790340U +#define DBSC_D3_DBTR17 0xE6790344U +#define DBSC_D3_DBTR18 0xE6790348U +#define DBSC_D3_DBTR19 0xE679034CU +#define DBSC_D3_DBTR20 0xE6790350U +#define DBSC_D3_DBTR21 0xE6790354U +#define DBSC_D3_DBTR22 0xE6790358U +#define DBSC_D3_DBTR24 0xE6790360U +#define DBSC_D3_DBTR25 0xE6790364U +#define DBSC_D3_DBBL 0xE6790400U +#define DBSC_D3_DBRFCNF1 0xE6790414U +#define DBSC_D3_DBRFCNF2 0xE6790418U +#define DBSC_D3_DBCALCNF 0xE6790424U +#define DBSC_D3_DBRNK2 0xE6790438U +#define DBSC_D3_DBRNK3 0xE679043CU +#define DBSC_D3_DBRNK4 0xE6790440U +#define DBSC_D3_DBRNK5 0xE6790444U +#define DBSC_D3_DBPDNCNF 0xE6790450U +#define DBSC_D3_DBODT0 0xE6790460U +#define DBSC_D3_DBODT1 0xE6790464U +#define DBSC_D3_DBODT2 0xE6790468U +#define DBSC_D3_DBODT3 0xE679046CU +#define DBSC_D3_DBADJ0 0xE6790500U +#define DBSC_D3_DBDBICNT 0xE6790518U +#define DBSC_D3_DBDFICUPDCNF 0xE679052CU +#define DBSC_D3_DBDFICNT0 0xE6790604U +#define DBSC_D3_DBPDLK0 0xE6790620U +#define DBSC_D3_DBPDRGA0 0xE6790624U +#define DBSC_D3_DBPDRGD0 0xE6790628U +#define DBSC_D3_DBPDSTAT00 0xE6790630U +#define DBSC_D3_DBDFISTAT1 0xE6790640U +#define DBSC_D3_DBDFICNT1 0xE6790644U +#define DBSC_D3_DBPDLK1 0xE6790660U +#define DBSC_D3_DBPDRGA1 0xE6790664U +#define DBSC_D3_DBPDRGD1 0xE6790668U +#define DBSC_D3_DBDFICNT2 0xE6790684U +#define DBSC_D3_DBPDLK2 0xE67906A0U +#define DBSC_D3_DBPDRGA2 0xE67906A4U +#define DBSC_D3_DBPDRGD2 0xE67906A8U +#define DBSC_D3_DBPDSTAT20 0xE67906B0U +#define DBSC_D3_DBDFISTAT3 0xE67906C0U +#define DBSC_D3_DBDFICNT3 0xE67906C4U +#define DBSC_D3_DBPDLK3 0xE67906E0U +#define DBSC_D3_DBPDRGA3 0xE67906E4U +#define DBSC_D3_DBPDRGD3 0xE67906E8U +#define DBSC_D3_DBBUS0CNF1 0xE6790804U +#define DBSC_D3_DBCAM0CNF1 0xE6790904U +#define DBSC_D3_DBCAM0CNF2 0xE6790908U +#define DBSC_D3_DBCAM0STAT0 0xE6790980U +#define DBSC_D3_DBCAM1STAT0 0xE6790990U +#define DBSC_D3_DBBCAMDIS 0xE67909FCU +#define DBSC_D3_DBSCHCNT0 0xE6791000U +#define DBSC_D3_DBSCHSZ0 0xE6791010U +#define DBSC_D3_DBSCHRW0 0xE6791020U +#define DBSC_D3_DBSCHRW1 0xE6791024U +#define DBSC_D3_DBSCHQOS00 0xE6791030U +#define DBSC_D3_DBSCHQOS01 0xE6791034U +#define DBSC_D3_DBSCHQOS02 0xE6791038U +#define DBSC_D3_DBSCHQOS03 0xE679103CU +#define DBSC_D3_DBSCHQOS10 0xE6791040U +#define DBSC_D3_DBSCHQOS11 0xE6791044U +#define DBSC_D3_DBSCHQOS12 0xE6791048U +#define DBSC_D3_DBSCHQOS13 0xE679104CU +#define DBSC_D3_DBSCHQOS20 0xE6791050U +#define DBSC_D3_DBSCHQOS21 0xE6791054U +#define DBSC_D3_DBSCHQOS22 0xE6791058U +#define DBSC_D3_DBSCHQOS23 0xE679105CU +#define DBSC_D3_DBSCHQOS30 0xE6791060U +#define DBSC_D3_DBSCHQOS31 0xE6791064U +#define DBSC_D3_DBSCHQOS32 0xE6791068U +#define DBSC_D3_DBSCHQOS33 0xE679106CU +#define DBSC_D3_DBSCHQOS40 0xE6791070U +#define DBSC_D3_DBSCHQOS41 0xE6791074U +#define DBSC_D3_DBSCHQOS42 0xE6791078U +#define DBSC_D3_DBSCHQOS43 0xE679107CU +#define DBSC_D3_DBSCHQOS50 0xE6791080U +#define DBSC_D3_DBSCHQOS51 0xE6791084U +#define DBSC_D3_DBSCHQOS52 0xE6791088U +#define DBSC_D3_DBSCHQOS53 0xE679108CU +#define DBSC_D3_DBSCHQOS60 0xE6791090U +#define DBSC_D3_DBSCHQOS61 0xE6791094U +#define DBSC_D3_DBSCHQOS62 0xE6791098U +#define DBSC_D3_DBSCHQOS63 0xE679109CU +#define DBSC_D3_DBSCHQOS70 0xE67910A0U +#define DBSC_D3_DBSCHQOS71 0xE67910A4U +#define DBSC_D3_DBSCHQOS72 0xE67910A8U +#define DBSC_D3_DBSCHQOS73 0xE67910ACU +#define DBSC_D3_DBSCHQOS80 0xE67910B0U +#define DBSC_D3_DBSCHQOS81 0xE67910B4U +#define DBSC_D3_DBSCHQOS82 0xE67910B8U +#define DBSC_D3_DBSCHQOS83 0xE67910BCU +#define DBSC_D3_DBSCHQOS90 0xE67910C0U +#define DBSC_D3_DBSCHQOS91 0xE67910C4U +#define DBSC_D3_DBSCHQOS92 0xE67910C8U +#define DBSC_D3_DBSCHQOS93 0xE67910CCU +#define DBSC_D3_DBSCHQOS100 0xE67910D0U +#define DBSC_D3_DBSCHQOS101 0xE67910D4U +#define DBSC_D3_DBSCHQOS102 0xE67910D8U +#define DBSC_D3_DBSCHQOS103 0xE67910DCU +#define DBSC_D3_DBSCHQOS110 0xE67910E0U +#define DBSC_D3_DBSCHQOS111 0xE67910E4U +#define DBSC_D3_DBSCHQOS112 0xE67910E8U +#define DBSC_D3_DBSCHQOS113 0xE67910ECU +#define DBSC_D3_DBSCHQOS120 0xE67910F0U +#define DBSC_D3_DBSCHQOS121 0xE67910F4U +#define DBSC_D3_DBSCHQOS122 0xE67910F8U +#define DBSC_D3_DBSCHQOS123 0xE67910FCU +#define DBSC_D3_DBSCHQOS130 0xE6791100U +#define DBSC_D3_DBSCHQOS131 0xE6791104U +#define DBSC_D3_DBSCHQOS132 0xE6791108U +#define DBSC_D3_DBSCHQOS133 0xE679110CU +#define DBSC_D3_DBSCHQOS140 0xE6791110U +#define DBSC_D3_DBSCHQOS141 0xE6791114U +#define DBSC_D3_DBSCHQOS142 0xE6791118U +#define DBSC_D3_DBSCHQOS143 0xE679111CU +#define DBSC_D3_DBSCHQOS150 0xE6791120U +#define DBSC_D3_DBSCHQOS151 0xE6791124U +#define DBSC_D3_DBSCHQOS152 0xE6791128U +#define DBSC_D3_DBSCHQOS153 0xE679112CU +#define DBSC_D3_SCFCTST0 0xE6791700U +#define DBSC_D3_SCFCTST1 0xE6791708U +#define DBSC_D3_SCFCTST2 0xE679170CU +#define DBSC_D3_DBMRRDR0 0xE6791800U +#define DBSC_D3_DBMRRDR1 0xE6791804U +#define DBSC_D3_DBMRRDR2 0xE6791808U +#define DBSC_D3_DBMRRDR3 0xE679180CU +#define DBSC_D3_DBMRRDR4 0xE6791810U +#define DBSC_D3_DBMRRDR5 0xE6791814U +#define DBSC_D3_DBMRRDR6 0xE6791818U +#define DBSC_D3_DBMRRDR7 0xE679181CU + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* BOOT_INIT_DRAM_REGDEF_D3_H_*/ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk index 2b9389100..5b4feb7b6 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk @@ -4,4 +4,8 @@ # SPDX-License-Identifier: BSD-3-Clause # +ifeq (${RCAR_LSI},${RCAR_E3}) BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c +else +BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c +endif diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c new file mode 100644 index 000000000..588c57de7 --- /dev/null +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c @@ -0,0 +1,691 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> +#include <mmio.h> +#include <common/debug.h> + +#include "boot_init_dram_regdef_d3.h" + +#define RCAR_DDR_VERSION "rev.0.01" + +#if RCAR_LSI != RCAR_D3 +#error "Don't have DDR initialize routine." +#endif + +static void WriteReg_32(uint32_t a, uint32_t v) +{ + (*(volatile uint32_t*)(uintptr_t)a) = v; +} + +static uint32_t ReadReg_32(uint32_t a) +{ + uint32_t w = (*(volatile uint32_t*)(uintptr_t)a); + return w; +} + +static void init_ddr_d3_1866(void) +{ + uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12; + + WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_D3_DBKIND,0x00000007); + WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01); + WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001); + WriteReg_32(DBSC_D3_DBTR0,0x0000000D); + WriteReg_32(DBSC_D3_DBTR1,0x00000009); + WriteReg_32(DBSC_D3_DBTR2,0x00000000); + WriteReg_32(DBSC_D3_DBTR3,0x0000000D); + WriteReg_32(DBSC_D3_DBTR4,0x000D000D); + WriteReg_32(DBSC_D3_DBTR5,0x0000002D); + WriteReg_32(DBSC_D3_DBTR6,0x00000020); + WriteReg_32(DBSC_D3_DBTR7,0x00060006); + WriteReg_32(DBSC_D3_DBTR8,0x00000021); + WriteReg_32(DBSC_D3_DBTR9,0x00000007); + WriteReg_32(DBSC_D3_DBTR10,0x0000000E); + WriteReg_32(DBSC_D3_DBTR11,0x0000000C); + WriteReg_32(DBSC_D3_DBTR12,0x00140014); + WriteReg_32(DBSC_D3_DBTR13,0x000000F2); + WriteReg_32(DBSC_D3_DBTR14,0x00170006); + WriteReg_32(DBSC_D3_DBTR15,0x00060005); + WriteReg_32(DBSC_D3_DBTR16,0x09210507); + WriteReg_32(DBSC_D3_DBTR17,0x040E0000); + WriteReg_32(DBSC_D3_DBTR18,0x00000200); + WriteReg_32(DBSC_D3_DBTR19,0x012B004B); + WriteReg_32(DBSC_D3_DBTR20,0x020000FB); + WriteReg_32(DBSC_D3_DBTR21,0x00040004); + WriteReg_32(DBSC_D3_DBBL,0x00000000); + WriteReg_32(DBSC_D3_DBODT0,0x00000001); + WriteReg_32(DBSC_D3_DBADJ0,0x00000001); + WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002); + WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010); + WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001); + WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046); + WriteReg_32(DBSC_D3_SCFCTST0,0x0D020D04); + WriteReg_32(DBSC_D3_SCFCTST1,0x0306040C); + + WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A); + WriteReg_32(DBSC_D3_DBCMD,0x01000001); + WriteReg_32(DBSC_D3_DBCMD,0x08000000); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); + WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A04); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); + WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058A00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); + WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007); + while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0A206F89); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022); + WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023); + WriteReg_32(DBSC_D3_DBPDRGD0,0x35A00D77); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024); + WriteReg_32(DBSC_D3_DBPDRGD0,0x2A8A2C28); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025); + WriteReg_32(DBSC_D3_DBPDRGD0,0x30005E00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0014CB49); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00000F14); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029); + WriteReg_32(DBSC_D3_DBPDRGD0,0x000000A0); + WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C); + WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884); + WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A); + WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9); + WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9); + WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E); + RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1; + RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2; + RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2; + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181); + WriteReg_32(DBSC_D3_DBCMD,0x08000001); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + for (uint32_t i = 0; i<2; i++) + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8; + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007); + if ( RegVal_R6 > 0 ) + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6); + } else + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); + } + } + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005); + WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005); + WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF); + RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0); + WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00))); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF); + RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0); + WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00))); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C); + WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + for (uint32_t i = 0; i < 2; i++) + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20); + RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007); + RegVal_R12 = (RegVal_R5 >> 0x2); + if ( RegVal_R12 < RegVal_R6 ) + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); + } + else + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007)); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); + } + } + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007); + while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 ); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E); + + WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010); + WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B); + WriteReg_32(DBSC_D3_DBRFCNF1,0x00080E23); + WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000); + WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001); + WriteReg_32(DBSC_D3_DBRFEN,0x00000001); + WriteReg_32(DBSC_D3_DBACEN,0x00000001); + WriteReg_32(DBSC_D3_DBPDLK0,0x00000000); + WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init + WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218); + WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4); + WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037); + WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001); + WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111); + WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123); + WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00); + WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00); + WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000); + WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000); + WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300); + WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0); + WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200); + WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100); + WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300); + WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0); + WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200); + WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100); + WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100); + WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0); + WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0); + WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040); + WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0); + WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0); + WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080); + WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040); + WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040); + WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030); + WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020); + WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010); + WriteReg_32(0xE67F0018,0x00000001); + WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000); +#endif +} + +static void init_ddr_d3_1600(void) +{ + uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12; + + WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_D3_DBKIND,0x00000007); + WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01); + WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001); + WriteReg_32(DBSC_D3_DBTR0,0x0000000B); + WriteReg_32(DBSC_D3_DBTR1,0x00000008); + WriteReg_32(DBSC_D3_DBTR2,0x00000000); + WriteReg_32(DBSC_D3_DBTR3,0x0000000B); + WriteReg_32(DBSC_D3_DBTR4,0x000B000B); + WriteReg_32(DBSC_D3_DBTR5,0x00000027); + WriteReg_32(DBSC_D3_DBTR6,0x0000001C); + WriteReg_32(DBSC_D3_DBTR7,0x00060006); + WriteReg_32(DBSC_D3_DBTR8,0x00000020); + WriteReg_32(DBSC_D3_DBTR9,0x00000006); + WriteReg_32(DBSC_D3_DBTR10,0x0000000C); + WriteReg_32(DBSC_D3_DBTR11,0x0000000A); + WriteReg_32(DBSC_D3_DBTR12,0x00120012); + WriteReg_32(DBSC_D3_DBTR13,0x000000D0); + WriteReg_32(DBSC_D3_DBTR14,0x00140005); + WriteReg_32(DBSC_D3_DBTR15,0x00050004); + WriteReg_32(DBSC_D3_DBTR16,0x071F0305); + WriteReg_32(DBSC_D3_DBTR17,0x040C0000); + WriteReg_32(DBSC_D3_DBTR18,0x00000200); + WriteReg_32(DBSC_D3_DBTR19,0x01000040); + WriteReg_32(DBSC_D3_DBTR20,0x020000D8); + WriteReg_32(DBSC_D3_DBTR21,0x00040004); + WriteReg_32(DBSC_D3_DBBL,0x00000000); + WriteReg_32(DBSC_D3_DBODT0,0x00000001); + WriteReg_32(DBSC_D3_DBADJ0,0x00000001); + WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002); + WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010); + WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001); + WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046); + WriteReg_32(DBSC_D3_SCFCTST0,0x0D020C04); + WriteReg_32(DBSC_D3_SCFCTST1,0x0305040C); + + WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A); + WriteReg_32(DBSC_D3_DBCMD,0x01000001); + WriteReg_32(DBSC_D3_DBCMD,0x08000000); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); + WriteReg_32(DBSC_D3_DBPDRGD0,0x04058904); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); + WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058900); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); + WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007); + while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004); + WriteReg_32(DBSC_D3_DBPDRGD0,0x08C05FF0); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022); + WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023); + WriteReg_32(DBSC_D3_DBPDRGD0,0x2D9C0B66); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024); + WriteReg_32(DBSC_D3_DBPDRGD0,0x2A88C400); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025); + WriteReg_32(DBSC_D3_DBPDRGD0,0x30005200); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0014A9C9); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00000D70); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00000098); + WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C); + WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884); + WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A); + WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9); + WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9); + WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E); + RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1; + RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2; + RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2; + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181); + WriteReg_32(DBSC_D3_DBCMD,0x08000001); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + for (uint32_t i = 0; i<2; i++) + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8; + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007); + if ( RegVal_R6 > 0 ) + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6); + } else + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); + } + } + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005); + WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005); + WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF); + RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0); + WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00))); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF); + RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0); + WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00))); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C); + WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + for (uint32_t i = 0; i < 2; i++) + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20); + RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007); + RegVal_R12 = (RegVal_R5 >> 0x2); + if ( RegVal_R12 < RegVal_R6 ) + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); + } + else + { + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007)); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); + WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); + } + } + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007); + while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 ); + WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021); + WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E); + + WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010); + WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B); + WriteReg_32(DBSC_D3_DBRFCNF1,0x00080C30); + WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000); + WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001); + WriteReg_32(DBSC_D3_DBRFEN,0x00000001); + WriteReg_32(DBSC_D3_DBACEN,0x00000001); + WriteReg_32(DBSC_D3_DBPDLK0,0x00000000); + WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init + WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218); + WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4); + WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037); + WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001); + WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111); + WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123); + WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00); + WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00); + WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000); + WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000); + WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300); + WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0); + WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200); + WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100); + WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300); + WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0); + WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200); + WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100); + WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100); + WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0); + WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0); + WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040); + WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0); + WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0); + WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080); + WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040); + WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040); + WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030); + WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020); + WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010); + WriteReg_32(0xE67F0018,0x00000001); + WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000); +#endif +} + +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_PRODUCT_D3 (0x00005800U) + +#define RST_MODEMR (0xE6160060) +#define MODEMR_MD19 (0x00080000U) + +int32_t rcar_dram_init(void) +{ + uint32_t reg; + uint32_t ddr_mbps; + + reg = mmio_read_32(PRR); + + if (PRR_PRODUCT_D3 != (reg & PRR_PRODUCT_MASK)) { + ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n", + reg); + panic(); + } + + reg = mmio_read_32(RST_MODEMR); + if (MODEMR_MD19 == (reg & MODEMR_MD19)) { + init_ddr_d3_1866(); + ddr_mbps = 1866; + } else { + init_ddr_d3_1600(); + ddr_mbps = 1600; + } + + NOTICE("BL2: DDR%d\n", ddr_mbps); + + return 0; +} diff --git a/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c new file mode 100644 index 000000000..639f832b5 --- /dev/null +++ b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c @@ -0,0 +1,943 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> +#include <mmio.h> +#include "pfc_init_d3.h" +#include "rcar_def.h" + + +/* GPIO base address */ +#define GPIO_BASE (0xE6050000U) + +/* GPIO registers */ +#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) +#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) +#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) +#define GPIO_INDT0 (GPIO_BASE + 0x000CU) +#define GPIO_INTDT0 (GPIO_BASE + 0x0010U) +#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) +#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) +#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) +#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) +#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) +#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) +#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) +#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) +#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) +#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) +#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) +#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) +#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) +#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) +#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) +#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define GPIO_INTDT1 (GPIO_BASE + 0x1010U) +#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) +#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) +#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) +#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) +#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) +#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) +#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) +#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) +#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) +#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) +#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) +#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) +#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) +#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) +#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) +#define GPIO_INDT2 (GPIO_BASE + 0x200CU) +#define GPIO_INTDT2 (GPIO_BASE + 0x2010U) +#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) +#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) +#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) +#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) +#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) +#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) +#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) +#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) +#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) +#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) +#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) +#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) +#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) +#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) +#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) +#define GPIO_INDT3 (GPIO_BASE + 0x300CU) +#define GPIO_INTDT3 (GPIO_BASE + 0x3010U) +#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) +#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) +#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) +#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) +#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) +#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) +#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) +#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) +#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) +#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) +#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) +#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) +#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) +#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) +#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) +#define GPIO_INDT4 (GPIO_BASE + 0x400CU) +#define GPIO_INTDT4 (GPIO_BASE + 0x4010U) +#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) +#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) +#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) +#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) +#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) +#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) +#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) +#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) +#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) +#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) +#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) +#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) +#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) +#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) +#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) +#define GPIO_INDT5 (GPIO_BASE + 0x500CU) +#define GPIO_INTDT5 (GPIO_BASE + 0x5010U) +#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) +#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) +#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) +#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) +#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) +#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) +#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) +#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) +#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) +#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) +#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) +#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) +#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U) +#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U) +#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U) +#define GPIO_INDT6 (GPIO_BASE + 0x540CU) +#define GPIO_INTDT6 (GPIO_BASE + 0x5410U) +#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U) +#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U) +#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU) +#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U) +#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U) +#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U) +#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U) +#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU) +#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U) +#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U) +#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U) +#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU) +#define GPIO_IOINTSEL7 (GPIO_BASE + 0x5800U) +#define GPIO_INOUTSEL7 (GPIO_BASE + 0x5804U) +#define GPIO_OUTDT7 (GPIO_BASE + 0x5808U) +#define GPIO_INDT7 (GPIO_BASE + 0x580CU) +#define GPIO_INTDT7 (GPIO_BASE + 0x5810U) +#define GPIO_INTCLR7 (GPIO_BASE + 0x5814U) +#define GPIO_INTMSK7 (GPIO_BASE + 0x5818U) +#define GPIO_MSKCLR7 (GPIO_BASE + 0x581CU) +#define GPIO_POSNEG7 (GPIO_BASE + 0x5820U) +#define GPIO_EDGLEVEL7 (GPIO_BASE + 0x5824U) +#define GPIO_FILONOFF7 (GPIO_BASE + 0x5828U) +#define GPIO_INTMSKS7 (GPIO_BASE + 0x5838U) +#define GPIO_MSKCLRS7 (GPIO_BASE + 0x583CU) +#define GPIO_OUTDTSEL7 (GPIO_BASE + 0x5840U) +#define GPIO_OUTDTH7 (GPIO_BASE + 0x5844U) +#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U) +#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU) + + +/* Pin functon base address */ +#define PFC_BASE (0xE6060000U) + +/* Pin functon registers */ +#define PFC_PMMR (PFC_BASE + 0x0000U) +#define PFC_GPSR0 (PFC_BASE + 0x0100U) +#define PFC_GPSR1 (PFC_BASE + 0x0104U) +#define PFC_GPSR2 (PFC_BASE + 0x0108U) +#define PFC_GPSR3 (PFC_BASE + 0x010CU) +#define PFC_GPSR4 (PFC_BASE + 0x0110U) +#define PFC_GPSR5 (PFC_BASE + 0x0114U) +#define PFC_GPSR6 (PFC_BASE + 0x0118U) +#define PFC_GPSR7 (PFC_BASE + 0x011CU) +#define PFC_IPSR0 (PFC_BASE + 0x0200U) +#define PFC_IPSR1 (PFC_BASE + 0x0204U) +#define PFC_IPSR2 (PFC_BASE + 0x0208U) +#define PFC_IPSR3 (PFC_BASE + 0x020CU) +#define PFC_IPSR4 (PFC_BASE + 0x0210U) +#define PFC_IPSR5 (PFC_BASE + 0x0214U) +#define PFC_IPSR6 (PFC_BASE + 0x0218U) +#define PFC_IPSR7 (PFC_BASE + 0x021CU) +#define PFC_IPSR8 (PFC_BASE + 0x0220U) +#define PFC_IPSR9 (PFC_BASE + 0x0224U) +#define PFC_IPSR10 (PFC_BASE + 0x0228U) +#define PFC_IPSR11 (PFC_BASE + 0x022CU) +#define PFC_IPSR12 (PFC_BASE + 0x0230U) +#define PFC_IPSR13 (PFC_BASE + 0x0234U) +#define PFC_IPSR14 (PFC_BASE + 0x0238U) +#define PFC_IPSR15 (PFC_BASE + 0x023CU) +#define PFC_IPSR16 (PFC_BASE + 0x0240U) +#define PFC_IPSR17 (PFC_BASE + 0x0244U) +#define PFC_IPSR18 (PFC_BASE + 0x0248U) +#define PFC_DRVCTRL0 (PFC_BASE + 0x0300U) +#define PFC_DRVCTRL1 (PFC_BASE + 0x0304U) +#define PFC_DRVCTRL2 (PFC_BASE + 0x0308U) +#define PFC_DRVCTRL3 (PFC_BASE + 0x030CU) +#define PFC_DRVCTRL4 (PFC_BASE + 0x0310U) +#define PFC_DRVCTRL5 (PFC_BASE + 0x0314U) +#define PFC_DRVCTRL6 (PFC_BASE + 0x0318U) +#define PFC_DRVCTRL7 (PFC_BASE + 0x031CU) +#define PFC_DRVCTRL8 (PFC_BASE + 0x0320U) +#define PFC_DRVCTRL9 (PFC_BASE + 0x0324U) +#define PFC_DRVCTRL10 (PFC_BASE + 0x0328U) +#define PFC_DRVCTRL11 (PFC_BASE + 0x032CU) +#define PFC_DRVCTRL12 (PFC_BASE + 0x0330U) +#define PFC_DRVCTRL13 (PFC_BASE + 0x0334U) +#define PFC_DRVCTRL14 (PFC_BASE + 0x0338U) +#define PFC_DRVCTRL15 (PFC_BASE + 0x033CU) +#define PFC_DRVCTRL16 (PFC_BASE + 0x0340U) +#define PFC_DRVCTRL17 (PFC_BASE + 0x0344U) +#define PFC_DRVCTRL18 (PFC_BASE + 0x0348U) +#define PFC_DRVCTRL19 (PFC_BASE + 0x034CU) +#define PFC_DRVCTRL20 (PFC_BASE + 0x0350U) +#define PFC_DRVCTRL21 (PFC_BASE + 0x0354U) +#define PFC_DRVCTRL22 (PFC_BASE + 0x0358U) +#define PFC_DRVCTRL23 (PFC_BASE + 0x035CU) +#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U) +#define PFC_POCCTRL0 (PFC_BASE + 0x0380U) +#define PFC_POCCTRL1 (PFC_BASE + 0x0388U) +#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U) +#define PFC_IOCTRL (PFC_BASE + 0x03E0U) +#define PFC_TSREG (PFC_BASE + 0x03E4U) +#define PFC_PUEN0 (PFC_BASE + 0x0400U) +#define PFC_PUEN1 (PFC_BASE + 0x0404U) +#define PFC_PUEN2 (PFC_BASE + 0x0408U) +#define PFC_PUEN3 (PFC_BASE + 0x040CU) +#define PFC_PUEN4 (PFC_BASE + 0x0410U) +#define PFC_PUEN5 (PFC_BASE + 0x0414U) +#define PFC_PUEN6 (PFC_BASE + 0x0418U) +#define PFC_PUD0 (PFC_BASE + 0x0440U) +#define PFC_PUD1 (PFC_BASE + 0x0444U) +#define PFC_PUD2 (PFC_BASE + 0x0448U) +#define PFC_PUD3 (PFC_BASE + 0x044CU) +#define PFC_PUD4 (PFC_BASE + 0x0450U) +#define PFC_PUD5 (PFC_BASE + 0x0454U) +#define PFC_PUD6 (PFC_BASE + 0x0458U) +#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) +#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U) +#define PFC_MOD_SEL2 (PFC_BASE + 0x0508U) + +#define GPSR0_D15 ((uint32_t)1U << 15U) +#define GPSR0_D14 ((uint32_t)1U << 14U) +#define GPSR0_D13 ((uint32_t)1U << 13U) +#define GPSR0_D12 ((uint32_t)1U << 12U) +#define GPSR0_D11 ((uint32_t)1U << 11U) +#define GPSR0_D10 ((uint32_t)1U << 10U) +#define GPSR0_D9 ((uint32_t)1U << 9U) +#define GPSR0_D8 ((uint32_t)1U << 8U) +#define GPSR0_D7 ((uint32_t)1U << 7U) +#define GPSR0_D6 ((uint32_t)1U << 6U) +#define GPSR0_D5 ((uint32_t)1U << 5U) +#define GPSR0_D4 ((uint32_t)1U << 4U) +#define GPSR0_D3 ((uint32_t)1U << 3U) +#define GPSR0_D2 ((uint32_t)1U << 2U) +#define GPSR0_D1 ((uint32_t)1U << 1U) +#define GPSR0_D0 ((uint32_t)1U << 0U) +#define GPSR1_CLKOUT ((uint32_t)1U << 28U) +#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U) +#define GPSR1_WE1 ((uint32_t)1U << 26U) +#define GPSR1_WE0 ((uint32_t)1U << 25U) +#define GPSR1_RD_WR ((uint32_t)1U << 24U) +#define GPSR1_RD ((uint32_t)1U << 23U) +#define GPSR1_BS ((uint32_t)1U << 22U) +#define GPSR1_CS1_A26 ((uint32_t)1U << 21U) +#define GPSR1_CS0 ((uint32_t)1U << 20U) +#define GPSR1_A19 ((uint32_t)1U << 19U) +#define GPSR1_A18 ((uint32_t)1U << 18U) +#define GPSR1_A17 ((uint32_t)1U << 17U) +#define GPSR1_A16 ((uint32_t)1U << 16U) +#define GPSR1_A15 ((uint32_t)1U << 15U) +#define GPSR1_A14 ((uint32_t)1U << 14U) +#define GPSR1_A13 ((uint32_t)1U << 13U) +#define GPSR1_A12 ((uint32_t)1U << 12U) +#define GPSR1_A11 ((uint32_t)1U << 11U) +#define GPSR1_A10 ((uint32_t)1U << 10U) +#define GPSR1_A9 ((uint32_t)1U << 9U) +#define GPSR1_A8 ((uint32_t)1U << 8U) +#define GPSR1_A7 ((uint32_t)1U << 7U) +#define GPSR1_A6 ((uint32_t)1U << 6U) +#define GPSR1_A5 ((uint32_t)1U << 5U) +#define GPSR1_A4 ((uint32_t)1U << 4U) +#define GPSR1_A3 ((uint32_t)1U << 3U) +#define GPSR1_A2 ((uint32_t)1U << 2U) +#define GPSR1_A1 ((uint32_t)1U << 1U) +#define GPSR1_A0 ((uint32_t)1U << 0U) +#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U) +#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U) +#define GPSR2_AVB_LINK ((uint32_t)1U << 12U) +#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U) +#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U) +#define GPSR2_AVB_MDC ((uint32_t)1U << 9U) +#define GPSR2_PWM2_A ((uint32_t)1U << 8U) +#define GPSR2_PWM1_A ((uint32_t)1U << 7U) +#define GPSR2_PWM0 ((uint32_t)1U << 6U) +#define GPSR2_IRQ5 ((uint32_t)1U << 5U) +#define GPSR2_IRQ4 ((uint32_t)1U << 4U) +#define GPSR2_IRQ3 ((uint32_t)1U << 3U) +#define GPSR2_IRQ2 ((uint32_t)1U << 2U) +#define GPSR2_IRQ1 ((uint32_t)1U << 1U) +#define GPSR2_IRQ0 ((uint32_t)1U << 0U) +#define GPSR3_SD1_WP ((uint32_t)1U << 15U) +#define GPSR3_SD1_CD ((uint32_t)1U << 14U) +#define GPSR3_SD0_WP ((uint32_t)1U << 13U) +#define GPSR3_SD0_CD ((uint32_t)1U << 12U) +#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U) +#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U) +#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U) +#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U) +#define GPSR3_SD1_CMD ((uint32_t)1U << 7U) +#define GPSR3_SD1_CLK ((uint32_t)1U << 6U) +#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U) +#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U) +#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U) +#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U) +#define GPSR3_SD0_CMD ((uint32_t)1U << 1U) +#define GPSR3_SD0_CLK ((uint32_t)1U << 0U) +#define GPSR4_SD3_DS ((uint32_t)1U << 17U) +#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U) +#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U) +#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U) +#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U) +#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U) +#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U) +#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U) +#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U) +#define GPSR4_SD3_CMD ((uint32_t)1U << 8U) +#define GPSR4_SD3_CLK ((uint32_t)1U << 7U) +#define GPSR4_SD2_DS ((uint32_t)1U << 6U) +#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U) +#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U) +#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U) +#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U) +#define GPSR4_SD2_CMD ((uint32_t)1U << 1U) +#define GPSR4_SD2_CLK ((uint32_t)1U << 0U) +#define GPSR5_MLB_DAT ((uint32_t)1U << 25U) +#define GPSR5_MLB_SIG ((uint32_t)1U << 24U) +#define GPSR5_MLB_CLK ((uint32_t)1U << 23U) +#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U) +#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U) +#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U) +#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U) +#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U) +#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U) +#define GPSR5_HRTS0 ((uint32_t)1U << 16U) +#define GPSR5_HCTS0 ((uint32_t)1U << 15U) +#define GPSR5_HTX0 ((uint32_t)1U << 14U) +#define GPSR5_HRX0 ((uint32_t)1U << 13U) +#define GPSR5_HSCK0 ((uint32_t)1U << 12U) +#define GPSR5_RX2_A ((uint32_t)1U << 11U) +#define GPSR5_TX2_A ((uint32_t)1U << 10U) +#define GPSR5_SCK2 ((uint32_t)1U << 9U) +#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U) +#define GPSR5_CTS1 ((uint32_t)1U << 7U) +#define GPSR5_TX1_A ((uint32_t)1U << 6U) +#define GPSR5_RX1_A ((uint32_t)1U << 5U) +#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U) +#define GPSR5_CTS0 ((uint32_t)1U << 3U) +#define GPSR5_TX0 ((uint32_t)1U << 2U) +#define GPSR5_RX0 ((uint32_t)1U << 1U) +#define GPSR5_SCK0 ((uint32_t)1U << 0U) +#define GPSR6_USB31_OVC ((uint32_t)1U << 31U) +#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U) +#define GPSR6_USB30_OVC ((uint32_t)1U << 29U) +#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U) +#define GPSR6_USB1_OVC ((uint32_t)1U << 27U) +#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U) +#define GPSR6_USB0_OVC ((uint32_t)1U << 25U) +#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U) +#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U) +#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U) +#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U) +#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U) +#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U) +#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U) +#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U) +#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U) +#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U) +#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U) +#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U) +#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U) +#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U) +#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U) +#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U) +#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U) +#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U) +#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U) +#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U) +#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U) +#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U) +#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U) +#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U) +#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U) +#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U) +#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U) +#define GPSR7_AVS2 ((uint32_t)1U << 1U) +#define GPSR7_AVS1 ((uint32_t)1U << 0U) + +#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) +#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) +#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) +#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) +#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) +#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) +#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) +#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) + +#define POC_SD3_DS_33V ((uint32_t)1U << 29U) +#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U) +#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U) +#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U) +#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U) +#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U) +#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U) +#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U) +#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U) +#define POC_SD3_CMD_33V ((uint32_t)1U << 20U) +#define POC_SD3_CLK_33V ((uint32_t)1U << 19U) +#define POC_SD2_DS_33V ((uint32_t)1U << 18U) +#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U) +#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U) +#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U) +#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U) +#define POC_SD2_CMD_33V ((uint32_t)1U << 13U) +#define POC_SD2_CLK_33V ((uint32_t)1U << 12U) +#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U) +#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U) +#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U) +#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U) +#define POC_SD1_CMD_33V ((uint32_t)1U << 7U) +#define POC_SD1_CLK_33V ((uint32_t)1U << 6U) +#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U) +#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U) +#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U) +#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U) +#define POC_SD0_CMD_33V ((uint32_t)1U << 1U) +#define POC_SD0_CLK_33V ((uint32_t)1U << 0U) + +#define DRVCTRL0_MASK (0xCCCCCCCCU) +#define DRVCTRL1_MASK (0xCCCCCCC8U) +#define DRVCTRL2_MASK (0x88888888U) +#define DRVCTRL3_MASK (0x88888888U) +#define DRVCTRL4_MASK (0x88888888U) +#define DRVCTRL5_MASK (0x88888888U) +#define DRVCTRL6_MASK (0x88888888U) +#define DRVCTRL7_MASK (0x88888888U) +#define DRVCTRL8_MASK (0x88888888U) +#define DRVCTRL9_MASK (0x88888888U) +#define DRVCTRL10_MASK (0x88888888U) +#define DRVCTRL11_MASK (0x888888CCU) +#define DRVCTRL12_MASK (0xCCCFFFCFU) +#define DRVCTRL13_MASK (0xCC888888U) +#define DRVCTRL14_MASK (0x88888888U) +#define DRVCTRL15_MASK (0x88888888U) +#define DRVCTRL16_MASK (0x88888888U) +#define DRVCTRL17_MASK (0x88888888U) +#define DRVCTRL18_MASK (0x88888888U) +#define DRVCTRL19_MASK (0x88888888U) +#define DRVCTRL20_MASK (0x88888888U) +#define DRVCTRL21_MASK (0x88888888U) +#define DRVCTRL22_MASK (0x88888888U) +#define DRVCTRL23_MASK (0x88888888U) +#define DRVCTRL24_MASK (0x8888888FU) + +#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U) +#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U) +#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U) +#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U) +#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U) +#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U) +#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U) +#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U) +#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U) +#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U) +#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U) +#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U) +#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U) +#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U) +#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U) +#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U) +#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U) +#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U) +#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U) +#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U) +#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U) +#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U) +#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U) +#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) +#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) +#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U) +#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U) +#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U) +#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U) +#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U) +#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) +#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U) +#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U) +#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U) +#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U) +#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U) +#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U) +#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U) +#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U) +#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U) +#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U) +#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U) +#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U) +#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U) +#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U) +#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U) +#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U) +#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U) +#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) +#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) +#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U) +#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U) +#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U) +#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U) +#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U) +#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U) +#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U) +#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U) +#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U) +#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U) +#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U) +#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U) +#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U) +#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U) +#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U) +#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U) +#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U) +#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U) +#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U) +#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U) +#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U) +#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U) +#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U) +#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U) +#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U) +#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U) +#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U) +#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U) +#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U) +#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U) +#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U) +#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U) +#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U) +#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U) +#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U) +#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U) +#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U) +#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U) +#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U) +#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U) +#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U) +#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U) +#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U) +#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U) +#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U) +#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U) +#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U) +#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U) +#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U) +#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U) +#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U) +#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U) +#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U) +#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U) +#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U) +#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U) +#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U) +#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U) +#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U) +#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U) +#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U) +#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U) +#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U) +#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U) +#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U) +#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U) +#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U) +#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U) +#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U) +#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U) +#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U) +#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U) +#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U) +#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U) +#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U) +#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U) +#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U) +#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U) +#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U) +#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U) +#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U) +#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U) +#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U) +#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U) +#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U) +#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U) + +#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U) +#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U) +#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U) +#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U) +#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U) +#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U) +#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U) +#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U) +#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U) +#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U) +#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U) +#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U) +#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U) +#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U) +#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U) +#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U) +#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U) +#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U) +#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U) +#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U) +#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U) +#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U) +#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U) +#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U) +#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U) +#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U) +#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U) +#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U) +#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U) +#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U) +#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U) +#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U) +#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U) +#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U) +#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U) +#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U) +#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U) +#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U) +#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U) +#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U) +#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U) +#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U) +#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U) +#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U) +#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U) +#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U) +#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U) +#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U) +#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U) +#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U) +#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U) +#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U) +#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U) +#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U) +#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U) +#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U) +#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U) +#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U) +#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U) +#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U) +#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U) +#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U) +#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U) +#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U) +#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U) +#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U) +#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U) +#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U) +#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U) +#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U) +#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U) +#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U) +#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U) +#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U) +#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U) +#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U) +#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U) +#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U) +#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U) +#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U) +#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U) +#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U) +#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U) +#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U) +#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U) +#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U) +#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U) +#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) +#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) +#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U) +#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U) +#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U) +#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U) +#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U) +#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U) +#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U) +#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U) +#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U) +#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U) +#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U) +#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U) +#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U) +#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U) +#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U) +#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U) +#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U) +#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U) +#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U) +#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U) +#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U) +#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U) +#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U) +#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U) +#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U) +#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U) +#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U) +#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U) +#define MOD_SEL2_FM_A ((uint32_t)0U << 27U) +#define MOD_SEL2_FM_B ((uint32_t)1U << 27U) +#define MOD_SEL2_FM_C ((uint32_t)2U << 27U) +#define MOD_SEL2_FM_D ((uint32_t)3U << 27U) +#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U) +#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U) +#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U) +#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U) +#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U) +#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U) +#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U) +#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U) +#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U) +#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U) +#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U) +#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U) +#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U) +#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U) +#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U) +#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U) +#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U) +#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U) +#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U) + + +/* SCIF3 Registers for Dummy write */ +#define SCIF3_BASE (0xE6C50000U) +#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) +#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) +#define SCFCR_DATA (0x0000U) + +/* Realtime module stop control */ +#define CPG_BASE (0xE6150000U) +#define CPG_MSTPSR0 (CPG_BASE + 0x0030U) +#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) +#define RMSTPCR0_RTDMAC (0x00200000U) + +/* RT-DMAC Registers */ +#define RTDMAC_CH (0U) /* choose 0 to 15 */ + +#define RTDMAC_BASE (0xFFC10000U) +#define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U) +#define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U) +#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x))) +#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x))) +#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x))) +#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x))) +#define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x))) +#define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x))) +#define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U) +#define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U) +#define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U) +#define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U) + +#define RDMOR_DME (0x0001U) /* DMA Master Enable */ +#define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */ +#define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */ +#define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */ +#define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */ +#define RDMCHCR_DE (0x00000001U) /* DMA Enable */ +#define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */ +#define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */ +#define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */ + + +static void pfc_reg_write(uint32_t addr, uint32_t data); + +static void pfc_reg_write(uint32_t addr, uint32_t data) +{ + uint32_t prr; + + prr = mmio_read_32(RCAR_PRR); + prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + + mmio_write_32(PFC_PMMR, ~data); + if (prr == (RCAR_PRODUCT_M3_CUT10)) { + mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ + } + mmio_write_32((uintptr_t)addr, data); + if (prr == (RCAR_PRODUCT_M3_CUT10)) { + mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ + } +} + + +void pfc_init_d3(void) +{ + /* initialize module select */ + pfc_reg_write(PFC_MOD_SEL0, 0x00000000U); + pfc_reg_write(PFC_MOD_SEL1, 0x00000000U); + + /* initialize peripheral function select */ + pfc_reg_write(PFC_IPSR0, 0x00000001U); + pfc_reg_write(PFC_IPSR1, 0x00000000U); + pfc_reg_write(PFC_IPSR2, 0x00000000U); + pfc_reg_write(PFC_IPSR3, 0x00000000U); + pfc_reg_write(PFC_IPSR4, 0x00002000U); + pfc_reg_write(PFC_IPSR5, 0x00000000U); + pfc_reg_write(PFC_IPSR6, 0x00000000U); + pfc_reg_write(PFC_IPSR7, 0x00000000U); + pfc_reg_write(PFC_IPSR8, 0x11003301U); + pfc_reg_write(PFC_IPSR9, 0x11111111U); + pfc_reg_write(PFC_IPSR10, 0x00020000U); + pfc_reg_write(PFC_IPSR11, 0x40001110U); + pfc_reg_write(PFC_IPSR12, 0x00000000U); + pfc_reg_write(PFC_IPSR13, 0x00000000U); + + /* initialize GPIO/perihperal function select */ + pfc_reg_write(PFC_GPSR0, 0x0000001FU); + pfc_reg_write(PFC_GPSR1, 0x3FFFFFFFU); + pfc_reg_write(PFC_GPSR2, 0xFFFFFFFFU); + pfc_reg_write(PFC_GPSR3, 0x000003FFU); + pfc_reg_write(PFC_GPSR4, 0xFC7F0F7EU); + pfc_reg_write(PFC_GPSR5, 0x001BFFFBU); + pfc_reg_write(PFC_GPSR6, 0x00003FFFU); + + /* initialize POC control register */ + pfc_reg_write(PFC_POCCTRL0, 0xC00FFFFFU); + pfc_reg_write(PFC_POCCTRL1, 0XFFFFFFFEU); + pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U); + + /* initialize LSI pin pull-up/down control */ + pfc_reg_write(PFC_PUD0, 0x0047C1A2U); + pfc_reg_write(PFC_PUD1, 0x4E13ABFFU); + pfc_reg_write(PFC_PUD2, 0xFFFFFFFFU); + pfc_reg_write(PFC_PUD3, 0xFF0FFFFFU); + pfc_reg_write(PFC_PUD4, 0xE0000000U); + pfc_reg_write(PFC_PUD5, 0x60000000U); + + /* initialize LSI pin pull-enable register */ + pfc_reg_write(PFC_PUEN0, 0x00000000U); + pfc_reg_write(PFC_PUEN1, 0x00000000U); + pfc_reg_write(PFC_PUEN2, 0x00000000U); + pfc_reg_write(PFC_PUEN3, 0x000F008CU); + pfc_reg_write(PFC_PUEN4, 0x00000000U); + pfc_reg_write(PFC_PUEN5, 0x00000000U); + + /* initialize positive/negative logic select */ + mmio_write_32(GPIO_POSNEG0, 0x00000000U); + mmio_write_32(GPIO_POSNEG1, 0x00000000U); + mmio_write_32(GPIO_POSNEG2, 0x00000000U); + mmio_write_32(GPIO_POSNEG3, 0x00000000U); + mmio_write_32(GPIO_POSNEG4, 0x00000000U); + mmio_write_32(GPIO_POSNEG5, 0x00000000U); + mmio_write_32(GPIO_POSNEG6, 0x00000000U); + + /* initialize general IO/interrupt switching */ + mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); + + /* initialize general output register */ + mmio_write_32(GPIO_OUTDT0, 0x00000000U); + mmio_write_32(GPIO_OUTDT1, 0x00000000U); + mmio_write_32(GPIO_OUTDT2, 0x00000400U); + mmio_write_32(GPIO_OUTDT3, 0x00000000U); + mmio_write_32(GPIO_OUTDT4, 0x00000000U); + mmio_write_32(GPIO_OUTDT5, 0x00000006U); + mmio_write_32(GPIO_OUTDT6, 0x00003880U); + + /* initialize general input/output switching */ + mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL1, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL2, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL3, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL4, 0x00802000U); + mmio_write_32(GPIO_INOUTSEL5, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL6, 0x00000000U); +} diff --git a/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h new file mode 100644 index 000000000..ee1fada3b --- /dev/null +++ b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PFC_INIT_D3_H__ +#define PFC_INIT_D3_H__ + +void pfc_init_d3(void); + +#endif /* PFC_INIT_D3_H__ */ diff --git a/drivers/staging/renesas/rcar/pfc/pfc.mk b/drivers/staging/renesas/rcar/pfc/pfc.mk index 40e409000..5703558fa 100644 --- a/drivers/staging/renesas/rcar/pfc/pfc.mk +++ b/drivers/staging/renesas/rcar/pfc/pfc.mk @@ -28,6 +28,9 @@ else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_E3}) BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c endif + ifeq (${RCAR_LSI},${RCAR_D3}) + BL2_SOURCES += drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c + endif else ifeq (${RCAR_LSI},${RCAR_H3}) ifeq (${LSI_CUT},10) @@ -51,6 +54,9 @@ else ifeq (${RCAR_LSI},${RCAR_E3}) BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c endif + ifeq (${RCAR_LSI},${RCAR_D3}) + BL2_SOURCES += drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c + endif endif BL2_SOURCES += drivers/staging/renesas/rcar/pfc/pfc_init.c diff --git a/drivers/staging/renesas/rcar/pfc/pfc_init.c b/drivers/staging/renesas/rcar/pfc/pfc_init.c index f20e8b0b5..cec562409 100644 --- a/drivers/staging/renesas/rcar/pfc/pfc_init.c +++ b/drivers/staging/renesas/rcar/pfc/pfc_init.c @@ -29,6 +29,9 @@ #if RCAR_LSI == RCAR_E3 /* E3 */ #include "E3/pfc_init_e3.h" #endif +#if RCAR_LSI == RCAR_D3 /* D3 */ +#include "D3/pfc_init_d3.h" +#endif /* Product Register */ #define PRR (0xFFF00044U) @@ -38,6 +41,7 @@ #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ #define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ +#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */ #define PRR_PRODUCT_10 (0x00U) #define PRR_PRODUCT_11 (0x01U) #define PRR_PRODUCT_20 (0x10U) @@ -124,6 +128,13 @@ void rcar_pfc_init(void) pfc_init_e3(); #endif break; + case PRR_PRODUCT_D3: +#if RCAR_LSI != RCAR_D3 + PRR_PRODUCT_ERR(reg); +#else + pfc_init_d3(); +#endif + break; default: PRR_PRODUCT_ERR(reg); break; @@ -167,6 +178,11 @@ void rcar_pfc_init(void) PRR_PRODUCT_ERR(reg); } pfc_init_e3(); +#elif RCAR_LSI == RCAR_D3 /* D3 */ + if ((PRR_PRODUCT_D3) != (reg & PRR_PRODUCT_MASK)) { + PRR_PRODUCT_ERR(reg); + } + pfc_init_d3(); #else #error "Don't have PFC initialize routine(unknown)." #endif diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c new file mode 100644 index 000000000..b115d633b --- /dev/null +++ b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> +#include <common/debug.h> +#include "qos_init_d3.h" + + +#define RCAR_QOS_VERSION "rev.0.05" + +#define RCAR_QOS_NONE (3U) +#define RCAR_QOS_TYPE_DEFAULT (0U) + +#define RCAR_DRAM_SPLIT_LINEAR (0U) +#define RCAR_DRAM_SPLIT_4CH (1U) +#define RCAR_DRAM_SPLIT_2CH (2U) +#define RCAR_DRAM_SPLIT_AUTO (3U) + +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) + +#define DBSC_BASE (0xE6790000U) +#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_AXARB (DBSC_BASE + 0x0800U) +#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) +#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) +#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) +#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) +#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) +#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) +#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) +#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) +#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) +#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) +#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) +#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) +#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) +#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) +#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) +#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) +#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) +#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) +#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) +#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) +#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) +#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) +#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) +#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) +#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) +#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) +#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) +#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) +#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) +#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) +#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) +#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) +#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) +#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) + +#define AXI_BASE (0xE6784000U) +#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) +#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) + +#define MSTAT_BASE (0xE67E0000U) +#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) +#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) +#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) +#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) +#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) +#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) + +#define RALLOC_BASE (0xE67F0000U) +#define RALLOC_RAS (RALLOC_BASE + 0x0000U) +#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) +#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) +#define RALLOC_REGGD (RALLOC_BASE + 0x0020U) +#define RALLOC_DANN (RALLOC_BASE + 0x0030U) +#define RALLOC_DANT (RALLOC_BASE + 0x0038U) +#define RALLOC_EC (RALLOC_BASE + 0x003CU) +#define RALLOC_EMS (RALLOC_BASE + 0x0040U) +#define RALLOC_FSS (RALLOC_BASE + 0x0048U) +#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) +#define RALLOC_BERR (RALLOC_BASE + 0x0054U) +#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U) +#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) +#define RALLOC_TICKDUPL (RALLOC_BASE + 0x0088U) + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +static inline void io_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} + +static inline void io_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +typedef struct { + uintptr_t addr; + uint64_t value; +} mstat_slot_t; + + +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT +static const mstat_slot_t mstat_fix[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x001004340000FFFFU}, + {0x0038U, 0x001004140000FFFFU}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x00140B030000FFFFU}, + {0x0060U, 0x001408610000FFFFU}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x001410620000FFFFU}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x000C041C0000FFFFU}, + {0x00A8U, 0x000C04090000FFFFU}, + {0x00B0U, 0x000C04110000FFFFU}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x000C041C0000FFFFU}, + {0x00C8U, 0x000C04090000FFFFU}, + {0x00D0U, 0x000C04110000FFFFU}, + {0x00D8U, 0x0000000000000000U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x001018570000FFFFU}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x001008570000FFFFU}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x0000000000000000U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x001008520000FFFFU}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x0000000000000000U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x0000000000000000U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x00100CA30000FFFFU}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x0000000000000000U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x0000000000000000U}, + {0x01C8U, 0x0000000000000000U}, + {0x01D0U, 0x0000000000000000U}, + {0x01D8U, 0x0000000000000000U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x000C04020000FFFFU}, + {0x01F0U, 0x0000000000000000U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x000C04090000FFFFU}, + {0x0210U, 0x0000000000000000U}, + {0x0218U, 0x0000000000000000U}, + {0x0220U, 0x0000000000000000U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x0000000000000000U}, + {0x0238U, 0x0000000000000000U}, + {0x0240U, 0x0000000000000000U}, + {0x0248U, 0x0000000000000000U}, + {0x0250U, 0x0000000000000000U}, + {0x0258U, 0x0000000000000000U}, + {0x0260U, 0x0000000000000000U}, + {0x0268U, 0x001410040000FFFFU}, + {0x0270U, 0x001404020000FFFFU}, + {0x0278U, 0x0000000000000000U}, + {0x0280U, 0x0000000000000000U}, + {0x0288U, 0x0000000000000000U}, + {0x0290U, 0x001410040000FFFFU}, + {0x0298U, 0x001404020000FFFFU}, + {0x02A0U, 0x000C04050000FFFFU}, + {0x02A8U, 0x000C04050000FFFFU}, + {0x02B0U, 0x0000000000000000U}, + {0x02B8U, 0x0000000000000000U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x000C04050000FFFFU}, + {0x02D8U, 0x000C04050000FFFFU}, + {0x02E0U, 0x0000000000000000U}, + {0x02E8U, 0x0000000000000000U}, + {0x02F0U, 0x0000000000000000U}, + {0x02F8U, 0x0000000000000000U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x0000000000000000U}, + {0x0310U, 0x0000000000000000U}, + {0x0318U, 0x0000000000000000U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, + {0x0340U, 0x0000000000000000U}, + {0x0348U, 0x0000000000000000U}, + {0x0350U, 0x0000000000000000U}, + {0x0358U, 0x0000000000000000U}, + {0x0360U, 0x0000000000000000U}, + {0x0368U, 0x0000000000000000U}, + {0x0370U, 0x000C04020000FFFFU}, + {0x0378U, 0x000C04020000FFFFU}, + {0x0380U, 0x000C04090000FFFFU}, + {0x0388U, 0x000C04090000FFFFU}, + {0x0390U, 0x0000000000000000U}, +}; + +static const mstat_slot_t mstat_be[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x0000000000000000U}, + {0x0060U, 0x0000000000000000U}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x0000000000000000U}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x0000000000000000U}, + {0x00A8U, 0x0000000000000000U}, + {0x00B0U, 0x0000000000000000U}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x0000000000000000U}, + {0x00C8U, 0x0000000000000000U}, + {0x00D0U, 0x0000000000000000U}, + {0x00D8U, 0x0000000000000000U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x0000000000000000U}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x0000000000000000U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x0000000000000000U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x0000000000000000U}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x0000000000000000U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x0000000000000000U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x0000000000000000U}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x0000000000000000U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x00110090060FA001U}, + {0x01C8U, 0x00110090060FA001U}, + {0x01D0U, 0x0000000000000000U}, + {0x01D8U, 0x0000000000000000U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x0000000000000000U}, + {0x01F0U, 0x0011001006004401U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x0000000000000000U}, + {0x0210U, 0x0011001006004401U}, + {0x0218U, 0x0011001006009801U}, + {0x0220U, 0x0011001006009801U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x0011001006009801U}, + {0x0238U, 0x0011001006009801U}, + {0x0240U, 0x0000000000000000U}, + {0x0248U, 0x0000000000000000U}, + {0x0250U, 0x0000000000000000U}, + {0x0258U, 0x0000000000000000U}, + {0x0260U, 0x0000000000000000U}, + {0x0268U, 0x0000000000000000U}, + {0x0270U, 0x0000000000000000U}, + {0x0278U, 0x0000000000000000U}, + {0x0280U, 0x0000000000000000U}, + {0x0288U, 0x0000000000000000U}, + {0x0290U, 0x0000000000000000U}, + {0x0298U, 0x0000000000000000U}, + {0x02A0U, 0x0000000000000000U}, + {0x02A8U, 0x0000000000000000U}, + {0x02B0U, 0x0000000000000000U}, + {0x02B8U, 0x0011001006003401U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x0000000000000000U}, + {0x02D8U, 0x0000000000000000U}, + {0x02E0U, 0x0000000000000000U}, + {0x02E8U, 0x0011001006003401U}, + {0x02F0U, 0x00110090060FA001U}, + {0x02F8U, 0x00110090060FA001U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x0000000000000000U}, + {0x0310U, 0x0000000000000000U}, + {0x0318U, 0x0012001006003401U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, + {0x0340U, 0x0000000000000000U}, + {0x0348U, 0x0000000000000000U}, + {0x0350U, 0x0000000000000000U}, + {0x0358U, 0x00120090060FA001U}, + {0x0360U, 0x00120090060FA001U}, + {0x0368U, 0x0012001006003401U}, + {0x0370U, 0x0000000000000000U}, + {0x0378U, 0x0000000000000000U}, + {0x0380U, 0x0000000000000000U}, + {0x0388U, 0x0000000000000000U}, + {0x0390U, 0x0012001006003401U}, +}; +#endif + +static void dbsc_setting(void) +{ + uint32_t md=0; + + /* BUFCAM settings */ + //DBSC_DBCAM0CNF0 not set + io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1 + io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2 + io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0 + //DBSC_DBSCHCNT1 not set + io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0 + io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0 + + md = (*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 19; + + switch (md) { + case 0x0: //MD19=0 : DDR3L-1600, 4GByte(1GByte x4) + /* DDR1600 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + default: //MD19=1 : DDR3L-1856, 4GByte(1GByte x4) + /* DDR1856 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + } + + /* QoS Settings */ + io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00); + io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00); + io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000); + io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000); + //DBSC_DBSCHQOS_1_0 not set + //DBSC_DBSCHQOS_1_1 not set + //DBSC_DBSCHQOS_1_2 not set + //DBSC_DBSCHQOS_1_3 not set + //DBSC_DBSCHQOS_2_0 not set + //DBSC_DBSCHQOS_2_1 not set + //DBSC_DBSCHQOS_2_2 not set + //DBSC_DBSCHQOS_2_3 not set + //DBSC_DBSCHQOS_3_0 not set + //DBSC_DBSCHQOS_3_1 not set + //DBSC_DBSCHQOS_3_2 not set + //DBSC_DBSCHQOS_3_3 not set + io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300); + io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0); + io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200); + io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100); + //DBSC_DBSCHQOS_5_0 not set + //DBSC_DBSCHQOS_5_1 not set + //DBSC_DBSCHQOS_5_2 not set + //DBSC_DBSCHQOS_5_3 not set + //DBSC_DBSCHQOS_6_0 not set + //DBSC_DBSCHQOS_6_1 not set + //DBSC_DBSCHQOS_6_2 not set + //DBSC_DBSCHQOS_6_3 not set + //DBSC_DBSCHQOS_7_0 not set + //DBSC_DBSCHQOS_7_1 not set + //DBSC_DBSCHQOS_7_2 not set + //DBSC_DBSCHQOS_7_3 not set + //DBSC_DBSCHQOS_8_0 not set + //DBSC_DBSCHQOS_8_1 not set + //DBSC_DBSCHQOS_8_2 not set + //DBSC_DBSCHQOS_8_3 not set + io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300); + io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0); + io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200); + io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100); + //DBSC_DBSCHQOS_10_0 not set + //DBSC_DBSCHQOS_10_1 not set + //DBSC_DBSCHQOS_10_2 not set + //DBSC_DBSCHQOS_10_3 not set + //DBSC_DBSCHQOS_11_0 not set + //DBSC_DBSCHQOS_11_1 not set + //DBSC_DBSCHQOS_11_2 not set + //DBSC_DBSCHQOS_11_3 not set + //DBSC_DBSCHQOS_12_0 not set + //DBSC_DBSCHQOS_12_1 not set + //DBSC_DBSCHQOS_12_2 not set + //DBSC_DBSCHQOS_12_3 not set + io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100); + io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0); + io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0); + io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040); + io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0); + io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0); + io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080); + io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040); + io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040); + io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030); + io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020); + io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010); +} + +void qos_init_d3(void) +{ + io_write_32(DBSC_DBSYSCNT0, 0x00001234); + + dbsc_setting(); + + /* DRAM Split Address mapping */ +#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH + ERROR("DRAM Split 4ch not supported.(D3)"); + panic(); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH + ERROR("DRAM Split 2ch not supported.(D3)"); + panic(); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO + ERROR("DRAM Split Auto not supported.(D3)"); + panic(); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR +/* NOTICE("BL2: DRAM Split is OFF\n"); */ + /* Split setting(DDR 1ch) */ + io_write_32(AXI_ADSPLCR0, 0x00000000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#else + ERROR("DRAM split is an invalid value.(D3)"); + panic(); +#endif + +#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT + NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); +#endif + + /* Resource Alloc setting */ + io_write_32(RALLOC_RAS, 0x00000020U); + io_write_32(RALLOC_FIXTH, 0x000F0005U); + io_write_32(RALLOC_RAEN, 0x00000001U); + io_write_32(RALLOC_REGGD, 0x00000000U); + io_write_64(RALLOC_DANN, 0x0404020002020201U); + io_write_32(RALLOC_DANT, 0x00100804U); + io_write_32(RALLOC_EC, 0x00000000U); + io_write_64(RALLOC_EMS, 0x0000000000000000U); + io_write_32(RALLOC_FSS, 0x0000000AU); + io_write_32(RALLOC_INSFC, 0xC7840001U); + io_write_32(RALLOC_BERR, 0x00000000U); + io_write_32(RALLOC_EARLYR, 0x00000000U); + io_write_32(RALLOC_RACNT0, 0x00010003U); + io_write_32(RALLOC_TICKDUPL, 0x00000000U); + + /* GPU setting */ + io_write_32(0xFD812030U, 0x00000000U); + + /* MSTAT setting */ + io_write_32(MSTAT_SL_INIT, 0x030500ACU); + io_write_32(MSTAT_REF_ARS, 0x00780000U); + + /* MSTAT SRAM setting */ + { + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { + io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, + mstat_fix[i].value); + io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, + mstat_fix[i].value); + } + for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { + io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, + mstat_be[i].value); + io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, + mstat_be[i].value); + } + } + + /* 3DG bus Leaf setting */ + io_write_32(0xFD820808U, 0x00001234U); + io_write_32(0xFD820800U, 0x00000000U); + io_write_32(0xFD821800U, 0x00000000U); + io_write_32(0xFD822800U, 0x00000000U); + io_write_32(0xFD823800U, 0x00000000U); + + /* RT bus Leaf setting */ + io_write_32(0xF1300800U, 0x00000003U); + io_write_32(0xF1340800U, 0x00000003U); + io_write_32(0xFFC50800U, 0x00000000U); + io_write_32(0xFFC51800U, 0x00000000U); + + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); + + /* MSTAT start */ + io_write_32(MSTAT_STATQC, 0x00000001U); +#else + NOTICE("BL2: QoS is None\n"); + + /* Resource Alloc setting */ + io_write_32(RALLOC_EC, 0x00000000U); + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); +#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ + io_write_32(DBSC_DBSYSCNT0, 0x00000000); +} diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h new file mode 100644 index 000000000..968ee7a47 --- /dev/null +++ b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef QOS_INIT_H_D3__ +#define QOS_INIT_H_D3__ + +void qos_init_d3(void); + +#endif /* QOS_INIT_H_D3__ */ diff --git a/drivers/staging/renesas/rcar/qos/qos.mk b/drivers/staging/renesas/rcar/qos/qos.mk index 9fabc56f8..77b3c6179 100644 --- a/drivers/staging/renesas/rcar/qos/qos.mk +++ b/drivers/staging/renesas/rcar/qos/qos.mk @@ -35,6 +35,9 @@ else ifdef RCAR_LSI_CUT_COMPAT ifeq (${RCAR_LSI},${RCAR_E3}) BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c endif + ifeq (${RCAR_LSI},${RCAR_D3}) + BL2_SOURCES += drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c + endif else ifeq (${RCAR_LSI},${RCAR_H3}) ifeq (${LSI_CUT},10) @@ -88,6 +91,9 @@ else BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c endif endif + ifeq (${RCAR_LSI},${RCAR_D3}) + BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_d3.c + endif endif BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c diff --git a/drivers/staging/renesas/rcar/qos/qos_init.c b/drivers/staging/renesas/rcar/qos/qos_init.c index affd42502..895f43f5b 100644 --- a/drivers/staging/renesas/rcar/qos/qos_init.c +++ b/drivers/staging/renesas/rcar/qos/qos_init.c @@ -41,6 +41,9 @@ #if RCAR_LSI == RCAR_E3 /* E3 */ #include "E3/qos_init_e3_v10.h" #endif +#if RCAR_LSI == RCAR_D3 /* D3 */ +#include "D3/qos_init_d3.h" +#endif /* Product Register */ #define PRR (0xFFF00044U) @@ -50,13 +53,14 @@ #define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ #define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ #define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ +#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */ #define PRR_PRODUCT_10 (0x00U) #define PRR_PRODUCT_11 (0x01U) #define PRR_PRODUCT_20 (0x10U) #define PRR_PRODUCT_21 (0x11U) #define PRR_PRODUCT_30 (0x20U) -#if !(RCAR_LSI == RCAR_E3) +#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) #define DRAM_CH_CNT 0x04 uint32_t qos_init_ddr_ch; @@ -81,7 +85,7 @@ uint8_t qos_init_ddr_phyvalid; void rcar_qos_init(void) { uint32_t reg; -#if !(RCAR_LSI == RCAR_E3) +#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) uint32_t i; qos_init_ddr_ch = 0; @@ -166,6 +170,18 @@ void rcar_qos_init(void) PRR_PRODUCT_ERR(reg); #endif break; + case PRR_PRODUCT_D3: +#if (RCAR_LSI == RCAR_D3) + switch (reg & PRR_CUT_MASK) { + case PRR_PRODUCT_10: + default: + qos_init_d3(); + break; + } +#else + PRR_PRODUCT_ERR(reg); +#endif + break; default: PRR_PRODUCT_ERR(reg); break; @@ -245,6 +261,13 @@ void rcar_qos_init(void) PRR_PRODUCT_ERR(reg); } qos_init_m3n_v10(); +#elif RCAR_LSI == RCAR_D3 /* D3 */ + /* D3 Cut 10 or later */ + if ((PRR_PRODUCT_D3) + != (reg & (PRR_PRODUCT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + qos_init_d3(); #elif RCAR_LSI == RCAR_E3 /* E3 */ /* E3 Cut 10 or later */ if ((PRR_PRODUCT_E3) @@ -258,7 +281,7 @@ void rcar_qos_init(void) #endif } -#if !(RCAR_LSI == RCAR_E3) +#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) uint32_t get_refperiod(void) { uint32_t refperiod = QOSWT_WTSET0_CYCLE; diff --git a/include/drivers/meson/gxl/crypto/sha_dma.h b/include/drivers/meson/gxl/crypto/sha_dma.h new file mode 100644 index 000000000..52129a61f --- /dev/null +++ b/include/drivers/meson/gxl/crypto/sha_dma.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2019, Remi Pommarel <repk@triplefau.lt> + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef SHA_DMA_H +#define SHA_DMA_H + +#define SHA256_HASHSZ 32 +#define SHA256_BLOCKSZ 0x40 + +enum ASD_MODE { + ASM_INVAL, + ASM_SHA256, + ASM_SHA224, +}; + +struct asd_ctx { + uint8_t digest[SHA256_HASHSZ]; + uint8_t block[SHA256_BLOCKSZ]; + size_t blocksz; + enum ASD_MODE mode; + uint8_t started; +}; + +static inline void asd_sha_init(struct asd_ctx *ctx, enum ASD_MODE mode) +{ + ctx->started = 0; + ctx->mode = mode; + ctx->blocksz = 0; +} + +void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len); +void asd_sha_finalize(struct asd_ctx *ctx); + +#endif diff --git a/maintainers.rst b/maintainers.rst index a1ad137fe..52c3daca1 100644 --- a/maintainers.rst +++ b/maintainers.rst @@ -34,6 +34,14 @@ Amlogic Meson S905 (GXBB) platform port :F: drivers/meson/ :F: plat/meson/gxbb/ +Amlogic Meson S905x (GXL) platform port +--------------------------------------- +:M: Remi Pommarel <repk@triplefau.lt> +:G: `remi-triplefault`_ +:F: docs/plat/meson-gxl.rst +:F: drivers/meson/gxl +:F: plat/meson/gxl/ + Armv7-A architecture port ------------------------- :M: Etienne Carriere <etienne.carriere@linaro.org> @@ -272,6 +280,7 @@ Xilinx platform port .. _mtk09422: https://github.com/mtk09422 .. _npoushin: https://github.com/npoushin .. _qoriq-open-source: https://github.com/qoriq-open-source +.. _remi-triplefault: https://github.com/repk .. _rockchip-linux: https://github.com/rockchip-linux .. _shawnguo2: https://github.com/shawnguo2 .. _sivadur: https://github.com/sivadur diff --git a/plat/meson/gxl/aarch64/gxl_helpers.S b/plat/meson/gxl/aarch64/gxl_helpers.S new file mode 100644 index 000000000..760d6c46d --- /dev/null +++ b/plat/meson/gxl/aarch64/gxl_helpers.S @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <assert_macros.S> +#include <platform_def.h> + + .globl plat_crash_console_flush + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_reset_handler + .globl plat_gxbb_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void); + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_gxbb_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); + * ----------------------------------------------------- + */ +func plat_gxbb_calc_core_pos + and x0, x0, #MPIDR_CPU_MASK + ret +endfunc plat_gxbb_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary(void); + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #GXBB_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* --------------------------------------------- + * void platform_mem_init(void); + * --------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, GXBB_UART0_AO_BASE + mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ + mov_imm x2, GXBB_UART_BAUDRATE + b console_meson_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, GXBB_UART0_AO_BASE + b console_meson_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, GXBB_UART0_AO_BASE + b console_meson_core_flush +endfunc plat_crash_console_flush + + /* --------------------------------------------- + * void plat_reset_handler(void); + * --------------------------------------------- + */ +func plat_reset_handler + ret +endfunc plat_reset_handler diff --git a/plat/meson/gxl/gxl_bl31_setup.c b/plat/meson/gxl/gxl_bl31_setup.c new file mode 100644 index 000000000..7fe05292d --- /dev/null +++ b/plat/meson/gxl/gxl_bl31_setup.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <common/bl_common.h> +#include <drivers/arm/gicv2.h> +#include <common/interrupt_props.h> +#include <plat/common/platform.h> +#include <platform_def.h> +#include <lib/xlat_tables/xlat_mmu_helpers.h> + +#include "gxl_private.h" + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL31 from BL2. + */ +static entry_point_info_t bl33_image_ep_info; +static image_info_t bl30_image_info; +static image_info_t bl301_image_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(type == NON_SECURE); + + next_image_info = &bl33_image_ep_info; + + /* None of the images can have 0x0 as the entrypoint. */ + if (next_image_info->pc != 0U) { + return next_image_info; + } else { + return NULL; + } +} + +/******************************************************************************* + * Perform any BL31 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +struct gxl_bl31_param { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; + image_info_t *scp_image_info[]; +}; + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + struct gxl_bl31_param *from_bl2; + + /* Initialize the console to provide early debug support */ + gxbb_console_init(); + + /* + * In debug builds, we pass a special value in 'arg1' to verify platform + * parameters from BL2 to BL31. In release builds it's not used. + */ + assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL); + + /* Check that params passed from BL2 are not NULL. */ + from_bl2 = (struct gxl_bl31_param *) arg0; + + /* Check params passed from BL2 are not NULL. */ + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + /* + * Copy BL33 entry point information. It is stored in Secure RAM, in + * BL2's address space. + */ + bl33_image_ep_info = *from_bl2->bl33_ep_info; + + if (bl33_image_ep_info.pc == 0U) { + ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); + panic(); + } + + bl30_image_info = *from_bl2->scp_image_info[0]; + bl301_image_info = *from_bl2->scp_image_info[1]; +} + +void bl31_plat_arch_setup(void) +{ + gxbb_setup_page_tables(); + + enable_mmu_el3(0); +} + +static inline void gxl_scp_boot(void) +{ + scpi_upload_scp_fw(bl30_image_info.image_base, + bl30_image_info.image_size, 0); + scpi_upload_scp_fw(bl301_image_info.image_base, + bl301_image_info.image_size, 1); +} + +/******************************************************************************* + * GICv2 driver setup information + ******************************************************************************/ +static const interrupt_prop_t gxbb_interrupt_props[] = { + INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), + INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), +}; + +static const gicv2_driver_data_t gxbb_gic_data = { + .gicd_base = GXBB_GICD_BASE, + .gicc_base = GXBB_GICC_BASE, + .interrupt_props = gxbb_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), +}; + +void bl31_platform_setup(void) +{ + mhu_secure_init(); + + gicv2_driver_init(&gxbb_gic_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); + + gxl_scp_boot(); + + gxbb_thermal_unknown(); +} diff --git a/plat/meson/gxl/gxl_common.c b/plat/meson/gxl/gxl_common.c new file mode 100644 index 000000000..e3bd6048a --- /dev/null +++ b/plat/meson/gxl/gxl_common.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/ep_info.h> +#include <bl31/interrupt_mgmt.h> +#include <meson_console.h> +#include <lib/mmio.h> +#include <platform_def.h> +#include <stdint.h> +#include <lib/xlat_tables/xlat_tables_v2.h> + +/******************************************************************************* + * Platform memory map regions + ******************************************************************************/ +#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \ + GXBB_NSDRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \ + GXBB_NSDRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \ + GXBB_SEC_DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \ + GXBB_SEC_DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \ + GXBB_TZRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \ + GXBB_SEC_DEVICE2_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \ + GXBB_SEC_DEVICE3_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +static const mmap_region_t gxbb_mmap[] = { + MAP_NSDRAM0, + MAP_NSDRAM1, + MAP_SEC_DEVICE0, + MAP_SEC_DEVICE1, + MAP_TZRAM, + MAP_SEC_DEVICE2, + MAP_SEC_DEVICE3, + {0} +}; + +/******************************************************************************* + * Per-image regions + ******************************************************************************/ +#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \ + BL31_END - BL31_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) + +#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \ + BL_RO_DATA_END - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) + +#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/******************************************************************************* + * Function that sets up the translation tables. + ******************************************************************************/ +void gxbb_setup_page_tables(void) +{ +#if IMAGE_BL31 + const mmap_region_t gxbb_bl_mmap[] = { + MAP_BL31, + MAP_BL_CODE, + MAP_BL_RO_DATA, +#if USE_COHERENT_MEM + MAP_BL_COHERENT, +#endif + {0} + }; +#endif + + mmap_add(gxbb_bl_mmap); + + mmap_add(gxbb_mmap); + + init_xlat_tables(); +} + +/******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_meson_t gxbb_console; + +void gxbb_console_init(void) +{ + int rc = console_meson_register(GXBB_UART0_AO_BASE, + GXBB_UART0_AO_CLK_IN_HZ, + GXBB_UART_BAUDRATE, + &gxbb_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&gxbb_console.console, + CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); +} + +/******************************************************************************* + * Function that returns the system counter frequency + ******************************************************************************/ +unsigned int plat_get_syscnt_freq2(void) +{ + uint32_t val; + + val = mmio_read_32(GXBB_SYS_CPU_CFG7); + val &= 0xFDFFFFFF; + mmio_write_32(GXBB_SYS_CPU_CFG7, val); + + val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); + val &= 0xFFFFFE00; + mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); + + return GXBB_OSC24M_CLK_IN_HZ; +} diff --git a/plat/meson/gxl/gxl_def.h b/plat/meson/gxl/gxl_def.h new file mode 100644 index 000000000..ada26560c --- /dev/null +++ b/plat/meson/gxl/gxl_def.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXBB_DEF_H +#define GXBB_DEF_H + +#include <lib/utils_def.h> + +/******************************************************************************* + * System oscillator + ******************************************************************************/ +#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ + +/******************************************************************************* + * Memory regions + ******************************************************************************/ +#define GXBB_NSDRAM0_BASE UL(0x01000000) +#define GXBB_NSDRAM0_SIZE UL(0x0F000000) + +#define GXBB_NSDRAM1_BASE UL(0x10000000) +#define GXBB_NSDRAM1_SIZE UL(0x00100000) + +#define BL31_BASE UL(0x05100000) +#define BL31_SIZE UL(0x000C0000) +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* Shared memory used for SMC services */ +#define GXBB_SHARE_MEM_INPUT_BASE UL(0x050FE000) +#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x050FF000) + +#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000) +#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000) + +#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000) +#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000) + +#define GXBB_TZRAM_BASE UL(0xD9000000) +#define GXBB_TZRAM_SIZE UL(0x00014000) +/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ + +/* Mailboxes */ +#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) +#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) +#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00) + +// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) +// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * +// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * + +#define GXBB_TZROM_BASE UL(0xD9040000) +#define GXBB_TZROM_SIZE UL(0x00010000) + +#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000) +#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000) + +#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000) +#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000) + +/******************************************************************************* + * GIC-400 and interrupt handling related constants + ******************************************************************************/ +#define GXBB_GICD_BASE UL(0xC4301000) +#define GXBB_GICC_BASE UL(0xC4302000) + +#define IRQ_SEC_PHY_TIMER 29 + +#define IRQ_SEC_SGI_0 8 +#define IRQ_SEC_SGI_1 9 +#define IRQ_SEC_SGI_2 10 +#define IRQ_SEC_SGI_3 11 +#define IRQ_SEC_SGI_4 12 +#define IRQ_SEC_SGI_5 13 +#define IRQ_SEC_SGI_6 14 +#define IRQ_SEC_SGI_7 15 + +/******************************************************************************* + * UART definitions + ******************************************************************************/ +#define GXBB_UART0_AO_BASE UL(0xC81004C0) +#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ +#define GXBB_UART_BAUDRATE U(115200) + +/******************************************************************************* + * Memory-mapped I/O Registers + ******************************************************************************/ +#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4) + +#define GXBB_SYS_CPU_CFG7 UL(0xC8834664) + +#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C) + +#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404) +#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408) +#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) +#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428) +#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) +#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430) + +/******************************************************************************* + * System Monitor Call IDs and arguments + ******************************************************************************/ +#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) +#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) + +#define GXBB_SM_EFUSE_READ U(0x82000030) +#define GXBB_SM_EFUSE_USER_MAX U(0x82000033) + +#define GXBB_SM_JTAG_ON U(0x82000040) +#define GXBB_SM_JTAG_OFF U(0x82000041) + +#define GXBB_JTAG_STATE_ON U(0) +#define GXBB_JTAG_STATE_OFF U(1) + +#define GXBB_JTAG_M3_AO U(0) +#define GXBB_JTAG_M3_EE U(1) +#define GXBB_JTAG_A53_AO U(2) +#define GXBB_JTAG_A53_EE U(3) + +#endif /* GXBB_DEF_H */ diff --git a/plat/meson/gxl/gxl_efuse.c b/plat/meson/gxl/gxl_efuse.c new file mode 100644 index 000000000..b17d1b8e3 --- /dev/null +++ b/plat/meson/gxl/gxl_efuse.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include "gxl_private.h" + +#define EFUSE_BASE 0x140 +#define EFUSE_SIZE 0xC0 + +uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size) +{ + if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE) + return 0; + + return scpi_efuse_read(dst, offset + EFUSE_BASE, size); +} + +uint64_t gxbb_efuse_user_max(void) +{ + return EFUSE_SIZE; +} diff --git a/plat/meson/gxl/gxl_mhu.c b/plat/meson/gxl/gxl_mhu.c new file mode 100644 index 000000000..4c1d5b600 --- /dev/null +++ b/plat/meson/gxl/gxl_mhu.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/bakery_lock.h> +#include <lib/mmio.h> +#include <platform_def.h> + +static DEFINE_BAKERY_LOCK(mhu_lock); + +void mhu_secure_message_start(void) +{ + bakery_lock_get(&mhu_lock); + + while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + ; +} + +void mhu_secure_message_send(uint32_t msg) +{ + mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg); + + while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0) + ; +} + +uint32_t mhu_secure_message_wait(void) +{ + uint32_t val; + + do { + val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0); + } while (val == 0); + + return val; +} + +void mhu_secure_message_end(void) +{ + mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); + + bakery_lock_release(&mhu_lock); +} + +void mhu_secure_init(void) +{ + bakery_lock_init(&mhu_lock); + + mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF); +} diff --git a/plat/meson/gxl/gxl_pm.c b/plat/meson/gxl/gxl_pm.c new file mode 100644 index 000000000..d9b69ef82 --- /dev/null +++ b/plat/meson/gxl/gxl_pm.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <drivers/console.h> +#include <common/debug.h> +#include <errno.h> +#include <drivers/arm/gicv2.h> +#include <lib/mmio.h> +#include <plat/common/platform.h> +#include <platform_def.h> +#include <lib/psci/psci.h> + +#include "gxl_private.h" + +#define SCPI_POWER_ON 0 +#define SCPI_POWER_RETENTION 1 +#define SCPI_POWER_OFF 3 + +#define SCPI_SYSTEM_SHUTDOWN 0 +#define SCPI_SYSTEM_REBOOT 1 + +static uintptr_t gxbb_sec_entrypoint; +static volatile uint32_t gxbb_cpu0_go; + +static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value) +{ + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); + + mmio_write_64(cpu_mailbox_addr, value); + flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t)); +} + +static void __dead2 gxbb_system_reset(void) +{ + INFO("BL31: PSCI_SYSTEM_RESET\n"); + + uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); + + NOTICE("BL31: Reboot reason: 0x%x\n", status); + + status &= 0xFFFF0FF0; + + console_flush(); + + mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); + + int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); + + if (ret != 0) { + ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret); + panic(); + } + + wfi(); + + ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); + panic(); +} + +static void __dead2 gxbb_system_off(void) +{ + INFO("BL31: PSCI_SYSTEM_OFF\n"); + + unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); + + if (ret != 0) { + ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret); + panic(); + } + + gxbb_program_mailbox(read_mpidr_el1(), 0); + + wfi(); + + ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n"); + panic(); +} + +static int32_t gxbb_pwr_domain_on(u_register_t mpidr) +{ + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) { + VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); + + gxbb_cpu0_go = 1; + flush_dcache_range((uintptr_t)&gxbb_cpu0_go, + sizeof(gxbb_cpu0_go)); + dsb(); + isb(); + + sev(); + + return PSCI_E_SUCCESS; + } + + gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint); + scpi_set_css_power_state(mpidr, + SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); + dmbsy(); + sev(); + + return PSCI_E_SUCCESS; +} + +static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); + + if (core == GXBB_PRIMARY_CPU) { + gxbb_cpu0_go = 0; + flush_dcache_range((uintptr_t)&gxbb_cpu0_go, + sizeof(gxbb_cpu0_go)); + dsb(); + isb(); + } + + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +static void gxbb_pwr_domain_off(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int core = plat_gxbb_calc_core_pos(mpidr); + uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4); + + mmio_write_32(addr, 0xFFFFFFFF); + flush_dcache_range(addr, sizeof(uint32_t)); + + gicv2_cpuif_disable(); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) + return; + + scpi_set_css_power_state(mpidr, + SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); +} + +static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t + *target_state) +{ + unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1()); + + /* CPU0 can't be turned OFF, emulate it with a WFE loop */ + if (core == GXBB_PRIMARY_CPU) { + VERBOSE("BL31: CPU0 entering wait loop...\n"); + + while (gxbb_cpu0_go == 0) + wfe(); + + VERBOSE("BL31: CPU0 resumed.\n"); + + write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT); + } + + dsbsy(); + + for (;;) + wfi(); +} + +/******************************************************************************* + * Platform handlers and setup function. + ******************************************************************************/ +static const plat_psci_ops_t gxbb_ops = { + .pwr_domain_on = gxbb_pwr_domain_on, + .pwr_domain_on_finish = gxbb_pwr_domain_on_finish, + .pwr_domain_off = gxbb_pwr_domain_off, + .pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi, + .system_off = gxbb_system_off, + .system_reset = gxbb_system_reset, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + gxbb_sec_entrypoint = sec_entrypoint; + *psci_ops = &gxbb_ops; + gxbb_cpu0_go = 0; + return 0; +} diff --git a/plat/meson/gxl/gxl_private.h b/plat/meson/gxl/gxl_private.h new file mode 100644 index 000000000..913cbf653 --- /dev/null +++ b/plat/meson/gxl/gxl_private.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GXBB_PRIVATE_H +#define GXBB_PRIVATE_H + +#include <stdint.h> +#include <stddef.h> + +/* Utility functions */ +unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); +void gxbb_console_init(void); +void gxbb_setup_page_tables(void); + +/* MHU functions */ +void mhu_secure_message_start(void); +void mhu_secure_message_send(uint32_t msg); +uint32_t mhu_secure_message_wait(void); +void mhu_secure_message_end(void); +void mhu_secure_init(void); + +/* SCPI functions */ +void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state); +uint32_t scpi_sys_power_state(uint64_t system_state); +void scpi_jtag_set_state(uint32_t state, uint8_t select); +uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size); +void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3); +void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); + +/* Peripherals */ +void gxbb_thermal_unknown(void); +uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size); +uint64_t gxbb_efuse_user_max(void); + +#endif /* GXBB_PRIVATE_H */ diff --git a/plat/meson/gxl/gxl_scpi.c b/plat/meson/gxl/gxl_scpi.c new file mode 100644 index 000000000..13d652436 --- /dev/null +++ b/plat/meson/gxl/gxl_scpi.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <lib/mmio.h> +#include <plat/common/platform.h> +#include <platform_def.h> +#include <string.h> +#include <crypto/sha_dma.h> + +#include "gxl_private.h" + +#define SIZE_SHIFT 20 +#define SIZE_MASK 0x1FF +#define SIZE_FWBLK 0x200UL + +/* + * Note: The Amlogic SCP firmware uses the legacy SCPI protocol. + */ +#define SCPI_CMD_SET_CSS_POWER_STATE 0x04 +#define SCPI_CMD_SET_SYS_POWER_STATE 0x08 + +#define SCPI_CMD_JTAG_SET_STATE 0xC0 +#define SCPI_CMD_EFUSE_READ 0xC2 + +#define SCPI_CMD_COPY_FW 0xd4 +#define SCPI_CMD_SET_FW_ADDR 0xd3 +#define SCPI_CMD_FW_SIZE 0xd2 + +static inline uint32_t scpi_cmd(uint32_t command, uint32_t size) +{ + return command | (size << SIZE_SHIFT); +} + +static void scpi_secure_message_send(uint32_t command, uint32_t size) +{ + mhu_secure_message_send(scpi_cmd(command, size)); +} + +uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out) +{ + uint32_t response = mhu_secure_message_wait(); + + size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; + + response &= ~(SIZE_MASK << SIZE_SHIFT); + + if (size_out != NULL) + *size_out = size; + + if (message_out != NULL) + *message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD; + + return response; +} + +void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state) +{ + uint32_t state = (mpidr & 0x0F) | /* CPU ID */ + ((mpidr & 0xF00) >> 4) | /* Cluster ID */ + (cpu_state << 8) | + (cluster_state << 12) | + (css_state << 16); + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +uint32_t scpi_sys_power_state(uint64_t system_state) +{ + uint32_t *response; + size_t size; + + mhu_secure_message_start(); + mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1)); + scpi_secure_message_receive((void *)&response, &size); + mhu_secure_message_end(); + + return *response; +} + +void scpi_jtag_set_state(uint32_t state, uint8_t select) +{ + assert(state <= GXBB_JTAG_STATE_OFF); + + if (select > GXBB_JTAG_A53_EE) { + WARN("BL31: Invalid JTAG select (0x%x).\n", select); + return; + } + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, + (state << 8) | (uint32_t)select); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size) +{ + uint32_t *response; + size_t resp_size; + + if (size > 0x1FC) + return 0; + + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size); + mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8)); + scpi_secure_message_receive((void *)&response, &resp_size); + mhu_secure_message_end(); + + /* + * response[0] is the size of the response message. + * response[1 ... N] are the contents. + */ + if (*response != 0) + memcpy(dst, response + 1, *response); + + return *response; +} + +void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3) +{ + mhu_secure_message_start(); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2); + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3); + mhu_secure_message_send(scpi_cmd(0xC3, 16)); + mhu_secure_message_wait(); + mhu_secure_message_end(); +} + +static inline void scpi_copy_scp_data(uint8_t *data, size_t len) +{ + void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + size_t sz; + + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + mhu_secure_message_wait(); + + for (sz = 0; sz < len; sz += SIZE_FWBLK) { + memcpy(dst, data + sz, MIN(SIZE_FWBLK, len - sz)); + mhu_secure_message_send(SCPI_CMD_COPY_FW); + } +} + +static inline void scpi_set_scp_addr(uint64_t addr, size_t len) +{ + volatile uint64_t *dst = (uint64_t *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + + /* + * It is ok as GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD is mapped as + * non cachable + */ + *dst = addr; + scpi_secure_message_send(SCPI_CMD_SET_FW_ADDR, sizeof(addr)); + mhu_secure_message_wait(); + + mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, len); + scpi_secure_message_send(SCPI_CMD_FW_SIZE, len); + mhu_secure_message_wait(); +} + +static inline void scpi_send_fw_hash(uint8_t hash[], size_t len) +{ + void *dst = (void *)GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD; + + memcpy(dst, hash, len); + mhu_secure_message_send(0xd0); + mhu_secure_message_send(0xd1); + mhu_secure_message_send(0xd5); + mhu_secure_message_end(); +} + +/** + * Upload a FW to SCP. + * + * @param addr: firmware data address + * @param size: size of firmware + * @param send: If set, actually copy the firmware in SCP memory otherwise only + * send the firmware address. + */ +void scpi_upload_scp_fw(uintptr_t addr, size_t size, int send) +{ + struct asd_ctx ctx; + + asd_sha_init(&ctx, ASM_SHA256); + asd_sha_update(&ctx, (void *)addr, size); + asd_sha_finalize(&ctx); + + mhu_secure_message_start(); + if (send == 0) + scpi_set_scp_addr(addr, size); + else + scpi_copy_scp_data((void *)addr, size); + + scpi_send_fw_hash(ctx.digest, sizeof(ctx.digest)); +} diff --git a/plat/meson/gxl/gxl_sip_svc.c b/plat/meson/gxl/gxl_sip_svc.c new file mode 100644 index 000000000..74fbc80e4 --- /dev/null +++ b/plat/meson/gxl/gxl_sip_svc.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <lib/mmio.h> +#include <platform_def.h> +#include <common/runtime_svc.h> +#include <stdint.h> + +#include "gxl_private.h" + +/******************************************************************************* + * This function is responsible for handling all SiP calls + ******************************************************************************/ +static uintptr_t gxbb_sip_handler(uint32_t smc_fid, + u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *cookie, void *handle, + u_register_t flags) +{ + switch (smc_fid) { + + case GXBB_SM_GET_SHARE_MEM_INPUT_BASE: + SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE); + + case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE: + SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE); + + case GXBB_SM_EFUSE_READ: + { + void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE; + uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2); + + SMC_RET1(handle, ret); + } + case GXBB_SM_EFUSE_USER_MAX: + SMC_RET1(handle, gxbb_efuse_user_max()); + + case GXBB_SM_JTAG_ON: + scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1); + SMC_RET1(handle, 0); + + case GXBB_SM_JTAG_OFF: + scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1); + SMC_RET1(handle, 0); + + default: + ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +DECLARE_RT_SVC( + gxbb_sip_handler, + + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + gxbb_sip_handler +); diff --git a/plat/meson/gxl/gxl_thermal.c b/plat/meson/gxl/gxl_thermal.c new file mode 100644 index 000000000..3af1c6dc6 --- /dev/null +++ b/plat/meson/gxl/gxl_thermal.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include "gxl_private.h" + +static int32_t modules_initialized = -1; + +/******************************************************************************* + * Unknown commands related to something thermal-related + ******************************************************************************/ +void gxbb_thermal_unknown(void) +{ + uint16_t ret; + + if (modules_initialized == -1) { + scpi_efuse_read(&ret, 0, 2); + modules_initialized = ret; + } + + scpi_unknown_thermal(10, 2, /* thermal */ + 13, 1); /* thermalver */ +} diff --git a/plat/meson/gxl/gxl_topology.c b/plat/meson/gxl/gxl_topology.c new file mode 100644 index 000000000..cca3ead50 --- /dev/null +++ b/plat/meson/gxl/gxl_topology.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <platform_def.h> +#include <stdint.h> + +#include "gxl_private.h" + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return plat_gxbb_calc_core_pos(mpidr); +} diff --git a/plat/meson/gxl/include/plat_macros.S b/plat/meson/gxl/include/plat_macros.S new file mode 100644 index 000000000..c721c21b6 --- /dev/null +++ b/plat/meson/gxl/include/plat_macros.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <drivers/arm/gicv2.h> +#include <platform_def.h> + +.section .rodata.gic_reg_name, "aS" + +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + + /* GICC registers */ + + mov_imm x17, GXBB_GICC_BASE + + adr x6, gicc_regs + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + bl str_in_crash_buf_print + + /* GICD registers */ + + mov_imm x16, GXBB_GICD_BASE + + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str + +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/meson/gxl/include/platform_def.h b/plat/meson/gxl/include/platform_def.h new file mode 100644 index 000000000..b32ec56da --- /dev/null +++ b/plat/meson/gxl/include/platform_def.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <lib/utils_def.h> + +#include "../gxl_def.h" + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) + +#define PLATFORM_STACK_SIZE UL(0x1000) + +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT + +#define GXBB_PRIMARY_CPU U(0) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* Local power state for power-down. Valid for CPU and cluster power domains. */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) +#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +/* Memory-related defines */ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_MMAP_REGIONS 12 +#define MAX_XLAT_TABLES 6 + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/meson/gxl/platform.mk b/plat/meson/gxl/platform.mk new file mode 100644 index 000000000..ea4aead72 --- /dev/null +++ b/plat/meson/gxl/platform.mk @@ -0,0 +1,94 @@ +# +# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include lib/xlat_tables_v2/xlat_tables.mk + +DOIMAGEPATH ?= tools/meson +DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage + +PLAT_INCLUDES := -Iinclude/drivers/meson/ \ + -Iinclude/drivers/meson/gxl \ + -Iplat/meson/gxl/include + +GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c + +PLAT_BL_COMMON_SOURCES := drivers/meson/console/aarch64/meson_console.S \ + plat/meson/gxl/gxl_common.c \ + plat/meson/gxl/gxl_topology.c \ + ${XLAT_TABLES_LIB_SRCS} + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + plat/meson/gxl/aarch64/gxl_helpers.S \ + plat/meson/gxl/gxl_bl31_setup.c \ + plat/meson/gxl/gxl_efuse.c \ + plat/meson/gxl/gxl_mhu.c \ + plat/meson/gxl/gxl_pm.c \ + plat/meson/gxl/gxl_scpi.c \ + plat/meson/gxl/gxl_sip_svc.c \ + plat/meson/gxl/gxl_thermal.c \ + drivers/meson/gxl/crypto/sha_dma.c \ + ${GXBB_GIC_SOURCES} + +# Tune compiler for Cortex-A53 +ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else ifneq ($(findstring clang,$(notdir $(CC))),) + TF_CFLAGS_aarch64 += -mcpu=cortex-a53 +else + TF_CFLAGS_aarch64 += -mtune=cortex-a53 +endif + +# Build config flags +# ------------------ + +# Enable all errata workarounds for Cortex-A53 +ERRATA_A53_855873 := 1 +ERRATA_A53_819472 := 1 +ERRATA_A53_824069 := 1 +ERRATA_A53_827319 := 1 + +WORKAROUND_CVE_2017_5715 := 0 + +# Have different sections for code and rodata +SEPARATE_CODE_AND_RODATA := 1 + +# Use Coherent memory +USE_COHERENT_MEM := 1 + +# Use multi console API +MULTI_CONSOLE_API := 1 + +# Verify build config +# ------------------- + +ifneq (${MULTI_CONSOLE_API}, 1) + $(error Error: gxl needs MULTI_CONSOLE_API=1) +endif + +ifneq (${RESET_TO_BL31}, 0) + $(error Error: gxl needs RESET_TO_BL31=0) +endif + +ifeq (${ARCH},aarch32) + $(error Error: AArch32 not supported on gxl) +endif + +all: ${BUILD_PLAT}/bl31.img +distclean realclean clean: cleanimage + +cleanimage: + ${Q}${MAKE} -C ${DOIMAGEPATH} clean + +${DOIMAGETOOL}: + ${Q}${MAKE} -C ${DOIMAGEPATH} + +${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL} + ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img + diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c index 1dff69035..673217297 100644 --- a/plat/renesas/rcar/bl2_cpg_init.c +++ b/plat/renesas/rcar/bl2_cpg_init.c @@ -33,6 +33,11 @@ static void bl2_realtime_cpg_init_e3(void); static void bl2_system_cpg_init_e3(void); #endif +#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3) +static void bl2_realtime_cpg_init_d3(void); +static void bl2_system_cpg_init_d3(void); +#endif + typedef struct { uintptr_t adr; uint32_t val; @@ -41,21 +46,39 @@ typedef struct { static void bl2_secure_cpg_init(void) { uint32_t stop_cr2, reset_cr2; + uint32_t stop_cr4, reset_cr4; + uint32_t stop_cr5, reset_cr5; -#if (RCAR_LSI == RCAR_E3) +#if (RCAR_LSI == RCAR_D3) + reset_cr2 = 0x00000000U; + stop_cr2 = 0xFFFFFFFFU; +#elif (RCAR_LSI == RCAR_E3) reset_cr2 = 0x10000000U; stop_cr2 = 0xEFFFFFFFU; #else reset_cr2 = 0x14000000U; stop_cr2 = 0xEBFFFFFFU; #endif + +#if (RCAR_LSI == RCAR_D3) + reset_cr4 = 0x00000000U; + stop_cr4 = 0xFFFFFFFFU; + reset_cr5 = 0x00000000U; + stop_cr5 = 0xFFFFFFFFU; +#else + reset_cr4 = 0x80000003U; + stop_cr4 = 0x7FFFFFFFU; + reset_cr5 = 0x40000000U; + stop_cr5 = 0xBFFFFFFFU; +#endif + /** Secure Module Stop Control Registers */ cpg_write(SCMSTPCR0, 0xFFFFFFFFU); cpg_write(SCMSTPCR1, 0xFFFFFFFFU); cpg_write(SCMSTPCR2, stop_cr2); cpg_write(SCMSTPCR3, 0xFFFFFFFFU); - cpg_write(SCMSTPCR4, 0x7FFFFFFFU); - cpg_write(SCMSTPCR5, 0xBFFFFFFFU); + cpg_write(SCMSTPCR4, stop_cr4); + cpg_write(SCMSTPCR5, stop_cr5); cpg_write(SCMSTPCR6, 0xFFFFFFFFU); cpg_write(SCMSTPCR7, 0xFFFFFFFFU); cpg_write(SCMSTPCR8, 0xFFFFFFFFU); @@ -68,8 +91,8 @@ static void bl2_secure_cpg_init(void) cpg_write(SCSRSTECR1, 0x00000000U); cpg_write(SCSRSTECR2, reset_cr2); cpg_write(SCSRSTECR3, 0x00000000U); - cpg_write(SCSRSTECR4, 0x80000003U); - cpg_write(SCSRSTECR5, 0x40000000U); + cpg_write(SCSRSTECR4, reset_cr4); + cpg_write(SCSRSTECR5, reset_cr5); cpg_write(SCSRSTECR6, 0x00000000U); cpg_write(SCSRSTECR7, 0x00000000U); cpg_write(SCSRSTECR8, 0x00000000U); @@ -229,6 +252,42 @@ static void bl2_system_cpg_init_e3(void) } #endif +#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3) +static void bl2_realtime_cpg_init_d3(void) +{ + /* Realtime Module Stop Control Registers */ + cpg_write(RMSTPCR0, 0x00010000U); + cpg_write(RMSTPCR1, 0xFFFFFFFFU); + cpg_write(RMSTPCR2, 0x00060FDCU); + cpg_write(RMSTPCR3, 0xFFFFFFDFU); + cpg_write(RMSTPCR4, 0x80000184U); + cpg_write(RMSTPCR5, 0x83FFFFFFU); + cpg_write(RMSTPCR6, 0xFFFFFFFFU); + cpg_write(RMSTPCR7, 0xFFFFFFFFU); + cpg_write(RMSTPCR8, 0x00F1FFF7U); + cpg_write(RMSTPCR9, 0xF3F5E016U); + cpg_write(RMSTPCR10, 0xFFFEFFE0U); + cpg_write(RMSTPCR11, 0x000000B7U); +} + +static void bl2_system_cpg_init_d3(void) +{ + /* System Module Stop Control Registers */ + cpg_write(SMSTPCR0, 0x00010000U); + cpg_write(SMSTPCR1, 0xFFFFFFFFU); + cpg_write(SMSTPCR2, 0x00060FDCU); + cpg_write(SMSTPCR3, 0xFFFFFBDFU); + cpg_write(SMSTPCR4, 0x00000084U); + cpg_write(SMSTPCR5, 0x83FFFFFFU); + cpg_write(SMSTPCR6, 0xFFFFFFFFU); + cpg_write(SMSTPCR7, 0xFFFFFFFFU); + cpg_write(SMSTPCR8, 0x00F1FFF7U); + cpg_write(SMSTPCR9, 0xF3F5E016U); + cpg_write(SMSTPCR10, 0xFFFEFFE0U); + cpg_write(SMSTPCR11, 0x000000B7U); +} +#endif + void bl2_cpg_init(void) { uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK; @@ -254,6 +313,9 @@ void bl2_cpg_init(void) case RCAR_PRODUCT_E3: bl2_realtime_cpg_init_e3(); break; + case RCAR_PRODUCT_D3: + bl2_realtime_cpg_init_d3(); + break; default: panic(); break; @@ -266,6 +328,8 @@ void bl2_cpg_init(void) bl2_realtime_cpg_init_m3n(); #elif RCAR_LSI == RCAR_E3 bl2_realtime_cpg_init_e3(); +#elif RCAR_LSI == RCAR_D3 + bl2_realtime_cpg_init_d3(); #else #error "Don't have CPG initialize routine(unknown)." #endif @@ -290,6 +354,9 @@ void bl2_system_cpg_init(void) case RCAR_PRODUCT_E3: bl2_system_cpg_init_e3(); break; + case RCAR_PRODUCT_D3: + bl2_system_cpg_init_d3(); + break; default: panic(); break; @@ -302,6 +369,8 @@ void bl2_system_cpg_init(void) bl2_system_cpg_init_m3n(); #elif RCAR_LSI == RCAR_E3 bl2_system_cpg_init_e3(); +#elif RCAR_LSI == RCAR_D3 + bl2_system_cpg_init_d3(); #else #error "Don't have CPG initialize routine(unknown)." #endif diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index de8588c63..d21ddf505 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -76,6 +76,9 @@ static void bl2_init_generic_timer(void); #elif RCAR_LSI == RCAR_E3 #define TARGET_PRODUCT RCAR_PRODUCT_E3 #define TARGET_NAME "R-Car E3" +#elif RCAR_LSI == RCAR_D3 +#define TARGET_PRODUCT RCAR_PRODUCT_D3 +#define TARGET_NAME "R-Car D3" #elif RCAR_LSI == RCAR_AUTO #define TARGET_NAME "R-Car H3/M3/M3N" #endif @@ -242,6 +245,9 @@ void bl2_plat_flush_bl31_params(void) if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) goto tlb; + if (product == RCAR_PRODUCT_D3) + goto tlb; + /* Disable MFIS write protection */ mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); @@ -430,6 +436,10 @@ static void bl2_populate_compatible_string(void *fdt) ret = fdt_setprop_string(fdt, 0, "compatible", "renesas,ebisu"); break; + case BOARD_DRAAK: + ret = fdt_setprop_string(fdt, 0, "compatible", + "renesas,draak"); + break; default: NOTICE("BL2: Cannot set compatible string, board unsupported\n"); panic(); @@ -458,6 +468,10 @@ static void bl2_populate_compatible_string(void *fdt) ret = fdt_appendprop_string(fdt, 0, "compatible", "renesas,r8a77990"); break; + case RCAR_PRODUCT_D3: + ret = fdt_appendprop_string(fdt, 0, "compatible", + "renesas,r8a77995"); + break; default: NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); panic(); @@ -482,8 +496,10 @@ static void bl2_advertise_dram_entries(uint64_t dram_config[8]) if (!size) continue; - NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", - chan, start, start + size - 1, size >> 30); + NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", + chan, start, start + size - 1, + (size >> 30) ? : size >> 20, + (size >> 30) ? "G" : "M"); } /* @@ -596,6 +612,11 @@ static void bl2_advertise_dram_size(uint32_t product) dram_config[1] = 0x100000000ULL; #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ break; + + case RCAR_PRODUCT_D3: + /* 512MB */ + dram_config[1] = 0x20000000ULL; + break; } bl2_advertise_dram_entries(dram_config); @@ -615,6 +636,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, const char *product_h3 = "H3"; const char *product_m3 = "M3"; const char *product_e3 = "E3"; + const char *product_d3 = "D3"; const char *lcs_secure = "SE"; const char *lcs_cm = "CM"; const char *lcs_dm = "DM"; @@ -627,7 +649,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, const char *boot_qspi80 = "QSPI Flash(80MHz)"; const char *boot_emmc25x1 = "eMMC(25MHz x1)"; const char *boot_emmc50x8 = "eMMC(50MHz x8)"; -#if RCAR_LSI == RCAR_E3 +#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) const char *boot_hyper160 = "HyperFlash(150MHz)"; #else const char *boot_hyper160 = "HyperFlash(160MHz)"; @@ -694,6 +716,9 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, case RCAR_PRODUCT_E3: str = product_e3; break; + case RCAR_PRODUCT_D3: + str = product_d3; + break; default: str = unknown; break; @@ -734,6 +759,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, case BOARD_EBISU: case BOARD_STARTER_KIT_PRE: case BOARD_EBISU_4D: + case BOARD_DRAAK: break; default: type = BOARD_UNKNOWN; @@ -772,9 +798,17 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, str = boot_qspi80; break; case MODEMR_BOOT_DEV_EMMC_25X1: +#if RCAR_LSI == RCAR_D3 + ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); + panic(); +#endif str = boot_emmc25x1; break; case MODEMR_BOOT_DEV_EMMC_50X8: +#if RCAR_LSI == RCAR_D3 + ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); + panic(); +#endif str = boot_emmc50x8; break; default: @@ -938,7 +972,9 @@ void bl2_platform_setup(void) static void bl2_init_generic_timer(void) { -#if RCAR_LSI == RCAR_E3 +#if RCAR_LSI == RCAR_D3 + uint32_t reg_cntfid = EXTAL_DRAAK; +#elif RCAR_LSI == RCAR_E3 uint32_t reg_cntfid = EXTAL_EBISU; #else /* RCAR_LSI == RCAR_E3 */ uint32_t reg; diff --git a/plat/renesas/rcar/bl2_secure_setting.c b/plat/renesas/rcar/bl2_secure_setting.c index cbda1eb38..7473df5a2 100644 --- a/plat/renesas/rcar/bl2_secure_setting.c +++ b/plat/renesas/rcar/bl2_secure_setting.c @@ -52,7 +52,7 @@ static const struct { /* 1: Reserved[R-Car E3] */ /* Bit10: SCEG Secure Core slave ports */ /* 0: registers accessed from secure resource only */ -#if RCAR_LSI == RCAR_E3 +#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) { SEC_SEL6, 0xFFFFFBFFU}, #else diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c index 4e08b5a82..add3e34f6 100644 --- a/plat/renesas/rcar/bl31_plat_setup.c +++ b/plat/renesas/rcar/bl31_plat_setup.c @@ -85,10 +85,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, NOTICE("BL3-1 : Rev.%s\n", version_of_renesas); +#if RCAR_LSI != RCAR_D3 if (RCAR_CLUSTER_A53A57 == rcar_pwrc_get_cluster()) { plat_cci_init(); plat_cci_enable(); } +#endif } void bl31_plat_arch_setup(void) diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h index 934b2dcd9..9f071bcc4 100644 --- a/plat/renesas/rcar/include/platform_def.h +++ b/plat/renesas/rcar/include/platform_def.h @@ -103,14 +103,14 @@ /* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug * size plus a little space for growth. */ #define RCAR_SYSRAM_BASE U(0xE6300000) -#if RCAR_LSI == RCAR_E3 +#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) #define BL2_LIMIT U(0xE6320000) #else #define BL2_LIMIT U(0xE6360000) #endif #define BL2_BASE U(0xE6304000) -#if RCAR_LSI == RCAR_E3 +#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) #define BL2_IMAGE_LIMIT U(0xE6318000) #else #define BL2_IMAGE_LIMIT U(0xE632E800) diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index 6bbd6fa7b..9bf418fee 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -153,6 +153,7 @@ #define RCAR_PRODUCT_M3 U(0x00005200) #define RCAR_PRODUCT_M3N U(0x00005500) #define RCAR_PRODUCT_E3 U(0x00005700) +#define RCAR_PRODUCT_D3 U(0x00005800) #define RCAR_CUT_VER10 U(0x00000000) #define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N/E3 Ver.1.1 */ #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ @@ -205,6 +206,7 @@ #define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */ #define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */ #define EXTAL_EBISU U(24000000) /* Ebisu */ +#define EXTAL_DRAAK U(24000000) /* Draak */ /* CPG write protect registers */ #define CPGWPR_PASSWORD (0x5A5AFFFFU) #define CPGWPCR_PASSWORD (0xA5A50000U) diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c index 47eda9a02..f41c172a9 100644 --- a/plat/renesas/rcar/plat_pm.c +++ b/plat/renesas/rcar/plat_pm.c @@ -92,18 +92,22 @@ static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state) static void rcar_pwr_domain_off(const psci_power_state_t *target_state) { +#if RCAR_LSI != RCAR_D3 uint32_t cluster_type = rcar_pwrc_get_cluster(); +#endif unsigned long mpidr = read_mpidr_el1(); gicv2_cpuif_disable(); rcar_pwrc_cpuoff(mpidr); +#if RCAR_LSI != RCAR_D3 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { if (cluster_type == RCAR_CLUSTER_A53A57) plat_cci_disable(); rcar_pwrc_clusteroff(mpidr); } +#endif } static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state) diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk index 715b8ae17..5eb20fc87 100644 --- a/plat/renesas/rcar/platform.mk +++ b/plat/renesas/rcar/platform.mk @@ -29,12 +29,14 @@ RCAR_M3:=1 RCAR_M3N:=2 RCAR_E3:=3 RCAR_H3N:=4 +RCAR_D3:=5 RCAR_AUTO:=99 $(eval $(call add_define,RCAR_H3)) $(eval $(call add_define,RCAR_M3)) $(eval $(call add_define,RCAR_M3N)) $(eval $(call add_define,RCAR_E3)) $(eval $(call add_define,RCAR_H3N)) +$(eval $(call add_define,RCAR_D3)) $(eval $(call add_define,RCAR_AUTO)) RCAR_CUT_10:=0 RCAR_CUT_11:=1 @@ -143,6 +145,21 @@ else endif $(eval $(call add_define,RCAR_LSI_CUT)) endif + else ifeq (${LSI},D3) + RCAR_LSI:=${RCAR_D3} + ifndef LSI_CUT + # enable compatible function. + RCAR_LSI_CUT_COMPAT := 1 + $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) + else + # disable compatible function. + ifeq (${LSI_CUT},10) + RCAR_LSI_CUT:=0 + else + $(error "Error: ${LSI_CUT} is not supported.") + endif + $(eval $(call add_define,RCAR_LSI_CUT)) + endif else $(error "Error: ${LSI} is not supported.") endif diff --git a/readme.rst b/readme.rst index ee35ff150..849bbb3b9 100644 --- a/readme.rst +++ b/readme.rst @@ -211,6 +211,7 @@ This release also contains the following platform support: - Allwinner sun50i_a64 and sun50i_h6 - Amlogic Meson S905 (GXBB) +- Amlogic Meson S905x (GXL) - Arm Juno Software Development Platform - Arm Neoverse N1 System Development Platform (N1SDP) - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP diff --git a/tools/meson/Makefile b/tools/meson/Makefile new file mode 100644 index 000000000..1a1d1f812 --- /dev/null +++ b/tools/meson/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2019 Remi Pommarel <repk@triplefau.lt> +# +# SPDX-License-Identifier: BSD-3-Clause +# https://spdx.org/licenses +# +MAKE_HELPERS_DIRECTORY := ../../make_helpers/ +include ${MAKE_HELPERS_DIRECTORY}build_macros.mk +include ${MAKE_HELPERS_DIRECTORY}build_env.mk + +PROJECT := doimage${BIN_EXT} +OBJECTS := doimage.o +V := 0 + +HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 -D_GNU_SOURCE + +ifeq (${DEBUG},1) + HOSTCCFLAGS += -g -O0 -DDEBUG +else + HOSTCCFLAGS += -O2 +endif + +ifeq (${V},0) + Q := @ +else + Q := +endif + +HOSTCC := gcc + +.PHONY: all clean distclean + +all: ${PROJECT} + +${PROJECT}: ${OBJECTS} Makefile + @echo " HOSTLD $@" + ${Q}${HOSTCC} ${OBJECTS} -o $@ + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @${ECHO_BLANK_LINE} + +%.o: %.c Makefile + @echo " HOSTCC $<" + ${Q}${HOSTCC} -c ${HOSTCCFLAGS} $< -o $@ + +clean: + $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS}) + +distclean: clean diff --git a/tools/meson/doimage.c b/tools/meson/doimage.c new file mode 100644 index 000000000..b304038d1 --- /dev/null +++ b/tools/meson/doimage.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2019, Remi Pommarel <repk@triplefau.lt> + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <stdlib.h> +#include <stdio.h> +#include <fcntl.h> +#include <unistd.h> +#include <stdint.h> +#include <endian.h> + +#define DEFAULT_PROGNAME "doimage" +#define PROGNAME(argc, argv) (((argc) >= 1) ? ((argv)[0]) : DEFAULT_PROGNAME) + +#define BL31_MAGIC 0x12348765 +#define BL31_LOADADDR 0x05100000 +#define BUFLEN 512 + +static inline void usage(char const *prog) +{ + fprintf(stderr, "Usage: %s <bl31.bin> <bl31.img>\n", prog); +} + +static inline int fdwrite(int fd, uint8_t *data, size_t len) +{ + ssize_t nr; + size_t l; + int ret = -1; + + for (l = 0; l < len; l += nr) { + nr = write(fd, data + l, len - l); + if (nr < 0) { + perror("Cannot write to bl31.img"); + goto out; + } + } + + ret = 0; +out: + return ret; +} + +int main(int argc, char **argv) +{ + int fin, fout, ret = -1; + ssize_t len; + uint32_t data; + uint8_t buf[BUFLEN]; + + if (argc != 3) { + usage(PROGNAME(argc, argv)); + goto out; + } + + fin = open(argv[1], O_RDONLY); + if (fin < 0) { + perror("Cannot open bl31.bin"); + goto out; + } + + fout = open(argv[2], O_WRONLY | O_CREAT, 0660); + if (fout < 0) { + perror("Cannot open bl31.img"); + goto closefin; + } + + data = htole32(BL31_MAGIC); + if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) + goto closefout; + + lseek(fout, 8, SEEK_SET); + data = htole32(BL31_LOADADDR); + if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) + goto closefout; + + lseek(fout, 0x200, SEEK_SET); + while ((len = read(fin, buf, sizeof(buf))) > 0) + if (fdwrite(fout, buf, len) < 0) + goto closefout; + if (len < 0) { + perror("Cannot read bl31.bin"); + goto closefout; + } + + ret = 0; + +closefout: + close(fout); +closefin: + close(fin); +out: + return ret; +} diff --git a/tools/renesas/rcar_layout_create/makefile b/tools/renesas/rcar_layout_create/makefile index b3af401c5..d5857549b 100644 --- a/tools/renesas/rcar_layout_create/makefile +++ b/tools/renesas/rcar_layout_create/makefile @@ -55,6 +55,15 @@ endif endif $(eval $(call add_define,RCAR_SA6_TYPE)) +# Handle different VMA adjustment on D3 +ifeq (${RCAR_LSI},${RCAR_D3}) +RCAR_VMA_ADJUST_ADDR := 0xE6320000 +else +RCAR_VMA_ADJUST_ADDR := 0xE6312000 +endif +$(eval $(call add_define,RCAR_VMA_ADJUST_ADDR)) + + ################################################### #c compiler @@ -88,8 +97,8 @@ $(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) -o $(OUTPUT_FILE_SA0) \ -Map $(FILE_NAME_SA0).map \ - $(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec - $(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin + $(objcopy) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec + $(objcopy) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin $(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) $(LD) $(OBJ_FILE_SA6) \ @@ -97,8 +106,8 @@ $(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) -o $(OUTPUT_FILE_SA6) \ -Map $(FILE_NAME_SA6).map \ - $(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec - $(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin + $(objcopy) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec + $(objcopy) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin ################################################### # Compile diff --git a/tools/renesas/rcar_layout_create/sa0.c b/tools/renesas/rcar_layout_create/sa0.c index b902d3373..79354eca6 100644 --- a/tools/renesas/rcar_layout_create/sa0.c +++ b/tools/renesas/rcar_layout_create/sa0.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_SA0_SIZE_SMALL (0) /* for E3 */ +#define RCAR_SA0_SIZE_SMALL (0) /* for E3/D3 */ #define RCAR_SA0_SIZE_NORMAL (1) /* for H3/M3/M3N */ #define BL2_ADDRESS (0xE6304000) /* BL2 start address */ |