diff options
| -rw-r--r-- | plat/nvidia/tegra/include/t194/tegra_mc_def.h | 23 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_memctrl.c | 239 |
2 files changed, 164 insertions, 98 deletions
diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h index 5da770f2e..6911ba194 100644 --- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h @@ -18,14 +18,14 @@ #define MC_CLIENT_ORDER_ID_27 U(0x2a6c) #define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U #define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4) -#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (1U << 4) +#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (2U << 4) #define MC_CLIENT_ORDER_ID_28 U(0x2a70) #define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U #define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4) #define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4) #define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12) -#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12) +#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (1U << 12) #define mc_client_order_id(val, id, client) \ ((val & ~MC_CLIENT_ORDER_ID_##id##_##client##_MASK) | \ @@ -53,6 +53,11 @@ #define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28) #define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28) +#define MC_HUB_PC_VC_ID_12 U(0x2aa8) +#define MC_HUB_PC_VC_ID_12_RESET_VAL 0x11001011U +#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID_MASK (0x3U << 12) +#define MC_HUB_PC_VC_ID_12_UFSHCPC2_VC_ID (VC_NISO << 12) + #define mc_hub_vc_id(val, id, client) \ ((val & ~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK) | \ MC_HUB_PC_VC_ID_##id##_##client##_VC_ID) @@ -105,7 +110,7 @@ #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13) -#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15) +#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17) #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17) @@ -652,5 +657,17 @@ #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) +#define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK (ULL(0x3) << 15) +#define TSA_CONFIG_CSW_SO_DEV_HUB2 (ULL(2) << 15) + +#define tsa_read_32(client) \ + mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client) + +#define mc_set_tsa_hub2(val, client) \ + { \ + mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ + ((val & ~TSA_CONFIG_CSW_SO_DEV_HUBID_MASK) | \ + TSA_CONFIG_CSW_SO_DEV_HUB2)); \ + } #endif /* TEGRA_MC_DEF_H */ diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 0f8092224..d9ea50e62 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -381,10 +381,12 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_tsa_w_passthrough(AXISW); mc_set_tsa_w_passthrough(BPMPDMAW); mc_set_tsa_w_passthrough(BPMPW); + mc_set_tsa_w_passthrough(EQOSW); mc_set_tsa_w_passthrough(ETRW); - mc_set_tsa_w_passthrough(SCEDMAW); mc_set_tsa_w_passthrough(RCEDMAW); mc_set_tsa_w_passthrough(RCEW); + mc_set_tsa_w_passthrough(SCEDMAW); + mc_set_tsa_w_passthrough(SCEW); mc_set_tsa_w_passthrough(SDMMCW); mc_set_tsa_w_passthrough(SDMMCWA); mc_set_tsa_w_passthrough(SDMMCWAB); @@ -394,6 +396,25 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_tsa_w_passthrough(UFSHCW); mc_set_tsa_w_passthrough(VICSWR); mc_set_tsa_w_passthrough(VIFALW); + /* + * set HUB2 as SO_DEV_HUBID + */ + reg_val = tsa_read_32(PCIE0W); + mc_set_tsa_hub2(reg_val, PCIE0W); + reg_val = tsa_read_32(PCIE1W); + mc_set_tsa_hub2(reg_val, PCIE1W); + reg_val = tsa_read_32(PCIE2AW); + mc_set_tsa_hub2(reg_val, PCIE2AW); + reg_val = tsa_read_32(PCIE3W); + mc_set_tsa_hub2(reg_val, PCIE3W); + reg_val = tsa_read_32(PCIE4W); + mc_set_tsa_hub2(reg_val, PCIE4W); + reg_val = tsa_read_32(SATAW); + mc_set_tsa_hub2(reg_val, SATAW); + reg_val = tsa_read_32(XUSB_DEVW); + mc_set_tsa_hub2(reg_val, XUSB_DEVW); + reg_val = tsa_read_32(XUSB_HOSTW); + mc_set_tsa_hub2(reg_val, XUSB_HOSTW); /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3 * ISO clients(DISP, VI, EQOS) should never snoop caches and @@ -429,112 +450,141 @@ static void tegra194_memctrl_reconfig_mss_clients(void) * between A01 and A02, tegra_memctrl_set_overrides() programs * CGID_TAG_ADR for the necessary clients on A02. */ - mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); + mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + if (tegra_platform_is_silicon()) { + mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + } + mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); /* * TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled. - */ + */ mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); - mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); - mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, - FORCE_COHERENT_SNOOP); - if (tegra_platform_is_silicon()) { - mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO, - FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP); - mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, - NO_OVERRIDE, NO_OVERRIDE); - } + mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(AXIAPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(AXIAPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0FALRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0FALWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA0WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1FALRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1FALWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(DLA1WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + mc_set_txn_override(ISPFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPRA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDEC1SWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENC1SWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDB1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0RDC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA0WRC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDA1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDB1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1RDC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(PVA1WRC, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT, FORCE_COHERENT); + mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT); + /* - * At this point, ordering can occur at ROC. So, remove PCFIFO's + * At this point, ordering can occur at SCF. So, remove PCFIFO's * control over ordering requests. * * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for * boot and strongly ordered MSS clients */ - /* SATAW is ordered client */ - reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL | - mc_set_pcfifo_ordered_boot_so_mss(1, SATAW); - tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val); - reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL & mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) & mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR); - /* XUSB_DEVW has PCFIFO enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL & @@ -558,7 +608,7 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) & mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW); /* EQOSW has PCFIFO order enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW); + reg_val |= mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL & @@ -570,10 +620,6 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) & mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) & mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W); - /* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */ - reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) | - mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) | - mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val); reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL & @@ -607,6 +653,9 @@ static void tegra194_memctrl_reconfig_mss_clients(void) reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_4_RESET_VAL, 4, NIC); tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val); + reg_val = mc_hub_vc_id(MC_HUB_PC_VC_ID_12_RESET_VAL, 12, UFSHCPC2); + tegra_mc_write_32(MC_HUB_PC_VC_ID_12, reg_val); + wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); |