diff options
| -rw-r--r-- | plat/rockchip/common/rockchip_gicv2.c | 7 | ||||
| -rw-r--r-- | plat/rockchip/rk3328/rk3328_def.h | 12 | ||||
| -rw-r--r-- | plat/rockchip/rk3368/rk3368_def.h | 10 |
3 files changed, 12 insertions, 17 deletions
diff --git a/plat/rockchip/common/rockchip_gicv2.c b/plat/rockchip/common/rockchip_gicv2.c index 222a88261..8db2b30d1 100644 --- a/plat/rockchip/common/rockchip_gicv2.c +++ b/plat/rockchip/common/rockchip_gicv2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,11 +22,10 @@ #pragma weak plat_rockchip_gic_pcpu_init /****************************************************************************** - * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 - * interrupts. + * List of interrupts. *****************************************************************************/ static const interrupt_prop_t g0_interrupt_props[] = { - PLAT_RK_GICV2_G1S_IRQS + PLAT_RK_GICV2_G0_IRQS }; /* diff --git a/plat/rockchip/rk3328/rk3328_def.h b/plat/rockchip/rk3328/rk3328_def.h index 4704a72ed..0ce13ad12 100644 --- a/plat/rockchip/rk3328/rk3328_def.h +++ b/plat/rockchip/rk3328/rk3328_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -131,15 +131,13 @@ #define RK_IRQ_SEC_SGI_7 15 /* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. + * Define a list of Group 0 interrupts. */ -#define PLAT_RK_GICV2_G1S_IRQS \ +#define PLAT_RK_GICV2_G0_IRQS \ INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL), \ + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ - GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL) + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) #define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/ #define SHARE_MEM_PAGE_NUM 15 diff --git a/plat/rockchip/rk3368/rk3368_def.h b/plat/rockchip/rk3368/rk3368_def.h index a7be7c367..10ac77b1e 100644 --- a/plat/rockchip/rk3368/rk3368_def.h +++ b/plat/rockchip/rk3368/rk3368_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -96,12 +96,10 @@ #define RK_IRQ_SEC_SGI_7 15 /* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. + * Define a list of Group 0 interrupts. */ -#define PLAT_RK_GICV2_G1S_IRQS \ +#define PLAT_RK_GICV2_G0_IRQS \ INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ - GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL) + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) #endif /* RK3368_DEF_H */ |