drivers: st: update drivers code

Reword some traces.
Use uintptr_t where required.
Reduce scope of variables.
Improve io_stm32image algo.
Complete some IP registers definitions.
Add failure on supported DDR (stm32mp1_ddr_init()).
Fix cache flush on cache disable (stm32mp1_ddr_setup).

Change-Id: Ie02fa71e02b9d69abc807fd5b7df233e5be6668c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

3 files changed, 128 insertions, 16 deletions

diff --git a/include/drivers/st/stm32_gpio.h b/include/drivers/st/stm32_gpio.h
index acd95ecab..4fb27e055 100644
--- a/include/drivers/st/stm32_gpio.h
+++ b/include/drivers/st/stm32_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -82,8 +82,8 @@
 
 #define GPIO_SPEED_LOW		0x00
 #define GPIO_SPEED_MEDIUM	0x01
-#define GPIO_SPEED_FAST		0x02
-#define GPIO_SPEED_HIGH		0x03
+#define GPIO_SPEED_HIGH		0x02
+#define GPIO_SPEED_VERY_HIGH	0x03
 #define GPIO_SPEED_MASK		U(0x03)
 
 #define GPIO_NO_PULL		0x00
diff --git a/include/drivers/st/stm32mp1_ddr_regs.h b/include/drivers/st/stm32mp1_ddr_regs.h
index bfcd5e210..342239a52 100644
--- a/include/drivers/st/stm32mp1_ddr_regs.h
+++ b/include/drivers/st/stm32mp1_ddr_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -247,11 +247,14 @@ struct stm32mp1_ddrphy {
 #define DDRCTRL_DBGSTAT				0x310
 #define DDRCTRL_SWCTL				0x320
 #define DDRCTRL_SWSTAT				0x324
+#define DDRCTRL_PSTAT				0x3FC
 #define DDRCTRL_PCTRL_0				0x490
 #define DDRCTRL_PCTRL_1				0x540
 
 /* DDR Controller Register fields */
 #define DDRCTRL_MSTR_DDR3			BIT(0)
+#define DDRCTRL_MSTR_LPDDR2			BIT(2)
+#define DDRCTRL_MSTR_LPDDR3			BIT(3)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK	GENMASK(13, 12)
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL	0
 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF	BIT(12)
@@ -269,7 +272,7 @@ struct stm32mp1_ddrphy {
 /* Only one rank supported */
 #define DDRCTRL_MRCTRL0_MR_RANK_SHIFT		4
 #define DDRCTRL_MRCTRL0_MR_RANK_ALL \
-		(0x1U << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
+					BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
 #define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT		12
 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK		GENMASK(15, 12)
 #define DDRCTRL_MRCTRL0_MR_WR			BIT(31)
@@ -367,6 +370,7 @@ struct stm32mp1_ddrphy {
 
 #define DDRPHYC_DLLGCR_BPS200			BIT(23)
 
+#define DDRPHYC_ACDLLCR_DLLSRST			BIT(30)
 #define DDRPHYC_ACDLLCR_DLLDIS			BIT(31)
 
 #define DDRPHYC_PTR0_TDLLSRST_OFFSET		0
diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h
index fd406c57e..2f29e84d5 100644
--- a/include/drivers/st/stm32mp1_rcc.h
+++ b/include/drivers/st/stm32mp1_rcc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -68,6 +68,14 @@
 #define RCC_MP_AHB6ENCLRR		U(0x21C)
 #define RCC_MP_TZAHB6ENSETR		U(0x220)
 #define RCC_MP_TZAHB6ENCLRR		U(0x224)
+#define RCC_MC_APB4ENSETR		U(0x280)
+#define RCC_MC_APB4ENCLRR		U(0x284)
+#define RCC_MC_APB5ENSETR		U(0x288)
+#define RCC_MC_APB5ENCLRR		U(0x28C)
+#define RCC_MC_AHB5ENSETR		U(0x290)
+#define RCC_MC_AHB5ENCLRR		U(0x294)
+#define RCC_MC_AHB6ENSETR		U(0x298)
+#define RCC_MC_AHB6ENCLRR		U(0x29C)
 #define RCC_MP_APB4LPENSETR		U(0x300)
 #define RCC_MP_APB4LPENCLRR		U(0x304)
 #define RCC_MP_APB5LPENSETR		U(0x308)
@@ -78,6 +86,14 @@
 #define RCC_MP_AHB6LPENCLRR		U(0x31C)
 #define RCC_MP_TZAHB6LPENSETR		U(0x320)
 #define RCC_MP_TZAHB6LPENCLRR		U(0x324)
+#define RCC_MC_APB4LPENSETR		U(0x380)
+#define RCC_MC_APB4LPENCLRR		U(0x384)
+#define RCC_MC_APB5LPENSETR		U(0x388)
+#define RCC_MC_APB5LPENCLRR		U(0x38C)
+#define RCC_MC_AHB5LPENSETR		U(0x390)
+#define RCC_MC_AHB5LPENCLRR		U(0x394)
+#define RCC_MC_AHB6LPENSETR		U(0x398)
+#define RCC_MC_AHB6LPENCLRR		U(0x39C)
 #define RCC_BR_RSTSCLRR			U(0x400)
 #define RCC_MP_GRSTCSETR		U(0x404)
 #define RCC_MP_RSTSCLRR			U(0x408)
@@ -162,6 +178,22 @@
 #define RCC_MP_AHB4ENCLRR		U(0xA2C)
 #define RCC_MP_MLAHBENSETR		U(0xA38)
 #define RCC_MP_MLAHBENCLRR		U(0xA3C)
+#define RCC_MC_APB1ENSETR		U(0xA80)
+#define RCC_MC_APB1ENCLRR		U(0xA84)
+#define RCC_MC_APB2ENSETR		U(0xA88)
+#define RCC_MC_APB2ENCLRR		U(0xA8C)
+#define RCC_MC_APB3ENSETR		U(0xA90)
+#define RCC_MC_APB3ENCLRR		U(0xA94)
+#define RCC_MC_AHB2ENSETR		U(0xA98)
+#define RCC_MC_AHB2ENCLRR		U(0xA9C)
+#define RCC_MC_AHB3ENSETR		U(0xAA0)
+#define RCC_MC_AHB3ENCLRR		U(0xAA4)
+#define RCC_MC_AHB4ENSETR		U(0xAA8)
+#define RCC_MC_AHB4ENCLRR		U(0xAAC)
+#define RCC_MC_AXIMENSETR		U(0xAB0)
+#define RCC_MC_AXIMENCLRR		U(0xAB4)
+#define RCC_MC_MLAHBENSETR		U(0xAB8)
+#define RCC_MC_MLAHBENCLRR		U(0xABC)
 #define RCC_MP_APB1LPENSETR		U(0xB00)
 #define RCC_MP_APB1LPENCLRR		U(0xB04)
 #define RCC_MP_APB2LPENSETR		U(0xB08)
@@ -178,10 +210,31 @@
 #define RCC_MP_AXIMLPENCLRR		U(0xB34)
 #define RCC_MP_MLAHBLPENSETR		U(0xB38)
 #define RCC_MP_MLAHBLPENCLRR		U(0xB3C)
+#define RCC_MC_APB1LPENSETR		U(0xB80)
+#define RCC_MC_APB1LPENCLRR		U(0xB84)
+#define RCC_MC_APB2LPENSETR		U(0xB88)
+#define RCC_MC_APB2LPENCLRR		U(0xB8C)
+#define RCC_MC_APB3LPENSETR		U(0xB90)
+#define RCC_MC_APB3LPENCLRR		U(0xB94)
+#define RCC_MC_AHB2LPENSETR		U(0xB98)
+#define RCC_MC_AHB2LPENCLRR		U(0xB9C)
+#define RCC_MC_AHB3LPENSETR		U(0xBA0)
+#define RCC_MC_AHB3LPENCLRR		U(0xBA4)
+#define RCC_MC_AHB4LPENSETR		U(0xBA8)
+#define RCC_MC_AHB4LPENCLRR		U(0xBAC)
+#define RCC_MC_AXIMLPENSETR		U(0xBB0)
+#define RCC_MC_AXIMLPENCLRR		U(0xBB4)
+#define RCC_MC_MLAHBLPENSETR		U(0xBB8)
+#define RCC_MC_MLAHBLPENCLRR		U(0xBBC)
+#define RCC_MC_RSTSCLRR			U(0xC00)
+#define RCC_MC_CIER			U(0xC14)
+#define RCC_MC_CIFR			U(0xC18)
 #define RCC_VERR			U(0xFF4)
 #define RCC_IDR				U(0xFF8)
 #define RCC_SIDR			U(0xFFC)
 
+#define RCC_OFFSET_MASK			GENMASK(11, 0)
+
 /* Values for RCC_TZCR register */
 #define RCC_TZCR_TZEN			BIT(0)
 
@@ -221,6 +274,9 @@
 #define RCC_MPUDIV_MASK			GENMASK(2, 0)
 #define RCC_AXIDIV_MASK			GENMASK(2, 0)
 
+/* Used for TIMER Prescaler */
+#define RCC_TIMGXPRER_TIMGXPRE		BIT(0)
+
 /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 #define RCC_MP_ENCLRR_OFFSET		U(4)
 
@@ -228,6 +284,7 @@
 #define RCC_BDCR_LSEON			BIT(0)
 #define RCC_BDCR_LSEBYP			BIT(1)
 #define RCC_BDCR_LSERDY			BIT(2)
+#define RCC_BDCR_DIGBYP			BIT(3)
 #define RCC_BDCR_LSEDRV_MASK		GENMASK(5, 4)
 #define RCC_BDCR_LSEDRV_SHIFT		4
 #define RCC_BDCR_LSECSSON		BIT(8)
@@ -243,6 +300,7 @@
 /* Used for all RCC_PLL<n>CR registers */
 #define RCC_PLLNCR_PLLON		BIT(0)
 #define RCC_PLLNCR_PLLRDY		BIT(1)
+#define RCC_PLLNCR_SSCG_CTRL		BIT(2)
 #define RCC_PLLNCR_DIVPEN		BIT(4)
 #define RCC_PLLNCR_DIVQEN		BIT(5)
 #define RCC_PLLNCR_DIVREN		BIT(6)
@@ -281,8 +339,12 @@
 
 /* Used for RCC_OCENSETR and RCC_OCENCLRR registers */
 #define RCC_OCENR_HSION			BIT(0)
+#define RCC_OCENR_HSIKERON		BIT(1)
 #define RCC_OCENR_CSION			BIT(4)
+#define RCC_OCENR_CSIKERON		BIT(5)
+#define RCC_OCENR_DIGBYP		BIT(7)
 #define RCC_OCENR_HSEON			BIT(8)
+#define RCC_OCENR_HSEKERON		BIT(9)
 #define RCC_OCENR_HSEBYP		BIT(10)
 #define RCC_OCENR_HSECSSON		BIT(11)
 
@@ -319,6 +381,16 @@
 
 /* Fields of RCC_HSICFGR register */
 #define RCC_HSICFGR_HSIDIV_MASK		GENMASK(1, 0)
+#define RCC_HSICFGR_HSITRIM_SHIFT	8
+#define RCC_HSICFGR_HSITRIM_MASK	GENMASK(14, 8)
+#define RCC_HSICFGR_HSICAL_SHIFT	16
+#define RCC_HSICFGR_HSICAL_MASK		GENMASK(27, 16)
+
+/* Fields of RCC_CSICFGR register */
+#define RCC_CSICFGR_CSITRIM_SHIFT	8
+#define RCC_CSICFGR_CSITRIM_MASK	GENMASK(12, 8)
+#define RCC_CSICFGR_CSICAL_SHIFT	16
+#define RCC_CSICFGR_CSICAL_MASK		GENMASK(23, 16)
 
 /* Used for RCC_MCO related operations */
 #define RCC_MCOCFG_MCOON		BIT(12)
@@ -330,22 +402,36 @@
 #define RCC_DBGCFGR_DBGCKEN		BIT(8)
 
 /* RCC register fields for reset reasons */
-#define  RCC_MP_RSTSCLRR_PORRSTF	BIT(0)
-#define  RCC_MP_RSTSCLRR_BORRSTF	BIT(1)
-#define  RCC_MP_RSTSCLRR_PADRSTF	BIT(2)
-#define  RCC_MP_RSTSCLRR_HCSSRSTF	BIT(3)
-#define  RCC_MP_RSTSCLRR_VCORERSTF	BIT(4)
-#define  RCC_MP_RSTSCLRR_MPSYSRSTF	BIT(6)
-#define  RCC_MP_RSTSCLRR_IWDG1RSTF	BIT(8)
-#define  RCC_MP_RSTSCLRR_IWDG2RSTF	BIT(9)
-#define  RCC_MP_RSTSCLRR_STDBYRSTF	BIT(11)
-#define  RCC_MP_RSTSCLRR_CSTDBYRSTF	BIT(12)
+#define RCC_MP_RSTSCLRR_PORRSTF		BIT(0)
+#define RCC_MP_RSTSCLRR_BORRSTF		BIT(1)
+#define RCC_MP_RSTSCLRR_PADRSTF		BIT(2)
+#define RCC_MP_RSTSCLRR_HCSSRSTF	BIT(3)
+#define RCC_MP_RSTSCLRR_VCORERSTF	BIT(4)
+#define RCC_MP_RSTSCLRR_MPSYSRSTF	BIT(6)
+#define RCC_MP_RSTSCLRR_MCSYSRSTF	BIT(7)
+#define RCC_MP_RSTSCLRR_IWDG1RSTF	BIT(8)
+#define RCC_MP_RSTSCLRR_IWDG2RSTF	BIT(9)
+#define RCC_MP_RSTSCLRR_STDBYRSTF	BIT(11)
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF	BIT(12)
+#define RCC_MP_RSTSCLRR_MPUP0RSTF	BIT(13)
+#define RCC_MP_RSTSCLRR_MPUP1RSTF	BIT(14)
 
 /* Global Reset Register */
 #define RCC_MP_GRSTCSETR_MPSYSRST	BIT(0)
+#define RCC_MP_GRSTCSETR_MPUP0RST	BIT(4)
+#define RCC_MP_GRSTCSETR_MPUP1RST	BIT(5)
 
 /* Clock Source Interrupt Flag Register */
 #define RCC_MP_CIFR_MASK		U(0x110F1F)
+#define RCC_MP_CIFR_LSIRDYF		BIT(0)
+#define RCC_MP_CIFR_LSERDYF		BIT(1)
+#define RCC_MP_CIFR_HSIRDYF		BIT(2)
+#define RCC_MP_CIFR_HSERDYF		BIT(3)
+#define RCC_MP_CIFR_CSIRDYF		BIT(4)
+#define RCC_MP_CIFR_PLL1DYF		BIT(8)
+#define RCC_MP_CIFR_PLL2DYF		BIT(9)
+#define RCC_MP_CIFR_PLL3DYF		BIT(10)
+#define RCC_MP_CIFR_PLL4DYF		BIT(11)
 #define RCC_MP_CIFR_WKUPF		BIT(20)
 
 /* Stop Request Set Register */
@@ -362,7 +448,29 @@
 /* Values of RCC_MP_APB1ENSETR register */
 #define RCC_MP_APB1ENSETR_UART4EN	BIT(16)
 
+/* Values of RCC_MP_APB5ENSETR register */
+#define RCC_MP_APB5ENSETR_SPI6EN	BIT(0)
+#define RCC_MP_APB5ENSETR_I2C4EN	BIT(2)
+#define RCC_MP_APB5ENSETR_I2C6EN	BIT(3)
+#define RCC_MP_APB5ENSETR_USART1EN	BIT(4)
+#define RCC_MP_APB5ENSETR_RTCAPBEN	BIT(8)
+#define RCC_MP_APB5ENSETR_IWDG1APBEN	BIT(15)
+
 /* Values of RCC_MP_AHB4ENSETR register */
 #define RCC_MP_AHB4ENSETR_GPIOGEN	BIT(6)
+#define RCC_MP_AHB4ENSETR_GPIOHEN	BIT(7)
+
+/* Values of RCC_MP_AHB5ENSETR register */
+#define RCC_MP_AHB5ENSETR_GPIOZEN	BIT(0)
+#define RCC_MP_AHB5ENSETR_CRYP1EN	BIT(4)
+#define RCC_MP_AHB5ENSETR_HASH1EN	BIT(5)
+#define RCC_MP_AHB5ENSETR_RNG1EN	BIT(6)
+
+/* Values of RCC_MP_IWDGFZSETR register */
+#define RCC_MP_IWDGFZSETR_IWDG1		BIT(0)
+#define RCC_MP_IWDGFZSETR_IWDG2		BIT(1)
+
+/* Values of RCC_PWRLPDLYCR register */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK	GENMASK(21, 0)
 
 #endif /* STM32MP1_RCC_H */