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| author | Avinash Mehta <avinash.mehta@arm.com> | 2020-10-28 16:43:28 +0000 |
|---|---|---|
| committer | avinash mehta <avinashmehtadelhi@review.trustedfirmware.org> | 2021-02-03 10:10:58 +0000 |
| commit | e5da15e04597e374f7a9fdfbf86d47b85c35e728 (patch) | |
| tree | c532be662b45b700f353d3b497077f254026d833 /fdts | |
| parent | 96edbe03413bfa870b4320e4642f58ee3b9de4b8 (diff) | |
| download | platform_external_arm-trusted-firmware-e5da15e04597e374f7a9fdfbf86d47b85c35e728.tar.gz platform_external_arm-trusted-firmware-e5da15e04597e374f7a9fdfbf86d47b85c35e728.tar.bz2 platform_external_arm-trusted-firmware-e5da15e04597e374f7a9fdfbf86d47b85c35e728.zip | |
product/tc0: Enable Theodul DSU in TC platform
Increase the core count and add respective entries in DTS.
Add Klein assembly file to cpu sources for core initialization.
Add SCMI entries for cores.
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Change-Id: I14dc1d87df6dcc8d560ade833ce1f92507054747
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/tc0.dts | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/fdts/tc0.dts b/fdts/tc0.dts index f1ade19e6..b17807aa1 100644 --- a/fdts/tc0.dts +++ b/fdts/tc0.dts @@ -38,6 +38,18 @@ core3 { cpu = <&CPU3>; }; + core4 { + cpu = <&CPU4>; + }; + core5 { + cpu = <&CPU5>; + }; + core6 { + cpu = <&CPU6>; + }; + core7 { + cpu = <&CPU7>; + }; }; }; @@ -102,6 +114,42 @@ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; + CPU4:cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x400>; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU5:cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x500>; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU6:cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x600>; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU7:cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x700>; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; memory@80000000 { |