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| author | Pritesh Raithatha <praithatha@nvidia.com> | 2018-03-09 10:15:17 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-01-23 09:01:56 -0800 |
| commit | 939fd3db83886925972e4847e42557ca58ce58f9 (patch) | |
| tree | 1cb96a80dcac44bc8b3731b829ce6c92fd4bb80d | |
| parent | 33a8ba6a38a4518732e83d55c7afbd5c9ef0e86d (diff) | |
| download | platform_external_arm-trusted-firmware-939fd3db83886925972e4847e42557ca58ce58f9.tar.gz platform_external_arm-trusted-firmware-939fd3db83886925972e4847e42557ca58ce58f9.tar.bz2 platform_external_arm-trusted-firmware-939fd3db83886925972e4847e42557ca58ce58f9.zip | |
Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1
PCIE0R1 does not program stream IDs, so allow the stream ID to be
overriden by the MC.
Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_memctrl.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 3ec07f22e..bb1dd6706 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -130,6 +130,7 @@ const static uint32_t tegra194_streamid_override_regs[] = { MC_STREAMID_OVERRIDE_CFG_NVENCSRD1, MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1, MC_STREAMID_OVERRIDE_CFG_ISPRA1, + MC_STREAMID_OVERRIDE_CFG_PCIE0R1, MC_STREAMID_OVERRIDE_CFG_MIU0R, MC_STREAMID_OVERRIDE_CFG_MIU0W, MC_STREAMID_OVERRIDE_CFG_MIU1R, @@ -259,6 +260,7 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = { mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE), + mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE), |