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| author | Steven Kao <skao@nvidia.com> | 2018-02-09 21:35:20 +0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-01-23 09:01:42 -0800 |
| commit | 33a8ba6a38a4518732e83d55c7afbd5c9ef0e86d (patch) | |
| tree | bb581cfb03191781ab34d39ccf34d7681b48bb6a | |
| parent | 34a6610aeb8e1e976c3afc65155210e919633927 (diff) | |
| download | platform_external_arm-trusted-firmware-33a8ba6a38a4518732e83d55c7afbd5c9ef0e86d.tar.gz platform_external_arm-trusted-firmware-33a8ba6a38a4518732e83d55c7afbd5c9ef0e86d.tar.bz2 platform_external_arm-trusted-firmware-33a8ba6a38a4518732e83d55c7afbd5c9ef0e86d.zip | |
Tegra194: support for boot params wider than 32-bits
The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure scratch register #75 has been assigned to pass the higher
bits.
This patch adds support to parse the higher bits from scratch #75
and use them in calculating the base address for the location of
the boot params.
Scratch #75 format
====================
31:16 - bl31_plat_params high address
15:0 - bl31_params high address
Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80
Signed-off-by: Steven Kao <skao@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/include/t194/tegra_def.h | 11 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_setup.c | 14 |
2 files changed, 19 insertions, 6 deletions
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index da8056bb6..6eb58b970 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -180,6 +180,7 @@ * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE U(0x0C390000) +#define SECURE_SCRATCH_RSV75 U(0x2BC) #define SECURE_SCRATCH_RSV81_LO U(0x2EC) #define SECURE_SCRATCH_RSV81_HI U(0x2F0) #define SECURE_SCRATCH_RSV97 U(0x36C) @@ -188,8 +189,14 @@ #define SECURE_SCRATCH_RSV109_LO U(0x3CC) #define SECURE_SCRATCH_RSV109_HI U(0x3D0) -#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV81_LO -#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV81_HI +#define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 +#define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF) +#define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0) +#define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75 +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000) +#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16) +#define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI #define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97 #define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO #define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 38c737d92..ead6bf552 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -276,9 +276,12 @@ void plat_gic_setup(void) ******************************************************************************/ struct tegra_bl31_params *plat_get_bl31_params(void) { - uint32_t val; + uint64_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); + val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & + SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT; + val <<= 32; + val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); return (struct tegra_bl31_params *)(uintptr_t)val; } @@ -288,9 +291,12 @@ struct tegra_bl31_params *plat_get_bl31_params(void) ******************************************************************************/ plat_params_from_bl2_t *plat_get_bl31_plat_params(void) { - uint32_t val; + uint64_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); + val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT; + val <<= 32; + val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); return (plat_params_from_bl2_t *)(uintptr_t)val; } |