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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2019-05-03 16:35:25 +0530 |
|---|---|---|
| committer | Jolly Shah <jolly.shah@xilinx.com> | 2020-01-15 11:04:05 -0800 |
| commit | d69bbd0e80d07d4c9008a0666e192491ddf52e43 (patch) | |
| tree | 3559eee7d3730136e407492faa6c470da86d26c4 | |
| parent | 29af4789759714db41d10e3c80d0b00e14916d54 (diff) | |
| download | platform_external_arm-trusted-firmware-d69bbd0e80d07d4c9008a0666e192491ddf52e43.tar.gz platform_external_arm-trusted-firmware-d69bbd0e80d07d4c9008a0666e192491ddf52e43.tar.bz2 platform_external_arm-trusted-firmware-d69bbd0e80d07d4c9008a0666e192491ddf52e43.zip | |
xilinx: versal: Wire silicon default setup
Add new option for serial and default clock setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a
| -rw-r--r-- | plat/xilinx/versal/include/versal_def.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index a1479a10c..94bd321b8 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -19,6 +19,7 @@ /* List all supported platforms */ #define VERSAL_PLATFORM_ID_versal_virt 1 +#define VERSAL_PLATFORM_ID_silicon 4 #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) @@ -85,6 +86,11 @@ # define VERSAL_UART_CLOCK 25000000 # define VERSAL_UART_BAUDRATE 115200 # define VERSAL_CPU_CLOCK 2720000 +#elif VERSAL_PLATFORM_IS(silicon) +# define PLATFORM_NAME "Versal Silicon" +# define VERSAL_UART_CLOCK 100000000 +# define VERSAL_UART_BAUDRATE 115200 +# define VERSAL_CPU_CLOCK 100000000 #endif /* Access control register defines */ |