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| author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-12-24 10:42:52 +0800 |
|---|---|---|
| committer | Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2020-01-16 10:56:42 +0800 |
| commit | 9c8f3af50a227cb095a629c0877ff82111c801a9 (patch) | |
| tree | ade953ad592051ee1684791dead6e5cb1d03893d | |
| parent | dfdd38c2e14f4a41721f83483e82ee28b6f57c6f (diff) | |
| download | platform_external_arm-trusted-firmware-9c8f3af50a227cb095a629c0877ff82111c801a9.tar.gz platform_external_arm-trusted-firmware-9c8f3af50a227cb095a629c0877ff82111c801a9.tar.bz2 platform_external_arm-trusted-firmware-9c8f3af50a227cb095a629c0877ff82111c801a9.zip | |
intel: Add bridge control for FPGA reconfig
This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d
| -rw-r--r-- | plat/intel/soc/agilex/platform.mk | 1 | ||||
| -rw-r--r-- | plat/intel/soc/common/socfpga_sip_svc.c | 16 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/platform.mk | 1 |
3 files changed, 18 insertions, 0 deletions
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index d04d630b4..f47c3f113 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -60,6 +60,7 @@ BL31_SOURCES += \ plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/common/socfpga_topology.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index f9ba2351d..41dae9e76 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -11,6 +11,7 @@ #include <tools_share/uuid.h> #include "socfpga_mailbox.h" +#include "socfpga_reset_manager.h" #include "socfpga_sip_svc.h" /* Number of SiP Calls implemented */ @@ -27,6 +28,7 @@ static int rcv_id; static int max_blocks; static uint32_t bytes_per_block; static uint32_t blocks_submitted; +static int is_partial_reconfig; struct fpga_config_info { uint32_t addr; @@ -109,6 +111,12 @@ static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) return INTEL_SIP_SMC_STATUS_ERROR; } + if (query_type != 1) { + /* full reconfiguration */ + if (!is_partial_reconfig) + socfpga_bridges_enable(); /* Enable bridge */ + } + return INTEL_SIP_SMC_STATUS_OK; } @@ -196,6 +204,8 @@ static int intel_fpga_config_start(uint32_t config_type) uint32_t response[3]; int status = 0; + is_partial_reconfig = config_type; + mailbox_clear_response(); mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0); @@ -225,6 +235,12 @@ static int intel_fpga_config_start(uint32_t config_type) send_id = 0; rcv_id = 0; + /* full reconfiguration */ + if (!is_partial_reconfig) { + /* Disable bridge */ + socfpga_bridges_disable(); + } + return 0; } diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index a89c3d443..efbab24b3 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -59,6 +59,7 @@ BL31_SOURCES += \ plat/intel/soc/common/socfpga_sip_svc.c \ plat/intel/soc/common/socfpga_topology.c \ plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 |