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| author | Pritesh Raithatha <praithatha@nvidia.com> | 2018-04-19 13:11:43 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-01-23 09:03:01 -0800 |
| commit | 844e6cc5e73d081f0709d6cf39de6c4b0ff9c08b (patch) | |
| tree | 30152091f5ffbee0c89efa8fc178988e2825b0d7 | |
| parent | 4a9026d413d1d97f8ef4a7c7a3d39ac25cfa03c6 (diff) | |
| download | platform_external_arm-trusted-firmware-844e6cc5e73d081f0709d6cf39de6c4b0ff9c08b.tar.gz platform_external_arm-trusted-firmware-844e6cc5e73d081f0709d6cf39de6c4b0ff9c08b.tar.bz2 platform_external_arm-trusted-firmware-844e6cc5e73d081f0709d6cf39de6c4b0ff9c08b.zip | |
Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list
PCIE0R1 security and override registers need to be preserved across
system suspend. Adding them to system suspend save register list.
Due to addition of above registers, increasing context save memory
by 2 bytes.
Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_smmu.c | 4 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_trampoline.S | 4 |
2 files changed, 5 insertions, 3 deletions
diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 640ef4deb..3b4a3803c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -139,6 +139,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { mc_make_sid_security_cfg(NVENCSRD1), mc_make_sid_security_cfg(NVENC1SRD1), mc_make_sid_security_cfg(ISPRA1), + mc_make_sid_security_cfg(PCIE0R1), mc_make_sid_security_cfg(MIU0R), mc_make_sid_security_cfg(MIU0W), mc_make_sid_security_cfg(MIU1R), @@ -262,6 +263,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { mc_make_sid_override_cfg(NVENCSRD1), mc_make_sid_override_cfg(NVENC1SRD1), mc_make_sid_override_cfg(ISPRA1), + mc_make_sid_override_cfg(PCIE0R1), mc_make_sid_override_cfg(MIU0R), mc_make_sid_override_cfg(MIU0W), mc_make_sid_override_cfg(MIU1R), diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S index 696a5774e..540c2019c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S +++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ #define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7 #define TEGRA194_STATE_SYSTEM_RESUME 0x600D -#define TEGRA194_SMMU_CTX_SIZE 0x80B +#define TEGRA194_SMMU_CTX_SIZE 0x80D .align 4 .globl tegra194_cpu_reset_handler |