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| author | Varun Wadekar <vwadekar@nvidia.com> | 2018-04-03 13:10:48 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-01-23 09:02:46 -0800 |
| commit | 4a9026d413d1d97f8ef4a7c7a3d39ac25cfa03c6 (patch) | |
| tree | e619cf8868ea63eaea3106a70c2b3dd92954c779 | |
| parent | db891f32f6c2100beb6c7d8eedcab2df57df632f (diff) | |
| download | platform_external_arm-trusted-firmware-4a9026d413d1d97f8ef4a7c7a3d39ac25cfa03c6.tar.gz platform_external_arm-trusted-firmware-4a9026d413d1d97f8ef4a7c7a3d39ac25cfa03c6.tar.bz2 platform_external_arm-trusted-firmware-4a9026d413d1d97f8ef4a7c7a3d39ac25cfa03c6.zip | |
Tegra194: enable driver for general purpose DMA engine
This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.
Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/include/t194/tegra_def.h | 7 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_setup.c | 2 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/platform_t194.mk | 6 |
3 files changed, 14 insertions, 1 deletions
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 9737a2941..df1d65630 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -54,6 +54,11 @@ #define MISCREG_PFCFG U(0x200C) /******************************************************************************* + * Tegra General Purpose Centralised DMA constants + ******************************************************************************/ +#define TEGRA_GPCDMA_BASE U(0x02610000) + +/******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ #define TEGRA_MC_STREAMID_BASE U(0x02C00000) @@ -248,6 +253,8 @@ #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C) #define GPU_RESET_BIT (U(1) << 0) #define GPU_SET_BIT (U(1) << 0) +#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) +#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) /******************************************************************************* * XUSB STREAMIDs diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index c064bdf77..912dcc6f9 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -68,6 +68,8 @@ static const mmap_region_t tegra_mmap[] = { (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */ (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */ diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 1389f8f23..1e49e51da 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -8,9 +8,12 @@ ENABLE_CONSOLE_SPE := 0 $(eval $(call add_define,ENABLE_CONSOLE_SPE)) -ENABLE_STRICT_CHECKING_MODE := 1 +ENABLE_STRICT_CHECKING_MODE := 1 $(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE)) +USE_GPC_DMA := 1 +$(eval $(call add_define,USE_GPC_DMA)) + RESET_TO_BL31 := 1 PROGRAMMABLE_RESET_ADDRESS := 1 @@ -40,6 +43,7 @@ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \ ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \ + ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \ ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ ${COMMON_DIR}/drivers/smmu/smmu.c \ ${SOC_DIR}/drivers/mce/mce.c \ |