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| author | Puneet Saxena <puneets@nvidia.com> | 2018-01-02 11:13:01 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-01-23 08:59:12 -0800 |
| commit | 21e22fe301e61ea25ab11c6fee8ed83a2fefeb0a (patch) | |
| tree | b5fb08e715821bf9668cfc68752e0086c4256335 | |
| parent | 1a7a1dcd13f8513b7e33addcc5af0209bebb921a (diff) | |
| download | platform_external_arm-trusted-firmware-21e22fe301e61ea25ab11c6fee8ed83a2fefeb0a.tar.gz platform_external_arm-trusted-firmware-21e22fe301e61ea25ab11c6fee8ed83a2fefeb0a.tar.bz2 platform_external_arm-trusted-firmware-21e22fe301e61ea25ab11c6fee8ed83a2fefeb0a.zip | |
Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent
Force memory transactions from seswr and sesrd as coherent_snoop from
no-override. This is necessary as niso clients should use coherent
path.
Presently its set as FORCE_COHERENT_SNOOP. Once SE+TZ is enabled
with SMMU, this needs to be replaced by FORCE_COHERENT.
Change-Id: I8b50722de743b9028129b4715769ef93deab73b5
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
| -rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_memctrl.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 57186503b..07c05c8b1 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -388,6 +388,7 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_tsa_w_passthrough(SDMMCW); mc_set_tsa_w_passthrough(SDMMCWA); mc_set_tsa_w_passthrough(SDMMCWAB); + mc_set_tsa_w_passthrough(SESWR); mc_set_tsa_w_passthrough(TSECSWR); mc_set_tsa_w_passthrough(TSECSWRB); mc_set_tsa_w_passthrough(UFSHCW); @@ -467,8 +468,11 @@ static void tegra194_memctrl_reconfig_mss_clients(void) mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); - mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); - mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE); + /* + * TO DO: make SESRD/WR FORCE_COHERENT once SE+TZ with SMMU is enabled. + */ + mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); + mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, FORCE_COHERENT_SNOOP); mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE); |