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| author | Victor Khimenko <khim@google.com> | 2016-10-10 17:38:17 +0200 |
|---|---|---|
| committer | Victor Khimenko <khim@google.com> | 2016-10-10 19:29:09 +0200 |
| commit | 2481784ced1961fde6c6605f31fa1134cfdd3e5f (patch) | |
| tree | 55ed738873e970ac1f115e87fb151fb50399f300 /InitCache.s | |
| parent | 230c1021ca6cef9677c4e8c87a92016048183b6f (diff) | |
| parent | d98beba6c8fa7b38fb62cb799c9c7de355937cf3 (diff) | |
| download | platform_external_arm-neon-tests-2481784ced1961fde6c6605f31fa1134cfdd3e5f.tar.gz platform_external_arm-neon-tests-2481784ced1961fde6c6605f31fa1134cfdd3e5f.tar.bz2 platform_external_arm-neon-tests-2481784ced1961fde6c6605f31fa1134cfdd3e5f.zip | |
Initial import of upstream sources
BUG=30471686
Change-Id: I1270bfb2ee8f7f43683104e92f131dd42222ffd9
Diffstat (limited to 'InitCache.s')
| -rw-r--r-- | InitCache.s | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/InitCache.s b/InitCache.s new file mode 100644 index 0000000..250652a --- /dev/null +++ b/InitCache.s @@ -0,0 +1,52 @@ +; Copyright ARM Ltd 2005. All rights reserved. + +;================================================================== +; This code provides basic global enable for a Cortex-A8 cache +; and program flow prediction +; This code must be run from a privileged mode +;================================================================== + + AREA CORTEXA8CACHE, CODE, READONLY + EXPORT core_init + +core_init + +;================================================================== +; Global Enable for Cortex-A8 Instruction and Data Caching +;================================================================== + + MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0 + ORR r0, r0, #(0x1 <<12) ; enable I Cache + ;BIC r0, r0, #(0x1 <<12) ; Clear bit 0 + ORR r0, r0, #(0x1 <<2) ; enable D Cache + ;BIC r0, r0, #(0x1 << 2) ; Clear bit 0 + ORR r0, r0, #0x1 ; enable MMU + MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1 + +;================================================================== +; Enable Cortex-A8 Level2 Unified Cache +;================================================================== + + MRC p15, 0, r0, c1, c0, 1 ; Read Auxiliary Control Register + ORR r0, r0, #2 ; L2EN bit, enable L2 cache + ;BIC r0, r0, #(0x1 << 1) ; L2EN bit, disable L2 cache + ;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI + ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI + ORR r0, r0, #(0x1 << 5) ;Enables caching NEON data within the L1 data cache + MCR p15, 0, r0, c1, c0, 1 ; Write Auxiliary Control Register + +;================================================================== +; Cortex-A8 program flow prediction +;================================================================== + + MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0 + ORR r0, r0, #(0x1 <<11) ; Enable all forms of branch prediction + ;BIC r0, r0, #(0x1 << 11) ; Disable all forms of branch prediction + MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1 + +;================================================================== + + BX lr + + END ; mark the end of this file + |