Fix input data for vld3 and vld4 tests.

Reported by Victoria Zhislina.

3 files changed, 15 insertions, 12 deletions

diff --git a/compute_ref.axf b/compute_ref.axf
index 2a480d0..cba0d45 100644
--- a/compute_ref.axf
+++ b/compute_ref.axf
diff --git a/ref-rvct.txt b/ref-rvct.txt
index 05128c4..0a0fcff 100644
--- a/ref-rvct.txt
+++ b/ref-rvct.txt
@@ -2014,11 +2014,11 @@ VLD3/VLD3Q:41:result_uint16x4 [] = { fff8, fff9, fffa, fffb,  }
 VLD3/VLD3Q:42:result_uint32x2 [] = { fffffff4, fffffff5,  }
 VLD3/VLD3Q:43:result_uint64x1 [] = { fffffffffffffff2,  }
 VLD3/VLD3Q:44:result_float32x2 [] = { c1400000 -0x1.8000000p+3 -12, c1300000 -0x1.6000000p+3 -11,  }
-VLD3/VLD3Q:45:result_int8x16 [] = { fffffff0, ffffffff, fffffff1, ffffffff, fffffff2, ffffffff, fffffff3, ffffffff, fffffff4, ffffffff, fffffff5, ffffffff, fffffff6, ffffffff, fffffff7, ffffffff,  }
+VLD3/VLD3Q:45:result_int8x16 [] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f,  }
 VLD3/VLD3Q:46:result_int16x8 [] = { 0, 1, 2, 3, 4, 5, 6, 7,  }
 VLD3/VLD3Q:47:result_int32x4 [] = { fffffff8, fffffff9, fffffffa, fffffffb,  }
 VLD3/VLD3Q:48:result_int64x2 [] = { 3333333333333333, 3333333333333333,  }
-VLD3/VLD3Q:49:result_uint8x16 [] = { f0, ff, f1, ff, f2, ff, f3, ff, f4, ff, f5, ff, f6, ff, f7, ff,  }
+VLD3/VLD3Q:49:result_uint8x16 [] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f,  }
 VLD3/VLD3Q:50:result_uint16x8 [] = { 0, 1, 2, 3, 4, 5, 6, 7,  }
 VLD3/VLD3Q:51:result_uint32x4 [] = { fffffff8, fffffff9, fffffffa, fffffffb,  }
 VLD3/VLD3Q:52:result_uint64x2 [] = { 3333333333333333, 3333333333333333,  }
@@ -2074,11 +2074,11 @@ VLD4/VLD4Q:41:result_uint16x4 [] = { fff8, fff9, fffa, fffb,  }
 VLD4/VLD4Q:42:result_uint32x2 [] = { fffffff4, fffffff5,  }
 VLD4/VLD4Q:43:result_uint64x1 [] = { fffffffffffffff2,  }
 VLD4/VLD4Q:44:result_float32x2 [] = { c1400000 -0x1.8000000p+3 -12, c1300000 -0x1.6000000p+3 -11,  }
-VLD4/VLD4Q:45:result_int8x16 [] = { fffffff0, ffffffff, fffffff1, ffffffff, fffffff2, ffffffff, fffffff3, ffffffff, fffffff4, ffffffff, fffffff5, ffffffff, fffffff6, ffffffff, fffffff7, ffffffff,  }
+VLD4/VLD4Q:45:result_int8x16 [] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f,  }
 VLD4/VLD4Q:46:result_int16x8 [] = { 0, 1, 2, 3, 4, 5, 6, 7,  }
 VLD4/VLD4Q:47:result_int32x4 [] = { fffffff8, fffffff9, fffffffa, fffffffb,  }
 VLD4/VLD4Q:48:result_int64x2 [] = { 3333333333333333, 3333333333333333,  }
-VLD4/VLD4Q:49:result_uint8x16 [] = { f0, ff, f1, ff, f2, ff, f3, ff, f4, ff, f5, ff, f6, ff, f7, ff,  }
+VLD4/VLD4Q:49:result_uint8x16 [] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f,  }
 VLD4/VLD4Q:50:result_uint16x8 [] = { 0, 1, 2, 3, 4, 5, 6, 7,  }
 VLD4/VLD4Q:51:result_uint32x4 [] = { fffffff8, fffffff9, fffffffa, fffffffb,  }
 VLD4/VLD4Q:52:result_uint64x2 [] = { 3333333333333333, 3333333333333333,  }
@@ -2094,11 +2094,11 @@ VLD4/VLD4Q:59:result_uint16x4 [] = { fffc, fffd, fffe, ffff,  }
 VLD4/VLD4Q:60:result_uint32x2 [] = { fffffff6, fffffff7,  }
 VLD4/VLD4Q:61:result_uint64x1 [] = { fffffffffffffff3,  }
 VLD4/VLD4Q:62:result_float32x2 [] = { c1200000 -0x1.4000000p+3 -10, c1100000 -0x1.2000000p+3 -9,  }
-VLD4/VLD4Q:63:result_int8x16 [] = { fffffff8, ffffffff, fffffff9, ffffffff, fffffffa, ffffffff, fffffffb, ffffffff, fffffffc, ffffffff, fffffffd, ffffffff, fffffffe, ffffffff, ffffffff, ffffffff,  }
+VLD4/VLD4Q:63:result_int8x16 [] = { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2a, 2b, 2c, 2d, 2e, 2f,  }
 VLD4/VLD4Q:64:result_int16x8 [] = { 8, 9, a, b, c, d, e, f,  }
 VLD4/VLD4Q:65:result_int32x4 [] = { fffffffc, fffffffd, fffffffe, ffffffff,  }
 VLD4/VLD4Q:66:result_int64x2 [] = { 3333333333333333, 3333333333333333,  }
-VLD4/VLD4Q:67:result_uint8x16 [] = { f8, ff, f9, ff, fa, ff, fb, ff, fc, ff, fd, ff, fe, ff, ff, ff,  }
+VLD4/VLD4Q:67:result_uint8x16 [] = { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2a, 2b, 2c, 2d, 2e, 2f,  }
 VLD4/VLD4Q:68:result_uint16x8 [] = { 8, 9, a, b, c, d, e, f,  }
 VLD4/VLD4Q:69:result_uint32x4 [] = { fffffffc, fffffffd, fffffffe, ffffffff,  }
 VLD4/VLD4Q:70:result_uint64x2 [] = { 3333333333333333, 3333333333333333,  }
diff --git a/stm-arm-neon-ref.h b/stm-arm-neon-ref.h
index e1239e6..2d38742 100644
--- a/stm-arm-neon-ref.h
+++ b/stm-arm-neon-ref.h
@@ -123,12 +123,15 @@ static int result_idx = 0;
 extern FILE* log_file;
 extern FILE* ref_file;
 
-/* Sample initialization vectors */
-#define INIT_TAB(T) [] = { (T)-16, (T)-15, (T)-14, (T)-13, (T)-12, (T)-11, \
-			   (T)-10, (T)-9, (T)-8, (T)-7, (T)-6, (T)-5, (T)-4, \
-			   (T)-3, (T)-2, (T)-1, (T)0, (T)1, (T)2, (T)3, (T)4, \
-			   (T)5, (T)6, (T)7, (T)8, (T)9, (T)10, (T)11, (T)12, \
-			   (T)13, (T)14, (T)15 }
+/* Sample initialization vectors. For simplicity, use the same one for
+   each vector size (it's not a problem if it's too large), and have
+   it large enough for the vld4 input samples. */
+#define INIT_TAB(T) [] = { \
+    (T)-16, (T)-15, (T)-14, (T)-13, (T)-12, (T)-11, (T)-10, (T)-9, (T)-8, (T)-7, (T)-6, (T)-5, (T)-4, (T)-3, (T)-2, (T)-1, \
+    (T)0, (T)1, (T)2, (T)3, (T)4, (T)5, (T)6, (T)7, (T)8, (T)9, (T)10, (T)11, (T)12, (T)13, (T)14, (T)15, \
+    (T)16, (T)17,(T)18,(T)19,(T)20, (T)21, (T)22, (T)23, (T)24, (T)25, (T)26, (T)27, (T)28, (T)29, (T)30, (T)31, \
+    (T)32, (T)33,(T)34,(T)35,(T)36, (T)37, (T)38, (T)39, (T)40, (T)41, (T)42, (T)43, (T)44, (T)45, (T)46, (T)47, \
+  }
 
 /* Input buffers, 1 of each size */
 static VECT_VAR_DECL_INIT(buffer, int, 8, 8);