diff options
| author | Liming Gao <liming.gao@intel.com> | 2016-06-14 16:36:53 +0800 |
|---|---|---|
| committer | Liming Gao <liming.gao@intel.com> | 2016-06-28 09:52:18 +0800 |
| commit | ba15b97142411291274e13b1018d3b9890a473b8 (patch) | |
| tree | 19b92b525ad66497abe732b893a9f4a526191315 /UefiCpuPkg/PiSmmCpuDxeSmm | |
| parent | 9f54832f4bcabd549ac97e3b9efe2aa68ac898e8 (diff) | |
| download | device_linaro_bootloader_edk2-ba15b97142411291274e13b1018d3b9890a473b8.tar.gz device_linaro_bootloader_edk2-ba15b97142411291274e13b1018d3b9890a473b8.tar.bz2 device_linaro_bootloader_edk2-ba15b97142411291274e13b1018d3b9890a473b8.zip | |
UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmmInit.asm to NASM
Manually convert X64/SmmInit.asm to X64/SmmInit.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm new file mode 100644 index 000000000..9d05e2cb0 --- /dev/null +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm @@ -0,0 +1,130 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; SmmInit.nasm
+;
+; Abstract:
+;
+; Functions for relocating SMBASE's for all processors
+;
+;-------------------------------------------------------------------------------
+
+extern ASM_PFX(SmmInitHandler)
+extern ASM_PFX(mRebasedFlag)
+extern ASM_PFX(mSmmRelocationOriginalAddress)
+
+global ASM_PFX(gSmmCr3)
+global ASM_PFX(gSmmCr4)
+global ASM_PFX(gSmmCr0)
+global ASM_PFX(gSmmJmpAddr)
+global ASM_PFX(gSmmInitStack)
+global ASM_PFX(gcSmiInitGdtr)
+global ASM_PFX(gcSmmInitSize)
+global ASM_PFX(gcSmmInitTemplate)
+global ASM_PFX(mRebasedFlagAddr32)
+global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
+
+ DEFAULT REL
+ SECTION .text
+
+ASM_PFX(gcSmiInitGdtr):
+ DW 0
+ DQ 0
+
+global ASM_PFX(SmmStartup)
+ASM_PFX(SmmStartup):
+ DB 0x66, 0xb8 ; mov eax, imm32
+ASM_PFX(gSmmCr3): DD 0
+ mov cr3, rax
+ DB 0x66, 0x2e
+ lgdt [ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
+ DB 0x66, 0xb8 ; mov eax, imm32
+ASM_PFX(gSmmCr4): DD 0
+ or ah, 2 ; enable XMM registers access
+ mov cr4, rax
+ DB 0x66
+ mov ecx, 0xc0000080 ; IA32_EFER MSR
+ rdmsr
+ or ah, 1 ; set LME bit
+ wrmsr
+ DB 0x66, 0xb8 ; mov eax, imm32
+ASM_PFX(gSmmCr0): DD 0
+ mov cr0, rax ; enable protected mode & paging
+ DB 0x66, 0xea ; far jmp to long mode
+ASM_PFX(gSmmJmpAddr): DQ @LongMode
+@LongMode: ; long-mode starts here
+ DB 0x48, 0xbc ; mov rsp, imm64
+ASM_PFX(gSmmInitStack): DQ 0
+ and sp, 0xfff0 ; make sure RSP is 16-byte aligned
+ ;
+ ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
+ ; them before calling C-function.
+ ;
+ sub rsp, 0x60
+ movdqa [rsp], xmm0
+ movdqa [rsp + 0x10], xmm1
+ movdqa [rsp + 0x20], xmm2
+ movdqa [rsp + 0x30], xmm3
+ movdqa [rsp + 0x40], xmm4
+ movdqa [rsp + 0x50], xmm5
+
+ add rsp, -0x20
+ call ASM_PFX(SmmInitHandler)
+ add rsp, 0x20
+
+ ;
+ ; Restore XMM0~5 after calling C-function.
+ ;
+ movdqa xmm0, [rsp]
+ movdqa xmm1, [rsp + 0x10]
+ movdqa xmm2, [rsp + 0x20]
+ movdqa xmm3, [rsp + 0x30]
+ movdqa xmm4, [rsp + 0x40]
+ movdqa xmm5, [rsp + 0x50]
+
+ rsm
+
+BITS 16
+ASM_PFX(gcSmmInitTemplate):
+ mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
+ sub ebp, 0x30000
+ jmp ebp
+@L1:
+ DQ ASM_PFX(SmmStartup)
+
+ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
+
+BITS 64
+global ASM_PFX(SmmRelocationSemaphoreComplete)
+ASM_PFX(SmmRelocationSemaphoreComplete):
+ push rax
+ mov rax, [ASM_PFX(mRebasedFlag)]
+ mov byte [rax], 1
+ pop rax
+ jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
+
+;
+; Semaphore code running in 32-bit mode
+;
+global ASM_PFX(SmmRelocationSemaphoreComplete32)
+ASM_PFX(SmmRelocationSemaphoreComplete32):
+ ;
+ ; mov byte ptr [], 1
+ ;
+ db 0xc6, 0x5
+ASM_PFX(mRebasedFlagAddr32): dd 0
+ db 1
+ ;
+ ; jmp dword ptr []
+ ;
+ db 0xff, 0x25
+ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
|