diff options
| author | Heyi Guo <heyi.guo@linaro.org> | 2016-10-12 16:04:31 +0800 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2016-11-29 14:11:35 +0000 |
| commit | 6cb401743fac310b7b0480c0ca3bd2ccfde5e87f (patch) | |
| tree | d2efe105816b7dfc254398bff6306107134b64fd /Platforms/Hisilicon/D02 | |
| parent | f8b67bc325e458ef880f6b5aed4aba265779dd9d (diff) | |
| download | device_linaro_bootloader_OpenPlatformPkg-6cb401743fac310b7b0480c0ca3bd2ccfde5e87f.tar.gz device_linaro_bootloader_OpenPlatformPkg-6cb401743fac310b7b0480c0ca3bd2ccfde5e87f.tar.bz2 device_linaro_bootloader_OpenPlatformPkg-6cb401743fac310b7b0480c0ca3bd2ccfde5e87f.zip | |
Hisilicon/PCIe: support different memory address in PCIe domain
Most of PCIe memory BARs can only be mapped to 4G above system address,
for there is not enough address space under 4G. However, some legacy
PCIe devices may require to be mapped into 32bit address. To support
such devices, a pair of new parameters is introduced to expose memory
address under 4G in PCIe domain, which can be different from the address
in system domain, by setting iATU accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platforms/Hisilicon/D02')
| -rw-r--r-- | Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c index b487b5f..797163a 100644 --- a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c @@ -29,7 +29,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit
0,
0,
- (PCI_HB0RB0_PCI_BASE) //RbPciBar
+ (PCI_HB0RB0_PCI_BASE), //RbPciBar
+ 0,
+ 0
},
/* Port 1 */
{
@@ -42,7 +44,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1, //IoLimit
PCI_HB0RB1_CPUMEMREGIONBASE,
PCI_HB0RB2_CPUIOREGIONBASE,
- (PCI_HB0RB1_PCI_BASE) //RbPciBar
+ (PCI_HB0RB1_PCI_BASE), //RbPciBar
+ PCI_HB0RB1_PCIREGION_BASE,
+ PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1
},
/* Port 2 */
{
@@ -55,7 +59,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1, //IoLimit
PCI_HB0RB2_CPUMEMREGIONBASE,
PCI_HB0RB2_CPUIOREGIONBASE,
- (PCI_HB0RB2_PCI_BASE) //RbPciBar
+ (PCI_HB0RB2_PCI_BASE), //RbPciBar
+ PCI_HB0RB2_PCIREGION_BASE ,
+ PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1
},
/* Port 3 */
@@ -69,7 +75,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit
0,
0,
- (PCI_HB0RB3_PCI_BASE) //RbPciBar
+ (PCI_HB0RB3_PCI_BASE), //RbPciBar
+ 0,
+ 0
}
},
{// HostBridge 1
@@ -84,7 +92,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit
0,
0,
- (PCI_HB1RB0_PCI_BASE) //RbPciBar
+ (PCI_HB1RB0_PCI_BASE), //RbPciBar
+ 0,
+ 0
},
/* Port 1 */
{
@@ -97,7 +107,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit
0,
0,
- (PCI_HB1RB1_PCI_BASE) //RbPciBar
+ (PCI_HB1RB1_PCI_BASE), //RbPciBar
+ 0,
+ 0
},
/* Port 2 */
{
@@ -110,7 +122,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit
0,
0,
- (PCI_HB1RB2_PCI_BASE) //RbPciBar
+ (PCI_HB1RB2_PCI_BASE), //RbPciBar
+ 0,
+ 0
},
/* Port 3 */
@@ -124,7 +138,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit
0,
0,
- (PCI_HB1RB3_PCI_BASE) //RbPciBar
+ (PCI_HB1RB3_PCI_BASE), //RbPciBar
+ 0,
+ 0
}
}
};
|