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| author | flyingnosky <flyingnosky@163.com> | 2016-09-01 15:01:02 +0800 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2016-12-08 12:52:23 +0000 |
| commit | 8114d25709b8f503773140d642328e73ed9d3121 (patch) | |
| tree | 6752761779c67d850940821156972785ec8f295f /Chips/Hisilicon | |
| parent | 191c7cfd916b7b532ca0c42d428ecc463937cccc (diff) | |
| download | device_linaro_bootloader_OpenPlatformPkg-8114d25709b8f503773140d642328e73ed9d3121.tar.gz device_linaro_bootloader_OpenPlatformPkg-8114d25709b8f503773140d642328e73ed9d3121.tar.bz2 device_linaro_bootloader_OpenPlatformPkg-8114d25709b8f503773140d642328e73ed9d3121.zip | |
D03/ACPI: support 50MHZ and 66MHZ boards in acpi mode
1. Check the value of register(0xD000E014) to decide whether this is 50MHZ
or 66MHZ board attached. Configure register PHY_CTRL to support 50MHZ or
66MHZ. Default Configure of PHY_CTRL is the configure of 50MHZ, if 66MHZ
board attached, change the value of PHY_CTRL.
2. D03 have 66M and 50M two types boards, they refer the different
reference clock, set the PCD to 0 so that the code will read frequency
from register and be adapted to 66M and 50M boards, so also update
FVMAIN_SEC binary to adapt different configuration about 50MHZ and
66MHZ boards.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Xiang Chen <chenxiang66@Hisilicon.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Chips/Hisilicon')
| -rw-r--r-- | Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 122 |
1 files changed, 121 insertions, 1 deletions
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index e19ea18..9944a50 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -80,6 +80,32 @@ Scope(_SB) STS, 32,
}
+ OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000)
+ Field (PHYS, DWordAcc, NoLock, Preserve) {
+ Offset (0x0014),
+ PHY0, 32,
+ Offset (0x0414),
+ PHY1, 32,
+ Offset (0x0814),
+ PHY2, 32,
+ Offset (0x0c14),
+ PHY3, 32,
+ Offset (0x1014),
+ PHY4, 32,
+ Offset (0x1414),
+ PHY5, 32,
+ Offset (0x1814),
+ PHY6, 32,
+ Offset (0x1c14),
+ PHY7, 32,
+ }
+
+ OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+ Field (SYSR, DWordAcc, NoLock, Preserve) {
+ Offset (0xe014),
+ DIE4, 32,
+ }
+
Method (_RST, 0x0, Serialized)
{
Store(0x7ffff, RST)
@@ -88,6 +114,19 @@ Scope(_SB) Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
+ Store(DIE4, local0)
+ If (LEqual (local0, 0)) {
+ /* 66MHZ */
+ Store(0x0199B694, Local1)
+ Store(Local1, PHY0)
+ Store(Local1, PHY1)
+ Store(Local1, PHY2)
+ Store(Local1, PHY3)
+ Store(Local1, PHY4)
+ Store(Local1, PHY5)
+ Store(Local1, PHY6)
+ Store(Local1, PHY7)
+ }
}
}
@@ -157,6 +196,32 @@ Scope(_SB) STS, 32,
}
+ OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000)
+ Field (PHYS, DWordAcc, NoLock, Preserve) {
+ Offset (0x0014),
+ PHY0, 32,
+ Offset (0x0414),
+ PHY1, 32,
+ Offset (0x0814),
+ PHY2, 32,
+ Offset (0x0c14),
+ PHY3, 32,
+ Offset (0x1014),
+ PHY4, 32,
+ Offset (0x1414),
+ PHY5, 32,
+ Offset (0x1814),
+ PHY6, 32,
+ Offset (0x1c14),
+ PHY7, 32,
+ }
+
+ OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+ Field (SYSR, DWordAcc, NoLock, Preserve) {
+ Offset (0xe014),
+ DIE4, 32,
+ }
+
Method (_RST, 0x0, Serialized)
{
Store(0x7ffff, RST)
@@ -165,6 +230,19 @@ Scope(_SB) Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
+ Store(DIE4, local0)
+ If (LEqual (local0, 0)) {
+ /* 66MHZ */
+ Store(0x0199B694, Local1)
+ Store(Local1, PHY0)
+ Store(Local1, PHY1)
+ Store(Local1, PHY2)
+ Store(Local1, PHY3)
+ Store(Local1, PHY4)
+ Store(Local1, PHY5)
+ Store(Local1, PHY6)
+ Store(Local1, PHY7)
+ }
}
}
@@ -216,7 +294,7 @@ Scope(_SB) Package () {"interrupt-parent",Package() {\_SB.MBI2}},
Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
Package () {"queue-count", 16},
- Package () {"phy-count", 8},
+ Package () {"phy-count", 9},
}
})
@@ -233,6 +311,34 @@ Scope(_SB) STS, 32,
}
+ OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400)
+ Field (PHYS, DWordAcc, NoLock, Preserve) {
+ Offset (0x0014),
+ PHY0, 32,
+ Offset (0x0414),
+ PHY1, 32,
+ Offset (0x0814),
+ PHY2, 32,
+ Offset (0x0c14),
+ PHY3, 32,
+ Offset (0x1014),
+ PHY4, 32,
+ Offset (0x1414),
+ PHY5, 32,
+ Offset (0x1814),
+ PHY6, 32,
+ Offset (0x1c14),
+ PHY7, 32,
+ offset (0x2014),
+ PHY8, 32,
+ }
+
+ OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+ Field (SYSR, DWordAcc, NoLock, Preserve) {
+ Offset (0xe014),
+ DIE4, 32,
+ }
+
Method (_RST, 0x0, Serialized)
{
Store(0x7ffff, RST)
@@ -241,6 +347,20 @@ Scope(_SB) Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
+ Store(DIE4, local0)
+ If (LEqual (local0, 0)) {
+ /* 66MHZ */
+ Store(0x0199B694, Local1)
+ Store(Local1, PHY0)
+ Store(Local1, PHY1)
+ Store(Local1, PHY2)
+ Store(Local1, PHY3)
+ Store(Local1, PHY4)
+ Store(Local1, PHY5)
+ Store(Local1, PHY6)
+ Store(Local1, PHY7)
+ Store(Local1, PHY8)
+ }
}
}
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