Merge pull request #68 from johnstultz-work/bootloader-update

Update AOSP source branch to more recent OpenPlatformPkg code
author: Haojian Zhuang <haojian.zhuang@linaro.org> 2017-11-09 10:38:31 +0800
committer: GitHub <noreply@github.com> 2017-11-09 10:38:31 +0800
commit: afdc321b862b4279e8faca4e20c99c7981c93897 (patch)
tree: 0169d848937191cf10d3432ba578659062e8738d
parent: 473e79955da9c1ba38a63fd3eefe5fd04f5cab35 (diff)
parent: cf17095317ae5a2704c439e93459595e8f249579 (diff)
download: device_linaro_bootloader_OpenPlatformPkg-afdc321b862b4279e8faca4e20c99c7981c93897.tar.gz
device_linaro_bootloader_OpenPlatformPkg-afdc321b862b4279e8faca4e20c99c7981c93897.tar.bz2
device_linaro_bootloader_OpenPlatformPkg-afdc321b862b4279e8faca4e20c99c7981c93897.zip
859 files changed, 155789 insertions, 33263 deletions
diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 0000000..ab4583b
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1 @@
+*.depex binary
diff --git a/Applications/EepromCmd/EepromCmd.c b/Applications/EepromCmd/EepromCmd.c
new file mode 100644
index 0000000..f43e411
--- /dev/null
+++ b/Applications/EepromCmd/EepromCmd.c
@@ -0,0 +1,397 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <Uefi.h>
+
+#include <ShellBase.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ShellCommandLib.h>
+#include <Library/ShellLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PrintLib.h>
+#include <Library/HiiLib.h>
+
+#include <Library/UefiLib.h>
+#include <Library/ShellCEntryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Eeprom.h>
+
+#define I2C_DEVICE_INDEX(bus, address) (((address) & 0xffff) | (bus) << 16)
+#define I2C_DEVICE_ADDRESS(index) ((index) & 0xffff)
+#define I2C_DEVICE_BUS(index) ((index) >> 16)
+
+CONST CHAR16 ShellEepromFileName[] = L"ShellCommand";
+EFI_HANDLE ShellEepromHiiHandle = NULL;
+
+STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
+  {L"-d", TypeValue},
+  {L"-m", TypeValue},
+  {L"read", TypeFlag},
+  {L"write", TypeFlag},
+  {L"list", TypeFlag},
+  {L"help", TypeFlag},
+  {NULL , TypeMax}
+  };
+
+/**
+  Return the file name of the help text file if not using HII.
+
+  @return The string pointer to the file name.
+**/
+STATIC
+CONST CHAR16*
+EFIAPI
+ShellCommandGetManFileNameEeprom (
+  VOID
+  )
+{
+  return ShellEepromFileName;
+}
+
+STATIC
+VOID
+Usage (
+  VOID
+  )
+{
+  Print (L"Basic EEPROM commands:\n"
+         "eeprom [read] [write] [list] [<Chip>] [<Bus>][<Address>] [<Length>] [-d <Data>] [-m <Source>]\n"
+         "All modes except 'list' require Address, Length and Chip set.\n\n"
+         "read    - read from EEPROM\n"
+         "write   - write Data to EEPROM, requires -d\n"
+         "list    - list available EEPROM devices\n\n"
+         "-m      - transfer from/to RAM memory\n\n"
+         "Chip    - EEPROM bus address\n"
+         "Bus     - I2C bus address\n"
+         "Address - address in EEPROM to read/write\n"
+         "Data    - data byte to be written\n"
+         "Length  - length of data to read/write/copy\n"
+         "Source  - address of data in RAM to be copied\n"
+         "Examples:\n"
+         "List devices:\n"
+         " eeprom list\n"
+         "Read 16 bytes from address 0x0 in chip 0x57:\n"
+         " eeprom read 0x57 0x0 0x0 0x10\n"
+         "Fill 16 bytes with 0xab at address 0x0 in chip 0x57:\n"
+         " eeprom write 0x57 0x0 0x0 0x10 -d 0xab\n"
+         "Copy 32 bytes from 0x2000000 in RAM to EEPROM:\n"
+         " eeprom write 0x57 0x0 0x0 0x20 -m 0x2000000\n"
+         "Copy 32 bytes from EEPROM to RAM:\n"
+         " eeprom read 0x57 0x0 0x0 0x20 -m 0x2000000\n"
+  );
+}
+
+STATIC
+EFI_STATUS
+EepromList (
+    )
+{
+  EFI_HANDLE *HandleBuffer;
+  EFI_STATUS Status;
+  UINTN ProtocolCount;
+  MARVELL_EEPROM_PROTOCOL *EepromProtocol;
+  UINTN i;
+  Status = gBS->LocateHandleBuffer ( ByProtocol,
+                                     &gMarvellEepromProtocolGuid,
+                                     NULL,
+                                     &ProtocolCount,
+                                     &HandleBuffer
+                                   );
+  if (ProtocolCount == 0) {
+    Print (L"0 devices found.\n");
+  } else {
+    Print (L"%u devices found: ", ProtocolCount);
+  }
+
+  for (i = 0; i < ProtocolCount; i++) {
+    Status = gBS->OpenProtocol (
+                    HandleBuffer[i],
+                    &gMarvellEepromProtocolGuid,
+                    (VOID **) &EepromProtocol,
+                    gImageHandle,
+                    NULL,
+                    EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL );
+    Print (L"0x%x at bus %d\n", I2C_DEVICE_ADDRESS(EepromProtocol->Identifier),
+        I2C_DEVICE_BUS(EepromProtocol->Identifier));
+    Status = gBS->CloseProtocol ( HandleBuffer[i],
+                                  &gMarvellEepromProtocolGuid,
+                                  gImageHandle,
+                                  NULL );
+  }
+  Print (L"\n");
+  return Status;
+}
+
+STATIC
+EFI_STATUS
+EepromLocateProtocol (
+ IN  UINT32 Identifier,
+ OUT EFI_HANDLE *FoundHandle,
+ OUT MARVELL_EEPROM_PROTOCOL **FoundEepromProtocol
+ )
+{
+  EFI_HANDLE *HandleBuffer;
+  EFI_STATUS Status;
+  UINTN ProtocolCount;
+  MARVELL_EEPROM_PROTOCOL *EepromProtocol;
+  UINTN i;
+  Status = gBS->LocateHandleBuffer ( ByProtocol,
+                                     &gMarvellEepromProtocolGuid,
+                                     NULL,
+                                     &ProtocolCount,
+                                     &HandleBuffer
+                                   );
+  if (EFI_ERROR(Status))
+    return Status;
+
+  for (i = 0; i < ProtocolCount; i++) {
+    Status = gBS->OpenProtocol (
+                    HandleBuffer[i],
+                    &gMarvellEepromProtocolGuid,
+                    (VOID **) &EepromProtocol,
+                    gImageHandle,
+                    NULL,
+                    EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL );
+    if (EepromProtocol->Identifier == Identifier) {
+      *FoundEepromProtocol = EepromProtocol;
+      *FoundHandle = HandleBuffer[i];
+      return EFI_SUCCESS;
+    }
+    Status = gBS->CloseProtocol ( HandleBuffer[i],
+                                  &gMarvellEepromProtocolGuid,
+                                  gImageHandle,
+                                  NULL );
+  }
+  *FoundEepromProtocol = NULL;
+  return EFI_UNSUPPORTED;
+}
+
+SHELL_STATUS
+EFIAPI
+ShellCommandRunEeprom (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS              Status;
+  LIST_ENTRY              *CheckPackage;
+  CHAR16                  *ProblemParam;
+  CONST CHAR16            *ValueStr;
+  UINTN                   Address, Length, Chip, Source, Bus;
+  UINT8                   Data;
+  UINT8                   *Buffer;
+  BOOLEAN                 ReadMode, MemMode;
+  EFI_HANDLE              Handle, ProtHandle;
+  MARVELL_EEPROM_PROTOCOL *EepromProtocol = NULL;
+  UINTN                   Count, HandleSize;
+
+  Handle = NULL;
+  Source = 0;
+  HandleSize = 2 * sizeof (EFI_HANDLE);
+
+  Status = gBS->LocateHandle (ByProtocol, &gMarvellEepromProtocolGuid, NULL,
+    &HandleSize, &ProtHandle);
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_INFO, "No Eeprom protocol, connect I2C stack\n"));
+    Status = gBS->LocateHandle (ByProtocol, &gEfiI2cMasterProtocolGuid, NULL,
+      &HandleSize, &ProtHandle);
+    if (EFI_ERROR(Status)) {
+      Print (L"Failed to locate I2cMaster protocol, abort!\n");
+      return SHELL_ABORTED;
+    }
+    Status = gBS->ConnectController (ProtHandle, NULL, NULL, TRUE);
+    if (EFI_ERROR(Status)) {
+      Print (L"Cannot connect I2C stack, abort!\n");
+      return SHELL_ABORTED;
+    }
+  }
+
+  Status = ShellInitialize ();
+  if (EFI_ERROR (Status)) {
+    Print (L"Error - failed to initialize shell\n");
+    return SHELL_ABORTED;
+  }
+
+  Status = ShellCommandLineParse (ParamList, &CheckPackage, &ProblemParam, TRUE);
+  if (EFI_ERROR (Status)) {
+    Print (L"Error - failed to parse command line\n");
+    return SHELL_ABORTED;
+  }
+
+  if (ShellCommandLineGetFlag (CheckPackage, L"list")) {
+    EepromList();
+    return SHELL_SUCCESS;
+  }
+
+  if (ShellCommandLineGetFlag (CheckPackage, L"help")) {
+    Usage();
+    return SHELL_SUCCESS;
+  }
+
+  if (ShellCommandLineGetCount(CheckPackage) < 4) {
+    Print (L"Not enough arguments given.\n");
+    Usage();
+  }
+
+  ReadMode = ShellCommandLineGetFlag (CheckPackage, L"read");
+  if (ReadMode == ShellCommandLineGetFlag (CheckPackage, L"write")) {
+    Print (L"Error - type read, write, list or help.\n");
+    return SHELL_INVALID_PARAMETER;
+  }
+
+  MemMode = ShellCommandLineGetFlag (CheckPackage, L"-m");
+  Data = 0;
+  if (!ReadMode && !MemMode) {
+    ValueStr = ShellCommandLineGetValue (CheckPackage, L"-d");
+    if (ValueStr == NULL) {
+      Print (L"Error - no data to write.\n");
+      return SHELL_INVALID_PARAMETER;
+    }
+    Data = ShellHexStrToUintn (ValueStr);
+  }
+
+  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 1);
+  Chip = ShellHexStrToUintn (ValueStr);
+
+  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 2);
+  Bus = ShellHexStrToUintn (ValueStr);
+
+  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 3);
+  Address = ShellHexStrToUintn (ValueStr);
+
+  ValueStr = ShellCommandLineGetRawValue(CheckPackage, 4);
+  Length = ShellHexStrToUintn (ValueStr);
+
+  if (MemMode) {
+    ValueStr = ShellCommandLineGetValue (CheckPackage, L"-m");
+    if (ValueStr == NULL) {
+      Print (L"Error - no memory address given.\n");
+      return SHELL_INVALID_PARAMETER;
+    }
+    Source = ShellHexStrToUintn (ValueStr);
+  }
+
+  EepromLocateProtocol (I2C_DEVICE_INDEX(Bus, Chip), &Handle, &EepromProtocol);
+  if (EepromProtocol == NULL) {
+    Print (L"Failed to locate EEPROM protocol.\n");
+    return SHELL_INVALID_PARAMETER;
+  }
+
+  if (MemMode) {
+    Buffer = (VOID *) Source;
+  } else {
+    Buffer = AllocateZeroPool (Length);
+    if (Buffer == NULL) {
+      Status = SHELL_OUT_OF_RESOURCES;
+      Print (L"Error - out of resources.\n");
+      goto out_close;
+    }
+    if (!ReadMode) {
+      for (Count = 0; Count < Length; Count++)
+        Buffer[Count] = Data;
+    }
+  }
+  EepromProtocol->Transfer(EepromProtocol, Address, Length, Buffer,
+      ReadMode ? EEPROM_READ : EEPROM_WRITE);
+
+  if (MemMode) {
+  Print (L"Transfered succesfully.\n");
+  } else {
+    Print (L"Transfered:\n");
+    for (Count = 0; Count < Length; Count++) {
+      Print(L"0x%x ", Buffer[Count]);
+      if (Count % 8 == 7)
+        Print(L"\n");
+    }
+    Print (L"\n");
+  }
+
+  Status = SHELL_SUCCESS;
+
+  if (!MemMode)
+    FreePool(Buffer);
+out_close:
+  gBS->CloseProtocol ( Handle,
+                       &gMarvellEepromProtocolGuid,
+                       gImageHandle,
+                       NULL );
+
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+ShellEepromCmdLibConstructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+
+  ShellEepromHiiHandle = NULL;
+
+  ShellEepromHiiHandle = HiiAddPackages (
+                          &gShellEepromHiiGuid, gImageHandle,
+                          UefiShellEepromLibStrings, NULL
+                          );
+  if (ShellEepromHiiHandle == NULL) {
+    Print (L"Filed to add Hii package\n");
+    return EFI_DEVICE_ERROR;
+  }
+  ShellCommandRegisterCommandName (
+     L"eeprom", ShellCommandRunEeprom, ShellCommandGetManFileNameEeprom, 0,
+     L"eeprom", TRUE , ShellEepromHiiHandle, STRING_TOKEN (STR_GET_HELP_EEPROM)
+     );
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+ShellEepromCmdLibDestructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+
+  if (ShellEepromHiiHandle != NULL) {
+    HiiRemovePackages (ShellEepromHiiHandle);
+  }
+  return EFI_SUCCESS;
+}
diff --git a/Applications/EepromCmd/EepromCmd.inf b/Applications/EepromCmd/EepromCmd.inf
new file mode 100644
index 0000000..1171fc1
--- /dev/null
+++ b/Applications/EepromCmd/EepromCmd.inf
@@ -0,0 +1,71 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION = 0x00010006
+  BASE_NAME = UefiShellEepromLib
+  FILE_GUID = adf4b61c-2ca3-4e1a-9597-99282f5a4aa2
+  MODULE_TYPE = UEFI_APPLICATION
+  VERSION_STRING = 0.1
+  LIBRARY_CLASS  = NULL|UEFI_APPLICATION UEFI_DRIVER
+  CONSTRUCTOR = ShellEepromCmdLibConstructor
+  DESTRUCTOR  = ShellEepromCmdLibDestructor
+
+[Sources]
+  EepromCmd.c
+  EepromCmd.uni
+
+[Packages]
+  MdePkg/MdePkg.dec
+  ShellPkg/ShellPkg.dec
+  StdLib/StdLib.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  UefiLib
+  UefiBootServicesTableLib
+  MemoryAllocationLib
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  ShellCommandLib
+  ShellLib
+  UefiLib
+  UefiRuntimeServicesTableLib
+  PcdLib
+
+[Protocols]
+ gMarvellEepromProtocolGuid
+ gEfiI2cMasterProtocolGuid
+
+[Guids]
+  gShellEepromHiiGuid
diff --git a/Applications/EepromCmd/EepromCmd.uni b/Applications/EepromCmd/EepromCmd.uni
new file mode 100644
index 0000000..e41c6d8
--- /dev/null
+++ b/Applications/EepromCmd/EepromCmd.uni
diff --git a/Applications/FirmwareUpdate/FUpdate.c b/Applications/FirmwareUpdate/FUpdate.c
new file mode 100644
index 0000000..edb6986
--- /dev/null
+++ b/Applications/FirmwareUpdate/FUpdate.c
@@ -0,0 +1,413 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include <ShellBase.h>
+#include <Uefi.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/FileHandleLib.h>
+#include <Library/HiiLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PrintLib.h>
+#include <Library/ShellCEntryLib.h>
+#include <Library/ShellCommandLib.h>
+#include <Library/ShellLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/Spi.h>
+#include <Protocol/SpiFlash.h>
+
+#define CMD_NAME_STRING       L"fupdate"
+
+#define MAIN_HDR_MAGIC        0xB105B002
+
+STATIC MARVELL_SPI_FLASH_PROTOCOL *SpiFlashProtocol;
+STATIC MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol;
+
+STATIC CONST CHAR16 gShellFUpdateFileName[] = L"ShellCommands";
+STATIC EFI_HANDLE gShellFUpdateHiiHandle = NULL;
+
+STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
+  {L"help", TypeFlag},
+  {NULL , TypeMax}
+  };
+
+typedef struct {              // Bytes
+  UINT32  Magic;              //  0-3
+  UINT32  PrologSize;         //  4-7
+  UINT32  PrologChecksum;     //  8-11
+  UINT32  BootImageSize;      // 12-15
+  UINT32  BootImageChecksum;  // 16-19
+  UINT32  Reserved0;          // 20-23
+  UINT32  LoadAddr;           // 24-27
+  UINT32  ExecAddr;           // 28-31
+  UINT8   UartConfig;         //  32
+  UINT8   Baudrate;           //  33
+  UINT8   ExtCount;           //  34
+  UINT8   AuxFlags;           //  35
+  UINT32  IoArg0;             // 36-39
+  UINT32  IoArg1;             // 40-43
+  UINT32  IoArg2;             // 43-47
+  UINT32  IoArg3;             // 48-51
+  UINT32  Reserved1;          // 52-55
+  UINT32  Reserved2;          // 56-59
+  UINT32  Reserved3;          // 60-63
+} MV_FIRMWARE_IMAGE_HEADER;
+
+STATIC
+EFI_STATUS
+SpiFlashProbe (
+  IN SPI_DEVICE    *Slave
+  )
+{
+  EFI_STATUS       Status;
+  UINT32           IdBuffer, Id, RefId;
+
+  Id = PcdGet32 (PcdSpiFlashId);
+
+  IdBuffer = CMD_READ_ID & 0xff;
+
+  // Read SPI flash ID
+  SpiFlashProtocol->ReadId (Slave, sizeof (UINT32), (UINT8 *)&IdBuffer);
+
+  // Swap and extract 3 bytes of the ID
+  RefId = SwapBytes32 (IdBuffer) >> 8;
+
+  if (RefId == 0) {
+    Print (L"%s: No SPI flash detected");
+    return EFI_DEVICE_ERROR;
+  } else if (RefId != Id) {
+    Print (L"%s: Unsupported SPI flash detected with ID=%2x\n", CMD_NAME_STRING, RefId);
+    return EFI_DEVICE_ERROR;
+  }
+
+  Print (L"%s: Detected supported SPI flash with ID=%3x\n", CMD_NAME_STRING, RefId);
+
+  Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave);
+  if (EFI_ERROR(Status)) {
+    Print (L"%s: Cannot initialize flash device\n", CMD_NAME_STRING);
+    return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+CheckImageHeader (
+  IN OUT UINTN *ImageHeader
+  )
+{
+  MV_FIRMWARE_IMAGE_HEADER *Header;
+  UINT32 HeaderLength, Checksum, ChecksumBackup;
+
+  Header = (MV_FIRMWARE_IMAGE_HEADER *)ImageHeader;
+  HeaderLength = Header->PrologSize;
+  ChecksumBackup = Header->PrologChecksum;
+
+  // Compare magic number
+  if (Header->Magic != MAIN_HDR_MAGIC) {
+    Print (L"%s: Bad Image magic 0x%08x != 0x%08x\n", CMD_NAME_STRING, Header->Magic, MAIN_HDR_MAGIC);
+    return EFI_DEVICE_ERROR;
+  }
+
+  // The checksum field is discarded from calculation
+  Header->PrologChecksum = 0;
+
+  Checksum = CalculateSum32 ((UINT32 *)Header, HeaderLength);
+  if (Checksum != ChecksumBackup) {
+    Print (L"%s: Bad Image checksum. 0x%x != 0x%x\n", CMD_NAME_STRING, Checksum, ChecksumBackup);
+    return EFI_DEVICE_ERROR;
+  }
+
+  // Restore checksum backup
+  Header->PrologChecksum = ChecksumBackup;
+
+  return 0;
+}
+
+STATIC
+EFI_STATUS
+PrepareFirmwareImage (
+  IN LIST_ENTRY             *CheckPackage,
+  IN OUT SHELL_FILE_HANDLE  *FileHandle,
+  IN OUT UINTN              **FileBuffer,
+  IN OUT UINTN              *FileSize
+  )
+{
+  CONST CHAR16         *FileStr;
+  EFI_STATUS           Status;
+  UINT64               OpenMode;
+  UINTN                *Buffer;
+
+  // Parse string from commandline
+  FileStr = ShellCommandLineGetRawValue (CheckPackage, 1);
+  if (FileStr == NULL) {
+    Print (L"%s: No image specified\n", CMD_NAME_STRING);
+    return EFI_INVALID_PARAMETER;
+  } else {
+    Status = ShellIsFile (FileStr);
+    if (EFI_ERROR(Status)) {
+      Print (L"%s: File not found\n", CMD_NAME_STRING);
+      return EFI_INVALID_PARAMETER;
+    }
+  }
+
+  // Obtain file size
+  OpenMode = EFI_FILE_MODE_READ;
+
+  Status = ShellOpenFileByName (FileStr, FileHandle, OpenMode, 0);
+    if (EFI_ERROR (Status)) {
+      Print (L"%s: Cannot open Image file\n", CMD_NAME_STRING);
+      return EFI_DEVICE_ERROR;
+    }
+
+  Status = FileHandleGetSize (*FileHandle, FileSize);
+    if (EFI_ERROR (Status)) {
+      Print (L"%s: Cannot get Image file size\n", CMD_NAME_STRING);
+    }
+
+  // Read Image header into buffer
+  Buffer = AllocateZeroPool (*FileSize);
+
+  Status = FileHandleRead (*FileHandle, FileSize, Buffer);
+  if (EFI_ERROR (Status)) {
+    Print (L"%s: Cannot read Image file header\n", CMD_NAME_STRING);
+    ShellCloseFile (FileHandle);
+    FreePool (Buffer);
+    return EFI_DEVICE_ERROR;
+  }
+
+  *FileBuffer = Buffer;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Return the file name of the help text file if not using HII.
+
+  @return The string pointer to the file name.
+**/
+STATIC
+CONST CHAR16*
+EFIAPI
+ShellCommandGetManFileNameFUpdate (
+  VOID
+  )
+{
+  return gShellFUpdateFileName;
+}
+
+STATIC
+VOID
+FUpdateUsage (
+  VOID
+  )
+{
+  Print (L"\nFirmware update command\n"
+         "fupdate <LocalFilePath>\n\n"
+         "LocalFilePath - path to local firmware image file\n"
+         "Example:\n"
+         "Update firmware from file fs2:flash-image.bin\n"
+         "  fupdate fs2:flash-image.bin\n"
+  );
+}
+
+STATIC
+SHELL_STATUS
+EFIAPI
+ShellCommandRunFUpdate (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  IN SHELL_FILE_HANDLE    FileHandle;
+  SPI_DEVICE              *Slave;
+  UINTN                   FileSize;
+  UINTN                   *FileBuffer = NULL;
+  CHAR16                  *ProblemParam;
+  LIST_ENTRY              *CheckPackage;
+  EFI_STATUS              Status;
+
+  // Locate SPI protocols
+  Status = gBS->LocateProtocol (
+                   &gMarvellSpiFlashProtocolGuid,
+                   NULL,
+                   (VOID **)&SpiFlashProtocol
+                 );
+
+  if (EFI_ERROR(Status)) {
+    Print (L"%s: Cannot locate SpiFlash protocol\n", CMD_NAME_STRING);
+    return SHELL_ABORTED;
+  }
+
+  Status = gBS->LocateProtocol (
+                   &gMarvellSpiMasterProtocolGuid,
+                   NULL,
+                   (VOID **)&SpiMasterProtocol
+                 );
+
+  if (EFI_ERROR(Status)) {
+    Print (L"%s: Cannot locate SpiMaster protocol\n", CMD_NAME_STRING);
+    return SHELL_ABORTED;
+  }
+
+  // Parse command line
+  Status = ShellInitialize ();
+  if (EFI_ERROR (Status)) {
+    Print (L"%s: Error while initializing Shell\n", CMD_NAME_STRING);
+    ASSERT_EFI_ERROR (Status);
+    return SHELL_ABORTED;
+  }
+
+  Status = ShellCommandLineParse (ParamList, &CheckPackage, &ProblemParam, TRUE);
+  if (EFI_ERROR (Status)) {
+    Print (L"%s: Invalid parameter\n", CMD_NAME_STRING);
+    return SHELL_ABORTED;
+  }
+
+  if (ShellCommandLineGetFlag (CheckPackage, L"help")) {
+    FUpdateUsage();
+    return EFI_SUCCESS;
+  }
+
+  // Prepare local file to be burned into flash
+  Status = PrepareFirmwareImage (CheckPackage, &FileHandle, &FileBuffer, &FileSize);
+  if (EFI_ERROR(Status)) {
+    return SHELL_ABORTED;
+  }
+
+  // Check image checksum and magic
+  Status = CheckImageHeader (FileBuffer);
+  if (EFI_ERROR(Status)) {
+    goto HeaderError;
+  }
+
+  // Setup and probe SPI flash
+  Slave = SpiMasterProtocol->SetupDevice (SpiMasterProtocol, 0, 0);
+  if (Slave == NULL) {
+    Print(L"%s: Cannot allocate SPI device!\n", CMD_NAME_STRING);
+    goto HeaderError;
+  }
+
+  Status = SpiFlashProbe (Slave);
+  if (EFI_ERROR(Status)) {
+    Print (L"%s: Error while performing SPI flash probe\n", CMD_NAME_STRING);
+    goto FlashProbeError;
+  }
+
+  // Update firmware image in flash at offset 0x0
+  Status = SpiFlashProtocol->Update (Slave, 0, FileSize, (UINT8 *)FileBuffer);
+
+  // Release resources
+  SpiMasterProtocol->FreeDevice(Slave);
+  FreePool (FileBuffer);
+  ShellCloseFile (&FileHandle);
+
+  if (EFI_ERROR(Status)) {
+    Print (L"%s: Error while performing flash update\n", CMD_NAME_STRING);
+    return SHELL_ABORTED;
+  }
+
+  Print (L"%s: Update %d bytes at offset 0x0 succeeded!\n", CMD_NAME_STRING, FileSize);
+
+  return EFI_SUCCESS;
+
+FlashProbeError:
+  SpiMasterProtocol->FreeDevice(Slave);
+HeaderError:
+  FreePool (FileBuffer);
+  ShellCloseFile (&FileHandle);
+
+  return SHELL_ABORTED;
+}
+
+EFI_STATUS
+EFIAPI
+ShellFUpdateCommandConstructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS Status;
+
+  gShellFUpdateHiiHandle = NULL;
+
+  gShellFUpdateHiiHandle = HiiAddPackages (
+                                  &gShellFUpdateHiiGuid,
+                                  gImageHandle,
+                                  UefiShellFUpdateCommandLibStrings,
+                                  NULL
+                                );
+
+  if (gShellFUpdateHiiHandle == NULL) {
+    Print (L"%s: Cannot add Hii package\n", CMD_NAME_STRING);
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = ShellCommandRegisterCommandName (
+                           CMD_NAME_STRING,
+                           ShellCommandRunFUpdate,
+                           ShellCommandGetManFileNameFUpdate,
+                           0,
+                           CMD_NAME_STRING,
+                           TRUE,
+                           gShellFUpdateHiiHandle,
+                           STRING_TOKEN (STR_GET_HELP_FUPDATE)
+                         );
+
+  if (EFI_ERROR(Status)) {
+    Print (L"%s: Error while registering command\n", CMD_NAME_STRING);
+    return SHELL_ABORTED;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+ShellFUpdateCommandDestructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+
+  if (gShellFUpdateHiiHandle != NULL) {
+    HiiRemovePackages (gShellFUpdateHiiHandle);
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Applications/FirmwareUpdate/FUpdate.inf b/Applications/FirmwareUpdate/FUpdate.inf
new file mode 100644
index 0000000..4d4b97e
--- /dev/null
+++ b/Applications/FirmwareUpdate/FUpdate.inf
@@ -0,0 +1,75 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION = 0x00010019
+  BASE_NAME = UefiShellFUpdateCommandLib
+  FILE_GUID = 470292b2-926b-4ed8-8080-be7a260db627
+  MODULE_TYPE = UEFI_APPLICATION
+  VERSION_STRING = 0.1
+  LIBRARY_CLASS = NULL|UEFI_APPLICATION UEFI_DRIVER
+  CONSTRUCTOR = ShellFUpdateCommandConstructor
+  DESTRUCTOR = ShellFUpdateCommandDestructor
+
+[Sources]
+  FUpdate.c
+  FUpdate.uni
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+  ShellPkg/ShellPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  FileHandleLib
+  HiiLib
+  MemoryAllocationLib
+  PcdLib
+  ShellCommandLib
+  ShellLib
+  UefiBootServicesTableLib
+  UefiLib
+  UefiLib
+  UefiRuntimeServicesTableLib
+
+[Pcd]
+ gMarvellTokenSpaceGuid.PcdSpiFlashId
+
+[Protocols]
+ gMarvellSpiFlashProtocolGuid
+ gMarvellSpiMasterProtocolGuid
+
+[Guids]
+  gShellFUpdateHiiGuid
diff --git a/Applications/FirmwareUpdate/FUpdate.uni b/Applications/FirmwareUpdate/FUpdate.uni
new file mode 100644
index 0000000..9d52e59
--- /dev/null
+++ b/Applications/FirmwareUpdate/FUpdate.uni
diff --git a/Applications/SpiTool/SpiFlashCmd.c b/Applications/SpiTool/SpiFlashCmd.c
new file mode 100644
index 0000000..184e3d7
--- /dev/null
+++ b/Applications/SpiTool/SpiFlashCmd.c
@@ -0,0 +1,526 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include <Uefi.h>
+#include <ShellBase.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ShellCommandLib.h>
+#include <Library/ShellLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PrintLib.h>
+#include <Library/ShellCEntryLib.h>
+#include <Library/HiiLib.h>
+#include <Library/FileHandleLib.h>
+
+#include <Protocol/Spi.h>
+#include <Protocol/SpiFlash.h>
+
+MARVELL_SPI_FLASH_PROTOCOL *SpiFlashProtocol;
+MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol;
+
+CONST CHAR16 gShellSpiFlashFileName[] = L"ShellCommand";
+EFI_HANDLE gShellSfHiiHandle = NULL;
+
+BOOLEAN InitFlag = 1;
+
+STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
+  {L"read", TypeFlag},
+  {L"readfile", TypeFlag},
+  {L"write", TypeFlag},
+  {L"writefile", TypeFlag},
+  {L"erase", TypeFlag},
+  {L"update", TypeFlag},
+  {L"updatefile", TypeFlag},
+  {L"probe", TypeFlag},
+  {L"help", TypeFlag},
+  {NULL , TypeMax}
+  };
+
+typedef enum {
+  PROBE       = 1,
+  READ        = 2,
+  READ_FILE   = 4,
+  WRITE       = 8,
+  WRITE_FILE  = 16,
+  ERASE       = 32,
+  UPDATE      = 64,
+  UPDATE_FILE = 128,
+} Flags;
+
+/**
+  Return the file name of the help text file if not using HII.
+
+  @return The string pointer to the file name.
+**/
+CONST CHAR16*
+EFIAPI
+ShellCommandGetManFileNameSpiFlash (
+  VOID
+  )
+{
+
+  return gShellSpiFlashFileName;
+}
+
+VOID
+SfUsage (
+  VOID
+  )
+{
+  Print (L"\nBasic SPI command\n"
+         "sf [probe | read | readfile | write | writefile | erase |"
+         "update | updatefile]"
+         "[<Address> | <FilePath>] <Offset> <Length>\n\n"
+         "Length   - Number of bytes to send\n"
+         "Address  - Address in RAM to store/load data\n"
+         "FilePath - Path to file to read/write data from/to\n"
+         "Offset   - Offset from beggining of SPI flash to store/load data\n"
+         "Examples:\n"
+         "Check if there is response from SPI flash\n"
+         "  sf probe\n"
+         "Read 32 bytes from 0xe00000 of SPI flash into RAM at address 0x100000\n"
+         "  sf read 0x100000 0xe00000 32\n"
+         "Read 0x20 bytes from 0x200000 of SPI flash into RAM at address 0x300000\n"
+         "  sf read 0x300000 0x200000 0x20\n"
+         "Erase 0x10000 bytes from offset 0x100000 of SPI flash\n"
+         "  sf erase 0x100000 0x100000\n"
+         "Write 16 bytes from 0x200000 at RAM into SPI flash at address 0x4000000\n"
+         "  sf write 0x200000 0x4000000 16\n"
+         "Update 100 bytes from 0x100000 at RAM in SPI flash at address 0xe00000\n"
+         "  sf update 0x100000 0xe00000 100\n"
+         "Read 0x3000 bytes from 0x0 of SPI flash into file fs2:file.bin\n"
+         "  sf readfile fs2:file.bin 0x0 0x3000 \n"
+         "Update data in SPI flash at 0x3000000 from file Linux.efi\n"
+         "  sf updatefile Linux.efi 0x3000000\n"
+  );
+}
+
+STATIC
+EFI_STATUS
+OpenAndPrepareFile (
+  IN CHAR16 *FilePath,
+  SHELL_FILE_HANDLE *FileHandle
+  )
+{
+  EFI_STATUS Status;
+  UINT64 OpenMode;
+
+  OpenMode = EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE;
+
+  Status = ShellOpenFileByName (FilePath, FileHandle, OpenMode, 0);
+  if (EFI_ERROR (Status)) {
+    Print (L"sf: Cannot open file\n");
+    return Status;
+  }
+
+  Status = FileHandleSetPosition(*FileHandle, 0);
+
+  if (EFI_ERROR(Status)) {
+    Print (L"sf: Cannot set file position to first byte\n");
+    ShellCloseFile (FileHandle);
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+FlashProbe (
+  IN SPI_DEVICE       *Slave
+  )
+{
+  EFI_STATUS Status;
+  UINT8  IdBuffer[4];
+  UINT32 Id, RefId;
+
+  Id = PcdGet32 (PcdSpiFlashId);
+
+  IdBuffer[0] = CMD_READ_ID;
+
+  SpiFlashProtocol->ReadId (
+    Slave,
+    4,
+    IdBuffer
+    );
+
+  RefId = (IdBuffer[0] << 16) + (IdBuffer[1] << 8) + IdBuffer[2];
+
+  if (RefId == Id) {
+    Print (L"sf: Detected supported SPI flash with ID=%3x\n", RefId);
+    Status = SpiFlashProtocol->Init (SpiFlashProtocol, Slave);
+    if (EFI_ERROR(Status)) {
+      Print (L"sf: Cannot initialize flash device\n");
+      return SHELL_ABORTED;
+    }
+    InitFlag = 0;
+    return EFI_SUCCESS;
+  } else if (RefId != 0) {
+    Print (L"sf: Unsupported SPI flash detected with ID=%2x\n", RefId);
+    return SHELL_ABORTED;
+  }
+
+  Print (L"sf: No SPI flash detected");
+  return SHELL_ABORTED;
+}
+
+SHELL_STATUS
+EFIAPI
+ShellCommandRunSpiFlash (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+EFI_STATUS              Status;
+  SPI_DEVICE            *Slave;
+  LIST_ENTRY            *CheckPackage;
+  EFI_PHYSICAL_ADDRESS  Address = 0, Offset = 0;
+  SHELL_FILE_HANDLE     FileHandle = NULL;
+  UINTN                 ByteCount, FileSize, I;
+  UINT8                 *Buffer = NULL, *FileBuffer = NULL;
+  CHAR16                *ProblemParam, *FilePath;
+  CONST CHAR16          *AddressStr = NULL, *OffsetStr = NULL;
+  CONST CHAR16          *LengthStr = NULL, *FileStr = NULL;
+  BOOLEAN               AddrFlag = FALSE, LengthFlag = TRUE, FileFlag = FALSE;
+  UINT8                 Flag = 0, CheckFlag = 0;
+
+  Status = gBS->LocateProtocol (
+    &gMarvellSpiFlashProtocolGuid,
+    NULL,
+    (VOID **)&SpiFlashProtocol
+  );
+  if (EFI_ERROR(Status)) {
+    Print (L"sf: Cannot locate SpiFlash protocol\n");
+    return SHELL_ABORTED;
+  }
+
+  Status = gBS->LocateProtocol (
+    &gMarvellSpiMasterProtocolGuid,
+    NULL,
+    (VOID **)&SpiMasterProtocol
+  );
+  if (EFI_ERROR(Status)) {
+    Print (L"sf: Cannot locate SpiMaster protocol\n");
+    return SHELL_ABORTED;
+  }
+
+  // Parse Shell command line
+  Status = ShellInitialize ();
+  if (EFI_ERROR (Status)) {
+    Print (L"sf: Cannot initialize Shell\n");
+    ASSERT_EFI_ERROR (Status);
+    return SHELL_ABORTED;
+  }
+
+  Status = ShellCommandLineParse (ParamList, &CheckPackage, &ProblemParam, TRUE);
+  if (EFI_ERROR (Status)) {
+    Print (L"sf: Error while parsing command line\n");
+    return SHELL_ABORTED;
+  }
+
+  if (ShellCommandLineGetFlag (CheckPackage, L"help")) {
+    SfUsage();
+    return EFI_SUCCESS;
+  }
+
+  // Check flags provided by user
+  Flag |= (ShellCommandLineGetFlag (CheckPackage, L"probe") << 0);
+  Flag |= (ShellCommandLineGetFlag (CheckPackage, L"read") << 1);
+  Flag |= (ShellCommandLineGetFlag (CheckPackage, L"readfile") << 2);
+  Flag |= (ShellCommandLineGetFlag (CheckPackage, L"write") << 3);
+  Flag |= (ShellCommandLineGetFlag (CheckPackage, L"writefile") << 4);
+  Flag |= (ShellCommandLineGetFlag (CheckPackage, L"erase") << 5);
+  Flag |= (ShellCommandLineGetFlag (CheckPackage, L"update") << 6);
+  Flag |= (ShellCommandLineGetFlag (CheckPackage, L"updatefile") << 7);
+
+  if (InitFlag && !(Flag & PROBE)) {
+    Print (L"Please run sf probe\n");
+    return EFI_SUCCESS;
+  }
+
+  CheckFlag = Flag;
+  for (I = 0; CheckFlag; CheckFlag >>= 1) {
+    I += CheckFlag & 1;
+    if (I > 1) {
+      Print (L"sf: Too many flags\n");
+      SfUsage();
+      return SHELL_ABORTED;
+    }
+  }
+
+  // Setup new spi device
+  Slave = SpiMasterProtocol->SetupDevice (SpiMasterProtocol, 0, 0);
+    if (Slave == NULL) {
+      Print(L"sf: Cannot allocate SPI device!\n");
+      return SHELL_ABORTED;
+    }
+
+  switch (Flag) {
+  case PROBE:
+    // Probe spi bus
+    Status = FlashProbe (Slave);
+    if (EFI_ERROR(Status)) {
+      // No supported spi flash detected
+      return SHELL_ABORTED;
+    } else {
+      return Status;
+    }
+    break;
+  // Fall through
+  case READ:
+  case WRITE:
+  case UPDATE:
+    AddressStr = ShellCommandLineGetRawValue (CheckPackage, 1);
+    OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2);
+    LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3);
+    AddrFlag = TRUE;
+    break;
+  case ERASE:
+    OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 1);
+    LengthStr = ShellCommandLineGetRawValue (CheckPackage, 2);
+    break;
+  case READ_FILE:
+    FileStr = ShellCommandLineGetRawValue (CheckPackage, 1);
+    OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2);
+    LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3);
+    FileFlag = TRUE;
+    break;
+  case WRITE_FILE:
+  case UPDATE_FILE:
+    FileStr = ShellCommandLineGetRawValue (CheckPackage, 1);
+    OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2);
+    LengthFlag = FALSE;
+    FileFlag = TRUE;
+    break;
+  }
+
+  // Read address parameter
+  if ((AddressStr == NULL) & AddrFlag) {
+    Print (L"sf: No address parameter!\n");
+    return SHELL_ABORTED;
+  } else if (AddrFlag) {
+    Address = ShellHexStrToUintn (AddressStr);
+    if (Address == (UINTN)(-1)) {
+      Print (L"sf: Wrong address parameter\n");
+      return SHELL_ABORTED;
+    }
+  }
+
+  // Read offset parameter
+  if (OffsetStr == NULL) {
+    Print (L"sf: No offset Parameter!\n");
+    return SHELL_ABORTED;
+  } else {
+    Offset = ShellHexStrToUintn (OffsetStr);
+    if (Offset < 0) {
+      Print (L"sf: Wrong offset parameter: %s", OffsetStr);
+      return SHELL_ABORTED;
+    }
+  }
+
+  // Read length parameter
+  if ((LengthStr == NULL) & LengthFlag) {
+    Print (L"sf: No lenght parameter!\n");
+    return SHELL_ABORTED;
+  } else if (LengthFlag) {
+    ByteCount = ShellStrToUintn (LengthStr);
+    if (ByteCount < 0) {
+      Print (L"sf: Wrong length parameter %s!\n", LengthStr);
+      return SHELL_ABORTED;
+    }
+  }
+
+  if (FileFlag) {
+    // Read FilePath parameter
+    if (FileStr == NULL) {
+      Print (L"sf: No FilePath parameter!\n");
+      return SHELL_ABORTED;
+    } else {
+      FilePath = (CHAR16 *) FileStr;
+      Status = ShellIsFile (FilePath);
+      // When read file into flash, file doesn't have to exist
+      if (EFI_ERROR(Status && !(Flag & READ_FILE))) {
+        Print (L"sf: Wrong FilePath parameter!\n");
+        return SHELL_ABORTED;
+      }
+    }
+
+    Status = OpenAndPrepareFile (FilePath, &FileHandle);
+    if (EFI_ERROR(Status)) {
+      Print (L"sf: Error while preparing file\n");
+      return SHELL_ABORTED;
+    }
+
+    // Get file size in order to check correctness at the end of transfer
+    if (Flag & (WRITE_FILE | UPDATE_FILE)) {
+      Status = FileHandleGetSize (FileHandle, &FileSize);
+      if (EFI_ERROR (Status)) {
+        Print (L"sf: Cannot get file size\n");
+      }
+      ByteCount = (UINTN) FileSize;
+    }
+
+    FileBuffer = AllocateZeroPool ((UINTN) ByteCount);
+    if (FileBuffer == NULL) {
+      Print (L"sf: Cannot allocate memory\n");
+      goto Error_Close_File;
+    }
+
+    // Read file content and store it in FileBuffer
+    if (Flag & (WRITE_FILE | UPDATE_FILE)) {
+      Status = FileHandleRead (FileHandle, &ByteCount, FileBuffer);
+      if (EFI_ERROR (Status)) {
+        Print (L"sf: Read from file error\n");
+        goto Error_Free_Buffer;
+      } else if (ByteCount != (UINTN) FileSize) {
+        Print (L"sf: Not whole file read. Abort\n");
+        goto Error_Free_Buffer;
+      }
+    }
+  }
+
+  Buffer = (UINT8 *) Address;
+  if (FileFlag) {
+    Buffer = FileBuffer;
+  }
+
+  switch (Flag) {
+  case READ:
+  case READ_FILE:
+    Status = SpiFlashProtocol->Read (Slave, Offset, ByteCount, Buffer);
+    break;
+  case ERASE:
+    Status = SpiFlashProtocol->Erase (Slave, Offset, ByteCount);
+    break;
+  case WRITE:
+  case WRITE_FILE:
+    Status = SpiFlashProtocol->Write (Slave, Offset, ByteCount, Buffer);
+    break;
+  case UPDATE:
+  case UPDATE_FILE:
+    Status = SpiFlashProtocol->Update (Slave, Offset, ByteCount, Buffer);
+    break;
+  }
+
+  SpiMasterProtocol->FreeDevice(Slave);
+
+  if (EFI_ERROR (Status)) {
+    Print (L"sf: Error while performing spi transfer\n");
+    return SHELL_ABORTED;
+  }
+
+  switch (Flag) {
+  case ERASE:
+    Print (L"sf: %d bytes succesfully erased at offset 0x%x\n", ByteCount,
+      Offset);
+    break;
+  case WRITE:
+  case WRITE_FILE:
+    Print (L"sf: Write %d bytes at offset 0x%x\n", ByteCount, Offset);
+    break;
+  case UPDATE:
+  case UPDATE_FILE:
+    Print (L"sf: Update %d bytes at offset 0x%x\n", ByteCount, Offset);
+    break;
+  case READ:
+    Print (L"sf: Read %d bytes from offset 0x%x\n", ByteCount, Offset);
+    break;
+  case READ_FILE:
+    Status = FileHandleWrite (FileHandle, &ByteCount, FileBuffer);
+    if (EFI_ERROR(Status)) {
+      Print (L"sf: Error while writing into file\n");
+      goto Error_Free_Buffer;
+    }
+    break;
+  }
+
+  if (FileFlag) {
+    FreePool (FileBuffer);
+
+    if (FileHandle != NULL) {
+      ShellCloseFile (&FileHandle);
+    }
+  }
+
+  return EFI_SUCCESS;
+
+Error_Free_Buffer:
+  FreePool (FileBuffer);
+Error_Close_File:
+  ShellCloseFile (&FileHandle);
+  return SHELL_ABORTED;
+}
+
+EFI_STATUS
+EFIAPI
+ShellSpiFlashLibConstructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  gShellSfHiiHandle = NULL;
+
+  gShellSfHiiHandle = HiiAddPackages (
+                        &gShellSfHiiGuid, gImageHandle,
+                        UefiShellSpiFlashLibStrings, NULL
+                        );
+  if (gShellSfHiiHandle == NULL) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  ShellCommandRegisterCommandName (
+     L"sf", ShellCommandRunSpiFlash, ShellCommandGetManFileNameSpiFlash, 0,
+     L"sf", TRUE , gShellSfHiiHandle, STRING_TOKEN (STR_GET_HELP_SF)
+     );
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+ShellSpiFlashLibDestructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+
+  if (gShellSfHiiHandle != NULL) {
+    HiiRemovePackages (gShellSfHiiHandle);
+  }
+  return EFI_SUCCESS;
+}
diff --git a/Applications/SpiTool/SpiFlashCmd.inf b/Applications/SpiTool/SpiFlashCmd.inf
new file mode 100644
index 0000000..d91fdf3
--- /dev/null
+++ b/Applications/SpiTool/SpiFlashCmd.inf
@@ -0,0 +1,75 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+ INF_VERSION = 0x00010006
+ BASE_NAME = UefiShellSpiFlashLib
+ FILE_GUID = 2f2dd8c9-221f-4acf-afe5-5897264c5774
+ MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 0.1
+ LIBRARY_CLASS = NULL|UEFI_APPLICATION UEFI_DRIVER
+ CONSTRUCTOR = ShellSpiFlashLibConstructor
+ DESTRUCTOR = ShellSpiFlashLibDestructor
+
+[Sources]
+ SpiFlashCmd.c
+ SpiFlashCmd.uni
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ShellPkg/ShellPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+ UefiLib
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ ShellCommandLib
+ ShellLib
+ UefiLib
+ UefiRuntimeServicesTableLib
+ PcdLib
+ HiiLib
+ FileHandleLib
+
+[Pcd]
+ gMarvellTokenSpaceGuid.PcdSpiFlashId
+
+[Protocols]
+ gMarvellSpiFlashProtocolGuid
+ gMarvellSpiMasterProtocolGuid
+
+[Guids]
+ gShellSfHiiGuid
diff --git a/Applications/SpiTool/SpiFlashCmd.uni b/Applications/SpiTool/SpiFlashCmd.uni
new file mode 100644
index 0000000..3f25663
--- /dev/null
+++ b/Applications/SpiTool/SpiFlashCmd.uni
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.inf b/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.inf
new file mode 100755
index 0000000..d798c57
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.inf
@@ -0,0 +1,48 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Hi1610SerdesLib
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SerdesLib
+
+[Binaries.common]
+  LIB|Hi1610SerdesLib.lib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  BaseLib
+  BaseMemoryLib
+  TimerLib
+
+  OemMiscLib
+
+[BuildOptions]
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag
+
+[Pcd]
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.lib
new file mode 100644
index 0000000..c55d678
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.lib
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
new file mode 100755
index 0000000..219cb47
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
@@ -0,0 +1,54 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IpmiCmdLib
+  FILE_GUID                      = E06060B9-1688-41d9-BC12-72567A4D3400
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = IpmiCmdLib
+
+[Sources]
+
+[Binaries.AARCH64]
+  LIB|IpmiCmdLib.lib|*
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  DebugLib
+  ArmLib
+  BaseMemoryLib
+[Ppis]
+
+
+[Guids]
+
+[Protocols]
+  gIpmiInterfaceProtocolGuid
+  gHisiBoardNicProtocolGuid
+  gBmcInfoProtocolGuid
+
+[FixedPcd]
+
+
+
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib
new file mode 100644
index 0000000..1b02db1
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.lib
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf b/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
new file mode 100644
index 0000000..2aafac7
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = LpcLib
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = LpcLib
+
+[Sources.common]
+
+[Binaries.AARCH64]
+  LIB|LpcLib.lib|*
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  BaseLib
+  ArmLib
+  TimerLib
+
+  PlatformSysCtrlLib
+
+[BuildOptions]
+
+[Pcd]
+
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.lib
new file mode 100644
index 0000000..f74d98d
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.lib
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf
new file mode 100755
index 0000000..0ad3cd4
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf
@@ -0,0 +1,55 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformSysCtrlLibHi1610
+  FILE_GUID                      = EBF63479-8F72-4ada-8B2A-960322F7F61A
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PlatformSysCtrlLib
+
+[Sources.common]
+
+
+[Sources.AARCH64]
+
+[Binaries.AARCH64]
+ LIB|PlatformSysCtrlLibHi1610.lib|*
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  OemAddressMapLib
+  OemMiscLib
+  IoLib
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress
+
+[BuildOptions]
+
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib
new file mode 100644
index 0000000..ca78ae6
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf b/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf
new file mode 100755
index 0000000..8c4b3b2
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf
@@ -0,0 +1,49 @@
+#/** @file
+#
+#  Component discription file for NorFlashDxe module
+#
+#  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = LpcSerialPortLib
+  FILE_GUID                      = 09F5FBB9-2AF2-41db-8387-1050300EB762
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SerialPortLib
+
+
+[Sources.common]
+
+[Binaries.AARCH64]
+  LIB|LpcSerialPortLib.lib|*
+
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  LpcLib
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay
+  gHisiTokenSpaceGuid.PcdUartClkInHz
+
diff --git a/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.lib b/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.lib
new file mode 100644
index 0000000..6f88fc1
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.lib
diff --git a/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf b/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
new file mode 100644
index 0000000..1fee6ea
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
@@ -0,0 +1,48 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = Hi1616SerdesLib
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SerdesLib
+
+[Binaries.common]
+  LIB|Hi1616SerdesLib.lib
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  TimerLib
+  IoLib
+
+  OemMiscLib
+
+[BuildOptions]
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag
+
+[Pcd]
diff --git a/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.lib b/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.lib
new file mode 100644
index 0000000..82abd5f
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.lib
diff --git a/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf b/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
new file mode 100644
index 0000000..50c63a1
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
@@ -0,0 +1,54 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = PlatformSysCtrlLibHi1616
+  FILE_GUID                      = EBF63479-8F72-4ada-8B2A-960322F7F61A
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PlatformSysCtrlLib
+
+[Sources.common]
+
+
+[Sources.AARCH64]
+
+[Binaries.AARCH64]
+ LIB|PlatformSysCtrlLibHi1616.lib|*
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  IoLib
+  OemAddressMapLib
+  OemMiscLib
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress
+
+[BuildOptions]
+
diff --git a/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib b/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib
new file mode 100644
index 0000000..a4fe13a
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib
diff --git a/Chips/TexasInstruments/Omap35xx/License.txt b/Chips/Hisilicon/Binary/License.txt
index 05dbd36..cd6fd02 100755..100644
--- a/Chips/TexasInstruments/Omap35xx/License.txt
+++ b/Chips/Hisilicon/Binary/License.txt
@@ -1,16 +1,15 @@
-Copyright (c) 2009-2010, Apple Inc. All rights reserved.
-Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+Copyright (c) 2016, Hisilicon Limited. All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
-* Redistributions of source code must retain the above copyright
-  notice, this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright
-  notice, this list of conditions and the following disclaimer in
-  the documentation and/or other materials provided with the
-  distribution.
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in
+   the documentation and/or other materials provided with the
+   distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
diff --git a/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf b/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf
new file mode 100644
index 0000000..7a41ed8
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf
@@ -0,0 +1,54 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformSysCtrlLibPv660
+  FILE_GUID                      = EBF63479-8F72-4ada-8B2A-960322F7F61A
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PlatformSysCtrlLib
+
+[Sources.common]
+
+
+[Sources.AARCH64]
+
+[Binaries.AARCH64]
+ LIB|PlatformSysCtrlLibPv660.lib|*
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  OemAddressMapLib
+  OemMiscLib
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress
+
+[BuildOptions]
+
diff --git a/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.lib b/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.lib
new file mode 100644
index 0000000..37082f9
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.lib
diff --git a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf
new file mode 100644
index 0000000..e7cd204
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf
@@ -0,0 +1,48 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Pv660SerdesLib
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SerdesLib
+
+[Binaries.common]
+  LIB|Pv660SerdesLib.lib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  BaseLib
+  BaseMemoryLib
+
+
+  OemMiscLib
+
+[BuildOptions]
+
+[FixedPcd]
+
+
+
diff --git a/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib
new file mode 100644
index 0000000..5f8ab73
--- /dev/null
+++ b/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.lib
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 0000000..3d5ae91
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,40 @@
+/** @file
+
+  Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <PiDxe.h>
+#include <Guid/EventGroup.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/AcpiAml.h>
+#include "EthMac.h"
+
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  return EthMacInit();
+}
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
new file mode 100644
index 0000000..812a214
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -0,0 +1,72 @@
+## @file
+#
+#  Copyright (c) 2014, Applied Micro Curcuit Corp. All rights reserved.<BR>
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AcpiPlatform
+  FILE_GUID                      = e0829681-e9fa-4117-a8d7-84efadff863d
+  MODULE_TYPE                    = DXE_DRIVER
+  #MODULE_TYPE                    = UEFI_APPLICATION
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = AcpiPlatformEntryPoint
+
+[Sources]
+  AcpiPlatform.c
+  EthMac.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  ShellPkg/ShellPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiLib
+  PcdLib
+  BaseMemoryLib
+  DebugLib
+  MemoryAllocationLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  #UefiApplicationEntryPoint
+
+[Guids]
+  gShellVariableGuid                            # ALWAYS_CONSUMED
+  gArmMpCoreInfoGuid
+
+[Protocols]
+  gEfiAcpiTableProtocolGuid                     # PROTOCOL ALWAYS_CONSUMED
+  gEfiAcpiSdtProtocolGuid                       # PROTOCOL ALWAYS_CONSUMED
+  gHisiBoardNicProtocolGuid                           # PROTOCOL ALWAYS_CONSUMED
+
+[FeaturePcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol
+
+[Pcd]
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+
+[Depex]
+  gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gHisiBoardNicProtocolGuid
+
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c
new file mode 100644
index 0000000..41f5692
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c
@@ -0,0 +1,484 @@
+/** @file
+
+  Copyright (c) 2014, Applied Micro Curcuit Corporation. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  This driver is called to initialize the FW part of the PHY in preparation
+  for the OS.
+
+**/
+
+#include <Guid/ShellVariableGuid.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+
+#include <PiDxe.h>
+#include <Guid/EventGroup.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/AcpiAml.h>
+
+#include <Protocol/HisiBoardNicProtocol.h>
+
+// Turn on debug message by enabling below define
+//#define ACPI_DEBUG
+
+#ifdef ACPI_DEBUG
+#define DBG(arg...) DEBUG((EFI_D_ERROR,## arg))
+#else
+#define DBG(arg...)
+#endif
+
+#define EFI_ACPI_MAX_NUM_TABLES         20
+#define DSDT_SIGNATURE                  0x54445344
+
+#define D02_ACPI_ETH_ID                     "HISI00C1"
+#define D03_ACPI_ETH_ID                     "HISI00C2"
+
+#define ACPI_ETH_MAC_KEY                "local-mac-address"
+
+#define PREFIX_VARIABLE_NAME            L"MAC"
+#define PREFIX_VARIABLE_NAME_COMPAT     L"RGMII_MAC"
+#define MAC_MAX_LEN                     30
+
+EFI_STATUS GetEnvMac(
+  IN          UINTN    MacNextID,
+  IN OUT      UINT8    *MacBuffer)
+{
+  EFI_MAC_ADDRESS Mac;
+  EFI_STATUS Status;
+  HISI_BOARD_NIC_PROTOCOL *OemNic = NULL;
+
+  Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic);
+  if(EFI_ERROR(Status))
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __FUNCTION__, __LINE__, Status));
+    return Status;
+  }
+
+  Status = OemNic->GetMac(&Mac, MacNextID);
+  if(EFI_ERROR(Status))
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] GetMac failed %r\n", __FUNCTION__, __LINE__, Status));
+    return Status;
+  }
+
+  CopyMem (MacBuffer, &Mac, 6);
+  DEBUG((EFI_D_ERROR, "Port %d MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
+        MacNextID,
+        MacBuffer[0],
+        MacBuffer[1],
+        MacBuffer[2],
+        MacBuffer[3],
+        MacBuffer[4],
+        MacBuffer[5]
+        ));
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS _SearchReplacePackageMACAddress(
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiTableProtocol,
+  IN EFI_ACPI_HANDLE        ChildHandle,
+  IN UINTN                  Level,
+  IN OUT BOOLEAN            *Found,
+  IN UINTN                  MacNextID)
+{
+  // ASL template for ethernet driver:
+/*
+ *   Name (_DSD, Package () {
+ *   ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ *   Package () {
+ *     Package (2) {"mac-address", Package (6) { 00, 11, 22, 33, 44, 55 }}
+ *     Package (2) {"phy-channel", 0},
+ *     Package (2) {"phy-mode", "rgmii"},
+ *     Package (2) {"max-transfer-unit", 0x5dc},   // MTU of 1500
+ *     Package (2) {"max-speed", 0x3e8},            // 1000 Mbps
+ *   }
+ * })
+ */
+  EFI_STATUS          Status;
+  EFI_ACPI_DATA_TYPE  DataType;
+  CONST UINT8         *Data;
+  CONST VOID          *Buffer;
+  UINTN               DataSize;
+  UINTN               Count;
+  EFI_ACPI_HANDLE     CurrentHandle;
+  EFI_ACPI_HANDLE     NextHandle;
+  UINT8               MACBuffer[MAC_MAX_LEN];
+
+  DBG("In Level:%d\n", Level);
+  Status = EFI_SUCCESS;
+  for (CurrentHandle = NULL; ;) {
+    Status = AcpiTableProtocol->GetChild(ChildHandle, &CurrentHandle);
+    if (Level != 3 && (EFI_ERROR(Status) || CurrentHandle == NULL))
+       break;
+
+    Status = AcpiTableProtocol->GetOption(CurrentHandle, 0, &DataType, &Buffer, &DataSize);
+    Data = Buffer;
+    DBG("_DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n",
+        DataSize, Data[0], DataSize > 1 ? Data[1] : 0);
+
+    if (Level < 2 && Data[0] != AML_PACKAGE_OP)
+      continue;
+
+    if (Level == 2 && Data[0] == AML_STRING_PREFIX) {
+      Status = AcpiTableProtocol->GetOption(CurrentHandle, 1, &DataType, &Buffer, &DataSize);
+      if (EFI_ERROR(Status))
+        break;
+
+      DBG("  _DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X\n",
+              DataSize, Data[0], DataSize > 1 ? Data[1] : 0);
+
+      Data = Buffer;
+      if (DataType != EFI_ACPI_DATA_TYPE_STRING
+              || AsciiStrCmp((CHAR8 *) Data, ACPI_ETH_MAC_KEY) != 0)
+        continue;
+
+      DBG("_DSD Key Type %d. Found MAC address key\n", DataType);
+
+      //
+      // We found the node.
+      //
+      *Found = TRUE;
+      continue;
+    }
+
+    if (Level == 3 && *Found) {
+
+      //Update the MAC
+      Status = GetEnvMac(MacNextID, MACBuffer);
+      if (EFI_ERROR(Status))
+        break;
+
+      for (Count = 0; Count < 6; Count++) {
+        Status = AcpiTableProtocol->GetOption(CurrentHandle, 1, &DataType, &Buffer, &DataSize);
+        if (EFI_ERROR(Status))
+          break;
+
+        Data = Buffer;
+        DBG("    _DSD Child Subnode Store Op Code 0x%02X 0x%02X %02X DataType 0x%X\n",
+            DataSize, Data[0], DataSize > 1 ? Data[1] : 0, DataType);
+
+        if (DataType != EFI_ACPI_DATA_TYPE_UINT)
+          break;
+
+        // only need one byte.
+        // FIXME: Assume the CPU is little endian
+        Status = AcpiTableProtocol->SetOption(CurrentHandle, 1, (VOID *)&MACBuffer[Count], sizeof(UINT8));
+        if (EFI_ERROR(Status))
+          break;
+        Status = AcpiTableProtocol->GetChild(ChildHandle, &CurrentHandle);
+        if (EFI_ERROR(Status) || CurrentHandle == NULL)
+          break;
+      }
+      break;
+    }
+
+    if (Level > 3)
+      break;
+
+    //Search next package
+    AcpiTableProtocol->Open((VOID *) Buffer, &NextHandle);
+    Status = _SearchReplacePackageMACAddress(AcpiTableProtocol, NextHandle, Level + 1, Found, MacNextID);
+    AcpiTableProtocol->Close(NextHandle);
+    if (!EFI_ERROR(Status))
+      break;
+  }
+
+  return Status;
+}
+
+EFI_STATUS SearchReplacePackageMACAddress(
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiTableProtocol,
+  IN EFI_ACPI_HANDLE        ChildHandle,
+  IN UINTN                  MacNextID)
+{
+  BOOLEAN Found = FALSE;
+  UINTN Level = 0;
+
+  return _SearchReplacePackageMACAddress(AcpiTableProtocol, ChildHandle, Level, &Found, MacNextID);
+}
+
+EFI_STATUS
+GetEthID (
+  EFI_ACPI_SDT_PROTOCOL   *AcpiTableProtocol,
+  EFI_ACPI_HANDLE         ChildHandle,
+  UINTN                   *EthID
+  )
+{
+  EFI_STATUS Status;
+  EFI_ACPI_DATA_TYPE  DataType;
+  CHAR8               Data[5];
+  CONST VOID          *Buffer;
+  UINTN               DataSize;
+
+  // Get NameString ETHx
+  Status = AcpiTableProtocol->GetOption (ChildHandle, 1, &DataType, &Buffer, &DataSize);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "[%a:%d] Get NameString failed: %r\n", __FUNCTION__, __LINE__, Status));
+    return Status;
+  }
+
+  CopyMem (Data, Buffer, 4);
+  DBG("Size %p Data %02x %02x %02x %02x\n", DataSize, Data[0], Data[1], Data[2], Data[3]);
+
+  Data[4] = '\0';
+  if (DataSize != 4 ||
+      AsciiStrnCmp ("ETH", Data, 3) != 0 ||
+      Data[3] > '9' || Data[3] < '0') {
+    DEBUG ((EFI_D_ERROR, "[%a:%d] The NameString %a is not ETHn\n", __FUNCTION__, __LINE__, Data));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  *EthID = Data[3] - '0';
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS ProcessDSDTDevice (
+  EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+  EFI_ACPI_HANDLE ChildHandle)
+{
+  EFI_STATUS          Status;
+  EFI_ACPI_DATA_TYPE  DataType;
+  CONST UINT8         *Data;
+  CONST VOID          *Buffer;
+  UINTN               DataSize;
+  EFI_ACPI_HANDLE     DevHandle;
+  INTN                Found = 0;
+  UINTN               MacNextID;
+
+  Status = AcpiTableProtocol->GetOption(ChildHandle, 0, &DataType, &Buffer, &DataSize);
+  if (EFI_ERROR(Status))
+    return EFI_SUCCESS;
+
+  Data = Buffer;
+  //
+  // Skip all non-device type
+  //
+  if (DataSize != 2 || Data[0] != AML_EXT_OP || Data[1] != AML_EXT_DEVICE_OP)
+    return EFI_SUCCESS;
+
+  //
+  // Walk the device type node
+  //
+  for (DevHandle = NULL; ; ) {
+    Status = AcpiTableProtocol->GetChild(ChildHandle, &DevHandle);
+    if (EFI_ERROR(Status) || DevHandle == NULL)
+      break;
+
+    //
+    // Search for _HID with Ethernet ID
+    //
+    Status = AcpiTableProtocol->GetOption(DevHandle, 0, &DataType, &Buffer, &DataSize);
+    if (EFI_ERROR(Status))
+      break;
+
+    Data = Buffer;
+    DBG("Data Type 0x%02X %02X\n", Data[0], DataSize > 1 ? Data[1] : 0);
+    if (DataSize == 1 && Data[0] == AML_NAME_OP) {
+      Status = AcpiTableProtocol->GetOption(DevHandle, 1, &DataType, &Buffer, &DataSize);
+      if (EFI_ERROR(Status))
+        break;
+
+      Data = Buffer;
+      if (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING) {
+        if (AsciiStrnCmp((CHAR8 *) Data, "_HID", 4) == 0) {
+          EFI_ACPI_HANDLE ValueHandle;
+
+          Status = AcpiTableProtocol->GetOption(DevHandle, 2, &DataType, &Buffer, &DataSize);
+          if (EFI_ERROR(Status))
+            break;
+
+          if (DataType != EFI_ACPI_DATA_TYPE_CHILD)
+            continue;
+
+          AcpiTableProtocol->Open((VOID *) Buffer, &ValueHandle);
+          Status = AcpiTableProtocol->GetOption(ValueHandle, 1, &DataType, &Buffer, &DataSize);
+
+          Data = Buffer;
+          DBG("[%a:%d] - _HID = %a\n", __FUNCTION__, __LINE__, Data);
+
+          if (EFI_ERROR(Status) ||
+              DataType != EFI_ACPI_DATA_TYPE_STRING ||
+              ((AsciiStrCmp((CHAR8 *) Data, D02_ACPI_ETH_ID) != 0) &&
+              (AsciiStrCmp((CHAR8 *) Data, D03_ACPI_ETH_ID) != 0))) {
+            AcpiTableProtocol->Close(ValueHandle);
+            Found = 0;
+            continue;
+          }
+
+          DBG("Found Ethernet device\n");
+          AcpiTableProtocol->Close(ValueHandle);
+          Status = GetEthID (AcpiTableProtocol, ChildHandle, &MacNextID);
+          if (EFI_ERROR (Status)) {
+            continue;
+          }
+          Found = 1;
+        } else if (Found == 1 && AsciiStrnCmp((CHAR8 *) Data, "_DSD", 4) == 0) {
+          //
+          // Patch MAC address for open source kernel
+          //
+          EFI_ACPI_HANDLE    PkgHandle;
+          Status = AcpiTableProtocol->GetOption(DevHandle, 2, &DataType, &Buffer, &DataSize);
+          if (EFI_ERROR(Status))
+            break;
+
+          if (DataType != EFI_ACPI_DATA_TYPE_CHILD)
+            continue;
+
+          //
+          // Open package data
+          //
+          AcpiTableProtocol->Open((VOID *) Buffer, &PkgHandle);
+          Status = AcpiTableProtocol->GetOption(PkgHandle, 0, &DataType, &Buffer, &DataSize);
+
+          Data = Buffer;
+          DBG("_DSD Subnode Store Op Code 0x%02X %02X\n",
+                Data[0], DataSize > 1 ? Data[1] : 0);
+
+          //
+          // Walk the _DSD node
+          //
+          if (DataSize == 1 && Data[0] == AML_PACKAGE_OP)
+            Status = SearchReplacePackageMACAddress(AcpiTableProtocol, PkgHandle, MacNextID);
+
+          AcpiTableProtocol->Close(PkgHandle);
+        }
+      }
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+BOOLEAN
+IsSbScope (
+  EFI_ACPI_SDT_PROTOCOL   *AcpiTableProtocol,
+  EFI_ACPI_HANDLE         ChildHandle
+  )
+{
+  EFI_STATUS          Status;
+  EFI_ACPI_DATA_TYPE  DataType;
+  CONST UINT8         *Data;
+  CONST VOID          *Buffer;
+  UINTN               DataSize;
+
+  Status = AcpiTableProtocol->GetOption (ChildHandle, 0, &DataType, &Buffer, &DataSize);
+  if (EFI_ERROR(Status)) return FALSE;
+
+  Data = Buffer;
+  if (DataSize != 1 || Data[0] != AML_SCOPE_OP) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+EFI_STATUS ProcessDSDTChild(
+  EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+  EFI_ACPI_HANDLE ChildHandle)
+{
+  EFI_STATUS          Status;
+  EFI_ACPI_HANDLE     DevHandle;
+
+  // Check Scope(_SB) at first
+  if (!IsSbScope (AcpiTableProtocol, ChildHandle)) {
+    return ProcessDSDTDevice (AcpiTableProtocol, ChildHandle);
+  }
+
+  for (DevHandle = NULL; ; ) {
+    Status = AcpiTableProtocol->GetChild (ChildHandle, &DevHandle);
+    if (EFI_ERROR(Status) || DevHandle == NULL) {
+      break;
+    }
+
+    ProcessDSDTDevice (AcpiTableProtocol, DevHandle);
+  }
+
+  return EFI_SUCCESS;
+}
+
+static EFI_STATUS ProcessDSDT(
+  EFI_ACPI_SDT_PROTOCOL *AcpiTableProtocol,
+  EFI_ACPI_HANDLE TableHandle)
+{
+  EFI_STATUS              Status;
+  EFI_ACPI_HANDLE         ChildHandle;
+  //
+  // Parse table for device type
+  DBG ("[%a:%d] - TableHandle=%p\n", __FUNCTION__, __LINE__, TableHandle);
+  for (ChildHandle = NULL; ; ) {
+    Status = AcpiTableProtocol->GetChild(TableHandle, &ChildHandle);
+    DBG ("[%a:%d] - Child=%p, %r\n", __FUNCTION__, __LINE__, ChildHandle, Status);
+    if (EFI_ERROR(Status))
+      break;
+    if (ChildHandle == NULL)
+      break;
+
+    ProcessDSDTChild(AcpiTableProtocol, ChildHandle);
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS EthMacInit(void)
+{
+  EFI_STATUS              Status;
+  EFI_ACPI_SDT_PROTOCOL   *AcpiTableProtocol;
+  EFI_ACPI_SDT_HEADER     *Table;
+  EFI_ACPI_TABLE_VERSION  TableVersion;
+  UINTN                   TableKey;
+  EFI_ACPI_HANDLE         TableHandle;
+  UINTN                   i;
+
+  DEBUG ((EFI_D_ERROR, "Updating Ethernet MAC in ACPI DSDT...\n"));
+
+  //
+  // Find the AcpiTable protocol
+  Status = gBS->LocateProtocol(&gEfiAcpiSdtProtocolGuid, NULL, (VOID**) &AcpiTableProtocol);
+  if (EFI_ERROR(Status)) {
+    DBG("Unable to locate ACPI table protocol\n");
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Search for DSDT Table
+  for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) {
+    Status = AcpiTableProtocol->GetAcpiTable(i, &Table, &TableVersion, &TableKey);
+    if (EFI_ERROR(Status))
+      break;
+    if (Table->Signature != DSDT_SIGNATURE)
+      continue;
+
+    Status = AcpiTableProtocol->OpenSdt(TableKey, &TableHandle);
+    if (EFI_ERROR(Status))
+      break;
+
+    ProcessDSDT(AcpiTableProtocol, TableHandle);
+
+    AcpiTableProtocol->Close(TableHandle);
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.h b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.h
new file mode 100644
index 0000000..bf4cbb1
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.h
@@ -0,0 +1,22 @@
+/*
+ *
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
+ * Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2015, Linaro Limited. All rights reserved.
+ * Author: Loc Ho <lho@apm.com>
+ *
+ * This program and the accompanying materials
+ *are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution.  The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ */
+#ifndef _ETH_MAC_H_
+#define _ETH_MAC_H_
+
+EFI_STATUS EthMacInit(VOID);
+
+#endif
+
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c
new file mode 100644
index 0000000..91c0733
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c
@@ -0,0 +1,109 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "FlashFvbDxe.h"
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoReadBlocks (
+    IN  EFI_BLOCK_IO_PROTOCOL*     This,
+    IN  UINT32                  MediaId,
+    IN  EFI_LBA                     Lba,
+    IN  UINTN         BufferSizeInBytes,
+    OUT VOID*                     Buffer
+)
+{
+    FLASH_INSTANCE*   Instance;
+    EFI_STATUS          Status;
+
+    Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+    DEBUG ((EFI_D_INFO, "FlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+    if ( !This->Media->MediaPresent )
+    {
+        Status = EFI_NO_MEDIA;
+    }
+    else if ( This->Media->MediaId != MediaId )
+    {
+        Status = EFI_MEDIA_CHANGED;
+    }
+    else
+    {
+        Status = FlashReadBlocks (Instance, Lba, BufferSizeInBytes, Buffer);
+    }
+
+    return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoWriteBlocks (
+    IN  EFI_BLOCK_IO_PROTOCOL*     This,
+    IN  UINT32                  MediaId,
+    IN  EFI_LBA                     Lba,
+    IN  UINTN         BufferSizeInBytes,
+    IN  VOID*                     Buffer
+)
+{
+    FLASH_INSTANCE*   Instance;
+    EFI_STATUS          Status;
+
+    Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+    DEBUG ((EFI_D_INFO, "FlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+    if ( !This->Media->MediaPresent )
+    {
+        Status = EFI_NO_MEDIA;
+    }
+    else if ( This->Media->MediaId != MediaId )
+    {
+        Status = EFI_MEDIA_CHANGED;
+    }
+    else if ( This->Media->ReadOnly )
+    {
+        Status = EFI_WRITE_PROTECTED;
+    }
+    else
+    {
+        Status = FlashWriteBlocks (Instance, Lba, BufferSizeInBytes, Buffer);
+    }
+
+    return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoFlushBlocks (
+    IN EFI_BLOCK_IO_PROTOCOL*  This
+)
+{
+    // No Flush required for the NOR Flash driver
+    // because cache operations are not permitted.
+
+    // Nothing to do so just return without error
+    return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
new file mode 100644
index 0000000..544228a
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
@@ -0,0 +1,1230 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on files under ArmPlatformPkg/Drivers/NorFlashDxe/
+**/
+
+#include "FlashFvbDxe.h"
+STATIC EFI_EVENT mFlashFvbVirtualAddrChangeEvent;
+STATIC UINTN     mFlashNvStorageVariableBase;
+
+
+//
+// Global variable declarations
+//
+
+FLASH_DESCRIPTION mFlashDevices[FLASH_DEVICE_COUNT] =
+{
+    {
+        // UEFI Variable Services non-volatile storage
+        0xa4000000,
+        FixedPcdGet32(PcdFlashNvStorageVariableBase),
+        0x20000,
+        SIZE_64KB,
+        {0xCC2CBF29, 0x1498, 0x4CDD, {0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x09, 0x09}}
+    }
+
+};
+
+FLASH_INSTANCE** mFlashInstances;
+
+FLASH_INSTANCE  mFlashInstanceTemplate =
+{
+    FLASH_SIGNATURE, // Signature
+    NULL, // Handle ... NEED TO BE FILLED
+
+    FALSE, // Initialized
+    NULL, // Initialize
+
+    0, // DeviceBaseAddress ... NEED TO BE FILLED
+    0, // RegionBaseAddress ... NEED TO BE FILLED
+    0, // Size ... NEED TO BE FILLED
+    0, // StartLba
+
+    {
+        EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision
+        NULL, // Media ... NEED TO BE FILLED
+        NULL, //NorFlashBlockIoReset
+        FlashBlockIoReadBlocks,
+        FlashBlockIoWriteBlocks,
+        FlashBlockIoFlushBlocks
+    }, // BlockIoProtocol
+
+    {
+        0, // MediaId ... NEED TO BE FILLED
+        FALSE, // RemovableMedia
+        TRUE, // MediaPresent
+        FALSE, // LogicalPartition
+        FALSE, // ReadOnly
+        FALSE, // WriteCaching;
+        SIZE_64KB, // BlockSize ... NEED TO BE FILLED
+        4, //  IoAlign
+        0, // LastBlock ... NEED TO BE FILLED
+        0, // LowestAlignedLba
+        1, // LogicalBlocksPerPhysicalBlock
+    }, //Media;
+
+    FALSE, // SupportFvb ... NEED TO BE FILLED
+    {
+        FvbGetAttributes,
+        FvbSetAttributes,
+        FvbGetPhysicalAddress,
+        FvbGetBlockSize,
+        FvbRead,
+        FvbWrite,
+        FvbEraseBlocks,
+        NULL, //ParentHandle
+    }, //  FvbProtoccol;
+
+    {
+        {
+            {
+                HARDWARE_DEVICE_PATH,
+                HW_VENDOR_DP,
+                {(UINT8)(sizeof(VENDOR_DEVICE_PATH)),
+                (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)},
+            },
+            { 0x0, 0x0, 0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }}, // GUID ... NEED TO BE FILLED
+        },
+        {
+            END_DEVICE_PATH_TYPE,
+            END_ENTIRE_DEVICE_PATH_SUBTYPE,
+            {sizeof (EFI_DEVICE_PATH_PROTOCOL),
+            0}
+        }
+    } // DevicePath
+};
+
+HISI_SPI_FLASH_PROTOCOL* mFlash;
+
+///
+/// The Firmware Volume Block Protocol is the low-level interface
+/// to a firmware volume. File-level access to a firmware volume
+/// should not be done using the Firmware Volume Block Protocol.
+/// Normal access to a firmware volume must use the Firmware
+/// Volume Protocol. Typically, only the file system driver that
+/// produces the Firmware Volume Protocol will bind to the
+/// Firmware Volume Block Protocol.
+///
+
+/**
+  Initialises the FV Header and Variable Store Header
+  to support variable operations.
+
+  @param[in]  Ptr - Location to initialise the headers
+
+**/
+EFI_STATUS
+InitializeFvAndVariableStoreHeaders (
+    IN FLASH_INSTANCE* Instance
+)
+{
+    EFI_STATUS                          Status;
+    VOID*                               Headers;
+    UINTN                               HeadersLength;
+    EFI_FIRMWARE_VOLUME_HEADER*          FirmwareVolumeHeader;
+    VARIABLE_STORE_HEADER*               VariableStoreHeader;
+
+    if (!Instance->Initialized && Instance->Initialize)
+    {
+        Instance->Initialize (Instance);
+    }
+
+    HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER);
+    Headers = AllocateZeroPool(HeadersLength);
+
+    // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
+    ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet32(PcdFlashNvStorageFtwWorkingBase));
+    ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet32(PcdFlashNvStorageFtwSpareBase));
+
+    // Check if the size of the area is at least one block size
+    ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0));
+    ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0));
+    ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0));
+
+    // Ensure the Variable area Base Addresses are aligned on a block size boundaries
+    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Media.BlockSize == 0);
+    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->Media.BlockSize == 0);
+    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Media.BlockSize == 0);
+
+    //
+    // EFI_FIRMWARE_VOLUME_HEADER
+    //
+    FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
+    CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
+    FirmwareVolumeHeader->FvLength =
+        PcdGet32(PcdFlashNvStorageVariableSize) +
+        PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
+        PcdGet32(PcdFlashNvStorageFtwSpareSize);
+    FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
+    FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) (
+                                           EFI_FVB2_READ_ENABLED_CAP   | // Reads may be enabled
+                                           EFI_FVB2_READ_STATUS        | // Reads are currently enabled
+                                           EFI_FVB2_STICKY_WRITE       | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+                                           EFI_FVB2_MEMORY_MAPPED      | // It is memory mapped
+                                           EFI_FVB2_ERASE_POLARITY     | // After erasure all bits take this value (i.e. '1')
+                                           EFI_FVB2_WRITE_STATUS       | // Writes are currently enabled
+                                           EFI_FVB2_WRITE_ENABLED_CAP    // Writes may be enabled
+                                       );
+    FirmwareVolumeHeader->HeaderLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY);
+    FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
+    FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
+    FirmwareVolumeHeader->BlockMap[0].Length      = Instance->Media.BlockSize;
+    FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
+    FirmwareVolumeHeader->BlockMap[1].Length      = 0;
+    FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16*)FirmwareVolumeHeader, FirmwareVolumeHeader->HeaderLength);
+
+    //
+    // VARIABLE_STORE_HEADER
+    //
+    VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)Headers + (UINTN)FirmwareVolumeHeader->HeaderLength);
+    CopyGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid);
+    VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
+    VariableStoreHeader->Format            = VARIABLE_STORE_FORMATTED;
+    VariableStoreHeader->State             = VARIABLE_STORE_HEALTHY;
+
+    // Install the combined super-header in the NorFlash
+    Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
+
+    FreePool (Headers);
+    return Status;
+}
+
+/**
+  Check the integrity of firmware volume header.
+
+  @param[in] FwVolHeader - A pointer to a firmware volume header
+
+  @retval  EFI_SUCCESS   - The firmware volume is consistent
+  @retval  EFI_NOT_FOUND - The firmware volume has been corrupted.
+
+**/
+EFI_STATUS
+ValidateFvHeader (
+    IN  FLASH_INSTANCE* Instance
+)
+{
+    UINT16                      Checksum;
+    EFI_FIRMWARE_VOLUME_HEADER* FwVolHeader;
+    VARIABLE_STORE_HEADER*      VariableStoreHeader;
+    UINTN                       VariableStoreLength;
+    UINTN                       FvLength;
+
+    FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress;
+
+    FvLength = PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
+               PcdGet32(PcdFlashNvStorageFtwSpareSize);
+
+    //
+    // Verify the header revision, header signature, length
+    // Length of FvBlock cannot be 2**64-1
+    // HeaderLength cannot be an odd number
+    //
+    if (   (FwVolHeader->Revision  != EFI_FVH_REVISION)
+           || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
+           || (FwVolHeader->FvLength  != FvLength)
+       )
+    {
+        DEBUG ((EFI_D_ERROR, "ValidateFvHeader: No Firmware Volume header present\n"));
+        return EFI_NOT_FOUND;
+    }
+
+    // Check the Firmware Volume Guid
+    if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE )
+    {
+        DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Firmware Volume Guid non-compatible\n"));
+        return EFI_NOT_FOUND;
+    }
+
+    // Verify the header checksum
+    Checksum = CalculateSum16((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
+    if (Checksum != 0)
+    {
+        DEBUG ((EFI_D_ERROR, "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n", Checksum));
+        return EFI_NOT_FOUND;
+    }
+
+    VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + (UINTN)FwVolHeader->HeaderLength);
+
+    // Check the Variable Store Guid
+    if ( CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) == FALSE )
+    {
+        DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Variable Store Guid non-compatible\n"));
+        return EFI_NOT_FOUND;
+    }
+
+    VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
+    if (VariableStoreHeader->Size != VariableStoreLength)
+    {
+        DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Variable Store Length does not match\n"));
+        return EFI_NOT_FOUND;
+    }
+
+    return EFI_SUCCESS;
+}
+
+/**
+ The FvbGetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This         Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes   Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
+                     current settings are returned.
+                     Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*    This,
+    OUT       EFI_FVB_ATTRIBUTES_2*                   Attributes
+)
+{
+    EFI_FVB_ATTRIBUTES_2  FlashFvbAttributes;
+    FLASH_INSTANCE*                 Instance;
+
+    Instance = INSTANCE_FROM_FVB_THIS(This);
+
+    FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) (
+
+                             EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+                             EFI_FVB2_READ_STATUS      | // Reads are currently enabled
+                             EFI_FVB2_STICKY_WRITE     | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+                             EFI_FVB2_MEMORY_MAPPED    | // It is memory mapped
+                             EFI_FVB2_ERASE_POLARITY     // After erasure all bits take this value (i.e. '1')
+
+                         );
+
+    // Check if it is write protected
+    if (Instance->Media.ReadOnly != TRUE)
+    {
+
+        FlashFvbAttributes = FlashFvbAttributes         |
+                             EFI_FVB2_WRITE_STATUS      | // Writes are currently enabled
+                             EFI_FVB2_WRITE_ENABLED_CAP;  // Writes may be enabled
+    }
+
+    *Attributes = FlashFvbAttributes;
+
+    return EFI_SUCCESS;
+}
+
+/**
+ The FvbSetAttributes() function sets configurable firmware volume attributes
+ and returns the new settings of the firmware volume.
+
+
+ @param This                     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes               On input, Attributes is a pointer to EFI_FVB_ATTRIBUTES_2
+                                 that contains the desired firmware volume settings.
+                                 On successful return, it contains the new settings of
+                                 the firmware volume.
+                                 Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS             The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER   The attributes requested are in conflict with the capabilities
+                                 as declared in the firmware volume header.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*  This,
+    IN OUT    EFI_FVB_ATTRIBUTES_2*                 Attributes
+)
+{
+    DEBUG ((EFI_D_ERROR, "FvbSetAttributes(0x%X) is not supported\n", *Attributes));
+    return EFI_UNSUPPORTED;
+}
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This               Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address            Pointer to a caller-allocated
+                           EFI_PHYSICAL_ADDRESS that, on successful
+                           return from GetPhysicalAddress(), contains the
+                           base address of the firmware volume.
+
+ @retval EFI_SUCCESS       The firmware volume base address was returned.
+
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress (
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*  This,
+    OUT       EFI_PHYSICAL_ADDRESS*                 Address
+)
+{
+
+    if(NULL == Address)
+    {
+        return EFI_UNSUPPORTED;
+    };
+
+    *Address = mFlashNvStorageVariableBase;
+    return EFI_SUCCESS;
+}
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+ @param This                     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba                      Indicates the block for which to return the size.
+
+ @param BlockSize                Pointer to a caller-allocated UINTN in which
+                                 the size of the block is returned.
+
+ @param NumberOfBlocks           Pointer to a caller-allocated UINTN in
+                                 which the number of consecutive blocks,
+                                 starting with Lba, is returned. All
+                                 blocks in this range have a size of
+                                 BlockSize.
+
+
+ @retval EFI_SUCCESS             The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER   The requested LBA is out of range.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize (
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*  This,
+    IN        EFI_LBA                              Lba,
+    OUT       UINTN*                                BlockSize,
+    OUT       UINTN*                                NumberOfBlocks
+)
+{
+    EFI_STATUS Status;
+    FLASH_INSTANCE* Instance;
+
+    Instance = INSTANCE_FROM_FVB_THIS(This);
+
+    if (Lba > Instance->Media.LastBlock)
+    {
+        Status = EFI_INVALID_PARAMETER;
+    }
+    else
+    {
+        // This is easy because in this platform each NorFlash device has equal sized blocks.
+        *BlockSize = (UINTN) Instance->Media.BlockSize;
+        *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1);
+
+
+        Status = EFI_SUCCESS;
+    }
+
+    return Status;
+}
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This                 Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba                  The starting logical block index from which to read.
+
+ @param Offset               Offset into the block at which to begin reading.
+
+ @param NumBytes             Pointer to a UINTN.
+                             At entry, *NumBytes contains the total size of the buffer.
+                             At exit, *NumBytes contains the total number of bytes read.
+
+ @param Buffer               Pointer to a caller-allocated buffer that will be used
+                             to hold the data that is read.
+
+ @retval EFI_SUCCESS         The firmware volume was read successfully,  and contents are
+                             in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
+                             On output, NumBytes contains the total number of bytes
+                             returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED   The firmware volume is in the ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR    The block device is not functioning correctly and could not be read.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbRead (
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*   This,
+    IN        EFI_LBA                               Lba,
+    IN        UINTN                                 Offset,
+    IN OUT    UINTN*                                 NumBytes,
+    IN OUT    UINT8*                                 Buffer
+)
+{
+    EFI_STATUS                    Status;
+    UINTN                      BlockSize;
+    FLASH_INSTANCE*             Instance;
+
+    UINTN                   StartAddress;
+    UINTN                    ReadAddress;
+
+    Instance = INSTANCE_FROM_FVB_THIS(This);
+
+    if (!Instance->Initialized && Instance->Initialize)
+    {
+        if (EfiAtRuntime ()) {
+            DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Initialize at runtime is not supported!\n", __FUNCTION__, __LINE__));
+            return EFI_UNSUPPORTED;
+        }
+
+        Instance->Initialize(Instance);
+    }
+
+    Status = EFI_SUCCESS;
+
+    // Cache the block size to avoid de-referencing pointers all the time
+    BlockSize = Instance->Media.BlockSize;
+
+    // The read must not span block boundaries.
+    // We need to check each variable individually because adding two large values together overflows.
+    if ((Offset               >= BlockSize) ||
+        (*NumBytes            >  BlockSize) ||
+        ((Offset + *NumBytes) >  BlockSize))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL] ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", __FUNCTION__, __LINE__, Offset, *NumBytes, BlockSize ));
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+    // We must have some bytes to read
+    if (*NumBytes == 0)
+    {
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+    // Get the address to start reading from
+    StartAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress,
+                                      Lba,
+                                      BlockSize
+                                     );
+    ReadAddress = StartAddress - Instance->DeviceBaseAddress + Offset;
+
+    Status = mFlash->Read(mFlash, (UINT32)ReadAddress, Buffer, *NumBytes);
+    if (EFI_SUCCESS != Status)
+    {
+        // Return one of the pre-approved error statuses
+        Status = EFI_DEVICE_ERROR;
+        return Status;
+    }
+
+
+    return Status;
+}
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again.  Before calling the
+ Write() function,  it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This                 Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba                  The starting logical block index to write to.
+
+ @param Offset               Offset into the block at which to begin writing.
+
+ @param NumBytes             The pointer to a UINTN.
+                             At entry, *NumBytes contains the total size of the buffer.
+                             At exit, *NumBytes contains the total number of bytes actually written.
+
+ @param Buffer               The pointer to a caller-allocated buffer that contains the source for the write.
+
+ @retval EFI_SUCCESS         The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
+                             On output, NumBytes contains the total number of bytes
+                             actually written.
+
+ @retval EFI_ACCESS_DENIED   The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR    The block device is malfunctioning and could not be written.
+
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbWrite (
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*   This,
+    IN        EFI_LBA                               Lba,
+    IN        UINTN                                 Offset,
+    IN OUT    UINTN*                                 NumBytes,
+    IN        UINT8*                                 Buffer
+)
+{
+    EFI_STATUS                     Status;
+    UINTN                       BlockSize;
+    FLASH_INSTANCE*              Instance;
+    UINTN                    BlockAddress;
+    UINTN                    WriteAddress;
+
+    Instance = INSTANCE_FROM_FVB_THIS(This);
+    if (NULL == Instance)
+    {
+        return EFI_INVALID_PARAMETER;
+
+    }
+
+    if (!Instance->Initialized && Instance->Initialize)
+    {
+        if (EfiAtRuntime ()) {
+            DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Initialize at runtime is not supported!\n", __FUNCTION__, __LINE__));
+            return EFI_UNSUPPORTED;
+        }
+
+        Instance->Initialize(Instance);
+    }
+
+    Status = EFI_SUCCESS;
+
+    // Detect WriteDisabled state
+    if (Instance->Media.ReadOnly == TRUE)
+    {
+        DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - Can not write: Device is in WriteDisabled state.\n"));
+        // It is in WriteDisabled state, return an error right away
+        return EFI_ACCESS_DENIED;
+    }
+
+    // Cache the block size to avoid de-referencing pointers all the time
+    BlockSize = Instance->Media.BlockSize;
+
+    // The write must not span block boundaries.
+    // We need to check each variable individually because adding two large values together overflows.
+    if ( ( Offset               >= BlockSize ) ||
+         ( *NumBytes            >  BlockSize ) ||
+         ( (Offset + *NumBytes) >  BlockSize )    )
+    {
+        DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+    // We must have some bytes to write
+    if (*NumBytes == 0)
+    {
+        DEBUG ((EFI_D_ERROR, "FvbWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+    BlockAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, BlockSize);
+    WriteAddress = BlockAddress - Instance->DeviceBaseAddress + Offset;
+
+    Status = mFlash->Write(mFlash, (UINT32)WriteAddress, (UINT8*)Buffer, *NumBytes);
+    if (EFI_SUCCESS != Status)
+    {
+        DEBUG((EFI_D_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status));
+        return Status;
+    }
+
+    return Status;
+
+}
+
+/**
+ Erases and initialises a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This                     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ...                      The variable argument list is a list of tuples.
+                                 Each tuple describes a range of LBAs to erase
+                                 and consists of the following:
+                                 - An EFI_LBA that indicates the starting LBA
+                                 - A UINTN that indicates the number of blocks to erase.
+
+                                 The list is terminated with an EFI_LBA_LIST_TERMINATOR.
+                                 For example, the following indicates that two ranges of blocks
+                                 (5-7 and 10-11) are to be erased:
+                                 EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+ @retval EFI_SUCCESS             The erase request successfully completed.
+
+ @retval EFI_ACCESS_DENIED       The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR        The block device is not functioning correctly and could not be written.
+                                 The firmware device may have been partially erased.
+
+ @retval EFI_INVALID_PARAMETER   One or more of the LBAs listed in the variable argument list do
+                                 not exist in the firmware volume.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks (
+    IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+    ...
+)
+{
+    EFI_STATUS  Status;
+    VA_LIST     Args;
+    UINTN       BlockAddress; // Physical address of Lba to erase
+    EFI_LBA     StartingLba; // Lba from which we start erasing
+    UINTN       NumOfLba; // Number of Lba blocks to erase
+    FLASH_INSTANCE* Instance;
+
+    Instance = INSTANCE_FROM_FVB_THIS(This);
+
+    Status = EFI_SUCCESS;
+
+    // Detect WriteDisabled state
+    if (Instance->Media.ReadOnly == TRUE)
+    {
+        // Firmware volume is in WriteDisabled state
+        return EFI_ACCESS_DENIED;
+    }
+
+    // Before erasing, check the entire list of parameters to ensure all specified blocks are valid
+    VA_START (Args, This);
+    do
+    {
+        // Get the Lba from which we start erasing
+        StartingLba = VA_ARG (Args, EFI_LBA);
+
+        // Have we reached the end of the list?
+        if (StartingLba == EFI_LBA_LIST_TERMINATOR)
+        {
+            //Exit the while loop
+            break;
+        }
+
+        // How many Lba blocks are we requested to erase?
+        NumOfLba = VA_ARG (Args, UINT32);
+
+        // All blocks must be within range
+        if ((NumOfLba == 0) || ((Instance->StartLba + StartingLba + NumOfLba - 1) > Instance->Media.LastBlock))
+        {
+            VA_END (Args);
+            Status = EFI_INVALID_PARAMETER;
+            goto EXIT;
+        }
+    }
+    while (TRUE);
+    VA_END (Args);
+
+    //
+    // To get here, all must be ok, so start erasing
+    //
+    VA_START (Args, This);
+    do
+    {
+        // Get the Lba from which we start erasing
+        StartingLba = VA_ARG (Args, EFI_LBA);
+
+        // Have we reached the end of the list?
+        if (StartingLba == EFI_LBA_LIST_TERMINATOR)
+        {
+            // Exit the while loop
+            break;
+        }
+
+        // How many Lba blocks are we requested to erase?
+        NumOfLba = VA_ARG (Args, UINT32);
+
+        // Go through each one and erase it
+        while (NumOfLba > 0)
+        {
+
+            // Get the physical address of Lba to erase
+            BlockAddress = GET_BLOCK_ADDRESS (
+                               Instance->RegionBaseAddress,
+                               Instance->StartLba + StartingLba,
+                               Instance->Media.BlockSize
+                           );
+
+            // Erase it
+
+            Status = FlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
+            if (EFI_ERROR(Status))
+            {
+                VA_END (Args);
+                Status = EFI_DEVICE_ERROR;
+                goto EXIT;
+            }
+
+            // Move to the next Lba
+            StartingLba++;
+            NumOfLba--;
+        }
+    }
+    while (TRUE);
+    VA_END (Args);
+
+EXIT:
+    return Status;
+}
+
+EFI_STATUS
+EFIAPI
+FvbInitialize (
+    IN FLASH_INSTANCE* Instance
+)
+{
+    EFI_STATUS  Status;
+    UINT32      FvbNumLba;
+
+    Instance->Initialized = TRUE;
+    mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase);
+
+    // Set the index of the first LBA for the FVB
+    Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
+
+    // Determine if there is a valid header at the beginning of the Flash
+    Status = ValidateFvHeader (Instance);
+    if (EFI_ERROR(Status))
+    {
+        // There is no valid header, so time to install one.
+        // Erase all the Flash that is reserved for variable storage
+        FvbNumLba = (PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) + (UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize;
+        Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR);
+        if (EFI_ERROR(Status))
+        {
+            return Status;
+        }
+
+        // Install all appropriate headers
+        Status = InitializeFvAndVariableStoreHeaders (Instance);
+        if (EFI_ERROR(Status))
+        {
+            return Status;
+        }
+    }
+    return Status;
+}
+
+
+EFI_STATUS
+FlashPlatformGetDevices (
+    OUT FLASH_DESCRIPTION**   FlashDevices,
+    OUT UINT32*                  Count
+)
+{
+    if ((FlashDevices == NULL) || (Count == NULL))
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    *FlashDevices = mFlashDevices;
+    *Count = FLASH_DEVICE_COUNT;
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+FlashCreateInstance (
+    IN UINTN                  FlashDeviceBase,
+    IN UINTN                  FlashRegionBase,
+    IN UINTN                  FlashSize,
+    IN UINT32                 MediaId,
+    IN UINT32                 BlockSize,
+    IN BOOLEAN                SupportFvb,
+    IN CONST GUID*             FlashGuid,
+    OUT FLASH_INSTANCE**  FlashInstance
+)
+{
+    EFI_STATUS Status;
+    FLASH_INSTANCE* Instance;
+
+    if (FlashInstance == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Instance = AllocateRuntimeCopyPool (sizeof(FLASH_INSTANCE), &mFlashInstanceTemplate);
+    if (Instance == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Instance->DeviceBaseAddress = FlashDeviceBase;
+    Instance->RegionBaseAddress = FlashRegionBase;
+    Instance->Size = FlashSize;
+
+    Instance->BlockIoProtocol.Media = &Instance->Media;
+    Instance->Media.MediaId = MediaId;
+    Instance->Media.BlockSize = BlockSize;
+    Instance->Media.LastBlock = (FlashSize / BlockSize) - 1;
+
+    CopyGuid (&Instance->DevicePath.Vendor.Guid, FlashGuid);
+
+    if (SupportFvb)
+    {
+        Instance->SupportFvb = TRUE;
+        Instance->Initialize = FvbInitialize;
+
+        Status = gBS->InstallMultipleProtocolInterfaces (
+                     &Instance->Handle,
+                     &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+                     &gEfiBlockIoProtocolGuid,  &Instance->BlockIoProtocol,
+                     &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
+                     NULL
+                 );
+
+        if (EFI_ERROR(Status))
+        {
+            FreePool(Instance);
+            return Status;
+        }
+    }
+    else
+    {
+        Instance->Initialized = TRUE;
+
+        Status = gBS->InstallMultipleProtocolInterfaces (
+                     &Instance->Handle,
+                     &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+                     &gEfiBlockIoProtocolGuid,  &Instance->BlockIoProtocol,
+                     NULL
+                 );
+        if (EFI_ERROR(Status))
+        {
+            FreePool(Instance);
+            return Status;
+        }
+    }
+
+    *FlashInstance = Instance;
+    return Status;
+}
+
+EFI_STATUS
+FlashUnlockSingleBlockIfNecessary (
+    IN FLASH_INSTANCE*           Instance,
+    IN UINTN                  BlockAddress
+)
+{
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+FlashEraseSingleBlock (
+    IN FLASH_INSTANCE*           Instance,
+    IN UINTN                  BlockAddress
+)
+{
+    EFI_STATUS            Status;
+    UINTN                 EraseAddress;
+
+    Status = EFI_SUCCESS;
+    EraseAddress = BlockAddress - Instance->DeviceBaseAddress;
+
+    Status = mFlash->Erase(mFlash, (UINT32)EraseAddress, Instance->Media.BlockSize);
+    if (EFI_SUCCESS != Status)
+    {
+        DEBUG((EFI_D_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status));
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+/**
+ * The following function presumes that the block has already been unlocked.
+ **/
+EFI_STATUS
+FlashUnlockAndEraseSingleBlock (
+    IN FLASH_INSTANCE*     Instance,
+    IN UINTN                  BlockAddress
+)
+{
+    EFI_STATUS      Status;
+    UINTN           Index;
+
+    Index = 0;
+    // The block erase might fail a first time (SW bug ?). Retry it ...
+    do
+    {
+        // Unlock the block if we have to
+        Status = FlashUnlockSingleBlockIfNecessary (Instance, BlockAddress);
+        if (!EFI_ERROR(Status))
+        {
+            Status = FlashEraseSingleBlock (Instance, BlockAddress);
+        }
+        Index++;
+    }
+    while ((Index < FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED));
+
+    if (Index == FLASH_ERASE_RETRY)
+    {
+        DEBUG((EFI_D_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", BlockAddress, Index));
+    }
+
+    return Status;
+}
+
+EFI_STATUS
+FlashWriteBlocks (
+    IN FLASH_INSTANCE*        Instance,
+    IN EFI_LBA                Lba,
+    IN UINTN                  BufferSizeInBytes,
+    IN VOID*                   Buffer
+)
+{
+    EFI_STATUS      Status = EFI_SUCCESS;
+    UINTN                   BlockAddress;
+    UINT32                     NumBlocks;
+    UINTN                   WriteAddress;
+
+    // The buffer must be valid
+    if (Buffer == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if (Instance->Media.ReadOnly == TRUE)
+    {
+        return EFI_WRITE_PROTECTED;
+    }
+
+    // We must have some bytes to read
+    if (BufferSizeInBytes == 0)
+    {
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+    // The size of the buffer must be a multiple of the block size
+    if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0)
+    {
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+    // All blocks must be within the device
+    NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
+    if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL]ERROR - Write will exceed last block.\n", __FUNCTION__, __LINE__ ));
+        return EFI_INVALID_PARAMETER;
+    }
+
+    BlockAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, Instance->Media.BlockSize);
+
+    WriteAddress = BlockAddress - Instance->DeviceBaseAddress;
+
+    Status = mFlash->Write(mFlash, (UINT32)WriteAddress, (UINT8*)Buffer, BufferSizeInBytes);
+    if (EFI_SUCCESS != Status)
+    {
+        DEBUG((EFI_D_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status));
+        return Status;
+    }
+
+    return Status;
+}
+
+EFI_STATUS
+FlashReadBlocks (
+    IN FLASH_INSTANCE*   Instance,
+    IN EFI_LBA              Lba,
+    IN UINTN                BufferSizeInBytes,
+    OUT VOID*                Buffer
+)
+{
+    UINT32                     NumBlocks;
+    UINTN                   StartAddress;
+    UINTN                    ReadAddress;
+    EFI_STATUS                    Status;
+
+    // The buffer must be valid
+    if (Buffer == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    // We must have some bytes to read
+    if (BufferSizeInBytes == 0)
+    {
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+    // The size of the buffer must be a multiple of the block size
+    if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0)
+    {
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+    // All blocks must be within the device
+    NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
+    if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1))
+    {
+        DEBUG((EFI_D_ERROR, "FlashReadBlocks: ERROR - Read will exceed last block\n"));
+        return EFI_INVALID_PARAMETER;
+    }
+
+    // Get the address to start reading from
+    StartAddress = GET_BLOCK_ADDRESS (Instance->RegionBaseAddress,
+                                      Lba,
+                                      Instance->Media.BlockSize
+                                     );
+
+
+    ReadAddress = StartAddress - Instance->DeviceBaseAddress;
+
+    Status = mFlash->Read(mFlash, (UINT32)ReadAddress, Buffer, BufferSizeInBytes);
+    if (EFI_SUCCESS != Status)
+    {
+        DEBUG((EFI_D_ERROR, "%s - %d Status=%r\n", __FILE__, __LINE__, Status));
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+VOID
+EFIAPI
+FlashFvbVirtualNotifyEvent (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  EfiConvertPointer (0x0, (VOID**)&mFlash);
+  EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
+  return;
+}
+
+EFI_STATUS
+EFIAPI
+FlashFvbInitialize (
+    IN EFI_HANDLE         ImageHandle,
+    IN EFI_SYSTEM_TABLE*   SystemTable
+)
+{
+    EFI_STATUS              Status;
+    UINT32                  Index;
+    FLASH_DESCRIPTION*      FlashDevices;
+    UINT32                  FlashDeviceCount;
+    BOOLEAN                 ContainVariableStorage;
+
+
+    Status = FlashPlatformGetDevices (&FlashDevices, &FlashDeviceCount);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Fail to get Flash devices\n", __FUNCTION__, __LINE__));
+        return Status;
+    }
+
+    mFlashInstances = AllocatePool ((UINT32)(sizeof(FLASH_INSTANCE*) * FlashDeviceCount));
+
+    Status = gBS->LocateProtocol (&gHisiSpiFlashProtocolGuid, NULL, (VOID*) &mFlash);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status=%r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    for (Index = 0; Index < FlashDeviceCount; Index++)
+    {
+        // Check if this Flash device contain the variable storage region
+        ContainVariableStorage =
+            (FlashDevices[Index].RegionBaseAddress <= (UINT32)PcdGet32 (PcdFlashNvStorageVariableBase)) &&
+            ((UINT32)(PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size);
+
+        Status = FlashCreateInstance (
+                     FlashDevices[Index].DeviceBaseAddress,
+                     FlashDevices[Index].RegionBaseAddress,
+                     FlashDevices[Index].Size,
+                     Index,
+                     FlashDevices[Index].BlockSize,
+                     ContainVariableStorage,
+                     &FlashDevices[Index].Guid,
+                     &mFlashInstances[Index]
+                 );
+        if (EFI_ERROR(Status))
+        {
+            DEBUG((EFI_D_ERROR, "[%a]:[%dL] Fail to create instance for Flash[%d]\n", __FUNCTION__, __LINE__, Index));
+        }
+    }
+    //
+    // Register for the virtual address change event
+    //
+    Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  FlashFvbVirtualNotifyEvent,
+                  NULL,
+                  &gEfiEventVirtualAddressChangeGuid,
+                  &mFlashFvbVirtualAddrChangeEvent
+                  );
+    ASSERT_EFI_ERROR (Status);
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h
new file mode 100644
index 0000000..76385b6
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.h
@@ -0,0 +1,228 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef __FLASH_FVB_DXE_H__
+#define __FLASH_FVB_DXE_H__
+
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+#include <Protocol/BlockIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+#include <Library/DebugLib.h>
+
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/HisiSpiFlashProtocol.h>
+
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <Guid/VariableFormat.h>
+#include <Guid/SystemNvDataGuid.h>
+
+
+#define FLASH_ERASE_RETRY                     10
+#define FLASH_DEVICE_COUNT                     1
+
+// Device access macros
+// These are necessary because we use 2 x 16bit parts to make up 32bit data
+typedef struct
+{
+    UINTN       DeviceBaseAddress;    // Start address of the Device Base Address (DBA)
+    UINTN       RegionBaseAddress;    // Start address of one single region
+    UINTN       Size;
+    UINTN       BlockSize;
+    EFI_GUID    Guid;
+} FLASH_DESCRIPTION;
+
+#define GET_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) )
+
+#define FLASH_SIGNATURE                       SIGNATURE_32('s', 'p', 'i', '0')
+#define INSTANCE_FROM_FVB_THIS(a)             CR(a, FLASH_INSTANCE, FvbProtocol, FLASH_SIGNATURE)
+#define INSTANCE_FROM_BLKIO_THIS(a)           CR(a, FLASH_INSTANCE, BlockIoProtocol, FLASH_SIGNATURE)
+
+typedef struct _FLASH_INSTANCE                FLASH_INSTANCE;
+
+typedef EFI_STATUS (*FLASH_INITIALIZE)        (FLASH_INSTANCE* Instance);
+
+typedef struct
+{
+    VENDOR_DEVICE_PATH                  Vendor;
+    EFI_DEVICE_PATH_PROTOCOL            End;
+} FLASH_DEVICE_PATH;
+
+struct _FLASH_INSTANCE
+{
+    UINT32                              Signature;
+    EFI_HANDLE                          Handle;
+
+    BOOLEAN                             Initialized;
+    FLASH_INITIALIZE                    Initialize;
+
+    UINTN                               DeviceBaseAddress;
+    UINTN                               RegionBaseAddress;
+    UINTN                               Size;
+    EFI_LBA                             StartLba;
+
+    EFI_BLOCK_IO_PROTOCOL               BlockIoProtocol;
+    EFI_BLOCK_IO_MEDIA                  Media;
+
+    BOOLEAN                             SupportFvb;
+    EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
+
+    FLASH_DEVICE_PATH                   DevicePath;
+};
+
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoReadBlocks (
+    IN  EFI_BLOCK_IO_PROTOCOL*   This,
+    IN  UINT32                   MediaId,
+    IN  EFI_LBA                  Lba,
+    IN  UINTN                    BufferSizeInBytes,
+    OUT VOID*                    Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoWriteBlocks (
+    IN  EFI_BLOCK_IO_PROTOCOL*   This,
+    IN  UINT32                   MediaId,
+    IN  EFI_LBA                  Lba,
+    IN  UINTN                    BufferSizeInBytes,
+    IN  VOID*                    Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+FlashBlockIoFlushBlocks (
+    IN EFI_BLOCK_IO_PROTOCOL*    This
+);
+
+
+//
+// FvbHw.c
+//
+
+EFI_STATUS
+EFIAPI
+FvbInitialize (
+    IN FLASH_INSTANCE*                            Instance
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*     This,
+    OUT       EFI_FVB_ATTRIBUTES_2*                    Attributes
+);
+
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*     This,
+    IN OUT    EFI_FVB_ATTRIBUTES_2*                    Attributes
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*     This,
+    OUT       EFI_PHYSICAL_ADDRESS*                    Address
+);
+
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*     This,
+    IN        EFI_LBA                                  Lba,
+    OUT       UINTN*                                   BlockSize,
+    OUT       UINTN*                                   NumberOfBlocks
+);
+
+EFI_STATUS
+EFIAPI
+FvbRead(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*     This,
+    IN        EFI_LBA                                  Lba,
+    IN        UINTN                                   Offset,
+    IN OUT    UINTN*                                   NumBytes,
+    IN OUT    UINT8*                                   Buffer
+);
+
+EFI_STATUS
+EFIAPI
+FvbWrite(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*     This,
+    IN        EFI_LBA                                  Lba,
+    IN        UINTN                                    Offset,
+    IN OUT    UINTN*                                   NumBytes,
+    IN        UINT8*                                   Buffer
+);
+
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks(
+    IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL*     This,
+    ...
+);
+
+//
+// FlashFvbDxe.c
+//
+
+EFI_STATUS
+FlashUnlockAndEraseSingleBlock (
+    IN FLASH_INSTANCE*         Instance,
+    IN UINTN                   BlockAddress
+);
+
+EFI_STATUS
+FlashWriteBlocks (
+    IN  FLASH_INSTANCE*    Instance,
+    IN  EFI_LBA            Lba,
+    IN  UINTN              BufferSizeInBytes,
+    IN  VOID*              Buffer
+);
+
+EFI_STATUS
+FlashReadBlocks (
+    IN FLASH_INSTANCE*       Instance,
+    IN EFI_LBA               Lba,
+    IN UINTN                 BufferSizeInBytes,
+    OUT VOID*                Buffer
+);
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
new file mode 100644
index 0000000..aa9c288
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
@@ -0,0 +1,69 @@
+#/** @file
+#
+#    Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = FlashFvbDxe
+  FILE_GUID                      = 93E34C7E-B50E-11DF-9223-2443DFD72085
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = FlashFvbInitialize
+
+[Sources.common]
+  FlashFvbDxe.c
+  FlashBlockIoDxe.c
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  IoLib
+  BaseLib
+  DebugLib
+  HobLib
+  UefiLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  UefiRuntimeLib
+
+[Guids]
+  gEfiSystemNvDataFvGuid
+  gEfiVariableGuid
+
+[Protocols]
+  gEfiBlockIoProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiFirmwareVolumeBlockProtocolGuid
+  gHisiSpiFlashProtocolGuid
+
+[Pcd.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+  gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked
+
+[Depex]
+  gHisiSpiFlashProtocolGuid
+
+[BuildOptions]
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 0000000..c8b56e1
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,269 @@
+/** @file
+  Sample ACPI Platform Driver
+
+  Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <IndustryStandard/Acpi.h>
+#include "UpdateAcpiTable.h"
+
+/**
+  Locate the first instance of a protocol.  If the protocol requested is an
+  FV protocol, then it will return the first FV that contains the ACPI table
+  storage file.
+
+  @param  Instance      Return pointer to the first instance of the protocol
+
+  @return EFI_SUCCESS           The function completed successfully.
+  @return EFI_NOT_FOUND         The protocol could not be located.
+  @return EFI_OUT_OF_RESOURCES  There are not enough resources to find the protocol.
+
+**/
+EFI_STATUS
+LocateFvInstanceWithTables (
+  OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         NumberOfHandles;
+  EFI_FV_FILETYPE               FileType;
+  UINT32                        FvStatus;
+  EFI_FV_FILE_ATTRIBUTES        Attributes;
+  UINTN                         Size;
+  UINTN                         Index;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;
+
+  FvStatus = 0;
+
+  //
+  // Locate protocol.
+  //
+  Status = gBS->LocateHandleBuffer (
+                   ByProtocol,
+                   &gEfiFirmwareVolume2ProtocolGuid,
+                   NULL,
+                   &NumberOfHandles,
+                   &HandleBuffer
+                   );
+  if (EFI_ERROR (Status)) {
+    //
+    // Defined errors at this time are not found and out of resources.
+    //
+    return Status;
+  }
+
+
+
+  //
+  // Looking for FV with ACPI storage file
+  //
+
+  for (Index = 0; Index < NumberOfHandles; Index++) {
+    //
+    // Get the protocol on this handle
+    // This should not fail because of LocateHandleBuffer
+    //
+    Status = gBS->HandleProtocol (
+                     HandleBuffer[Index],
+                     &gEfiFirmwareVolume2ProtocolGuid,
+                     (VOID**) &FvInstance
+                     );
+    ASSERT_EFI_ERROR (Status);
+
+    //
+    // See if it has the ACPI storage file
+    //
+    Status = FvInstance->ReadFile (
+                           FvInstance,
+                           (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
+                           NULL,
+                           &Size,
+                           &FileType,
+                           &Attributes,
+                           &FvStatus
+                           );
+
+    //
+    // If we found it, then we are done
+    //
+    if (Status == EFI_SUCCESS) {
+      *Instance = FvInstance;
+      break;
+    }
+  }
+
+  //
+  // Our exit status is determined by the success of the previous operations
+  // If the protocol was found, Instance already points to it.
+  //
+
+  //
+  // Free any allocated buffers
+  //
+  gBS->FreePool (HandleBuffer);
+
+  return Status;
+}
+
+
+/**
+  This function calculates and updates an UINT8 checksum.
+
+  @param  Buffer          Pointer to buffer to checksum
+  @param  Size            Number of bytes to checksum
+
+**/
+VOID
+AcpiPlatformChecksum (
+  IN UINT8      *Buffer,
+  IN UINTN      Size
+  )
+{
+  UINTN ChecksumOffset;
+
+  ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
+
+  //
+  // Set checksum to 0 first
+  //
+  Buffer[ChecksumOffset] = 0;
+
+  //
+  // Update checksum value
+  //
+  Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
+}
+
+
+/**
+  Entrypoint of Acpi Platform driver.
+
+  @param  ImageHandle
+  @param  SystemTable
+
+  @return EFI_SUCCESS
+  @return EFI_LOAD_ERROR
+  @return EFI_OUT_OF_RESOURCES
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS                     Status;
+  EFI_ACPI_TABLE_PROTOCOL        *AcpiTable;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL  *FwVol;
+  INTN                           Instance;
+  EFI_ACPI_COMMON_HEADER         *CurrentTable;
+  UINTN                          TableHandle;
+  UINT32                         FvStatus;
+  UINTN                          TableSize;
+  UINTN                          Size;
+  EFI_STATUS                     TableStatus;
+  EFI_ACPI_DESCRIPTION_HEADER    *TableHeader;
+
+  Instance     = 0;
+  CurrentTable = NULL;
+  TableHandle  = 0;
+
+  //
+  // Find the AcpiTable protocol
+  //
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+  if (EFI_ERROR (Status)) {
+    return EFI_ABORTED;
+  }
+
+  //
+  // Locate the firmware volume protocol
+  //
+  Status = LocateFvInstanceWithTables (&FwVol);
+  if (EFI_ERROR (Status)) {
+    return EFI_ABORTED;
+  }
+  //
+  // Read tables from the storage file.
+  //
+  while (Status == EFI_SUCCESS) {
+
+    Status = FwVol->ReadSection (
+                      FwVol,
+                      (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
+                      EFI_SECTION_RAW,
+                      Instance,
+                      (VOID**) &CurrentTable,
+                      &Size,
+                      &FvStatus
+                      );
+    if (!EFI_ERROR(Status)) {
+      //
+      // Add the table
+      //
+      TableHeader = (EFI_ACPI_DESCRIPTION_HEADER*) (CurrentTable);
+      //Update specfic Acpi Table
+      //If the Table is updated failed, doesn't install it,
+      //go to find next section.
+      TableStatus = UpdateAcpiTable(TableHeader);
+      if (TableStatus == EFI_SUCCESS) {
+        TableHandle = 0;
+
+        TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
+        ASSERT (Size >= TableSize);
+
+        //
+        // Checksum ACPI table
+        //
+        AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);
+
+        //
+        // Install ACPI table
+        //
+        Status = AcpiTable->InstallAcpiTable (
+                              AcpiTable,
+                              CurrentTable,
+                              TableSize,
+                              &TableHandle
+                              );
+      }
+      //
+      // Free memory allocated by ReadSection
+      //
+      gBS->FreePool (CurrentTable);
+
+      if (EFI_ERROR(Status)) {
+        return EFI_ABORTED;
+      }
+
+      //
+      // Increment the instance
+      //
+      Instance++;
+      CurrentTable = NULL;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni
new file mode 100644
index 0000000..1275549
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni
@@ -0,0 +1,22 @@
+// /** @file
+// Sample ACPI Platform Driver
+//
+// Sample ACPI Platform Driver
+//
+// Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Sample ACPI Platform Driver"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Sample ACPI Platform Driver"
+
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
new file mode 100644
index 0000000..56514e5
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -0,0 +1,62 @@
+## @file
+#  Sample ACPI Platform Driver
+#
+#  Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AcpiPlatform
+  MODULE_UNI_FILE                = AcpiPlatform.uni
+  FILE_GUID                      = cb933912-df8f-4305-b1f9-7b44fa11395c
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = AcpiPlatformEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC
+#
+
+[Sources]
+  AcpiPlatform.c
+  UpdateAcpiTable.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiLib
+  DxeServicesLib
+  PcdLib
+  BaseMemoryLib
+  DebugLib
+  HobLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[Protocols]
+  gEfiAcpiTableProtocolGuid                     ## CONSUMES
+
+[Guids]
+  gHisiEfiMemoryMapGuid
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile    ## CONSUMES
+
+[Depex]
+  gEfiAcpiTableProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  AcpiPlatformExtra.uni
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni
new file mode 100644
index 0000000..4c21968
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni
@@ -0,0 +1,20 @@
+// /** @file
+// AcpiPlatform Localized Strings and Content
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"ACPI Platform Sample DXE Driver"
+
+
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
new file mode 100644
index 0000000..7d06fcc
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
@@ -0,0 +1,137 @@
+/** @file
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <PlatformArch.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiNextLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/HwMemInitLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#define CORE_NUM_PER_SOCKET  32
+#define NODE_IN_SOCKET       2
+#define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET)
+
+STATIC
+VOID
+RemoveUnusedMemoryNode (
+  IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE  *Table,
+  IN     UINTN                        MemoryNodeNum
+)
+{
+  UINTN                   CurrPtr, NewPtr;
+
+  if (MemoryNodeNum >= EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT) {
+    return;
+  }
+
+  CurrPtr = (UINTN) &(Table->Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]);
+  NewPtr = (UINTN) &(Table->Memory[MemoryNodeNum]);
+
+  CopyMem ((VOID *)NewPtr, (VOID *)CurrPtr, (UINTN)Table + Table->Header.Header.Length - CurrPtr);
+
+  Table->Header.Header.Length -= CurrPtr - NewPtr;
+
+  return;
+}
+
+STATIC
+EFI_STATUS
+UpdateSrat (
+  IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table
+  )
+{
+  UINT8               Skt = 0;
+  UINTN               Index = 0;
+  VOID                *HobList;
+  GBL_DATA            *Gbl_Data;
+  UINTN               Base;
+  UINTN               Size;
+  UINT8               NodeId;
+  UINT32              ScclInterleaveEn;
+  UINTN               MemoryNode = 0;
+
+  DEBUG((DEBUG_INFO, "SRAT: Updating SRAT memory information.\n"));
+
+  HobList = GetHobList();
+  if (HobList == NULL) {
+    return EFI_UNSUPPORTED;
+  }
+  Gbl_Data = (GBL_DATA*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList);
+  if (Gbl_Data == NULL) {
+    DEBUG((DEBUG_ERROR, "Get next Guid HOb fail.\n"));
+    return EFI_NOT_FOUND;
+  }
+  Gbl_Data = GET_GUID_HOB_DATA(Gbl_Data);
+  for(Skt = 0; Skt < MAX_SOCKET; Skt++) {
+    for(Index = 0; Index < MAX_NUM_PER_TYPE; Index++) {
+      NodeId = Gbl_Data->NumaInfo[Skt][Index].NodeId;
+      Base = Gbl_Data->NumaInfo[Skt][Index].Base;
+      Size = Gbl_Data->NumaInfo[Skt][Index].Length;
+      DEBUG((DEBUG_INFO, "Skt %d Index %d: NodeId = %d, Base = 0x%lx, Size = 0x%lx\n", Skt, Index, NodeId, Base, Size));
+      if (Size > 0) {
+        Table->Memory[MemoryNode].ProximityDomain = NodeId;
+        Table->Memory[MemoryNode].AddressBaseLow = Base;
+        Table->Memory[MemoryNode].AddressBaseHigh = Base >> 32;
+        Table->Memory[MemoryNode].LengthLow = Size;
+        Table->Memory[MemoryNode].LengthHigh = Size >> 32;
+        MemoryNode = MemoryNode + 1;
+      }
+    }
+    ScclInterleaveEn = Gbl_Data->NumaInfo[Skt][0].ScclInterleaveEn;
+    DEBUG((DEBUG_INFO, "ScclInterleaveEn = %d\n", ScclInterleaveEn));
+    //update gicc structure
+    if (ScclInterleaveEn != 0) {
+      DEBUG((DEBUG_INFO, "SRAT: Updating SRAT Gicc information.\n"));
+      for (Index = CORECOUNT (Skt); Index < CORECOUNT (Skt + 1); Index++) {
+        Table->Gicc[Index].ProximityDomain = Skt * NODE_IN_SOCKET;
+      }
+    }
+  }
+
+  //remove invalid memory node
+  RemoveUnusedMemoryNode (Table, MemoryNode);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+UpdateSlit (
+  IN OUT EFI_ACPI_DESCRIPTION_HEADER  *Table
+  )
+{
+  return  EFI_SUCCESS;
+}
+
+EFI_STATUS
+UpdateAcpiTable (
+  IN OUT EFI_ACPI_DESCRIPTION_HEADER      *TableHeader
+)
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+
+  switch (TableHeader->Signature) {
+
+  case EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE:
+    Status = UpdateSrat ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) TableHeader);
+    break;
+
+  case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:
+    Status = UpdateSlit (TableHeader);
+    break;
+  }
+  return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.h b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.h
new file mode 100644
index 0000000..45b3729
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.h
@@ -0,0 +1,16 @@
+/** @file
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+EFI_STATUS
+UpdateAcpiTable (
+  IN OUT EFI_ACPI_DESCRIPTION_HEADER      *TableHeader
+);
+
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c
new file mode 100644
index 0000000..ab3b70c
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashConfig.c
@@ -0,0 +1,162 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include "NorFlashHw.h"
+
+
+#define COMMAND_TYPE1 0x1
+#define COMMAND_TYPE2 0x2
+#define COMMAND_TYPE3 0x4
+#define COMMAND_TYPE4 0x8
+#define COMMAND_TYPE5 0x10
+
+
+NOR_FLASH_INFO_TABLE gFlashInfo[]=
+{
+
+    {//S29GL512m
+      0x00010001,
+      0x227E227E,
+      0x22232223,
+      0x22012201,
+      1,
+      0x20000000,
+      0x20000,
+      0x0010,
+      COMMAND_TYPE1
+    },
+    {//S29GL1g
+      0x00010001,
+      0x227E227E,
+      0x22282228,
+      0x22012201,
+      1,
+      0x40000000,
+      0x20000,
+      0x0020,
+      COMMAND_TYPE1
+    },
+    {//M29ew512m
+      0x00890089,
+      0x227E227E,
+      0x22232223,
+      0x22012201,
+      1,
+      0x20000000,
+      0x20000,
+      0x0010,
+      COMMAND_TYPE1
+    },
+    {//M29EW2g
+      0x00890089,
+      0x227E227E,
+      0x22482248,
+      0x22012201,
+      1,
+      0x80000000,
+      0x20000,
+      0x0020,
+      COMMAND_TYPE1
+    },
+    {
+      0x00890089,
+      0x227E227E,
+      0x22282228,
+      0x22012201,
+      1,
+      0x10000000,
+      0x20000,
+      0x0020,
+      COMMAND_TYPE1
+    },
+    {
+      0x00890089,
+      0x227E227E,
+      0x22282228,
+      0x22012201,
+      2,
+      0x10000000,
+      0x20000,
+      0x0020,
+      COMMAND_TYPE1
+    }
+};
+
+
+
+FLASH_COMMAND_RESET gFlashCommandReset[]=
+{
+    {
+       COMMAND_TYPE1,
+       (0x00F000F0)
+    }
+
+};
+
+
+FLASH_COMMAND_ID gFlashCommandId[]=
+{
+     {
+       COMMAND_TYPE1,
+       (0x0555),
+       (0x00AA00AA),
+       (0x02AA),
+       (0x00550055),
+       (0x0555),
+       (0x00900090),
+       (0x0000),
+
+       (0x0001),
+       (0x000E),
+       (0x000F)
+    }
+};
+
+
+FLASH_COMMAND_WRITE gFlashCommandWrite[]=
+{
+    {
+       COMMAND_TYPE1,
+       (0x0555),
+       (0x00AA00AA),
+       (0x02AA),
+       (0x00550055),
+       (0x00250025),
+       (0x00290029)
+    }
+
+};
+
+
+FLASH_COMMAND_ERASE gFlashCommandErase[]=
+{
+    {
+       COMMAND_TYPE1,
+       (0x0555),
+       (0x00AA00AA),
+       (0x02AA),
+       (0x00550055),
+       (0x0555),
+       (0x00800080),
+       (0x0555),
+       (0x00AA00AA),
+       (0x02AA),
+       (0x00550055),
+       (0x00300030)
+    }
+
+};
+
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c
new file mode 100644
index 0000000..8b8a5d7
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.c
@@ -0,0 +1,594 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <Protocol/NorFlashProtocol.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Protocol/Cpu.h>
+#include "NorFlashHw.h"
+
+
+EFI_STATUS Erase(
+   IN UNI_NOR_FLASH_PROTOCOL   *This,
+   IN  UINT32                   Offset,
+   IN  UINT32                   Length
+  );
+
+EFI_STATUS  Write(
+  IN UNI_NOR_FLASH_PROTOCOL   *This,
+  IN  UINT32                  Offset,
+  IN  UINT8                  *Buffer,
+  UINT32                     ulLength
+  );
+
+EFI_STATUS Read(
+  IN UNI_NOR_FLASH_PROTOCOL   *This,
+  IN UINT32                   Offset,
+  IN OUT UINT8               *Buffer,
+  IN UINT32                   ulLen
+  );
+
+UNI_NOR_FLASH_PROTOCOL gUniNorFlash = {
+    Erase,
+    Write,
+    Read
+};
+
+
+EFI_STATUS
+EFIAPI Read(
+  IN UNI_NOR_FLASH_PROTOCOL   *This,
+  IN UINT32                   Offset,
+  IN OUT UINT8               *Buffer,
+  IN UINT32                    ulLen
+  )
+{
+    UINT32       index;
+    UINT64 ullAddr;
+    UINT32 ullCnt = 0;
+    UINT32 *puiBuffer32 = NULL;
+    UINT32 *puiDst32 = NULL;
+    UINT8 *pucBuffer8 = NULL;
+    UINT8 *pucDst8 = NULL;
+
+    if (Offset + ulLen > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Exceed the flash scope!\n", __FUNCTION__,__LINE__));
+        return EFI_INVALID_PARAMETER;
+    }
+    if (0 == ulLen)
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Length is Zero!\n", __FUNCTION__,__LINE__));
+        return EFI_INVALID_PARAMETER;
+    }
+    if (NULL == Buffer)
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Buffer is NULL!\n", __FUNCTION__,__LINE__));
+        return EFI_BAD_BUFFER_SIZE;
+    }
+
+
+    ullAddr = gIndex.Base + Offset;
+
+    pucBuffer8 = (UINT8 *)Buffer;
+    pucDst8    = (UINT8 *)((UINTN)ullAddr);
+
+
+    if (ulLen < FOUR_BYTE_UNIT)
+    {
+        for(index = 0; index< ulLen; index++)
+        {
+            *pucBuffer8++ = *pucDst8++;
+        }
+    }
+    else
+    {
+
+        ullCnt = Offset % FOUR_BYTE_UNIT;
+        ullCnt = FOUR_BYTE_UNIT - ullCnt;
+
+        for(index = 0; index < ullCnt; index++)
+        {
+            *pucBuffer8++ = *pucDst8++;
+        }
+
+        ulLen -= ullCnt;
+
+        puiBuffer32 = (UINT32 *)pucBuffer8;
+        puiDst32    = (UINT32 *)pucDst8;
+        ullCnt      = ulLen / FOUR_BYTE_UNIT;
+
+        for(index = 0; index < ullCnt; index++)
+        {
+            *puiBuffer32++ = *puiDst32++;
+        }
+
+        ullCnt     = ulLen % FOUR_BYTE_UNIT;
+        pucBuffer8 = (UINT8 *)puiBuffer32;
+        pucDst8    = (UINT8 *)puiDst32;
+
+        for(index = 0; index < ullCnt; index++)
+        {
+            *pucBuffer8++ = *pucDst8++;
+        }
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+
+static EFI_STATUS WriteAfterErase_Fill(
+    IN  const UINT32       Offset,
+    IN  const UINT8       *Buffer,
+    IN  const UINT32       Length
+    )
+{
+    EFI_STATUS Status;
+    UINT32 Loop;
+    UINT32 DataOffset;
+    UINT32 NewOffset;
+    UINT8 *NewDataUnit;
+
+    UINT32 FlashUnitLength;
+
+    FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum;
+
+    if (0 == Length)
+    {
+        return EFI_SUCCESS;
+    }
+    if ((Offset % FlashUnitLength + Length) > FlashUnitLength)
+    {
+        DEBUG ((EFI_D_INFO, "[%a]:[%dL]:Exceed the Flash Size!\n", __FUNCTION__,__LINE__));
+        return EFI_UNSUPPORTED;
+    }
+
+
+    Status = gBS->AllocatePool(EfiBootServicesData, FlashUnitLength, (VOID *)&NewDataUnit);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Allocate Pool failed, %r!\n", __FUNCTION__,__LINE__, Status));
+        return Status;
+    }
+
+
+    NewOffset = Offset - (Offset % FlashUnitLength);
+
+    gBS->CopyMem((VOID *)NewDataUnit, (VOID *)(UINTN)(gIndex.Base + NewOffset), FlashUnitLength);
+
+    DataOffset = Offset % FlashUnitLength;
+    for (Loop = 0; Loop < Length; Loop ++)
+    {
+        NewDataUnit[(UINT32)(DataOffset + Loop)] = Buffer[Loop];
+    }
+
+    Status = BufferWrite(NewOffset, (void *)NewDataUnit, FlashUnitLength);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:BufferWrite %r!\n", __FUNCTION__,__LINE__, Status));
+        return Status;
+    }
+
+    (void)gBS->FreePool((VOID *)NewDataUnit);
+    return Status;
+}
+
+
+static EFI_STATUS WriteAfterErase_Final(
+    IN  UINT32       Offset,
+    IN  UINT8       *Buffer,
+    IN  UINT32       Length
+    )
+{
+    EFI_STATUS Status;
+    UINT32 Loop;
+    UINT32 FlashUnitLength;
+
+    FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum;
+
+    if (0 == Length)
+    {
+        return EFI_SUCCESS;
+    }
+
+    if (0 != (Offset % FlashUnitLength))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: Offset must be a multiple of 0x%x!\n", __FUNCTION__,__LINE__,FlashUnitLength));
+        return EFI_UNSUPPORTED;
+    }
+
+
+    Loop = Length / FlashUnitLength;
+    while (Loop --)
+    {
+        Status = BufferWrite(Offset, (void *)Buffer, FlashUnitLength);
+        if (EFI_ERROR(Status))
+        {
+            DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:BufferWrite Failed: %r!\n", __FUNCTION__,__LINE__, Status));
+            return EFI_DEVICE_ERROR;
+        }
+        Offset += FlashUnitLength;
+        Buffer += FlashUnitLength;
+    }
+
+
+    Length = Length % FlashUnitLength;
+    if (Length)
+    {
+        Status = WriteAfterErase_Fill(Offset, Buffer, Length);
+        if (EFI_ERROR(Status))
+        {
+            DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:WriteAfterErase_Fill failed,%r!\n", __FUNCTION__,__LINE__, Status));
+            return Status;
+        }
+    }
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS
+WriteAfterErase(
+    UINT32       TempBase,
+    UINT32       Offset,
+    UINT8       *Buffer,
+    UINT32       Length
+  )
+{
+    EFI_STATUS Status;
+    UINT32 FlashUnitLength;
+
+    FlashUnitLength = gFlashInfo[gIndex.InfIndex].BufferProgramSize << gFlashInfo[gIndex.InfIndex].ParallelNum;
+
+    if (0 == Length)
+    {
+        return EFI_SUCCESS;
+    }
+
+
+    if (Offset % FlashUnitLength)
+    {
+        UINT32 TempLength;
+
+
+        TempLength = FlashUnitLength - (Offset % FlashUnitLength);
+        if (TempLength > Length)
+        {
+            TempLength = Length;
+        }
+        Status = WriteAfterErase_Fill(Offset, Buffer, TempLength);
+        if (EFI_ERROR(Status))
+        {
+            DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: %r!\n", __FUNCTION__,__LINE__, Status));
+            return Status;
+        }
+
+        Offset += TempLength;
+        Length -= TempLength;
+        Buffer += TempLength;
+
+        //Desc:if Offset >= gOneFlashSize,modify base
+        if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+        {
+            TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize;
+            gIndex.Base = TempBase;
+            Offset = 0;
+        }
+    }
+
+
+    Status = WriteAfterErase_Final(Offset, Buffer, Length);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: %r!\n", __FUNCTION__,__LINE__, Status));
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+FlashSectorErase(
+    UINT32      TempBase,
+    UINT32      Offset,
+    UINT32      Length
+  )
+{
+    EFI_STATUS  Status;
+    UINT32 SectorOffset;
+    UINT8 *StaticBuffer;
+    UINT8 *Buffer;
+    UINT32 TempOffset;
+    UINT32 TempLength;
+    UINT32 LeftLength;
+
+
+    if (0 == Length)
+    {
+        return EFI_SUCCESS;
+    }
+
+    LeftLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum));
+    if (LeftLength < Length)
+    {
+        return EFI_UNSUPPORTED;
+    }
+
+
+    SectorOffset = Offset - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum));
+
+    Status = gBS->AllocatePool(EfiBootServicesData, gFlashInfo[gIndex.InfIndex].BlockSize * (UINTN)gFlashInfo[gIndex.InfIndex].ParallelNum, (VOID *)&StaticBuffer);
+    if (EFI_ERROR(Status))
+    {
+        return Status;
+    }
+
+    Buffer = StaticBuffer;
+
+    gBS->CopyMem((VOID *)Buffer, (VOID *)(UINTN)(TempBase + SectorOffset),
+                 (gFlashInfo[gIndex.InfIndex].BlockSize * (UINTN)gFlashInfo[gIndex.InfIndex].ParallelNum));
+
+
+    Status = SectorErase(TempBase, SectorOffset);
+    if (EFI_ERROR(Status))
+    {
+        goto DO;
+    }
+
+
+    TempOffset = SectorOffset;
+    TempLength = Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum);
+
+    Status = WriteAfterErase(TempBase, TempOffset, Buffer, TempLength);
+    if (EFI_ERROR(Status))
+    {
+        goto DO;
+    }
+
+
+    Buffer = Buffer + TempLength + Length;
+    TempOffset = Offset + Length;
+    TempLength = SectorOffset + (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum) - TempOffset;
+
+    Status = WriteAfterErase(TempBase, TempOffset, Buffer, TempLength);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: %r!\n", __FUNCTION__,__LINE__,Status));
+        goto DO;
+    }
+
+    (void)gBS->FreePool((VOID *)StaticBuffer);
+    return EFI_SUCCESS;
+
+DO:
+    (void)gBS->FreePool((VOID *)StaticBuffer);
+    return Status;
+}
+
+
+EFI_STATUS
+EFIAPI Erase(
+   IN UNI_NOR_FLASH_PROTOCOL   *This,
+   IN UINT32                   Offset,
+   IN UINT32                   Length
+  )
+{
+    EFI_STATUS  Status = EFI_SUCCESS;
+    UINT32 Sectors;
+    UINT32 TempLength;
+    UINT32 TempBase;
+    UINT32 Loop;
+
+
+    if (Offset + Length > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Exceed the Flash Size!\n", __FUNCTION__,__LINE__));
+        return EFI_ABORTED;
+    }
+    if (0 == Length)
+    {
+        return EFI_SUCCESS;
+    }
+
+
+    Sectors = ((Offset + Length - 1) / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - (Offset / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) + 1;
+    TempBase = gIndex.Base;
+
+    //if Offset >= gOneFlashSize,modify base
+    if(0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+    {
+        TempBase +=  gFlashInfo[gIndex.InfIndex].SingleChipSize * (Offset/gFlashInfo[gIndex.InfIndex].SingleChipSize);
+        Offset = Offset - (Offset & gFlashInfo[gIndex.InfIndex].SingleChipSize);
+    }
+
+    for (Loop = 0; Loop <= Sectors; Loop ++)
+    {
+
+        TempLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum));
+
+
+        if (TempLength > Length)
+        {
+            TempLength = Length;
+        }
+
+        Status = FlashSectorErase(TempBase, Offset, TempLength);
+        if (EFI_ERROR(Status))
+        {
+            DEBUG ((EFI_D_ERROR, "[%a]:[%dL]: FlashErase One Sector Error, Status = %r!\n", __FUNCTION__,__LINE__,Status));
+            return Status;
+        }
+
+        Offset += TempLength;
+
+         //if Offset >= gOneFlashSize,modify base
+        if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+        {
+            TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize;
+            Offset = 0;
+        }
+        Length -= TempLength;
+    }
+
+    return Status;
+}
+
+
+EFI_STATUS
+EFIAPI Write(
+  IN UNI_NOR_FLASH_PROTOCOL   *This,
+  IN UINT32                   Offset,
+  IN UINT8                   *Buffer,
+  UINT32                     ulLength
+  )
+{
+    EFI_STATUS  Status;
+    UINT32     TempLength;
+    UINT32       TempBase;
+    UINT32           Loop;
+    UINT32        Sectors;
+
+    if((Offset + ulLength) > (gFlashInfo[gIndex.InfIndex].SingleChipSize * gFlashInfo[gIndex.InfIndex].ParallelNum))
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Exceed the Flash Size!\n", __FUNCTION__,__LINE__));
+        return EFI_INVALID_PARAMETER;
+    }
+    if (0 == ulLength)
+    {
+        return EFI_SUCCESS;
+    }
+
+
+    Sectors = ((Offset + ulLength - 1) / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) - (Offset / (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum)) + 1;
+    TempBase = gIndex.Base;
+
+    //if Offset >= gOneFlashSize,modify base
+    if(0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+    {
+        TempBase +=  gFlashInfo[gIndex.InfIndex].SingleChipSize * (Offset/gFlashInfo[gIndex.InfIndex].SingleChipSize);
+        Offset = Offset - (Offset & gFlashInfo[gIndex.InfIndex].SingleChipSize);
+    }
+
+    for (Loop = 0; Loop <= Sectors; Loop ++)
+    {
+
+        TempLength = gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum - (Offset % (gFlashInfo[gIndex.InfIndex].BlockSize * gFlashInfo[gIndex.InfIndex].ParallelNum));
+
+
+        if (TempLength > ulLength)
+        {
+            TempLength = ulLength;
+        }
+
+
+        if (TRUE == IsNeedToWrite(TempBase, Offset, Buffer, TempLength))
+        {
+            Status = FlashSectorErase(TempBase, Offset, TempLength);
+            if (EFI_ERROR(Status))
+            {
+                DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:FlashErase One Sector Error, Status = %r!\n", __FUNCTION__,__LINE__,Status));
+                return Status;
+            }
+
+
+            Status = WriteAfterErase(TempBase, Offset, Buffer, TempLength);
+            if (EFI_ERROR(Status))
+            {
+                DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:WriteAfterErase Status = %r!\n", __FUNCTION__,__LINE__,Status));
+                return Status;
+            }
+        }
+
+        Offset += TempLength;
+        Buffer += TempLength;
+
+         //if Offset >= gOneFlashSize,modify base
+        if (0 < (Offset / gFlashInfo[gIndex.InfIndex].SingleChipSize))
+        {
+            TempBase += gFlashInfo[gIndex.InfIndex].SingleChipSize;
+            Offset = 0;
+        }
+        ulLength -= TempLength;
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+VOID SetFlashAttributeToUncache(VOID)
+{
+    EFI_CPU_ARCH_PROTOCOL             *gCpu           = NULL;
+    EFI_STATUS Status;
+
+    Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "LocateProtocol gEfiCpuArchProtocolGuid Status = %r !\n", Status));
+    }
+
+    Status = gCpu->SetMemoryAttributes(
+                     gCpu,
+                     PcdGet64(PcdNORFlashBase),
+                     PcdGet32(PcdNORFlashCachableSize),
+                     EFI_MEMORY_UC
+                     );
+
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "gCpu->SetMemoryAttributes Status = %r !\n", Status));
+    }
+
+}
+
+EFI_STATUS
+EFIAPI InitializeFlash (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable)
+{
+    EFI_STATUS Status;
+
+
+    gIndex.Base = (UINT32)PcdGet64(PcdNORFlashBase);
+
+    SetFlashAttributeToUncache();
+    Status = FlashInit(gIndex.Base);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "Init Flash Error !\n"));
+        return Status;
+    }
+    else
+    {
+        DEBUG((EFI_D_ERROR, "Init Flash OK!\n"));
+    }
+
+    Status = gBS->InstallProtocolInterface (
+                            &ImageHandle,
+                            &gUniNorFlashProtocolGuid,
+                            EFI_NATIVE_INTERFACE,
+                            &gUniNorFlash);
+    if(EFI_SUCCESS != Status)
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Install Protocol Interface %r!\n", __FUNCTION__,__LINE__,Status));
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf
new file mode 100644
index 0000000..ef942f2
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = NorFlashDxe
+  FILE_GUID                      = E29977F9-20A4-4551-B0EC-BCE246592E73
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeFlash
+
+[Sources.common]
+  NorFlashDxe.c
+  NorFlashHw.c
+  NorFlashConfig.c
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+  BaseLib
+  DebugLib
+  IoLib
+  SerialPortLib
+  ArmLib
+  CacheMaintenanceLib
+  UefiLib
+  PrintLib
+  PcdLib
+
+  DxeServicesTableLib
+[Guids]
+
+[Protocols]
+  gUniNorFlashProtocolGuid
+  gEfiCpuArchProtocolGuid
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdNORFlashBase
+  gHisiTokenSpaceGuid.PcdNORFlashCachableSize
+
+
+[Depex]
+ TRUE
+
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c
new file mode 100644
index 0000000..3aeaeb9
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.c
@@ -0,0 +1,628 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/IoLib.h>
+#include "NorFlashHw.h"
+
+
+BOOLEAN  gFlashBusy = FALSE;
+FLASH_INDEX gIndex = {
+    0,
+    0,
+    0,
+    0,
+    0,
+    0
+};
+
+
+UINT32 PortReadData (
+    UINT32 Index,
+    UINT32 FlashAddr
+  )
+{
+
+    switch (gFlashInfo[Index].ParallelNum)
+    {
+        case 2:
+            return MmioRead32 (FlashAddr);
+        case 1:
+            return MmioRead16 (FlashAddr);
+
+        default:
+            DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:illegal PortWidth!\n", __FUNCTION__,__LINE__));
+            return 0xffffffff;
+    }
+}
+
+EFI_STATUS
+PortWriteData (
+    UINT32 Index,
+    UINT32 FlashAddr,
+    UINT32 InputData
+  )
+{
+
+    switch (gFlashInfo[Index].ParallelNum)
+    {
+        case 2:
+             MmioWrite32 (FlashAddr, InputData);
+             break;
+        case 1:
+             MmioWrite16 (FlashAddr, InputData);
+             break;
+        default:
+             DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:illegal PortWidth!\n", __FUNCTION__,__LINE__));
+             return EFI_DEVICE_ERROR;
+    }
+    return EFI_SUCCESS;
+}
+
+UINT32 PortAdjustData(
+    UINT32 Index,
+    UINT32 ulInputData
+  )
+{
+
+    switch (gFlashInfo[Index].ParallelNum)
+    {
+        case 2:
+             return ulInputData;
+        case 1:
+             return (0x0000ffff & ulInputData );
+        default:
+            DEBUG((EFI_D_ERROR,"[FLASH_S29GL256N_PortAdjustData]: Error--illegal g_ulFlashS29Gl256NPortWidth!\n\r"));
+            return 0xffffffff;
+    }
+}
+
+
+EFI_STATUS GetCommandIndex(
+    UINT32 Index
+  )
+{
+    UINT32 CommandCount = 0;
+    UINT32 i;
+    UINT8 Flag = 1;
+
+    CommandCount = sizeof(gFlashCommandReset) / sizeof(FLASH_COMMAND_RESET);
+    for(i = 0;i < CommandCount; i ++ )
+    {
+        if(gFlashInfo[Index].CommandType & gFlashCommandReset[i].CommandType)
+        {
+            Flag = 0;
+            gIndex.ReIndex = i;
+            break;
+        }
+    }
+
+    if(Flag)
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Can not Get Reset Command!\n", __FUNCTION__,__LINE__));
+        return EFI_DEVICE_ERROR;
+    }
+
+    CommandCount = sizeof(gFlashCommandId) / sizeof(FLASH_COMMAND_ID);
+    for(Flag = 1,i = 0;i < CommandCount; i ++ )
+    {
+        if(gFlashInfo[Index].CommandType & gFlashCommandId[i].CommandType)
+        {
+            Flag = 0;
+            gIndex.IdIndex = i;
+            break;
+        }
+    }
+
+    if(Flag)
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Can not Get ID Command!\n", __FUNCTION__,__LINE__));
+        return EFI_DEVICE_ERROR;
+    }
+
+    CommandCount = sizeof(gFlashCommandWrite) / sizeof(FLASH_COMMAND_WRITE);
+    for(Flag = 1, i = 0;i < CommandCount; i ++ )
+    {
+        if(gFlashInfo[Index].CommandType & gFlashCommandWrite[i].CommandType)
+        {
+            Flag = 0;
+            gIndex.WIndex = i;
+            break;
+        }
+    }
+
+    if(Flag)
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Can not Get Write Command!\n", __FUNCTION__,__LINE__));
+        return EFI_DEVICE_ERROR;
+    }
+
+    CommandCount = sizeof(gFlashCommandErase) / sizeof(FLASH_COMMAND_ERASE);
+    for(Flag = 1, i = 0;i < CommandCount; i ++ )
+    {
+        if(gFlashInfo[Index].CommandType & gFlashCommandErase[i].CommandType)
+        {
+            Flag = 0;
+            gIndex.WIndex = i;
+            break;
+        }
+    }
+
+    if(Flag)
+    {
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Can not Get Erase Command!\n", __FUNCTION__,__LINE__));
+        return EFI_DEVICE_ERROR;
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+VOID FlashReset(UINT32 Base)
+{
+    (VOID)PortWriteData(gIndex.InfIndex, Base, gFlashCommandReset[gIndex.ReIndex].ResetData);
+    (void)gBS->Stall(20000);
+}
+
+
+void GetManufacturerID(UINT32 Index, UINT32 Base, UINT8 *pbyData)
+{
+
+    UINT32 dwAddr;
+
+    FlashReset(Base);
+
+    dwAddr = Base +  (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep1 << gFlashInfo[Index].ParallelNum);
+    (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep1);
+
+    dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep2 << gFlashInfo[Index].ParallelNum);
+    (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep2);
+
+    dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep3 << gFlashInfo[Index].ParallelNum);
+    (VOID)PortWriteData(Index, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep3);
+
+    *pbyData = (UINT8)PortReadData(Index, Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddress << gFlashInfo[Index].ParallelNum));
+
+    FlashReset(Base);    //must reset to return to the read mode
+}
+
+
+EFI_STATUS FlashInit(UINT32 Base)
+{
+    UINT32 FlashCount = 0;
+    UINT32 i = 0;
+    EFI_STATUS Status;
+    UINT8 Flag = 1;
+    UINT32 TempData = 0;
+    UINT32 TempDev1 = 0;
+    UINT32 TempDev2 = 0;
+    UINT32 TempDev3 = 0;
+    UINT32 dwAddr;
+
+    FlashCount = sizeof(gFlashInfo) / sizeof(NOR_FLASH_INFO_TABLE);
+    for(;i < FlashCount; i ++ )
+    {
+
+        Status = GetCommandIndex(i);
+        if (EFI_ERROR(Status))
+         {
+             DEBUG ((EFI_D_ERROR, "[%a]:[%dL]:Get Command Index %r!\n", __FUNCTION__,__LINE__, Status));
+             return Status;
+         }
+
+        FlashReset(Base);
+
+        dwAddr = Base +  (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep1 << gFlashInfo[i].ParallelNum);
+        (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep1);
+
+        dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep2 << gFlashInfo[i].ParallelNum);
+        (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep2);
+
+        dwAddr = Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddressStep3 << gFlashInfo[i].ParallelNum);
+        (VOID)PortWriteData(i, dwAddr, gFlashCommandId[gIndex.IdIndex].ManuIDDataStep3);
+        //Get manufacture ID
+        TempData = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].ManuIDAddress << gFlashInfo[i].ParallelNum));
+
+        //Get Device Id
+        TempDev1 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress1 << gFlashInfo[i].ParallelNum));
+        TempDev2 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress2 << gFlashInfo[i].ParallelNum));
+        TempDev3 = PortReadData(i, Base + (gFlashCommandId[gIndex.IdIndex].DeviceIDAddress3 << gFlashInfo[i].ParallelNum));
+        DEBUG ((EFI_D_ERROR, "[cdtest]manufactor ID 0x%x!\n",TempData));
+        DEBUG ((EFI_D_ERROR, "[cdtest]Device ID 1 0x%x!\n",TempDev1));
+        DEBUG ((EFI_D_ERROR, "[cdtest]Device ID 2 0x%x!\n",TempDev2));
+        DEBUG ((EFI_D_ERROR, "[cdtest]Device ID 3 0x%x!\n",TempDev3));
+
+        FlashReset(Base);
+
+
+        if((0xffffffff != TempData)
+            && (PortAdjustData(i, gFlashInfo[i].ManufacturerID) == TempData))
+        {
+            if((0xffffffff != TempDev1)
+                && (PortAdjustData(i, gFlashInfo[i].DeviceID1) == TempDev1))
+            {
+                if((0xffffffff != TempDev2)
+                    && (PortAdjustData(i, gFlashInfo[i].DeviceID2) == TempDev2))
+                {
+                    if((0xffffffff != TempDev3)
+                        && (PortAdjustData(i, gFlashInfo[i].DeviceID3) == TempDev3))
+                    {
+                        Flag = 0;
+                        gIndex.InfIndex = i;
+                        break;
+                    }
+                }
+            }
+         }
+    }
+
+    if(Flag)
+    {
+        return EFI_DEVICE_ERROR;
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+static BOOLEAN width8IsAll(
+    const UINT64       Base,
+    const UINT64       Offset,
+    const UINT64       Length,
+    const UINT8        Value
+)
+{
+    UINT64 NewAddr = Base + Offset;
+    UINT64 NewLength = Length;
+    while (NewLength --)
+    {
+        if (*(UINT8 *)(UINTN)NewAddr == Value)
+        {
+            NewAddr ++;
+            continue;
+        }
+        else
+        {
+            return FALSE;
+        }
+    }
+    return TRUE;
+}
+
+
+
+EFI_STATUS BufferWriteCommand(UINTN Base, UINTN Offset, void *pData)
+{
+    UINT32 dwCommAddr;
+    UINT32 *pdwData;
+    UINT16 *pwData;
+    UINT32 dwLoop;
+    UINT32 ulWriteWordCount;
+    UINT32 dwAddr;
+
+    if(gFlashBusy)
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL]:Flash is busy!\n", __FUNCTION__,__LINE__));
+        return EFI_NOT_READY;
+    }
+    gFlashBusy = TRUE;
+
+    if(2 == gFlashInfo[gIndex.InfIndex].ParallelNum)
+    {
+        pdwData = (UINT32 *)pData;
+
+        dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+        (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep1);
+
+        dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+        (VOID)PortWriteData(gIndex.InfIndex, dwAddr,  gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep2);
+
+        //dwAddr = Base + (Offset << gFlashInfo[gIndex.InfIndex].ParallelNum);
+        dwAddr = (UINT32)Base + Offset;
+        (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep3);
+
+
+       ulWriteWordCount = ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << 16) | (gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1);
+       (VOID)PortWriteData(gIndex.InfIndex, dwAddr, ulWriteWordCount);
+
+
+       for (dwLoop = 0; dwLoop < gFlashInfo[gIndex.InfIndex].BufferProgramSize; dwLoop ++)
+       {
+           dwCommAddr = (UINT32)Base + (UINT32)Offset + (dwLoop << gFlashInfo[gIndex.InfIndex].ParallelNum);
+           MmioWrite32 (dwCommAddr, *pdwData);
+           pdwData ++;
+       }
+
+       dwAddr = (UINT32)Base + (UINT32)Offset + ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << gFlashInfo[gIndex.InfIndex].ParallelNum);
+       (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramtoFlash);
+
+
+
+    }
+    else
+    {
+        pwData  = (UINT16 *)pData;
+
+        dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+        (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep1);
+
+        dwAddr = (UINT32)Base + (gFlashCommandWrite[gIndex.WIndex].BufferProgramAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+        (VOID)PortWriteData(gIndex.InfIndex, dwAddr,  gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep2);
+
+        //dwAddr = Base + (Offset << gFlashInfo[gIndex.InfIndex].ParallelNum);
+        dwAddr = (UINT32)Base + Offset;
+        (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramDataStep3);
+
+
+        ulWriteWordCount = gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1;
+        (VOID)PortWriteData(gIndex.InfIndex, dwAddr, ulWriteWordCount);
+
+
+        for (dwLoop = 0; dwLoop < gFlashInfo[gIndex.InfIndex].BufferProgramSize; dwLoop ++)
+        {
+            dwCommAddr = (UINT32)Base + (UINT32)Offset + (dwLoop << gFlashInfo[gIndex.InfIndex].ParallelNum);
+            MmioWrite16 (dwCommAddr, *pwData);
+            pwData ++;
+        }
+
+        dwAddr = (UINT32)Base + (UINT32)Offset + ((gFlashInfo[gIndex.InfIndex].BufferProgramSize - 1) << gFlashInfo[gIndex.InfIndex].ParallelNum);
+        (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandWrite[gIndex.WIndex].BufferProgramtoFlash);
+
+    }
+
+    (void)gBS->Stall(200);
+
+    gFlashBusy = FALSE;
+    return EFI_SUCCESS;
+
+}
+
+
+EFI_STATUS SectorEraseCommand(UINTN Base, UINTN Offset)
+{
+    UINT32 dwAddr;
+
+    if(gFlashBusy)
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL]:Flash is busy!\n", __FUNCTION__,__LINE__));
+        return EFI_NOT_READY;
+    }
+
+    gFlashBusy = TRUE;
+
+    dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep1 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+    (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep1);
+
+    dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep2 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+    (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep2);
+
+    dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep3 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+    (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep3);
+
+    dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep4 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+    (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep4);
+
+    dwAddr = (UINT32)Base + (gFlashCommandErase[gIndex.EIndex].SectorEraseAddressStep5 << gFlashInfo[gIndex.InfIndex].ParallelNum);
+    (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep5);
+
+    dwAddr = (UINT32)Base + Offset;
+    (VOID)PortWriteData(gIndex.InfIndex, dwAddr, gFlashCommandErase[gIndex.EIndex].SectorEraseDataStep6);
+
+    (void)gBS->Stall(500000);
+
+    gFlashBusy = FALSE;
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS CompleteCheck(UINT32 Base, UINT32 Offset, void *pData, UINT32 Length)
+{
+    UINT32 dwTestAddr;
+    UINT32 dwTestData;
+    UINT32 dwTemp = 0;
+    UINT32 dwTemp1 = 0;
+    UINT32 i;
+    UINT32 dwTimeOut = 3000000;
+
+    if(gFlashBusy)
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL]:Flash is busy!\n", __FUNCTION__,__LINE__));
+        return EFI_NOT_READY;
+    }
+    gFlashBusy = TRUE;
+
+    if(2 == gFlashInfo[gIndex.InfIndex].ParallelNum)
+    {
+        dwTestAddr = Base + Offset + Length - sizeof(UINT32);
+        dwTestData = *((UINT32 *)((UINT8 *)pData + Length - sizeof(UINT32)));
+
+        while(dwTimeOut--)
+        {
+            dwTemp1 = MmioRead32 (dwTestAddr);
+            if (dwTestData == dwTemp1)
+            {
+                dwTemp = MmioRead32 (dwTestAddr);
+                dwTemp1 = MmioRead32 (dwTestAddr);
+                if ((dwTemp == dwTemp1) && (dwTestData == dwTemp1))
+                {
+                    gFlashBusy = FALSE;
+                    return EFI_SUCCESS;
+                }
+            }
+
+            (void)gBS->Stall(1);
+        }
+
+        if((UINT16)(dwTemp1 >> 16) != (UINT16)(dwTestData >> 16))
+        {
+            DEBUG((EFI_D_ERROR, "CompleteCheck ERROR: chip1 address %x, buffer %x, flash %x!\n", Offset, dwTestData, dwTemp1));
+        }
+        if((UINT16)(dwTemp1) != (UINT16)(dwTestData))
+        {
+            DEBUG((EFI_D_ERROR, "CompleteCheck ERROR: chip2 address %x, buffer %x, flash %x!\n", Offset, dwTestData, dwTemp1));
+        }
+    }
+    else
+    {
+        dwTestAddr = Base + Offset + Length - sizeof(UINT16);
+        dwTestData = *((UINT16 *)((UINT8 *)pData + Length - sizeof(UINT16)));
+
+        while(dwTimeOut--)
+        {
+            dwTemp1 = MmioRead16 (dwTestAddr);
+            if (dwTestData == dwTemp1)
+            {
+                dwTemp = MmioRead16 (dwTestAddr);
+                dwTemp1 = MmioRead16 (dwTestAddr);
+                if ((dwTemp == dwTemp1) && (dwTestData == dwTemp1))
+                {
+                    gFlashBusy = FALSE;
+                    return EFI_SUCCESS;
+                }
+            }
+
+            (void)gBS->Stall(1);
+        }
+    }
+
+    for(i = 0; i < 5; i ++)
+    {
+        DEBUG((EFI_D_ERROR, "CompleteCheck ERROR: flash %x\n",PortReadData(gIndex.InfIndex, dwTestAddr)));
+    }
+
+    FlashReset(Base);
+
+    gFlashBusy = FALSE;
+    DEBUG((EFI_D_ERROR, "CompleteCheck ERROR: timeout address %x, buffer %x, flash %x\n", Offset, dwTestData, dwTemp1));
+    return EFI_TIMEOUT;
+}
+
+EFI_STATUS IsNeedToWrite(
+    IN  UINT32         Base,
+    IN  UINT32       Offset,
+    IN  UINT8       *Buffer,
+    IN  UINT32       Length
+  )
+{
+    UINTN NewAddr = Base + Offset;
+    UINT8 FlashData = 0;
+    UINT8 BufferData = 0;
+
+    for(; Length > 0; Length --)
+    {
+        BufferData = *Buffer;
+        //lint -epn -e511
+        FlashData = *(UINT8 *)NewAddr;
+        if (BufferData != FlashData)
+        {
+            return TRUE;
+        }
+        NewAddr ++;
+        Buffer ++;
+    }
+
+    return FALSE;
+}
+
+
+EFI_STATUS BufferWrite(UINT32 Offset, void *pData, UINT32 Length)
+{
+    EFI_STATUS Status;
+    UINT32 dwLoop;
+    UINT32 Retry = 3;
+
+    if (FALSE == IsNeedToWrite(gIndex.Base, Offset, (UINT8 *)pData, Length))
+    {
+        return EFI_SUCCESS;
+    }
+
+    do
+    {
+        (void)BufferWriteCommand(gIndex.Base, Offset, pData);
+        Status = CompleteCheck(gIndex.Base, Offset, pData, Length);
+
+
+        if (EFI_SUCCESS == Status)
+        {
+            for (dwLoop = 0; dwLoop < Length; dwLoop ++)
+            {
+                if (*(UINT8 *)(UINTN)(gIndex.Base + Offset + dwLoop) != *((UINT8 *)pData + dwLoop))
+                {
+                    DEBUG((EFI_D_ERROR, "Flash_WriteUnit ERROR: address %x, buffer %x, flash %x\n", Offset, *((UINT8 *)pData + dwLoop), *(UINT8 *)(UINTN)(gIndex.Base + Offset + dwLoop)));
+                    Status = EFI_ABORTED;
+                    continue;
+                }
+            }
+        }
+        else
+        {
+            DEBUG((EFI_D_ERROR, "Flash_WriteUnit ERROR: complete check failed, %r\n", Status));
+            continue;
+        }
+    } while ((Retry--) && EFI_ERROR(Status));
+
+    return Status;
+}
+
+
+EFI_STATUS SectorErase(UINT32 Base, UINT32 Offset)
+{
+    UINT8 gTemp[FLASH_MAX_UNIT];
+    UINT64 dwLoop = FLASH_MAX_UNIT - 1;
+    UINT32 Retry = 3;
+    EFI_STATUS Status;
+
+    do
+    {
+        gTemp[dwLoop] = 0xFF;
+    }while (dwLoop --);
+
+    do
+    {
+        (void)SectorEraseCommand(Base, Offset);
+        Status = CompleteCheck(Base, Offset, (void *)gTemp, FLASH_MAX_UNIT);
+
+
+        if (EFI_SUCCESS == Status)
+        {
+
+            if (width8IsAll(Base,Offset - (Offset % gFlashInfo[gIndex.InfIndex].BlockSize), gFlashInfo[gIndex.InfIndex].BlockSize, 0xFF))
+            {
+                return EFI_SUCCESS;
+            }
+            else
+            {
+                DEBUG((EFI_D_ERROR, "Flash_SectorErase ERROR: not all address equal 0xFF\n"));
+
+                Status = EFI_ABORTED;
+                continue;
+            }
+        }
+        else
+        {
+            DEBUG((EFI_D_ERROR, "Flash_SectorErase ERROR: complete check failed, %r\n", Status));
+            continue;
+        }
+    }while ((Retry--) && EFI_ERROR(Status));
+
+    if(Retry)
+    {
+        //do nothing for pclint
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h
new file mode 100644
index 0000000..36c0c9e
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashHw.h
@@ -0,0 +1,116 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _NOR_FLASH_HW_H_
+#define _NOR_FLASH_HW_H_
+
+#include <Uefi/UefiBaseType.h>
+
+
+#define FOUR_BYTE_UNIT    4
+#define FLASH_MAX_UNIT    4
+
+#define FLASH_DEVICE_NUM  0x10
+
+
+
+typedef struct {
+    UINT32 ManufacturerID;
+    UINT32 DeviceID1;
+    UINT32 DeviceID2;
+    UINT32 DeviceID3;
+    UINT8  ParallelNum;
+    UINT32 SingleChipSize;
+    UINT32 BlockSize;
+    UINT32 BufferProgramSize;
+    UINT32 CommandType;
+}NOR_FLASH_INFO_TABLE;
+
+/*Define Command Address And Data*/
+/*reset*/
+typedef struct {
+    UINT32 CommandType;
+    UINT32 ResetData;
+}FLASH_COMMAND_RESET;
+
+/*manufacture ID & Device ID*/
+typedef struct {
+    UINT32 CommandType;
+    UINT32 ManuIDAddressStep1;
+    UINT32 ManuIDDataStep1;
+    UINT32 ManuIDAddressStep2;
+    UINT32 ManuIDDataStep2;
+    UINT32 ManuIDAddressStep3;
+    UINT32 ManuIDDataStep3;
+    UINT32 ManuIDAddress;
+
+    UINT32 DeviceIDAddress1;
+    UINT32 DeviceIDAddress2;
+    UINT32 DeviceIDAddress3;
+}FLASH_COMMAND_ID;
+
+/*Write Buffer*/
+typedef struct {
+    UINT32 CommandType;
+    UINT32 BufferProgramAddressStep1;
+    UINT32 BufferProgramDataStep1;
+    UINT32 BufferProgramAddressStep2;
+    UINT32 BufferProgramDataStep2;
+    UINT32 BufferProgramDataStep3;
+    UINT32 BufferProgramtoFlash;
+}FLASH_COMMAND_WRITE;
+
+/*erase*/
+typedef struct {
+    UINT32 CommandType;
+    UINT32 SectorEraseAddressStep1;
+    UINT32 SectorEraseDataStep1;
+    UINT32 SectorEraseAddressStep2;
+    UINT32 SectorEraseDataStep2;
+    UINT32 SectorEraseAddressStep3;
+    UINT32 SectorEraseDataStep3;
+    UINT32 SectorEraseAddressStep4;
+    UINT32 SectorEraseDataStep4;
+    UINT32 SectorEraseAddressStep5;
+    UINT32 SectorEraseDataStep5;
+    UINT32 SectorEraseDataStep6;
+}FLASH_COMMAND_ERASE;
+
+
+typedef struct {
+    UINT32 Base;
+    UINT32 InfIndex;
+    UINT32 ReIndex;
+    UINT32 IdIndex;
+    UINT32 WIndex;
+    UINT32 EIndex;
+}FLASH_INDEX;
+
+
+extern EFI_STATUS FlashInit(UINT32 Base);
+extern EFI_STATUS SectorErase(UINT32 Base, UINT32 Offset);
+extern EFI_STATUS BufferWrite(UINT32 Offset, void *pData, UINT32 Length);
+extern EFI_STATUS IsNeedToWrite(UINT32 Base, UINT32 Offset, UINT8 *Buffer, UINT32 Length);
+
+
+extern NOR_FLASH_INFO_TABLE gFlashInfo[FLASH_DEVICE_NUM];
+extern FLASH_COMMAND_RESET gFlashCommandReset[FLASH_DEVICE_NUM];
+extern FLASH_COMMAND_ID gFlashCommandId[FLASH_DEVICE_NUM];
+extern FLASH_COMMAND_WRITE gFlashCommandWrite[FLASH_DEVICE_NUM];
+extern FLASH_COMMAND_ERASE gFlashCommandErase[FLASH_DEVICE_NUM];
+extern FLASH_INDEX gIndex;
+
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
new file mode 100644
index 0000000..a970da6
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
@@ -0,0 +1,1651 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution.  The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#include <Uefi.h>
+#include <Protocol/EmbeddedGpio.h>
+#include <Guid/EventGroup.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/OemMiscLib.h>
+
+#include "PciHostBridge.h"
+
+UINTN RootBridgeNumber[PCIE_MAX_HOSTBRIDGE] = { PCIE_MAX_ROOTBRIDGE,PCIE_MAX_ROOTBRIDGE };
+
+UINT64 RootBridgeAttribute[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+    { //Host Bridge0
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+    },
+    { //Host Bridge1
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+            EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+    }
+    };
+
+EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+  { //Host Bridge0
+  /* Port 0 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A03),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+  /* Port 1 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A04),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+  /* Port 2 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A05),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+  /* Port 3 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A06),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+    /* Port 4 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A07),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+    /* Port 5 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A08),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+    /* Port 6 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A09),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+    /* Port 7 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A0A),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    }
+},
+{ // Host Bridge1
+  /* Port 0 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A0B),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+  /* Port 1 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A0C),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+  /* Port 2 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A0D),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+  /* Port 3 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A0E),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+   /* Port 4 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A0F),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+    /* Port 5 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A10),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+    /* Port 6 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A11),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    },
+    /* Port 7 */
+    {
+      {
+        {
+          ACPI_DEVICE_PATH,
+          ACPI_DP,
+          {
+            (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+            (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+          }
+        },
+        EISA_PNP_ID(0x0A12),
+        0
+      },
+
+      {
+        END_DEVICE_PATH_TYPE,
+        END_ENTIRE_DEVICE_PATH_SUBTYPE,
+        {
+          END_DEVICE_PATH_LENGTH,
+          0
+        }
+      }
+    }
+  }
+};
+
+EFI_HANDLE mDriverImageHandle;
+
+PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
+  PCI_HOST_BRIDGE_SIGNATURE,  // Signature
+  NULL,                       // HostBridgeHandle
+  0,                          // RootBridgeNumber
+  {NULL, NULL},               // Head
+  FALSE,                      // ResourceSubiteed
+  TRUE,                       // CanRestarted
+  {
+    NotifyPhase,
+    GetNextRootBridge,
+    GetAttributes,
+    StartBusEnumeration,
+    SetBusNumbers,
+    SubmitResources,
+    GetProposedResources,
+    PreprocessController
+  }
+};
+
+/**
+  Entry point of this driver
+
+  @param ImageHandle     Handle of driver image
+  @param SystemTable     Point to EFI_SYSTEM_TABLE
+
+  @retval EFI_OUT_OF_RESOURCES  Can not allocate memory resource
+  @retval EFI_DEVICE_ERROR      Can not install the protocol instance
+  @retval EFI_SUCCESS           Success to initialize the Pci host bridge.
+**/
+EFI_STATUS
+EFIAPI
+InitializePciHostBridge (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  UINTN                       Loop1;
+  UINTN                       Loop2;
+  PCI_HOST_BRIDGE_INSTANCE    *HostBridge = NULL;
+  PCI_ROOT_BRIDGE_INSTANCE    *PrivateData;
+  UINT32       PcieRootBridgeMask;
+
+  if (!OemIsMpBoot())
+  {
+    PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
+  }
+  else
+  {
+    PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
+  }
+
+  mDriverImageHandle = ImageHandle;
+  //
+  // Create Host Bridge Device Handle
+  //
+  //Each Host Bridge have 8 Root Bridges max, every bits of 0xFF(8 bit) stands for the according PCIe Port
+  //is enable or not
+  for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) {
+    if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) {
+      continue;
+    }
+
+
+    HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
+    if (HostBridge == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+
+    HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];
+    InitializeListHead (&HostBridge->Head);
+
+    Status = gBS->InstallMultipleProtocolInterfaces (
+                  &HostBridge->HostBridgeHandle,
+                  &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
+                  NULL
+                  );
+    if (EFI_ERROR (Status)) {
+      FreePool (HostBridge);
+      return EFI_DEVICE_ERROR;
+    }
+
+    //
+    // Create Root Bridge Device Handle in this Host Bridge
+    //
+    for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
+      if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) {
+        continue;
+      }
+
+      PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));
+      if (PrivateData == NULL) {
+        FreePool (HostBridge);
+        return EFI_OUT_OF_RESOURCES;
+      }
+      PrivateData->Port = Loop2;
+      PrivateData->SocType = PcdGet32(Pcdsoctype);
+      PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
+      PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
+
+      (VOID)RootBridgeConstructor (
+           &PrivateData->Io,
+           HostBridge->HostBridgeHandle,
+           RootBridgeAttribute[Loop1][Loop2],
+           &mResAppeture[Loop1][Loop2],
+           Loop1
+      );
+
+      Status = gBS->InstallMultipleProtocolInterfaces(
+                      &PrivateData->Handle,
+                      &gEfiDevicePathProtocolGuid,      PrivateData->DevicePath,
+                      &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
+                      NULL
+                      );
+      if (EFI_ERROR (Status)) {
+        (VOID)gBS->UninstallMultipleProtocolInterfaces (
+                HostBridge->HostBridgeHandle,
+                &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
+                NULL
+                );
+        FreePool(PrivateData);
+        FreePool (HostBridge);
+        return EFI_DEVICE_ERROR;
+      }
+      // PCI  Memory Space
+      Status = gDS->AddMemorySpace (
+             EfiGcdMemoryTypeMemoryMappedIo,
+             mResAppeture[Loop1][Loop2] .MemBase,
+             mResAppeture[Loop1][Loop2] .MemLimit -mResAppeture[Loop1][Loop2] .MemBase + 1,
+             0
+      );
+      if (EFI_ERROR (Status)) {
+        DEBUG((EFI_D_ERROR,"PCIE AddMemorySpace Error\n"));
+      }
+      InsertTailList (&HostBridge->Head, &PrivateData->Link);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+NotifyAllocateMemResources(
+ IN PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance,
+ IN PCI_RESOURCE_TYPE                     Index,
+ IN OUT UINT64                            *AllocatedLenMem
+)
+{
+  EFI_PHYSICAL_ADDRESS                  BaseAddress;
+  EFI_STATUS                            ReturnStatus;
+  UINT64                                AddrLen;
+  UINTN                                 BitsOfAlignment;
+
+  AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+  PCIE_DEBUG("Addrlen:%llx\n", AddrLen);
+  // Get the number of '1' in Alignment.
+  BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
+
+  BaseAddress = (RootBridgeInstance->MemBase + *AllocatedLenMem +
+                       RootBridgeInstance->ResAllocNode[Index].Alignment)
+                        & ~(RootBridgeInstance->ResAllocNode[Index].Alignment);
+  if ((BaseAddress + AddrLen - 1) > RootBridgeInstance->MemLimit) {
+          ReturnStatus = EFI_OUT_OF_RESOURCES;
+          RootBridgeInstance->ResAllocNode[Index].Length = 0;
+          return ReturnStatus;
+  }
+
+  PCIE_DEBUG("(P)Mem32/64 request memory at:%llx\n", BaseAddress);
+  ReturnStatus = gDS->AllocateMemorySpace (
+                     EfiGcdAllocateAddress,
+                     EfiGcdMemoryTypeMemoryMappedIo,
+                     BitsOfAlignment,
+                     AddrLen,
+                     &BaseAddress,
+                     mDriverImageHandle,
+                     NULL
+                 );
+
+  if (!EFI_ERROR (ReturnStatus)) {
+     // We were able to allocate the PCI memory
+     RootBridgeInstance->ResAllocNode[Index].Base   = (UINTN)BaseAddress;
+     RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
+     *AllocatedLenMem += AddrLen;
+     PCIE_DEBUG("(P)Mem32/64 resource allocated:%llx\n", BaseAddress);
+
+  } else {
+      // Not able to allocate enough PCI memory
+      if (ReturnStatus != EFI_OUT_OF_RESOURCES) {
+        RootBridgeInstance->ResAllocNode[Index].Length = 0;
+      }
+    }
+  return ReturnStatus;
+}
+
+EFI_STATUS
+EFIAPI
+NotifyAllocateResources(
+ IN PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance
+)
+{
+  EFI_STATUS                            ReturnStatus;
+  LIST_ENTRY                            *List;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+  PCI_RESOURCE_TYPE                     Index;
+
+  ReturnStatus = EFI_SUCCESS;
+  List = HostBridgeInstance->Head.ForwardLink;
+
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+
+    UINT64 AllocatedLenMem = 0;
+    for (Index = TypeIo; Index < TypeBus; Index++) {
+      if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+        if(Index == TypeIo) {
+          PCIE_DEBUG("NOT SUPPOER IO RESOURCES ON THIS PLATFORM\n");
+        } else if ((Index >= TypeMem32) && (Index <= TypePMem64)) {
+          ReturnStatus = NotifyAllocateMemResources(RootBridgeInstance,Index,&AllocatedLenMem);
+        } else {
+               ASSERT (FALSE);
+        }
+      }
+    }
+
+    List = List->ForwardLink;
+  }
+
+  return ReturnStatus;
+}
+
+EFI_STATUS
+EFIAPI
+NotifyFreeResources(
+  IN PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance
+)
+{
+  EFI_STATUS                            ReturnStatus;
+  LIST_ENTRY                            *List;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+  PCI_RESOURCE_TYPE                     Index;
+  UINT64                                AddrLen;
+  EFI_PHYSICAL_ADDRESS                  BaseAddress;
+
+  ReturnStatus = EFI_SUCCESS;
+  List = HostBridgeInstance->Head.ForwardLink;
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    for (Index = TypeIo; Index < TypeBus; Index++) {
+      if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
+        AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+        BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
+
+        if(Index <= TypePMem64){
+          ReturnStatus = gDS->FreeMemorySpace (BaseAddress, AddrLen);
+        }else{
+          ASSERT (FALSE);
+        }
+
+        RootBridgeInstance->ResAllocNode[Index].Type      = Index;
+        RootBridgeInstance->ResAllocNode[Index].Base      = 0;
+        RootBridgeInstance->ResAllocNode[Index].Length    = 0;
+        RootBridgeInstance->ResAllocNode[Index].Status    = ResNone;
+      }
+    }
+
+    List = List->ForwardLink;
+  }
+
+  HostBridgeInstance->ResourceSubmited = FALSE;
+  HostBridgeInstance->CanRestarted     = TRUE;
+  return ReturnStatus;
+
+}
+
+VOID
+EFIAPI
+NotifyBeginEnumeration(
+  IN PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance
+)
+{
+  LIST_ENTRY                            *List;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+  PCI_RESOURCE_TYPE                     Index;
+
+  //
+  // Reset the Each Root Bridge
+  //
+  List = HostBridgeInstance->Head.ForwardLink;
+
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    for (Index = TypeIo; Index < TypeMax; Index++) {
+      RootBridgeInstance->ResAllocNode[Index].Type      = Index;
+      RootBridgeInstance->ResAllocNode[Index].Base      = 0;
+      RootBridgeInstance->ResAllocNode[Index].Length    = 0;
+      RootBridgeInstance->ResAllocNode[Index].Status    = ResNone;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  HostBridgeInstance->ResourceSubmited = FALSE;
+  HostBridgeInstance->CanRestarted     = TRUE;
+}
+
+/**
+   These are the notifications from the PCI bus driver that it is about to enter a certain
+   phase of the PCI enumeration process.
+
+   This member function can be used to notify the host bridge driver to perform specific actions,
+   including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
+   Eight notification points are defined at this time. See belows:
+   EfiPciHostBridgeBeginEnumeration       Resets the host bridge PCI apertures and internal data
+                                          structures. The PCI enumerator should issue this notification
+                                          before starting a fresh enumeration process. Enumeration cannot
+                                          be restarted after sending any other notification such as
+                                          EfiPciHostBridgeBeginBusAllocation.
+   EfiPciHostBridgeBeginBusAllocation     The bus allocation phase is about to begin. No specific action is
+                                          required here. This notification can be used to perform any
+                                          chipset-specific programming.
+   EfiPciHostBridgeEndBusAllocation       The bus allocation and bus programming phase is complete. No
+                                          specific action is required here. This notification can be used to
+                                          perform any chipset-specific programming.
+   EfiPciHostBridgeBeginResourceAllocation
+                                          The resource allocation phase is about to begin. No specific
+                                          action is required here. This notification can be used to perform
+                                          any chipset-specific programming.
+   EfiPciHostBridgeAllocateResources      Allocates resources per previously submitted requests for all the PCI
+                                          root bridges. These resource settings are returned on the next call to
+                                          GetProposedResources(). Before calling NotifyPhase() with a Phase of
+                                          EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
+                                          for gathering I/O and memory requests for
+                                          all the PCI root bridges and submitting these requests using
+                                          SubmitResources(). This function pads the resource amount
+                                          to suit the root bridge hardware, takes care of dependencies between
+                                          the PCI root bridges, and calls the Global Coherency Domain (GCD)
+                                          with the allocation request. In the case of padding, the allocated range
+                                          could be bigger than what was requested.
+   EfiPciHostBridgeSetResources           Programs the host bridge hardware to decode previously allocated
+                                          resources (proposed resources) for all the PCI root bridges. After the
+                                          hardware is programmed, reassigning resources will not be supported.
+                                          The bus settings are not affected.
+   EfiPciHostBridgeFreeResources          Deallocates resources that were previously allocated for all the PCI
+                                          root bridges and resets the I/O and memory apertures to their initial
+                                          state. The bus settings are not affected. If the request to allocate
+                                          resources fails, the PCI enumerator can use this notification to
+                                          deallocate previous resources, adjust the requests, and retry
+                                          allocation.
+   EfiPciHostBridgeEndResourceAllocation  The resource allocation phase is completed. No specific action is
+                                          required here. This notification can be used to perform any chipsetspecific
+                                          programming.
+
+   @param[in] This                The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+   @param[in] Phase               The phase during enumeration
+
+   @retval EFI_NOT_READY          This phase cannot be entered at this time. For example, this error
+                                  is valid for a Phase of EfiPciHostBridgeAllocateResources if
+                                  SubmitResources() has not been called for one or more
+                                  PCI root bridges before this call
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error. This error is valid
+                                  for a Phase of EfiPciHostBridgeSetResources.
+   @retval EFI_INVALID_PARAMETER  Invalid phase parameter
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+                                  This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
+                                  previously submitted resource requests cannot be fulfilled or
+                                  were only partially fulfilled.
+   @retval EFI_SUCCESS            The notification was accepted without any errors.
+
+**/
+EFI_STATUS
+EFIAPI
+NotifyPhase(
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase
+  )
+{
+  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
+  EFI_STATUS                            ReturnStatus;
+
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  ReturnStatus = EFI_SUCCESS;
+
+  switch (Phase) {
+
+  case EfiPciHostBridgeBeginEnumeration:
+  PCIE_DEBUG("Case EfiPciHostBridgeBeginEnumeration\n");
+    if (HostBridgeInstance->CanRestarted) {
+      NotifyBeginEnumeration(HostBridgeInstance);
+    } else {
+      //
+      // Can not restart
+      //
+      return EFI_NOT_READY;
+    }
+    break;
+
+  case EfiPciHostBridgeEndEnumeration:
+    PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n");
+    break;
+
+  case EfiPciHostBridgeBeginBusAllocation:
+    PCIE_DEBUG("Case EfiPciHostBridgeBeginBusAllocation\n");
+    //
+    // No specific action is required here, can perform any chipset specific programing
+    //
+
+    HostBridgeInstance->CanRestarted = FALSE;
+    break;
+
+  case EfiPciHostBridgeEndBusAllocation:
+    PCIE_DEBUG("Case EfiPciHostBridgeEndBusAllocation\n");
+    //
+    // No specific action is required here, can perform any chipset specific programing
+    //
+    break;
+
+  case EfiPciHostBridgeBeginResourceAllocation:
+    PCIE_DEBUG("Case EfiPciHostBridgeBeginResourceAllocation\n");
+    //
+    // No specific action is required here, can perform any chipset specific programing
+    //
+    break;
+
+  case EfiPciHostBridgeAllocateResources:
+    PCIE_DEBUG("Case EfiPciHostBridgeAllocateResources\n");
+
+    if (HostBridgeInstance->ResourceSubmited) {
+      //
+      // Take care of the resource dependencies between the root bridges
+      //
+     ReturnStatus = NotifyAllocateResources(HostBridgeInstance);
+    } else {
+      return EFI_NOT_READY;
+    }
+    //break;
+
+  case EfiPciHostBridgeSetResources:
+    PCIE_DEBUG("Case EfiPciHostBridgeSetResources\n");
+    break;
+
+  case EfiPciHostBridgeFreeResources:
+    PCIE_DEBUG("Case EfiPciHostBridgeFreeResources\n");
+
+    ReturnStatus = NotifyFreeResources(HostBridgeInstance);
+    break;
+
+  case EfiPciHostBridgeEndResourceAllocation:
+    PCIE_DEBUG("Case EfiPciHostBridgeEndResourceAllocation\n");
+    HostBridgeInstance->CanRestarted = FALSE;
+    break;
+
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return ReturnStatus;
+}
+
+/**
+   Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
+
+   This function is called multiple times to retrieve the device handles of all the PCI root bridges that
+   are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
+   root bridges. On each call, the handle that was returned by the previous call is passed into the
+   interface, and on output the interface returns the device handle of the next PCI root bridge. The
+   caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+   for that root bridge. When there are no more PCI root bridges to report, the interface returns
+   EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
+   are returned by this function.
+   For D945 implementation, there is only one root bridge in PCI host bridge.
+
+   @param[in]       This              The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+   @param[in, out]  RootBridgeHandle  Returns the device handle of the next PCI root bridge.
+
+   @retval EFI_SUCCESS            If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
+                                  specific Host bridge and return EFI_SUCCESS.
+   @retval EFI_NOT_FOUND          Can not find the any more root bridge in specific host bridge.
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not an EFI_HANDLE that was
+                                  returned on a previous call to GetNextRootBridge().
+**/
+EFI_STATUS
+EFIAPI
+GetNextRootBridge(
+  IN       EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN OUT   EFI_HANDLE                                       *RootBridgeHandle
+  )
+{
+  BOOLEAN                               NoRootBridge;
+  LIST_ENTRY                            *List;
+  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+
+  NoRootBridge = TRUE;
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List = HostBridgeInstance->Head.ForwardLink;
+
+
+  while (List != &HostBridgeInstance->Head) {
+    NoRootBridge = FALSE;
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (*RootBridgeHandle == NULL) {
+      //
+      // Return the first Root Bridge Handle of the Host Bridge
+      //
+      *RootBridgeHandle = RootBridgeInstance->Handle;
+      return EFI_SUCCESS;
+    } else {
+      if (*RootBridgeHandle == RootBridgeInstance->Handle) {
+        //
+        // Get next if have
+        //
+        List = List->ForwardLink;
+        if (List!=&HostBridgeInstance->Head) {
+          RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+          *RootBridgeHandle = RootBridgeInstance->Handle;
+          return EFI_SUCCESS;
+        } else {
+          return EFI_NOT_FOUND;
+        }
+      }
+    }
+
+    List = List->ForwardLink;
+  } //end while
+
+  if (NoRootBridge) {
+    return EFI_NOT_FOUND;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+}
+
+/**
+   Returns the allocation attributes of a PCI root bridge.
+
+   The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
+   from one PCI root bridge to another. These attributes are different from the decode-related
+   attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
+   RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
+   handles of all the root bridges that are associated with this host bridge must be obtained by calling
+   GetNextRootBridge(). The attributes are static in the sense that they do not change during or
+   after the enumeration process. The hardware may provide mechanisms to change the attributes on
+   the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
+   installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
+   "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
+   For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
+   include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
+   prefetchable memory.
+      Attribute                                 Description
+   ------------------------------------         ----------------------------------------------------------------------
+   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM         If this bit is set, then the PCI root bridge does not support separate
+                                                windows for nonprefetchable and prefetchable memory. A PCI bus
+                                                driver needs to include requests for prefetchable memory in the
+                                                nonprefetchable memory pool.
+
+   EFI_PCI_HOST_BRIDGE_MEM64_DECODE             If this bit is set, then the PCI root bridge supports 64-bit memory
+                                                windows. If this bit is not set, the PCI bus driver needs to include
+                                                requests for a 64-bit memory address in the corresponding 32-bit
+                                                memory pool.
+
+   @param[in]   This               The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+   @param[in]   RootBridgeHandle   The device handle of the PCI root bridge in which the caller is interested. Type
+                                   EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+   @param[out]  Attributes         The pointer to attribte of root bridge, it is output parameter
+
+   @retval EFI_INVALID_PARAMETER   Attribute pointer is NULL
+   @retval EFI_INVALID_PARAMETER   RootBridgehandle is invalid.
+   @retval EFI_SUCCESS             Success to get attribute of interested root bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+GetAttributes(
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN  EFI_HANDLE                                       RootBridgeHandle,
+  OUT UINT64                                           *Attributes
+  )
+{
+  LIST_ENTRY                            *List;
+  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+
+  if (Attributes == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List = HostBridgeInstance->Head.ForwardLink;
+
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      *Attributes = RootBridgeInstance->RootBridgeAttrib;
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  //
+  // RootBridgeHandle is not an EFI_HANDLE
+  // that was returned on a previous call to GetNextRootBridge()
+  //
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+   Sets up the specified PCI root bridge for the bus enumeration process.
+
+   This member function sets up the root bridge for bus enumeration and returns the PCI bus range
+   over which the search should be performed in ACPI 2.0 resource descriptor format.
+
+   @param[in]   This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+   @param[in]   RootBridgeHandle  The PCI Root Bridge to be set up.
+   @param[out]  Configuration     Pointer to the pointer to the PCI bus resource descriptor.
+
+   @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
+   @retval EFI_OUT_OF_RESOURCES  Fail to allocate ACPI resource descriptor tag.
+   @retval EFI_SUCCESS           Sucess to allocate ACPI resource descriptor.
+
+**/
+EFI_STATUS
+EFIAPI
+StartBusEnumeration(
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN  EFI_HANDLE                                       RootBridgeHandle,
+  OUT VOID                                             **Configuration
+  )
+{
+  LIST_ENTRY                            *List;
+  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+  VOID                                  *Buffer;
+  UINT8                                 *Temp;
+  UINT64                                BusStart;
+  UINT64                                BusEnd;
+
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List = HostBridgeInstance->Head.ForwardLink;
+
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      //
+      // Set up the Root Bridge for Bus Enumeration
+      //
+      BusStart = RootBridgeInstance->BusBase;
+      BusEnd   = RootBridgeInstance->BusLimit;
+      //
+      // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
+      //
+
+      Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
+      if (Buffer == NULL) {
+        return EFI_OUT_OF_RESOURCES;
+      }
+
+      Temp = (UINT8 *)Buffer;
+
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len  = 0x2B;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
+      ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
+
+      Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
+      ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
+
+      *Configuration = Buffer;
+      return EFI_SUCCESS;
+    }
+    List = List->ForwardLink;
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+   Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
+
+   This member function programs the specified PCI root bridge to decode the bus range that is
+   specified by the input parameter Configuration.
+   The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
+
+   @param[in] This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+   @param[in] RootBridgeHandle  The PCI Root Bridge whose bus range is to be programmed
+   @param[in] Configuration     The pointer to the PCI bus resource descriptor
+
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_INVALID_PARAMETER  Configuration is NULL.
+   @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.
+   @retval EFI_INVALID_PARAMETER  Configuration does not include a valid ACPI 2.0 bus resource descriptor.
+   @retval EFI_INVALID_PARAMETER  Configuration includes valid ACPI 2.0 resource descriptors other than
+                                  bus descriptors.
+   @retval EFI_INVALID_PARAMETER  Configuration contains one or more invalid ACPI resource descriptors.
+   @retval EFI_INVALID_PARAMETER  "Address Range Minimum" is invalid for this root bridge.
+   @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this root bridge.
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.
+   @retval EFI_SUCCESS            The bus range for the PCI root bridge was programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+SetBusNumbers(
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  IN VOID                                             *Configuration
+  )
+{
+  LIST_ENTRY                            *List;
+  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+  UINT8                                 *Ptr;
+  UINTN                                 BusStart;
+  UINTN                                 BusEnd;
+  UINTN                                 BusLen;
+
+  if (Configuration == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Ptr = Configuration;
+
+  //
+  // Check the Configuration is valid
+  //
+  if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+  if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List = HostBridgeInstance->Head.ForwardLink;
+
+  Ptr = Configuration;
+
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
+      BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
+      BusEnd = BusStart + BusLen - 1;
+
+      if (BusStart > BusEnd) {
+        return EFI_INVALID_PARAMETER;
+      }
+
+      if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
+        return EFI_INVALID_PARAMETER;
+      }
+
+      //
+      // Update the Bus Range
+      //
+      RootBridgeInstance->ResAllocNode[TypeBus].Base   = BusStart;
+      RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
+      RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
+
+      //
+      // Program the Root Bridge Hardware
+      //
+
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+VOID
+EFIAPI
+SubmitGetResourceType(
+ IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr,
+ OUT   UINT64*                            Index
+)
+{
+  switch (Ptr->ResType) {
+    case 0:
+      if (Ptr->AddrSpaceGranularity == 32) {
+        if (Ptr->SpecificFlag == 0x06)
+          *Index = TypePMem32;
+        else
+          *Index = TypeMem32;
+      }
+
+      if (Ptr->AddrSpaceGranularity == 64) {
+        if (Ptr->SpecificFlag == 0x06)
+          *Index = TypePMem64;
+        else
+          *Index = TypeMem64;
+      }
+      break;
+
+    case 1:
+      *Index = TypeIo;
+      break;
+
+    default:
+      break;
+  };
+
+}
+
+/**
+   Submits the I/O and memory resource requirements for the specified PCI root bridge.
+
+   This function is used to submit all the I/O and memory resources that are required by the specified
+   PCI root bridge. The input parameter Configuration is used to specify the following:
+   - The various types of resources that are required
+   - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+   @param[in] This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+   @param[in] RootBridgeHandle  The PCI root bridge whose I/O and memory resource requirements are being submitted.
+   @param[in] Configuration     The pointer to the PCI I/O and PCI memory resource descriptor.
+
+   @retval EFI_SUCCESS            The I/O and memory resource requests for a PCI root bridge were accepted.
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_INVALID_PARAMETER  Configuration is NULL.
+   @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.
+   @retval EFI_INVALID_PARAMETER  Configuration includes requests for one or more resource types that are
+                                  not supported by this PCI root bridge. This error will happen if the caller
+                                  did not combine resources according to Attributes that were returned by
+                                  GetAllocAttributes().
+   @retval EFI_INVALID_PARAMETER  Address Range Maximum" is invalid.
+   @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  "Address Space Granularity" is invalid for this PCI root bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+SubmitResources(
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  IN VOID                                             *Configuration
+  )
+{
+  LIST_ENTRY                            *List;
+  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+  UINT8                                 *Temp;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;
+  UINT64                                AddrLen;
+  UINT64                                Alignment;
+  UINTN                                 Index;
+
+  PCIE_DEBUG("In SubmitResources\n");
+  //
+  // Check the input parameter: Configuration
+  //
+  if (Configuration == NULL)
+    return EFI_INVALID_PARAMETER;
+
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List = HostBridgeInstance->Head.ForwardLink;
+
+  Temp = (UINT8 *)Configuration;
+  while ( *Temp == 0x8A)
+    Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
+
+  if (*Temp != 0x79)
+    return EFI_INVALID_PARAMETER;
+
+  Temp = (UINT8 *)Configuration;
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      while ( *Temp == 0x8A) {
+        Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
+        PCIE_DEBUG("Ptr->ResType:%d\n", Ptr->ResType);
+        PCIE_DEBUG("Ptr->Addrlen:%llx\n", Ptr->AddrLen);
+        PCIE_DEBUG("Ptr->AddrRangeMax:%llx\n", Ptr->AddrRangeMax);
+        PCIE_DEBUG("Ptr->AddrRangeMin:%llx\n", Ptr->AddrRangeMin);
+        PCIE_DEBUG("Ptr->SpecificFlag:%llx\n", Ptr->SpecificFlag);
+        PCIE_DEBUG("Ptr->AddrSpaceGranularity:%d\n", Ptr->AddrSpaceGranularity);
+        PCIE_DEBUG("RootBridgeInstance->RootBridgeAttrib:%llx\n", RootBridgeInstance->RootBridgeAttrib);
+        //
+        // Check address range alignment
+        //
+        if (Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
+          return EFI_INVALID_PARAMETER;
+        }
+        Index = 0;
+        SubmitGetResourceType(Ptr,&Index);
+        AddrLen = (UINTN) Ptr->AddrLen;
+        Alignment = (UINTN) Ptr->AddrRangeMax;
+        RootBridgeInstance->ResAllocNode[Index].Length  = AddrLen;
+        RootBridgeInstance->ResAllocNode[Index].Alignment = Alignment;
+        RootBridgeInstance->ResAllocNode[Index].Status  = ResRequested;
+        HostBridgeInstance->ResourceSubmited = TRUE;
+
+        Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
+      }
+
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+   Returns the proposed resource settings for the specified PCI root bridge.
+
+   This member function returns the proposed resource settings for the specified PCI root bridge. The
+   proposed resource settings are prepared when NotifyPhase() is called with a Phase of
+   EfiPciHostBridgeAllocateResources. The output parameter Configuration
+   specifies the following:
+   - The various types of resources, excluding bus resources, that are allocated
+   - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+   @param[in]  This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+   @param[in]  RootBridgeHandle  The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+   @param[out] Configuration     The pointer to the pointer to the PCI I/O and memory resource descriptor.
+
+   @retval EFI_SUCCESS            The requested parameters were returned.
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+SetResource(
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance,
+  VOID                                  *Buffer
+
+)
+{
+  UINTN                                 Index;
+  UINT8                                 *Temp;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;
+  UINT64                                ResStatus;
+
+  Temp = Buffer;
+
+  for (Index = 0; Index < TypeBus; Index ++)
+  {
+    if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+      Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
+      ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
+
+      switch (Index) {
+
+      case TypeIo:
+        //
+        // Io
+        //
+        Ptr->Desc = 0x8A;
+        Ptr->Len  = 0x2B;
+        Ptr->ResType = 1;
+        Ptr->GenFlag = 0;
+        Ptr->SpecificFlag = 0;
+        /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+        Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+                            (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+        Ptr->AddrRangeMax = 0;
+        Ptr->AddrTranslationOffset = \
+             (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+        Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+        break;
+
+      case TypeMem32:
+        //
+        // Memory 32
+        //
+        Ptr->Desc = 0x8A;
+        Ptr->Len  = 0x2B;
+        Ptr->ResType = 0;
+        Ptr->GenFlag = 0;
+        Ptr->SpecificFlag = 0;
+        Ptr->AddrSpaceGranularity = 32;
+        /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+        Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+                             (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+        Ptr->AddrRangeMax = 0;
+        Ptr->AddrTranslationOffset = \
+             (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+        Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+        break;
+
+      case TypePMem32:
+        //
+        // Prefetch memory 32
+        //
+        Ptr->Desc = 0x8A;
+        Ptr->Len  = 0x2B;
+        Ptr->ResType = 0;
+        Ptr->GenFlag = 0;
+        Ptr->SpecificFlag = 6;
+        Ptr->AddrSpaceGranularity = 32;
+        /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+        Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+                             (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+        Ptr->AddrRangeMax = 0;
+        Ptr->AddrTranslationOffset = \
+             (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+        Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+        break;
+
+      case TypeMem64:
+        //
+        // Memory 64
+        //
+        Ptr->Desc = 0x8A;
+        Ptr->Len  = 0x2B;
+        Ptr->ResType = 0;
+        Ptr->GenFlag = 0;
+        Ptr->SpecificFlag = 0;
+        Ptr->AddrSpaceGranularity = 64;
+        /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+        Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+                             (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
+        Ptr->AddrRangeMax = 0;
+        Ptr->AddrTranslationOffset = \
+             (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+        Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+        break;
+
+      case TypePMem64:
+        //
+        // Prefetch memory 64
+        //
+        Ptr->Desc = 0x8A;
+        Ptr->Len  = 0x2B;
+        Ptr->ResType = 0;
+        Ptr->GenFlag = 0;
+        Ptr->SpecificFlag = 6;
+        Ptr->AddrSpaceGranularity = 64;
+        /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
+        Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
+                             (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
+        Ptr->AddrRangeMax = 0;
+        Ptr->AddrTranslationOffset = \
+             (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
+        Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
+        break;
+      };
+      PCIE_DEBUG("Ptr->ResType:%d\n", Ptr->ResType);
+      PCIE_DEBUG("Ptr->Addrlen:%llx\n", Ptr->AddrLen);
+      PCIE_DEBUG("Ptr->AddrRangeMax:%llx\n", Ptr->AddrRangeMax);
+      PCIE_DEBUG("Ptr->AddrRangeMin:%llx\n", Ptr->AddrRangeMin);
+      PCIE_DEBUG("Ptr->SpecificFlag:%llx\n", Ptr->SpecificFlag);
+      PCIE_DEBUG("Ptr->AddrTranslationOffset:%d\n", Ptr->AddrTranslationOffset);
+      PCIE_DEBUG("Ptr->AddrSpaceGranularity:%d\n", Ptr->AddrSpaceGranularity);
+
+      Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
+    }
+  }
+  ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
+  ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
+
+  return EFI_SUCCESS;
+}
+/**
+   Returns the proposed resource settings for the specified PCI root bridge.
+
+   This member function returns the proposed resource settings for the specified PCI root bridge. The
+   proposed resource settings are prepared when NotifyPhase() is called with a Phase of
+   EfiPciHostBridgeAllocateResources. The output parameter Configuration
+   specifies the following:
+   - The various types of resources, excluding bus resources, that are allocated
+   - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+   @param[in]  This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+   @param[in]  RootBridgeHandle  The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+   @param[out] Configuration     The pointer to the pointer to the PCI I/O and memory resource descriptor.
+
+   @retval EFI_SUCCESS            The requested parameters were returned.
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+GetProposedResources(
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN  EFI_HANDLE                                       RootBridgeHandle,
+  OUT VOID                                             **Configuration
+  )
+{
+  LIST_ENTRY                            *List;
+  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+  UINTN                                 Index;
+  UINTN                                 Number;
+  VOID                                  *Buffer;
+
+  Buffer = NULL;
+  Number = 0;
+
+  PCIE_DEBUG("In GetProposedResources\n");
+  //
+  // Get the Host Bridge Instance from the resource allocation protocol
+  //
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List = HostBridgeInstance->Head.ForwardLink;
+
+  //
+  // Enumerate the root bridges in this host bridge
+  //
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      for (Index = 0; Index < TypeBus; Index ++) {
+        if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
+          Number ++;
+        }
+      }
+
+      Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
+      if (Buffer == NULL) {
+        return EFI_OUT_OF_RESOURCES;
+      }
+
+      (VOID)SetResource(RootBridgeInstance,Buffer);
+
+      *Configuration = Buffer;
+
+      return EFI_SUCCESS;
+    }
+
+    List = List->ForwardLink;
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+   Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
+   stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
+   PCI controllers before enumeration.
+
+   This function is called during the PCI enumeration process. No specific action is expected from this
+   member function. It allows the host bridge driver to preinitialize individual PCI controllers before
+   enumeration.
+
+   @param This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+   @param RootBridgeHandle  The associated PCI root bridge handle. Type EFI_HANDLE is defined in
+                            InstallProtocolInterface() in the UEFI 2.0 Specification.
+   @param PciAddress        The address of the PCI device on the PCI bus. This address can be passed to the
+                            EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
+                            configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
+                            the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
+   @param Phase             The phase of the PCI device enumeration.
+
+   @retval EFI_SUCCESS              The requested parameters were returned.
+   @retval EFI_INVALID_PARAMETER    RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_INVALID_PARAMETER    Phase is not a valid phase that is defined in
+                                    EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
+   @retval EFI_DEVICE_ERROR         Programming failed due to a hardware error. The PCI enumerator should
+                                    not enumerate this device, including its child devices if it is a PCI-to-PCI
+                                    bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+PreprocessController (
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL          *This,
+  IN  EFI_HANDLE                                                RootBridgeHandle,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS               PciAddress,
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE              Phase
+  )
+{
+  PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
+  PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
+  LIST_ENTRY                            *List;
+
+  HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+  List = HostBridgeInstance->Head.ForwardLink;
+
+  //
+  // Enumerate the root bridges in this host bridge
+  //
+  while (List != &HostBridgeInstance->Head) {
+    RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+    if (RootBridgeHandle == RootBridgeInstance->Handle) {
+      break;
+    }
+    List = List->ForwardLink;
+  }
+  if (List == &HostBridgeInstance->Head) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
new file mode 100644
index 0000000..cddda6b
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
@@ -0,0 +1,521 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution.  The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#ifndef _PCI_HOST_BRIDGE_H_
+#define _PCI_HOST_BRIDGE_H_
+
+#include <PiDxe.h>
+
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/Acpi.h>
+
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/Metronome.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/CpuIo2.h>
+
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+
+// Enable below statments to enable PCIE debug
+//#define  PCIE_DEBUG_ENABLE
+//#define  PCIE_VDEBUG_ENABLE
+//#define  PCIE_CDEBUG_ENABLE
+
+#ifdef PCIE_CDEBUG_ENABLE
+# define PCIE_CSR_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
+#else
+# define PCIE_CSR_DEBUG(arg...)
+#endif
+
+#ifdef PCIE_VDEBUG_ENABLE
+# define PCIE_VDEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
+#else
+# define PCIE_VDEBUG(arg...)
+#endif
+
+#ifdef PCIE_DEBUG_ENABLE
+# define PCIE_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
+#else
+# define PCIE_DEBUG(arg...)
+#endif
+#define PCIE_WARN(arg...) DEBUG((EFI_D_WARN,## arg))
+#define PCIE_ERR(arg...) DEBUG((EFI_D_ERROR,## arg))
+#define PCIE_INFO(arg...) DEBUG((EFI_D_INFO,## arg))
+
+#define MAX_PCI_DEVICE_NUMBER      31
+#define MAX_PCI_FUNCTION_NUMBER    7
+#define MAX_PCI_REG_ADDRESS        0xFFFF
+
+typedef enum {
+  IoOperation,
+  MemOperation,
+  PciOperation
+} OPERATION_TYPE;
+
+#define PCI_HOST_BRIDGE_SIGNATURE  SIGNATURE_32('e', 'h', 's', 't')
+typedef struct {
+  UINTN                                             Signature;
+  EFI_HANDLE                                        HostBridgeHandle;
+  UINTN                                             RootBridgeNumber;
+  LIST_ENTRY                                        Head;
+  BOOLEAN                                           ResourceSubmited;
+  BOOLEAN                                           CanRestarted;
+  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  ResAlloc;
+} PCI_HOST_BRIDGE_INSTANCE;
+
+#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \
+  CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
+
+//
+//  HostBridge Resource Allocation interface
+//
+
+/**
+   These are the notifications from the PCI bus driver that it is about to enter a certain
+   phase of the PCI enumeration process.
+
+   This member function can be used to notify the host bridge driver to perform specific actions,
+   including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
+   Eight notification points are defined at this time. See belows:
+   EfiPciHostBridgeBeginEnumeration       Resets the host bridge PCI apertures and internal data
+                                          structures. The PCI enumerator should issue this notification
+                                          before starting a fresh enumeration process. Enumeration cannot
+                                          be restarted after sending any other notification such as
+                                          EfiPciHostBridgeBeginBusAllocation.
+   EfiPciHostBridgeBeginBusAllocation     The bus allocation phase is about to begin. No specific action is
+                                          required here. This notification can be used to perform any
+                                          chipset-specific programming.
+   EfiPciHostBridgeEndBusAllocation       The bus allocation and bus programming phase is complete. No
+                                          specific action is required here. This notification can be used to
+                                          perform any chipset-specific programming.
+   EfiPciHostBridgeBeginResourceAllocation
+                                          The resource allocation phase is about to begin. No specific
+                                          action is required here. This notification can be used to perform
+                                          any chipset-specific programming.
+   EfiPciHostBridgeAllocateResources      Allocates resources per previously submitted requests for all the PCI
+                                          root bridges. These resource settings are returned on the next call to
+                                          GetProposedResources(). Before calling NotifyPhase() with a Phase of
+                                          EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
+                                          for gathering I/O and memory requests for
+                                          all the PCI root bridges and submitting these requests using
+                                          SubmitResources(). This function pads the resource amount
+                                          to suit the root bridge hardware, takes care of dependencies between
+                                          the PCI root bridges, and calls the Global Coherency Domain (GCD)
+                                          with the allocation request. In the case of padding, the allocated range
+                                          could be bigger than what was requested.
+   EfiPciHostBridgeSetResources           Programs the host bridge hardware to decode previously allocated
+                                          resources (proposed resources) for all the PCI root bridges. After the
+                                          hardware is programmed, reassigning resources will not be supported.
+                                          The bus settings are not affected.
+   EfiPciHostBridgeFreeResources          Deallocates resources that were previously allocated for all the PCI
+                                          root bridges and resets the I/O and memory apertures to their initial
+                                          state. The bus settings are not affected. If the request to allocate
+                                          resources fails, the PCI enumerator can use this notification to
+                                          deallocate previous resources, adjust the requests, and retry
+                                          allocation.
+   EfiPciHostBridgeEndResourceAllocation  The resource allocation phase is completed. No specific action is
+                                          required here. This notification can be used to perform any chipsetspecific
+                                          programming.
+
+   @param[in] This                The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+   @param[in] Phase               The phase during enumeration
+
+   @retval EFI_NOT_READY          This phase cannot be entered at this time. For example, this error
+                                  is valid for a Phase of EfiPciHostBridgeAllocateResources if
+                                  SubmitResources() has not been called for one or more
+                                  PCI root bridges before this call
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error. This error is valid
+                                  for a Phase of EfiPciHostBridgeSetResources.
+   @retval EFI_INVALID_PARAMETER  Invalid phase parameter
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+                                  This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
+                                  previously submitted resource requests cannot be fulfilled or
+                                  were only partially fulfilled.
+   @retval EFI_SUCCESS            The notification was accepted without any errors.
+
+**/
+EFI_STATUS
+EFIAPI
+NotifyPhase(
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase
+  );
+
+/**
+   Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
+
+   This function is called multiple times to retrieve the device handles of all the PCI root bridges that
+   are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
+   root bridges. On each call, the handle that was returned by the previous call is passed into the
+   interface, and on output the interface returns the device handle of the next PCI root bridge. The
+   caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+   for that root bridge. When there are no more PCI root bridges to report, the interface returns
+   EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
+   are returned by this function.
+   For D945 implementation, there is only one root bridge in PCI host bridge.
+
+   @param[in]       This              The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+   @param[in, out]  RootBridgeHandle  Returns the device handle of the next PCI root bridge.
+
+   @retval EFI_SUCCESS            If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
+                                  specific Host bridge and return EFI_SUCCESS.
+   @retval EFI_NOT_FOUND          Can not find the any more root bridge in specific host bridge.
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not an EFI_HANDLE that was
+                                  returned on a previous call to GetNextRootBridge().
+**/
+EFI_STATUS
+EFIAPI
+GetNextRootBridge(
+  IN       EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN OUT   EFI_HANDLE                                       *RootBridgeHandle
+  );
+
+/**
+   Returns the allocation attributes of a PCI root bridge.
+
+   The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
+   from one PCI root bridge to another. These attributes are different from the decode-related
+   attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
+   RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
+   handles of all the root bridges that are associated with this host bridge must be obtained by calling
+   GetNextRootBridge(). The attributes are static in the sense that they do not change during or
+   after the enumeration process. The hardware may provide mechanisms to change the attributes on
+   the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
+   installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
+   "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
+   For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
+   include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
+   prefetchable memory.
+      Attribute                                 Description
+   ------------------------------------         ----------------------------------------------------------------------
+   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM         If this bit is set, then the PCI root bridge does not support separate
+                                                windows for nonprefetchable and prefetchable memory. A PCI bus
+                                                driver needs to include requests for prefetchable memory in the
+                                                nonprefetchable memory pool.
+
+   EFI_PCI_HOST_BRIDGE_MEM64_DECODE             If this bit is set, then the PCI root bridge supports 64-bit memory
+                                                windows. If this bit is not set, the PCI bus driver needs to include
+                                                requests for a 64-bit memory address in the corresponding 32-bit
+                                                memory pool.
+
+   @param[in]   This               The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+   @param[in]   RootBridgeHandle   The device handle of the PCI root bridge in which the caller is interested. Type
+                                   EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+   @param[out]  Attributes         The pointer to attribte of root bridge, it is output parameter
+
+   @retval EFI_INVALID_PARAMETER   Attribute pointer is NULL
+   @retval EFI_INVALID_PARAMETER   RootBridgehandle is invalid.
+   @retval EFI_SUCCESS             Success to get attribute of interested root bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+GetAttributes(
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN  EFI_HANDLE                                       RootBridgeHandle,
+  OUT UINT64                                           *Attributes
+  );
+
+/**
+   Sets up the specified PCI root bridge for the bus enumeration process.
+
+   This member function sets up the root bridge for bus enumeration and returns the PCI bus range
+   over which the search should be performed in ACPI 2.0 resource descriptor format.
+
+   @param[in]   This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
+   @param[in]   RootBridgeHandle  The PCI Root Bridge to be set up.
+   @param[out]  Configuration     Pointer to the pointer to the PCI bus resource descriptor.
+
+   @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
+   @retval EFI_OUT_OF_RESOURCES  Fail to allocate ACPI resource descriptor tag.
+   @retval EFI_SUCCESS           Sucess to allocate ACPI resource descriptor.
+
+**/
+EFI_STATUS
+EFIAPI
+StartBusEnumeration(
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN  EFI_HANDLE                                       RootBridgeHandle,
+  OUT VOID                                             **Configuration
+  );
+
+/**
+   Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
+
+   This member function programs the specified PCI root bridge to decode the bus range that is
+   specified by the input parameter Configuration.
+   The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
+
+   @param[in] This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
+   @param[in] RootBridgeHandle  The PCI Root Bridge whose bus range is to be programmed
+   @param[in] Configuration     The pointer to the PCI bus resource descriptor
+
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_INVALID_PARAMETER  Configuration is NULL.
+   @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.
+   @retval EFI_INVALID_PARAMETER  Configuration does not include a valid ACPI 2.0 bus resource descriptor.
+   @retval EFI_INVALID_PARAMETER  Configuration includes valid ACPI 2.0 resource descriptors other than
+                                  bus descriptors.
+   @retval EFI_INVALID_PARAMETER  Configuration contains one or more invalid ACPI resource descriptors.
+   @retval EFI_INVALID_PARAMETER  "Address Range Minimum" is invalid for this root bridge.
+   @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this root bridge.
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.
+   @retval EFI_SUCCESS            The bus range for the PCI root bridge was programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+SetBusNumbers(
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  IN VOID                                             *Configuration
+  );
+
+/**
+   Submits the I/O and memory resource requirements for the specified PCI root bridge.
+
+   This function is used to submit all the I/O and memory resources that are required by the specified
+   PCI root bridge. The input parameter Configuration is used to specify the following:
+   - The various types of resources that are required
+   - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+   @param[in] This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+   @param[in] RootBridgeHandle  The PCI root bridge whose I/O and memory resource requirements are being submitted.
+   @param[in] Configuration     The pointer to the PCI I/O and PCI memory resource descriptor.
+
+   @retval EFI_SUCCESS            The I/O and memory resource requests for a PCI root bridge were accepted.
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_INVALID_PARAMETER  Configuration is NULL.
+   @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.
+   @retval EFI_INVALID_PARAMETER  Configuration includes requests for one or more resource types that are
+                                  not supported by this PCI root bridge. This error will happen if the caller
+                                  did not combine resources according to Attributes that were returned by
+                                  GetAllocAttributes().
+   @retval EFI_INVALID_PARAMETER  Address Range Maximum" is invalid.
+   @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  "Address Space Granularity" is invalid for this PCI root bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+SubmitResources(
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN EFI_HANDLE                                       RootBridgeHandle,
+  IN VOID                                             *Configuration
+  );
+
+/**
+   Returns the proposed resource settings for the specified PCI root bridge.
+
+   This member function returns the proposed resource settings for the specified PCI root bridge. The
+   proposed resource settings are prepared when NotifyPhase() is called with a Phase of
+   EfiPciHostBridgeAllocateResources. The output parameter Configuration
+   specifies the following:
+   - The various types of resources, excluding bus resources, that are allocated
+   - The associated lengths in terms of ACPI 2.0 resource descriptor format
+
+   @param[in]  This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+   @param[in]  RootBridgeHandle  The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
+   @param[out] Configuration     The pointer to the pointer to the PCI I/O and memory resource descriptor.
+
+   @retval EFI_SUCCESS            The requested parameters were returned.
+   @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+GetProposedResources(
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
+  IN  EFI_HANDLE                                       RootBridgeHandle,
+  OUT VOID                                             **Configuration
+  );
+
+/**
+   Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
+   stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
+   PCI controllers before enumeration.
+
+   This function is called during the PCI enumeration process. No specific action is expected from this
+   member function. It allows the host bridge driver to preinitialize individual PCI controllers before
+   enumeration.
+
+   @param This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
+   @param RootBridgeHandle  The associated PCI root bridge handle. Type EFI_HANDLE is defined in
+                            InstallProtocolInterface() in the UEFI 2.0 Specification.
+   @param PciAddress        The address of the PCI device on the PCI bus. This address can be passed to the
+                            EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
+                            configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
+                            the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
+   @param Phase             The phase of the PCI device enumeration.
+
+   @retval EFI_SUCCESS              The requested parameters were returned.
+   @retval EFI_INVALID_PARAMETER    RootBridgeHandle is not a valid root bridge handle.
+   @retval EFI_INVALID_PARAMETER    Phase is not a valid phase that is defined in
+                                    EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
+   @retval EFI_DEVICE_ERROR         Programming failed due to a hardware error. The PCI enumerator should
+                                    not enumerate this device, including its child devices if it is a PCI-to-PCI
+                                    bridge.
+
+**/
+EFI_STATUS
+EFIAPI
+PreprocessController (
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *This,
+  IN  EFI_HANDLE                                        RootBridgeHandle,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS       PciAddress,
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE      Phase
+  );
+
+
+//
+// Define resource status constant
+//
+#define EFI_RESOURCE_NONEXISTENT   0xFFFFFFFFFFFFFFFFULL
+#define EFI_RESOURCE_LESS          0xFFFFFFFFFFFFFFFEULL
+
+
+//
+// Driver Instance Data Prototypes
+//
+
+typedef struct {
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation;
+  UINTN                                      NumberOfBytes;
+  UINTN                                      NumberOfPages;
+  EFI_PHYSICAL_ADDRESS                       HostAddress;
+  EFI_PHYSICAL_ADDRESS                       MappedHostAddress;
+} MAP_INFO;
+
+typedef struct {
+  ACPI_HID_DEVICE_PATH              AcpiDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL          EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+typedef enum {
+  TypeIo = 0,
+  TypeMem32,
+  TypePMem32,
+  TypeMem64,
+  TypePMem64,
+  TypeBus,
+  TypeMax
+} PCI_RESOURCE_TYPE;
+
+typedef enum {
+  ResNone = 0,
+  ResSubmitted,
+  ResRequested,
+  ResAllocated,
+  ResStatusMax
+} RES_STATUS;
+
+typedef struct {
+  PCI_RESOURCE_TYPE Type;
+  UINT64            Base;
+  UINT64            Length;
+  UINT64            Alignment;
+  RES_STATUS        Status;
+} PCI_RES_NODE;
+
+#define PCI_ROOT_BRIDGE_SIGNATURE  SIGNATURE_32('e', '2', 'p', 'b')
+
+typedef struct {
+  UINT32                 Signature;
+  LIST_ENTRY             Link;
+  EFI_HANDLE             Handle;
+  UINT64                 RootBridgeAttrib;
+  UINT64                 Attributes;
+  UINT64                 Supports;
+
+  //
+  // Specific for this memory controller: Bus, I/O, Mem
+  //
+  PCI_RES_NODE           ResAllocNode[6];
+
+  //
+  // Addressing for Memory and I/O and Bus arrange
+  //
+  UINT64                 BusBase;
+  UINT64                 MemBase;
+  UINT64                 IoBase;
+  UINT64                 BusLimit;
+  UINT64                 MemLimit;
+  UINT64                 IoLimit;
+  UINT64                 RbPciBar;
+  UINT64                 Ecam;
+
+  UINTN                  PciAddress;
+  UINTN                  PciData;
+  UINTN                  Port;
+  UINT32                 SocType;
+  UINT64                 CpuMemRegionBase;
+  UINT64                 CpuIoRegionBase;
+  UINT64                 PciRegionBase;
+  UINT64                 PciRegionLimit;
+
+  EFI_DEVICE_PATH_PROTOCOL                *DevicePath;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         Io;
+
+} PCI_ROOT_BRIDGE_INSTANCE;
+
+
+//
+// Driver Instance Data Macros
+//
+#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
+  CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
+
+
+#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \
+  CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
+
+/**
+
+  Construct the Pci Root Bridge Io protocol
+
+  @param Protocol         Point to protocol instance
+  @param HostBridgeHandle Handle of host bridge
+  @param Attri            Attribute of host bridge
+  @param ResAppeture      ResourceAppeture for host bridge
+
+  @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
+
+**/
+EFI_STATUS
+RootBridgeConstructor (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,
+  IN EFI_HANDLE                         HostBridgeHandle,
+  IN UINT64                             Attri,
+  IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE  *ResAppeture,
+  IN UINT32                             Seg
+  );
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
new file mode 100644
index 0000000..5cfbee5
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
@@ -0,0 +1,74 @@
+## @file
+#
+#  Component description file PCI Host Bridge driver.
+#  Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PciHostBridge
+  FILE_GUID                      = B0E61270-263F-11E3-8224-0800200C9A66
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializePciHostBridge
+
+[Packages]
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  MemoryAllocationLib
+  DxeServicesTableLib
+  CacheMaintenanceLib
+  DmaLib
+  BaseMemoryLib
+  BaseLib
+  DebugLib
+  TimerLib
+  ArmLib
+  DevicePathLib
+  PcdLib
+  OemMiscLib
+
+[Sources]
+  PciHostBridge.c
+  PciRootBridgeIo.c
+  PciHostBridge.h
+
+[Protocols]
+  gEfiPciHostBridgeResourceAllocationProtocolGuid
+  gEfiPciRootBridgeIoProtocolGuid
+  gEfiMetronomeArchProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEmbeddedGpioProtocolGuid
+
+[depex]
+  gEfiMetronomeArchProtocolGuid
+
+[FeaturePcd]
+
+[Pcd]
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P
+  gHisiTokenSpaceGuid.Pcdsoctype
+
+[Guids]
+  gEfiEventExitBootServicesGuid                 ## PRODUCES ## Event
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
new file mode 100644
index 0000000..03edcf1
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -0,0 +1,2313 @@
+/**
+ * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
+ * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution.  The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#include "PciHostBridge.h"
+#include <Library/DevicePathLib.h>
+#include <Library/DmaLib.h>
+#include <Library/PciExpressLib.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+
+
+typedef struct {
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     SpaceDesp[TypeMax];
+  EFI_ACPI_END_TAG_DESCRIPTOR           EndDesp;
+} RESOURCE_CONFIGURATION;
+
+RESOURCE_CONFIGURATION Configuration = {
+  {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},
+  {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
+  {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},
+  {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},
+  {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},
+  {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},
+  {0x79, 0}
+};
+
+//
+// Protocol Member Function Prototypes
+//
+
+/**
+   Polls an address in memory mapped I/O space until an exit condition is met, or
+   a timeout occurs.
+
+   This function provides a standard way to poll a PCI memory location. A PCI memory read
+   operation is performed at the PCI memory address specified by Address for the width specified
+   by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
+   read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
+   Mask) is equal to Value.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operations.
+   @param[in]   Address   The base address of the memory operations. The caller is
+                          responsible for aligning Address if required.
+   @param[in]   Mask      Mask used for the polling criteria. Bytes above Width in Mask
+                          are ignored. The bits in the bytes below Width which are zero in
+                          Mask are ignored when polling the memory address.
+   @param[in]   Value     The comparison value used for the polling exit criteria.
+   @param[in]   Delay     The number of 100 ns units to poll. Note that timer available may
+                          be of poorer granularity.
+   @param[out]  Result    Pointer to the last value read from the memory location.
+
+   @retval EFI_SUCCESS            The last data returned from the access matched the poll exit criteria.
+   @retval EFI_INVALID_PARAMETER  Width is invalid.
+   @retval EFI_INVALID_PARAMETER  Result is NULL.
+   @retval EFI_TIMEOUT            Delay expired before a match occurred.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollMem (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                                 Address,
+  IN  UINT64                                 Mask,
+  IN  UINT64                                 Value,
+  IN  UINT64                                 Delay,
+  OUT UINT64                                 *Result
+  );
+
+/**
+   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
+   satisfied or after a defined duration.
+
+   This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
+   performed at the PCI I/O address specified by Address for the width specified by Width.
+   The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
+   repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
+   to Value.
+
+   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in] Width     Signifies the width of the I/O operations.
+   @param[in] Address   The base address of the I/O operations. The caller is responsible
+                        for aligning Address if required.
+   @param[in] Mask      Mask used for the polling criteria. Bytes above Width in Mask
+                        are ignored. The bits in the bytes below Width which are zero in
+                        Mask are ignored when polling the I/O address.
+   @param[in] Value     The comparison value used for the polling exit criteria.
+   @param[in] Delay     The number of 100 ns units to poll. Note that timer available may
+                        be of poorer granularity.
+   @param[out] Result   Pointer to the last value read from the memory location.
+
+   @retval EFI_SUCCESS            The last data returned from the access matched the poll exit criteria.
+   @retval EFI_INVALID_PARAMETER  Width is invalid.
+   @retval EFI_INVALID_PARAMETER  Result is NULL.
+   @retval EFI_TIMEOUT            Delay expired before a match occurred.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollIo (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                                 Address,
+  IN  UINT64                                 Mask,
+  IN  UINT64                                 Value,
+  IN  UINT64                                 Delay,
+  OUT UINT64                                 *Result
+  );
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
+   registers in the PCI root bridge memory space.
+   The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+   any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operation.
+   @param[in]   Address   The base address of the memory operation. The caller is
+                          responsible for aligning the Address if required.
+   @param[in]   Count     The number of memory operations to perform. Bytes moved is
+                          Width size * Count, starting at Address.
+   @param[out]  Buffer    For read operations, the destination buffer to store the results. For
+                          write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  OUT    VOID                                   *Buffer
+  );
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
+   registers in the PCI root bridge memory space.
+   The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+   any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operation.
+   @param[in]   Address   The base address of the memory operation. The caller is
+                          responsible for aligning the Address if required.
+   @param[in]   Count     The number of memory operations to perform. Bytes moved is
+                          Width size * Count, starting at Address.
+   @param[in]   Buffer    For read operations, the destination buffer to store the results. For
+                          write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemWrite (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN     VOID                                   *Buffer
+  );
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width       Signifies the width of the memory operations.
+   @param[in]   UserAddress The base address of the I/O operation. The caller is responsible for
+                            aligning the Address if required.
+   @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width
+                            size * Count, starting at Address.
+   @param[out]  UserBuffer  For read operations, the destination buffer to store the results. For
+                            write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 UserAddress,
+  IN     UINTN                                  Count,
+  OUT    VOID                                   *UserBuffer
+  );
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width       Signifies the width of the memory operations.
+   @param[in]   UserAddress The base address of the I/O operation. The caller is responsible for
+                            aligning the Address if required.
+   @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width
+                            size * Count, starting at Address.
+   @param[in]   UserBuffer  For read operations, the destination buffer to store the results. For
+                            write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoWrite (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 UserAddress,
+  IN     UINTN                                  Count,
+  IN     VOID                                   *UserBuffer
+  );
+
+/**
+   Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
+   root bridge memory space.
+
+   The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
+   space to another region of PCI root bridge memory space. This is especially useful for video scroll
+   operation on a memory mapped video buffer.
+   The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+   any alignment and memory width restrictions that a PCI root bridge on a platform might require.
+
+   @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
+   @param[in] Width       Signifies the width of the memory operations.
+   @param[in] DestAddress The destination address of the memory operation. The caller is
+                          responsible for aligning the DestAddress if required.
+   @param[in] SrcAddress  The source address of the memory operation. The caller is
+                          responsible for aligning the SrcAddress if required.
+   @param[in] Count       The number of memory operations to perform. Bytes moved is
+                          Width size * Count, starting at DestAddress and SrcAddress.
+
+   @retval  EFI_SUCCESS             The data was copied from one memory region to another memory region.
+   @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.
+   @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoCopyMem (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 DestAddress,
+  IN     UINT64                                 SrcAddress,
+  IN     UINTN                                  Count
+  );
+
+/**
+   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+   The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
+   registers for a PCI controller.
+   The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
+   any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
+   require.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operations.
+   @param[in]   Address   The address within the PCI configuration space for the PCI controller.
+   @param[in]   Count     The number of PCI configuration operations to perform. Bytes
+                          moved is Width size * Count, starting at Address.
+   @param[out]  Buffer    For read operations, the destination buffer to store the results. For
+                          write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  OUT    VOID                                   *Buffer
+  );
+
+/**
+   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+   The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
+   registers for a PCI controller.
+   The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
+   any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
+   require.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operations.
+   @param[in]   Address   The address within the PCI configuration space for the PCI controller.
+   @param[in]   Count     The number of PCI configuration operations to perform. Bytes
+                          moved is Width size * Count, starting at Address.
+   @param[in]   Buffer    For read operations, the destination buffer to store the results. For
+                          write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciWrite (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN     VOID                                   *Buffer
+  );
+
+/**
+   Provides the PCI controller-specific addresses required to access system memory from a
+   DMA bus master.
+
+   The Map() function provides the PCI controller specific addresses needed to access system
+   memory. This function is used to map system memory for PCI bus master DMA accesses.
+
+   @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]       Operation       Indicates if the bus master is going to read or write to system memory.
+   @param[in]       HostAddress     The system memory address to map to the PCI controller.
+   @param[in, out]  NumberOfBytes   On input the number of bytes to map. On output the number of bytes that were mapped.
+   @param[out]      DeviceAddress   The resulting map address for the bus master PCI controller to use
+                                    to access the system memory's HostAddress.
+   @param[out]      Mapping         The value to pass to Unmap() when the bus master DMA operation is complete.
+
+   @retval EFI_SUCCESS            The range was mapped for the returned NumberOfBytes.
+   @retval EFI_INVALID_PARAMETER  Operation is invalid.
+   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.
+   @retval EFI_INVALID_PARAMETER  NumberOfBytes is NULL.
+   @retval EFI_INVALID_PARAMETER  DeviceAddress is NULL.
+   @retval EFI_INVALID_PARAMETER  Mapping is NULL.
+   @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.
+   @retval EFI_DEVICE_ERROR       The system hardware could not map the requested address.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMap (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
+  IN     VOID                                       *HostAddress,
+  IN OUT UINTN                                      *NumberOfBytes,
+  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
+  OUT    VOID                                       **Mapping
+  );
+
+/**
+   Completes the Map() operation and releases any corresponding resources.
+
+   The Unmap() function completes the Map() operation and releases any corresponding resources.
+   If the operation was an EfiPciOperationBusMasterWrite or
+   EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
+   Any resources used for the mapping are freed.
+
+   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in] Mapping   The mapping value returned from Map().
+
+   @retval EFI_SUCCESS            The range was unmapped.
+   @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().
+   @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoUnmap (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  VOID                             *Mapping
+  );
+
+/**
+   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
+   EfiPciOperationBusMasterCommonBuffer64 mapping.
+
+   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param Type        This parameter is not used and must be ignored.
+   @param MemoryType  The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
+   @param Pages       The number of pages to allocate.
+   @param HostAddress A pointer to store the base system memory address of the allocated range.
+   @param Attributes  The requested bit mask of attributes for the allocated range. Only
+                      the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
+                      and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
+
+   @retval EFI_SUCCESS            The requested memory pages were allocated.
+   @retval EFI_INVALID_PARAMETER  MemoryType is invalid.
+   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.
+   @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal attribute bits are
+                                  MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
+   @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoAllocateBuffer (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  EFI_ALLOCATE_TYPE                Type,
+  IN  EFI_MEMORY_TYPE                  MemoryType,
+  IN  UINTN                            Pages,
+  OUT VOID                             **HostAddress,
+  IN  UINT64                           Attributes
+  );
+
+/**
+   Frees memory that was allocated with AllocateBuffer().
+
+   The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
+
+   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param Pages       The number of pages to free.
+   @param HostAddress The base system memory address of the allocated range.
+
+   @retval EFI_SUCCESS            The requested memory pages were freed.
+   @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and Pages
+                                  was not allocated with AllocateBuffer().
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFreeBuffer (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  UINTN                            Pages,
+  OUT VOID                             *HostAddress
+  );
+
+/**
+   Flushes all PCI posted write transactions from a PCI host bridge to system memory.
+
+   The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
+   memory. Posted write transactions are generated by PCI bus masters when they perform write
+   transactions to target addresses in system memory.
+   This function does not flush posted write transactions from any PCI bridges. A PCI controller
+   specific action must be taken to guarantee that the posted write transactions have been flushed from
+   the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
+   a PCI read transaction from the PCI controller prior to calling Flush().
+
+   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+
+   @retval EFI_SUCCESS        The PCI posted write transactions were flushed from the PCI host
+                              bridge to system memory.
+   @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed from the PCI
+                              host bridge due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFlush (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This
+  );
+
+/**
+   Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
+   attributes that a PCI root bridge is currently using.
+
+   The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
+   and the mask of attributes that the PCI root bridge is currently using.
+
+   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param Supported   A pointer to the mask of attributes that this PCI root bridge
+                      supports setting with SetAttributes().
+   @param Attributes  A pointer to the mask of attributes that this PCI root bridge is
+                      currently using.
+
+   @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI root
+                                  bridge supports is returned in Supports. If Attributes is
+                                  not NULL, then the attributes that the PCI root bridge is currently
+                                  using is returned in Attributes.
+   @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoGetAttributes (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  OUT UINT64                           *Supported,
+  OUT UINT64                           *Attributes
+  );
+
+/**
+   Sets attributes for a resource range on a PCI root bridge.
+
+   The SetAttributes() function sets the attributes specified in Attributes for the PCI root
+   bridge on the resource range specified by ResourceBase and ResourceLength. Since the
+   granularity of setting these attributes may vary from resource type to resource type, and from
+   platform to platform, the actual resource range and the one passed in by the caller may differ. As a
+   result, this function may set the attributes specified by Attributes on a larger resource range
+   than the caller requested. The actual range is returned in ResourceBase and
+   ResourceLength. The caller is responsible for verifying that the actual range for which the
+   attributes were set is acceptable.
+
+   @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]       Attributes      The mask of attributes to set. If the attribute bit
+                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
+                                    MEMORY_DISABLE is set, then the resource range is specified by
+                                    ResourceBase and ResourceLength. If
+                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
+                                    MEMORY_DISABLE are not set, then ResourceBase and
+                                    ResourceLength are ignored, and may be NULL.
+   @param[in, out]  ResourceBase    A pointer to the base address of the resource range to be modified
+                                    by the attributes specified by Attributes.
+   @param[in, out]  ResourceLength  A pointer to the length of the resource range to be modified by the
+                                    attributes specified by Attributes.
+
+   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.
+   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
+   @retval  EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoSetAttributes (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN     UINT64                           Attributes,
+  IN OUT UINT64                           *ResourceBase,
+  IN OUT UINT64                           *ResourceLength
+  );
+
+/**
+   Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
+   resource descriptors.
+
+   There are only two resource descriptor types from the ACPI Specification that may be used to
+   describe the current resources allocated to a PCI root bridge. These are the QWORD Address
+   Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
+   QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
+   or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
+   Address Space Descriptors followed by an End Tag.
+
+   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[out]  Resources   A pointer to the ACPI 2.0 resource descriptors that describe the
+                            current configuration of this PCI root bridge. The storage for the
+                            ACPI 2.0 resource descriptors is allocated by this function. The
+                            caller must treat the return buffer as read-only data, and the buffer
+                            must not be freed by the caller.
+
+   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.
+   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
+   @retval  EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoConfiguration (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  OUT    VOID                             **Resources
+  );
+
+//
+// Memory Controller Pci Root Bridge Io Module Variables
+//
+EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+UINT8 mInStride[] = {
+  1, // EfiPciWidthUint8
+  2, // EfiPciWidthUint16
+  4, // EfiPciWidthUint32
+  8, // EfiPciWidthUint64
+  0, // EfiPciWidthFifoUint8
+  0, // EfiPciWidthFifoUint16
+  0, // EfiPciWidthFifoUint32
+  0, // EfiPciWidthFifoUint64
+  1, // EfiPciWidthFillUint8
+  2, // EfiPciWidthFillUint16
+  4, // EfiPciWidthFillUint32
+  8  // EfiPciWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+UINT8 mOutStride[] = {
+  1, // EfiPciWidthUint8
+  2, // EfiPciWidthUint16
+  4, // EfiPciWidthUint32
+  8, // EfiPciWidthUint64
+  1, // EfiPciWidthFifoUint8
+  2, // EfiPciWidthFifoUint16
+  4, // EfiPciWidthFifoUint32
+  8, // EfiPciWidthFifoUint64
+  0, // EfiPciWidthFillUint8
+  0, // EfiPciWidthFillUint16
+  0, // EfiPciWidthFillUint32
+  0  // EfiPciWidthFillUint64
+};
+
+
+UINT64 GetPcieCfgAddress (
+    UINT64 Ecam,
+    UINTN Bus,
+    UINTN Device,
+    UINTN Function,
+    UINTN Reg
+    )
+{
+  return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg);
+}
+
+
+void SetAtuConfig0RW (
+    PCI_ROOT_BRIDGE_INSTANCE *Private,
+    UINT32 Index
+    )
+{
+    UINTN RbPciBase = Private->RbPciBar;
+    UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
+
+
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
+
+    {
+      UINTN i;
+      for (i=0; i<0x20; i+=4) {
+        DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+      }
+    }
+}
+
+void SetAtuConfig1RW (
+    PCI_ROOT_BRIDGE_INSTANCE *Private,
+    UINT32 Index
+    )
+{
+    UINTN RbPciBase = Private->RbPciBar;
+    UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
+
+
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
+
+    {
+      UINTN i;
+      for (i=0; i<0x20; i+=4) {
+        DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+      }
+    }
+}
+
+void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index)
+{
+
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO);
+
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
+
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
+
+    {
+      UINTN i;
+      for (i=0; i<0x20; i+=4) {
+        DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+      }
+    }
+}
+
+void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index)
+{
+
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM);
+
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32));
+
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
+
+    {
+      UINTN i;
+      for (i=0; i<0x20; i+=4) {
+        DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+      }
+    }
+}
+
+VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private)
+{
+  SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0);
+  SetAtuConfig0RW (Private, 1);
+  SetAtuConfig1RW (Private, 2);
+  SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
+}
+
+
+BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port)
+{
+    UINT32                     Value = 0;
+
+    if (0x1610 == SocType)
+    {
+        Value = MmioRead32(RbPciBar + 0x131C);
+        if ((Value & 0x3F) == 0x11)
+        {
+            return TRUE;
+        }
+        return FALSE;
+    }
+    else
+    {
+        Value = MmioRead32 (0xb0000000 + 0x6818 + 0x100 * Port);
+        if ((Value & 0x3F) == 0x11)
+        {
+            return TRUE;
+        }
+        return FALSE;
+    }
+}
+
+/**
+
+  Construct the Pci Root Bridge Io protocol
+
+  @param Protocol         Point to protocol instance
+  @param HostBridgeHandle Handle of host bridge
+  @param Attri            Attribute of host bridge
+  @param ResAppeture      ResourceAppeture for host bridge
+
+  @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
+
+**/
+EFI_STATUS
+RootBridgeConstructor (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,
+  IN EFI_HANDLE                         HostBridgeHandle,
+  IN UINT64                             Attri,
+  IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE  *ResAppeture,
+  IN UINT32                             Seg
+  )
+{
+  EFI_STATUS                        Status;
+  PCI_ROOT_BRIDGE_INSTANCE          *PrivateData;
+  PCI_RESOURCE_TYPE                 Index;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);
+
+  //
+  // The host to pci bridge, the host memory and io addresses are
+  // direct mapped to pci addresses, so no need translate, set bases to 0.
+  //
+  PrivateData->MemBase = ResAppeture->MemBase;
+  PrivateData->IoBase  = ResAppeture->IoBase;
+  PrivateData->RbPciBar = ResAppeture->RbPciBar;
+  PrivateData->MemLimit = ResAppeture->MemLimit;
+  PrivateData->IoLimit  = ResAppeture->IoLimit;
+  PrivateData->Ecam = ResAppeture->Ecam;
+  PrivateData->CpuMemRegionBase = ResAppeture->CpuMemRegionBase;
+  PrivateData->CpuIoRegionBase = ResAppeture->CpuIoRegionBase;
+  PrivateData->PciRegionBase = ResAppeture->PciRegionBase;
+  PrivateData->PciRegionLimit = ResAppeture->PciRegionLimit;
+
+  //
+  // Bus Appeture for this Root Bridge (Possible Range)
+  //
+  PrivateData->BusBase  = ResAppeture->BusBase;
+  PrivateData->BusLimit = ResAppeture->BusLimit;
+
+  //
+  // Specific for this chipset
+  //
+  for (Index = TypeIo; Index < TypeMax; Index++) {
+    PrivateData->ResAllocNode[Index].Type      = Index;
+    PrivateData->ResAllocNode[Index].Base      = 0;
+    PrivateData->ResAllocNode[Index].Length    = 0;
+    PrivateData->ResAllocNode[Index].Status    = ResNone;
+  }
+
+  PrivateData->RootBridgeAttrib = Attri;
+
+  PrivateData->Supports    = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \
+                             EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
+                             EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
+                             EFI_PCI_ATTRIBUTE_VGA_IO_16  | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | \
+                             EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER;
+  PrivateData->Attributes  = PrivateData->Supports;
+
+  Protocol->ParentHandle   = HostBridgeHandle;
+
+  Protocol->PollMem        = RootBridgeIoPollMem;
+  Protocol->PollIo         = RootBridgeIoPollIo;
+
+  Protocol->Mem.Read       = RootBridgeIoMemRead;
+  Protocol->Mem.Write      = RootBridgeIoMemWrite;
+
+  Protocol->Io.Read        = RootBridgeIoIoRead;
+  Protocol->Io.Write       = RootBridgeIoIoWrite;
+
+  Protocol->CopyMem        = RootBridgeIoCopyMem;
+
+  Protocol->Pci.Read       = RootBridgeIoPciRead;
+  Protocol->Pci.Write      = RootBridgeIoPciWrite;
+
+  Protocol->Map            = RootBridgeIoMap;
+  Protocol->Unmap          = RootBridgeIoUnmap;
+
+  Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;
+  Protocol->FreeBuffer     = RootBridgeIoFreeBuffer;
+
+  Protocol->Flush          = RootBridgeIoFlush;
+
+  Protocol->GetAttributes  = RootBridgeIoGetAttributes;
+  Protocol->SetAttributes  = RootBridgeIoSetAttributes;
+
+  Protocol->Configuration  = RootBridgeIoConfiguration;
+
+  Protocol->SegmentNumber  = Seg;
+
+  InitAtu (PrivateData);
+
+  Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
+  if (EFI_ERROR(Status))
+  {
+      DEBUG((EFI_D_ERROR,"LocateProtocol MetronomeArchProtocol Error\n"));
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
+
+  The I/O operations are carried out exactly as requested. The caller is responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  @param[in] This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+  @param[in] OperationType  I/O operation type: IO/MMIO/PCI.
+  @param[in] Width          Signifies the width of the I/O or Memory operation.
+  @param[in] Address        The base address of the I/O operation.
+  @param[in] Count          The number of I/O operations to perform. The number of
+                            bytes moved is Width size * Count, starting at Address.
+  @param[in] Buffer         For read operations, the destination buffer to store the results.
+                            For write operations, the source buffer from which to write data.
+
+  @retval EFI_SUCCESS            The parameters for this request pass the checks.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
+                                 and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+RootBridgeIoCheckParameter (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN OPERATION_TYPE                         OperationType,
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64                                 Address,
+  IN UINTN                                  Count,
+  IN VOID                                   *Buffer
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE                     *PrivateData;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  *PciRbAddr;
+  UINT64                                       MaxCount;
+  UINT64                                       Base;
+  UINT64                                       Limit;
+
+  //
+  // Check to see if Buffer is NULL
+  //
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Width is in the valid range
+  //
+  if ((UINT32)Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // For FIFO type, the target address won't increase during the access,
+  // so treat Count as 1
+  //
+  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
+    Count = 1;
+  }
+
+  //
+  // Check to see if Width is in the valid range for I/O Port operations
+  //
+  Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Address is aligned
+  //
+  if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+    return EFI_UNSUPPORTED;
+  }
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+  //
+  // Check to see if any address associated with this transfer exceeds the maximum
+  // allowed address.  The maximum address implied by the parameters passed in is
+  // Address + Size * Count.  If the following condition is met, then the transfer
+  // is not supported.
+  //
+  //    Address + Size * Count > Limit + 1
+  //
+  // Since Limit can be the maximum integer value supported by the CPU and Count
+  // can also be the maximum integer value supported by the CPU, this range
+  // check must be adjusted to avoid all oveflow conditions.
+  //
+  // The following form of the range check is equivalent but assumes that
+  // Limit is of the form (2^n - 1).
+  //
+  if (OperationType == IoOperation) {
+    Base = PrivateData->IoBase;
+    Limit = PrivateData->IoLimit;
+  } else if (OperationType == MemOperation) {
+    Base = PrivateData->MemBase;
+    Limit = PrivateData->MemLimit;
+  } else {
+    PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
+    if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    /* The root complex has only one device / function */
+    if (PciRbAddr->Bus == PrivateData->BusBase && PciRbAddr->Device != 0) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    /* The other side of the RC has only one device as well */
+    if (PciRbAddr->Bus == (PrivateData->BusBase + 1 ) && PciRbAddr->Device != 0) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    if (PciRbAddr->ExtendedRegister != 0) {
+      Address = PciRbAddr->ExtendedRegister;
+    } else {
+      Address = PciRbAddr->Register;
+    }
+    Base = 0;
+    Limit = MAX_PCI_REG_ADDRESS;
+  }
+
+  if (Address < Base) {
+      return EFI_INVALID_PARAMETER;
+  }
+
+  if (Count == 0) {
+    if (Address > Limit) {
+      return EFI_UNSUPPORTED;
+    }
+  } else {
+    MaxCount = RShiftU64 (Limit, Width);
+    if (MaxCount < (Count - 1)) {
+      return EFI_UNSUPPORTED;
+    }
+    if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+      return EFI_UNSUPPORTED;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+   Internal help function for read and write memory space.
+
+   @param[in]   This          A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Write         Switch value for Read or Write.
+   @param[in]   Width         Signifies the width of the memory operations.
+   @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.
+   @param[in]   Count         The number of PCI configuration operations to perform. Bytes
+                              moved is Width size * Count, starting at Address.
+   @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
+                              write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+RootBridgeIoMemRW (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     BOOLEAN                                Write,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  )
+{
+  EFI_STATUS                             Status;
+  UINT8                                  InStride;
+  UINT8                                  OutStride;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  OperationWidth;
+  UINT8                                  *Uint8Buffer;
+  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+  /* Address is bus resource */
+  Address -= PrivateData->PciRegionBase;
+  Address += PrivateData->CpuMemRegionBase;
+
+  PCIE_DEBUG("RootBridgeIoMemRW Address:0x%llx\n", Address);
+  PCIE_DEBUG("RootBridgeIoMemRW Count:0x%llx\n", Count);
+  PCIE_DEBUG("RootBridgeIoMemRW Write:0x%llx\n", Write);
+  PCIE_DEBUG("RootBridgeIoMemRW Width:0x%llx\n", Width);
+
+  Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  InStride = mInStride[Width];
+  OutStride = mOutStride[Width];
+  OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+    if (Write) {
+      switch (OperationWidth) {
+        case EfiPciWidthUint8:
+          MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+          break;
+        case EfiPciWidthUint16:
+          MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+          break;
+        case EfiPciWidthUint32:
+          MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+          break;
+        case EfiPciWidthUint64:
+          MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+          break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
+      }
+    } else {
+      switch (OperationWidth) {
+        case EfiPciWidthUint8:
+          *Uint8Buffer = MmioRead8 ((UINTN)Address);
+          break;
+        case EfiPciWidthUint16:
+          *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+          break;
+        case EfiPciWidthUint32:
+          *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+          break;
+        case EfiPciWidthUint64:
+          *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+          break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
+      }
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+   Internal help function for read and write IO space.
+
+   @param[in]   This          A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Write         Switch value for Read or Write.
+   @param[in]   Width         Signifies the width of the memory operations.
+   @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.
+   @param[in]   Count         The number of PCI configuration operations to perform. Bytes
+                              moved is Width size * Count, starting at Address.
+   @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
+                              write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+RootBridgeIoIoRW (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     BOOLEAN                                Write,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN OUT VOID                                   *Buffer
+  )
+{
+  EFI_STATUS                             Status;
+  UINT8                                  InStride;
+  UINT8                                  OutStride;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  OperationWidth;
+  UINT8                                  *Uint8Buffer;
+  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+  /* Address is bus resource */
+  Address -= PrivateData->IoBase;
+  Address += PrivateData->CpuIoRegionBase;
+
+  Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  InStride = mInStride[Width];
+  OutStride = mOutStride[Width];
+  OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+    if (Write) {
+      switch (OperationWidth) {
+        case EfiPciWidthUint8:
+          MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+          break;
+        case EfiPciWidthUint16:
+          MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+          break;
+        case EfiPciWidthUint32:
+          MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+          break;
+        case EfiPciWidthUint64:
+          MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+          break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
+      }
+    } else {
+      switch (OperationWidth) {
+        case EfiPciWidthUint8:
+          *Uint8Buffer = MmioRead8 ((UINTN)Address);
+          break;
+        case EfiPciWidthUint16:
+          *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+          break;
+        case EfiPciWidthUint32:
+          *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+          break;
+        case EfiPciWidthUint64:
+          *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+          break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
+      }
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+
+/**
+   Polls an address in memory mapped I/O space until an exit condition is met, or
+   a timeout occurs.
+
+   This function provides a standard way to poll a PCI memory location. A PCI memory read
+   operation is performed at the PCI memory address specified by Address for the width specified
+   by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
+   read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
+   Mask) is equal to Value.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operations.
+   @param[in]   Address   The base address of the memory operations. The caller is
+                          responsible for aligning Address if required.
+   @param[in]   Mask      Mask used for the polling criteria. Bytes above Width in Mask
+                          are ignored. The bits in the bytes below Width which are zero in
+                          Mask are ignored when polling the memory address.
+   @param[in]   Value     The comparison value used for the polling exit criteria.
+   @param[in]   Delay     The number of 100 ns units to poll. Note that timer available may
+                          be of poorer granularity.
+   @param[out]  Result    Pointer to the last value read from the memory location.
+
+   @retval EFI_SUCCESS            The last data returned from the access matched the poll exit criteria.
+   @retval EFI_INVALID_PARAMETER  Width is invalid.
+   @retval EFI_INVALID_PARAMETER  Result is NULL.
+   @retval EFI_TIMEOUT            Delay expired before a match occurred.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollMem (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                                 Address,
+  IN  UINT64                                 Mask,
+  IN  UINT64                                 Value,
+  IN  UINT64                                 Delay,
+  OUT UINT64                                 *Result
+  )
+{
+  EFI_STATUS  Status;
+  UINT64      NumberOfTicks;
+  UINT32      Remainder;
+
+  if (Result == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // No matter what, always do a single poll.
+  //
+  Status = This->Mem.Read (This, Width, Address, 1, Result);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  if ((*Result & Mask) == Value) {
+    return EFI_SUCCESS;
+  }
+
+  if (Delay == 0) {
+    return EFI_TIMEOUT;
+
+  } else {
+
+    //
+    // Determine the proper # of metronome ticks to wait for polling the
+    // location.  The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
+    // The "+1" to account for the possibility of the first tick being short
+    // because we started in the middle of a tick.
+    //
+    // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
+    // protocol definition is updated.
+    //
+    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);
+    if (Remainder != 0) {
+      NumberOfTicks += 1;
+    }
+    NumberOfTicks += 1;
+
+    while (NumberOfTicks != 0) {
+
+      mMetronome->WaitForTick (mMetronome, 1);
+
+      Status = This->Mem.Read (This, Width, Address, 1, Result);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+
+      if ((*Result & Mask) == Value) {
+        return EFI_SUCCESS;
+      }
+
+      NumberOfTicks -= 1;
+    }
+  }
+  return EFI_TIMEOUT;
+}
+
+/**
+   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
+   satisfied or after a defined duration.
+
+   This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
+   performed at the PCI I/O address specified by Address for the width specified by Width.
+   The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
+   repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
+   to Value.
+
+   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in] Width     Signifies the width of the I/O operations.
+   @param[in] Address   The base address of the I/O operations. The caller is responsible
+                        for aligning Address if required.
+   @param[in] Mask      Mask used for the polling criteria. Bytes above Width in Mask
+                        are ignored. The bits in the bytes below Width which are zero in
+                        Mask are ignored when polling the I/O address.
+   @param[in] Value     The comparison value used for the polling exit criteria.
+   @param[in] Delay     The number of 100 ns units to poll. Note that timer available may
+                        be of poorer granularity.
+   @param[out] Result   Pointer to the last value read from the memory location.
+
+   @retval EFI_SUCCESS            The last data returned from the access matched the poll exit criteria.
+   @retval EFI_INVALID_PARAMETER  Width is invalid.
+   @retval EFI_INVALID_PARAMETER  Result is NULL.
+   @retval EFI_TIMEOUT            Delay expired before a match occurred.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPollIo (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                                 Address,
+  IN  UINT64                                 Mask,
+  IN  UINT64                                 Value,
+  IN  UINT64                                 Delay,
+  OUT UINT64                                 *Result
+  )
+{
+  EFI_STATUS  Status;
+  UINT64      NumberOfTicks;
+  UINT32      Remainder;
+
+  //
+  // No matter what, always do a single poll.
+  //
+
+  if (Result == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = This->Io.Read (This, Width, Address, 1, Result);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  if ((*Result & Mask) == Value) {
+    return EFI_SUCCESS;
+  }
+
+  if (Delay == 0) {
+    return EFI_SUCCESS;
+
+  } else {
+
+    //
+    // Determine the proper # of metronome ticks to wait for polling the
+    // location.  The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
+    // The "+1" to account for the possibility of the first tick being short
+    // because we started in the middle of a tick.
+    //
+    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);
+    if (Remainder != 0) {
+      NumberOfTicks += 1;
+    }
+    NumberOfTicks += 1;
+
+    while (NumberOfTicks != 0) {
+
+      mMetronome->WaitForTick (mMetronome, 1);
+
+      Status = This->Io.Read (This, Width, Address, 1, Result);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+
+      if ((*Result & Mask) == Value) {
+        return EFI_SUCCESS;
+      }
+
+      NumberOfTicks -= 1;
+    }
+  }
+  return EFI_TIMEOUT;
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
+   registers in the PCI root bridge memory space.
+   The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+   any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operation.
+   @param[in]   Address   The base address of the memory operation. The caller is
+                          responsible for aligning the Address if required.
+   @param[in]   Count     The number of memory operations to perform. Bytes moved is
+                          Width size * Count, starting at Address.
+   @param[out]  Buffer    For read operations, the destination buffer to store the results. For
+                          write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  OUT    VOID                                   *Buffer
+  )
+{
+  return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
+   registers in the PCI root bridge memory space.
+   The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+   any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operation.
+   @param[in]   Address   The base address of the memory operation. The caller is
+                          responsible for aligning the Address if required.
+   @param[in]   Count     The number of memory operations to perform. Bytes moved is
+                          Width size * Count, starting at Address.
+   @param[in]   Buffer    For read operations, the destination buffer to store the results. For
+                          write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMemWrite (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  IN     VOID                                   *Buffer
+  )
+{
+  return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width       Signifies the width of the memory operations.
+   @param[in]   Address     The base address of the I/O operation. The caller is responsible for
+                            aligning the Address if required.
+   @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width
+                            size * Count, starting at Address.
+   @param[out]  Buffer      For read operations, the destination buffer to store the results. For
+                            write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoRead (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                 Address,
+  IN     UINTN                                  Count,
+  OUT    VOID                                   *Buffer
+  )
+{
+  return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
+
+   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width       Signifies the width of the memory operations.
+   @param[in]   Address     The base address of the I/O operation. The caller is responsible for
+                            aligning the Address if required.
+   @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width
+                            size * Count, starting at Address.
+   @param[in]   Buffer       For read operations, the destination buffer to store the results. For
+                            write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoIoWrite (
+  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *This,
+  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,
+  IN       UINT64                                  Address,
+  IN       UINTN                                   Count,
+  IN       VOID                                    *Buffer
+  )
+{
+  return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
+}
+
+/**
+   Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
+   root bridge memory space.
+
+   The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
+   space to another region of PCI root bridge memory space. This is especially useful for video scroll
+   operation on a memory mapped video buffer.
+   The memory operations are carried out exactly as requested. The caller is responsible for satisfying
+   any alignment and memory width restrictions that a PCI root bridge on a platform might require.
+
+   @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
+   @param[in] Width       Signifies the width of the memory operations.
+   @param[in] DestAddress The destination address of the memory operation. The caller is
+                          responsible for aligning the DestAddress if required.
+   @param[in] SrcAddress  The source address of the memory operation. The caller is
+                          responsible for aligning the SrcAddress if required.
+   @param[in] Count       The number of memory operations to perform. Bytes moved is
+                          Width size * Count, starting at DestAddress and SrcAddress.
+
+   @retval  EFI_SUCCESS             The data was copied from one memory region to another memory region.
+   @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.
+   @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoCopyMem (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,
+  IN UINT64                                       DestAddress,
+  IN UINT64                                       SrcAddress,
+  IN UINTN                                        Count
+  )
+{
+  EFI_STATUS  Status;
+  BOOLEAN     Direction;
+  UINTN       Stride;
+  UINTN       Index;
+  UINT64      Result;
+
+  if ((UINT32)Width > EfiPciWidthUint64) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (DestAddress == SrcAddress) {
+    return EFI_SUCCESS;
+  }
+
+  Stride = (UINTN)((UINTN)1 << Width);
+
+  Direction = TRUE;
+  if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {
+    Direction   = FALSE;
+    SrcAddress  = SrcAddress  + (Count-1) * Stride;
+    DestAddress = DestAddress + (Count-1) * Stride;
+  }
+
+  for (Index = 0;Index < Count;Index++) {
+    Status = RootBridgeIoMemRead (
+               This,
+               Width,
+               SrcAddress,
+               1,
+               &Result
+               );
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    Status = RootBridgeIoMemWrite (
+               This,
+               Width,
+               DestAddress,
+               1,
+               &Result
+               );
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    if (Direction) {
+      SrcAddress  += Stride;
+      DestAddress += Stride;
+    } else {
+      SrcAddress  -= Stride;
+      DestAddress -= Stride;
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Reads memory-mapped registers.
+  @param[in]  Width    Signifies the width of the I/O or Memory operation.
+  @param[in]  Address  The base address of the I/O operation.
+  @param[in]  Count    The number of I/O operations to perform. The number of
+                       bytes moved is Width size * Count, starting at Address.
+  @param[out] Buffer   For read operations, the destination buffer to store the results.
+                       For write operations, the source buffer from which to write data.
+
+  @retval EFI_SUCCESS            The data was read from or written to the PI system.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
+                                 and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+CpuMemoryServiceRead (
+  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                     Address,
+  IN  UINTN                      Count,
+  OUT VOID                       *Buffer
+  )
+{
+
+  UINT8                      InStride;
+  UINT8                      OutStride;
+  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
+  UINT8                      *Uint8Buffer;
+  UINT32                     Uint32Buffer = 0;
+
+  //
+  // Select loop based on the width of the transfer
+  //
+  InStride = mInStride[Width];
+  OutStride = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+    if (OperationWidth == EfiCpuIoWidthUint8) {
+      Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3)));
+      Uint32Buffer &= (0xFF << ((Address & 0x3) * 8));
+      *((UINT8*)Uint8Buffer) = (UINT8)(Uint32Buffer >> (((Address & 0x3) * 8)));
+    } else if (OperationWidth == EfiCpuIoWidthUint16) {
+      if (((Address & 0x3) == 1) || ((Address & 0x3) == 3)) {
+        return EFI_INVALID_PARAMETER;
+      }
+      Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3)));
+      Uint32Buffer &= (0xFFFF << ((Address & 0x3) * 8));
+      *(UINT16 *)Uint8Buffer = (UINT16)(Uint32Buffer >> (((Address & 0x3) * 8)));
+    } else if (OperationWidth == EfiCpuIoWidthUint32) {
+      *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+    } else if (OperationWidth == EfiCpuIoWidthUint64) {
+      *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+   The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
+   registers for a PCI controller.
+   The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
+   any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
+   require.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operations.
+   @param[in]   Address   The address within the PCI configuration space for the PCI controller.
+   @param[in]   Count     The number of PCI configuration operations to perform. Bytes
+                          moved is Width size * Count, starting at Address.
+   @param[out]  Buffer    For read operations, the destination buffer to store the results. For
+                          write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciRead (
+  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN       UINT64                                 EfiAddress,
+  IN       UINTN                                  Count,
+  OUT      VOID                                   *Buffer
+  )
+{
+  UINT32                      Offset;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress;
+  UINT64                      Address;
+  PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+
+  EfiPciAddress  = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress;
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (EfiPciAddress->ExtendedRegister) {
+    Offset = EfiPciAddress->ExtendedRegister;
+  } else {
+    Offset = EfiPciAddress->Register;
+  }
+
+  PCIE_DEBUG ("[%a:%d] - bus %x dev %x func %x Off %x\n", __FUNCTION__, __LINE__,
+         EfiPciAddress->Bus,
+         EfiPciAddress->Device,
+         EfiPciAddress->Function,
+         Offset
+        );
+  if (EfiPciAddress->Bus < PrivateData->BusBase || EfiPciAddress->Bus > PrivateData->BusLimit) {
+    PCIE_DEBUG ("[%a:%d] - Bus number out of range %d\n", __FUNCTION__, __LINE__, EfiPciAddress->Bus);
+    SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // The UEFI PCI enumerator scans for devices at all possible addresses,
+  // and ignores some PCI rules - this results in some hardware being
+  // detected multiple times. We work around this by faking absent
+  // devices
+  if(EfiPciAddress->Bus == PrivateData->BusBase)
+  {
+    if((EfiPciAddress->Device != 0x0) || (EfiPciAddress->Function != 0)) {
+      SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
+      return EFI_UNSUPPORTED;
+    }
+  }
+
+  if (EfiPciAddress->Bus == PrivateData->BusBase){
+    Address = PrivateData->RbPciBar + Offset;
+  }
+  else if(EfiPciAddress->Bus == PrivateData->BusBase + 1)
+  {
+    if (!PcieIsLinkUp(PrivateData->SocType,PrivateData->RbPciBar, PrivateData->Port))
+    {
+      SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
+      return EFI_NOT_READY;
+    }
+    Address = GetPcieCfgAddress (
+        PrivateData->Ecam,
+        EfiPciAddress->Bus,
+        EfiPciAddress->Device,
+        EfiPciAddress->Function,
+        Offset
+        );
+  }
+  else
+  {
+    Address = GetPcieCfgAddress (
+         PrivateData->Ecam,
+         EfiPciAddress->Bus,
+         EfiPciAddress->Device,
+         EfiPciAddress->Function,
+         Offset
+         );
+  }
+
+  (VOID)CpuMemoryServiceRead((EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);
+  PCIE_DEBUG ("[%a:%d] - %x\n", __FUNCTION__, __LINE__, *(UINT32 *)Buffer);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Writes memory-mapped registers.
+  @param[in]  Width    Signifies the width of the I/O or Memory operation.
+  @param[in]  Address  The base address of the I/O operation.
+  @param[in]  Count    The number of I/O operations to perform. The number of
+                       bytes moved is Width size * Count, starting at Address.
+  @param[in]  Buffer   For read operations, the destination buffer to store the results.
+                       For write operations, the source buffer from which to write data.
+
+  @retval EFI_SUCCESS            The data was read from or written to the PI system.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
+                                 and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+CpuMemoryServiceWrite (
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64                     Address,
+  IN UINTN                      Count,
+  IN VOID                       *Buffer
+  )
+{
+  UINT8                      InStride;
+  UINT8                      OutStride;
+  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
+  UINT8                      *Uint8Buffer;
+  UINT32                     Uint32Buffer;
+
+  //
+  // Select loop based on the width of the transfer
+  //
+  InStride = mInStride[Width];
+  OutStride = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+    if (OperationWidth == EfiCpuIoWidthUint8) {
+      Uint32Buffer = MmioRead32 ((UINTN)(Address & (~0x03)));
+      Uint32Buffer &= ~(UINT32)(0xFF << ((Address & 0x3) * 8));
+      Uint32Buffer |= (UINT32)(*(UINT8 *)Uint8Buffer) << ((Address & 0x3) * 8);
+      MmioWrite32 ((UINTN)(Address & (~0x03)), Uint32Buffer);
+    } else if (OperationWidth == EfiCpuIoWidthUint16) {
+      if (((Address & 0x3) == 1) || ((Address & 0x3) == 3)) {
+        return EFI_INVALID_PARAMETER;
+      }
+      Uint32Buffer = MmioRead32 ((UINTN)(Address & (~0x03)));
+      Uint32Buffer &= ~(UINT32)(0xFFFF << ((Address & 0x3) * 8));
+      Uint32Buffer |= (UINT32)(*(UINT16 *)Uint8Buffer) << ((Address & 0x3) * 8);
+      MmioWrite32 ((UINTN)(Address & (~0x03)), Uint32Buffer);
+    } else if (OperationWidth == EfiCpuIoWidthUint32) {
+      MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+    } else if (OperationWidth == EfiCpuIoWidthUint64) {
+      MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
+
+   The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
+   registers for a PCI controller.
+   The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
+   any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
+   require.
+
+   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]   Width     Signifies the width of the memory operations.
+   @param[in]   Address   The address within the PCI configuration space for the PCI controller.
+   @param[in]   Count     The number of PCI configuration operations to perform. Bytes
+                          moved is Width size * Count, starting at Address.
+   @param[in]   Buffer    For read operations, the destination buffer to store the results. For
+                          write operations, the source buffer to write data from.
+
+   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
+   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoPciWrite (
+  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
+  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
+  IN       UINT64                                 EfiAddress,
+  IN       UINTN                                  Count,
+  IN       VOID                                   *Buffer
+  )
+{
+  UINT32                      Offset;
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress;
+  UINT64                      Address;
+  PCI_ROOT_BRIDGE_INSTANCE    *PrivateData;
+
+  EfiPciAddress  = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress;
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Width >= EfiPciWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (EfiPciAddress->ExtendedRegister)
+    Offset = EfiPciAddress->ExtendedRegister;
+  else
+    Offset = EfiPciAddress->Register;
+
+  PCIE_DEBUG ("[%a:%d] - bus %x dev %x func %x Off %x\n", __FUNCTION__, __LINE__,
+         EfiPciAddress->Bus,
+         EfiPciAddress->Device,
+         EfiPciAddress->Function,
+         Offset
+        );
+  if (((EfiPciAddress->Bus == PrivateData->BusBase) && (EfiPciAddress->Device == 0x00) && (EfiPciAddress->Function == 0))){
+    Address = PrivateData->RbPciBar + Offset;
+    if ((Offset == 0x14) || (Offset == 0x10)) {
+      return EFI_SUCCESS;
+    }
+  }
+  else if (EfiPciAddress->Bus == PrivateData->BusBase + 1)
+  {
+     if (!PcieIsLinkUp(PrivateData->SocType,PrivateData->RbPciBar, PrivateData->Port)) {
+      return EFI_NOT_READY;
+    }
+    Address = GetPcieCfgAddress (
+        PrivateData->Ecam,
+        EfiPciAddress->Bus,
+        EfiPciAddress->Device,
+        EfiPciAddress->Function,
+        Offset
+    );
+  }
+  else
+  {
+    Address = GetPcieCfgAddress (
+       PrivateData->Ecam,
+       EfiPciAddress->Bus,
+       EfiPciAddress->Device,
+       EfiPciAddress->Function,
+       Offset
+       );
+  }
+
+  (VOID)CpuMemoryServiceWrite ((EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);
+  PCIE_DEBUG ("[%a:%d] - 0x%08x\n", __FUNCTION__, __LINE__, *(UINT32 *)Buffer);
+  return EFI_SUCCESS;
+}
+
+/**
+   Provides the PCI controller-specific addresses required to access system memory from a
+   DMA bus master.
+
+   The Map() function provides the PCI controller specific addresses needed to access system
+   memory. This function is used to map system memory for PCI bus master DMA accesses.
+
+   @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]       Operation       Indicates if the bus master is going to read or write to system memory.
+   @param[in]       HostAddress     The system memory address to map to the PCI controller.
+   @param[in, out]  NumberOfBytes   On input the number of bytes to map. On output the number of bytes that were mapped.
+   @param[out]      DeviceAddress   The resulting map address for the bus master PCI controller to use
+                                    to access the system memory's HostAddress.
+   @param[out]      Mapping         The value to pass to Unmap() when the bus master DMA operation is complete.
+
+   @retval EFI_SUCCESS            The range was mapped for the returned NumberOfBytes.
+   @retval EFI_INVALID_PARAMETER  Operation is invalid.
+   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.
+   @retval EFI_INVALID_PARAMETER  NumberOfBytes is NULL.
+   @retval EFI_INVALID_PARAMETER  DeviceAddress is NULL.
+   @retval EFI_INVALID_PARAMETER  Mapping is NULL.
+   @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.
+   @retval EFI_DEVICE_ERROR       The system hardware could not map the requested address.
+   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoMap (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
+  IN     VOID                                       *HostAddress,
+  IN OUT UINTN                                      *NumberOfBytes,
+  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
+  OUT    VOID                                       **Mapping
+  )
+{
+  DMA_MAP_OPERATION   DmaOperation;
+
+  if (Operation == EfiPciOperationBusMasterRead) {
+    DmaOperation = MapOperationBusMasterRead;
+  } else if (Operation == EfiPciOperationBusMasterWrite) {
+    DmaOperation = MapOperationBusMasterWrite;
+  } else if (Operation == EfiPciOperationBusMasterCommonBuffer) {
+    DmaOperation = MapOperationBusMasterCommonBuffer;
+  } else if (Operation == EfiPciOperationBusMasterRead64) {
+    DmaOperation = MapOperationBusMasterRead;
+  } else if (Operation == EfiPciOperationBusMasterWrite64) {
+     DmaOperation = MapOperationBusMasterWrite;
+  } else if (Operation == EfiPciOperationBusMasterCommonBuffer64) {
+    DmaOperation = MapOperationBusMasterCommonBuffer;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+  (VOID)DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
+  return EFI_SUCCESS;
+}
+
+/**
+   Completes the Map() operation and releases any corresponding resources.
+
+   The Unmap() function completes the Map() operation and releases any corresponding resources.
+   If the operation was an EfiPciOperationBusMasterWrite or
+   EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
+   Any resources used for the mapping are freed.
+
+   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in] Mapping   The mapping value returned from Map().
+
+   @retval EFI_SUCCESS            The range was unmapped.
+   @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().
+   @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoUnmap (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN VOID                             *Mapping
+  )
+{
+  return DmaUnmap (Mapping);
+}
+
+/**
+   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
+   EfiPciOperationBusMasterCommonBuffer64 mapping.
+
+   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param Type        This parameter is not used and must be ignored.
+   @param MemoryType  The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
+   @param Pages       The number of pages to allocate.
+   @param HostAddress A pointer to store the base system memory address of the allocated range.
+   @param Attributes  The requested bit mask of attributes for the allocated range. Only
+                      the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
+                      and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
+
+   @retval EFI_SUCCESS            The requested memory pages were allocated.
+   @retval EFI_INVALID_PARAMETER  MemoryType is invalid.
+   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.
+   @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal attribute bits are
+                                  MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
+   @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoAllocateBuffer (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  EFI_ALLOCATE_TYPE                Type,
+  IN  EFI_MEMORY_TYPE                  MemoryType,
+  IN  UINTN                            Pages,
+  OUT VOID                             **HostAddress,
+  IN  UINT64                           Attributes
+  )
+{
+  if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
+    return EFI_UNSUPPORTED;
+  }
+
+  return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
+
+}
+
+/**
+   Frees memory that was allocated with AllocateBuffer().
+
+   The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
+
+   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param Pages       The number of pages to free.
+   @param HostAddress The base system memory address of the allocated range.
+
+   @retval EFI_SUCCESS            The requested memory pages were freed.
+   @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and Pages
+                                  was not allocated with AllocateBuffer().
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFreeBuffer (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN  UINTN                            Pages,
+  OUT VOID                             *HostAddress
+  )
+{
+  return DmaFreeBuffer (Pages, HostAddress);
+}
+
+/**
+   Flushes all PCI posted write transactions from a PCI host bridge to system memory.
+
+   The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
+   memory. Posted write transactions are generated by PCI bus masters when they perform write
+   transactions to target addresses in system memory.
+   This function does not flush posted write transactions from any PCI bridges. A PCI controller
+   specific action must be taken to guarantee that the posted write transactions have been flushed from
+   the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
+   a PCI read transaction from the PCI controller prior to calling Flush().
+
+   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+
+   @retval EFI_SUCCESS        The PCI posted write transactions were flushed from the PCI host
+                              bridge to system memory.
+   @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed from the PCI
+                              host bridge due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoFlush (
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This
+  )
+{
+  //
+  // not supported yet
+  //
+  return EFI_SUCCESS;
+}
+
+/**
+   Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
+   attributes that a PCI root bridge is currently using.
+
+   The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
+   and the mask of attributes that the PCI root bridge is currently using.
+
+   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param Supported   A pointer to the mask of attributes that this PCI root bridge
+                      supports setting with SetAttributes().
+   @param Attributes  A pointer to the mask of attributes that this PCI root bridge is
+                      currently using.
+
+   @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI root
+                                  bridge supports is returned in Supports. If Attributes is
+                                  not NULL, then the attributes that the PCI root bridge is currently
+                                  using is returned in Attributes.
+   @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoGetAttributes (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  OUT UINT64                           *Supported,
+  OUT UINT64                           *Attributes
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
+
+  if (Attributes == NULL && Supported == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Set the return value for Supported and Attributes
+  //
+  if (Supported != NULL) {
+    *Supported  = PrivateData->Supports;
+  }
+
+  if (Attributes != NULL) {
+    *Attributes = PrivateData->Attributes;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+   Sets attributes for a resource range on a PCI root bridge.
+
+   The SetAttributes() function sets the attributes specified in Attributes for the PCI root
+   bridge on the resource range specified by ResourceBase and ResourceLength. Since the
+   granularity of setting these attributes may vary from resource type to resource type, and from
+   platform to platform, the actual resource range and the one passed in by the caller may differ. As a
+   result, this function may set the attributes specified by Attributes on a larger resource range
+   than the caller requested. The actual range is returned in ResourceBase and
+   ResourceLength. The caller is responsible for verifying that the actual range for which the
+   attributes were set is acceptable.
+
+   @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[in]       Attributes      The mask of attributes to set. If the attribute bit
+                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
+                                    MEMORY_DISABLE is set, then the resource range is specified by
+                                    ResourceBase and ResourceLength. If
+                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
+                                    MEMORY_DISABLE are not set, then ResourceBase and
+                                    ResourceLength are ignored, and may be NULL.
+   @param[in, out]  ResourceBase    A pointer to the base address of the resource range to be modified
+                                    by the attributes specified by Attributes.
+   @param[in, out]  ResourceLength  A pointer to the length of the resource range to be modified by the
+                                    attributes specified by Attributes.
+
+   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.
+   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
+   @retval  EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoSetAttributes (
+  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
+  IN     UINT64                           Attributes,
+  IN OUT UINT64                           *ResourceBase,
+  IN OUT UINT64                           *ResourceLength
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE            *PrivateData;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
+
+  if (Attributes != 0) {
+    if ((Attributes & (~(PrivateData->Supports))) != 0) {
+      return EFI_UNSUPPORTED;
+    }
+  }
+
+  //
+  // This is a generic driver for a PC-AT class system.  It does not have any
+  // chipset specific knowlegde, so none of the attributes can be set or
+  // cleared.  Any attempt to set attribute that are already set will succeed,
+  // and any attempt to set an attribute that is not supported will fail.
+  //
+  if (Attributes & (~PrivateData->Attributes)) {
+    /* FIXME: */
+    return EFI_UNSUPPORTED;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+   Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
+   resource descriptors.
+
+   There are only two resource descriptor types from the ACPI Specification that may be used to
+   describe the current resources allocated to a PCI root bridge. These are the QWORD Address
+   Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
+   QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
+   or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
+   Address Space Descriptors followed by an End Tag.
+
+   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+   @param[out]  Resources   A pointer to the ACPI 2.0 resource descriptors that describe the
+                            current configuration of this PCI root bridge. The storage for the
+                            ACPI 2.0 resource descriptors is allocated by this function. The
+                            caller must treat the return buffer as read-only data, and the buffer
+                            must not be freed by the caller.
+
+   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.
+   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
+   @retval  EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
+
+**/
+EFI_STATUS
+EFIAPI
+RootBridgeIoConfiguration (
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *This,
+  OUT VOID                                **Resources
+  )
+{
+  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;
+  UINTN                                 Index;
+
+  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+  for (Index = 0; Index < TypeMax; Index++) {
+    if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
+      Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
+      Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
+      Configuration.SpaceDesp[Index].AddrLen      = PrivateData->ResAllocNode[Index].Length;
+    }
+  }
+
+  *Resources = &Configuration;
+  return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c b/Chips/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c
new file mode 100644
index 0000000..18085c4
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c
@@ -0,0 +1,1049 @@
+/** @file
+
+  Copyright (c) 2016 Linaro Ltd.
+  Copyright (c) 2016 Hisilicon Limited.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/DmaLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UncachedMemoryAllocationLib.h>
+
+#include <Protocol/PlatformSasProtocol.h>
+#include <Protocol/ScsiPassThruExt.h>
+#include <IndustryStandard/Scsi.h>
+
+#define READ_REG32(Base, Offset) MmioRead32 ((Base) + (Offset))
+#define WRITE_REG32(Base, Offset, Val)  MmioWrite32 ((Base) + (Offset), (Val))
+
+#define PHY_READ_REG32(Base, Offset, phy) MmioRead32 ((Base) + (Offset) + 0x400 * (phy))
+#define PHY_WRITE_REG32(Base, Offset, phy, Val)  MmioWrite32 ((Base) + (Offset) + 0x400 * (phy), (Val))
+
+#define DLVRY_QUEUE_ENABLE              0x0
+#define IOST_BASE_ADDR_LO               0x8
+#define IOST_BASE_ADDR_HI               0xc
+#define ITCT_BASE_ADDR_LO               0x10
+#define ITCT_BASE_ADDR_HI               0x14
+#define BROKEN_MSG_ADDR_LO              0x18
+#define BROKEN_MSG_ADDR_HI              0x1c
+#define PHY_CONTEXT                     0x20
+#define PHY_PORT_NUM_MA                 0x28
+#define HGC_TRANS_TASK_CNT_LIMIT        0x38
+#define AXI_AHB_CLK_CFG                 0x3c
+#define HGC_SAS_TXFAIL_RETRY_CTRL       0x84
+#define HGC_GET_ITV_TIME                0x90
+#define DEVICE_MSG_WORK_MODE            0x94
+#define I_T_NEXUS_LOSS_TIME             0xa0
+#define BUS_INACTIVE_LIMIT_TIME         0xa8
+#define REJECT_TO_OPEN_LIMIT_TIME       0xac
+#define CFG_AGING_TIME                  0xbc
+#define HGC_DFX_CFG2                    0xc0
+#define FIS_LIST_BADDR_L                0xc4
+#define CFG_1US_TIMER_TRSH              0xcc
+#define CFG_SAS_CONFIG                  0xd4
+#define INT_COAL_EN                     0x1bc
+#define OQ_INT_COAL_TIME                0x1c0
+#define OQ_INT_COAL_CNT                 0x1c4
+#define ENT_INT_COAL_TIME               0x1c8
+#define ENT_INT_COAL_CNT                0x1cc
+#define OQ_INT_SRC                      0x1d0
+#define OQ_INT_SRC_MSK                  0x1d4
+#define ENT_INT_SRC1                    0x1d8
+#define ENT_INT_SRC2                    0x1dc
+#define ENT_INT_SRC_MSK1                0x1e0
+#define ENT_INT_SRC_MSK2                0x1e4
+#define SAS_ECC_INTR_MSK                0x1ec
+#define HGC_ERR_STAT_EN                 0x238
+#define DLVRY_Q_0_BASE_ADDR_LO          0x260
+#define DLVRY_Q_0_BASE_ADDR_HI          0x264
+#define DLVRY_Q_0_DEPTH                 0x268
+#define DLVRY_Q_0_WR_PTR                0x26c
+#define DLVRY_Q_0_RD_PTR                0x270
+#define COMPL_Q_0_BASE_ADDR_LO          0x4e0
+#define COMPL_Q_0_BASE_ADDR_HI          0x4e4
+#define COMPL_Q_0_DEPTH                 0x4e8
+#define COMPL_Q_0_WR_PTR                0x4ec
+#define COMPL_Q_0_RD_PTR                0x4f0
+#define AXI_CFG                         0x5100
+
+#define PORT_BASE                       0x800
+#define PHY_CFG                         (PORT_BASE + 0x0)
+#define PHY_CFG_ENA_OFF                 0
+#define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
+#define PHY_CFG_DC_OPT_OFF              2
+#define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
+#define PROG_PHY_LINK_RATE              (PORT_BASE + 0xc)
+#define PHY_CTRL                        (PORT_BASE + 0x14)
+#define PHY_CTRL_RESET                  BIT0
+#define PHY_RATE_NEGO                   (PORT_BASE + 0x30)
+#define PHY_PCN                         (PORT_BASE + 0x44)
+#define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
+#define SL_CONTROL                      (PORT_BASE + 0x94)
+#define SL_CONTROL_NOTIFY_EN            BIT0
+#define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
+#define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
+#define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
+#define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
+#define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
+#define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
+#define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
+#define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
+#define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
+#define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
+#define DONE_RECEIVED_TIME              (PORT_BASE + 0x12c)
+#define CON_CFG_DRIVER                  (PORT_BASE + 0x130)
+#define PHY_CONFIG2                     (PORT_BASE + 0x1a8)
+#define PHY_CONFIG2_FORCE_TXDEEMPH_OFF  3
+#define PHY_CONFIG2_FORCE_TXDEEMPH_MSK  (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
+#define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
+#define CHL_INT0                        (PORT_BASE + 0x1b0)
+#define CHL_INT0_PHYCTRL_NOTRDY         BIT0
+#define CHL_INT1                        (PORT_BASE + 0x1b4)
+#define CHL_INT2                        (PORT_BASE + 0x1b8)
+#define CHL_INT2_SL_PHY_ENA             BIT6
+#define CHL_INT0_MSK                    (PORT_BASE + 0x1bc)
+#define CHL_INT0_MSK_PHYCTRL_NOTRDY     BIT0
+#define CHL_INT1_MSK                    (PORT_BASE + 0x1c0)
+#define CHL_INT2_MSK                    (PORT_BASE + 0x1c4)
+#define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
+#define DMA_TX_STATUS_BUSY              BIT0
+#define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
+#define DMA_RX_STATUS_BUSY              BIT0
+
+#define QUEUE_CNT                       32
+#define QUEUE_SLOTS                     256
+#define SLOT_ENTRIES                    8192
+#define PHY_CNT                         8
+#define MAX_ITCT_ENTRIES                1
+
+// Completion header
+#define CMPLT_HDR_IPTT_OFF              0
+#define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
+
+#define BIT(x)                          (1 << x)
+
+// HW dma structures
+// Delivery queue header
+// dw0
+#define CMD_HDR_RESP_REPORT_OFF     5
+#define CMD_HDR_RESP_REPORT_MSK     0x20
+#define CMD_HDR_TLR_CTRL_OFF        6
+#define CMD_HDR_TLR_CTRL_MSK        0xc0
+#define CMD_HDR_PORT_OFF            17
+#define CMD_HDR_PORT_MSK            0xe0000
+#define CMD_HDR_PRIORITY_OFF        27
+#define CMD_HDR_PRIORITY_MSK        0x8000000
+#define CMD_HDR_MODE_OFF            28
+#define CMD_HDR_MODE_MSK            0x10000000
+#define CMD_HDR_CMD_OFF             29
+#define CMD_HDR_CMD_MSK             0xe0000000
+// dw1
+#define CMD_HDR_VERIFY_DTL_OFF      10
+#define CMD_HDR_VERIFY_DTL_MSK      0x400
+#define CMD_HDR_SSP_FRAME_TYPE_OFF  13
+#define CMD_HDR_SSP_FRAME_TYPE_MSK  0xe000
+#define CMD_HDR_DEVICE_ID_OFF       16
+#define CMD_HDR_DEVICE_ID_MSK       0xffff0000
+// dw2
+#define CMD_HDR_CFL_OFF             0
+#define CMD_HDR_CFL_MSK             0x1ff
+#define CMD_HDR_MRFL_OFF            15
+#define CMD_HDR_MRFL_MSK            0xff8000
+#define CMD_HDR_FIRST_BURST_OFF     25
+#define CMD_HDR_FIRST_BURST_MSK     0x2000000
+// dw3
+#define CMD_HDR_IPTT_OFF            0
+#define CMD_HDR_IPTT_MSK            0xffff
+// dw6
+#define CMD_HDR_DATA_SGL_LEN_OFF    16
+#define CMD_HDR_DATA_SGL_LEN_MSK    0xffff0000
+
+// Completion header
+#define CMPLT_HDR_IPTT_OFF          0
+#define CMPLT_HDR_IPTT_MSK          (0xffff << CMPLT_HDR_IPTT_OFF)
+#define CMPLT_HDR_CMD_CMPLT_MSK     BIT17
+#define CMPLT_HDR_ERR_RCRD_XFRD_MSK BIT18
+#define CMPLT_HDR_RSPNS_XFRD_MSK    BIT19
+#define CMPLT_HDR_IO_CFG_ERR_MSK    BIT27
+
+#define SENSE_DATA_PRES             26
+
+#define SGE_LIMIT 0x10000
+#define upper_32_bits(n) ((UINT32)(((n) >> 16) >> 16))
+#define lower_32_bits(n) ((UINT32)(n))
+#define MAX_TARGET_ID 4
+
+// Generic HW DMA host memory structures
+struct hisi_sas_cmd_hdr {
+    UINT32 dw0;
+    UINT32 dw1;
+    UINT32 dw2;
+    UINT32 transfer_tags;
+    UINT32 data_transfer_len;
+    UINT32 first_burst_num;
+    UINT32 sg_len;
+    UINT32 dw7;
+    UINT64 cmd_table_addr;
+    UINT64 sts_buffer_addr;
+    UINT64 prd_table_addr;
+    UINT64 dif_prd_table_addr;
+};
+
+struct hisi_sas_complete_hdr {
+    UINT32 data;
+};
+
+struct hisi_sas_iost {
+    UINT64 qw0;
+    UINT64 qw1;
+    UINT64 qw2;
+    UINT64 qw3;
+};
+
+struct hisi_sas_itct {
+    UINT64 qw0;
+    UINT64 sas_addr;
+    UINT64 qw2;
+    UINT64 qw3;
+    UINT64 qw4;
+    UINT64 qw_sata_ncq0_3;
+    UINT64 qw_sata_ncq7_4;
+    UINT64 qw_sata_ncq11_8;
+    UINT64 qw_sata_ncq15_12;
+    UINT64 qw_sata_ncq19_16;
+    UINT64 qw_sata_ncq23_20;
+    UINT64 qw_sata_ncq27_24;
+    UINT64 qw_sata_ncq31_28;
+    UINT64 qw_non_ncq_iptt;
+    UINT64 qw_rsvd0;
+    UINT64 qw_rsvd1;
+};
+
+struct hisi_sas_breakpoint {
+    UINT8 data[128];
+};
+
+struct hisi_sas_sge {
+    UINT64 addr;
+    UINT32 page_ctrl_0;
+    UINT32 page_ctrl_1;
+    UINT32 data_len;
+    UINT32 data_off;
+};
+
+struct hisi_sas_sge_page {
+    struct hisi_sas_sge sg[512];
+};
+
+struct hisi_sas_cmd {
+    UINT8 cmd[128];
+};
+
+struct hisi_sas_sts {
+UINT32 status[260];
+};
+
+struct hisi_sas_slot {
+    BOOLEAN used;
+};
+
+struct hisi_hba {
+    struct hisi_sas_cmd_hdr      *cmd_hdr[QUEUE_CNT];
+    struct hisi_sas_complete_hdr *complete_hdr[QUEUE_CNT];
+    struct hisi_sas_sge_page     *sge[QUEUE_CNT];
+    struct hisi_sas_sts          *status_buf[QUEUE_CNT];
+    struct hisi_sas_cmd          *command_table[QUEUE_CNT];
+    struct hisi_sas_iost         *iost;
+    struct hisi_sas_itct         *itct;
+    struct hisi_sas_breakpoint   *breakpoint;
+    struct hisi_sas_slot         *slots;
+    UINT32 base;
+    int queue;
+    int port_id;
+    UINT32 LatestTargetId;
+    UINT64 LatestLun;
+};
+
+#pragma pack (1)
+typedef struct {
+  VENDOR_DEVICE_PATH                  Vendor;
+  UINT64                              PhysBase;
+  EFI_DEVICE_PATH_PROTOCOL            End;
+} SAS_V1_TRANSPORT_DEVICE_PATH;
+#pragma pack ()
+
+typedef struct {
+    UINT32 Signature;
+    EFI_EXT_SCSI_PASS_THRU_MODE     ExtScsiPassThruMode;
+    EFI_EXT_SCSI_PASS_THRU_PROTOCOL ExtScsiPassThru;
+    SAS_V1_TRANSPORT_DEVICE_PATH    *DevicePath;
+    struct hisi_hba *hba;
+    EFI_EVENT TimerEvent;
+} SAS_V1_INFO;
+
+#define SAS_DEVICE_SIGNATURE SIGNATURE_32 ('S','A','S','0')
+#define SAS_FROM_PASS_THRU(a) CR (a, SAS_V1_INFO, ExtScsiPassThru, SAS_DEVICE_SIGNATURE)
+
+STATIC EFI_STATUS prepare_cmd (
+  struct hisi_hba *hba,
+  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
+  )
+{
+  struct hisi_sas_slot *slot;
+  struct hisi_sas_cmd_hdr *hdr;
+  struct hisi_sas_sge_page *sge;
+  struct hisi_sas_sts *sts;
+  struct hisi_sas_cmd *cmd;
+  EFI_SCSI_SENSE_DATA *SensePtr = Packet->SenseData;
+  VOID   *Buffer = NULL;
+  UINTN BufferSize = 0;
+  int queue = hba->queue;
+  UINT32 r, w = 0, slot_idx = 0;
+  UINT32 base = hba->base;
+  UINT8 *p;
+  EFI_PHYSICAL_ADDRESS  BufferAddress;
+  EFI_STATUS            Status = EFI_SUCCESS;
+  VOID                  *BufferMap = NULL;
+  DMA_MAP_OPERATION DmaOperation = MapOperationBusMasterCommonBuffer;
+
+  while (1) {
+    w = READ_REG32(base, DLVRY_Q_0_WR_PTR + (queue * 0x14));
+    r = READ_REG32(base, DLVRY_Q_0_RD_PTR + (queue * 0x14));
+    slot_idx = queue * QUEUE_SLOTS + w;
+    slot = &hba->slots[slot_idx];
+    if (slot->used || (r == (w+1) % QUEUE_SLOTS)) {
+      queue = (queue + 1) % QUEUE_CNT;
+      if (queue == hba->queue) {
+        DEBUG ((EFI_D_ERROR, "could not find free slot\n"));
+        return EFI_NOT_READY;
+      }
+      continue;
+    }
+    break;
+  }
+
+  hdr = &hba->cmd_hdr[queue][w];
+  cmd = &hba->command_table[queue][w];
+  sts = &hba->status_buf[queue][w];
+  sge = &hba->sge[queue][w];
+
+  ZeroMem (cmd, sizeof (struct hisi_sas_cmd));
+  ZeroMem (sts, sizeof (struct hisi_sas_sts));
+  if (SensePtr)
+    ZeroMem (SensePtr, sizeof (EFI_SCSI_SENSE_DATA));
+
+  slot->used = TRUE;
+  hba->queue = (queue + 1) % QUEUE_CNT;
+
+  // Only consider ssp
+  hdr->dw0 = (1 << CMD_HDR_RESP_REPORT_OFF) |
+       (0x2 << CMD_HDR_TLR_CTRL_OFF) |
+       (hba->port_id << CMD_HDR_PORT_OFF) |
+       (1 << CMD_HDR_MODE_OFF) |
+       (1 << CMD_HDR_CMD_OFF);
+  hdr->dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
+  hdr->dw1 |= 0 << CMD_HDR_DEVICE_ID_OFF;
+  hdr->dw2 = 0x83000d;
+  hdr->transfer_tags = slot_idx << CMD_HDR_IPTT_OFF;
+
+  if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
+    Buffer = Packet->InDataBuffer;
+    BufferSize = Packet->InTransferLength;
+    if (Buffer) {
+      hdr->dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
+      DmaOperation = MapOperationBusMasterWrite;
+    }
+  } else if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_WRITE) {
+    Buffer = Packet->OutDataBuffer;
+    BufferSize = Packet->OutTransferLength;
+    if (Buffer) {
+      DmaOperation = MapOperationBusMasterRead;
+      hdr->dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
+    }
+  } else {
+    hdr->dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
+  }
+
+  hdr->data_transfer_len = BufferSize;
+  hdr->cmd_table_addr = (UINT64)cmd;
+  hdr->sts_buffer_addr = (UINT64)sts;
+
+  CopyMem (&cmd->cmd[36], Packet->Cdb, Packet->CdbLength);
+
+  if (Buffer != NULL) {
+    struct hisi_sas_sge *sg;
+    UINT32 remain, len, pos = 0, i = 0;
+
+    Status = DmaMap (DmaOperation, Buffer, &BufferSize, &BufferAddress, &BufferMap);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    remain = len = BufferSize;
+
+    while (remain) {
+      if (len > SGE_LIMIT)
+        len = SGE_LIMIT;
+      sg = &sge->sg[i];
+      sg->addr = (UINT64)(BufferAddress + pos);
+      sg->page_ctrl_0 = sg->page_ctrl_1 = 0;
+      sg->data_len = len;
+      sg->data_off = 0;
+      remain -= len;
+      pos += len;
+      len = remain;
+      i++;
+    }
+
+    hdr->prd_table_addr = (UINT64)sge;
+    hdr->sg_len = i << CMD_HDR_DATA_SGL_LEN_OFF;
+  }
+
+  // Ensure descriptor effective before start dma
+  MemoryFence();
+
+  // Start dma
+  WRITE_REG32(base, DLVRY_Q_0_WR_PTR + queue * 0x14, ++w % QUEUE_SLOTS);
+
+  // Wait for dma complete
+  while (slot->used) {
+    if (READ_REG32(base, OQ_INT_SRC) & BIT(queue)) {
+      struct hisi_sas_complete_hdr *complete_hdr;
+      UINT32 data, rd;
+      rd = READ_REG32(base, COMPL_Q_0_RD_PTR + (0x14 * queue));
+
+      complete_hdr = &hba->complete_hdr[queue][rd];
+      data = complete_hdr->data;
+
+      // Check whether dma transfer error
+      if ((data & CMPLT_HDR_ERR_RCRD_XFRD_MSK) &&
+        !(data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
+        DEBUG ((EFI_D_VERBOSE, "sas retry data=0x%x\n", data));
+        DEBUG ((EFI_D_VERBOSE, "sts[0]=0x%x\n", sts->status[0]));
+        DEBUG ((EFI_D_VERBOSE, "sts[1]=0x%x\n", sts->status[1]));
+        DEBUG ((EFI_D_VERBOSE, "sts[2]=0x%x\n", sts->status[2]));
+        Status = EFI_NOT_READY;
+        // wait 1 second and retry, some disk need long time to be ready
+        // and ScsiDisk treat retry over 3 times as error
+        MicroSecondDelay(1000000);
+      }
+       // Update read point
+       WRITE_REG32(base, COMPL_Q_0_RD_PTR + (0x14 * queue), w);
+       // Clear int
+       WRITE_REG32(base, OQ_INT_SRC, BIT(queue));
+       slot->used = FALSE;
+       break;
+    }
+    // Wait for status change in polling
+    NanoSecondDelay (100);
+  }
+
+  if (BufferMap)
+       DmaUnmap (BufferMap);
+
+  p = (UINT8 *)&sts->status[0];
+  if (p[SENSE_DATA_PRES]) {
+    // Disk not ready normal return for ScsiDiskTestUnitReady do next try
+    SensePtr->Sense_Key = EFI_SCSI_SK_NOT_READY;
+    SensePtr->Addnl_Sense_Code = EFI_SCSI_ASC_NOT_READY;
+    SensePtr->Addnl_Sense_Code_Qualifier = EFI_SCSI_ASCQ_IN_PROGRESS;
+    // wait 1 second for disk spin up, refer drivers/scsi/sd.c
+    MicroSecondDelay(1000000);
+  }
+  return Status;
+}
+
+STATIC VOID hisi_sas_v1_init(struct hisi_hba *hba, PLATFORM_SAS_PROTOCOL *plat)
+{
+  int i, j;
+  UINT32 val, base = hba->base;
+
+  // Reset
+  for (i = 0; i < PHY_CNT; i++) {
+    UINT32 phy_ctrl = PHY_READ_REG32(base, PHY_CTRL, i);
+
+    phy_ctrl |= PHY_CTRL_RESET;
+    PHY_WRITE_REG32(base, PHY_CTRL, i, phy_ctrl);
+  }
+  // spec says safe to wait 50us after reset
+  MicroSecondDelay(50);
+
+  // Ensure DMA tx & rx idle
+  for (i = 0; i < PHY_CNT; i++) {
+    UINT32 dma_tx_status, dma_rx_status;
+
+    for (j = 0; j < 100; j++) {
+      dma_tx_status = PHY_READ_REG32(base, DMA_TX_STATUS, i);
+      dma_rx_status = PHY_READ_REG32(base, DMA_RX_STATUS, i);
+
+      if (!(dma_tx_status & DMA_TX_STATUS_BUSY) &&
+        !(dma_rx_status & DMA_RX_STATUS_BUSY))
+        break;
+
+        // Wait for status change in polling
+        NanoSecondDelay (100);
+    }
+  }
+
+  // Ensure axi bus idle
+  for (j = 0; j < 100; j++) {
+    UINT32 axi_status = READ_REG32(base, AXI_CFG);
+    if (axi_status == 0)
+      break;
+
+    // Wait for status change in polling
+    NanoSecondDelay (100);
+  }
+
+  plat->Init(plat);
+
+  WRITE_REG32(base, DLVRY_QUEUE_ENABLE, 0xffffffff);
+  WRITE_REG32(base, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
+  WRITE_REG32(base, DEVICE_MSG_WORK_MODE, 0x1);
+  WRITE_REG32(base, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
+  WRITE_REG32(base, HGC_ERR_STAT_EN, 0x401);
+  WRITE_REG32(base, CFG_1US_TIMER_TRSH, 0x64);
+  WRITE_REG32(base, HGC_GET_ITV_TIME, 0x1);
+  WRITE_REG32(base, I_T_NEXUS_LOSS_TIME, 0x64);
+  WRITE_REG32(base, BUS_INACTIVE_LIMIT_TIME, 0x2710);
+  WRITE_REG32(base, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
+  WRITE_REG32(base, CFG_AGING_TIME, 0x7a12);
+  WRITE_REG32(base, HGC_DFX_CFG2, 0x9c40);
+  WRITE_REG32(base, FIS_LIST_BADDR_L, 0x2);
+  WRITE_REG32(base, INT_COAL_EN, 0xc);
+  WRITE_REG32(base, OQ_INT_COAL_TIME, 0x186a0);
+  WRITE_REG32(base, OQ_INT_COAL_CNT, 1);
+  WRITE_REG32(base, ENT_INT_COAL_TIME, 0x1);
+  WRITE_REG32(base, ENT_INT_COAL_CNT, 0x1);
+  WRITE_REG32(base, OQ_INT_SRC, 0xffffffff);
+  WRITE_REG32(base, ENT_INT_SRC1, 0xffffffff);
+  WRITE_REG32(base, ENT_INT_SRC_MSK1, 0);
+  WRITE_REG32(base, ENT_INT_SRC2, 0xffffffff);
+  WRITE_REG32(base, ENT_INT_SRC_MSK2, 0);
+  WRITE_REG32(base, SAS_ECC_INTR_MSK, 0);
+  WRITE_REG32(base, AXI_AHB_CLK_CFG, 0x2);
+  WRITE_REG32(base, CFG_SAS_CONFIG, 0x22000000);
+
+  for (i = 0; i < PHY_CNT; i++) {
+    PHY_WRITE_REG32(base, PROG_PHY_LINK_RATE, i, 0x88a);
+    PHY_WRITE_REG32(base, PHY_CONFIG2, i, 0x7c080);
+    PHY_WRITE_REG32(base, PHY_RATE_NEGO, i, 0x415ee00);
+    PHY_WRITE_REG32(base, PHY_PCN, i, 0x80a80000);
+    PHY_WRITE_REG32(base, SL_TOUT_CFG, i, 0x7d7d7d7d);
+    PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 0x0);
+    PHY_WRITE_REG32(base, RXOP_CHECK_CFG_H, i, 0x1000);
+    PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 0);
+    PHY_WRITE_REG32(base, CON_CFG_DRIVER, i, 0x13f0a);
+    PHY_WRITE_REG32(base, CHL_INT_COAL_EN, i, 3);
+    PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 8);
+  }
+
+  for (i = 0; i < QUEUE_CNT; i++) {
+    WRITE_REG32(base, DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), upper_32_bits((UINT64)(hba->cmd_hdr[i])));
+    WRITE_REG32(base, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), lower_32_bits((UINT64)(hba->cmd_hdr[i])));
+    WRITE_REG32(base, DLVRY_Q_0_DEPTH + (i * 0x14), QUEUE_SLOTS);
+
+    WRITE_REG32(base, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), upper_32_bits((UINT64)(hba->complete_hdr[i])));
+    WRITE_REG32(base, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), lower_32_bits((UINT64)(hba->complete_hdr[i])));
+    WRITE_REG32(base, COMPL_Q_0_DEPTH + (i * 0x14), QUEUE_SLOTS);
+  }
+
+  WRITE_REG32(base, ITCT_BASE_ADDR_LO, lower_32_bits((UINT64)(hba->itct)));
+  WRITE_REG32(base, ITCT_BASE_ADDR_HI, upper_32_bits((UINT64)(hba->itct)));
+
+  WRITE_REG32(base, IOST_BASE_ADDR_LO, lower_32_bits((UINT64)(hba->iost)));
+  WRITE_REG32(base, IOST_BASE_ADDR_HI, upper_32_bits((UINT64)(hba->iost)));
+
+  WRITE_REG32(base, BROKEN_MSG_ADDR_LO, lower_32_bits((UINT64)(hba->breakpoint)));
+  WRITE_REG32(base, BROKEN_MSG_ADDR_HI, upper_32_bits((UINT64)(hba->breakpoint)));
+
+  for (i = 0; i < PHY_CNT; i++) {
+    // Clear interrupt status
+    val = PHY_READ_REG32(base, CHL_INT0, i);
+    PHY_WRITE_REG32(base, CHL_INT0, i, val);
+    val = PHY_READ_REG32(base, CHL_INT1, i);
+    PHY_WRITE_REG32(base, CHL_INT1, i, val);
+    val = PHY_READ_REG32(base, CHL_INT2, i);
+    PHY_WRITE_REG32(base, CHL_INT2, i, val);
+
+    // Bypass chip bug mask abnormal intr
+    PHY_WRITE_REG32(base, CHL_INT0_MSK, i, 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY);
+  }
+
+  // Init phy
+  for (i = 0; i < PHY_CNT; i++) {
+    PHY_WRITE_REG32(base, TX_ID_DWORD0, i, 0x10010e00);
+    PHY_WRITE_REG32(base, TX_ID_DWORD1, i, 0x16);
+    PHY_WRITE_REG32(base, TX_ID_DWORD2, i, 0x20880150);
+    PHY_WRITE_REG32(base, TX_ID_DWORD3, i, 0x16);
+    PHY_WRITE_REG32(base, TX_ID_DWORD4, i, 0x20880150);
+    PHY_WRITE_REG32(base, TX_ID_DWORD5, i, 0x0);
+
+    val = PHY_READ_REG32(base, PHY_CFG, i);
+    val &= ~PHY_CFG_DC_OPT_MSK;
+    val |= 1 << PHY_CFG_DC_OPT_OFF;
+    PHY_WRITE_REG32(base, PHY_CFG, i, val);
+
+    val = PHY_READ_REG32(base, PHY_CONFIG2, i);
+    val &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
+    PHY_WRITE_REG32(base, PHY_CONFIG2, i, val);
+
+    val = PHY_READ_REG32(base, PHY_CFG, i);
+    val |= PHY_CFG_ENA_MSK;
+    PHY_WRITE_REG32(base, PHY_CFG, i, val);
+  }
+}
+
+STATIC VOID sas_init(SAS_V1_INFO *SasV1Info, PLATFORM_SAS_PROTOCOL *plat)
+{
+  struct hisi_hba *hba = SasV1Info->hba;
+  int i, s;
+
+  for (i = 0; i < QUEUE_CNT; i++) {
+    s = sizeof(struct hisi_sas_cmd_hdr) * QUEUE_SLOTS;
+    DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->cmd_hdr[i]);
+    ASSERT (hba->cmd_hdr[i] != NULL);
+    ZeroMem (hba->cmd_hdr[i], s);
+
+    s = sizeof(struct hisi_sas_complete_hdr) * QUEUE_SLOTS;
+    DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->complete_hdr[i]);
+    ASSERT (hba->complete_hdr[i] != NULL);
+    ZeroMem (hba->complete_hdr[i], s);
+
+    s = sizeof(struct hisi_sas_sts) * QUEUE_SLOTS;
+    DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->status_buf[i]);
+    ASSERT (hba->status_buf[i] != NULL);
+    ZeroMem (hba->status_buf[i], s);
+
+    s = sizeof(struct hisi_sas_cmd) * QUEUE_SLOTS;
+    DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->command_table[i]);
+    ASSERT (hba->command_table[i] != NULL);
+    ZeroMem (hba->command_table[i], s);
+
+    s = sizeof(struct hisi_sas_sge_page) * QUEUE_SLOTS;
+    DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->sge[i]);
+    ASSERT (hba->sge[i] != NULL);
+    ZeroMem (hba->sge[i], s);
+  }
+
+  s = SLOT_ENTRIES * sizeof(struct hisi_sas_iost);
+  DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->iost);
+  ASSERT (hba->iost != NULL);
+  ZeroMem (hba->iost, s);
+
+  s = SLOT_ENTRIES * sizeof(struct hisi_sas_breakpoint);
+  DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->breakpoint);
+  ASSERT (hba->breakpoint != NULL);
+  ZeroMem (hba->breakpoint, s);
+
+  s = MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
+  DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->itct);
+  ASSERT (hba->itct != NULL);
+  ZeroMem (hba->itct, s);
+
+  hba->slots = AllocateZeroPool (SLOT_ENTRIES * sizeof(struct hisi_sas_slot));
+  ASSERT (hba->slots != NULL);
+
+  hisi_sas_v1_init(hba, plat);
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+SasV1ExtScsiPassThruFunction (
+  IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL                    *This,
+  IN UINT8                                              *Target,
+  IN UINT64                                             Lun,
+  IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET     *Packet,
+  IN EFI_EVENT                                          Event OPTIONAL
+  )
+{
+  SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This);
+  struct hisi_hba *hba = SasV1Info->hba;
+
+  return prepare_cmd(hba, Packet);
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+SasV1ExtScsiPassThruGetNextTargetLun (
+  IN  EFI_EXT_SCSI_PASS_THRU_PROTOCOL    *This,
+  IN OUT UINT8                           **Target,
+  IN OUT UINT64                          *Lun
+  )
+{
+  SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This);
+  struct hisi_hba *hba = SasV1Info->hba;
+  UINT8 ScsiId[TARGET_MAX_BYTES];
+  UINT8 TargetId;
+
+  if (*Target == NULL || Lun == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  SetMem (ScsiId, TARGET_MAX_BYTES, 0xFF);
+
+  TargetId = (*Target)[0];
+
+  if (TargetId == MAX_TARGET_ID) {
+    return EFI_NOT_FOUND;
+  }
+
+  if (CompareMem(*Target, ScsiId, TARGET_MAX_BYTES) == 0) {
+    SetMem (*Target, TARGET_MAX_BYTES,0);
+  } else {
+    (*Target)[0] = (UINT8) (hba->LatestTargetId + 1);
+  }
+
+  *Lun = 0;
+
+  //
+  // Update the LatestTargetId.
+  //
+  hba->LatestTargetId  = (*Target)[0];
+  hba->LatestLun       = *Lun;
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+SasV1ExtScsiPassThruBuildDevicePath (
+  IN     EFI_EXT_SCSI_PASS_THRU_PROTOCOL    *This,
+  IN     UINT8                              *Target,
+  IN     UINT64                             Lun,
+  IN OUT EFI_DEVICE_PATH_PROTOCOL           **DevicePath
+  )
+{
+  SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This);
+
+  *DevicePath  = DuplicateDevicePath ((EFI_DEVICE_PATH_PROTOCOL *)(SasV1Info->DevicePath));
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+SasV1ExtScsiPassThruGetTargetLun (
+  IN  EFI_EXT_SCSI_PASS_THRU_PROTOCOL    *This,
+  IN  EFI_DEVICE_PATH_PROTOCOL           *DevicePath,
+  OUT UINT8                              **Target,
+  OUT UINT64                             *Lun
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+SasV1ExtScsiPassThruResetChannel (
+  IN  EFI_EXT_SCSI_PASS_THRU_PROTOCOL   *This
+  )
+{
+
+  return EFI_UNSUPPORTED;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+SasV1ExtScsiPassThruResetTarget (
+  IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL    *This,
+  IN UINT8                              *Target,
+  IN UINT64                             Lun
+  )
+{
+
+  return EFI_UNSUPPORTED;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+SasV1ExtScsiPassThruGetNextTarget (
+  IN  EFI_EXT_SCSI_PASS_THRU_PROTOCOL    *This,
+  IN OUT UINT8                           **Target
+  )
+{
+
+  return EFI_UNSUPPORTED;
+}
+
+STATIC EFI_EXT_SCSI_PASS_THRU_PROTOCOL SasV1ExtScsiPassThruProtocolTemplate = {
+  NULL,
+  SasV1ExtScsiPassThruFunction,
+  SasV1ExtScsiPassThruGetNextTargetLun,
+  SasV1ExtScsiPassThruBuildDevicePath,
+  SasV1ExtScsiPassThruGetTargetLun,
+  SasV1ExtScsiPassThruResetChannel,
+  SasV1ExtScsiPassThruResetTarget,
+  SasV1ExtScsiPassThruGetNextTarget
+};
+
+EFI_STATUS
+EFIAPI
+SasDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL    *This,
+  IN EFI_HANDLE                     Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
+  )
+{
+  PLATFORM_SAS_PROTOCOL *plat;
+  EFI_STATUS Status;
+
+  Status = gBS->OpenProtocol (
+                Controller,
+                &gPlatformSasProtocolGuid,
+                (VOID **) &plat,
+                This->DriverBindingHandle,
+                Controller,
+                EFI_OPEN_PROTOCOL_BY_DRIVER
+                );
+  if (Status == EFI_ALREADY_STARTED) {
+    return EFI_SUCCESS;
+  }
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Close the Sas Host used to perform the supported test
+  //
+  gBS->CloseProtocol (
+      Controller,
+      &gPlatformSasProtocolGuid,
+      This->DriverBindingHandle,
+      Controller
+      );
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SasDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  )
+{
+  EFI_STATUS Status;
+  PLATFORM_SAS_PROTOCOL *plat;
+  SAS_V1_INFO *SasV1Info = NULL;
+  SAS_V1_TRANSPORT_DEVICE_PATH  *DevicePath;
+  UINT32 val, base;
+  int i, phy_id = 0;
+  struct hisi_sas_itct *itct;
+  struct hisi_hba *hba;
+
+  Status = gBS->OpenProtocol (
+                Controller,
+                &gPlatformSasProtocolGuid,
+                (VOID **) &plat,
+                This->DriverBindingHandle,
+                Controller,
+                EFI_OPEN_PROTOCOL_BY_DRIVER
+                );
+
+  if (EFI_ERROR (Status)) {
+    if (Status == EFI_ALREADY_STARTED) {
+      return EFI_SUCCESS;
+    }
+    return Status;
+  }
+
+  SasV1Info = AllocateZeroPool (sizeof (SAS_V1_INFO));
+  ASSERT (SasV1Info);
+  SasV1Info->Signature = SAS_DEVICE_SIGNATURE;
+
+  SasV1Info->hba = AllocateZeroPool (sizeof(struct hisi_hba));
+  ASSERT (SasV1Info->hba);
+  hba = SasV1Info->hba;
+  base = hba->base = plat->BaseAddr;
+
+  sas_init(SasV1Info, plat);
+
+  // Wait for sas controller phyup happen
+  MicroSecondDelay(100000);
+
+  for (i = 0; i < PHY_CNT; i++) {
+    val = PHY_READ_REG32(base, CHL_INT2, i);
+
+    if (val & CHL_INT2_SL_PHY_ENA) {
+      phy_id = i;
+    }
+  }
+
+  itct = &hba->itct[0]; //device_id = 0
+
+  hba->port_id = (READ_REG32(base, PHY_PORT_NUM_MA) >> (4 * phy_id)) & 0xf;
+  // Setup itct
+  itct->qw0 = 0x355;
+  itct->sas_addr = PHY_READ_REG32(base, RX_IDAF_DWORD3, phy_id);
+  itct->sas_addr = itct->sas_addr << 32 | PHY_READ_REG32(base, RX_IDAF_DWORD4, phy_id);
+  itct->qw2 = 0;
+
+  // Clear phyup
+  PHY_WRITE_REG32(base, CHL_INT2, phy_id, CHL_INT2_SL_PHY_ENA);
+  val = PHY_READ_REG32(base, CHL_INT0, phy_id);
+  val &= ~CHL_INT0_PHYCTRL_NOTRDY;
+  PHY_WRITE_REG32(base, CHL_INT0, phy_id, val);
+  PHY_WRITE_REG32(base, CHL_INT0_MSK, phy_id, 0x3ce3ee);
+
+  // Need notify
+  val = PHY_READ_REG32(base, SL_CONTROL, phy_id);
+  val |= SL_CONTROL_NOTIFY_EN;
+  PHY_WRITE_REG32(base, SL_CONTROL, phy_id, val);
+  // wait 100ms required for notify takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+  MicroSecondDelay(100000);
+  val = PHY_READ_REG32(base, SL_CONTROL, phy_id);
+  val &= ~SL_CONTROL_NOTIFY_EN;
+  PHY_WRITE_REG32(base, SL_CONTROL, phy_id, val);
+
+  CopyMem (&SasV1Info->ExtScsiPassThru, &SasV1ExtScsiPassThruProtocolTemplate, sizeof (EFI_EXT_SCSI_PASS_THRU_PROTOCOL));
+  SasV1Info->ExtScsiPassThruMode.AdapterId = 2;
+  SasV1Info->ExtScsiPassThruMode.Attributes = EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL | EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL;
+  SasV1Info->ExtScsiPassThruMode.IoAlign  = 64; //cache line align
+  SasV1Info->ExtScsiPassThru.Mode = &SasV1Info->ExtScsiPassThruMode;
+
+  DevicePath = (SAS_V1_TRANSPORT_DEVICE_PATH *)CreateDeviceNode (
+                                               HARDWARE_DEVICE_PATH,
+                                               HW_VENDOR_DP,
+                                               sizeof (SAS_V1_TRANSPORT_DEVICE_PATH));
+  ASSERT (DevicePath != NULL);
+  SasV1Info->DevicePath = DevicePath;
+
+  CopyMem (&DevicePath->Vendor.Guid, &gPlatformSasProtocolGuid, sizeof (EFI_GUID));
+  DevicePath->PhysBase = base;
+  SetDevicePathNodeLength (&DevicePath->Vendor,
+                           sizeof (*DevicePath) - sizeof (DevicePath->End));
+  SetDevicePathEndNode (&DevicePath->End);
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                &Controller,
+                &gEfiDevicePathProtocolGuid, DevicePath,
+                &gEfiExtScsiPassThruProtocolGuid, &SasV1Info->ExtScsiPassThru,
+                NULL);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SasDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
+  IN  EFI_HANDLE                    Controller,
+  IN  UINTN                         NumberOfChildren,
+  IN  EFI_HANDLE                    *ChildHandleBuffer
+  )
+{
+  SAS_V1_INFO *SasV1Info;
+  EFI_STATUS Status;
+  EFI_EXT_SCSI_PASS_THRU_PROTOCOL *ExtScsi;
+  int i, s;
+
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiExtScsiPassThruProtocolGuid,
+                  (VOID **) &ExtScsi,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  SasV1Info = SAS_FROM_PASS_THRU(ExtScsi);
+
+  Status = gBS->UninstallMultipleProtocolInterfaces (
+                Controller,
+                &gEfiDevicePathProtocolGuid,
+                SasV1Info->DevicePath,
+                &gEfiExtScsiPassThruProtocolGuid,
+                &SasV1Info->ExtScsiPassThru,
+                NULL);
+  if (!EFI_ERROR (Status)) {
+    gBS->CloseProtocol (
+           Controller,
+           &gPlatformSasProtocolGuid,
+           This->DriverBindingHandle,
+           Controller
+           );
+
+    gBS->CloseEvent (SasV1Info->TimerEvent);
+
+    for (i = 0; i < QUEUE_CNT; i++) {
+      s = sizeof(struct hisi_sas_cmd_hdr) * QUEUE_SLOTS;
+      DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->cmd_hdr[i]);
+      s = sizeof(struct hisi_sas_complete_hdr) * QUEUE_SLOTS;
+      DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->complete_hdr[i]);
+      s = sizeof(struct hisi_sas_sts) * QUEUE_SLOTS;
+      DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->status_buf[i]);
+      s = sizeof(struct hisi_sas_cmd) * QUEUE_SLOTS;
+      DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->command_table[i]);
+      s = sizeof(struct hisi_sas_sge_page) * QUEUE_SLOTS;
+      DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->sge[i]);
+    }
+
+    s = SLOT_ENTRIES * sizeof(struct hisi_sas_iost);
+    DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->iost);
+    s = SLOT_ENTRIES * sizeof(struct hisi_sas_breakpoint);
+    DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->breakpoint);
+    s = MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
+    DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->itct);
+
+    FreePool (SasV1Info->hba->slots);
+    FreePool (SasV1Info->hba);
+    FreePool (SasV1Info);
+    return EFI_SUCCESS;
+  }
+  return Status;
+}
+
+EFI_DRIVER_BINDING_PROTOCOL gSasDriverBinding = {
+  SasDriverBindingSupported,
+  SasDriverBindingStart,
+  SasDriverBindingStop,
+  0xa,
+  NULL,
+  NULL
+};
+
+EFI_STATUS
+SasV1Initialize (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  return EfiLibInstallDriverBindingComponentName2 (
+           ImageHandle,
+           SystemTable,
+           &gSasDriverBinding,
+           ImageHandle,
+           NULL,
+           NULL
+           );
+}
diff --git a/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/OmapDmaLib.inf b/Chips/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf
index 1893adf..48f5188 100755..100644
--- a/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/OmapDmaLib.inf
+++ b/Chips/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf
@@ -1,6 +1,7 @@
 #/** @file
 #
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#  Copyright (c) 2016 Linaro Ltd.
+#  Copyright (c) 2016 Hisilicon Limited.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
@@ -13,38 +14,33 @@
 
 [Defines]
   INF_VERSION                    = 0x00010005
-  BASE_NAME                      = OmapDmaLib
-  FILE_GUID                      = 09B17D99-BB07-49a8-B0D2-06D6AFCBE3AB
+  BASE_NAME                      = SasV1Dxe
+  FILE_GUID                      = 2b235921-8405-4219-a461-972a3a60969c
   MODULE_TYPE                    = UEFI_DRIVER
   VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = OmapDmaLib
+
+  ENTRY_POINT                    = SasV1Initialize
 
 
 [Sources.common]
-  OmapDmaLib.c
+  SasV1Dxe.c
 
 [Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
   ArmPkg/ArmPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
 
 [LibraryClasses]
-  DebugLib
-  UefiBootServicesTableLib
+  DmaLib
+  IoLib
   MemoryAllocationLib
+  PcdLib
+  TimerLib
+  UefiDriverEntryPoint
+  UefiLib
   UncachedMemoryAllocationLib
-  IoLib
-  BaseMemoryLib
-  ArmLib
-
 
 [Protocols]
-  gEfiCpuArchProtocolGuid
-
-[Guids]
-
-[Pcd]
-
-[Depex]
-  gEfiCpuArchProtocolGuid
+  gEfiExtScsiPassThruProtocolGuid
+  gPlatformSasProtocolGuid
diff --git a/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
new file mode 100644
index 0000000..8d8dacd
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
@@ -0,0 +1,205 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "AddSmbiosType9.h"
+
+extern SMBIOS_TABLE_TYPE9 gPcieSlotInfo[];
+extern UINT8 OemGetPcieSlotNumber ();
+
+REPORT_PCIEDIDVID2BMC  PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
+      {67,0,0,0},
+      {225,0,0,3},
+      {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+      {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+VOID
+EFIAPI
+UpdateSmbiosType9Info(
+  IN OUT SMBIOS_TABLE_TYPE9             *Type9Record
+)
+{
+    EFI_STATUS                         Status;
+    UINTN                              HandleIndex;
+    EFI_HANDLE                        *HandleBuffer;
+    UINTN                              HandleCount;
+    EFI_PCI_IO_PROTOCOL               *PciIo;
+    UINTN                              SegmentNumber;
+    UINTN                              BusNumber;
+    UINTN                              DeviceNumber;
+    UINTN                              FunctionNumber;
+    UINTN                              Index;
+    REPORT_PCIEDIDVID2BMC              ReportPcieDidVid[PCIEDEVICE_REPORT_MAX];
+    if(OemIsMpBoot()){
+        (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport_2P,sizeof(PcieDeviceToReport_2P));
+    } else {
+        (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport,sizeof(PcieDeviceToReport));
+    }
+    Status = gBS->LocateHandleBuffer (
+                                      ByProtocol,
+                                      &gEfiPciIoProtocolGuid,
+                                      NULL,
+                                      &HandleCount,
+                                      &HandleBuffer
+                                      );
+    if(EFI_ERROR(Status)) {
+        DEBUG((EFI_D_ERROR, " Locate gEfiPciIoProtocol Failed.\n"));
+        gBS->FreePool ((VOID *)HandleBuffer);
+        return;
+    }
+    for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
+        Status = gBS->HandleProtocol (
+                                        HandleBuffer[HandleIndex],
+                                        &gEfiPciIoProtocolGuid,
+                                        (VOID **)&PciIo
+                                        );
+        if (EFI_ERROR (Status)) {
+            DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status));
+            continue;
+        }
+        (VOID)PciIo->GetLocation(PciIo, &SegmentNumber, &BusNumber, &DeviceNumber, &FunctionNumber);
+        for(Index = 0; Index < sizeof(ReportPcieDidVid) / sizeof(REPORT_PCIEDIDVID2BMC); Index++){
+            if (Type9Record->SlotID == ReportPcieDidVid[Index].Slot + 1) {
+                if((BusNumber == ReportPcieDidVid[Index].Bus) && (DeviceNumber == ReportPcieDidVid[Index].Device)) {
+                    DEBUG((EFI_D_ERROR,"PCIe device plot in slot Seg %d  bdf %d %d %d\r\n",SegmentNumber,BusNumber,DeviceNumber,FunctionNumber));
+                    Type9Record->SegmentGroupNum   = SegmentNumber;
+                    Type9Record->BusNum            = BusNumber;
+                    Type9Record->DevFuncNum        = (DeviceNumber << 3) | FunctionNumber;
+                    Type9Record->CurrentUsage      = SlotUsageInUse;
+                    break;
+                }
+            }
+        }
+    }
+    gBS->FreePool ((VOID *)HandleBuffer);
+    return;
+}
+EFI_STATUS
+EFIAPI
+AddSmbiosType9Entry (
+  IN EFI_HANDLE            ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+{
+    EFI_STATUS                          Status;
+    EFI_SMBIOS_TYPE                     SmbiosType;
+    EFI_SMBIOS_HANDLE                   SmbiosHandle;
+    EFI_SMBIOS_PROTOCOL                 *Smbios;
+    EFI_SMBIOS_TABLE_HEADER             *Record;
+    SMBIOS_TABLE_TYPE9                  *Type9Record;
+    SMBIOS_TABLE_TYPE9                  *SmbiosRecord = NULL;
+    CHAR8                              *OptionalStrStart;
+
+    UINT8                               SmbiosAddType9Number;
+    UINT8                               Index;
+
+    CHAR16                              *SlotDesignation = NULL;
+    UINTN                               SlotDesignationStrLen;
+
+    Status = gBS->LocateProtocol (
+                  &gEfiSmbiosProtocolGuid,
+                  NULL,
+                  (VOID **) &Smbios
+                  );
+    if (EFI_ERROR (Status)) {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol Failed. Status : %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    do {
+        SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+        SmbiosType = EFI_SMBIOS_TYPE_SYSTEM_SLOTS;
+        Status = Smbios->GetNext (Smbios, &SmbiosHandle, &SmbiosType, &Record, NULL);
+        if (!EFI_ERROR(Status)) {
+            Status = Smbios->Remove (Smbios, SmbiosHandle);
+            if (EFI_ERROR(Status)) {
+                DEBUG((EFI_D_ERROR, "[%a]:[%dL] Remove System Slot Failed. Status : %r\n", __FUNCTION__, __LINE__, Status));
+                break;
+            }
+        }
+    } while (SmbiosHandle != SMBIOS_HANDLE_PI_RESERVED);
+
+    SmbiosAddType9Number = OemGetPcieSlotNumber();
+
+    for (Index = 0; Index < SmbiosAddType9Number; Index++)
+    {
+        if (gPcieSlotInfo[Index].Hdr.Type != EFI_SMBIOS_TYPE_SYSTEM_SLOTS)
+        {
+            continue;
+        }
+
+        Type9Record = &gPcieSlotInfo[Index];
+
+        UpdateSmbiosType9Info (Type9Record);
+        SlotDesignation = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+        if (NULL == SlotDesignation)
+        {
+            Status = EFI_OUT_OF_RESOURCES;
+            DEBUG((EFI_D_ERROR, "[%a]:[%dL] AllocateZeroPool Failed. Status : %r\n", __FUNCTION__, __LINE__, Status));
+
+            goto Exit;
+        }
+
+        SlotDesignationStrLen = UnicodeSPrint (SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE Slot%d", Type9Record->SlotID);
+
+        //
+        // Two zeros following the last string.
+        //
+        SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE9) + SlotDesignationStrLen + 1 + 1);
+        if(NULL == SmbiosRecord)
+        {
+            Status = EFI_OUT_OF_RESOURCES;
+            DEBUG((EFI_D_ERROR, "[%a]:[%dL] AllocateZeroPool Failed. Status : %r\n", __FUNCTION__, __LINE__, Status));
+
+            goto Exit;
+        }
+
+        (VOID)CopyMem(SmbiosRecord, Type9Record, sizeof (SMBIOS_TABLE_TYPE9));
+
+        SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9);
+
+        OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+        UnicodeStrToAsciiStr(SlotDesignation, OptionalStrStart);
+
+        //
+        // Now we have got the full smbios record, call smbios protocol to add this record.
+        //
+        SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+        Status = Smbios->Add (Smbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)SmbiosRecord);
+        if(EFI_ERROR(Status))
+        {
+            DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type09 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+            goto Exit;
+        }
+
+        FreePool(SmbiosRecord);
+        FreePool(SlotDesignation);
+    }
+
+    return EFI_SUCCESS;
+
+Exit:
+    if(SmbiosRecord != NULL)
+    {
+        FreePool(SmbiosRecord);
+    }
+
+    if(SlotDesignation != NULL)
+    {
+        FreePool(SlotDesignation);
+    }
+
+    return Status;
+}
+
diff --git a/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.h b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.h
index 0748ddf..5766152 100755..100644
--- a/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.h
+++ b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.h
@@ -1,6 +1,7 @@
 /** @file
 *
-*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -12,33 +13,24 @@
 *
 **/
 
-#ifndef _MMC_HOST_DXE_H_
-#define _MMC_HOST_DXE_H_
 
-#include <Uefi.h>
+#ifndef _ADD_SMBIOS_TYPE9_H_
+#define _ADD_SMBIOS_TYPE9_H_
 
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/SmBios.h>
+#include <Protocol/Smbios.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
 #include <Library/BaseLib.h>
-#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
 #include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PrintLib.h>
 #include <Library/UefiBootServicesTableLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/OmapLib.h>
-#include <Library/OmapDmaLib.h>
-#include <Library/DmaLib.h>
-
-#include <Protocol/EmbeddedExternalDevice.h>
-#include <Protocol/BlockIo.h>
-#include <Protocol/DevicePath.h>
-#include <Protocol/MmcHost.h>
-
-#include <Omap3530/Omap3530.h>
-#include <TPS65950.h>
-
-#define MAX_RETRY_COUNT  (100*5)
-
-extern EFI_BLOCK_IO_PROTOCOL gBlockIo;
+#include <Library/MemoryAllocationLib.h>
+#include <Library/OemMiscLib.h>
 
 #endif
diff --git a/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
new file mode 100644
index 0000000..a90399b
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AddSmbiosType9
+  FILE_GUID                      = 7AE6F104-66DF-48EF-B5A3-5050BF4908F0
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = AddSmbiosType9Entry
+
+[Sources]
+  AddSmbiosType9.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  MemoryAllocationLib
+  DebugLib
+  UefiLib
+  UefiDriverEntryPoint
+  OemMiscLib
+
+[Protocols]
+  gEfiSmbiosProtocolGuid
+  gEfiPciIoProtocolGuid
+
+[Guids]
+
+[Pcd]
+
+[Depex]
+  gEfiSmbiosProtocolGuid AND
+  gEfiPciIoProtocolGuid
diff --git a/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
new file mode 100644
index 0000000..da714c9
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
@@ -0,0 +1,762 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include "MemorySubClass.h"
+
+EFI_SMBIOS_PROTOCOL             *mSmbios = NULL;
+EFI_HII_HANDLE                  mHiiHandle;
+
+UINT8                           mMaxSkt;
+UINT8                           mMaxCh;
+
+VOID
+SmbiosGetManufacturer (
+  IN  UINT8           MfgIdLSB,
+  IN  UINT8           MfgIdMSB,
+  OUT CHAR16          *Manufacturer
+)
+{
+    UINT32                  Index = 0;
+
+    (VOID)StrCpyS(Manufacturer, SMBIOS_STRING_MAX_LENGTH - 1, L"Unknown");
+    while (JEP106[Index].MfgIdLSB != 0xFF && JEP106[Index].MfgIdMSB != 0xFF )
+    {
+        if (JEP106[Index].MfgIdLSB == MfgIdLSB && JEP106[Index].MfgIdMSB == MfgIdMSB)
+        {
+            (VOID)StrCpyS (Manufacturer, SMBIOS_STRING_MAX_LENGTH - 1, JEP106[Index].Name);
+            break;
+        }
+        Index++;
+    }
+}
+
+VOID
+SmbiosGetPartNumber (
+  IN pGBL_DATA          pGblData,
+  IN UINT8              Skt,
+  IN UINT8              Ch,
+  IN UINT8              Dimm,
+  OUT CHAR16             *PartNumber
+  )
+{
+    CHAR16                        StringBuffer2[SMBIOS_STRING_MAX_LENGTH];
+    UINT32                        Index2;
+
+    (VOID)StrCpyS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, L"");
+    if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3)
+    {
+        for (Index2 = 0; Index2 < SPD_MODULE_PART; Index2++)
+        {
+            UnicodeSPrint (StringBuffer2, SMBIOS_STRING_MAX_LENGTH - 1, L"%c", pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdModPart[Index2]);
+            (VOID)StrCatS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, StringBuffer2);
+        }
+    }
+    else
+    {
+        for (Index2 = 0; Index2 < SPD_MODULE_PART_DDR4; Index2++)
+        {
+            UnicodeSPrint (StringBuffer2, SMBIOS_STRING_MAX_LENGTH - 1, L"%c", pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdModPartDDR4[Index2]);
+            (VOID)StrCatS(PartNumber, SMBIOS_STRING_MAX_LENGTH - 1, StringBuffer2);
+        }
+    }
+
+    return;
+}
+
+VOID
+SmbiosGetSerialNumber (
+  IN pGBL_DATA          pGblData,
+  IN UINT8              Skt,
+  IN UINT8              Ch,
+  IN UINT8              Dimm,
+  OUT CHAR16            *SerialNumber
+  )
+{
+    UINT32              Temp;
+
+    Temp = SwapBytes32 (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdSerialNum);
+
+    UnicodeSPrint(SerialNumber, SMBIOS_STRING_MAX_LENGTH, L"0x%08x", Temp);
+
+    return;
+}
+
+BOOLEAN
+IsDimmPresent (
+  IN  pGBL_DATA          pGblData,
+  IN  UINT8              Skt,
+  IN  UINT8              Ch,
+  IN  UINT8              Dimm
+)
+{
+    if (pGblData->Channel[Skt][Ch].Status == FALSE ||
+          pGblData->Channel[Skt][Ch].Dimm[Dimm].Status == FALSE)
+    {
+        return FALSE;
+    }
+    else
+    {
+        return TRUE;
+    }
+}
+
+UINT8
+SmbiosGetMemoryType (
+  IN  pGBL_DATA          pGblData,
+  IN  UINT8              Skt,
+  IN  UINT8              Ch,
+  IN  UINT8              Dimm
+)
+{
+    UINT8 MemoryType;
+
+    if(!IsDimmPresent(pGblData, Skt, Ch, Dimm))
+    {
+        return MemoryTypeUnknown;
+    }
+
+    if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3)
+    {
+        MemoryType = MemoryTypeDdr3;
+    }
+    else if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR4)
+    {
+        MemoryType = MemoryTypeDdr4;
+    }
+    else
+    {
+        MemoryType = MemoryTypeUnknown;
+    }
+
+    return MemoryType;
+}
+
+VOID
+SmbiosGetTypeDetail (
+  IN  pGBL_DATA             pGblData,
+  IN  UINT8                 Skt,
+  IN  UINT8                 Ch,
+  IN  UINT8                 Dimm,
+  IN  OUT MEMORY_DEVICE_TYPE_DETAIL *TypeDetail
+)
+{
+    if (NULL == TypeDetail)
+    {
+        return;
+    }
+
+    if(!IsDimmPresent(pGblData, Skt, Ch, Dimm))
+    {
+        TypeDetail->Unknown = 1;
+        return;
+    }
+
+    switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].ModuleType)
+    {
+        case SPD_UDIMM:
+          TypeDetail->Unbuffered = 1;
+          break;
+
+        case SPD_LRDIMM:
+          TypeDetail->LrDimm = 1;
+          break;
+
+        case SPD_RDIMM:
+          TypeDetail->Registered = 1;
+          break;
+
+        default:
+          TypeDetail->Unknown = 1;
+          break;
+    }
+}
+
+VOID
+SmbiosGetDimmVoltageInfo (
+  IN     pGBL_DATA             pGblData,
+  IN     UINT8                 Skt,
+  IN     UINT8                 Ch,
+  IN     UINT8                 Dimm,
+  IN OUT SMBIOS_TABLE_TYPE17   *Type17Record
+
+)
+{
+    if(!IsDimmPresent(pGblData, Skt, Ch, Dimm))
+    {
+        return;
+    }
+
+    if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR3)
+    {
+        Type17Record->MinimumVoltage                = 1250;
+        Type17Record->MaximumVoltage                = 1500;
+
+        switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdVdd)
+        {
+            case SPD_VDD_150:
+              Type17Record->ConfiguredVoltage = 1500;
+              break;
+
+            case SPD_VDD_135:
+              Type17Record->ConfiguredVoltage = 1350;
+              break;
+
+            case SPD_VDD_125:
+              Type17Record->ConfiguredVoltage = 1250;
+              break;
+
+            default:
+              break;
+        }
+    }
+    else if (pGblData->Channel[Skt][Ch].Dimm[Dimm].DramType == SPD_TYPE_DDR4)
+    {
+        Type17Record->MinimumVoltage                = 1200;
+        Type17Record->MaximumVoltage                = 2000;
+        switch (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdVdd)
+        {
+            case SPD_VDD_120:
+              Type17Record->ConfiguredVoltage = 1200;
+              break;
+
+            default:
+              break;
+        }
+    }
+}
+
+VOID
+SmbiosGetMemoryDevicesNumber (
+  IN OUT UINT16 *NumberOfDevices
+)
+{
+    UINT8       Skt, Ch, Dimm;
+
+    for(Skt = 0; Skt < mMaxSkt; Skt++)
+    {
+        for(Ch = 0; Ch < mMaxCh; Ch++)
+        {
+            for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++)
+            {
+                (*NumberOfDevices)++;
+            }
+        }
+    }
+}
+
+UINT8
+SmbiosGetPartitionWidth (
+)
+{
+
+    UINT8       Skt, Ch, Dimm;
+    UINT8       PartitionWidth = 0;
+
+    for(Skt = 0; Skt < mMaxSkt; Skt++)
+    {
+        for(Ch = 0; Ch < mMaxCh; Ch++)
+        {
+            for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++)
+            {
+                PartitionWidth++;
+            }
+        }
+    }
+
+    return PartitionWidth;
+}
+
+EFI_STATUS
+SmbiosAddType16Table (
+  IN  pGBL_DATA          pGblData,
+  OUT EFI_SMBIOS_HANDLE  *MemArraySmbiosHandle
+  )
+{
+    EFI_STATUS                      Status;
+    UINT64                          MemoryCapacity;
+    SMBIOS_TABLE_TYPE16             *Type16Record;
+
+    UINT16                          NumberOfMemoryDevices = 0;
+
+    SmbiosGetMemoryDevicesNumber (&NumberOfMemoryDevices);
+
+    MemoryCapacity = (UINT64) LShiftU64 (NumberOfMemoryDevices * MAX_DIMM_SIZE, 20); // GB to KB.
+
+    //
+    // Type 16 SMBIOS Record
+    //
+    Type16Record = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE16) + 1 + 1);
+    if (NULL == Type16Record)
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+    Type16Record->Hdr.Type                          = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY;
+    Type16Record->Hdr.Length                        = sizeof (SMBIOS_TABLE_TYPE16);
+    Type16Record->Hdr.Handle                        = 0x0;
+    Type16Record->Location                          = MemoryArrayLocationSystemBoard;
+    Type16Record->Use                               = MemoryArrayUseSystemMemory;
+    Type16Record->MemoryErrorInformationHandle      = 0xFFFE;
+    Type16Record->NumberOfMemoryDevices             = NumberOfMemoryDevices;
+
+    if(pGblData->EccEn)
+    {
+        Type16Record->MemoryErrorCorrection         = MemoryErrorCorrectionSingleBitEcc;
+    }
+    else
+    {
+        Type16Record->MemoryErrorCorrection         = MemoryErrorCorrectionNone;
+    }
+
+    if (MemoryCapacity >= 0x80000000)
+    {
+        Type16Record->MaximumCapacity = 0x80000000;   // in KB;
+        Type16Record->ExtendedMaximumCapacity = MemoryCapacity << 10;  // Extended Max capacity should be stored in bytes.
+    }
+    else
+    {
+        Type16Record->MaximumCapacity = (UINT32)MemoryCapacity;  // Max capacity should be stored in kilo bytes.
+        Type16Record->ExtendedMaximumCapacity = 0;
+    }
+
+    *MemArraySmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+    Status = mSmbios->Add (mSmbios, NULL, MemArraySmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type16Record);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type16 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(Type16Record);
+    return Status;
+}
+
+EFI_STATUS
+SmbiosAddType19Table (
+  IN pGBL_DATA          pGblData,
+  IN EFI_SMBIOS_HANDLE  MemArraySmbiosHandle
+  )
+{
+    EFI_STATUS                      Status;
+    UINT32                          MemInfoTotalMem;
+    UINT64                          TotalMemorySize;
+    EFI_SMBIOS_HANDLE               MemArrayMappedAddrSmbiosHandle;
+    SMBIOS_TABLE_TYPE19             *Type19Record;
+
+    MemInfoTotalMem = pGblData->MemSize;  // In MB
+
+    if (MemInfoTotalMem == 0)
+    {
+        return EFI_NOT_FOUND;
+    }
+
+    TotalMemorySize = (UINT64) LShiftU64 (MemInfoTotalMem, 10);  // MB to KB.
+
+    //
+    // Type 19 SMBIOS Record
+    //
+    Type19Record = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE19) + 1 + 1);
+    if (NULL == Type19Record)
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+    Type19Record->Hdr.Type                          = EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS;
+    Type19Record->Hdr.Length                        = sizeof(SMBIOS_TABLE_TYPE19);
+    Type19Record->Hdr.Handle                        = 0x0;
+    Type19Record->StartingAddress                   = 0x0;
+    Type19Record->EndingAddress                     = (UINT32) (TotalMemorySize - 1); // in KB;
+    Type19Record->MemoryArrayHandle                 = MemArraySmbiosHandle;
+    Type19Record->PartitionWidth                    = SmbiosGetPartitionWidth ();
+    Type19Record->ExtendedStartingAddress           = 0x0;
+    Type19Record->ExtendedEndingAddress             = 0x0;
+
+    MemArrayMappedAddrSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+    Status = mSmbios->Add (mSmbios, NULL, &MemArrayMappedAddrSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type19Record);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type19 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(Type19Record);
+    return Status;
+}
+
+
+EFI_STATUS
+SmbiosAddType17Table (
+  IN pGBL_DATA          pGblData,
+  IN UINT8              Skt,
+  IN UINT8              Ch,
+  IN UINT8              Dimm,
+  IN EFI_SMBIOS_HANDLE  MemArraySmbiosHandle
+  )
+{
+    EFI_STATUS                      Status;
+    SMBIOS_TABLE_TYPE17             *Type17Record;
+    EFI_SMBIOS_HANDLE               MemDevSmbiosHandle;
+    UINTN                           TableSize;
+
+    UINTN                           StringBufferSize;
+    EFI_STRING                      StringBuffer;
+    UINT16                          MemInfoMemFreq;
+    UINT16                          MemoryTotalWidth;
+    UINT16                          MemoryDataWidth;
+    UINT16                          MemoryDeviceSize;
+    UINT16                          MemorySpeed;
+    UINT8                           Attributes;
+    UINT32                          MemoryDeviceExtendSize;
+    UINT16                          CfgMemorySpeed;
+
+    CHAR8                           *OptionalStrStart;
+    UINTN                           DeviceLocatorStrLen;
+    UINTN                           BankLocatorStrLen;
+    UINTN                           ManufactureStrLen;
+    UINTN                           SerialNumberStrLen;
+    UINTN                           AssertTagStrLen;
+    UINTN                           PartNumberStrLen;
+    EFI_STRING                      DeviceLocatorStr;
+    EFI_STRING                      BankLocatorStr;
+    EFI_STRING                      ManufactureStr;
+    EFI_STRING                      SerialNumberStr;
+    EFI_STRING                      AssertTagStr;
+    EFI_STRING                      PartNumberStr;
+    EFI_STRING_ID                   DeviceLocator;
+
+    Type17Record        = NULL;
+    DeviceLocatorStr    = NULL;
+    BankLocatorStr      = NULL;
+    ManufactureStr      = NULL;
+    SerialNumberStr     = NULL;
+    AssertTagStr        = NULL;
+    PartNumberStr       = NULL;
+
+    MemoryTotalWidth    = 0;
+    MemoryDataWidth     = 0;
+    MemoryDeviceSize    = 0;
+    MemoryDeviceExtendSize = 0;
+    MemorySpeed         = 0;
+    Attributes          = 0;
+    CfgMemorySpeed      = 0;
+
+    //
+    // Allocate Buffers
+    //
+    StringBufferSize = (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH;
+    StringBuffer = AllocateZeroPool (StringBufferSize);
+    if(NULL == StringBuffer)
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+
+    //
+    // Manufacture
+    //
+    ManufactureStr = AllocateZeroPool (StringBufferSize);
+    if(NULL == ManufactureStr)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto FREE_STR_BUF;
+    }
+    UnicodeSPrint(ManufactureStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM");
+
+    //
+    // SerialNumber
+    //
+    SerialNumberStr = AllocateZeroPool (StringBufferSize);
+    if(NULL == SerialNumberStr)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto FREE_STR_MAN;
+    }
+    UnicodeSPrint(SerialNumberStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM");
+
+    //
+    // AssetTag
+    //
+    AssertTagStr = AllocateZeroPool (StringBufferSize);
+    if(NULL == AssertTagStr)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto FREE_STR_SN;
+    }
+    UnicodeSPrint(AssertTagStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM");
+
+    //
+    // PartNumber
+    //
+    PartNumberStr = AllocateZeroPool (StringBufferSize);
+    if(NULL == PartNumberStr)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto FREE_STR_AST;
+    }
+    UnicodeSPrint(PartNumberStr, SMBIOS_STRING_MAX_LENGTH - 1, L"NO DIMM");
+
+
+    if(IsDimmPresent(pGblData, Skt, Ch, Dimm))
+    {
+        MemoryDataWidth = pGblData->Channel[Skt][Ch].Dimm[Dimm].PrimaryBusWidth;
+        MemoryTotalWidth = MemoryDataWidth + pGblData->Channel[Skt][Ch].Dimm[Dimm].ExtensionBusWidth;
+
+        MemoryDeviceSize = pGblData->Channel[Skt][Ch].Dimm[Dimm].DimmSize;  //in MB
+        MemoryDeviceExtendSize = 0;
+
+        if (MemoryDeviceSize >= 0x7fff)
+        {
+            MemoryDeviceExtendSize = MemoryDeviceSize;  // in MB
+            MemoryDeviceSize = 0x7fff;                    // max value
+        }
+
+        MemInfoMemFreq = pGblData->Freq;
+        MemorySpeed = pGblData->Channel[Skt][Ch].Dimm[Dimm].DimmSpeed;
+        Attributes = pGblData->Channel[Skt][Ch].Dimm[Dimm].RankNum;
+        CfgMemorySpeed = MemInfoMemFreq;
+
+        //
+        // Manufacturer
+        //
+        SmbiosGetManufacturer (pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdMMfgId & 0xFF,
+                                        pGblData->Channel[Skt][Ch].Dimm[Dimm].SpdMMfgId >> 8,
+                                        ManufactureStr
+                                        );
+
+        //
+        // SerialNumber
+        //
+        SmbiosGetSerialNumber(pGblData, Skt, Ch, Dimm, SerialNumberStr);
+
+        //
+        // AssetTag
+        //
+        UnicodeSPrint(AssertTagStr, SMBIOS_STRING_MAX_LENGTH - 1, L"Unknown");
+
+        //
+        // PartNumber
+        //
+        SmbiosGetPartNumber(pGblData, Skt, Ch, Dimm, PartNumberStr);
+    }
+
+    //
+    // DeviceLocator
+    //
+    DeviceLocatorStr = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+    if(NULL == DeviceLocatorStr)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto FREE_STR_PN;
+    }
+    DeviceLocator = gDimmToDevLocator[Skt][Ch][Dimm];
+    if (DeviceLocator != 0xFFFF)
+    {
+        UnicodeSPrint(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"DIMM%x%x%x ", Skt, Ch, Dimm);
+        StringBuffer = HiiGetPackageString (&gEfiCallerIdGuid, DeviceLocator, NULL);
+        (VOID)StrCatS(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, StringBuffer);
+    }
+    else
+    {
+    UnicodeSPrint(DeviceLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"DIMM%x%x%x", Skt, Ch, Dimm);
+    }
+    DeviceLocatorStrLen = StrLen (DeviceLocatorStr);
+
+    //
+    // BankLocator
+    //
+    BankLocatorStr = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+    if(NULL == BankLocatorStr)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto FREE_STR_DEV;
+    }
+    UnicodeSPrint(BankLocatorStr, SMBIOS_STRING_MAX_LENGTH, L"SOCKET %x CHANNEL %x DIMM %x", Skt, Ch, Dimm);
+    BankLocatorStrLen = StrLen (BankLocatorStr);
+
+    ManufactureStrLen = StrLen (ManufactureStr);
+    SerialNumberStrLen = StrLen (SerialNumberStr);
+    AssertTagStrLen = StrLen (AssertTagStr);
+    PartNumberStrLen = StrLen (PartNumberStr);
+
+    //
+    // Report Type 17 SMBIOS Record
+    //
+    TableSize = sizeof(SMBIOS_TABLE_TYPE17) + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1 + AssertTagStrLen + 1 + PartNumberStrLen + 1 + 1;
+    Type17Record = AllocateZeroPool (TableSize);
+    if(NULL == Type17Record)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto FREE_BL;
+    }
+
+    Type17Record->Hdr.Type                      = EFI_SMBIOS_TYPE_MEMORY_DEVICE;
+    Type17Record->Hdr.Length                    = sizeof (SMBIOS_TABLE_TYPE17);
+    Type17Record->Hdr.Handle                    = 0;
+    Type17Record->MemoryArrayHandle             = MemArraySmbiosHandle;
+    Type17Record->MemoryErrorInformationHandle  = 0xFFFE;
+    Type17Record->TotalWidth                    = MemoryTotalWidth;
+    Type17Record->DataWidth                     = MemoryDataWidth;
+    Type17Record->Size                          = MemoryDeviceSize;           // in MB
+    Type17Record->FormFactor                    = MemoryFormFactorDimm;
+    Type17Record->DeviceLocator                 = 1;
+    Type17Record->BankLocator                   = 2;
+    Type17Record->MemoryType                    = SmbiosGetMemoryType (pGblData, Skt, Ch, Dimm);
+
+    Type17Record->TypeDetail.Synchronous    = 1;
+
+    SmbiosGetTypeDetail (pGblData, Skt, Ch, Dimm, &(Type17Record->TypeDetail));
+
+    Type17Record->Speed                         = MemorySpeed; // in MHZ
+    Type17Record->Manufacturer                  = 3;
+    Type17Record->SerialNumber                  = 4;
+    Type17Record->AssetTag                      = 5;
+    Type17Record->PartNumber                    = 6;
+    Type17Record->Attributes                    = Attributes;
+    Type17Record->ExtendedSize                  = MemoryDeviceExtendSize;
+    Type17Record->ConfiguredMemoryClockSpeed    = CfgMemorySpeed;
+    //
+    // Add for smbios 2.8.0
+    //
+    SmbiosGetDimmVoltageInfo (pGblData, Skt, Ch, Dimm, Type17Record);
+
+    OptionalStrStart = (CHAR8 *) (Type17Record + 1);
+    UnicodeStrToAsciiStr (DeviceLocatorStr, OptionalStrStart);
+    UnicodeStrToAsciiStr (BankLocatorStr, OptionalStrStart + DeviceLocatorStrLen + 1);
+    UnicodeStrToAsciiStr (ManufactureStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1);
+    UnicodeStrToAsciiStr (SerialNumberStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1);
+    UnicodeStrToAsciiStr (AssertTagStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1);
+    UnicodeStrToAsciiStr (PartNumberStr, OptionalStrStart + DeviceLocatorStrLen + 1 + BankLocatorStrLen + 1 + ManufactureStrLen + 1 + SerialNumberStrLen + 1 + AssertTagStrLen + 1);
+
+    MemDevSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+    Status = mSmbios->Add (mSmbios, NULL, &MemDevSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type17Record);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type17 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool (Type17Record);
+
+FREE_BL:
+    FreePool (BankLocatorStr);
+
+FREE_STR_DEV:
+    FreePool (DeviceLocatorStr);
+
+FREE_STR_PN:
+    FreePool (PartNumberStr);
+
+FREE_STR_AST:
+    FreePool (AssertTagStr);
+
+FREE_STR_SN:
+    FreePool (SerialNumberStr);
+
+FREE_STR_MAN:
+    FreePool (ManufactureStr);
+
+FREE_STR_BUF:
+    FreePool (StringBuffer);
+
+    return Status;
+}
+
+
+/**
+  Standard EFI driver point.  This driver locates the MemoryConfigurationData Variable,
+  if it exists, add the related SMBIOS tables by PI SMBIOS protocol.
+
+  @param  ImageHandle     Handle for the image of this driver
+  @param  SystemTable     Pointer to the EFI System Table
+
+  @retval  EFI_SUCCESS    The data was successfully stored.
+
+**/
+EFI_STATUS
+EFIAPI
+MemorySubClassEntryPoint(
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+    EFI_STATUS                      Status;
+    EFI_SMBIOS_PROTOCOL             *Smbios;
+    EFI_HOB_GUID_TYPE               *GuidHob;
+    pGBL_DATA                       pGblData;
+    EFI_SMBIOS_HANDLE               MemArraySmbiosHandle;
+    UINT8                           Skt, Ch, Dimm;
+
+    GuidHob = GetFirstGuidHob(&gHisiEfiMemoryMapGuid);
+    if(NULL == GuidHob)
+    {
+        DEBUG((EFI_D_ERROR, "Could not get MemoryMap Guid hob.  %r\n"));
+        return EFI_NOT_FOUND;
+    }
+    pGblData = (pGBL_DATA) GET_GUID_HOB_DATA(GuidHob);
+
+    //
+    // Locate dependent protocols
+    //
+    Status = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol.  %r\n", Status));
+        return Status;
+    }
+    mSmbios = Smbios;
+
+    //
+    // Add our default strings to the HII database. They will be modified later.
+    //
+    mHiiHandle = OemGetPackages();
+    if(NULL == mHiiHandle)
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+    mMaxSkt  = OemGetSocketNumber();
+    mMaxCh   = OemGetDdrChannel();
+    // Get DIMM slot number on Socket 0 Channel 0
+    // TODO: Assume all channels have same slot number
+
+    Status = SmbiosAddType16Table (pGblData, &MemArraySmbiosHandle);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "Smbios Add Type16 Table Failed.  %r\n", Status));
+        return Status;
+    }
+
+    Status = SmbiosAddType19Table (pGblData, MemArraySmbiosHandle);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "Smbios Add Type19 Table Failed.  %r\n", Status));
+        return Status;
+    }
+
+    for(Skt = 0; Skt < mMaxSkt; Skt++)
+    {
+        for(Ch = 0; Ch < mMaxCh; Ch++)
+        {
+            for(Dimm = 0; Dimm < OemGetDimmSlot(Skt, Ch); Dimm++)
+            {
+                Status = SmbiosAddType17Table (pGblData, Skt, Ch, Dimm, MemArraySmbiosHandle);
+                if(EFI_ERROR(Status))
+                {
+                    DEBUG((EFI_D_ERROR, "Smbios Add Type17 Table Failed.  %r\n", Status));
+                }
+            }
+        }
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
new file mode 100644
index 0000000..c35ce39
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
@@ -0,0 +1,79 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _MEMORY_SUBCLASS_DRIVER_H
+#define _MEMORY_SUBCLASS_DRIVER_H
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/HiiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/HobLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PcdLib.h>
+
+#include <Library/HwMemInitLib.h>
+#include <Guid/DebugMask.h>
+#include <Guid/MemoryMapData.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemMiscLib.h>
+
+//
+// This is the generated header file which includes whatever needs to be exported (strings + IFR)
+//
+
+extern UINT8 MemorySubClassStrings[];
+
+#define MAX_DIMM_SIZE       32  // In GB
+
+struct SPD_JEDEC_MANUFACTURER
+{
+    UINT8  MfgIdLSB;
+    UINT8  MfgIdMSB;
+    CHAR16 *Name;
+};
+
+struct SPD_JEDEC_MANUFACTURER JEP106[] = {
+    {    0, 0x10, L"NEC"},
+    {    0, 0x2c, L"Micron"},
+    {    0, 0x3d, L"Tektronix"},
+    {    0, 0x97, L"TI"},
+    {    0, 0xad, L"Hynix"},
+    {    0, 0xb3, L"IDT"},
+    {    0, 0xc1, L"Infineon"},
+    {    0, 0xce, L"Samsung"},
+    {    1, 0x94, L"Smart"},
+    {    1, 0x98, L"Kingston"},
+    {    2, 0xc8, L"Agilent"},
+    {    2, 0xfe, L"Elpida"},
+    {    3, 0x0b, L"Nanya"},
+    {    4, 0x43, L"Ramaxel"},
+    {    4, 0xb3, L"Inphi"},
+    {    5, 0x51, L"Qimonda"},
+    {    5, 0x57, L"AENEON"},
+    { 0xFF, 0xFF, L""}
+};
+
+
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
new file mode 100644
index 0000000..a2ea3a0
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
@@ -0,0 +1,59 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MemorySubClass
+  FILE_GUID                      = 62194F1A-5A0D-4B33-9EF0-7D05C6CB923A
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = MemorySubClassEntryPoint
+
+[Sources]
+  MemorySubClassStrings.uni
+  MemorySubClass.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelFrameworkPkg/IntelFrameworkPkg.dec
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  HobLib
+  HiiLib
+  MemoryAllocationLib
+  BaseMemoryLib
+  BaseLib
+  DebugLib
+  PrintLib
+  PlatformSysCtrlLib
+  PcdLib
+
+[Protocols]
+  gEfiSmbiosProtocolGuid                       # PROTOCOL ALWAYS_CONSUMED
+
+[Pcd]
+
+[Guids]
+   gHisiEfiMemoryMapGuid
+
+[Depex]
+  gEfiSmbiosProtocolGuid
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni
new file mode 100644
index 0000000..edf8464
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassStrings.uni
@@ -0,0 +1,30 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+// Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// --*/
+
+/=#
+
+#langdef en-US "English"
+
+//
+// Begin English Language Strings
+//
+
+#string STR_MEMORY_SUBCLASS_UNKNOWN    #language en-US  "Unknown"
+
+//
+// End English Language Strings
+//
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
new file mode 100644
index 0000000..61473e8
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -0,0 +1,728 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "ProcessorSubClass.h"
+
+#include <FrameworkDxe.h>
+
+EFI_HII_HANDLE                  mHiiHandle;
+
+EFI_SMBIOS_PROTOCOL             *mSmbios;
+
+SMBIOS_TABLE_TYPE7   mSmbiosCacheTable[] = {
+    //L1 Instruction Cache
+    {
+        {                                               //Header
+            EFI_SMBIOS_TYPE_CACHE_INFORMATION,              //Type
+            sizeof(SMBIOS_TABLE_TYPE7),                     //Length
+            0                                               //Handle
+        },
+        1,                                              //SocketDesignation
+        0,                                              //CacheConfiguration
+        0,                                              //MaximumCacheSize
+        48,                                             //InstalledSize
+        {                                               //SupportedSRAMType
+            0
+        },
+        {                                               //CurrentSRAMType
+            0
+        },
+        0,                                              //CacheSpeed
+        CacheErrorParity,                               //ErrorCorrectionType
+        CacheTypeInstruction,                           //SystemCacheType
+        CacheAssociativity8Way                          //Associativity
+    },
+
+    //L1 Data Cache
+    {
+        {                                               //Header
+            EFI_SMBIOS_TYPE_CACHE_INFORMATION,              //Type
+            sizeof(SMBIOS_TABLE_TYPE7),                     //Length
+            0                                               //Handle
+        },
+        1,                                              //SocketDesignation
+        0,                                              //CacheConfiguration
+        0,                                              //MaximumCacheSize
+        32,                                              //InstalledSize
+        {                                               //SupportedSRAMType
+            0
+        },
+        {                                               //CurrentSRAMType
+            0
+        },
+        0,                                              //CacheSpeed
+        CacheErrorSingleBit,                            //ErrorCorrectionType
+        CacheTypeData,                                  //SystemCacheType
+        CacheAssociativity8Way                          //Associativity
+    },
+
+    //L2 Cache
+    {
+        {                                               //Header
+            EFI_SMBIOS_TYPE_CACHE_INFORMATION,              //Type
+            sizeof(SMBIOS_TABLE_TYPE7),                     //Length
+            0                                               //Handle
+        },
+        1,                                              //SocketDesignation
+        0,                                              //CacheConfiguration
+        0,                                              //MaximumCacheSize
+        4096,                                           //InstalledSize
+        {                                               //SupportedSRAMType
+            0
+        },
+        {                                               //CurrentSRAMType
+            0
+        },
+        0,                                              //CacheSpeed
+        CacheErrorSingleBit,                            //ErrorCorrectionType
+        CacheTypeUnified,                               //SystemCacheType
+        CacheAssociativity8Way                          //Associativity
+    },
+
+    //L3 Cache
+    {
+        {                                               //Header
+            EFI_SMBIOS_TYPE_CACHE_INFORMATION,              //Type
+            sizeof(SMBIOS_TABLE_TYPE7),                     //Length
+            0                                               //Handle
+        },
+        1,                                              //SocketDesignation
+        0,                                              //CacheConfiguration
+        0,                                              //MaximumCacheSize
+        16384,                                          //InstalledSize
+        {                                               //SupportedSRAMType
+            0
+        },
+        {                                               //CurrentSRAMType
+            0
+        },
+        0,                                              //CacheSpeed
+        CacheErrorSingleBit,                            //ErrorCorrectionType
+        CacheTypeUnified,                               //SystemCacheType
+        CacheAssociativity16Way                         //Associativity
+    }
+};
+
+SMBIOS_TABLE_TYPE4   mSmbiosProcessorTable[] = {
+    //CPU0
+    {
+        {                                               //Header
+            EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION,          //Type
+            sizeof(SMBIOS_TABLE_TYPE4),                     //Length
+            0                                               //Handle
+        },
+        1,                                              //Socket
+        CentralProcessor,                               //ProcessorType
+        ProcessorFamilyOther,                           //ProcessorFamily
+        2,                                              //ProcessorManufacture
+        {                                               //ProcessorId
+            {                                               //Signature
+                0
+            },
+            {                                               //FeatureFlags
+                0
+            }
+        },
+        3,                                              //ProcessorVersion
+        {                                               //Voltage
+            0
+        },
+        EXTERNAL_CLOCK,                                 //ExternalClock
+        CPU_MAX_SPEED,                                  //MaxSpeed
+        0,                                              //CurrentSpeed
+        0,                                              //Status
+        ProcessorUpgradeUnknown,                        //ProcessorUpgrade
+        0xFFFF,                                         //L1CacheHandle
+        0xFFFF,                                         //L2CacheHandle
+        0xFFFF,                                         //L3CacheHandle
+        4,                                              //SerialNumber
+        5,                                              //AssetTag
+        6,                                              //PartNumber
+
+        0,                                              //CoreCount
+        0,                                              //EnabledCoreCount
+        0,                                              //ThreadCount
+        0,                                              //ProcessorCharacteristics
+
+        ProcessorFamilyARM,                             //ProcessorFamily2
+
+        0,                                              //CoreCount2
+        0,                                              //EnabledCoreCount2
+        0                                               //ThreadCount2
+    },
+
+    //CPU1
+    {
+        {                                               //Header
+            EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION,          //Type
+            sizeof(SMBIOS_TABLE_TYPE4),                     //Length
+            0                                               //Handle
+        },
+        1,                                              //Socket
+        CentralProcessor,                               //ProcessorType
+        ProcessorFamilyOther,                           //ProcessorFamily
+        2,                                              //ProcessorManufacture
+        {                                               //ProcessorId
+            {                                               //Signature
+                0
+            },
+            {                                               //FeatureFlags
+                0
+            }
+        },
+        3,                                              //ProcessorVersion
+        {                                               //Voltage
+            0
+        },
+        EXTERNAL_CLOCK,                                 //ExternalClock
+        CPU_MAX_SPEED,                                  //MaxSpeed
+        0,                                              //CurrentSpeed
+        0,                                              //Status
+        ProcessorUpgradeUnknown,                        //ProcessorUpgrade
+        0xFFFF,                                         //L1CacheHandle
+        0xFFFF,                                         //L2CacheHandle
+        0xFFFF,                                         //L3CacheHandle
+        4,                                              //SerialNumber
+        5,                                              //AssetTag
+        6,                                              //PartNumber
+
+        0,                                              //CoreCount
+        0,                                              //EnabledCoreCount
+        0,                                              //ThreadCount
+        0,                                              //ProcessorCharacteristics
+
+        ProcessorFamilyARM,                             //ProcessorFamily2
+
+        0,                                              //CoreCount2
+        0,                                              //EnabledCoreCount2
+        0                                               //ThreadCount2
+    }
+};
+
+
+UINT16
+GetCpuFrequency (
+  IN  UINT8 ProcessorNumber
+)
+{
+    return (UINT16)(PlatformGetCpuFreq(ProcessorNumber)/1000/1000);
+}
+
+UINTN
+GetCacheSocketStr (
+  IN  UINT8     CacheLevel,
+  OUT CHAR16    *CacheSocketStr
+  )
+{
+    UINTN CacheSocketStrLen;
+
+    if(CacheLevel == CPU_CACHE_L1_Instruction)
+    {
+        CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Instruction Cache", CacheLevel + 1);
+    }
+    else if(CacheLevel == CPU_CACHE_L1_Data)
+    {
+        CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Data Cache", CacheLevel);
+    }
+    else
+    {
+        CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, SMBIOS_STRING_MAX_LENGTH - 1, L"L%x Cache", CacheLevel);
+    }
+
+    return CacheSocketStrLen;
+}
+
+VOID
+UpdateSmbiosCacheTable (
+  IN UINT8  CacheLevel
+  )
+{
+    UINT16                      CoreCount;
+    UINT32                      TotalSize;
+    UINT32                      CacheSize;
+    UINT16                      MaximumCacheSize;
+    UINT16                      InstalledSize;
+    CACHE_CONFIGURATION         CacheConfig;
+    CACHE_SRAM_TYPE_DATA        CacheSramType = {0};
+
+    CoreCount = 16;     // Default value is 16 Core
+
+    //
+    // Set Cache Configuration
+    //
+    CacheConfig.Bits.Socketed                = 0;    // Not Socketed
+    CacheConfig.Bits.Reserved1               = 0;    //
+    CacheConfig.Bits.Location                = 0;    // Internal
+    CacheConfig.Bits.Enable                  = 1;    // Enabled
+    CacheConfig.Bits.Reserved2               = 0;
+    if(CacheLevel == CPU_CACHE_L1_Instruction || CacheLevel == CPU_CACHE_L1_Data)
+    {
+        CacheConfig.Bits.Level               = 0;
+        CacheConfig.Bits.OperationalMode     = 1;        // Write Back
+    }
+    else
+    {
+        CacheConfig.Bits.Level               = CacheLevel - 1;
+        CacheConfig.Bits.OperationalMode     = 2;        // Varies with Memory Address
+    }
+
+    mSmbiosCacheTable[CacheLevel].CacheConfiguration = CacheConfig.Data;
+
+    //
+    // Set Cache Size
+    //
+    CacheSize = mSmbiosCacheTable[CacheLevel].InstalledSize;
+    if (PACKAGE_16CORE != PlatformGetPackageType())  // 32 Core
+    {
+        CoreCount = CoreCount * 2;
+
+        if (CacheLevel > 1)
+        {
+            CacheSize = CacheSize * 2;
+        }
+    }
+
+    if(CacheLevel <= 1)
+    {
+        TotalSize = CacheSize * CoreCount;
+    }
+    else
+    {
+        TotalSize = CacheSize;
+    }
+
+    if((TotalSize >> 15) == 0)  // 1K granularity
+    {
+        MaximumCacheSize   = (UINT16)TotalSize;
+        InstalledSize      = (UINT16)TotalSize;
+    }
+    else    // 64K granularity
+    {
+        MaximumCacheSize   = (UINT16)(TotalSize >> 6);
+        InstalledSize      = (UINT16)(TotalSize >> 6);
+
+        // Set BIT15 to 1
+        MaximumCacheSize   |= BIT15;
+        InstalledSize      |= BIT15;
+    }
+
+    mSmbiosCacheTable[CacheLevel].MaximumCacheSize = MaximumCacheSize;
+    mSmbiosCacheTable[CacheLevel].InstalledSize = InstalledSize;
+
+    //
+    // Set SRAM Type
+    //
+    CacheSramType.Synchronous = 1;
+    (VOID)CopyMem(&mSmbiosCacheTable[CacheLevel].SupportedSRAMType, &CacheSramType, sizeof(CACHE_SRAM_TYPE_DATA));
+    (VOID)CopyMem(&mSmbiosCacheTable[CacheLevel].CurrentSRAMType, &CacheSramType, sizeof(CACHE_SRAM_TYPE_DATA));
+}
+
+/**
+  Add Type 7 SMBIOS Record for Cache Information.
+
+  @param[in]    ProcessorNumber     Processor number of specified processor.
+  @param[out]   L1CacheHandle       Pointer to the handle of the L1 Cache SMBIOS record.
+  @param[out]   L2CacheHandle       Pointer to the handle of the L2 Cache SMBIOS record.
+  @param[out]   L3CacheHandle       Pointer to the handle of the L3 Cache SMBIOS record.
+
+**/
+EFI_STATUS
+AddSmbiosCacheTypeTable (
+  IN UINTN                  ProcessorNumber,
+  OUT EFI_SMBIOS_HANDLE     *L1CacheHandle,
+  OUT EFI_SMBIOS_HANDLE     *L2CacheHandle,
+  OUT EFI_SMBIOS_HANDLE     *L3CacheHandle
+  )
+{
+    EFI_STATUS                  Status;
+    SMBIOS_TABLE_TYPE7          *Type7Record;
+    EFI_SMBIOS_HANDLE           SmbiosHandle;
+    UINTN                       TableSize;
+    UINT8                       CacheLevel;
+    CHAR8                       *OptionalStrStart;
+    EFI_STRING                  CacheSocketStr;
+    UINTN                       CacheSocketStrLen;
+    UINTN                       StringBufferSize;
+
+    Status = EFI_SUCCESS;
+
+    //
+    // Get Cache information
+    //
+    for(CacheLevel = 0; CacheLevel < MAX_CACHE_LEVEL; CacheLevel++)
+    {
+        Type7Record = NULL;
+
+        if(mSmbiosCacheTable[CacheLevel].InstalledSize == 0)
+        {
+            continue;
+        }
+
+        //
+        // Update Cache information
+        //
+        if (mSmbiosCacheTable[CacheLevel].MaximumCacheSize == 0)
+        {
+            UpdateSmbiosCacheTable (CacheLevel);
+        }
+
+        StringBufferSize = sizeof(CHAR16) * SMBIOS_STRING_MAX_LENGTH;
+        CacheSocketStr = AllocateZeroPool(StringBufferSize);
+        if (CacheSocketStr == NULL)
+        {
+            Status = EFI_OUT_OF_RESOURCES;
+            goto Exit;
+        }
+
+        CacheSocketStrLen = GetCacheSocketStr (CacheLevel, CacheSocketStr);
+
+        TableSize = sizeof(SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1;
+        Type7Record = AllocateZeroPool (TableSize);
+        if (Type7Record == NULL)
+        {
+            Status = EFI_OUT_OF_RESOURCES;
+            goto Exit;
+        }
+
+        (VOID)CopyMem(Type7Record, &mSmbiosCacheTable[CacheLevel], sizeof (SMBIOS_TABLE_TYPE7));
+
+        OptionalStrStart = (CHAR8 *) (Type7Record + 1);
+        UnicodeStrToAsciiStr (CacheSocketStr, OptionalStrStart);
+
+        SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+        Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type7Record);
+        if (EFI_ERROR (Status))
+        {
+            goto Exit;
+        }
+
+        // Config L1/L2/L3 Cache Handle
+        switch(CacheLevel)
+        {
+            case CPU_CACHE_L1_Instruction:
+            case CPU_CACHE_L1_Data:
+                *L1CacheHandle = SmbiosHandle;
+                break;
+            case CPU_CACHE_L2:
+                *L2CacheHandle = SmbiosHandle;
+                break;
+            case CPU_CACHE_L3:
+                *L3CacheHandle = SmbiosHandle;
+                break;
+            default :
+                break;
+        }
+Exit:
+        if(Type7Record != NULL)
+        {
+            FreePool (Type7Record);
+        }
+        if(CacheSocketStr != NULL)
+        {
+            FreePool (CacheSocketStr);
+            CacheSocketStr = NULL;
+        }
+    }
+
+    return Status;
+}
+
+/**
+  Add Type 4 SMBIOS Record for Processor Information.
+
+  @param[in]    ProcessorNumber     Processor number of specified processor.
+
+**/
+EFI_STATUS
+AddSmbiosProcessorTypeTable (
+  IN UINTN                  ProcessorNumber
+  )
+{
+    EFI_STATUS                  Status;
+    SMBIOS_TABLE_TYPE4          *Type4Record;
+    EFI_SMBIOS_HANDLE           SmbiosHandle;
+    EFI_SMBIOS_HANDLE           L1CacheHandle;
+    EFI_SMBIOS_HANDLE           L2CacheHandle;
+    EFI_SMBIOS_HANDLE           L3CacheHandle;
+
+    CHAR8                       *OptionalStrStart;
+    EFI_STRING_ID               ProcessorManu;
+    EFI_STRING_ID               ProcessorVersion;
+    EFI_STRING_ID               SerialNumber;
+    EFI_STRING_ID               AssetTag;
+    EFI_STRING_ID               PartNumber;
+    EFI_STRING                  ProcessorSocketStr;
+    EFI_STRING                  ProcessorManuStr;
+    EFI_STRING                  ProcessorVersionStr;
+    EFI_STRING                  SerialNumberStr;
+    EFI_STRING                  AssetTagStr;
+    EFI_STRING                  PartNumberStr;
+    UINTN                       ProcessorSocketStrLen;
+    UINTN                       ProcessorManuStrLen;
+    UINTN                       ProcessorVersionStrLen;
+    UINTN                       SerialNumberStrLen;
+    UINTN                       AssetTagStrLen;
+    UINTN                       PartNumberStrLen;
+    UINTN                       StringBufferSize;
+    UINTN                       TotalSize;
+
+    UINT8                       Voltage;
+    UINT16                      CoreCount;
+    UINT16                      CoreEnabled;
+    UINT16                      ThreadCount;
+    UINT16                      CurrentSpeed;
+    PROCESSOR_STATUS_DATA       ProcessorStatus = {{0}};
+    PROCESSOR_CHARACTERISTICS_DATA  ProcessorCharacteristics = {{0}};
+
+    CHAR16                      *CpuVersion;
+    STRING_REF                  TokenToUpdate;
+
+    UINT64                      *ProcessorId;
+    Type4Record         = NULL;
+    ProcessorManuStr    = NULL;
+    ProcessorVersionStr = NULL;
+    SerialNumberStr     = NULL;
+    AssetTagStr         = NULL;
+    PartNumberStr       = NULL;
+
+    if(OemIsSocketPresent(ProcessorNumber))  //CPU is present
+    {
+        Voltage         = BIT7 | 9;          // 0.9V
+
+        Status = AddSmbiosCacheTypeTable (ProcessorNumber, &L1CacheHandle, &L2CacheHandle, &L3CacheHandle);
+        if(EFI_ERROR(Status))
+        {
+            return Status;
+        }
+
+        CurrentSpeed        = GetCpuFrequency(ProcessorNumber);
+
+        CoreCount       = PlatformGetCoreCount();
+        CoreEnabled     = CoreCount;
+        ThreadCount     = CoreCount;
+
+        CpuVersion = (CHAR16 *) PcdGetPtr (PcdCPUInfo);
+        if (StrLen(CpuVersion) > 0)
+        {
+            TokenToUpdate = STRING_TOKEN (STR_PROCESSOR_VERSION);
+            HiiSetString (mHiiHandle, TokenToUpdate, CpuVersion, NULL);
+        }
+
+        ProcessorManu       = STRING_TOKEN (STR_PROCESSOR_MANUFACTURE);
+        ProcessorVersion    = STRING_TOKEN (STR_PROCESSOR_VERSION);
+        SerialNumber        = STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER);
+        AssetTag            = STRING_TOKEN (STR_PROCESSOR_ASSET_TAG);
+        PartNumber          = STRING_TOKEN (STR_PROCESSOR_PART_NUMBER);
+
+        // Processor Status
+        ProcessorStatus.Bits.CpuStatus           = 1;        // CPU Enabled
+        ProcessorStatus.Bits.Reserved1           = 0;
+        ProcessorStatus.Bits.SocketPopulated     = 1;        // CPU Socket Populated
+        ProcessorStatus.Bits.Reserved2           = 0;
+
+        // Processor Characteristics
+        ProcessorCharacteristics.Bits.Reserved       = 0;
+        ProcessorCharacteristics.Bits.Capable64Bit   = 1;        // 64-bit Capable
+        ProcessorCharacteristics.Bits.Unknown        = 0;
+        ProcessorCharacteristics.Bits.EnhancedVirtualization     = 1;
+        ProcessorCharacteristics.Bits.HardwareThread = 0;
+        ProcessorCharacteristics.Bits.MultiCore      = 1;
+        ProcessorCharacteristics.Bits.ExecuteProtection          = 1;
+        ProcessorCharacteristics.Bits.PowerPerformanceControl    = 1;
+        ProcessorCharacteristics.Bits.Reserved2      = 0;
+    }
+    else
+    {
+        Voltage             = 0;
+        CurrentSpeed        = 0;
+        CoreCount           = 0;
+        CoreEnabled         = 0;
+        ThreadCount         = 0;
+        L1CacheHandle       = 0xFFFF;
+        L2CacheHandle       = 0xFFFF;
+        L3CacheHandle       = 0xFFFF;
+
+        ProcessorManu       = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+        ProcessorVersion    = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+        SerialNumber        = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+        AssetTag            = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+        PartNumber          = STRING_TOKEN (STR_PROCESSOR_UNKNOWN);
+    }
+
+    // Processor Socket Designation
+    StringBufferSize = sizeof(CHAR16) * SMBIOS_STRING_MAX_LENGTH;
+    ProcessorSocketStr = AllocateZeroPool(StringBufferSize);
+    if (ProcessorSocketStr == NULL)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto Exit;
+    }
+
+    ProcessorSocketStrLen = UnicodeSPrint (ProcessorSocketStr, StringBufferSize, L"CPU%02d", ProcessorNumber + 1);
+
+    // Processor Manufacture
+    ProcessorManuStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorManu, NULL);
+    ProcessorManuStrLen = StrLen (ProcessorManuStr);
+
+    // Processor Version
+    ProcessorVersionStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorVersion, NULL);
+    ProcessorVersionStrLen = StrLen (ProcessorVersionStr);
+
+    // Serial Number
+    SerialNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber, NULL);
+    SerialNumberStrLen = StrLen (SerialNumberStr);
+
+    // Asset Tag
+    AssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL);
+    AssetTagStrLen = StrLen (AssetTagStr);
+
+    // Part Number
+    PartNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NULL);
+    PartNumberStrLen = StrLen (PartNumberStr);
+
+    TotalSize = sizeof (SMBIOS_TABLE_TYPE4) + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1 + AssetTagStrLen + 1 + PartNumberStrLen + 1 + 1;
+    Type4Record = AllocateZeroPool (TotalSize);
+    if (Type4Record == NULL)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto Exit;
+    }
+
+    (VOID)CopyMem(Type4Record, &mSmbiosProcessorTable[ProcessorNumber], sizeof (SMBIOS_TABLE_TYPE4));
+
+    *(UINT8 *) &Type4Record->Voltage        = Voltage;
+    Type4Record->CurrentSpeed               = CurrentSpeed;
+    Type4Record->Status                     = ProcessorStatus.Data;
+    Type4Record->L1CacheHandle              = L1CacheHandle;
+    Type4Record->L2CacheHandle              = L2CacheHandle;
+    Type4Record->L3CacheHandle              = L3CacheHandle;
+    Type4Record->CoreCount                  = CoreCount;
+    Type4Record->EnabledCoreCount           = CoreEnabled;
+    Type4Record->ThreadCount                = ThreadCount;
+    Type4Record->ProcessorCharacteristics   = ProcessorCharacteristics.Data;
+
+    Type4Record->ExternalClock              = (UINT16)(ArmReadCntFrq() / 1000 / 1000);
+    ProcessorId = (UINT64 *)&(Type4Record->ProcessorId);
+    *ProcessorId = ArmReadMidr();
+
+    OptionalStrStart = (CHAR8 *) (Type4Record + 1);
+    UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart);
+    UnicodeStrToAsciiStr (ProcessorManuStr, OptionalStrStart + ProcessorSocketStrLen + 1);
+    UnicodeStrToAsciiStr (ProcessorVersionStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1);
+    UnicodeStrToAsciiStr (SerialNumberStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1);
+    UnicodeStrToAsciiStr (AssetTagStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1);
+    UnicodeStrToAsciiStr (PartNumberStr, OptionalStrStart + ProcessorSocketStrLen + 1 + ProcessorManuStrLen + 1 + ProcessorVersionStrLen + 1 + SerialNumberStrLen + 1 + AssetTagStrLen + 1);
+
+    SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+    Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TABLE_HEADER *)Type4Record);
+    if (EFI_ERROR (Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+    FreePool (Type4Record);
+
+Exit:
+    if(ProcessorSocketStr != NULL)
+    {
+        FreePool (ProcessorSocketStr);
+    }
+    if(ProcessorManuStr != NULL)
+    {
+        FreePool (ProcessorManuStr);
+    }
+    if(ProcessorVersionStr != NULL)
+    {
+        FreePool (ProcessorVersionStr);
+    }
+    if(SerialNumberStr != NULL)
+    {
+        FreePool (SerialNumberStr);
+    }
+    if(AssetTagStr != NULL)
+    {
+        FreePool (AssetTagStr);
+    }
+    if(PartNumberStr != NULL)
+    {
+        FreePool (PartNumberStr);
+    }
+
+    return Status;
+}
+
+/**
+  Standard EFI driver point.  This driver locates the ProcessorConfigurationData Variable,
+  if it exists, add the related SMBIOS tables by PI SMBIOS protocol.
+
+  @param  ImageHandle     Handle for the image of this driver
+  @param  SystemTable     Pointer to the EFI System Table
+
+  @retval  EFI_SUCCESS    The data was successfully stored.
+
+**/
+EFI_STATUS
+EFIAPI
+ProcessorSubClassEntryPoint(
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+    EFI_STATUS                      Status;
+    UINT32                          SocketIndex;
+
+    //
+    // Locate dependent protocols
+    //
+    Status = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&mSmbios);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol.  %r\n", Status));
+        return Status;
+    }
+
+    //
+    // Add our default strings to the HII database. They will be modified later.
+    //
+    mHiiHandle = HiiAddPackages (
+                &gEfiCallerIdGuid,
+                NULL,
+                ProcessorSubClassStrings,
+                NULL,
+                NULL
+                );
+    if (mHiiHandle == NULL)
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+    //
+    // Add SMBIOS tables for populated sockets.
+    //
+    for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++)
+    {
+        if((SocketIndex == 1) && !OemIsMpBoot())
+        {
+            break;
+        }
+        Status = AddSmbiosProcessorTypeTable (SocketIndex);
+        if(EFI_ERROR(Status))
+        {
+            DEBUG((EFI_D_ERROR, "Add Processor Type Table Failed!  %r.\n", Status));
+            return Status;
+        }
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h
new file mode 100644
index 0000000..6ddc6cf
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h
@@ -0,0 +1,108 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PROCESSOR_SUBCLASS_DRIVER_H
+#define _PROCESSOR_SUBCLASS_DRIVER_H
+
+#include <Uefi.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/HiiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PcdLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/ArmLib.h>
+
+//
+// This is the generated header file which includes whatever needs to be exported (strings + IFR)
+//
+
+extern UINT8 ProcessorSubClassStrings[];
+
+#define CPU_CACHE_L1_Instruction        0
+#define CPU_CACHE_L1_Data               1
+#define CPU_CACHE_L2                    2
+#define CPU_CACHE_L3                    3
+#define MAX_CACHE_LEVEL                 4
+
+#define EXTERNAL_CLOCK                  50     //50 MHz
+#define CPU_MAX_SPEED                   2100   //2.1G
+
+//
+// Cache Info
+//
+typedef struct {
+  UINT16                    InstalledSize;    //In KB
+  CACHE_TYPE_DATA           SystemCacheType;
+  CACHE_ASSOCIATIVITY_DATA  Associativity;
+} CACHE_INFO;
+
+//
+// Cache Configuration
+//
+typedef union {
+  struct {
+    UINT16    Level           :3;
+    UINT16    Socketed        :1;
+    UINT16    Reserved1       :1;
+    UINT16    Location        :2;
+    UINT16    Enable          :1;
+    UINT16    OperationalMode :2;
+    UINT16    Reserved2       :6;
+  } Bits;
+  UINT16 Data;
+}CACHE_CONFIGURATION;
+
+//
+// Processor Status
+//
+typedef union {
+  struct {
+    UINT8 CpuStatus       :3; // Indicates the status of the processor.
+    UINT8 Reserved1       :3; // Reserved for future use. Should be set to zero.
+    UINT8 SocketPopulated :1; // Indicates if the processor socket is populated or not.
+    UINT8 Reserved2       :1; // Reserved for future use. Should be set to zero.
+  } Bits;
+  UINT8 Data;
+}PROCESSOR_STATUS_DATA;
+
+//
+// Processor Characteristics
+//
+typedef union {
+  struct {
+    UINT16 Reserved                 :1;
+    UINT16 Unknown                  :1;
+    UINT16 Capable64Bit             :1;
+    UINT16 MultiCore                :1;
+    UINT16 HardwareThread           :1;
+    UINT16 ExecuteProtection        :1;
+    UINT16 EnhancedVirtualization   :1;
+    UINT16 PowerPerformanceControl  :1;
+    UINT16 Reserved2                :8;
+  } Bits;
+  UINT16 Data;
+} PROCESSOR_CHARACTERISTICS_DATA;
+
+#endif
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
new file mode 100644
index 0000000..cc011d8
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
@@ -0,0 +1,64 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ProcessorSubClass
+  FILE_GUID                      = 9B25B1EA-0FD4-455D-A450-AD640C8A9C1B
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = ProcessorSubClassEntryPoint
+
+[Sources]
+  ProcessorSubClassStrings.uni
+  ProcessorSubClass.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelFrameworkPkg/IntelFrameworkPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  IoLib
+  HiiLib
+  MemoryAllocationLib
+  BaseMemoryLib
+  BaseLib
+  DebugLib
+  PrintLib
+  PcdLib
+
+  PlatformSysCtrlLib
+  OemMiscLib
+
+[Protocols]
+  gEfiSmbiosProtocolGuid                       # PROTOCOL ALWAYS_CONSUMED
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdCPUInfo
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+
+[Guids]
+
+
+[Depex]
+  gEfiSmbiosProtocolGuid
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni
new file mode 100644
index 0000000..d2928fa
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassStrings.uni
@@ -0,0 +1,32 @@
+///// @file
+//
+//  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+//  Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+/////
+
+/=#
+
+#langdef en-US "English"
+
+//
+// Processor Information
+//
+#string STR_PROCESSOR_SOCKET_DESIGNATION    #language en-US  "Hisilicon PhosphorV660 Processor"
+#string STR_PROCESSOR_MANUFACTURE           #language en-US  "Hisilicon"
+#string STR_PROCESSOR_VERSION               #language en-US  "Hi1610ES"
+#string STR_PROCESSOR_SERIAL_NUMBER         #language en-US  "To be filled by O.E.M."
+#string STR_PROCESSOR_ASSET_TAG             #language en-US  "To be filled by O.E.M."
+#string STR_PROCESSOR_PART_NUMBER           #language en-US  "To be filled by O.E.M."
+#string STR_PROCESSOR_UNKNOWN               #language en-US  "Unknown"
+
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h
new file mode 100644
index 0000000..66f9db9
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMisc.h
@@ -0,0 +1,226 @@
+/**@file
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  SmbiosMisc.h
+
+Abstract:
+
+  Header file for the SmbiosMisc Driver.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#ifndef _SMBIOS_MISC_DRIVER_H
+#define _SMBIOS_MISC_DRIVER_H
+
+#include <FrameworkDxe.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/HiiLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Guid/DebugMask.h>
+
+#include <Library/PrintLib.h>
+
+//
+// Data table entry update function.
+//
+typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) (
+  IN  VOID                 *RecordData,
+  IN  EFI_SMBIOS_PROTOCOL  *Smbios
+  );
+
+
+//
+// Data table entry definition.
+//
+typedef struct {
+  //
+  // intermediat input data for SMBIOS record
+  //
+  VOID                              *RecordData;
+  EFI_MISC_SMBIOS_DATA_FUNCTION     *Function;
+} EFI_MISC_SMBIOS_DATA_TABLE;
+
+
+//
+// Data Table extern definitions.
+//
+#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \
+extern NAME1 NAME2 ## Data; \
+extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function;
+
+
+//
+// Data Table entries
+//
+
+#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \
+{ \
+  & NAME1 ## Data, \
+    NAME2 ## Function \
+}
+
+
+//
+// Global definition macros.
+//
+#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \
+  NAME1 NAME2 ## Data
+
+#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \
+  EFI_STATUS EFIAPI NAME2 ## Function( \
+  IN  VOID                  *RecordData, \
+  IN  EFI_SMBIOS_PROTOCOL   *Smbios \
+  )
+
+//
+// Data Table Array Entries
+//
+extern EFI_HII_HANDLE               mHiiHandle;
+
+typedef struct _EFI_TYPE11_OEM_STRING{
+  UINT8                               Offset;
+  EFI_STRING_ID                       RefOemDefineString;
+} EFI_TYPE11_OEM_STRING;
+
+typedef struct _EFI_TYPE12_SYSTEM_CONFIGURATION_OPTIONS_STRING{
+  UINT8                               Offset;
+  EFI_STRING_ID                       RefType12SystemConfigurationOptionsString;
+} EFI_TYPE12_SYSTEM_CONFIGURATION_OPTIONS_STRING;
+
+typedef struct _EFI_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{
+  UINT8                               *LanguageSignature;
+  EFI_STRING_ID                       InstallableLanguageLongString;
+  EFI_STRING_ID                       InstallableLanguageAbbreviateString;
+} EFI_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING;
+
+typedef struct _EFI_TYPE40_ADDITIONAL_INFORMATION_ENTRY{
+  UINT8           RefType;
+  UINT8           RefOffset;
+  EFI_STRING_ID   RefString;
+  UINT8           Value;
+} EFI_TYPE40_ADDITIONAL_INFORMATION_ENTRY;
+
+typedef enum {
+  STRING,
+  DATA,
+} OEM_DEFINE_TYPE;
+
+typedef struct {
+  OEM_DEFINE_TYPE                Type;
+  UINTN                          Token;
+  UINTN                          DataSize;
+} OEM_DEFINE_INFO_STRING;
+
+typedef struct {
+  OEM_DEFINE_TYPE                Type;
+  UINTN                          DataAddress;
+  UINTN                          DataSize;
+} OEM_DEFINE_INFO_DATA;
+
+typedef union {
+  OEM_DEFINE_INFO_STRING         DefineString;
+  OEM_DEFINE_INFO_DATA           DefineData;
+} EFI_OEM_DEFINE_ARRAY;
+
+typedef struct _DMI_STRING_STRUCTURE {
+  UINT8                                 Type;
+  UINT8                                 Offset;
+  UINT8                                 Valid;
+  UINT16                                Length;
+  UINT8                                 String[1]; // Variable length field
+} DMI_STRING_STRUCTURE;
+
+typedef struct {
+  UINT8                                 Type;           // The SMBIOS structure type
+  UINT8                                 FixedOffset;    // The offset of the string reference
+                                                        // within the structure's fixed data.
+} DMI_UPDATABLE_STRING;
+
+EFI_STATUS
+FindString (
+  IN UINT8                              Type,
+  IN UINT8                              Offset,
+  IN EFI_STRING_ID                      TokenToUpdate
+);
+
+EFI_STATUS
+FindUuid (
+  EFI_GUID                    *Uuid
+);
+
+EFI_STATUS
+StringToBiosVeriosn (
+  IN  EFI_STRING_ID                     BiosVersionToken,
+  OUT UINT8                             *MajorVersion,
+  OUT UINT8                             *MinorVersion
+);
+
+
+/**
+ Logs SMBIOS record.
+
+ @param [in]   Buffer         Pointer to the data buffer.
+ @param [in]   SmbiosHandle   Pointer for retrieve handle.
+
+**/
+EFI_STATUS
+LogSmbiosData (
+  IN       UINT8                      *Buffer,
+  IN  OUT  EFI_SMBIOS_HANDLE          *SmbiosHandle
+  );
+
+/**
+ Get Link Type Handle.
+
+ @param [in]   SmbiosType     Get this Type from SMBIOS table
+ @param [out]  HandleArray    Pointer to Hadndler array with has been free by caller
+ @param [out]  HandleCount    Pointer to Hadndler Counter
+
+**/
+VOID
+GetLinkTypeHandle(
+  IN  UINT8                 SmbiosType,
+  OUT UINT16                **HandleArray,
+  OUT UINTN                 *HandleCount
+  );
+
+typedef enum {
+    ProductNameType01,
+    SerialNumType01,
+    UuidType01,
+    SystemManufacturerType01,
+    AssertTagType02,
+    SrNumType02,
+    BoardManufacturerType02,
+    AssetTagType03,
+    SrNumType03,
+    VersionType03,
+    ChassisTypeType03 ,
+    ManufacturerType03,
+} GET_INFO_BMC_OFFSET;
+
+VOID UpdateSmbiosInfo (IN EFI_HII_HANDLE mHiiHandle, IN EFI_STRING_ID TokenToUpdate, IN UINT8 Offset);
+EFI_STATUS GetUuidType1 (IN OUT EFI_GUID *Uuid);
+EFI_STATUS IpmiGetChassisType (IN OUT UINT8 *Type);
+#endif
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c
new file mode 100644
index 0000000..8e00865
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c
@@ -0,0 +1,58 @@
+/**@file
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  SmbiosMiscDataTable.c
+
+Abstract:
+
+  This file provide OEM to config SMBIOS Misc Type.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+  MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE0,  MiscBiosVendor, MiscBiosVendor)
+  MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE1,  MiscSystemManufacturer, MiscSystemManufacturer)
+  MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE3,  MiscChassisManufacturer, MiscChassisManufacturer)
+  MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE2,  MiscBaseBoardManufacturer, MiscBaseBoardManufacturer)
+  MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages, MiscNumberOfInstallableLanguages)
+  MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE32, MiscBootInformation, MiscBootInformation)
+  MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE38, MiscIpmiDeviceInformation, MiscIpmiDeviceInformation)
+
+
+EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[] = {
+  // Type0
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBiosVendor, MiscBiosVendor),
+  // Type1
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemManufacturer, MiscSystemManufacturer),
+  // Type3
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscChassisManufacturer, MiscChassisManufacturer),
+  // Type2
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBaseBoardManufacturer, MiscBaseBoardManufacturer),
+  // Type13
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscNumberOfInstallableLanguages, MiscNumberOfInstallableLanguages),
+  // Type32
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBootInformation, MiscBootInformation),
+  // Type38
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscIpmiDeviceInformation, MiscIpmiDeviceInformation),
+};
+
+
+//
+// Number of Data Table entries.
+//
+UINTN mSmbiosMiscDataTableEntries =
+  (sizeof mSmbiosMiscDataTable) / sizeof(EFI_MISC_SMBIOS_DATA_TABLE);
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
new file mode 100644
index 0000000..516d57d
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
@@ -0,0 +1,108 @@
+## @file
+# Component description file for SmbiosMisc instance.
+#
+# Parses the MiscSubclassDataTable and reports any generated data to the DataHub.
+#  All .uni file who tagged with "ToolCode="DUMMY"" in following file list is included by
+#  MiscSubclassDriver.uni file, the StrGather tool will expand MiscSubclassDriver.uni file
+#  and parse all .uni file.
+# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+# Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+##
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SmbiosMiscDxe
+  FILE_GUID                      = EF0C99B6-B1D3-4025-9405-BF6A560FE0E0
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = SmbiosMiscEntryPoint
+
+[Sources]
+  SmbiosMisc.h
+  SmbiosMiscDataTable.c
+  SmbiosMiscEntryPoint.c
+  SmbiosMiscLibString.uni
+  ./Type00/MiscBiosVendorData.c
+  ./Type00/MiscBiosVendorFunction.c
+  ./Type01/MiscSystemManufacturerData.c
+  ./Type01/MiscSystemManufacturerFunction.c
+  ./Type02/MiscBaseBoardManufacturerData.c
+  ./Type02/MiscBaseBoardManufacturerFunction.c
+  ./Type03/MiscChassisManufacturerData.c
+  ./Type03/MiscChassisManufacturerFunction.c
+  ./Type13/MiscNumberOfInstallableLanguagesData.c
+  ./Type13/MiscNumberOfInstallableLanguagesFunction.c
+  ./Type32/MiscBootInformationData.c
+  ./Type32/MiscBootInformationFunction.c
+  ./Type38/MiscIpmiDeviceInformationData.c
+  ./Type38/MiscIpmiDeviceInformationFunction.c
+
+  ./Type09/MiscSystemSlotDesignationData.c
+  ./Type09/MiscSystemSlotDesignationFunction.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelFrameworkPkg/IntelFrameworkPkg.dec
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  HiiLib
+  MemoryAllocationLib
+  DevicePathLib
+  BaseMemoryLib
+  BaseLib
+  DebugLib
+  UefiBootServicesTableLib
+  UefiRuntimeServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+  HobLib
+
+  IpmiCmdLib
+
+  SerdesLib
+
+[Protocols]
+  gEfiSmbiosProtocolGuid                       # PROTOCOL ALWAYS_CONSUMED
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdFdSize
+  gHisiTokenSpaceGuid.PcdFirmwareVendor
+  gHisiTokenSpaceGuid.PcdBiosVersionString
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString
+
+  gHisiTokenSpaceGuid.PcdSystemProductName
+  gHisiTokenSpaceGuid.PcdSystemVersion
+  gHisiTokenSpaceGuid.PcdBaseBoardProductName
+  gHisiTokenSpaceGuid.PcdBaseBoardVersion
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+
+  gHisiTokenSpaceGuid.PcdBiosVersionForBmc
+
+  gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang
+
+[Guids]
+  gEfiGenericVariableGuid
+  gVersionInfoHobGuid
+
+[Depex]
+  gEfiSmbiosProtocolGuid
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c
new file mode 100644
index 0000000..051410b
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c
@@ -0,0 +1,194 @@
+/**@file
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  SmbiosMiscEntryPoint.c
+
+Abstract:
+
+  This driver parses the mSmbiosMiscDataTable structure and reports
+  any generated data using SMBIOS protocol.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+#define MAX_HANDLE_COUNT  0x10
+
+EFI_HANDLE              mImageHandle;
+EFI_HII_HANDLE          mHiiHandle;
+EFI_SMBIOS_PROTOCOL     *mSmbios = NULL;
+
+//
+// Data Table Array
+//
+extern EFI_MISC_SMBIOS_DATA_TABLE   mSmbiosMiscDataTable[];
+//
+// Data Table Array Entries
+//
+extern UINTN                        mSmbiosMiscDataTableEntries;
+
+extern UINT8                        SmbiosMiscDxeStrings[];
+
+
+
+/**
+  Standard EFI driver point.  This driver parses the mSmbiosMiscDataTable
+  structure and reports any generated data using SMBIOS protocol.
+
+  @param  ImageHandle     Handle for the image of this driver
+  @param  SystemTable     Pointer to the EFI System Table
+
+  @retval  EFI_SUCCESS    The data was successfully stored.
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosMiscEntryPoint(
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+    UINTN                Index;
+    EFI_STATUS           EfiStatus;
+    EFI_SMBIOS_PROTOCOL  *Smbios;
+
+    mImageHandle = ImageHandle;
+
+    EfiStatus = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios);
+    if (EFI_ERROR(EfiStatus))
+    {
+        DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol.  %r\n", EfiStatus));
+        return EfiStatus;
+    }
+
+    mSmbios = Smbios;
+
+    mHiiHandle = HiiAddPackages (
+                   &gEfiCallerIdGuid,
+                   mImageHandle,
+                   SmbiosMiscDxeStrings,
+                   NULL
+                   );
+    if(mHiiHandle == NULL)
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+    for (Index = 0; Index < mSmbiosMiscDataTableEntries; ++Index)
+    {
+        //
+        // If the entry have a function pointer, just log the data.
+        //
+        if (mSmbiosMiscDataTable[Index].Function != NULL)
+        {
+            EfiStatus = (*mSmbiosMiscDataTable[Index].Function)(
+                mSmbiosMiscDataTable[Index].RecordData,
+                Smbios
+                );
+
+            if (EFI_ERROR(EfiStatus))
+            {
+                DEBUG((EFI_D_ERROR, "Misc smbios store error.  Index=%d, ReturnStatus=%r\n", Index, EfiStatus));
+                return EfiStatus;
+            }
+        }
+    }
+
+    return EfiStatus;
+}
+
+
+/**
+  Logs SMBIOS record.
+
+  @param  Buffer                The data for the fixed portion of the SMBIOS record. The format of the record is
+                                determined by EFI_SMBIOS_TABLE_HEADER.Type. The size of the formatted area is defined
+                                by EFI_SMBIOS_TABLE_HEADER.Length and either followed by a double-null (0x0000) or
+                                a set of null terminated strings and a null.
+  @param  SmbiosHandle          A unique handle will be assigned to the SMBIOS record.
+
+  @retval EFI_SUCCESS           Record was added.
+  @retval EFI_OUT_OF_RESOURCES  Record was not added due to lack of system resources.
+
+**/
+EFI_STATUS
+LogSmbiosData (
+  IN       UINT8                      *Buffer,
+  IN  OUT  EFI_SMBIOS_HANDLE          *SmbiosHandle
+  )
+{
+    EFI_STATUS         Status;
+
+    *SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+
+    Status = mSmbios->Add (
+                     mSmbios,
+                     NULL,
+                     SmbiosHandle,
+                     (EFI_SMBIOS_TABLE_HEADER *)Buffer
+                     );
+
+    return Status;
+}
+
+
+VOID
+GetLinkTypeHandle(
+  IN  UINT8                 SmbiosType,
+  OUT UINT16                **HandleArray,
+  OUT UINTN                 *HandleCount
+  )
+{
+    EFI_STATUS                       Status;
+    EFI_SMBIOS_HANDLE                SmbiosHandle;
+    EFI_SMBIOS_TABLE_HEADER          *LinkTypeData = NULL;
+
+    if(mSmbios == NULL)
+        return ;
+
+    SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+
+    *HandleArray = AllocateZeroPool(sizeof(UINT16) * MAX_HANDLE_COUNT);
+    if (*HandleArray == NULL)
+    {
+        DEBUG ((EFI_D_INFO, "HandleArray allocate memory resource failed.\n"));
+        return;
+    }
+
+    *HandleCount = 0;
+
+    while(1)
+    {
+        Status = mSmbios->GetNext(
+                            mSmbios,
+                            &SmbiosHandle,
+                            &SmbiosType,
+                            &LinkTypeData,
+                            NULL
+                            );
+
+        if(!EFI_ERROR(Status))
+        {
+            (*HandleArray)[*HandleCount] = LinkTypeData->Handle;
+            (*HandleCount)++;
+        }
+        else
+        {
+            break;
+        }
+    }
+}
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni
new file mode 100644
index 0000000..2e434e3
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscLibString.uni
@@ -0,0 +1,28 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+
+/=#
+
+#langdef en-US "English"
+
+#include "./Type00/MiscBiosVendor.uni"
+#include "./Type01/MiscSystemManufacturer.uni"
+#include "./Type02/MiscBaseBoardManufacturer.uni"
+#include "./Type03/MiscChassisManufacturer.uni"
+#include "./Type13/MiscNumberOfInstallableLanguages.uni"
+#include "./Type09/MiscSystemSlotDesignation.uni"
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni
new file mode 100644
index 0000000..215952a
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendor.uni
@@ -0,0 +1,25 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+//#string STR_MISC_BIOS_VENDOR           #language en-US  "Bios Vendor"
+#string STR_MISC_BIOS_VERSION          #language en-US  "Bios Version"
+//#string STR_MISC_BIOS_RELEASE_DATE     #language en-US  "Bios Release Date"
+
+#string STR_MISC_BIOS_VENDOR           #language en-US  "Huawei Technologies Co., Ltd."
+#string STR_MISC_BIOS_RELEASE_DATE     #language en-US  "01/01/1900"
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c
new file mode 100644
index 0000000..b822768
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c
@@ -0,0 +1,105 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscBiosVendorData.c
+
+Abstract:
+
+  This file provide OEM to define Smbios Type0 Data
+
+Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/
+
+**/
+
+
+#include "SmbiosMisc.h"
+
+
+//
+// Static (possibly build generated) Bios Vendor data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = {
+    {                                          //Hdr
+        EFI_SMBIOS_TYPE_BIOS_INFORMATION,          // Type,
+        0,                                         // Length,
+        0                                          // Handle
+    },
+    1,                                         //Vendor
+    2,                                         //BiosVersion
+    0xE000,                                    //BiosSegment
+    3,                                         //BiosReleaseDate
+    0,                                         //BiosSize
+    {                                          //BiosCharacteristics
+        0,                                         // Reserved                          :2
+        0,                                         // Unknown                           :1
+        0,                                         // BiosCharacteristicsNotSupported   :1
+        0,                                         // IsaIsSupported                    :1
+        0,                                         // McaIsSupported                    :1
+        0,                                         // EisaIsSupported                   :1
+        1,                                         // PciIsSupported                    :1
+        0,                                         // PcmciaIsSupported                 :1
+        0,                                         // PlugAndPlayIsSupported            :1
+        0,                                         // ApmIsSupported                    :1
+        1,                                         // BiosIsUpgradable                  :1
+        1,                                         // BiosShadowingAllowed              :1
+        0,                                         // VlVesaIsSupported                 :1
+        0,                                         // EscdSupportIsAvailable            :1
+        1,                                         // BootFromCdIsSupported             :1
+        1,                                         // SelectableBootIsSupported         :1
+        0,                                         // RomBiosIsSocketed                 :1
+        0,                                         // BootFromPcmciaIsSupported         :1
+        1,                                         // EDDSpecificationIsSupported       :1
+        1,                                         // JapaneseNecFloppyIsSupported      :1
+        1,                                         // JapaneseToshibaFloppyIsSupported  :1
+        1,                                         // Floppy525_360IsSupported          :1
+        1,                                         // Floppy525_12IsSupported           :1
+        1,                                         // Floppy35_720IsSupported           :1
+        1,                                         // Floppy35_288IsSupported           :1
+        0,                                         // PrintScreenIsSupported            :1
+        1,                                         // Keyboard8042IsSupported           :1
+        0,                                         // SerialIsSupported                 :1
+        0,                                         // PrinterIsSupported                :1
+        1,                                         // CgaMonoIsSupported                :1
+        0,                                         // NecPc98                           :1
+        0                                          // ReservedForVendor                 :32
+    },
+
+    {
+        0x03,                                        //BIOSCharacteristicsExtensionBytes[0]
+        //  {                                          //BiosReserved
+        //    1,                                         // AcpiIsSupported                   :1
+        //    1,                                         // UsbLegacyIsSupported              :1
+        //    0,                                         // AgpIsSupported                    :1
+        //    0,                                         // I20BootIsSupported                :1
+        //    0,                                         // Ls120BootIsSupported              :1
+        //    0,                                         // AtapiZipDriveBootIsSupported      :1
+        //    0,                                         // Boot1394IsSupported               :1
+        //    0                                          // SmartBatteryIsSupported           :1
+        //  },
+        0x0D                                         //BIOSCharacteristicsExtensionBytes[1]
+        //  {                                          //SystemReserved
+        //    1,                                         //BiosBootSpecIsSupported            :1
+        //    0,                                         //FunctionKeyNetworkBootIsSupported  :1
+        //    1,                                         //TargetContentDistributionEnabled   :1
+        //    1,                                         //UefiSpecificationSupported         :1
+        //    0,                                         //VirtualMachineSupported            :1
+        //    0                                          //ExtensionByte2Reserved             :3
+        //  },
+    },
+    0,                                        //SystemBiosMajorRelease;
+    0,                                        //SystemBiosMinorRelease;
+    0xFF,                                     //EmbeddedControllerFirmwareMajorRelease;
+    0xFF                                      //EmbeddedControllerFirmwareMinorRelease;
+};
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c
new file mode 100644
index 0000000..9a42f04
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c
@@ -0,0 +1,258 @@
+/** @file
+
+  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+  MiscBiosVendorData.c
+
+Abstract:
+
+  This driver parses the mMiscSubclassDataTable structure and reports
+  any generated data to the DataHub.
+
+Based on the files under Nt32Pkg/MiscSubClassPlatformDxe/
+
+--*/
+
+//
+#include "SmbiosMisc.h"
+#include <Library/HobLib.h>
+#include <Guid/VersionInfoHobGuid.h>
+
+
+/**
+  Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with '64k'
+  as the unit.
+
+  @param  Value              Pointer to Base2_Data
+
+  @retval
+
+**/
+UINT8
+Base2ToByteWith64KUnit (
+  IN  UINTN  Value
+  )
+{
+    UINT8 Size;
+
+    Size = Value / SIZE_64KB + (Value % SIZE_64KB + SIZE_64KB - 1) / SIZE_64KB;
+
+    return Size;
+}
+
+
+/**
+
+**/
+VOID *
+GetBiosReleaseDate (
+  )
+{
+    CHAR16                  *ReleaseDate = NULL;
+    VERSION_INFO            *Version;
+    VOID                    *Hob;
+
+    ReleaseDate = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+    if(NULL == ReleaseDate)
+    {
+        return NULL;
+    }
+
+    Hob = GetFirstGuidHob (&gVersionInfoHobGuid);
+    if (Hob == NULL) {
+      DEBUG ((EFI_D_ERROR, "[%a:%d] Version info HOB not found!\n", __FUNCTION__, __LINE__));
+      return NULL;
+    }
+
+    Version = GET_GUID_HOB_DATA (Hob);
+    (VOID)UnicodeSPrintAsciiFormat( ReleaseDate,
+                          (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH,
+                          "%02d/%02d/%4d",
+                          Version->BuildTime.Month,
+                          Version->BuildTime.Day,
+                          Version->BuildTime.Year
+                          );
+
+    return ReleaseDate;
+}
+
+VOID *
+GetBiosVersion (
+  )
+{
+    VERSION_INFO            *Version;
+    VOID                    *Hob;
+
+    Hob = GetFirstGuidHob (&gVersionInfoHobGuid);
+    if (Hob == NULL) {
+      DEBUG ((EFI_D_ERROR, "[%a:%d] Version info HOB not found!\n", __FUNCTION__, __LINE__));
+      return NULL;
+    }
+    Version = GET_GUID_HOB_DATA (Hob);
+    return Version->String;
+}
+
+
+/**
+  This function makes boot time changes to the contents of the
+  MiscBiosVendor (Type 0).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscBiosVendor)
+{
+    CHAR8                 *OptionalStrStart;
+    UINTN                 VendorStrLen;
+    UINTN                 VerStrLen;
+    UINTN                 DateStrLen;
+    UINTN                 BiosPhysicalSizeHexValue;
+    CHAR16                *Vendor;
+    CHAR16                *Version;
+    CHAR16                *ReleaseDate;
+    CHAR16                *Char16String;
+    EFI_STATUS            Status;
+    STRING_REF            TokenToUpdate;
+    STRING_REF            TokenToGet;
+    SMBIOS_TABLE_TYPE0    *SmbiosRecord;
+    EFI_SMBIOS_HANDLE     SmbiosHandle;
+    SMBIOS_TABLE_TYPE0    *InputData;
+
+    //
+    // First check for invalid parameters.
+    //
+    if (RecordData == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    InputData = (SMBIOS_TABLE_TYPE0 *)RecordData;
+
+    Vendor = (CHAR16 *) PcdGetPtr (PcdFirmwareVendor);
+    if (StrLen(Vendor) > 0)
+    {
+        TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
+        HiiSetString (mHiiHandle, TokenToUpdate, Vendor, NULL);
+    }
+
+    Version = GetBiosVersion();
+    if (StrLen (Version) > 0)
+    {
+        TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
+        HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);
+    }
+    else
+    {
+        Version = (CHAR16 *) PcdGetPtr (PcdBiosVersionForBmc);
+        if (StrLen (Version) > 0)
+        {
+            TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
+            HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);
+        }
+        else
+        {
+            Version = (CHAR16 *) PcdGetPtr (PcdBiosVersionString);
+            if (StrLen (Version) > 0)
+            {
+                TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
+                HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);
+            }
+        }
+    }
+
+    Char16String = GetBiosReleaseDate ();
+    if (StrLen(Char16String) > 0)
+    {
+        TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
+        HiiSetString (mHiiHandle, TokenToUpdate, Char16String, NULL);
+    }
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
+    Vendor = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    VendorStrLen = StrLen(Vendor);
+
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);
+    Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    VerStrLen = StrLen(Version);
+
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
+    ReleaseDate = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    DateStrLen = StrLen(ReleaseDate);
+
+    //
+    // Now update the BiosPhysicalSize
+    //
+    BiosPhysicalSizeHexValue = FixedPcdGet32 (PcdFdSize);
+
+    //
+    // Two zeros following the last string.
+    //
+    SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1);
+    if(NULL == SmbiosRecord)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto Exit;
+    }
+
+    (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE0));
+
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);
+    SmbiosRecord->BiosSegment = (UINT16)(FixedPcdGet32 (PcdFdBaseAddress) / 0x10000);
+    SmbiosRecord->BiosSize = Base2ToByteWith64KUnit(BiosPhysicalSizeHexValue) - 1;
+
+    OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+    UnicodeStrToAsciiStr(Vendor, OptionalStrStart);
+    UnicodeStrToAsciiStr(Version, OptionalStrStart + VendorStrLen + 1);
+    UnicodeStrToAsciiStr(ReleaseDate, OptionalStrStart + VendorStrLen + 1 + VerStrLen + 1);
+    //
+    // Now we have got the full smbios record, call smbios protocol to add this record.
+    //
+    Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(SmbiosRecord);
+
+Exit:
+    if(Vendor != NULL)
+    {
+        FreePool(Vendor);
+    }
+
+    if(Version != NULL)
+    {
+        FreePool(Version);
+    }
+
+    if(ReleaseDate != NULL)
+    {
+        FreePool(ReleaseDate);
+    }
+
+    if(Char16String != NULL)
+    {
+        FreePool(Char16String);
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni
new file mode 100644
index 0000000..1632f83
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturer.uni
@@ -0,0 +1,27 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+#string STR_MISC_SYSTEM_MANUFACTURER   #language en-US  "Huawei Technologies Co., Ltd."
+//#string STR_MISC_SYSTEM_PRODUCT_NAME   #language en-US  "To be filled by O.E.M."
+#string STR_MISC_SYSTEM_PRODUCT_NAME   #language en-US  "PANGEA"
+//#string STR_MISC_SYSTEM_VERSION        #language en-US  "To be filled by O.E.M."
+#string STR_MISC_SYSTEM_VERSION        #language en-US  "V200R002"
+#string STR_MISC_SYSTEM_SERIAL_NUMBER  #language en-US  "To be filled by O.E.M."
+#string STR_MISC_SYSTEM_SKU_NUMBER     #language en-US  "To be filled by O.E.M."
+#string STR_MISC_SYSTEM_FAMILY         #language en-US  "To be filled by O.E.M."
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c
new file mode 100644
index 0000000..37fc33b
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c
@@ -0,0 +1,52 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscSystemManufacturerData.c
+
+Abstract:
+
+  This file provide OEM to define Smbios Type1 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+
+**/
+
+/* Modify list
+DATA        AUTHOR            REASON
+*/
+
+#include "SmbiosMisc.h"
+
+
+//
+// Static (possibly build generated) System Manufacturer data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) = {
+    {                                               // Hdr
+        EFI_SMBIOS_TYPE_SYSTEM_INFORMATION,             // Type,
+        0,                                              // Length,
+        0                                               // Handle
+    },
+    1,                                              // Manufacturer
+    2,                                              // ProductName
+    3,                                              // Version
+    4,                                              // SerialNumber
+    {                                               // Uuid
+        0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa, 0xbb, 0xcc}
+    },
+    SystemWakeupTypePowerSwitch,                    // SystemWakeupType
+    5,                                              // SKUNumber,
+    6                                               // Family
+};
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c
new file mode 100644
index 0000000..fcefe24
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c
@@ -0,0 +1,195 @@
+/*++
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscSystemManufacturerFunction.c
+
+Abstract:
+
+  This driver parses the mMiscSubclassDataTable structure and reports
+  any generated data to smbios.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+
+**/
+
+#include "SmbiosMisc.h"
+
+/**
+  This function makes boot time changes to the contents of the
+  MiscSystemManufacturer (Type 1).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer)
+{
+    CHAR8                           *OptionalStrStart;
+    UINTN                           ManuStrLen;
+    UINTN                           VerStrLen;
+    UINTN                           PdNameStrLen;
+    UINTN                           SerialNumStrLen;
+    UINTN                           SKUNumStrLen;
+    UINTN                           FamilyStrLen;
+    EFI_STRING                      Manufacturer;
+    EFI_STRING                      ProductName;
+    EFI_STRING                      Version;
+    EFI_STRING                      SerialNumber;
+    EFI_STRING                      SKUNumber;
+    EFI_STRING                      Family;
+    STRING_REF                      TokenToGet;
+    EFI_SMBIOS_HANDLE               SmbiosHandle;
+    SMBIOS_TABLE_TYPE1              *SmbiosRecord;
+    SMBIOS_TABLE_TYPE1              *InputData;
+    EFI_STATUS                      Status;
+    STRING_REF                      TokenToUpdate;
+    CHAR16                          *Product;
+    CHAR16                          *pVersion;
+
+    EFI_GUID                        Uuid;
+
+    //
+    // First check for invalid parameters.
+    //
+    if (RecordData == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    InputData = (SMBIOS_TABLE_TYPE1 *)RecordData;
+
+    Product = (CHAR16 *) PcdGetPtr (PcdSystemProductName);
+    if (StrLen(Product) > 0)
+    {
+        TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
+        HiiSetString (mHiiHandle, TokenToUpdate, Product, NULL);
+    }
+
+    pVersion = (CHAR16 *) PcdGetPtr (PcdSystemVersion);
+    if (StrLen(pVersion) > 0)
+    {
+        TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
+        HiiSetString (mHiiHandle, TokenToUpdate, pVersion, NULL);
+    }
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME), ProductNameType01);
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), SerialNumType01);
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER), SystemManufacturerType01);
+
+    TokenToGet   = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);
+    Manufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    ManuStrLen   = StrLen(Manufacturer);
+
+    TokenToGet   = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
+    ProductName  = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    PdNameStrLen = StrLen(ProductName);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
+    Version    = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    VerStrLen  = StrLen(Version);
+
+    TokenToGet      = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER);
+    SerialNumber    = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    SerialNumStrLen = StrLen(SerialNumber);
+
+    TokenToGet   = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER);
+    SKUNumber    = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    SKUNumStrLen = StrLen(SKUNumber);
+
+    TokenToGet   = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY);
+    Family       = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    FamilyStrLen = StrLen(Family);
+
+    //
+    // Two zeros following the last string.
+    //
+    SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen      + 1
+                                                                + PdNameStrLen    + 1
+                                                                + VerStrLen       + 1
+                                                                + SerialNumStrLen + 1
+                                                                + SKUNumStrLen    + 1
+                                                                + FamilyStrLen    + 1 + 1);
+
+    if (NULL == SmbiosRecord)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto Exit;
+    }
+
+    (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE1));
+
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1);
+
+    SmbiosRecord->Uuid = InputData->Uuid;
+    Status = GetUuidType1 (&Uuid);
+    if (!EFI_ERROR (Status))
+    {
+        SmbiosRecord->Uuid = Uuid;
+    }
+
+    OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+    UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);
+    UnicodeStrToAsciiStr(ProductName,  OptionalStrStart + ManuStrLen + 1);
+    UnicodeStrToAsciiStr(Version,      OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1);
+    UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1);
+    UnicodeStrToAsciiStr(SKUNumber,    OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);
+    UnicodeStrToAsciiStr(Family,       OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen + 1);
+
+    //
+    // Now we have got the full smbios record, call smbios protocol to add this record.
+    //
+    Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(SmbiosRecord);
+
+Exit:
+    if(Manufacturer != NULL)
+    {
+        FreePool(Manufacturer);
+    }
+
+    if(ProductName != NULL)
+    {
+        FreePool(ProductName);
+    }
+
+    if(Version != NULL)
+    {
+        FreePool(Version);
+    }
+
+    if(SerialNumber != NULL)
+    {
+        FreePool(SerialNumber);
+    }
+
+    if(SKUNumber != NULL)
+    {
+        FreePool(SKUNumber);
+    }
+
+    if(Family != NULL)
+    {
+        FreePool(Family);
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni
new file mode 100644
index 0000000..11320c0
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturer.uni
@@ -0,0 +1,27 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+#string STR_MISC_BASE_BOARD_MANUFACTURER     #language en-US  "Huawei Technologies Co., Ltd."
+//#string STR_MISC_BASE_BOARD_PRODUCT_NAME     #language en-US  "To Be Filled By O.E.M."
+#string STR_MISC_BASE_BOARD_PRODUCT_NAME     #language en-US  "STL2SPCA"
+//#string STR_MISC_BASE_BOARD_VERSION          #language en-US  "To Be Filled By O.E.M."
+#string STR_MISC_BASE_BOARD_VERSION          #language en-US  "V200R002"
+#string STR_MISC_BASE_BOARD_SERIAL_NUMBER    #language en-US  "To Be Filled By O.E.M."
+#string STR_MISC_BASE_BOARD_ASSET_TAG        #language en-US  "To Be Filled By O.E.M."
+#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US  "To Be Filled By O.E.M."
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c
new file mode 100644
index 0000000..20991b1
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c
@@ -0,0 +1,56 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscBaseBoardManufacturerData.c
+
+Abstract:
+
+  This file provide OEM to define Smbios Type2 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+//
+// Static (possibly build generated) Chassis Manufacturer data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) = {
+    {                                                       // Hdr
+        EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION,                // Type,
+        0,                                                    // Length,
+        0                                                     // Handle
+    },
+    1,                                                      // BaseBoardManufacturer
+    2,                                                      // BaseBoardProductName
+    3,                                                      // BaseBoardVersion
+    4,                                                      // BaseBoardSerialNumber
+    5,                                                      // BaseBoardAssetTag
+    {                                                       // FeatureFlag
+        1,                                                    // Motherboard           :1
+        0,                                                    // RequiresDaughterCard  :1
+        0,                                                    // Removable             :1
+        1,                                                    // Replaceable           :1
+        0,                                                    // HotSwappable          :1
+        0                                                     // Reserved              :3
+    },
+    6,                                                      // BaseBoardChassisLocation
+    0,                                                      // ChassisHandle;
+    BaseBoardTypeMotherBoard,                               // BoardType;
+    0,                                                      // NumberOfContainedObjectHandles;
+    {
+        0
+    }                                                       // ContainedObjectHandles[1];
+};
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c
new file mode 100644
index 0000000..a141f9e
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c
@@ -0,0 +1,198 @@
+/** @file
+
+  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscBaseBoardManufacturerFunction.c
+
+Abstract:
+
+  This driver parses the mSmbiosMiscDataTable structure and reports
+  any generated data using SMBIOS protocol.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+
+/**
+  This function makes basic board manufacturer to the contents of the
+  Misc Base Board Manufacturer (Type 2).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer)
+{
+    CHAR8                             *OptionalStrStart;
+    UINTN                             ManuStrLen;
+    UINTN                             ProductNameStrLen;
+    UINTN                             VerStrLen;
+    UINTN                             SerialNumStrLen;
+    UINTN                             AssetTagStrLen;
+    UINTN                             ChassisLocaStrLen;
+    UINTN                             HandleCount = 0;
+    UINT16                            *HandleArray = NULL;
+    CHAR16                            *BaseBoardManufacturer;
+    CHAR16                            *BaseBoardProductName;
+    CHAR16                            *Version;
+    EFI_STRING                        SerialNumber;
+    EFI_STRING                        AssetTag;
+    EFI_STRING                        ChassisLocation;
+    STRING_REF                        TokenToGet;
+    EFI_SMBIOS_HANDLE                 SmbiosHandle;
+    SMBIOS_TABLE_TYPE2                *SmbiosRecord;
+    SMBIOS_TABLE_TYPE2                *InputData = NULL;
+    EFI_STATUS                        Status;
+
+    STRING_REF                        TokenToUpdate;
+    //CHAR16                            *ProductName;
+    //CHAR16                            *pVersion;
+    //uniBIOS_y00216284_018_end 2015-1-13 09:08:22
+
+    //
+    // First check for invalid parameters.
+    //
+    if (RecordData == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    InputData = (SMBIOS_TABLE_TYPE2*)RecordData;
+
+    BaseBoardProductName = (CHAR16 *) PcdGetPtr (PcdBaseBoardProductName);
+    if (StrLen(BaseBoardProductName) > 0)
+    {
+        TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);
+        HiiSetString (mHiiHandle, TokenToUpdate, BaseBoardProductName, NULL);
+    }
+
+    Version = (CHAR16 *) PcdGetPtr (PcdBaseBoardVersion);
+    if (StrLen(Version) > 0)
+    {
+        TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);
+        HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);
+    }
+
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG), AssertTagType02);
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER), SrNumType02);
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER), BoardManufacturerType02);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);
+    BaseBoardManufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    ManuStrLen = StrLen(BaseBoardManufacturer);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);
+    BaseBoardProductName = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    ProductNameStrLen = StrLen(BaseBoardProductName);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);
+    Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    VerStrLen = StrLen(Version);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER);
+    SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    SerialNumStrLen = StrLen(SerialNumber);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);
+    AssetTag = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    AssetTagStrLen = StrLen(AssetTag);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);
+    ChassisLocation = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    ChassisLocaStrLen = StrLen(ChassisLocation);
+
+    //
+    // Two zeros following the last string.
+    //
+    SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE2) + ManuStrLen        + 1
+                                                                + ProductNameStrLen + 1
+                                                                + VerStrLen         + 1
+                                                                + SerialNumStrLen   + 1
+                                                                + AssetTagStrLen    + 1
+                                                                + ChassisLocaStrLen + 1 + 1);
+    if (NULL == SmbiosRecord)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto Exit;
+    }
+
+    (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE2));
+    SmbiosRecord->Hdr.Length        = sizeof (SMBIOS_TABLE_TYPE2);
+
+    //
+    //  Update Contained objects Handle
+    //
+    SmbiosRecord->NumberOfContainedObjectHandles = 0;
+    GetLinkTypeHandle(EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, &HandleArray, &HandleCount);
+    if(HandleCount)
+    {
+        SmbiosRecord->ChassisHandle = HandleArray[0];
+    }
+
+    FreePool(HandleArray);
+
+    OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+    UnicodeStrToAsciiStr(BaseBoardManufacturer, OptionalStrStart);
+    UnicodeStrToAsciiStr(BaseBoardProductName,  OptionalStrStart + ManuStrLen + 1);
+    UnicodeStrToAsciiStr(Version,               OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1);
+    UnicodeStrToAsciiStr(SerialNumber,          OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1);
+    UnicodeStrToAsciiStr(AssetTag,              OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 );
+    UnicodeStrToAsciiStr(ChassisLocation,       OptionalStrStart + ManuStrLen + 1 + ProductNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssetTagStrLen + 1);
+
+    Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(SmbiosRecord);
+
+Exit:
+    if(BaseBoardManufacturer != NULL)
+    {
+        FreePool(BaseBoardManufacturer);
+    }
+
+    if(BaseBoardProductName != NULL)
+    {
+        FreePool(BaseBoardProductName);
+    }
+
+    if(Version != NULL)
+    {
+        FreePool(Version);
+    }
+
+    if(SerialNumber != NULL)
+    {
+        FreePool(SerialNumber);
+    }
+
+    if(AssetTag != NULL)
+    {
+        FreePool(AssetTag);
+    }
+
+    if(ChassisLocation != NULL)
+    {
+        FreePool(ChassisLocation);
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni
new file mode 100644
index 0000000..543ef00
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturer.uni
@@ -0,0 +1,24 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+#string STR_MISC_CHASSIS_MANUFACTURER  #language en-US  "Huawei Technologies Co., Ltd."
+#string STR_MISC_CHASSIS_VERSION       #language en-US  "To Be Filled By O.E.M."
+#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US  "To Be Filled By O.E.M."
+#string STR_MISC_CHASSIS_ASSET_TAG     #language en-US  "To Be Filled By O.E.M."
+#string STR_MISC_CHASSIS_SKU_NUMBER    #language en-US  "To Be Filled By O.E.M."
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c
new file mode 100644
index 0000000..6237fbe
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c
@@ -0,0 +1,66 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscChassisManufacturerData.c
+
+Abstract:
+
+  This file provide OEM to define Smbios Type3 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+/* Modify list
+DATA        AUTHOR            REASON
+*/
+
+#include "SmbiosMisc.h"
+
+
+//
+// Static (possibly build generated) Chassis Manufacturer data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {
+    {                                                       // Hdr
+        EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE  ,                   // Type,
+        0,                                                    // Length,
+        0                                                     // Handle
+    },
+    1,                                                      // Manufactrurer
+    MiscChassisTypeMainServerChassis,                       // Type
+    2,                                                      // Version
+    3,                                                      // SerialNumber
+    4,                                                      // AssetTag
+    ChassisStateSafe,                                       // BootupState
+    ChassisStateSafe,                                       // PowerSupplyState
+    ChassisStateSafe,                                       // ThermalState
+    ChassisSecurityStatusNone,                              // SecurityState
+    {
+        0,                                                    // OemDefined[0]
+        0,                                                    // OemDefined[1]
+        0,                                                    // OemDefined[2]
+        0                                                     // OemDefined[3]
+    },
+    2,                                                      // Height
+    1,                                                      // NumberofPowerCords
+    0,                                                      // ContainedElementCount
+    0,                                                      // ContainedElementRecordLength
+    {                                                       // ContainedElements[0]
+        {
+            0,                                                    // ContainedElementType
+            0,                                                    // ContainedElementMinimum
+            0                                                     // ContainedElementMaximum
+        }
+    }
+};
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
new file mode 100644
index 0000000..4bb1701
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
@@ -0,0 +1,199 @@
+/** @file
+
+Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscChassisManufacturerFunction.c
+
+Abstract:
+
+  This driver parses the mMiscSubclassDataTable structure and reports
+  any generated data to smbios.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+/* Modify list
+DATA        AUTHOR            REASON
+*/
+
+#include "SmbiosMisc.h"
+
+UINT8
+GetChassisType (
+)
+{
+    EFI_STATUS                      Status;
+    UINT8                           ChassisType;
+    Status = IpmiGetChassisType(&ChassisType);
+    if (EFI_ERROR(Status))
+    {
+       return 0;
+    }
+
+    return ChassisType;
+}
+
+/**
+  This function makes boot time changes to the contents of the
+  MiscChassisManufacturer (Type 3).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer)
+{
+    CHAR8                           *OptionalStrStart;
+    UINTN                           ManuStrLen;
+    UINTN                           VerStrLen;
+    UINTN                           AssertTagStrLen;
+    UINTN                           SerialNumStrLen;
+    UINTN                           ChaNumStrLen;
+    EFI_STRING                      Manufacturer;
+    EFI_STRING                      Version;
+    EFI_STRING                      SerialNumber;
+    EFI_STRING                      AssertTag;
+    EFI_STRING                      ChassisSkuNumber;
+    STRING_REF                      TokenToGet;
+    EFI_SMBIOS_HANDLE               SmbiosHandle;
+    SMBIOS_TABLE_TYPE3              *SmbiosRecord;
+    SMBIOS_TABLE_TYPE3              *InputData;
+    EFI_STATUS                      Status;
+
+    UINT8                           ContainedElementCount;
+    CONTAINED_ELEMENT               ContainedElements = {0};
+    UINT8                           ExtendLength = 0;
+
+    UINT8                           ChassisType;
+
+    //
+    // First check for invalid parameters.
+    //
+    if (RecordData == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    InputData = (SMBIOS_TABLE_TYPE3 *)RecordData;
+
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG), AssetTagType03);
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER), SrNumType03);
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_VERSION), VersionType03);
+    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER), ManufacturerType03);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);
+    Manufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    ManuStrLen = StrLen(Manufacturer);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION);
+    Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    VerStrLen = StrLen(Version);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);
+    SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    SerialNumStrLen = StrLen(SerialNumber);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);
+    AssertTag = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    AssertTagStrLen = StrLen(AssertTag);
+
+    TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER);
+    ChassisSkuNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    ChaNumStrLen = StrLen(ChassisSkuNumber);
+
+    ContainedElementCount = InputData->ContainedElementCount;
+
+    if (ContainedElementCount > 1)
+    {
+        ExtendLength = (ContainedElementCount - 1) * sizeof (CONTAINED_ELEMENT);
+    }
+
+    //
+    // Two zeros following the last string.
+    //
+    SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength    + 1
+                                                                + ManuStrLen      + 1
+                                                                + VerStrLen       + 1
+                                                                + SerialNumStrLen + 1
+                                                                + AssertTagStrLen + 1
+                                                                + ChaNumStrLen    + 1 + 1);
+    if (NULL == SmbiosRecord)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto Exit;
+    }
+
+    (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE3));
+
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength + 1;
+
+    ChassisType = GetChassisType ();
+    if (ChassisType != 0)
+    {
+        SmbiosRecord->Type  = ChassisType;
+    }
+
+    //ContainedElements
+    (VOID)CopyMem(SmbiosRecord + 1, &ContainedElements, ExtendLength);
+
+    //ChassisSkuNumber
+    *((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength) = 5;
+
+    OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength + 1);
+    UnicodeStrToAsciiStr(Manufacturer,     OptionalStrStart);
+    UnicodeStrToAsciiStr(Version,          OptionalStrStart + ManuStrLen + 1);
+    UnicodeStrToAsciiStr(SerialNumber,     OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1);
+    UnicodeStrToAsciiStr(AssertTag,        OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);
+    UnicodeStrToAsciiStr(ChassisSkuNumber, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen +1 + AssertTagStrLen + 1);
+    //
+    // Now we have got the full smbios record, call smbios protocol to add this record.
+    //
+    Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(SmbiosRecord);
+
+Exit:
+    if(Manufacturer != NULL)
+    {
+        FreePool(Manufacturer);
+    }
+
+    if(Version != NULL)
+    {
+        FreePool(Version);
+    }
+
+    if(SerialNumber != NULL)
+    {
+        FreePool(SerialNumber);
+    }
+
+    if(AssertTag != NULL)
+    {
+        FreePool(AssertTag);
+    }
+
+    if(ChassisSkuNumber != NULL)
+    {
+        FreePool(ChassisSkuNumber);
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni
new file mode 100644
index 0000000..19968f2
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignation.uni
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c
new file mode 100644
index 0000000..f9b1f03
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationData.c
@@ -0,0 +1,162 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+    MiscSystemSlotDesignationData.c
+
+Abstract:
+
+  This file provide OEM to define Smbios Type09 Data
+
+**/
+
+#include "SmbiosMisc.h"
+
+
+//
+// Static (possibly build generated) Bios Vendor data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie0) = {
+  {                                                     // Hdr
+    EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,
+    0,                                                    // Length,
+    0                                                     // Handle
+  },
+  1,                                                    // SlotDesignation
+  SlotTypePciExpressX8,     // SlotType
+  SlotDataBusWidth8X,       // SlotDataBusWidth
+  SlotUsageOther,           // SlotUsage
+  SlotLengthOther,          // SlotLength
+  0x0000,                   // SlotId
+  {                         // SlotCharacteristics1
+    0,                      // CharacteristicsUnknown  :1;
+    0,                      // Provides50Volts         :1;
+    0,                      // Provides33Volts         :1;
+    0,                      // SharedSlot              :1;
+    0,                      // PcCard16Supported       :1;
+    0,                      // CardBusSupported        :1;
+    0,                      // ZoomVideoSupported      :1;
+    0                       // ModemRingResumeSupported:1;
+  },
+  {                         // SlotCharacteristics2
+    0,                      // PmeSignalSupported      :1;
+    0,                      // HotPlugDevicesSupported  :1;
+    0,                      // SmbusSignalSupported    :1;
+    0                       // Reserved                :5;
+  },
+  0x00,                     // SegmentGroupNum
+  0x00,                     // BusNum
+  0                         // DevFuncNum
+};
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie1) = {
+  {                                                     // Hdr
+    EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,
+    0,                                                    // Length,
+    0                                                     // Handle
+  },
+  1,                                                    // SlotDesignation
+  SlotTypePciExpressX8,     // SlotType
+  SlotDataBusWidth8X,       // SlotDataBusWidth
+  SlotUsageAvailable,       // SlotUsage
+  SlotLengthOther,          // SlotLength
+  0x0001,                   // SlotId
+  {                         // SlotCharacteristics1
+    0,                      // CharacteristicsUnknown  :1;
+    0,                      // Provides50Volts         :1;
+    0,                      // Provides33Volts         :1;
+    0,                      // SharedSlot              :1;
+    0,                      // PcCard16Supported       :1;
+    0,                      // CardBusSupported        :1;
+    0,                      // ZoomVideoSupported      :1;
+    0                       // ModemRingResumeSupported:1;
+  },
+  {                         // SlotCharacteristics2
+    0,                      // PmeSignalSupported      :1;
+    0,                      // HotPlugDevicesSupported  :1;
+    0,                      // SmbusSignalSupported    :1;
+    0                       // Reserved                :5;
+  },
+  0x00,                     // SegmentGroupNum
+  0x40,                     // BusNum
+  0                         // DevFuncNum
+};
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie2) = {
+  {                                                     // Hdr
+    EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,
+    0,                                                    // Length,
+    0                                                     // Handle
+  },
+  1,                                                    // SlotDesignation
+  SlotTypePciExpressX8,     // SlotType
+  SlotDataBusWidth8X,       // SlotDataBusWidth
+  SlotUsageOther,           // SlotUsage
+  SlotLengthOther,          // SlotLength
+  0x0002,                   // SlotId
+  {                         // SlotCharacteristics1
+    0,                      // CharacteristicsUnknown  :1;
+    0,                      // Provides50Volts         :1;
+    0,                      // Provides33Volts         :1;
+    0,                      // SharedSlot              :1;
+    0,                      // PcCard16Supported       :1;
+    0,                      // CardBusSupported        :1;
+    0,                      // ZoomVideoSupported      :1;
+    0                       // ModemRingResumeSupported:1;
+  },
+  {                         // SlotCharacteristics2
+    0,                      // PmeSignalSupported      :1;
+    0,                      // HotPlugDevicesSupported  :1;
+    0,                      // SmbusSignalSupported    :1;
+    0                       // Reserved                :5;
+  },
+  0x00,                     // SegmentGroupNum
+  0x80,                     // BusNum
+  0                         // DevFuncNum
+};
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotDesignationPcie3) = {
+  {                                                     // Hdr
+    EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,
+    0,                                                    // Length,
+    0                                                     // Handle
+  },
+  1,                                                    // SlotDesignation
+  SlotTypePciExpressX4,     // SlotType
+  SlotDataBusWidth4X,       // SlotDataBusWidth
+  SlotUsageOther,           // SlotUsage
+  SlotLengthOther,          // SlotLength
+  0x0003,                   // SlotId
+  {                         // SlotCharacteristics1
+    0,                      // CharacteristicsUnknown  :1;
+    0,                      // Provides50Volts         :1;
+    0,                      // Provides33Volts         :1;
+    0,                      // SharedSlot              :1;
+    0,                      // PcCard16Supported       :1;
+    0,                      // CardBusSupported        :1;
+    0,                      // ZoomVideoSupported      :1;
+    0                       // ModemRingResumeSupported:1;
+  },
+  {                         // SlotCharacteristics2
+    0,                      // PmeSignalSupported      :1;
+    0,                      // HotPlugDevicesSupported  :1;
+    0,                      // SmbusSignalSupported    :1;
+    0                       // Reserved                :5;
+  },
+  0x00,                     // SegmentGroupNum
+  0xC0,                     // BusNum
+  0                         // DevFuncNum
+};
+
+/* eof - MiscSystemSlotsData.c */
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c
new file mode 100644
index 0000000..bc33639
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c
@@ -0,0 +1,201 @@
+/** @file
+  BIOS system slot designator information boot time changes.
+  SMBIOS type 9.
+
+  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SmbiosMisc.h"
+
+#include <Library/SerdesLib.h>
+
+extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie0Data;
+extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie1Data;
+extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie2Data;
+extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie3Data;
+
+VOID
+UpdateSlotDesignation (
+  IN SMBIOS_TABLE_TYPE9 *InputData
+  )
+{
+    STRING_REF                      TokenToUpdate;
+    CHAR16                          *SlotDesignation;
+    UINTN                           DesignationStrLen;
+
+    SlotDesignation = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
+    if (NULL == SlotDesignation)
+    {
+        return;
+    }
+
+    if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data)
+    {
+        UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE0");
+    }
+    else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data)
+    {
+        UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE1");
+    }
+    else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data)
+    {
+        UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE2");
+    }
+    else if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data)
+    {
+        UnicodeSPrint(SlotDesignation, SMBIOS_STRING_MAX_LENGTH - 1, L"PCIE3");
+    }
+
+    DesignationStrLen = StrLen (SlotDesignation);
+
+    if (DesignationStrLen > 0 )
+    {
+        TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_DESIGNATION);
+        HiiSetString (mHiiHandle, TokenToUpdate, SlotDesignation, NULL);
+    }
+
+    FreePool (SlotDesignation);
+}
+
+VOID
+UpdateSlotUsage(
+  IN OUT SMBIOS_TABLE_TYPE9 *InputData
+  )
+{
+    EFI_STATUS        Status;
+    SERDES_PARAM    SerdesParamA;
+    SERDES_PARAM    SerdesParamB;
+
+    Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status));
+        return;
+    }
+
+    //
+    // PCIE0
+    //
+    if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data)
+        && SerdesParamA.Hilink1Mode == EmHilink1Pcie0X8) {
+        InputData->CurrentUsage = SlotUsageAvailable;
+    }
+
+    //
+    // PCIE1
+    //
+    if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data)
+    {
+        if (SerdesParamA.Hilink0Mode == EmHilink0Pcie1X4Pcie2X4) {
+            InputData->SlotDataBusWidth = SlotDataBusWidth4X;
+        }
+    }
+
+    //
+    // PCIE2
+    //
+    if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data)
+    {
+        if (SerdesParamA.Hilink0Mode == EmHilink0Pcie1X4Pcie2X4) {
+            InputData->SlotDataBusWidth = SlotDataBusWidth4X;
+            InputData->CurrentUsage = SlotUsageAvailable;
+        } else if (SerdesParamA.Hilink2Mode == EmHilink2Pcie2X8) {
+            InputData->CurrentUsage = SlotUsageAvailable;
+        }
+    }
+
+    //
+    // PCIE3
+    //
+    if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data)
+        && SerdesParamA.Hilink5Mode == EmHilink5Pcie3X4) {
+        InputData->CurrentUsage = SlotUsageAvailable;
+    }
+}
+
+/**
+  This function makes boot time changes to the contents of the
+  MiscSystemSlotDesignator structure (Type 9).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscSystemSlotDesignation)
+{
+    CHAR8                              *OptionalStrStart;
+    UINTN                              SlotDesignationStrLen;
+    EFI_STATUS                         Status;
+    EFI_STRING                         SlotDesignation;
+    STRING_REF                         TokenToGet;
+    SMBIOS_TABLE_TYPE9                 *SmbiosRecord;
+    EFI_SMBIOS_HANDLE                  SmbiosHandle;
+    SMBIOS_TABLE_TYPE9                 *InputData = NULL;
+
+    //
+    // First check for invalid parameters.
+    //
+    if (RecordData == NULL)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    InputData = (SMBIOS_TABLE_TYPE9 *)RecordData;
+
+    UpdateSlotUsage (InputData);
+
+    UpdateSlotDesignation (InputData);
+
+    TokenToGet   = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_DESIGNATION);
+    SlotDesignation = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);
+    SlotDesignationStrLen = StrLen(SlotDesignation);
+
+    //
+    // Two zeros following the last string.
+    //
+    SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE9) + SlotDesignationStrLen + 1 + 1);
+    if(NULL == SmbiosRecord)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        goto Exit;
+    }
+
+    (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE9));
+
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9);
+
+    OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+    UnicodeStrToAsciiStr(SlotDesignation, OptionalStrStart);
+    //
+    // Now we have got the full smbios record, call smbios protocol to add this record.
+    //
+
+    Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+    if(EFI_ERROR(Status))
+    {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type09 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(SmbiosRecord);
+
+Exit:
+    if(SlotDesignation != NULL)
+    {
+      FreePool(SlotDesignation);
+    }
+
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni
new file mode 100644
index 0000000..c9873ad
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguages.uni
@@ -0,0 +1,49 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+// Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+// --*/
+
+/=#
+
+/=#
+//
+// Language String (Long Format)
+//
+#string STR_MISC_BIOS_LANGUAGES_ENG_LONG        #language en-US  "en|US|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_FRA_LONG        #language en-US  "fr|CA|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_CHN_LONG        #language en-US  "zh|TW|unicode"
+#string STR_MISC_BIOS_LANGUAGES_JPN_LONG        #language en-US  "ja|JP|unicode"
+#string STR_MISC_BIOS_LANGUAGES_ITA_LONG        #language en-US  "it|IT|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_SPA_LONG        #language en-US  "es|ES|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_GER_LONG        #language en-US  "de|DE|iso8859-1"
+#string STR_MISC_BIOS_LANGUAGES_POR_LONG        #language en-US  "pt|PT|iso8859-1"
+
+
+//
+// Language String (Abbreviated Format)
+//
+#string STR_MISC_BIOS_LANGUAGES_ENG_ABBREVIATE  #language en-US  "enUS"
+#string STR_MISC_BIOS_LANGUAGES_FRA_ABBREVIATE  #language en-US  "frCA"
+#string STR_MISC_BIOS_LANGUAGES_CHN_ABBREVIATE  #language en-US  "zhTW"
+#string STR_MISC_BIOS_LANGUAGES_JPN_ABBREVIATE  #language en-US  "jaJP"
+#string STR_MISC_BIOS_LANGUAGES_ITA_ABBREVIATE  #language en-US  "itIT"
+#string STR_MISC_BIOS_LANGUAGES_SPA_ABBREVIATE  #language en-US  "esES"
+#string STR_MISC_BIOS_LANGUAGES_GER_ABBREVIATE  #language en-US  "deDE"
+#string STR_MISC_BIOS_LANGUAGES_POR_ABBREVIATE  #language en-US  "ptPT"
+
+#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_ABBREVIATE  #language en-US  "zhCN"
+#string STR_MISC_BIOS_LANGUAGES_SIMPLECH_LONG        #language en-US  "zh|CN|unicode"
+
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c
new file mode 100644
index 0000000..60f6160
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c
@@ -0,0 +1,46 @@
+/**@file
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscNumberOfInstallableLanguagesData.c
+
+Abstract:
+
+  This file provide OEM to define Smbios Type13 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+//
+// Static (possibly build generated) Bios Vendor data.
+//
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages) =
+{
+  {                                                     // Hdr
+    EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION,            // Type,
+    0,                                                    // Length,
+    0                                                     // Handle
+  },
+  0,                                                    // InstallableLanguages
+  0,                                                    // Flags
+  {
+    0                                                   // Reserved[15]
+  },
+  1                                                     // CurrentLanguage
+};
+
+/* eof - MiscNumberOfInstallableLanguagesData.c */
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c
new file mode 100644
index 0000000..1f8f3ea
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c
@@ -0,0 +1,163 @@
+/** @file
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+/* Modify list
+DATA        AUTHOR            REASON
+*/
+
+#include "SmbiosMisc.h"
+
+/**
+  Get next language from language code list (with separator ';').
+
+  @param  LangCode       Input: point to first language in the list. On
+                         Otput: point to next language in the list, or
+                                NULL if no more language in the list.
+  @param  Lang           The first language in the list.
+
+**/
+VOID
+EFIAPI
+GetNextLanguage (
+  IN OUT CHAR8      **LangCode,
+  OUT CHAR8         *Lang
+  )
+{
+  UINTN  Index;
+  CHAR8  *StringPtr;
+
+  if(NULL == LangCode || NULL == *LangCode || NULL == Lang) {
+    return;
+  }
+
+  Index     = 0;
+  StringPtr = *LangCode;
+  while (StringPtr[Index] != 0 && StringPtr[Index] != ';') {
+    Index++;
+  }
+
+  (VOID)CopyMem(Lang, StringPtr, Index);
+  Lang[Index] = 0;
+
+  if (StringPtr[Index] == ';') {
+    Index++;
+  }
+  *LangCode = StringPtr + Index;
+}
+
+/**
+  This function returns the number of supported languages on HiiHandle.
+
+  @param   HiiHandle    The HII package list handle.
+
+  @retval  The number of supported languages.
+
+**/
+UINT16
+EFIAPI
+GetSupportedLanguageNumber (
+  IN EFI_HII_HANDLE    HiiHandle
+  )
+{
+  CHAR8   *Lang;
+  CHAR8   *Languages;
+  CHAR8   *LanguageString;
+  UINT16  LangNumber;
+
+  Languages = HiiGetSupportedLanguages (HiiHandle);
+  if (Languages == NULL) {
+    return 0;
+  }
+
+  LangNumber = 0;
+  Lang = AllocatePool (AsciiStrSize (Languages));
+  if (Lang != NULL) {
+    LanguageString = Languages;
+    while (*LanguageString != 0) {
+      GetNextLanguage (&LanguageString, Lang);
+      LangNumber++;
+    }
+    FreePool (Lang);
+  }
+  FreePool (Languages);
+  return LangNumber;
+}
+
+
+/**
+  This function makes boot time changes to the contents of the
+  MiscNumberOfInstallableLanguages (Type 13).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscNumberOfInstallableLanguages)
+{
+  UINTN                                     LangStrLen;
+  CHAR8                                     CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];
+  CHAR8                                     *OptionalStrStart;
+  EFI_STATUS                                Status;
+  EFI_SMBIOS_HANDLE                         SmbiosHandle;
+  SMBIOS_TABLE_TYPE13                       *SmbiosRecord;
+  SMBIOS_TABLE_TYPE13                       *InputData = NULL;;
+
+  //
+  // First check for invalid parameters.
+  //
+  if (RecordData == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  InputData = (SMBIOS_TABLE_TYPE13 *)RecordData;
+
+  InputData->InstallableLanguages = GetSupportedLanguageNumber (mHiiHandle);
+
+  //
+  // Try to check if current langcode matches with the langcodes in installed languages
+  //
+  ZeroMem(CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1);
+  (VOID)AsciiStrCpyS(CurrentLang, SMBIOS_STRING_MAX_LENGTH - 1, "en|US|iso8859-1");
+  LangStrLen = AsciiStrLen(CurrentLang);
+
+  //
+  // Two zeros following the last string.
+  //
+  SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1);
+  if(NULL == SmbiosRecord) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE13));
+
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13);
+
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+  (VOID)AsciiStrCpyS(OptionalStrStart, SMBIOS_STRING_MAX_LENGTH - 1, CurrentLang);
+  //
+  // Now we have got the full smbios record, call smbios protocol to add this record.
+  //
+  Status = LogSmbiosData((UINT8*)SmbiosRecord, &SmbiosHandle);
+  if(EFI_ERROR(Status)) {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+  }
+
+  FreePool(SmbiosRecord);
+  return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c
new file mode 100644
index 0000000..9f04694
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c
@@ -0,0 +1,48 @@
+/**@file
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscBootInformationData.c
+
+Abstract:
+
+  This driver parses the mMiscSubclassDataTable structure and reports
+  any generated data to the DataHub.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+//
+// Static (possibly build generated) Bios Vendor data.
+//
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE32, MiscBootInformation) = {
+  {                                                     // Hdr
+    EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION,              // Type,
+    0,                                                    // Length,
+    0                                                     // Handle
+  },
+  {                                                     // Reserved[6]
+    0,
+    0,
+    0,
+    0,
+    0,
+    0
+  },
+  BootInformationStatusNoError                          // BootInformationStatus
+};
+
+/* eof - MiscBootInformationData.c */
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c
new file mode 100644
index 0000000..7840445
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c
@@ -0,0 +1,74 @@
+/** @file
+  boot information boot time changes.
+  SMBIOS type 32.
+
+Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+/* Modify list
+DATA        AUTHOR            REASON
+*/
+
+#include "SmbiosMisc.h"
+
+/**
+  This function makes boot time changes to the contents of the
+  MiscBootInformation (Type 32).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+
+MISC_SMBIOS_TABLE_FUNCTION(MiscBootInformation)
+{
+    EFI_STATUS                         Status;
+    EFI_SMBIOS_HANDLE                  SmbiosHandle;
+    SMBIOS_TABLE_TYPE32                *SmbiosRecord;
+    SMBIOS_TABLE_TYPE32                *InputData;
+
+    //
+    // First check for invalid parameters.
+    //
+    if (RecordData == NULL) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    InputData = (SMBIOS_TABLE_TYPE32 *)RecordData;
+
+    //
+    // Two zeros following the last string.
+    //
+    SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1);
+    if(NULL == SmbiosRecord) {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+    (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE32));
+
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32);
+
+    //
+    // Now we have got the full smbios record, call smbios protocol to add this record.
+    //
+    Status = LogSmbiosData( (UINT8*)SmbiosRecord, &SmbiosHandle);
+    if(EFI_ERROR(Status)) {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(SmbiosRecord);
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c
new file mode 100644
index 0000000..2dc99f1
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationData.c
@@ -0,0 +1,42 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscIpmiDeviceInformationData.c
+
+Abstract:
+
+  This file provide OEM to define Smbios Type38 Data
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+
+#include "SmbiosMisc.h"
+
+MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE38, MiscIpmiDeviceInformation) =
+{
+  {                                                       // Header
+   EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION,                 // Type;
+   0,                                                       // Length;
+   0                                                        // Handle;
+  },
+  IPMIDeviceInfoInterfaceTypeUnknown,                         // InterfaceType
+  0x00,                                                   // Ipmi Specification Revision
+  0,                                                      // I2CSlaveAddress
+  0xFF,                                                   // NvStorageDeviceAddress
+  0x88,                                                   // BaseAddress
+  0,                                                      // BaseAddressModifier/InterruptInfo
+  0                                                       // InterruptNumber
+};
+
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c
new file mode 100644
index 0000000..f198237
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type38/MiscIpmiDeviceInformationFunction.c
@@ -0,0 +1,87 @@
+/*++
+
+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MiscIpmiDeviceInformationFunction.c
+
+Abstract:
+
+  This driver parses the mMiscSubclassDataTable structure and reports
+  any generated data to smbios.
+
+Based on files under Nt32Pkg/MiscSubClassPlatformDxe/
+**/
+/* Modify list
+DATA        AUTHOR            REASON
+*/
+
+#include "SmbiosMisc.h"
+
+#include <Protocol/IpmiInterfaceProtocol.h>
+
+/**
+  This function makes the attributes of IPMI to the contents of the
+  MiscChassisManufacturer structure.
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscIpmiDeviceInformation)
+{
+    EFI_STATUS                      Status;
+    EFI_SMBIOS_HANDLE               SmbiosHandle;
+    SMBIOS_TABLE_TYPE38             *SmbiosRecord;
+    SMBIOS_TABLE_TYPE38             *InputData = NULL;
+
+    IPMI_INTERFACE_PROTOCOL         *Ipmi;
+
+    //
+    // First check for invalid parameters.
+    //
+    if (RecordData == NULL) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    InputData = (SMBIOS_TABLE_TYPE38*)RecordData;
+
+    SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE38) + 1 + 1);
+    if(NULL == SmbiosRecord) {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+    (VOID)CopyMem(SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE38));
+
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE38);
+
+    Status = gBS->LocateProtocol (&gIpmiInterfaceProtocolGuid, NULL, (VOID **)&Ipmi);
+    if (!EFI_ERROR (Status)) {
+        SmbiosRecord->InterfaceType = Ipmi->GetIpmiInterfaceType (Ipmi);
+        SmbiosRecord->BaseAddress = (UINT64)Ipmi->GetIpmiBaseAddress (Ipmi) | Ipmi->GetIpmiBaseAddressType (Ipmi);
+        SmbiosRecord->IPMISpecificationRevision = Ipmi->GetIpmiVersion (Ipmi);
+    }
+    //
+    // Now we have got the full smbios record, call smbios protocol to add this record.
+    //
+    Status = LogSmbiosData((UINT8*)SmbiosRecord, &SmbiosHandle);
+    if(EFI_ERROR(Status)) {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Smbios Type38 Table Log Failed! %r \n", __FUNCTION__, __LINE__, Status));
+    }
+
+    FreePool(SmbiosRecord);
+    return Status;
+}
diff --git a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c
new file mode 100644
index 0000000..8586e33
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c
@@ -0,0 +1,158 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Uefi.h>
+#include <Pi/PiDxeCis.h>
+#include <Library/DebugLib.h>
+#include <libfdt.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PrintLib.h>
+#include <Guid/Fdt.h>
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/FdtUpdateLib.h>
+
+STATIC
+EFI_STATUS
+InstallFdtIntoConfigurationTable (
+  IN VOID* FdtBlob,
+  IN UINTN FdtSize
+  )
+{
+  EFI_STATUS Status;
+
+  // Check the FDT header is valid. We only make this check in DEBUG mode in case the FDT header change on
+  // production device and this ASSERT() becomes not valid.
+  if(!(fdt_check_header (FdtBlob) == 0))
+  {
+      DEBUG ((EFI_D_ERROR,"can not find FdtBlob \n"));
+      return EFI_INVALID_PARAMETER;
+  }
+
+  // Ensure the Size of the Device Tree is smaller than the size of the read file
+  if(!((UINTN)fdt_totalsize (FdtBlob) <= FdtSize))
+  {
+      DEBUG ((EFI_D_ERROR,"FdtBlob <= FdtSize \n"));
+      return EFI_INVALID_PARAMETER;
+  }
+
+  // Install the FDT into the Configuration Table
+  Status = gBS->InstallConfigurationTable (&gFdtTableGuid, FdtBlob);
+
+  return Status;
+}
+
+EFI_STATUS
+SetNvramSpace (VOID)
+{
+    EFI_STATUS          Status;
+    EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0};
+
+    if (PcdGet64(PcdReservedNvramSize) == 0) {
+      return EFI_SUCCESS;
+    }
+
+    Status = gDS->GetMemorySpaceDescriptor(PcdGet64(PcdReservedNvramBase),&desp);
+    if(EFI_ERROR(Status)){
+         DEBUG ((EFI_D_ERROR,"get memory space error:--------- \n"));
+        return Status;
+    }
+    desp.Attributes |= EFI_MEMORY_RUNTIME | EFI_MEMORY_WB;
+    Status = gDS->SetMemorySpaceAttributes(PcdGet64(PcdReservedNvramBase),PcdGet64(PcdReservedNvramSize), desp.Attributes);
+    if(EFI_ERROR(Status)){
+        DEBUG ((EFI_D_ERROR,"set memory space error:--------- \n"));
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI UpdateFdt (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable)
+{
+    INTN                Error;
+    VOID*               Fdt;
+    UINT32              Size;
+    UINTN               NewFdtBlobSize;
+    UINTN               NewFdtBlobBase;
+    EFI_STATUS          Status = EFI_SUCCESS;
+    UINT32              Index = 0;
+    UINTN               FDTConfigTable;
+
+    (VOID) SetNvramSpace ();
+
+    Fdt = (VOID*)(PcdGet64(FdtFileAddress));
+
+
+    Error = fdt_check_header ((VOID*)(PcdGet64(FdtFileAddress)));
+    DEBUG ((EFI_D_ERROR,"fdtfileaddress:--------- 0x%lx\n",PcdGet64(FdtFileAddress)));
+    if (Error != 0)
+    {
+        DEBUG ((EFI_D_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error)));
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Size = (UINTN)fdt_totalsize ((VOID*)(PcdGet64(FdtFileAddress)));
+    NewFdtBlobSize = Size + ADD_FILE_LENGTH;
+
+    Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(Size), &NewFdtBlobBase);
+    if (EFI_ERROR (Status))
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+    (VOID) CopyMem((VOID*)NewFdtBlobBase, Fdt, Size);
+
+    Status = EFIFdtUpdate(NewFdtBlobBase);
+    if (EFI_ERROR (Status))
+    {
+        DEBUG((EFI_D_ERROR, "%a(%d):EFIFdtUpdate Fail!\n", __FUNCTION__,__LINE__));
+        goto EXIT;
+    }
+
+
+    Status = InstallFdtIntoConfigurationTable ((VOID*)(UINTN)NewFdtBlobBase, NewFdtBlobSize);
+    DEBUG ((EFI_D_ERROR, "NewFdtBlobBase: 0x%lx  NewFdtBlobSize:0x%lx\n",NewFdtBlobBase,NewFdtBlobSize));
+    if (EFI_ERROR (Status))
+    {
+        DEBUG ((EFI_D_ERROR, "installfdtconfiguration table fail():\n"));
+        goto EXIT;
+    }
+
+
+    for (Index = 0; Index < gST->NumberOfTableEntries; Index ++)
+    {
+        if (CompareGuid (&gFdtTableGuid, &(gST->ConfigurationTable[Index].VendorGuid)))
+        {
+            FDTConfigTable = (UINTN)gST->ConfigurationTable[Index].VendorTable;
+            DEBUG ((EFI_D_ERROR, "FDTConfigTable Address: 0x%lx\n",FDTConfigTable));
+            break;
+        }
+    }
+
+    return Status;
+
+    EXIT:
+
+         gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize));
+
+    return Status;
+
+}
diff --git a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
new file mode 100644
index 0000000..ccdcae7
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
@@ -0,0 +1,62 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = UpdateFdtDxe
+  FILE_GUID                      = E29977F9-20A4-4551-B0EC-BCE246592E76
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = UpdateFdt
+
+[Sources.common]
+  UpdateFdtDxe.c
+
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  MemoryAllocationLib
+  UefiDriverEntryPoint
+  DebugLib
+  BaseLib
+  FdtLib
+  PcdLib
+  FdtUpdateLib
+  DxeServicesTableLib
+
+[Guids]
+ gFdtTableGuid
+[Protocols]
+
+ gHisiBoardNicProtocolGuid
+
+[Pcd]
+
+ gHisiTokenSpaceGuid.FdtFileAddress
+ gHisiTokenSpaceGuid.PcdReservedNvramSize
+ gHisiTokenSpaceGuid.PcdReservedNvramBase
+
+
+[Depex]
+  gEfiGenericMemTestProtocolGuid
diff --git a/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c b/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c
new file mode 100644
index 0000000..40e9137
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.c
@@ -0,0 +1,108 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <Guid/VersionInfoHobGuid.h>
+
+struct MonthDescription {
+  CONST CHAR8* MonthStr;
+  UINT32    MonthInt;
+} gMonthDescription[] = {
+  { "Jan", 1 },
+  { "Feb", 2 },
+  { "Mar", 3 },
+  { "Apr", 4 },
+  { "May", 5 },
+  { "Jun", 6 },
+  { "Jul", 7 },
+  { "Aug", 8 },
+  { "Sep", 9 },
+  { "Oct", 10 },
+  { "Nov", 11 },
+  { "Dec", 12 },
+  { "???", 1 },  // Use 1 as default month
+};
+
+VOID GetReleaseTime (EFI_TIME *Time)
+{
+  CONST CHAR8      *ReleaseDate = __DATE__;
+  CONST CHAR8      *ReleaseTime = __TIME__;
+  UINTN            i;
+
+  for(i=0;i<12;i++)
+  {
+    if(0 == AsciiStrnCmp(ReleaseDate, gMonthDescription[i].MonthStr, 3))
+    {
+      break;
+    }
+  }
+  Time->Month = gMonthDescription[i].MonthInt;
+  Time->Day = AsciiStrDecimalToUintn(ReleaseDate+4);
+  Time->Year = AsciiStrDecimalToUintn(ReleaseDate+7);
+  Time->Hour = AsciiStrDecimalToUintn(ReleaseTime);
+  Time->Minute = AsciiStrDecimalToUintn(ReleaseTime+3);
+  Time->Second = AsciiStrDecimalToUintn(ReleaseTime+6);
+
+  return;
+}
+
+EFI_STATUS
+EFIAPI
+VersionInfoEntry (
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+  CHAR8 Buffer[100];
+  UINTN CharCount;
+  VERSION_INFO *VersionInfo;
+  EFI_TIME Time = {0};
+  CONST CHAR16 *ReleaseString =
+    (CHAR16 *) FixedPcdGetPtr (PcdFirmwareVersionString);
+
+  GetReleaseTime (&Time);
+
+  CharCount = AsciiSPrint (
+    Buffer,
+    sizeof (Buffer),
+    "\n\rBoot firmware (version %s built at %t)\n\r\n\r",
+    ReleaseString,
+    &Time
+    );
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+  VersionInfo = BuildGuidHob (&gVersionInfoHobGuid,
+                      sizeof (VERSION_INFO) -
+                      sizeof (VersionInfo->String) +
+                      StrSize (ReleaseString));
+  if (VersionInfo == NULL) {
+    DEBUG ((EFI_D_ERROR, "[%a]:[%d] Build HOB failed!\n", __FILE__, __LINE__));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  CopyMem (&VersionInfo->BuildTime, &Time, sizeof (EFI_TIME));
+  CopyMem (VersionInfo->String, ReleaseString, StrSize (ReleaseString));
+
+  return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf b/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
new file mode 100644
index 0000000..bad1ae9
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
@@ -0,0 +1,53 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = VersionInfoPeim
+  FILE_GUID                      = F414EE11-EEE3-4edc-8C12-0E80E446A849
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = VersionInfoEntry
+
+[Sources.common]
+  VersionInfoPeim.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PeimEntryPoint
+  PcdLib
+  DebugLib
+  HobLib
+  BaseLib
+  BaseMemoryLib
+  PrintLib
+  SerialPortLib
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+
+[Guids]
+  gVersionInfoHobGuid
+
+[Depex]
+  TRUE
+
+[BuildOptions]
+
diff --git a/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
new file mode 100644
index 0000000..0cb1e80
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
@@ -0,0 +1,682 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "VirtualEhciPciIo.h"
+#include <Protocol/PciRootBridgeIo.h>
+
+UINT32 mUsbMemBase;
+UINTN mSegmentNumber  = 0;
+// Use 0xFF for the virtual PCI devices
+UINTN mBusNumber      = 0xFF;
+UINTN mDeviceNumber   = 0;
+UINTN mFunctionNumber = 0;
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESS              HostAddress;
+  EFI_PHYSICAL_ADDRESS              DeviceAddress;
+  UINTN                             NumberOfBytes;
+  EFI_PCI_IO_PROTOCOL_OPERATION     Operation;
+  BOOLEAN                           DoubleBuffer;
+} MEM_MAP_INFO_INSTANCE;
+
+
+EFI_CPU_ARCH_PROTOCOL      *gCpu;
+
+
+EHCI_PCI_CONFIG mEhciPciConfig = {
+  {
+    0x00,//UINT16  VendorId;
+    0x00,//UINT16  DeviceId;
+    0x00,//UINT16  Command;
+    0x0010,//UINT16  Status;
+    0x00,//UINT8   RevisionID;
+    {
+      PCI_IF_EHCI,//UINT8   ClassCode[3];
+      PCI_CLASS_SERIAL_USB,
+      PCI_CLASS_SERIAL
+    },
+    0x00,//UINT8   CacheLineSize;
+    0x00,//UINT8   LatencyTimer;
+    0x00,//UINT8   HeaderType;
+    0x00//UINT8   BIST;
+  },
+  {
+    {
+      0x00,//UINT32  Bar[6];
+      0x00,
+      0x00,
+      0x00,
+      0x00,
+      0x00
+    },
+    0x00,//UINT32  CISPtr;
+    0x00,//UINT16  SubsystemVendorID;
+    0x00,//UINT16  SubsystemID;
+    0x00,//UINT32  ExpansionRomBar;
+    0x40,//UINT8   CapabilityPtr;
+    {
+      0x00,//UINT8   Reserved1[3];
+      0x00,
+      0x00
+    },
+    0x00,//UINT32  Reserved2;
+    0x00,//UINT8   InterruptLine;
+    0x00,//UINT8   InterruptPin;
+    0x00,//UINT8   MinGnt;
+    0x00//UINT8   MaxLat;
+  },
+    0x0A,//  UINT8 CapabilityID offset 0x40
+    0x00,// UINT8 NextItemPtr
+    0x2000 //UINT16 DebugPort
+};
+
+
+
+EFI_STATUS
+EhciPciIoPollMem (
+  IN EFI_PCI_IO_PROTOCOL           *This,
+  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,
+  IN  UINT8                        BarIndex,
+  IN  UINT64                       Offset,
+  IN  UINT64                       Mask,
+  IN  UINT64                       Value,
+  IN  UINT64                       Delay,
+  OUT UINT64                       *Result
+  )
+{
+  ASSERT (FALSE);
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoPollIo (
+  IN EFI_PCI_IO_PROTOCOL           *This,
+  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,
+  IN  UINT8                        BarIndex,
+  IN  UINT64                       Offset,
+  IN  UINT64                       Mask,
+  IN  UINT64                       Value,
+  IN  UINT64                       Delay,
+  OUT UINT64                       *Result
+  )
+{
+  ASSERT (FALSE);
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoMemRead (
+  IN EFI_PCI_IO_PROTOCOL              *This,
+  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
+  IN     UINT8                        BarIndex,
+  IN     UINT64                       Offset,
+  IN     UINTN                        Count,
+  IN OUT VOID                         *Buffer
+  )
+{
+  UINT32 i;
+
+  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (BarIndex != 0) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Width     = Width & 0x03;
+
+  //
+  // Loop for each iteration and move the data
+  //
+  switch (Width) {
+  case EfiPciWidthUint8:
+    for (i = 0; i < Count; i++){
+      *((UINT8 *)Buffer + i)= MmioRead8(mUsbMemBase + Offset + i);
+    }
+    break;
+  case EfiPciWidthUint16:
+    for (i = 0; i < Count; i++){
+      *((UINT16 *)Buffer + i)= MmioRead16(mUsbMemBase + Offset + i * 2);
+    }
+    break;
+  case EfiPciWidthUint32:
+    for (i = 0; i < Count; i++){
+      *((UINT32 *)Buffer + i)= MmioRead32(mUsbMemBase + Offset + i * 4);
+    }
+    break;
+  case EfiPciWidthUint64:
+    for (i = 0; i < Count; i++){
+      *((UINT64 *)Buffer + i)= MmioRead64(mUsbMemBase + Offset + i * 8);
+    }
+    break;
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoMemWrite (
+  IN EFI_PCI_IO_PROTOCOL              *This,
+  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
+  IN     UINT8                        BarIndex,
+  IN     UINT64                       Offset,
+  IN     UINTN                        Count,
+  IN OUT VOID                         *Buffer
+  )
+{
+  UINT32 i;
+
+  if ((UINT32)Width >= EfiPciIoWidthMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Width     = Width & 0x03;
+
+  //
+  // Loop for each iteration and move the data
+  //
+  switch (Width) {
+  case EfiPciWidthUint8:
+    for (i = 0; i < Count; i++){
+      MmioWrite8(mUsbMemBase + Offset + i, *((UINT8 *)Buffer + i));
+    }
+    break;
+  case EfiPciWidthUint16:
+    for (i = 0; i < Count; i++){
+      MmioWrite16(mUsbMemBase + Offset + i * 2, *((UINT16 *)Buffer + i));
+    }
+    break;
+  case EfiPciWidthUint32:
+    for (i = 0; i < Count; i++){
+      MmioWrite32(mUsbMemBase + Offset + i * 4, *((UINT32 *)Buffer + i));
+    }
+    break;
+  case EfiPciWidthUint64:
+    for (i = 0; i < Count; i++){
+      MmioWrite64(mUsbMemBase + Offset + i * 8, *((UINT64 *)Buffer + i));
+    }
+    break;
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+
+}
+
+EFI_STATUS
+EhciPciIoIoRead (
+  IN EFI_PCI_IO_PROTOCOL              *This,
+  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
+  IN     UINT8                        BarIndex,
+  IN     UINT64                       Offset,
+  IN     UINTN                        Count,
+  IN OUT VOID                         *Buffer
+  )
+{
+  ASSERT (FALSE);
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoIoWrite (
+  IN EFI_PCI_IO_PROTOCOL              *This,
+  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
+  IN     UINT8                        BarIndex,
+  IN     UINT64                       Offset,
+  IN     UINTN                        Count,
+  IN OUT VOID                         *Buffer
+  )
+{
+  ASSERT (FALSE);
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoPciRead (
+  IN     EFI_PCI_IO_PROTOCOL       *This,
+  IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
+  IN     UINT32                     Offset,
+  IN     UINTN                      Count,
+  IN OUT VOID                      *Buffer
+  )
+{
+  UINT32 i;
+  UINT8 *DataPtr;
+
+  Width     = Width & 0x03;
+
+  if (Offset < sizeof (EHCI_PCI_CONFIG) / sizeof (UINT8)){
+
+    DataPtr = (UINT8 *)(&mEhciPciConfig) + Offset;
+
+    switch (Width) {
+    case EfiPciWidthUint8:
+      for (i = 0; i < Count; i++){
+        *((UINT8 *)Buffer + i)= *(DataPtr + i);
+      }
+      break;
+    case EfiPciWidthUint16:
+      for (i = 0; i < Count; i++){
+        *((UINT16 *)Buffer + i)= *((UINT16 *)DataPtr + i);
+      }
+      break;
+    case EfiPciWidthUint32:
+      for (i = 0; i < Count; i++){
+        *(UINT32 *)(Buffer + i)= *((UINT32 *)DataPtr + i);
+      }
+      break;
+    case EfiPciWidthUint64:
+      for (i = 0; i < Count; i++){
+        *(UINT64 *)(Buffer + i)= *((UINT64 *)DataPtr + i);
+      }
+      break;
+    default:
+      return EFI_INVALID_PARAMETER;
+    }
+
+  } else {
+    switch (Width) {
+    case EfiPciWidthUint8:
+        *(UINT8 *)Buffer = 0xFF;
+      break;
+    case EfiPciWidthUint16:
+        *(UINT16 *)Buffer = 0xFFFF;
+      break;
+    case EfiPciWidthUint32:
+        *(UINT32 *)Buffer = 0xFFFFFFFF;
+      break;
+    case EfiPciWidthUint64:
+        *(UINT64 *)Buffer = 0xFFFFFFFFFFFFFFFF;
+      break;
+    default:
+      return EFI_INVALID_PARAMETER;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoPciWrite (
+  IN EFI_PCI_IO_PROTOCOL              *This,
+  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
+  IN     UINT32                       Offset,
+  IN     UINTN                        Count,
+  IN OUT VOID                         *Buffer
+  )
+{
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoCopyMem (
+  IN EFI_PCI_IO_PROTOCOL              *This,
+  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
+  IN     UINT8                        DestBarIndex,
+  IN     UINT64                       DestOffset,
+  IN     UINT8                        SrcBarIndex,
+  IN     UINT64                       SrcOffset,
+  IN     UINTN                        Count
+  )
+{
+  ASSERT (FALSE);
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoMap (
+  IN EFI_PCI_IO_PROTOCOL                *This,
+  IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,
+  IN     VOID                           *HostAddress,
+  IN OUT UINTN                          *NumberOfBytes,
+  OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,
+  OUT    VOID                           **Mapping
+  )
+{
+  EFI_STATUS                      Status;
+  MEM_MAP_INFO_INSTANCE           *Map;
+  VOID                            *Buffer;
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
+
+  if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((UINT32)Operation >= EfiPciIoOperationMaximum) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  *DeviceAddress = ConvertToPhysicalAddress (HostAddress);
+
+  // Remember range so we can flush on the other side
+  Map = AllocatePool (sizeof (MEM_MAP_INFO_INSTANCE));
+  if (Map == NULL) {
+    return  EFI_OUT_OF_RESOURCES;
+  }
+
+  *Mapping = Map;
+
+  if ((((UINTN)HostAddress & (EFI_PAGE_SIZE - 1)) != 0) ||
+      ((*NumberOfBytes % EFI_PAGE_SIZE) != 0)) {
+
+    // Get the cacheability of the region
+    Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor);
+    if (EFI_ERROR(Status)) {
+      return Status;
+    }
+
+    // If the mapped buffer is not an uncached buffer
+    if ( (GcdDescriptor.Attributes != EFI_MEMORY_WC) &&
+         (GcdDescriptor.Attributes != EFI_MEMORY_UC) )
+    {
+      //
+      // If the buffer does not fill entire cache lines we must double buffer into
+      // uncached memory. Device (PCI) address becomes uncached page.
+      //
+      Map->DoubleBuffer  = TRUE;
+      Buffer = UncachedAllocatePages(EFI_SIZE_TO_PAGES (*NumberOfBytes));
+
+      if (Buffer == NULL) {
+        return EFI_OUT_OF_RESOURCES;
+      }
+
+    CopyMem (Buffer,  HostAddress, *NumberOfBytes);
+      *DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+    } else {
+      Map->DoubleBuffer  = FALSE;
+    }
+  } else {
+    Map->DoubleBuffer  = FALSE;
+
+    // Flush the Data Cache (should not have any effect if the memory region is uncached)
+    gCpu->FlushDataCache (gCpu, *DeviceAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
+
+    Status = gDS->SetMemorySpaceAttributes (*DeviceAddress & ~(BASE_4KB - 1), ALIGN_VALUE (*NumberOfBytes, BASE_4KB), EFI_MEMORY_WC);
+    if (EFI_ERROR (Status)) {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] SetMemorySpaceAttributes Fail. %r\n", __FUNCTION__, __LINE__, Status));
+    }
+  }
+
+  Map->HostAddress   = (UINTN)HostAddress;
+  Map->DeviceAddress = *DeviceAddress;
+  Map->NumberOfBytes = *NumberOfBytes;
+  Map->Operation     = Operation;
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoUnmap (
+  IN EFI_PCI_IO_PROTOCOL           *This,
+  IN  VOID                         *Mapping
+  )
+{
+  MEM_MAP_INFO_INSTANCE *Map;
+
+  if (Mapping == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Map = (MEM_MAP_INFO_INSTANCE *)Mapping;
+
+  if (Map->DoubleBuffer) {
+    if ((Map->Operation == EfiPciIoOperationBusMasterWrite) || (Map->Operation == EfiPciIoOperationBusMasterCommonBuffer)) {
+      CopyMem ((VOID *)(UINTN)Map->HostAddress, (VOID *)(UINTN)Map->DeviceAddress, Map->NumberOfBytes);
+    }
+
+    if((VOID *)(UINTN)Map->DeviceAddress != NULL) {
+      UncachedFreePages ((VOID *)(UINTN)Map->DeviceAddress, EFI_SIZE_TO_PAGES (Map->NumberOfBytes));
+    }
+
+
+  } else {
+    if (Map->Operation == EfiPciIoOperationBusMasterWrite) {
+      //
+      // Make sure we read buffer from uncached memory and not the cache
+      //
+      gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
+    }
+  }
+
+  FreePool (Map);
+
+  return EFI_SUCCESS;
+}
+
+
+
+EFI_STATUS
+EhciPciIoAllocateBuffer (
+  IN EFI_PCI_IO_PROTOCOL  *This,
+  IN  EFI_ALLOCATE_TYPE   Type,
+  IN  EFI_MEMORY_TYPE     MemoryType,
+  IN  UINTN               Pages,
+  OUT VOID                **HostAddress,
+  IN  UINT64              Attributes
+  )
+{
+  UINT32 HcCapParams;
+
+  if (Attributes &
+      (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE |
+         EFI_PCI_ATTRIBUTE_MEMORY_CACHED         ))) {
+    return EFI_UNSUPPORTED;
+  }
+
+  if (HostAddress == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (MemoryType == EfiBootServicesData) {
+    HcCapParams  = MmioRead32(mUsbMemBase + EHC_HCCPARAMS_OFFSET);
+    if ((BOOLEAN)(((HcCapParams) & (HCCP_64BIT)) == (HCCP_64BIT))){
+      *HostAddress = UncachedAllocatePages(Pages);
+    } else {
+      // TODO: We need support allocating UC memory below 4GB strictly
+      *HostAddress = UncachedAllocatePages(Pages);
+    }
+
+  }else{
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EhciPciIoFreeBuffer (
+  IN EFI_PCI_IO_PROTOCOL           *This,
+  IN  UINTN                        Pages,
+  IN  VOID                         *HostAddress
+  )
+{
+  UncachedFreePages (HostAddress, Pages);
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoFlush (
+  IN EFI_PCI_IO_PROTOCOL  *This
+  )
+{
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoGetLocation (
+  IN   EFI_PCI_IO_PROTOCOL  *This,
+  OUT  UINTN                *SegmentNumber,
+  OUT  UINTN                *BusNumber,
+  OUT  UINTN                *DeviceNumber,
+  OUT  UINTN                *FunctionNumber
+  )
+{
+
+  *SegmentNumber  = mSegmentNumber;
+  *BusNumber      = mBusNumber;
+  *DeviceNumber   = mDeviceNumber;
+  *FunctionNumber = mFunctionNumber;
+
+  return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EhciPciIoAttributes (
+  IN EFI_PCI_IO_PROTOCOL                       *This,
+  IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,
+  IN  UINT64                                   Attributes,
+  OUT UINT64                                   *Result OPTIONAL
+  )
+{
+  if (Result != NULL) {
+     *Result = 0;
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EhciPciIoGetBarAttributes (
+  IN EFI_PCI_IO_PROTOCOL             *This,
+  IN  UINT8                          BarIndex,
+  OUT UINT64                         *Supports, OPTIONAL
+  OUT VOID                           **Resources OPTIONAL
+  )
+{
+  ASSERT (FALSE);
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EhciPciIoSetBarAttributes (
+  IN EFI_PCI_IO_PROTOCOL              *This,
+  IN     UINT64                       Attributes,
+  IN     UINT8                        BarIndex,
+  IN OUT UINT64                       *Offset,
+  IN OUT UINT64                       *Length
+  )
+{
+  ASSERT (FALSE);
+  return EFI_UNSUPPORTED;
+}
+
+//
+// Pci Io Protocol Interface
+//
+EFI_PCI_IO_PROTOCOL  mEhciPciIoInterface = {
+  EhciPciIoPollMem,
+  EhciPciIoPollIo,
+  {
+    EhciPciIoMemRead,
+    EhciPciIoMemWrite
+  },
+  {
+    EhciPciIoIoRead,
+    EhciPciIoIoWrite
+  },
+  {
+    EhciPciIoPciRead,
+    EhciPciIoPciWrite
+  },
+  EhciPciIoCopyMem,
+  EhciPciIoMap,
+  EhciPciIoUnmap,
+  EhciPciIoAllocateBuffer,
+  EhciPciIoFreeBuffer,
+  EhciPciIoFlush,
+  EhciPciIoGetLocation,
+  EhciPciIoAttributes,
+  EhciPciIoGetBarAttributes,
+  EhciPciIoSetBarAttributes,
+  0,
+  NULL
+};
+
+
+EFI_STATUS
+EFIAPI
+EhciVirtualPciIoInitialize (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS          Status;
+  EFI_HANDLE                    Handle;
+  EFI_DEV_PATH              EndNode;
+  EFI_DEV_PATH              Node;
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath = NULL;
+
+  mUsbMemBase            = PlatformGetEhciBase ();
+
+    DEBUG ((EFI_D_ERROR, "mUsbMemBase: 0x%x\n", mUsbMemBase));
+
+  // Get the Cpu protocol for later use
+  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
+
+  //
+  // Install the pciio protocol, device path protocol
+  //
+  Handle = NULL;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gEfiPciIoProtocolGuid,
+                  &mEhciPciIoInterface,
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  (void)ZeroMem (&Node, sizeof (Node));
+  Node.DevPath.Type = HARDWARE_DEVICE_PATH;
+  Node.DevPath.SubType = HW_PCI_DP;
+  (void)SetDevicePathNodeLength (&Node.DevPath, sizeof (PCI_DEVICE_PATH));
+  // Make USB controller device path different from built-in SATA controller
+  Node.Pci.Function = 1;
+  Node.Pci.Device = 0;
+
+  SetDevicePathEndNode (&EndNode.DevPath);
+
+  DevicePath = AppendDevicePathNode (&EndNode.DevPath, &Node.DevPath);
+
+  Status = gBS->InstallProtocolInterface (
+                  &Handle,
+                  &gEfiDevicePathProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  DevicePath
+                  );
+  if(EFI_ERROR(Status))
+  {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] InstallProtocolInterface fail. %r\n", __FUNCTION__, __LINE__, Status));
+  }
+
+
+  return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.h b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.h
new file mode 100644
index 0000000..ae7a934
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.h
@@ -0,0 +1,82 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _EHCI_PCIIO_H_
+#define _EHCI_PCIIO_H_
+
+#include <Uefi.h>
+#include <PiDxe.h>
+
+#include <Protocol/Usb2HostController.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/Cpu.h>
+
+#include <Guid/EventGroup.h>
+
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/ArmLib.h>
+#include <Library/UncachedMemoryAllocationLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CacheMaintenanceLib.h>
+
+#include <Library/ReportStatusCodeLib.h>
+
+#include <IndustryStandard/Pci.h>
+#include <Library/PlatformSysCtrlLib.h>
+
+#define PCI_CLASS_SERIAL              0x0C
+#define PCI_CLASS_SERIAL_FIREWIRE     0x00
+#define PCI_CLASS_SERIAL_ACCESS_BUS   0x01
+#define PCI_CLASS_SERIAL_SSA          0x02
+#define PCI_CLASS_SERIAL_USB          0x03
+#define PCI_IF_EHCI                   0x20
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
+#define PCI_CLASS_SERIAL_SMB          0x05
+
+//
+// Capability register offset
+//
+#define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset
+#define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h
+#define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset
+
+//
+// Capability register bit definition
+//
+#define HCSP_NPORTS             0x0F // Number of root hub port
+#define HCSP_PPC                0x10 // Port Power Control
+#define HCCP_64BIT              0x01 // 64-bit addressing capability
+
+
+typedef struct {
+  PCI_DEVICE_INDEPENDENT_REGION Hdr;
+  PCI_DEVICE_HEADER_TYPE_REGION Device;
+  UINT8 CapabilityID;
+  UINT8 NextItemPtr;
+  UINT16 DebugPort;
+} EHCI_PCI_CONFIG;
+
+
+#endif    // _EHCI_PCIIO_H_
diff --git a/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
new file mode 100644
index 0000000..01c145a
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
@@ -0,0 +1,60 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = VirtualEhciPciIo
+  FILE_GUID                      = CCC39A9C-33EC-4e5a-924B-2C5CD4CEF6A4
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = EhciVirtualPciIoInitialize
+
+
+[Sources]
+  VirtualEhciPciIo.h
+  VirtualEhciPciIo.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[FeaturePcd]
+
+
+[LibraryClasses]
+  MemoryAllocationLib
+  BaseLib
+  UefiLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  BaseMemoryLib
+  DebugLib
+  PcdLib
+  IoLib
+  ReportStatusCodeLib
+  UncachedMemoryAllocationLib
+  ArmLib
+  DxeServicesTableLib
+  CacheMaintenanceLib
+  PlatformSysCtrlLib
+
+[Guids]
+
+[Protocols]
+  gEfiPciIoProtocolGuid                         ## TO_START
diff --git a/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c b/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c
new file mode 100644
index 0000000..2310ee4
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c
@@ -0,0 +1,64 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerdesLib.h>
+
+VOID
+EFIAPI
+ExitBootServicesEventSmmu (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+  SmmuConfigForOS ();
+  DEBUG((EFI_D_INFO,"SMMU ExitBootServicesEvent\n"));
+}
+
+
+EFI_STATUS
+EFIAPI
+IoInitDxeEntry (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable)
+{
+  EFI_STATUS Status;
+  EFI_EVENT  Event = NULL;
+
+  (VOID) EfiSerdesInitWrap ();
+
+  SmmuConfigForBios ();
+
+  Status = gBS->CreateEvent (
+      EVT_SIGNAL_EXIT_BOOT_SERVICES,
+      TPL_CALLBACK,
+      ExitBootServicesEventSmmu,
+      NULL,
+      &Event
+      );
+
+  if (EFI_ERROR(Status))
+  {
+    DEBUG ((EFI_D_ERROR, "[%a:%d] - CreateEvent failed: %r\n", __FUNCTION__,
+        __LINE__, Status));
+  }
+
+  return Status;
+}
+
diff --git a/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
new file mode 100644
index 0000000..4b9dced
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
@@ -0,0 +1,62 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IoInitDxe
+  FILE_GUID                      = e99c606a-5626-11e5-b09e-bb93f4e4c400
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = IoInitDxeEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources.common]
+  IoInitDxe.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+  BaseLib
+  PcdLib
+  CacheMaintenanceLib
+  SerdesLib
+  PlatformSysCtrlLib
+
+[Guids]
+
+[Protocols]
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+[Depex]
+  TRUE
+
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c
new file mode 100644
index 0000000..5fc0ead
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c
@@ -0,0 +1,165 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInit.h"
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PlatformPciLib.h>
+
+
+extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
+extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
+extern EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
+
+PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_ROOTBRIDGE] =
+{
+    //Port 0
+    {
+        0x0,                        //Portindex
+
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        }, //PortInfo
+
+    },
+
+    //Port 1
+    {
+        0x1,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+
+    //Port 2
+    {
+        0x2,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+
+    //Port 3
+    {
+        0x3,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+    //Port 4
+    {
+        0x4,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+    //Port 5
+    {
+        0x5,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+    //Port 6
+    {
+        0x6,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+    //Port 7
+    {
+        0x7,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+};
+
+EFI_STATUS
+PcieInitEntry (
+  IN EFI_HANDLE                 ImageHandle,
+  IN EFI_SYSTEM_TABLE           *SystemTable
+  )
+
+{
+    UINT32             Port;
+    EFI_STATUS         Status = EFI_SUCCESS;
+    UINT32             HostBridgeNum = 0;
+    UINT32             soctype = 0;
+    UINT32       PcieRootBridgeMask;
+
+
+    if (!OemIsMpBoot())
+    {
+        PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
+    }
+    else
+    {
+        PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
+    }
+
+    soctype = PcdGet32(Pcdsoctype);
+    for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) {
+        for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) {
+            /*
+               Host Bridge may contain lots of root bridges.
+               Each Host bridge have PCIE_MAX_ROOTBRIDGE root bridges
+               PcieRootBridgeMask have PCIE_MAX_ROOTBRIDGE*HostBridgeNum bits,
+               and each bit stands for this PCIe Port is enable or not
+            */
+            if (!(((( PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * HostBridgeNum))) >> Port) & 0x1)) {
+                continue;
+            }
+
+            Status = PciePortInit(soctype, HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
+            if(EFI_ERROR(Status))
+            {
+                DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
+            }
+
+        }
+    }
+
+
+    return EFI_SUCCESS;
+
+}
+
+
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h
new file mode 100644
index 0000000..466eb81
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.h
@@ -0,0 +1,92 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_H__
+#define __PCIE_INIT_H__
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+
+extern EFI_GUID gEfiPcieRootBridgeProtocolGuid;
+
+#define PCIE_LOG_ID                             1
+
+#define PCIE_CONFIG_SPACE_SIZE                  0x1000      //4k
+#define PCIE_MEMORY_SPACE_SIZE                  0x800000        //8M
+#define PCIE_IO_SPACE_SIZE          0x800000    //8M
+#define PCIE_TYPE1_MEM_SIZE          (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE)
+
+#define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000
+#define CONFIG_SPACE_BASE_ADDR_HIGH 0x0
+#define CONFIG_SPACE_ADDR_LIMIT      (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_MEM_BASE_ADDR_LOW   (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE)
+#define PCIE_MEM_BASE_ADDR_HIGH 0x0
+#define PCIE_MEM_ADDR_LIMIT      (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_IO_BASE_ADDR_LOW   (PCIE_MEM_ADDR_LIMIT - 1)
+#define PCIE_IO_BASE_ADDR_HIGH  0x0
+#define PCIE_IO_ADDR_LIMIT      (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1)
+
+#define PCIE_INBOUND_BASE        0xD0000000
+
+
+#define PCIE_ALL_DMA_BASE               (0x100000000)
+#define PCIE0_ALL_DMA_BASE              (PCIE_ALL_DMA_BASE)
+#define PCIE0_ALL_DMA_SIZE              (0x8000000)
+#define PCIE0_ALL_BAR01_BASE             (0x10000000)
+#define PCIE0_ALL_BAR23_BASE             (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE01_BASE         0x2c0000000  //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR)
+#define PCIE0_ALL_TRANSLATE01_SIZE         (PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE23_BASE         (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE)
+#define PCIE0_ALL_TRANSLATE23_SIZE         (PCIE0_ALL_DMA_SIZE)
+
+
+#define PCIE0_REG_BASE        (0xb0070000)
+#define PCIE1_REG_BASE        (0xb0080000)
+#define PCIE2_REG_BASE        (0xb0090000)
+#define PCIE3_REG_BASE        (0xb00a0000)
+
+#define PCIE_BASE_BAR               (0xf0000000)
+#define PCIE_BAR_SIZE                (0x1000000)
+
+
+#define PCIE_AXI_SIZE         (0x1000000)
+#define PCIE0_AXI_BASE        (0xb3000000)
+#define PCIE1_AXI_BASE        (PCIE0_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE2_AXI_BASE        (PCIE1_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE3_AXI_BASE        (PCIE2_AXI_BASE + PCIE_AXI_SIZE)
+
+#define PCIE0_CONFIG_BASE     (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE1_CONFIG_BASE     (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE2_CONFIG_BASE     (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE3_CONFIG_BASE     (PCIE3_AXI_BASE +  PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE)
+
+
+#define PCIE0_TRANSLATE_BASE            (0x30000000)
+#define PCIE1_TRANSLATE_BASE            (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE2_TRANSLATE_BASE            (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE3_TRANSLATE_BASE            (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+
+#define PCIE0_BAR_BASE              (PCIE0_AXI_BASE)
+#define PCIE1_BAR_BASE              (PCIE1_AXI_BASE)
+#define PCIE2_BAR_BASE              (PCIE2_AXI_BASE)
+#define PCIE3_BAR_BASE              (PCIE3_AXI_BASE)
+
+
+#endif
+
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
new file mode 100644
index 0000000..8b10dbc
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
@@ -0,0 +1,63 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PcieInitDxe
+  FILE_GUID                      = 2D53A704-A544-4A82-83DF-FFECF4B4AA97
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = PcieInitEntry
+
+[Sources]
+  PcieInit.c
+  PcieInitLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  UefiLib
+  BaseLib
+  DebugLib
+  ArmLib
+  TimerLib
+  PcdLib
+  IoLib
+  OemMiscLib
+
+[Protocols]
+  #gEfiPcieRootBridgeProtocolGuid
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P
+  gHisiTokenSpaceGuid.Pcdsoctype
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+
+[FeaturePcd]
+  gHisiTokenSpaceGuid.PcdIsItsSupported
+  gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable
+
+[depex]
+  TRUE
+
+
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
new file mode 100644
index 0000000..0b5a659
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -0,0 +1,1027 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Library/TimerLib.h>
+
+#define PCIE_SYS_REG_OFFSET 0x1000
+
+static PCIE_INIT_CFG mPcieIntCfg;
+UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000};
+UINT64 io_sub0_base = 0xa0000000;
+UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000};
+#define PCIE_REG_BASE(HostBridgeNum,port)              (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000))
+UINT32 loop_test_flag[4] = {0,0,0,0};
+UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR;
+#define PcieMaxLanNum       8
+#define PCIE_PORT_NUM_IN_SICL    4  //SICL: Super IO Cluster
+
+
+extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
+extern PCIE_IATU gastr_pcie_iatu_cfg;
+extern PCIE_IATU_VA mPcieIatuTable;
+
+VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value)
+{
+    RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+
+}
+
+UINT32 PcieRegRead(UINT32 Port, UINTN Offset)
+{
+    UINT32 Value = 0;
+
+    RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+    return Value;
+}
+
+VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
+{
+    RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+}
+
+UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
+{
+    UINT32 Value = 0;
+    RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+    return Value;
+}
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode)
+{
+    u_sc_pcie0_clkreq pcie0;
+    u_sc_pcie1_clkreq pcie1;
+    u_sc_pcie2_clkreq pcie2;
+    u_sc_pcie3_clkreq pcie3;
+
+    switch(Port)
+    {
+        case 0:
+            RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+            pcie0.Bits.pcie0_apb_cfg_sel = Mode;
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+            break;
+        case 1:
+            RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+            pcie1.Bits.pcie1_apb_cfg_sel = Mode;
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+            break;
+        case 2:
+            RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+            pcie2.Bits.pcie2_apb_cfg_sel = Mode;
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+            break;
+        case 3:
+            RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+            pcie3.Bits.pcie3_apb_cfg_sel = Mode;
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+            break;
+        default:
+            break;
+    }
+}
+
+VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN On)
+{
+    UINT32 i;
+    UINT32 Lanenum;
+    UINT32 Value;
+    UINT32 Laneid;
+    UINT32 Loopcnt;
+    UINT32 Lockedcnt[PcieMaxLanNum] = {0};
+
+    Lanenum = 8;
+    if (0x1610 == soctype)
+    {
+        if (On) {
+            /*
+            * to valid the RX, firstly, we should check and make
+            * sure the RX lanes have been steadily locked.
+            */
+            for (Loopcnt = 500 * Lanenum; Loopcnt > 0; Loopcnt--) {
+                Laneid = Loopcnt % Lanenum;
+                RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0xf4 + Laneid * 0x4, Value);
+                if (((Value >> 21) & 0x7) >= 4)
+                    Lockedcnt[Laneid]++;
+                else
+                    Lockedcnt[Laneid] = 0;
+                /*
+                * If we get a locked status above 8 times incessantly
+                * on anyone of the lanes, we get a stable lock.
+                */
+                if (Lockedcnt[Laneid] >= 8)
+                    break;
+                if (Laneid == (Lanenum - 1))
+                    MicroSecondDelay(500);
+                }
+            if (Loopcnt == 0)
+                DEBUG((EFI_D_ERROR, "pcs locked timeout!\n"));
+            for (i = 0; i < Lanenum; i++) {
+                RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
+                Value &= (~BIT14);
+                RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
+                }
+            } else {
+            for (i = 0; i < Lanenum; i++) {
+                RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
+                Value |= BIT14;
+                Value &= (~BIT15);
+                RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
+           }
+        }
+    }
+}
+
+EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    PCIE_CTRL_7_U pcie_ctrl7;
+    UINT32 Value = 0;
+
+    if (Port >= PCIE_MAX_ROOTBRIDGE) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if (0x1610 == soctype)
+    {
+        RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+        Value |= BIT11|BIT30|BIT31;
+        RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+        (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
+        return EFI_SUCCESS;
+    }
+    else
+    {
+        PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+        pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+        pcie_ctrl7.Bits.pcie_linkdown_auto_rstn_enable = 0x1;
+        pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1;
+        PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+        PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+        return EFI_SUCCESS;
+    }
+
+}
+
+STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32 Value;
+    UINTN  RegSegmentOffset;
+
+    if (Port >= PCIE_MAX_ROOTBRIDGE) {
+      DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port));
+      return EFI_INVALID_PARAMETER;
+    }
+
+    RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET;
+
+    //Enable SMMU bypass for translation
+    RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
+    //BIT13: controller master read SMMU bypass
+    //BIT12: controller master write SMMU bypass
+    //BIT10: SMMU bypass enable
+    Value |= (BIT13 | BIT12 | BIT10);
+    RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
+
+    //Switch strongly order (SO) to relaxed order (RO) for write transaction
+    RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
+    //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge
+    Value |= (BIT13 | BIT12);
+    //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction
+    Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17);
+    RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
+
+    //Force streamID for controller read operation
+    RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
+    //Force using streamID in PCIE_SYS_CTRL54_REG
+    Value &= ~(BIT30);
+    //Set streamID to 0, bit[0:15] is for request ID and should be kept
+    Value &= ~(0xff << 16);
+    RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
+
+    //Enable read and write snoopy
+    RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
+    Value |= (BIT30 | BIT28);
+    RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    PCIE_CTRL_7_U pcie_ctrl7;
+    UINT32 Value = 0;
+
+    if(Port >= PCIE_MAX_ROOTBRIDGE) {
+        return PCIE_ERR_PARAM_INVALID;
+    }
+
+    if (0x1610 == soctype)
+    {
+        RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+        Value &= ~(BIT11);
+        RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
+        PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
+        return EFI_SUCCESS;
+    }
+    else
+    {
+        PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+        pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+        pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0;
+        PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+        PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+        return EFI_SUCCESS;
+    }
+
+}
+
+
+EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)
+{
+    PCIE_EP_PCIE_CAP12_U pcie_cap12;
+
+    if(Port >= PCIE_MAX_ROOTBRIDGE) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG);
+    pcie_cap12.Bits.targetlinkspeed = Speed;
+    PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+
+    if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+        mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+    {
+        pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG);
+        pcie_cap12.Bits.targetlinkspeed = Speed;
+        PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+    PCIE_EP_PORT_LOGIC4_U pcie_logic4;
+    PCIE_EP_PORT_LOGIC22_U logic22;
+
+    if(Port >= PCIE_MAX_ROOTBRIDGE) {
+        return PCIE_ERR_PARAM_INVALID;
+    }
+
+    pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+    pcie_logic4.Bits.linkmodeenable = Width;
+    pcie_logic4.Bits.crosslinkenable = 0;
+    pcie_logic4.Bits.fastlinkmode = 1;
+    PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+    logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+    logic22.Bits.n_fts = 0xff;
+    if(Width == PCIE_WITDH_X1)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 1;
+    }
+    else if(Width == PCIE_WITDH_X2)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 2;
+    }
+    else
+    {
+        logic22.Bits.pre_determ_num_of_lane = 3;
+    }
+    PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+    if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+        mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+    {
+        pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG);
+        pcie_logic4.Bits.linkmodeenable = Width;
+        pcie_logic4.Bits.crosslinkenable = 0;
+        pcie_logic4.Bits.fastlinkmode = 1;
+        PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+        logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG);
+        logic22.Bits.n_fts = 0xff;
+        if(Width == PCIE_WITDH_X1)
+        {
+            logic22.Bits.pre_determ_num_of_lane = 1;
+        }
+        else if(Width == PCIE_WITDH_X2)
+        {
+            logic22.Bits.pre_determ_num_of_lane = 2;
+        }
+        else
+        {
+            logic22.Bits.pre_determ_num_of_lane = 3;
+        }
+        PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+    PCIE_EP_PORT_LOGIC22_U logic22;
+    PCIE_EEP_PCI_CFG_HDR15_U hdr15;
+    UINT32 Value = 0;
+    if(Port >= PCIE_MAX_ROOTBRIDGE) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+    Value &= ~(0x3f<<16);
+
+    if(Width == PCIE_WITDH_X1)
+    {
+        Value |= (0x1 << 16);
+    }
+    else if(Width == PCIE_WITDH_X2)
+    {
+        Value |= (0x3 << 16);
+    }
+    else if(Width == PCIE_WITDH_X4)
+    {
+        Value |= (0x7 << 16);
+    }
+    else if(Width == PCIE_WITDH_X8)
+    {
+        Value |= (0xf << 16);
+    }
+    else
+    {
+        DEBUG((EFI_D_ERROR,"Width is not valid\n"));
+    }
+
+    PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value);
+
+    logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+    if(Width == PCIE_WITDH_X1)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 1;
+    }
+    else if(Width == PCIE_WITDH_X2)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 2;
+    }
+    else if(Width == PCIE_WITDH_X4)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 4;
+    }
+    else if(Width == PCIE_WITDH_X8)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 8;
+    }
+    else
+    {
+        DEBUG((EFI_D_ERROR,"Width is not valid\n"));
+    }
+
+    logic22.UInt32 |= (0x100<<8);
+    logic22.UInt32 |= (0x1<<17);
+    PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+    /* setup RC BARs */
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004);
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000);
+
+    /* setup interrupt pins */
+    hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG);
+    hdr15.UInt32 &= 0xffff00ff;
+    hdr15.UInt32 |= 0x00000100;
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32);
+
+    /* setup bus numbers */
+    Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG);
+    Value &= 0xff000000;
+    Value |= 0x00010100;
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value);
+
+    /* setup command register */
+    Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG);
+    Value &= 0xffff0000;
+    Value |= 0x1|0x2|0x4|0x100;
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value);
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType)
+{
+    PCIE_CTRL_0_U str_pcie_ctrl_0;
+
+    if(Port >= PCIE_MAX_ROOTBRIDGE) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if (0x1610 == soctype)
+    {
+        RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28);
+    }
+    else
+    {
+        PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+        str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG);
+        if(PcieType == PCIE_END_POINT)
+        {
+            str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE;
+        }
+        else
+        {
+            str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC;
+        }
+        PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32);
+
+        PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+    }
+    return EFI_SUCCESS;
+}
+
+VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT8 i = 0;
+    UINT32 Value = 0;
+    if (0x1610 == soctype)
+    {
+        for (i = 0; i < PcieMaxLanNum; i++) {
+            RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+            Value |= (1 << 20); //bit 20: rxvalid enable
+            RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+        }
+        PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
+        RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
+    }
+    else
+    {
+        if(Port<=2)
+        {
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044);
+
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0);
+        }
+        else
+
+        {
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000);
+
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001);
+
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff);
+        }
+    }
+    return;
+}
+
+VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32  Value;
+
+    if (0x1610 == soctype)
+    {
+       PcieRegWrite(Port, 0x890, 0x1c00);
+    }
+    else
+    PcieRegWrite(Port, 0x890, 0x1400);
+    PcieRegWrite(Port, 0x894, 0xfd7);
+
+    PcieRegWrite(Port, 0x89c, 0x0);
+    PcieRegWrite(Port, 0x898, 0xfc00);
+    PcieRegWrite(Port, 0x89c, 0x1);
+    PcieRegWrite(Port, 0x898, 0xbd00);
+    PcieRegWrite(Port, 0x89c, 0x2);
+    PcieRegWrite(Port, 0x898, 0xccc0);
+    PcieRegWrite(Port, 0x89c, 0x3);
+    PcieRegWrite(Port, 0x898, 0x8dc0);
+    PcieRegWrite(Port, 0x89c, 0x4);
+    PcieRegWrite(Port, 0x898, 0xfc0);
+    PcieRegWrite(Port, 0x89c, 0x5);
+    PcieRegWrite(Port, 0x898, 0xe46);
+    PcieRegWrite(Port, 0x89c, 0x6);
+    PcieRegWrite(Port, 0x898, 0xdc8);
+    PcieRegWrite(Port, 0x89c, 0x7);
+    PcieRegWrite(Port, 0x898, 0xcb46);
+    PcieRegWrite(Port, 0x89c, 0x8);
+    PcieRegWrite(Port, 0x898, 0x8c07);
+    PcieRegWrite(Port, 0x89c, 0x9);
+    PcieRegWrite(Port, 0x898, 0xd0b);
+    PcieRegWrite(Port, 0x8a8, 0x103ff21);
+    if (0x1610 == soctype)
+    {
+        PcieRegWrite(Port, 0x164, 0x44444444);
+        PcieRegWrite(Port, 0x168, 0x44444444);
+        PcieRegWrite(Port, 0x16c, 0x44444444);
+        PcieRegWrite(Port, 0x170, 0x44444444);
+        RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
+        Value &= (~0x3f);
+        Value |= 0x5;
+        RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
+
+    }
+    else
+    {
+        Value = PcieRegRead(Port, 0x80);
+        Value |= 0x80;
+        PcieRegWrite(Port, 0x80, Value);
+
+        PcieRegWrite(Port, 0x184, 0x44444444);
+        PcieRegWrite(Port, 0x188, 0x44444444);
+        PcieRegWrite(Port, 0x18c, 0x44444444);
+        PcieRegWrite(Port, 0x190, 0x44444444);
+    }
+}
+
+
+EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32 PortIndexInSicl;
+    if(Port >= PCIE_MAX_ROOTBRIDGE) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if(PcieIsLinkUp(soctype, HostBridgeNum, Port))
+    {
+        (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
+    }
+
+    if (0x1610 == soctype)
+    {
+        PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+        if (PortIndexInSicl <= 2) {
+            RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
+            MicroSecondDelay(0x1000);
+        }
+        else
+        {
+            RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
+            MicroSecondDelay(0x1000);
+        }
+    }
+    else
+    {
+        if(Port <= 2)
+        {
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+            MicroSecondDelay(0x1000);
+        }
+        else
+        {
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+            MicroSecondDelay(0x1000);
+        }
+    }
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32 PortIndexInSicl;
+    if(Port >= PCIE_MAX_ROOTBRIDGE) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if(PcieIsLinkUp(soctype, HostBridgeNum, Port))
+    {
+        (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
+    }
+
+    if (0x1610 == soctype)
+    {
+        PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+        if (PortIndexInSicl <= 2) {
+            RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
+            MicroSecondDelay(0x1000);
+        }
+        else
+        {
+            RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG, 0x3);
+            MicroSecondDelay(0x1000);
+        }
+    }
+    else
+    {
+        if(Port <= 2)
+        {
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+            MicroSecondDelay(0x1000);
+        }
+        else
+        {
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+            MicroSecondDelay(0x1000);
+        }
+    }
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    u_sc_pcie_hilink_pcs_reset_req reset_req;
+    UINT32 PortIndexInSicl;
+    if (0x1610 == soctype)
+    {
+        PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+        reset_req.UInt32 = 0;
+        reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
+        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
+
+        reset_req.UInt32 = 0;
+        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
+        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+        //0x1000 microseconds delay comes from experiment and
+        //should be fairly enough for this operation.
+        MicroSecondDelay(0x1000);
+    }
+    else
+    {
+        if(Port <= 3)
+        {
+            reset_req.UInt32 = 0;
+            reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+
+            reset_req.UInt32 = 0;
+            reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+            MicroSecondDelay(0x1000);
+        }
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    u_sc_pcie_hilink_pcs_reset_req reset_req;
+    UINT32 PortIndexInSicl;
+    if (0x1610 == soctype)
+    {
+        PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+        reset_req.UInt32 = 0;
+        reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
+        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32);
+        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+        reset_req.UInt32 = 0;
+        reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
+        RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+        //0x1000 microseconds delay comes from experimenti
+        // and should be fairly enough for this operation.
+        MicroSecondDelay(0x1000);
+    }
+    else
+    {
+        if(Port <= 3)
+        {
+            reset_req.UInt32 = 0;
+            reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+            reset_req.UInt32 = 0;
+            reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+            MicroSecondDelay(0x1000);
+        }
+    }
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock)
+{
+    UINT32 reg_clock_disable;
+    UINT32 reg_clock_enable;
+    UINT32 PortIndexInSicl;
+    PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
+    if (PortIndexInSicl == 3) {
+        reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG;
+        reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG;
+    } else {
+        reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(PortIndexInSicl);
+        reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(PortIndexInSicl);
+    }
+
+    if (0x1610 == soctype)
+    {
+        if (Clock)
+            RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_enable, 0x7);
+        else
+            RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_disable, 0x7);
+    }
+    else
+    {
+        if (Clock)
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, 0x3);
+        else
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, 0x3);
+    }
+    return EFI_SUCCESS;
+}
+
+VOID PciePortNumSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Num)
+{
+    if (0x1610 == soctype)
+    {
+        UINT32 Value = 0;
+        RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
+        Value &= ~(0xff);
+        Value |= Num;
+        RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
+    }
+    return;
+}
+
+VOID PcieLaneReversalSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32 Value = 0;
+    if (0x1610 == soctype)
+    {
+        RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
+        Value |= BIT16;
+        RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
+    }
+    return;
+}
+EFI_STATUS PcieMaskLinkUpInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32 Value = 0;
+    if (0x1610 == soctype)
+    {
+        Value = PcieRegRead(Port, 0x120);
+        Value |= 1 << 25;
+        PcieRegWrite(Port,0x120, Value);
+    }
+    else
+    {
+        PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+        Value = PcieRegRead(Port, 0x1d0);
+        Value |= 1 << 12;
+        PcieRegWrite(Port,0x1d0, Value);
+        PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+    }
+    return EFI_SUCCESS;
+}
+
+BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32                     Value = 0;
+    U_SC_PCIE0_SYS_STATE4      PcieStat;
+    if (0x1610 == soctype)
+    {
+        RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32);
+        Value = PcieStat.UInt32;
+        if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+            return TRUE;
+        return FALSE;
+    }
+    else
+    {
+        RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+        Value = PcieStat.UInt32;
+        if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+            return TRUE;
+        return FALSE;
+    }
+}
+
+BOOLEAN PcieClockIsLock(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32 Value = 0;
+    if (0x1610 == soctype)
+    {
+        RegRead( PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x504, Value);
+        return ((Value & 0x3) == 0x3);
+    }
+    else return TRUE;
+
+}
+
+VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
+{
+    UINT32 Value = 0;
+    if (0x1610 == soctype)
+    {
+        RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value);
+        Value &= ~(0xf);
+        Value |= Spd;
+        RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value);
+        return;
+    }
+    return;
+}
+
+VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 Data)
+{
+     UINT32 Value = 0;
+     {
+         RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
+         Value &= 0x0000ffff;
+         Value |= 0x06040000;
+         RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
+         return;
+     }
+}
+
+VOID SysRegWrite(UINT32 SocType, UINT32 HostBridgeNum, UINT32 Port, UINTN Reg, UINTN Value)
+{
+  if (SocType == 0x1610) {
+    RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value);
+  } else {
+    //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
+    //in the same hostbridge.
+    RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value);
+  }
+}
+
+void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32 Value = 0;
+    UINT64 GicdSetSpiReg = PcdGet64 (PcdGicDistributorBase) + 0x40;
+
+    if (FeaturePcdGet (PcdIsItsSupported)) {
+        //PCIE_SYS_CTRL24_REG is MSI Low address register
+        //PCIE_SYS_CTRL28_REG is MSI High addres register
+        SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]);
+        SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32);
+    } else {
+        SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, GicdSetSpiReg);
+        SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, GicdSetSpiReg >> 32);
+    }
+    RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
+    Value |= (1 << 12);
+    RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
+
+    return;
+}
+
+EFI_STATUS
+EFIAPI
+PciePortInit (
+  IN UINT32                 soctype,
+  IN UINT32                 HostBridgeNum,
+  IN PCIE_DRIVER_CFG        *PcieCfg
+  )
+{
+     UINT16              Count = 0;
+     UINT32             PortIndex = PcieCfg->PortIndex;
+
+     if (PortIndex >= PCIE_MAX_ROOTBRIDGE) {
+        return EFI_INVALID_PARAMETER;
+     }
+
+     if (0x1610 == soctype)
+     {
+         mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex];
+         DEBUG((DEBUG_INFO, "Soc type is 161x\n"));
+     }
+     else
+     {
+         mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
+         DEBUG((EFI_D_INFO, "Soc type is 660\n"));
+     }
+
+     /* assert reset signals */
+     (VOID)AssertPcieCoreReset(soctype, HostBridgeNum, PortIndex);
+     (VOID)AssertPciePcsReset(soctype, HostBridgeNum, PortIndex);
+     (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 0);
+     (VOID)DeassertPcieCoreReset(soctype, HostBridgeNum, PortIndex);
+     /* de-assert phy reset */
+     (VOID)DeassertPciePcsReset(soctype, HostBridgeNum, PortIndex);
+
+     /* de-assert core reset */
+     (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 1);
+
+     while (!PcieClockIsLock(soctype, HostBridgeNum, PortIndex)) {
+         MicroSecondDelay(1000);
+         Count++;
+         if (Count >= 50) {
+            DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d PLL Lock failed\n", HostBridgeNum, PortIndex));
+            return PCIE_ERR_LINK_OVER_TIME;
+         }
+     }
+     /* initialize phy */
+     (VOID)PciePcsInit(soctype, HostBridgeNum, PortIndex);
+
+     (VOID)PcieModeSet(soctype, HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType);
+     (VOID)PcieSpdSet(soctype, HostBridgeNum, PortIndex, 3);
+     (VOID)PciePortNumSet(soctype, HostBridgeNum, PortIndex, 0);
+     /* setup root complex */
+     (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
+
+     /* disable link up interrupt */
+     (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex);
+
+     /* Pcie Equalization*/
+     (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
+
+     /* assert LTSSM enable */
+     (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex);
+     if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) {
+       //PCIe will still work even if performance tuning fails,
+       //and there is warning message inside the function to print
+       //detailed error if there is.
+       (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex);
+     }
+
+     PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex);
+     /*
+     * The default size of BAR0 in Hi1610 host bridge is 0x10000000,
+     * which will bring problem when most resource has been allocated
+     * to BAR0 in host bridge.However, we need not use BAR0 in host bridge
+     * in RC mode. Here we just disable it
+     */
+     PcieRegWrite(PortIndex, 0x10, 0);
+     (VOID)PcieWriteOwnConfig(HostBridgeNum, PortIndex, 0xa, 0x0604);
+     /* check if the link is up or not */
+     while (!PcieIsLinkUp(soctype, HostBridgeNum, PortIndex)) {
+         MicroSecondDelay(1000);
+         Count++;
+         if (Count >= 1000) {
+            DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex));
+            return PCIE_ERR_LINK_OVER_TIME;
+         }
+     }
+     DEBUG((EFI_D_INFO, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex));
+
+     PcieRegWrite(PortIndex, 0x8BC, 0);
+
+     return EFI_SUCCESS;
+}
+
+
+
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable)
+{
+    PCIE_SYS_CTRL20_U dbi_ro_enable;
+
+    if (Port >= PCIE_MAX_ROOTBRIDGE) {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+    dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG);
+    dbi_ro_enable.Bits.ro_sel = Enable;
+    PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32);
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+    return EFI_SUCCESS;
+
+}
+
+VOID PcieDelay(UINT32 dCount)
+{
+    volatile UINT32 *uwCnt = &dCount;
+
+    while(*uwCnt > 0)
+    {
+        *uwCnt = *uwCnt - 1;
+    }
+
+}
+
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
new file mode 100644
index 0000000..9671c57
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
@@ -0,0 +1,243 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_LIB_H__
+#define __PCIE_INIT_LIB_H__
+
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+#include "PcieKernelApi.h"
+
+#define PCIE_AXI_SLAVE_BASE             (0xb3000000)
+#define PCIE_MAX_AXI_SIZE               (0x1000000)
+#define PCIE_AXI_BASE(port)             (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE)
+#define PCIE_SMMU_BASE                  (0xb0040000)
+
+
+#define PCIE_DMA_CHANNEL_NUM            (2)
+#define PCIE_DMA_RESOURCE_MODE_SIZE     (0x40000)
+#define PCIE_DMA_BURST_SIZE             (0x80000000)
+
+#define PCIE_ADDR_BASE_OFFSET                       0x46C00000
+#define PCIE_ADDR_BASE_HOST_ADDR                    (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST)
+#define NP_DDR_BASE_ADDR_HOST                       0x236E00000ULL
+
+
+
+#define PCIE_GIC_MSI_ITS_BASE       (0xb7010040)
+#define PCIE_INT_BASE               (13824)
+#define PCIE_INT_LIMIT              (PCIE_INT_BASE + 64)
+
+#define PCIE_NTB_MEM_SIZE             (0x1000000)
+#define PCIE_NTB_BAR01_SIZE           (0x10000) // 64K
+#define PCIE_NTB_BAR23_SIZE           (0x800000) // 8M
+#define PCIE_NTB_BAR45_SIZE           (0x800000)
+
+#define PCIE_IATU_END               {PCIE_IATU_OUTBOUND,0,0,0}
+#define PCIE_IATU_INBOUND_MASK      (0x80000000)
+#define PCIE_IATU_INDEX_MASK         (0x7f)
+#define PCIE_IATU_TYPE_MASK         (0x1f)
+#define PCIE_IATU_EN                     (0x1 << 0)
+#define PCIE_IATU_SHIFT_MODE             (0x1 << 1)
+#define PCIE_IATU_BAR_MODE               (0x1 << 2)
+#define PCIE_IATU_FUNC_MODE               (0x1 << 3)
+#define PCIE_IATU_AT_MODE                 (0x1 << 4) //AT mach mode
+#define PCIE_IATU_ATTR_MODE               (0x1 << 5)
+#define PCIE_IATU_TD_MODE                 (0x1 << 6) //TD
+#define PCIE_IATU_TC_MODE                 (0x1 << 7) // TC
+#define PCIE_IATU_PREFETCH_MODE             (0x1 << 8)
+#define PCIE_IATU_DMA_BY_PASS_MODE          (0x1 << 9) //DMA bypass untranslate
+
+#define PCIE_BAR_MASK_SIZE          (0x800000)
+#define PCIE_BAR_TYPE_32            (0)
+#define PCIE_BAR_TYPE_64            (2)
+#define PCIE_BAR_PREFETCH_MODE      (1)
+
+#define PCS_SDS_CFG_REG            0x204
+#define SDS_CFG_STRIDE             0x4
+#define RegWrite(addr,data)            MmioWrite32((addr), (data))
+#define RegRead(addr,data)             ((data) = MmioRead32 (addr))
+
+
+typedef struct tagPcieDebugInfo
+{
+    UINT32 pcie_rdma_start_cnt;
+    UINT32 pcie_wdma_start_cnt;
+    UINT64 pcie_wdma_transfer_len;
+    UINT64 pcie_rdma_transfer_len;
+    UINT32 pcie_rdma_fail_cnt;
+    UINT32 pcie_wdma_fail_cnt;
+}pcie_debug_info_s;
+
+
+#define bdf_2_b(bdf)    ((bdf >> 8) & 0xFF)
+#define bdf_2_d(bdf)    ((bdf >> 3) & 0x1F)
+#define bdf_2_f(bdf)    ((bdf >> 0) & 0x7)
+#define b_d_f_2_bdf(b,d,f)    (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0))
+
+
+
+typedef UINT32 (*pcie_dma_func_int)(UINT32  ulErrno, UINT32 ulReserved);
+
+
+typedef struct {
+     UINT32             ViewPort;            //iATU Viewport Register
+     UINT32             RegionCtrl1;         //Region Control 1 Register
+     UINT32             RegionCtrl2;         //Region Control 2 Register
+     UINT32             BaseLow;             //Lower Base Address Register
+     UINT32             BaseHigh;            //Upper Base Address Register
+     UINT32             Limit;               //Limit Address Register
+     UINT32             TargetLow;           //Lower Target Address Register
+     UINT32             TargetHigh;          //Upper Target Address Register
+} PCIE_IATU_VA;
+
+typedef enum {
+    PCIE_IATU_OUTBOUND    = 0x0,
+    PCIE_IATU_INBOUND     = 0x1,
+} PCIE_IATU_DIR;
+
+typedef struct {
+    PCIE_IATU_DIR       IatuType;
+    UINT64              IatuBase;
+    UINT64              IatuSize;
+    UINT64              IatuTarget;
+} PCIE_IATU;
+
+typedef struct {
+    UINT32              IatuType;
+    UINT64              IatuBase;
+    UINT32              IatuLimit;
+    UINT64              IatuTarget;
+    UINT32              Valid;
+} PCIE_IATU_HW;
+
+typedef struct {
+    UINT32              PortIndex;
+    PCIE_PORT_INFO      PortInfo;
+    PCIE_IATU_HW        OutBound[PCIE_MAX_OUTBOUND];
+    PCIE_IATU_HW        InBound[PCIE_MAX_INBOUND];
+} PCIE_DRIVER_CFG;
+
+typedef enum {
+    PCIE_CONFIG_REG     = 0x0,
+    PCIE_SYS_CONTROL    = 0x1,
+} PCIE_RW_MODE;
+
+typedef union {
+    PCIE_DRIVER_CFG     PcieDevice;
+    PCIE_NTB_CFG        NtbDevice;
+} DRIVER_CFG_U;
+
+typedef struct {
+    VOID                *MappedOutbound[PCIE_MAX_OUTBOUND];
+    UINT32              OutboundType[PCIE_MAX_OUTBOUND];
+    UINT32              OutboundEn[PCIE_MAX_OUTBOUND];
+} PCIE_MAPPED_IATU_ADDR;
+
+typedef struct {
+    BOOLEAN             PortIsInitilized[PCIE_MAX_ROOTBRIDGE];
+    DRIVER_CFG_U        Dev[PCIE_MAX_ROOTBRIDGE];
+    VOID                *DmaResource[PCIE_MAX_ROOTBRIDGE];
+    UINT32              DmaChannel[PCIE_MAX_ROOTBRIDGE][PCIE_DMA_CHANNEL_NUM];
+    VOID                *RegResource[PCIE_MAX_ROOTBRIDGE];
+    VOID                *CfgResource[PCIE_MAX_ROOTBRIDGE];
+} PCIE_INIT_CFG;
+
+typedef enum {
+    PCIE_MMIO_IEP_CFG  = 0x1000,
+    PCIE_MMIO_IEP_CTRL = 0x0,
+    PCIE_MMIO_EEP_CFG  = 0x9000,
+    PCIE_MMIO_EEP_CTRL = 0x8000,
+} NTB_MMIO_MODE;
+
+typedef struct tagPcieDmaDes
+{
+    UINT32 uwChanCtrl;
+    UINT32 uwLen;
+    UINT32 uwLocalLow;
+    UINT32 uwLocalHigh;
+    UINT32 uwTagetLow;
+    UINT32 uwTagetHigh;
+}pcie_dma_des_s,*pcie_dma_des_ps;
+
+typedef enum {
+    PCIE_IATU_MEM,
+    PCIE_IATU_CFG = 0x4,
+    PCIE_IATU_IO
+} PCIE_IATU_OUT_TYPE;
+
+typedef enum {
+    PCIE_PAYLOAD_128B = 0,
+    PCIE_PAYLOAD_256B,
+    PCIE_PAYLOAD_512B,
+    PCIE_PAYLOAD_1024B,
+    PCIE_PAYLOAD_2048B,
+    PCIE_PAYLOAD_4096B,
+    PCIE_RESERVED_PAYLOAD
+} PCIE_PAYLOAD_SIZE;
+
+typedef struct tagPcieDfxInfo
+{
+    PCIE_EP_AER_CAP0_U aer_cap0;
+    PCIE_EP_AER_CAP1_U aer_cap1;
+    PCIE_EP_AER_CAP2_U aer_cap2;
+    PCIE_EP_AER_CAP3_U aer_cap3;
+    PCIE_EP_AER_CAP4_U aer_cap4;
+    PCIE_EP_AER_CAP5_U aer_cap5;
+    PCIE_EP_AER_CAP6_U aer_cap6;
+    UINT32 hdr_log0;
+    UINT32 hdr_log1;
+    UINT32 hdr_log2;
+    UINT32 hdr_log3;
+    PCIE_EP_AER_CAP11_U aer_cap11;
+    PCIE_EP_AER_CAP12_U aer_cap12;
+    PCIE_EP_AER_CAP13_U aer_cap13;
+
+    PCIE_EP_PORTLOGIC62_U port_logic62;
+    PCIE_EP_PORTLOGIC64_U port_logic64;
+    PCIE_EP_PORTLOGIC66_U port_logic66;
+    PCIE_EP_PORTLOGIC67_U port_logic67;
+    PCIE_EP_PORTLOGIC69_U port_logic69;
+    PCIE_EP_PORTLOGIC75_U port_logic75;
+    PCIE_EP_PORTLOGIC76_U port_logic76;
+    PCIE_EP_PORTLOGIC77_U port_logic77;
+    PCIE_EP_PORTLOGIC79_U port_logic79;
+    PCIE_EP_PORTLOGIC80_U port_logic80;
+    PCIE_EP_PORTLOGIC81_U port_logic81;
+    PCIE_EP_PORTLOGIC87_U port_logic87;
+
+    PCIE_CTRL_10_U  pcie_ctrl10;
+    UINT32 slve_rerr_addr_low;
+    UINT32 slve_rerr_addr_up;
+    UINT32 slve_werr_addr_low;
+    UINT32 slve_werr_addr_up;
+    UINT32 pcie_state4;
+    UINT32 pcie_state5;
+}PCIE_DFX_INFO_S;
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode);
+
+UINT32 PcieIsLinkDown(UINT32 Port);
+
+BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port);
+
+EFI_STATUS PcieWaitLinkUp(UINT32 Port);
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
+
+#endif
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h
new file mode 100644
index 0000000..db89597
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h
@@ -0,0 +1,344 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_KERNEL_API_H__
+#define __PCIE_KERNEL_API_H__
+
+#define PCIE_MAX_OUTBOUND               (6)
+#define PCIE_MAX_INBOUND               (4)
+#define PCIE3_MAX_OUTBOUND               (16)
+#define PCIE3_MAX_INBOUND                (16)
+
+#define PCIE_LINK_LOOP_CNT          (0x1000)
+#define PCIE_IATU_ADDR_MASK         (0xFFFFF000)
+#define PCIE_1M_ALIGN_SHIRFT        (20)
+#define PCIE_BDF_MASK               (0xF0000FFF)
+#define PCIE_BUS_SHIRFT             (20)
+#define PCIE_DEV_SHIRFT             (15)
+#define PCIE_FUNC_SHIRFT            (12)
+
+#define PCIE_DBI_CS2_ENABLE              (0x1)
+#define PCIE_DBI_CS2_DISABLE             (0x0)
+
+#define PCIE_DMA_CHANLE_READ             (0x1)
+#define PCIE_DMA_CHANLE_WRITE             (0x0)
+
+
+#define PCIE_ERR_IATU_TABLE_NULL            EFIERR (1)
+#define PCIE_ERR_LINK_OVER_TIME             EFIERR (2)
+#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE      EFIERR (3)
+#define PCIE_ERR_ALREADY_INIT               EFIERR (4)
+#define PCIE_ERR_PARAM_INVALID              EFIERR (5)
+#define PCIE_ERR_MEM_OPT_OVER               EFIERR (6)
+#define PCIE_ERR_NOT_INIT                   EFIERR (7)
+#define PCIE_ERR_CFG_OPT_OVER               EFIERR (8)
+#define PCIE_ERR_DMA_READ_CHANLE_BUSY       EFIERR (9)
+#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY      EFIERR (10)
+#define PCIE_ERR_DMAR_NO_RESORCE            EFIERR (11)
+#define PCIE_ERR_DMAW_NO_RESORCE            EFIERR (12)
+#define PCIE_ERR_DMA_OVER_MAX_RESORCE       EFIERR (13)
+#define PCIE_ERR_NO_IATU_WINDOW             EFIERR (14)
+#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME    EFIERR (15)
+#define PCIE_ERR_DMA_MEM_ALLOC_ERROR        EFIERR (16)
+#define PCIE_ERR_DMA_ABORT                  EFIERR (17)
+#define PCIE_ERR_UNSUPPORT_BAR_TYPE         EFIERR (18)
+
+typedef enum {
+    PCIE_ROOT_COMPLEX,
+    PCIE_END_POINT,
+    PCIE_NTB_TO_NTB,
+    PCIE_NTB_TO_RP,
+} PCIE_PORT_TYPE;
+
+typedef enum {
+    PCIE_GEN1_0 = 1,    //PCIE 1.0
+    PCIE_GEN2_0 = 2,    //PCIE 2.0
+    PCIE_GEN3_0 = 4     //PCIE 3.0
+} PCIE_PORT_GEN;
+
+typedef enum {
+    PCIE_WITDH_X1 = 0x1,
+    PCIE_WITDH_X2 = 0x3,
+    PCIE_WITDH_X4 = 0x7,
+    PCIE_WITDH_X8 = 0xf,
+    PCIE_WITDH_INVALID
+} PCIE_PORT_WIDTH;
+
+
+typedef struct {
+    PCIE_PORT_TYPE      PortType;
+    PCIE_PORT_WIDTH     PortWidth;
+    PCIE_PORT_GEN       PortGen;
+    UINT8               PcieLinkUp;
+} PCIE_PORT_INFO;
+
+typedef struct tagPciecfg_params
+{
+    UINT32 preemphasis;
+    UINT32 deemphasis;
+    UINT32 swing;
+    UINT32 balance;
+}pcie_cfg_params_s;
+
+typedef enum {
+    PCIE_CORRECTABLE_ERROR = 0,
+    PCIE_NON_FATAL_ERROR,
+    PCIE_FATAL_ERROR,
+    PCIE_UNSUPPORTED_REQUEST_ERROR,
+    PCIE_ALL_ERROR
+} PCIE_ERROR_TYPE;
+
+typedef union tagPcieDeviceStatus
+{
+       struct
+        {
+            UINT16 correctable_error : 1;
+            UINT16 non_fatal_error : 1;
+            UINT16 fatal_error : 1;
+            UINT16 unsupported_error : 1;
+            UINT16 aux_power : 1;
+            UINT16 transaction_pending : 1;
+            UINT16 reserved_6_15 : 10;
+       }Bits;
+
+    UINT16 Value;
+}pcie_device_status_u;
+
+
+typedef union tagPcieUcAerStatus
+{
+      struct
+        {
+            UINT32    undefined   : 1   ; /* [0] undefined  */
+            UINT32    reserved_1_3   : 3   ; /* reserved */
+            UINT32    data_link_proto_error   : 1   ; /* Data Link Protocol Error Status */
+            UINT32    reserved_5_11   : 7   ; /* reserved */
+            UINT32    poisoned_tlp_status   : 1   ; /* Poisoned TLP Status */
+            UINT32    flow_control_proto_error   : 1   ; /* Flow Control Protocol Error Status */
+            UINT32    completion_time_out   : 1   ; /* Completion Timeout Status */
+            UINT32    compler_abort_status   : 1   ; /* Completer Abort Status */
+            UINT32    unexpect_completion_status   : 1   ; /* Unexpected Completion Status */
+            UINT32    receiver_overflow_status   : 1   ; /*Receiver Overflow Status */
+            UINT32    malformed_tlp_status   : 1   ; /* Malformed TLP Status*/
+            UINT32    ecrc_error_status   : 1   ; /* ECRC Error Status */
+            UINT32    unsupport_request_error_status   : 1   ; /* Unsupported Request Error Status */
+            UINT32    reserved_21   : 1   ; /*  reserved */
+            UINT32    uncorrectable_interal_error   : 1   ; /* Uncorrectable Internal Error Status */
+            UINT32    reserved_23   : 1   ; /* reserved*/
+            UINT32    atomicop_egress_blocked_status   : 1   ; /* AtomicOp Egress Blocked Status */
+            UINT32    tlp_prefix_blocked_error_status   : 1   ; /* TLP Prefix Blocked Error Status */
+            UINT32    reserved_26_31   : 1   ; /* reserved */
+       }Bits;
+
+       UINT32 Value;
+}pcie_uc_aer_status_u;
+
+typedef union tagPcieCoAerStatus
+{
+       struct
+        {
+            UINT32    receiver_error_status   : 1   ; /* Receiver Error Status  */
+            UINT32    reserved_1_5   : 5   ; /* Reserved */
+            UINT32    bad_tlp_status   : 1   ; /* Bad TLP Status */
+            UINT32    bad_dllp_status   : 1   ; /* Bad DLLP Status */
+            UINT32    reply_num_rollover_status   : 1   ; /* REPLAY_NUM Rollover Status*/
+            UINT32    reserved_9_11   : 3   ; /* Reserved */
+            UINT32    reply_timer_timeout   : 1   ; /* Replay Timer Timeout Status */
+            UINT32    advisory_nonfatal_error   : 1   ; /* Advisory Non-Fatal Error Status*/
+            UINT32    corrected_internal_error   : 1   ; /*Corrected Internal Error Status*/
+            UINT32    reserved_15_31   : 1   ; /* Reserved */
+       }Bits;
+       UINT32 Value;
+}pcie_co_aer_status_u;
+
+typedef struct tagPcieAerStatus
+{
+    pcie_uc_aer_status_u uc_aer_status;
+    pcie_co_aer_status_u co_aer_status;
+}pcie_aer_status_s;
+
+
+
+typedef struct tagPcieLoopTestResult
+{
+   UINT32 tx_pkts_cnt;
+   UINT32 rx_pkts_cnt;
+   UINT32 error_pkts_cnt;
+   UINT32 droped_pkts_cnt;
+   UINT32 push_cnt;
+   pcie_device_status_u device_status;
+   pcie_aer_status_s    pcie_aer_status;
+} pcie_loop_test_result_s;
+
+typedef struct tagPcieDmaChannelAttrs {
+    UINT32 dma_chan_en;
+    UINT32 dma_mode;
+    UINT32 channel_status;
+}pcie_dma_channel_attrs_s;
+
+typedef enum tagPcieDmaChannelStatus
+{
+    PCIE_DMA_CS_RESERVED = 0,
+    PCIE_DMA_CS_RUNNING = 1,
+    PCIE_DMA_CS_HALTED = 2,
+    PCIE_DMA_CS_STOPPED = 3
+}pcie_dma_channel_status_e;
+
+typedef enum tagPcieDmaIntType{
+    PCIE_DMA_INT_TYPE_DONE=0,
+    PCIE_DMA_INT_TYPE_ABORT,
+    PCIE_DMA_INT_ALL,
+    PCIE_DMA_INT_NONE
+}pcie_dma_int_type_e;
+
+typedef enum tagPcieMulWinSize
+{
+    WIN_SIZE_4K = 0xc,
+    WIN_SIZE_8K,
+    WIN_SIZE_16K,
+    WIN_SIZE_32K,
+    WIN_SIZE_64K,
+    WIN_SIZE_128K,
+    WIN_SIZE_256K,
+    WIN_SIZE_512K,
+    WIN_SIZE_1M,
+    WIN_SIZE_2M,
+    WIN_SIZE_4M,
+    WIN_SIZE_8M,
+    WIN_SIZE_16M,
+    WIN_SIZE_32M,
+    WIN_SIZE_64M,
+    WIN_SIZE_128M,
+    WIN_SIZE_256M,
+    WIN_SIZE_512M,
+    WIN_SIZE_1G,
+    WIN_SIZE_2G,
+    WIN_SIZE_4G,
+    WIN_SIZE_8G,
+    WIN_SIZE_16G,
+    WIN_SIZE_32G,
+    WIN_SIZE_64G,
+    WIN_SIZE_128G,
+    WIN_SIZE_256G,
+    WIN_SIZE_512G = 0x27,
+}pcie_mul_win_size_e;
+
+typedef struct tagPcieMultiCastCfg
+{
+    UINT64 multicast_base_addr;
+    pcie_mul_win_size_e base_addr_size;
+    UINT64 base_translate_addr;
+}pcie_multicast_cfg_s;
+
+typedef enum tagPcieMode
+{
+    PCIE_EP_DEVICE = 0x0,
+    LEGACY_PCIE_EP_DEVICE = 0x1,
+    RP_OF_PCIE_RC = 0x4,
+    PCIE_INVALID = 0x100
+}pcie_mode_e;
+
+typedef struct{
+    UINT32              PortIndex;
+    PCIE_PORT_INFO      PortInfo;
+    UINT64              iep_bar01; /*iep bar 01*/
+    UINT64              iep_bar23;
+    UINT64              iep_bar45;
+    UINT64              iep_bar01_xlat;
+    UINT64              iep_bar23_xlat;
+    UINT64              iep_bar45_xlat;
+    UINT64              iep_bar_lmt23;
+    UINT64              iep_bar_lmt45; /*bar limit*/
+    UINT64              eep_bar01;
+    UINT64              eep_bar23;
+    UINT64              eep_bar45;
+    UINT64              eep_bar23_xlat;
+    UINT64              eep_bar45_xlat;
+    UINT64              eep_bar_lmt23; /*bar limit*/
+    UINT64              eep_bar_lmt45; /*bar limit*/
+} PCIE_NTB_CFG;
+
+extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info);
+
+extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl);
+
+extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed);
+
+extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+
+extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control);
+
+extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute);
+
+extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status);
+
+extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel);
+
+
+extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status);
+
+extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type);
+
+
+extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num);
+
+extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg);
+
+extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell);
+
+extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result);
+extern int pcie_port_reset(UINT32 Port);
+
+extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \
+pcie_device_status_u *pcie_stat);
+extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
+
+extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status);
+extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
+
+extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length);
+
+extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length);
+
+extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length);
+
+extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length);
+
+#endif
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf
new file mode 100644
index 0000000..b6be3d9
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf
@@ -0,0 +1,56 @@
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Hi1610AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  Dsdt/DsdtHi1610.asl
+  Facs.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  MadtHi1610.aslc
+  D03Mcfg.aslc
+  D03Iort.asl
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl
new file mode 100644
index 0000000..9a045b7
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl
@@ -0,0 +1,368 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength]  FieldName : HexFieldValue
+ */
+[0004]                          Signature : "IORT"    [IO Remapping Table]
+[0004]                       Table Length : 000002e4
+[0001]                           Revision : 00
+[0001]                           Checksum : BC
+[0006]                             Oem ID : "HISI  "
+[0008]                       Oem Table ID : "HIP06   "
+[0004]                       Oem Revision : 00000000
+[0004]                    Asl Compiler ID : "INTL"
+[0004]              Asl Compiler Revision : 20151124
+
+[0004]                         Node Count : 00000008
+[0004]                        Node Offset : 00000034
+[0004]                           Reserved : 00000000
+[0004]                   Optional Padding : 00 00 00 00
+
+/* ITS 0, for dsa */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000000
+
+/* mbi-gen dsa  mbi0 - usb, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0017]                        Device Name : "\_SB_.MBI0"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040080  // device id
+[0004]                   Output Reference : 00000034  // point to its dsa
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen dsa mbi1 - sas1, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI1"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040000
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen dsa mbi2 - sas2, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI2"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040040
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen dsa mbi3 - dsa0, srv named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI3"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040800
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen dsa mbi4 - dsa1, dbg0 named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI4"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040b1c
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen dsa mbi5 - dsa2, dbg1  named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI5"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040b1d
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen dsa mbi6 - dsa sas0  named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI6"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040900
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen mbi7 - RoCE named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI7"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040b1e
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* RC 0 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000000
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00002000
+[0004]                        Output Base : 00000000
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* RC 1 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000001
+
+[0004]                         Input base : 0000e000
+[0004]                           ID Count : 00002000
+[0004]                        Output Base : 0000e000
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* RC 2 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000002
+
+[0004]                         Input base : 00008000
+[0004]                           ID Count : 00002000
+[0004]                        Output Base : 00008000
+[0004]                   Output Reference : 00000034
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc
new file mode 100644
index 0000000..ed47a44
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2016 Hisilicon Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ */
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1610Platform.h"
+
+#define ACPI_5_0_MCFG_VERSION  0x1
+
+#pragma pack(1)
+typedef struct
+{
+   UINT64 ullBaseAddress;
+   UINT16 usSegGroupNum;
+   UINT8  ucStartBusNum;
+   UINT8  ucEndBusNum;
+   UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+   EFI_ACPI_DESCRIPTION_HEADER Header;
+   UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+   EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+   EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+  {
+      {
+        EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+        sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+        ACPI_5_0_MCFG_VERSION,
+        0x00,                                                     // Checksum will be updated at runtime
+        {EFI_ACPI_ARM_OEM_ID},
+        EFI_ACPI_ARM_OEM_TABLE_ID,
+        EFI_ACPI_ARM_OEM_REVISION,
+        EFI_ACPI_ARM_CREATOR_ID,
+        EFI_ACPI_ARM_CREATOR_REVISION
+      },
+      0x0000000000000000,                                 //Reserved
+  },
+  {
+
+    {
+      0xb0000000,                                         //Base Address
+      0x0,                                                //Segment Group Number
+      0x0,                                                //Start Bus Number
+      0x1f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    {
+      0xb0000000,                                         //Base Address
+      0x1,                                                //Segment Group Number
+      0xe0,                                               //Start Bus Number
+      0xff,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    {
+      0xa0000000,                                         //Base Address
+      0x2,                                                //Segment Group Number
+      0x80,                                               //Start Bus Number
+      0x9f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl
new file mode 100644
index 0000000..e995295
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/CPU.asl
@@ -0,0 +1,88 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+    //
+    // A57x16 Processor declaration
+    //
+    Device(CPU0) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 0)
+    }
+    Device(CPU1) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 1)
+    }
+    Device(CPU2) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 2)
+    }
+    Device(CPU3) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 3)
+    }
+    Device(CPU4) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 4)
+    }
+    Device(CPU5) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 5)
+    }
+    Device(CPU6) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 6)
+    }
+    Device(CPU7) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 7)
+    }
+    Device(CPU8) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 8)
+    }
+    Device(CPU9) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 9)
+    }
+    Device(CP10) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 10)
+    }
+    Device(CP11) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 11)
+    }
+    Device(CP12) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 12)
+    }
+    Device(CP13) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 13)
+    }
+    Device(CP14) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 14)
+    }
+    Device(CP15) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 15)
+    }
+}
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl
new file mode 100644
index 0000000..3bcc5fb
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl
@@ -0,0 +1,36 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+  Device(COM0) {
+    Name(_HID, "HISI0031") //it is not 16550 compatible
+    Name(_CID, "8250dw")
+    Name(_UID, Zero)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x80300000, 0x1000)
+      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"clock-frequency", 200000000},
+      }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl
new file mode 100644
index 0000000..765ca19
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl
@@ -0,0 +1,691 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  Device (MDIO)
+  {
+    OperationRegion(CLKR, SystemMemory, 0x60000338, 8)
+    Field(CLKR, DWordAcc, NoLock, Preserve) {
+      CLKE, 1,  // clock enable
+      , 31,
+      CLKD, 1,  // clode disable
+      , 31,
+    }
+    OperationRegion(RSTR, SystemMemory, 0x60000A38, 8)
+    Field(RSTR, DWordAcc, NoLock, Preserve) {
+      RSTE, 1,  // reset
+      , 31,
+      RSTD, 1,  // de-reset
+      , 31,
+    }
+
+    Name(_HID, "HISI0141")
+    Name (_CRS, ResourceTemplate (){
+      Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)
+            })
+
+    Method(_RST, 0, Serialized) {
+      Store (0x1, RSTE)
+      Sleep (10)
+      Store (0x1, CLKD)
+      Sleep (10)
+      Store (0x1, RSTD)
+      Sleep (10)
+      Store (0x1, CLKE)
+      Sleep (10)
+    }
+  }
+
+  Device (DSF0)
+  {
+    OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
+    Field(H3SR, DWordAcc, NoLock, Preserve) {
+          H3ST, 1,
+          , 31,  //RESERVED
+        }
+    OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
+    Field(H4SR, DWordAcc, NoLock, Preserve) {
+          H4ST, 1,
+          , 31,  //RESERVED
+        }
+    // DSAF RESET
+    OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
+    Field(DRER, DWordAcc, NoLock, Preserve) {
+          DRTE, 1,
+          , 31,  //RESERVED
+          DRTD, 1,
+          , 31,  //RESERVED
+        }
+    // NT RESET
+    OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
+    Field(NRER, DWordAcc, NoLock, Preserve) {
+          NRTE, 1,
+          , 31,  //RESERVED
+          NRTD, 1,
+          , 31,  //RESERVED
+        }
+    // XGE RESET
+    OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+    Field(XRER, DWordAcc, NoLock, Preserve) {
+          XRTE, 31,
+          , 1,    //RESERVED
+          XRTD, 31,
+          , 1,    //RESERVED
+        }
+
+    // GE RESET
+    OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+    Field(GRTR, DWordAcc, NoLock, Preserve) {
+          GR0E, 30,
+          , 2,    //RESERVED
+          GR0D, 30,
+          , 2,    //RESERVED
+          GR1E, 18,
+          , 14,  //RESERVED
+          GR1D, 18,
+          , 14,  //RESERVED
+        }
+    // PPE RESET
+    OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+    Field(PRTR, DWordAcc, NoLock, Preserve) {
+          PRTE, 10,
+          , 22,  //RESERVED
+          PRTD, 10,
+          , 22,  //RESERVED
+        }
+
+    // RCB PPE COM RESET
+    OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
+    Field(RRTR, DWordAcc, NoLock, Preserve) {
+          RRTE, 1,
+          , 31,  //RESERVED
+          RRTD, 1,
+          , 31,  //RESERVED
+        }
+
+    // DSAF Channel RESET
+    OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8)
+    Field(DCRR, DWordAcc, NoLock, Preserve) {
+          DCRE, 1,
+          , 31,  //RESERVED
+          DCRD, 1,
+          , 31,  //RESERVED
+        }
+
+    // RoCE RESET
+    OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8)
+    Field(RKRR, DWordAcc, NoLock, Preserve) {
+          RKRE, 1,
+          , 31,  //RESERVED
+          RKRD, 1,
+          , 31,  //RESERVED
+        }
+
+    // RoCE Clock enable/disable
+    OperationRegion(RKCR, SystemMemory, 0xC0000328, 8)
+    Field(RKCR, DWordAcc, NoLock, Preserve) {
+          RCLE, 1,
+          , 31,  //RESERVED
+          RCLD, 1,
+          , 31,  //RESERVED
+        }
+
+    // Hilink access sel cfg reg
+    OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
+    Field(HSER, DWordAcc, NoLock, Preserve) {
+          HSEL, 2,  // hilink_access_sel & hilink_access_wr_pul
+          , 30,    // RESERVED
+        }
+
+    // Serdes
+    OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
+    Field(H4LR, DWordAcc, NoLock, Preserve) {
+          H4L0, 16,    // port0
+          , 16,    //RESERVED
+          Offset (0x400),
+          H4L1, 16,    // port1
+          , 16,    //RESERVED
+          Offset (0x800),
+          H4L2, 16,    // port2
+          , 16,    //RESERVED
+          Offset (0xc00),
+          H4L3, 16,    // port3
+          , 16,    //RESERVED
+        }
+    OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
+    Field(H3LR, DWordAcc, NoLock, Preserve) {
+          H3L2, 16,    // port4
+          , 16,    //RESERVED
+          Offset (0x400),
+          H3L3, 16,    // port5
+          , 16,    //RESERVED
+        }
+                Name (_HID, "HISI00B2")
+                Name (_CCA, 1) // Cache-coherent controller
+                Name (_CRS, ResourceTemplate (){
+                        Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
+                        Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+        {
+          576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+          589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+        }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+        {
+          960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+          976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+          992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+          1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+          1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+          1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+          1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+          1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+          1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+          1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+          1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+          1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+        }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+        {
+          1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+          1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+          1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+          1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+          1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+          1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+          1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+          1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+          1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+          1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+          1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+          1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+        }
+                })
+                Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"mode", "6port-16rss"},
+        Package () {"buf-size", 4096},
+        Package () {"desc-num", 1024},
+        Package () {"interrupt-parent", Package() {\_SB.MBI3}},
+                        }
+                })
+
+    //reset XGE port
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XRST, 2, Serialized) {
+      ShiftLeft (0x2082082, Arg0, Local0)
+      Or (Local0, 0x1, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset XGE core
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XCRT, 2, Serialized) {
+      ShiftLeft (0x2080, Arg0, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset GE port
+    //Arg0 : GE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(GRST, 2, Serialized) {
+      If (LLessEqual (Arg0, 5)) {
+        //Service port
+        ShiftLeft (0x2082082, Arg0, Local0)
+        ShiftLeft (0x1, Arg0, Local1)
+
+        If (LEqual (Arg1, 0)) {
+          Store(Local1, GR1E)
+          Store(Local0, GR0E)
+        } Else  {
+          Store(Local0, GR0D)
+          Store(Local1, GR1D)
+        }
+      }
+    }
+
+    //reset PPE port
+    //Arg0 : PPE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(PRST, 2, Serialized) {
+      ShiftLeft (0x1, Arg0, Local0)
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, PRTE)
+      } Else  {
+        Store(Local0, PRTD)
+      }
+    }
+
+    //reset DSAF channels
+    //Arg0 : mask
+    //Arg1 : 0 reset, 1 de-reset
+    Method(DCRT, 2, Serialized) {
+      If (LEqual (Arg1, 0)) {
+        Store(Arg0, DCRE)
+      } Else  {
+        Store(Arg0, DCRD)
+      }
+    }
+
+    //reset RoCE
+    //Arg0 : 0 reset, 1 de-reset
+    Method(RRST, 1, Serialized) {
+      If (LEqual (Arg0, 0)) {
+        Store(0x1, RKRE)
+      } Else  {
+        Store(0x1, RCLD)
+        Store(0x1, RKRD)
+        sleep(20)
+        Store(0x1, RCLE)
+      }
+    }
+
+    // Set Serdes Loopback
+    //Arg0 : port
+    //Arg1 : 0 disable, 1 enable
+    Method(SRLP, 2, Serialized) {
+      ShiftLeft (Arg1, 10, Local0)
+      Switch (ToInteger(Arg0))
+      {
+        case (0x0){
+          Store (0, HSEL)
+          Store (H4L0, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L0)
+        }
+        case (0x1){
+          Store (0, HSEL)
+          Store (H4L1, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L1)
+        }
+        case (0x2){
+          Store (0, HSEL)
+          Store (H4L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L2)
+        }
+        case (0x3){
+          Store (0, HSEL)
+          Store (H4L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L3)
+        }
+        case (0x4){
+          Store (3, HSEL)
+          Store (H3L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L2)
+        }
+        case (0x5){
+          Store (3, HSEL)
+          Store (H3L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L3)
+        }
+      }
+    }
+
+    //Reset
+    //Arg0 : reset type (1: dsaf; 2: ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce)
+    //Arg1 : port
+    //Arg2 : 0 disable, 1 enable
+    Method(DRST, 3, Serialized)
+    {
+      Switch (ToInteger(Arg0))
+      {
+        //DSAF reset
+        case (0x1)
+        {
+          Store (Arg2, Local0)
+          If (LEqual (Local0, 0))
+          {
+            Store (0x1, DRTE)
+            Store (0x1, NRTE)
+            Sleep (10)
+            Store (0x1, RRTE)
+          }
+          Else
+          {
+            Store (0x1, DRTD)
+            Store (0x1, NRTD)
+            Sleep (10)
+            Store (0x1, RRTD)
+          }
+        }
+        //Reset PPE port
+        case (0x2)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          PRST (Local0, Local1)
+        }
+
+        //Reset XGE core
+        case (0x3)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XCRT (Local0, Local1)
+        }
+        //Reset XGE port
+        case (0x4)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XRST (Local0, Local1)
+        }
+
+        //Reset GE port
+        case (0x5)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          GRST (Local0, Local1)
+        }
+
+        //Reset DSAF Channels
+        case (0x6)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          DCRT (Local0, Local1)
+        }
+
+        //Reset RoCE
+        case (0x7)
+        {
+          // Discarding Arg1 as it is always 0
+          Store (Arg2, Local0)
+          RRST (Local0)
+        }
+      }
+    }
+
+    // _DSM Device Specific Method
+    //
+    // Arg0: UUID Unique function identifier
+    // Arg1: Integer Revision Level
+    // Arg2: Integer Function Index
+    //   0 : Return Supported Functions bit mask
+    //   1 : Reset Sequence
+    //    Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5:ge; 6:dchan; 7:roce)
+    //    Arg3[1] : port index in dsaf
+    //    Arg3[2] : 0 reset, 1 cancle reset
+    //   2 : Set Serdes Loopback
+    //    Arg3[0] : port
+    //    Arg3[1] : 0 disable, 1 enable
+    //   3 : LED op set
+    //    Arg3[0] : op type
+    //    Arg3[1] : port
+    //    Arg3[2] : para
+    //   4 : Get port type (GE or XGE)
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 GE, 1 XGE
+    //   5 : Get sfp status
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 no sfp, 1 have sfp
+    // Arg3: Package Parameters
+    Method (_DSM, 4, Serialized)
+    {
+      If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+      {
+        If (LEqual (Arg1, 0x00))
+        {
+          Switch (ToInteger(Arg2))
+          {
+            case (0x0)
+            {
+              Return (Buffer () {0x3F})
+            }
+
+            //Reset Sequence
+            case (0x1)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              Store (DeRefOf (Index (Arg3, 2)), Local2)
+              DRST (Local0, Local1, Local2)
+            }
+
+            //Set Serdes Loopback
+            case (0x2)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              SRLP (Local0, Local1)
+            }
+
+            //LED op set
+            case (0x3)
+            {
+
+            }
+
+            // Get port type (GE or XGE)
+            case (0x4)
+            {
+              Store (0, Local1)
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              If (LLessEqual (Local0, 3))
+              {
+                // mac0: Hilink4 Lane0
+                // mac1: Hilink4 Lane1
+                // mac2: Hilink4 Lane2
+                // mac3: Hilink4 Lane3
+                Store (H4ST, Local1)
+              }
+              ElseIf (LLessEqual (Local0, 5))
+              {
+                // mac4: Hilink3 Lane2
+                // mac5: Hilink3 Lane3
+                Store (H3ST, Local1)
+              }
+
+              Return (Local1)
+            }
+
+            //Get sfp status
+            case (0x5)
+            {
+
+            }
+          }
+        }
+      }
+      Return (Buffer() {0x00})
+    }
+    Device (PRT0)
+    {
+      Name (_ADR, 0x0)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 0},
+                Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+    Device (PRT1)
+    {
+      Name (_ADR, 0x1)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 1},
+                Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+    Device (PRT4)
+    {
+      Name (_ADR, 0x4)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 4},
+                                Package () {"phy-mode", "sgmii"},
+                Package () {"phy-addr", 0},
+                Package () {"mdio-node", Package (){\_SB.MDIO}},
+                Package () {"media-type", "copper"},
+                        }
+                })
+    }
+    Device (PRT5)
+    {
+      Name (_ADR, 0x5)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 5},
+                                Package () {"phy-mode", "sgmii"},
+                Package () {"phy-addr", 1},
+                Package () {"mdio-node", Package (){\_SB.MDIO}},
+                Package () {"media-type", "copper"},
+                        }
+                })
+    }
+  }
+  Device (ETH4) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 4},
+      }
+    })
+  }
+  Device (ETH5) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 5},
+      }
+    })
+  }
+  Device (ETH0) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 0},
+      }
+    })
+  }
+  Device (ETH1) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 1},
+      }
+    })
+  }
+  Device (ROCE) {
+    Name(_HID, "HISI00D1")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}},
+        Package () {"dsaf-handle", Package (){\_SB.DSF0}},
+        Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes
+        Package () {"interrupt-names", Package() {"hns-roce-comp-0",
+                                                  "hns-roce-comp-1",
+                                                  "hns-roce-comp-2",
+                                                  "hns-roce-comp-3",
+                                                  "hns-roce-comp-4",
+                                                  "hns-roce-comp-5",
+                                                  "hns-roce-comp-6",
+                                                  "hns-roce-comp-7",
+                                                  "hns-roce-comp-8",
+                                                  "hns-roce-comp-9",
+                                                  "hns-roce-comp-10",
+                                                  "hns-roce-comp-11",
+                                                  "hns-roce-comp-12",
+                                                  "hns-roce-comp-13",
+                                                  "hns-roce-comp-14",
+                                                  "hns-roce-comp-15",
+                                                  "hns-roce-comp-16",
+                                                  "hns-roce-comp-17",
+                                                  "hns-roce-comp-18",
+                                                  "hns-roce-comp-19",
+                                                  "hns-roce-comp-20",
+                                                  "hns-roce-comp-21",
+                                                  "hns-roce-comp-22",
+                                                  "hns-roce-comp-23",
+                                                  "hns-roce-comp-24",
+                                                  "hns-roce-comp-25",
+                                                  "hns-roce-comp-26",
+                                                  "hns-roce-comp-27",
+                                                  "hns-roce-comp-28",
+                                                  "hns-roce-comp-29",
+                                                  "hns-roce-comp-30",
+                                                  "hns-roce-comp-31",
+                                                  "hns-roce-async",
+                                                  "hns-roce-common"}},
+      }
+    })
+    Name (_CRS, ResourceTemplate (){
+      Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000)
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI7")
+        {
+          722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+          734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+          746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+        }
+   })
+    Name (_PRS, ResourceTemplate (){
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+        {
+          722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+          734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+          746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+        }
+   })
+ }
+}
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl
new file mode 100644
index 0000000..46b8db0
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl
@@ -0,0 +1,305 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  // Mbi-gen pcie subsys
+  Device(MBI0) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+   Name(_PRS, ResourceTemplate() {
+       Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {640, 641} //OHCI: 640, EHCI 641
+       })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 2}
+        }
+   })
+  }
+
+  // Mbi-gen sas1 intc
+  Device(MBI1) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, )
+                  {
+      64,65,66,67,68,
+      69,70,71,72,73,
+      74,75,76,77,78,
+      79,80,81,82,83,
+      84,85,86,87,88,
+      89,90,91,92,93,
+      94,95,96,97,98,
+      99,100,101,102,103,
+      104,105,106,107,108,
+      109,110,111,112,113,
+      114,115,116,117,118,
+      119,120,121,122,123,
+      124,125,126,127,128,
+      129,130,131,132,133,
+      134,135,136,137,138,
+      139,140,141,142,143,
+      144,145,146,147,148,
+      149,150,151,152,153,
+      154,155,156,157,158,
+      159,
+      }
+
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, )
+                  {
+         576,577,578,579,580,
+      581,582,583,584,585,
+      586,587,588,589,590,
+      591,592,593,594,595,
+      596,597,598,599,600,
+      601,602,603,604,605,
+      606,607,
+      }
+          })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 128}
+        }
+   })
+  }
+
+  Device(MBI2) {          // Mbi-gen sas2 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+       Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, )
+                  {
+      192,193,194,195,196,
+      197,198,199,200,201,
+      202,203,204,205,206,
+      207,208,209,210,211,
+      212,213,214,215,216,
+      217,218,219,220,221,
+      222,223,224,225,226,
+      227,228,229,230,231,
+      232,233,234,235,236,
+      237,238,239,240,241,
+      242,243,244,245,246,
+      247,248,249,250,251,
+      252,253,254,255,256,
+      257,258,259,260,261,
+      262,263,264,265,266,
+      267,268,269,270,271,
+      272,273,274,275,276,
+      277,278,279,280,281,
+      282,283,284,285,286,
+      287,
+      }
+
+                  Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, )
+                  {
+      608,609,610,611,
+      612,613,614,615,616,
+      617,618,619,620,621,
+      622,623,624,625,626,
+      627,628,629,630,631,
+      632,633,634,635,636,
+      637,638,639,
+      }
+          })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 128}
+        }
+   })
+  }
+
+  Device(MBI3) {          // Mbi-gen dsa0 srv intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+
+Name(_PRS, ResourceTemplate() {
+   Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
+        {
+          576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+          589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+        }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
+        {
+          960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+          976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+          992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+          1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+          1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+          1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+          1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+          1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+          1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+          1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+          1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+          1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+        }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,)
+        {
+          1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+          1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+          1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+          1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+          1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+          1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+          1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+          1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+          1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+          1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+          1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+          1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+        }
+})
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 409}
+        }
+   })
+  }
+/*
+  Device(MBI4) {          // Mbi-gen dsa1 dbg0 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 9}
+        }
+   })
+  }
+
+  Device(MBI5) {          // Mbi-gen dsa2 dbg1 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 9}
+        }
+   })
+  }
+*/
+  Device(MBI6) {          // Mbi-gen dsa sas0 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+     Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, )
+     {
+      64,65,66,67,68,
+      69,70,71,72,73,
+      74,75,76,77,78,
+      79,80,81,82,83,
+      84,85,86,87,88,
+      89,90,91,92,93,
+      94,95,96,97,98,
+      99,100,101,102,103,
+      104,105,106,107,108,
+      109,110,111,112,113,
+      114,115,116,117,118,
+      119,120,121,122,123,
+      124,125,126,127,128,
+      129,130,131,132,133,
+      134,135,136,137,138,
+      139,140,141,142,143,
+      144,145,146,147,148,
+      149,150,151,152,153,
+      154,155,156,157,158,
+      159,
+      }
+
+      Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, )
+                  {
+      601,602,603,604,
+      605,606,607,608,609,
+      610,611,612,613,614,
+      615,616,617,618,619,
+      620,621,622,623,624,
+      625,626,627,628,629,
+      630,631,632,
+      }
+          })
+
+
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 128}
+        }
+   })
+  }
+  Device(MBI7) {          // Mbi-gen roce intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+    Name (_PRS, ResourceTemplate (){
+       Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+         {
+           722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+           734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+           746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+         }
+    })
+    Name(_DSD, Package () {
+         ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+         Package ()
+         {
+           Package () {"num-pins", 34}
+         }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl
new file mode 100644
index 0000000..573c0a3
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl
@@ -0,0 +1,261 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+  // PCIe Root bus
+  Device (PCI0)
+  {
+    Name (_HID, "HISI0080") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0) // Segment of this Root complex
+    Name(_BBN, 0) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x0, // AddressMinimum - Minimum Bus Number
+          0x1f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x20 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xb2000000, // Min Base Address pci address
+          0xb7feffff, // Max Base Address
+          0x0, // Translate
+          0x5ff0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0xb7ff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+
+    Device (RES0)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CRS, ResourceTemplate (){
+        Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000)
+      })
+    }
+
+    OperationRegion(SCTR, SystemMemory, 0xa009131c, 4)
+    Field(SCTR, AnyAcc, NoLock, Preserve) {
+      LSTA, 32,
+    }
+    Method(_DSM, 0x4, Serialized) {
+      If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
+        switch(ToInteger(Arg2))
+        {
+          // Function 0: Return LinkStatus
+          case(0) {
+              Store (0, Local0)
+              Store (LSTA, Local0)
+              Return (Local0)
+          }
+          default {
+          }
+        }
+      }
+      // If not one of the function identifiers we recognize, then return a buffer
+      // with bit 0 set to 0 indicating no functions supported.
+      return(Buffer(){0})
+    }
+  } // Device(PCI0)
+
+  // PCIe Root bus
+  Device (PCI1)
+  {
+    Name (_HID, "HISI0080") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 1) // Segment of this Root complex
+    Name(_BBN, 0xe0) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0xe0, // AddressMinimum - Minimum Bus Number
+          0xff, // AddressMaximum - Maximum Bus Number
+          0,   // AddressTranslation - Set to 0
+          0x20 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xb8000000, // Min Base Address pci address
+          0xbdfeffff, // Max Base Address
+          0x0, // Translate
+          0x5ff0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0xbdff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+
+    Device (RES1)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CRS, ResourceTemplate (){
+        Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000)
+      })
+    }
+
+    OperationRegion(SCTR, SystemMemory, 0xa020131c, 4)
+    Field(SCTR, AnyAcc, NoLock, Preserve) {
+      LSTA, 32,
+    }
+    Method(_DSM, 0x4, Serialized) {
+      If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
+
+        switch(ToInteger(Arg2))
+        {
+          // Function 0: Return LinkStatus
+          case(0) {
+              Store (0, Local0)
+              Store (LSTA, Local0)
+              Return (Local0)
+          }
+          default {
+          }
+        }
+      }
+      // If not one of the function identifiers we recognize, then return a buffer
+      // with bit 0 set to 0 indicating no functions supported.
+      return(Buffer(){0})
+    }
+  } // Device(PCI1)
+
+  // PCIe Root bus
+  Device (PCI2)
+  {
+    Name (_HID, "HISI0080") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 2) // Segment of this Root complex
+    Name(_BBN, 0x80) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x80, // AddressMinimum - Minimum Bus Number
+          0x9f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x20 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xaa000000, // Min Base Address
+          0xaffeffff, // Max Base Address
+          0x0, // Translate
+          0x5ff0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0xafff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+
+    Device (RES2)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CRS, ResourceTemplate (){
+        Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000)
+      })
+    }
+
+    OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4)
+    Field(SCTR, AnyAcc, NoLock, Preserve) {
+      LSTA, 32,
+    }
+    Method(_DSM, 0x4, Serialized) {
+      If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949")))
+      {
+        switch(ToInteger(Arg2))
+        {
+          // Function 0: Return LinkStatus
+          case(0) {
+              Store (0, Local0)
+              Store (LSTA, Local0)
+              Return (Local0)
+          }
+          default {
+          }
+        }
+      }
+      // If not one of the function identifiers we recognize, then return a buffer
+      // with bit 0 set to 0 indicating no functions supported.
+      return(Buffer(){0})
+    }
+  } // Device(PCI2)
+}
+
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl
new file mode 100644
index 0000000..7b5d4de
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl
@@ -0,0 +1,367 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  Device(SAS0) {
+    Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6")
+      {
+        64,65,66,67,68,
+        69,70,71,72,73,
+        74,75,76,77,78,
+        79,80,81,82,83,
+        84,85,86,87,88,
+        89,90,91,92,93,
+        94,95,96,97,98,
+        99,100,101,102,103,
+        104,105,106,107,108,
+        109,110,111,112,113,
+        114,115,116,117,118,
+        119,120,121,122,123,
+        124,125,126,127,128,
+        129,130,131,132,133,
+        134,135,136,137,138,
+        139,140,141,142,143,
+        144,145,146,147,148,
+        149,150,151,152,153,
+        154,155,156,157,158,
+        159,
+      }
+
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI6" )
+      {
+        601,602,603,604,
+        605,606,607,608,609,
+        610,611,612,613,614,
+        615,616,617,618,619,
+        620,621,622,623,624,
+        625,626,627,628,629,
+        630,631,632,
+      }
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"interrupt-parent",Package() {\_SB.MBI6}},
+        Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},
+        Package () {"queue-count", 16},
+        Package () {"phy-count", 8},
+      }
+    })
+
+    OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x338),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xa60),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a30),
+      STS, 32,
+    }
+
+    OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000)
+    Field (PHYS, DWordAcc, NoLock, Preserve) {
+      Offset (0x0014),
+      PHY0, 32,
+      Offset (0x0414),
+      PHY1, 32,
+      Offset (0x0814),
+      PHY2, 32,
+      Offset (0x0c14),
+      PHY3, 32,
+      Offset (0x1014),
+      PHY4, 32,
+      Offset (0x1414),
+      PHY5, 32,
+      Offset (0x1814),
+      PHY6, 32,
+      Offset (0x1c14),
+      PHY7, 32,
+    }
+
+    OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+    Field (SYSR, DWordAcc, NoLock, Preserve) {
+      Offset (0xe014),
+      DIE4, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+      Store(DIE4, local0)
+      If (LEqual (local0, 0)) {
+        /* 66MHZ */
+        Store(0x0199B694, Local1)
+        Store(Local1, PHY0)
+        Store(Local1, PHY1)
+        Store(Local1, PHY2)
+        Store(Local1, PHY3)
+        Store(Local1, PHY4)
+        Store(Local1, PHY5)
+        Store(Local1, PHY6)
+        Store(Local1, PHY7)
+      }
+    }
+  }
+
+  Device(SAS1) {
+    Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
+
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+      {
+        64,65,66,67,68,
+        69,70,71,72,73,
+        74,75,76,77,78,
+        79,80,81,82,83,
+        84,85,86,87,88,
+        89,90,91,92,93,
+        94,95,96,97,98,
+        99,100,101,102,103,
+        104,105,106,107,108,
+        109,110,111,112,113,
+        114,115,116,117,118,
+        119,120,121,122,123,
+        124,125,126,127,128,
+        129,130,131,132,133,
+        134,135,136,137,138,
+        139,140,141,142,143,
+        144,145,146,147,148,
+        149,150,151,152,153,
+        154,155,156,157,158,
+        159,
+      }
+
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+      {
+        576,577,578,579,580,
+        581,582,583,584,585,
+        586,587,588,589,590,
+        591,592,593,594,595,
+        596,597,598,599,600,
+        601,602,603,604,605,
+        606,607,
+      }
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"interrupt-parent",Package() {\_SB.MBI1}},
+        Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+        Package () {"queue-count", 16},
+        Package () {"phy-count", 8},
+        Package () {"hip06-sas-v2-quirk-amt", 1},
+      }
+    })
+
+    OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x318),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xa18),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a0c),
+      STS, 32,
+    }
+
+    OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000)
+    Field (PHYS, DWordAcc, NoLock, Preserve) {
+      Offset (0x0014),
+      PHY0, 32,
+      Offset (0x0414),
+      PHY1, 32,
+      Offset (0x0814),
+      PHY2, 32,
+      Offset (0x0c14),
+      PHY3, 32,
+      Offset (0x1014),
+      PHY4, 32,
+      Offset (0x1414),
+      PHY5, 32,
+      Offset (0x1814),
+      PHY6, 32,
+      Offset (0x1c14),
+      PHY7, 32,
+    }
+
+    OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+    Field (SYSR, DWordAcc, NoLock, Preserve) {
+      Offset (0xe014),
+      DIE4, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+      Store(DIE4, local0)
+      If (LEqual (local0, 0)) {
+        /* 66MHZ */
+        Store(0x0199B694, Local1)
+        Store(Local1, PHY0)
+        Store(Local1, PHY1)
+        Store(Local1, PHY2)
+        Store(Local1, PHY3)
+        Store(Local1, PHY4)
+        Store(Local1, PHY5)
+        Store(Local1, PHY6)
+        Store(Local1, PHY7)
+      }
+    }
+  }
+
+  Device(SAS2) {
+    Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
+
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+      {
+        192,193,194,195,196,
+        197,198,199,200,201,
+        202,203,204,205,206,
+        207,208,209,210,211,
+        212,213,214,215,216,
+        217,218,219,220,221,
+        222,223,224,225,226,
+        227,228,229,230,231,
+        232,233,234,235,236,
+        237,238,239,240,241,
+        242,243,244,245,246,
+        247,248,249,250,251,
+        252,253,254,255,256,
+        257,258,259,260,261,
+        262,263,264,265,266,
+        267,268,269,270,271,
+        272,273,274,275,276,
+        277,278,279,280,281,
+        282,283,284,285,286,
+        287,
+      }
+
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+      {
+        608,609,610,611,
+        612,613,614,615,616,
+        617,618,619,620,621,
+        622,623,624,625,626,
+        627,628,629,630,631,
+        632,633,634,635,636,
+        637,638,639,
+      }
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"interrupt-parent",Package() {\_SB.MBI2}},
+        Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+        Package () {"queue-count", 16},
+        Package () {"phy-count", 9},
+      }
+    })
+
+    OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x3a8),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xae0),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a70),
+      STS, 32,
+    }
+
+    OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400)
+    Field (PHYS, DWordAcc, NoLock, Preserve) {
+      Offset (0x0014),
+      PHY0, 32,
+      Offset (0x0414),
+      PHY1, 32,
+      Offset (0x0814),
+      PHY2, 32,
+      Offset (0x0c14),
+      PHY3, 32,
+      Offset (0x1014),
+      PHY4, 32,
+      Offset (0x1414),
+      PHY5, 32,
+      Offset (0x1814),
+      PHY6, 32,
+      Offset (0x1c14),
+      PHY7, 32,
+      offset (0x2014),
+      PHY8, 32,
+    }
+
+    OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000)
+    Field (SYSR, DWordAcc, NoLock, Preserve) {
+      Offset (0xe014),
+      DIE4, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+      Store(DIE4, local0)
+      If (LEqual (local0, 0)) {
+        /* 66MHZ */
+        Store(0x0199B694, Local1)
+        Store(Local1, PHY0)
+        Store(Local1, PHY1)
+        Store(Local1, PHY2)
+        Store(Local1, PHY3)
+        Store(Local1, PHY4)
+        Store(Local1, PHY5)
+        Store(Local1, PHY6)
+        Store(Local1, PHY7)
+        Store(Local1, PHY8)
+      }
+    }
+  }
+
+}
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl
new file mode 100644
index 0000000..9132965
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Usb.asl
@@ -0,0 +1,136 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+  Device (USB0)
+        {
+            Name (_HID, "PNP0D20")  // _HID: Hardware ID
+            Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */)  // _CID: Compatible ID
+            Name (_CCA, One)  // _CCA: Cache Coherency Attribute
+            Method (_CRS, 0, Serialized)  // _CRS: Current Resource Settings
+            {
+                Name (RBUF, ResourceTemplate ()
+                {
+                    Memory32Fixed (ReadWrite,
+                        0xa7020000,         // Address Base
+                        0x00010000,         // Address Length
+                        )
+                    Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0")
+                    {
+                        641, //EHCI
+                    }
+                })
+                Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
+            }
+
+     Name (_DSD, Package () {
+              ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+              Package ()
+              {
+                  Package () {"interrupt-parent",Package() {\_SB.MBI0}}
+              }
+     })
+
+            Device (RHUB)
+            {
+                Name (_ADR, Zero)  // _ADR: Address
+                Device (PRT1)
+                {
+                    Name (_ADR, One)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        0xFF,
+                        Zero,
+                        Zero,
+                        Zero
+                    })
+                    Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device
+                    {
+                        ToPLD (
+                            PLD_Revision       = 0x1,
+                            PLD_IgnoreColor    = 0x1,
+                            PLD_Red            = 0x0,
+                            PLD_Green          = 0x0,
+                            PLD_Blue           = 0x0,
+                            PLD_Width          = 0x0,
+                            PLD_Height         = 0x0,
+                            PLD_UserVisible    = 0x1,
+                            PLD_Dock           = 0x0,
+                            PLD_Lid            = 0x0,
+                            PLD_Panel          = "UNKNOWN",
+                            PLD_VerticalPosition = "UPPER",
+                            PLD_HorizontalPosition = "LEFT",
+                            PLD_Shape          = "UNKNOWN",
+                            PLD_GroupOrientation = 0x0,
+                            PLD_GroupToken     = 0x0,
+                            PLD_GroupPosition  = 0x0,
+                            PLD_Bay            = 0x0,
+                            PLD_Ejectable      = 0x0,
+                            PLD_EjectRequired  = 0x0,
+                            PLD_CabinetNumber  = 0x0,
+                            PLD_CardCageNumber = 0x0,
+                            PLD_Reference      = 0x0,
+                            PLD_Rotation       = 0x0,
+                            PLD_Order          = 0x0,
+                            PLD_VerticalOffset = 0x0,
+                            PLD_HorizontalOffset = 0x0)
+
+                    })
+                }
+
+                Device (PRT2)
+                {
+                    Name (_ADR, 0x02)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+
+                Device (PRT3)
+                {
+                    Name (_ADR, 0x03)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+
+                Device (PRT4)
+                {
+                    Name (_ADR, 0x04)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+            }
+        }
+}
+
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl
new file mode 100644
index 0000000..4185f80
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl
@@ -0,0 +1,29 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Hi1610Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI  ", "HIP06   ", EFI_ACPI_ARM_OEM_REVISION) {
+     include ("Lpc.asl")
+     include ("D03Mbig.asl")
+     include ("CPU.asl")
+     include ("D03Usb.asl")
+     include ("D03Hns.asl")
+     include ("D03Sas.asl")
+     include ("D03Pci.asl")
+}
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl
new file mode 100644
index 0000000..0965afc
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Lpc.asl
@@ -0,0 +1,25 @@
+/** @file
+*
+*  Copyright (c) 2016 Hisilicon Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// LPC
+//
+
+Device (LPC0)
+{
+  Name(_HID, "HISI0191")  // HiSi LPC
+  Name (_CRS, ResourceTemplate () {
+    Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
+  })
+}
diff --git a/Platforms/ARM/Juno/AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc
index 137ead7..72cc66c 100644
--- a/Platforms/ARM/Juno/AcpiTables/Facs.aslc
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc
@@ -2,6 +2,8 @@
 *  Firmware ACPI Control Structure (FACS)
 *
 *  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -11,6 +13,8 @@
 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 *
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
 **/
 
 #include <IndustryStandard/Acpi.h>
@@ -60,3 +64,4 @@ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
 // data structure from the executable
 //
 VOID* CONST ReferenceAcpiTable = &Facs;
+
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..5307041
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc
@@ -0,0 +1,91 @@
+/** @file
+*  Fixed ACPI Description Table (FADT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1610Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+  ARM_ACPI_HEADER (
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+  ),
+  0,                                                                        // UINT32     FirmwareCtrl
+  0,                                                                        // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
+  EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED,                                      // UINT8      PreferredPmProfile
+  0,                                                                        // UINT16     SciInt
+  0,                                                                        // UINT32     SmiCmd
+  0,                                                                        // UINT8      AcpiEnable
+  0,                                                                        // UINT8      AcpiDisable
+  0,                                                                        // UINT8      S4BiosReq
+  0,                                                                        // UINT8      PstateCnt
+  0,                                                                        // UINT32     Pm1aEvtBlk
+  0,                                                                        // UINT32     Pm1bEvtBlk
+  0,                                                                        // UINT32     Pm1aCntBlk
+  0,                                                                        // UINT32     Pm1bCntBlk
+  0,                                                                        // UINT32     Pm2CntBlk
+  0,                                                                        // UINT32     PmTmrBlk
+  0,                                                                        // UINT32     Gpe0Blk
+  0,                                                                        // UINT32     Gpe1Blk
+  0,                                                                        // UINT8      Pm1EvtLen
+  0,                                                                        // UINT8      Pm1CntLen
+  0,                                                                        // UINT8      Pm2CntLen
+  0,                                                                        // UINT8      PmTmrLen
+  0,                                                                        // UINT8      Gpe0BlkLen
+  0,                                                                        // UINT8      Gpe1BlkLen
+  0,                                                                        // UINT8      Gpe1Base
+  0,                                                                        // UINT8      CstCnt
+  0,                                                                        // UINT16     PLvl2Lat
+  0,                                                                        // UINT16     PLvl3Lat
+  0,                                                                        // UINT16     FlushSize
+  0,                                                                        // UINT16     FlushStride
+  0,                                                                        // UINT8      DutyOffset
+  0,                                                                        // UINT8      DutyWidth
+  0,                                                                        // UINT8      DayAlrm
+  0,                                                                        // UINT8      MonAlrm
+  0,                                                                        // UINT8      Century
+  0,                                                                        // UINT16     IaPcBootArch
+  0,                                                                        // UINT8      Reserved1
+  EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  ResetReg
+  0,                                                                        // UINT8      ResetValue
+  EFI_ACPI_5_1_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
+  EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
+  0,                                                                        // UINT64     XFirmwareCtrl
+  0,                                                                        // UINT64     XDsdt
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
+  NULL_GAS                                                                  // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..922f5c3
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc
@@ -0,0 +1,96 @@
+/** @file
+*  Generic Timer Description Table (GTDT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1610Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0
+#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL       0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+  #define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+
+#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+  EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdogs[HI1610_WATCHDOG_COUNT];
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+  {
+    ARM_ACPI_HEADER(
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES,
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+    ),
+    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
+    0,                                            // UINT32  Reserved
+    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
+    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
+    0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
+#ifdef notyet
+    PV660_WATCHDOG_COUNT,                          // UINT32  PlatformTimerCount
+    sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+  },
+  {
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
+        0, 0, 0, 0),
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
+        0, 0, 0, 0)
+  }
+#else /* !notyet */
+  0, 0
+  }
+#endif
+  };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
+
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h
new file mode 100644
index 0000000..5a95b02
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h
@@ -0,0 +1,48 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#ifndef _HI1610_PLATFORM_H_
+#define _HI1610_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
+#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('I','N','T','L')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+  }
+
+#define HI1610_WATCHDOG_COUNT  2
+
+#endif
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc
new file mode 100644
index 0000000..7bebe8f
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc
@@ -0,0 +1,128 @@
+/** @file
+*  Multiple APIC Description Table (MADT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1610Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiNextLib.h>
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+// 0x20000 is only for socket 0
+#define PLATFORM_GET_MPID(ClusterId, CoreId)   (0x10000 | ((ClusterId) << 8) | (CoreId))
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_5_1_GIC_STRUCTURE                            GicInterfaces[16];
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+  EFI_ACPI_6_0_GIC_ITS_STRUCTURE                      GicITS[1];
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+  {
+    ARM_ACPI_HEADER (
+      EFI_ACPI_1_0_APIC_SIGNATURE,
+      EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+      EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+    ),
+    //
+    // MADT specific fields
+    //
+    0, // LocalApicAddress
+    0, // Flags
+  },
+  {
+    // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+    //                                          GsivId, GicRBase, Mpidr)
+    // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+    //       ACPI v5.1).
+    //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+    //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        0, 0, PLATFORM_GET_MPID(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        1, 1, PLATFORM_GET_MPID(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        2, 2, PLATFORM_GET_MPID(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        3, 3, PLATFORM_GET_MPID(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        5, 5, PLATFORM_GET_MPID(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        6, 6, PLATFORM_GET_MPID(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        7, 7, PLATFORM_GET_MPID(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        8, 8, PLATFORM_GET_MPID(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        9, 9, PLATFORM_GET_MPID(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        10, 10, PLATFORM_GET_MPID(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        11, 11, PLATFORM_GET_MPID(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        13, 13, PLATFORM_GET_MPID(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        14, 14, PLATFORM_GET_MPID(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        15, 15, PLATFORM_GET_MPID(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */),
+  },
+
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4),
+  {
+    EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000),
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc
new file mode 100644
index 0000000..8b7aee4
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Slit.aslc
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     Yi Li - yi.li@linaro.org
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1610Platform.h"
+
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000014
+
+#pragma pack(1)
+typedef struct {
+  UINT8   Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+
+typedef struct {
+  EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER    Header;
+  EFI_ACPI_5_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE                NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+
+} EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE;
+#pragma pack()
+
+//
+// System Locality Information Table
+// Please modify all values in Slit.h only.
+//
+EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
+  {
+    {
+      EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
+      sizeof (EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE),
+      EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
+      0x00,                                                     // Checksum will be updated at runtime
+      {EFI_ACPI_ARM_OEM_ID},
+      EFI_ACPI_ARM_OEM_TABLE_ID,
+      EFI_ACPI_ARM_OEM_REVISION,
+      EFI_ACPI_ARM_CREATOR_ID,
+      EFI_ACPI_ARM_CREATOR_REVISION,
+    },
+    //
+    // Beginning of SLIT specific fields
+    //
+    EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
+  },
+  {
+    {{0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27}}, //Locality   0
+    {{0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26}}, //Locality   1
+    {{0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25}}, //Locality   2
+    {{0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24}}, //Locality   3
+    {{0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23}}, //Locality   4
+    {{0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22}}, //Locality   5
+    {{0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21}}, //Locality   6
+    {{0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20}}, //Locality   7
+    {{0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}}, //Locality   8
+    {{0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}}, //Locality   9
+    {{0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D}}, //Locality   10
+    {{0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C}}, //Locality   11
+    {{0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B}}, //Locality   12
+    {{0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A}}, //Locality   13
+    {{0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17, 0x18, 0x19}}, //Locality   14
+    {{0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16, 0x17, 0x18}}, //Locality   15
+    {{0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10, 0x16, 0x17}}, //Locality   16
+    {{0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A, 0x15, 0x16}}, //Locality   17
+    {{0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x0A, 0x10}}, //Locality   18
+    {{0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x10, 0x0A}}, //Locality   19
+  },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Slit;
+
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc
new file mode 100644
index 0000000..99df1a4
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Srat.aslc
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     Yi Li - yi.li@linaro.org
+ *
+ *  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1610Platform.h"
+#include <Library/AcpiLib.h>
+#include <Library/AcpiNextLib.h>
+
+
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE_COUNT  4
+#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT                      4
+
+
+#pragma pack(1)
+typedef struct {
+  EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER          Header;
+  EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE  Apic;
+  EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE                      Memory[2];
+  EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE                        GICC[16];
+} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE;
+
+#pragma pack()
+
+
+//
+// Static Resource Affinity Table definition
+//
+EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE Srat = {
+  {
+    {EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+    sizeof (EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE),
+    EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
+    0x00,                                                     // Checksum will be updated at runtime
+    {EFI_ACPI_ARM_OEM_ID},
+    EFI_ACPI_ARM_OEM_TABLE_ID,
+    EFI_ACPI_ARM_OEM_REVISION,
+    EFI_ACPI_ARM_CREATOR_ID,
+    EFI_ACPI_ARM_CREATOR_REVISION},
+    /*Reserved*/
+    0x00000001,                                  // Reserved to be 1 for backward compatibility
+    EFI_ACPI_RESERVED_QWORD
+  },
+  /**/
+  {
+      0x00,                                     // Subtable Type:Processor Local APIC/SAPIC Affinity
+      sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE),                                     //Length
+      0x00,                                     //Proximity Domain Low(8)
+      0x00,                                     //Apic ID
+      0x00000001,                               //Flags
+      0x00,                                     //Local Sapic EID
+      {0,0,0},                                     //Proximity Domain High(24)
+      0x00000000,                               //ClockDomain
+  },
+  //
+  //
+  // Memory Affinity
+  //
+  {
+    EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x40000000,0x00000000,0x00000001),
+    EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x40000000,0x00000002,0xC0000000,0x00000001,0x00000001),
+  },
+
+  /*Processor Local x2APIC Affinity*/
+  //{
+  //   0x02,                                              // Subtable Type:Processor Local x2APIC Affinity
+  //   sizeof(EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE),
+  //   {0,0},                                             //Reserved1
+  //   0x00000000,                                        //Proximity Domain
+  //   0x00000000,                                        //Apic ID
+  //   0x00000001,                                        //Flags
+  //   0x00000000,                                        //Clock Domain
+  //   {0,0,0,0},                                         //Reserved2
+  //},
+
+  {
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000),   //GICC Affinity Processor 0
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000),   //GICC Affinity Processor 1
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000),   //GICC Affinity Processor 2
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000),   //GICC Affinity Processor 3
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000),   //GICC Affinity Processor 4
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000),   //GICC Affinity Processor 5
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000),   //GICC Affinity Processor 6
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000),   //GICC Affinity Processor 7
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000),   //GICC Affinity Processor 8
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000),   //GICC Affinity Processor 9
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000),   //GICC Affinity Processor 10
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000),   //GICC Affinity Processor 11
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000),   //GICC Affinity Processor 12
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000),   //GICC Affinity Processor 13
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000),   //GICC Affinity Processor 14
+    EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000)    //GICC Affinity Processor 15
+  },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Srat;
+
diff --git a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h
new file mode 100755
index 0000000..077dd5e
--- /dev/null
+++ b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h
@@ -0,0 +1,131 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_
+
+typedef enum {
+  EmHilink0Hccs1X8 = 0,
+  EmHilink0Pcie1X8 = 2,
+  EmHilink0Pcie1X4Pcie2X4 = 3,
+  EmHilink0Sas2X8 = 4,
+  EmHilink0Hccs1X8Width16,
+  EmHilink0Hccs1X8Width32,
+} HILINK0_MODE_TYPE;
+
+typedef enum {
+  EmHilink1Sas2X1 = 0,
+  EmHilink1Hccs0X8 = 1,
+  EmHilink1Pcie0X8 = 2,
+  EmHilink1Hccs0X8Width16,
+  EmHilink1Hccs0X8Width32,
+} HILINK1_MODE_TYPE;
+
+typedef enum {
+  EmHilink2Pcie2X8 = 0,
+  EmHilink2Sas0X8 = 2,
+} HILINK2_MODE_TYPE;
+
+typedef enum {
+  EmHilink5Pcie3X4 = 0,
+  EmHilink5Pcie2X2Pcie3X2 = 1,
+  EmHilink5Sas1X4 = 2,
+} HILINK5_MODE_TYPE;
+
+typedef enum {
+  Em32coreEvbBoard = 0,
+  Em16coreEvbBoard = 1,
+  EmV2R1CO5Borad = 2,
+  EmOtherBorad
+} BOARD_TYPE;
+
+
+typedef struct {
+  HILINK0_MODE_TYPE Hilink0Mode;
+  HILINK1_MODE_TYPE Hilink1Mode;
+  HILINK2_MODE_TYPE Hilink2Mode;
+  UINT32 Hilink3Mode;
+  UINT32 Hilink4Mode;
+  HILINK5_MODE_TYPE Hilink5Mode;
+  UINT32 Hilink6Mode;
+  UINT32 UseSsc;
+} SERDES_PARAM;
+
+
+#define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
+#define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
+#define SERDES_INVALID_RATE_MODE  0xFFFFFFFF
+
+typedef struct {
+  UINT32 MacroId;
+  UINT32 DsNum;
+  UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
+extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
+extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
+UINT32 GetEthType(UINT8 EthChannel);
+
+EFI_STATUS
+EfiSerdesInitWrap (VOID);
+
+void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg);
+
+//EYE test
+UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData);
+
+UINT32 Serdes_ReadBert(UINT32   ulMacroId , UINT32   ulDsNum);
+
+//PRBS test
+int serdes_prbs_test(UINT8 macro, UINT8 lane, UINT8 prbstype);
+
+int serdes_prbs_test_cancle(UINT8 macro,UINT8 lane);
+
+//CTLE/DFE
+void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane);
+
+void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane);
+
+void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane);
+
+void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane);
+
+void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane);
+//int serdes_reset(UINT32 macro);
+//int serdes_release_reset(UINT32 macro);
+void Custom_Wave(UINT32 macro,UINT32 lane,UINT32 mode);
+void serdes_ffe_show(UINT32 macro,UINT32 lane);
+void serdes_dfe_show(UINT32 macro,UINT32 lane);
+int  serdes_read_bert(UINT8 macro, UINT8 lane);
+void  serdes_clean_bert(UINT8 macro, UINT8 lane);
+int  serdes_get_four_point_eye_diagram(UINT32 macro, UINT32 lane,UINT32 eyemode, UINT32 data_rate);
+void serdes_release_mcu(UINT32 macro,UINT32 val);
+int hilink_write(UINT32 macro, UINT32 reg, UINT32 value);
+int hilink_read(UINT32 macro, UINT32 reg, UINT32 *value);
+int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);//TXRXPARLPBKEN
+int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+void serdes_ctle_show(UINT32 macro,UINT32 lane);
+int serdes_cs_write(UINT32 macro,UINT32 cs_num,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value);
+UINT32 serdes_cs_read(UINT32 macro,UINT32 cs_num,UINT32 reg_num);
+int serdes_ds_write(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value);
+int serdes_ds_read(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num);
+int report_serdes_mux(void);
+int serdes_key_reg_show(UINT32 macro);
+void serdes_state_show(UINT32 macro);
+UINT32 Serdes_ReadBert(UINT32   ulMacroId , UINT32   ulDsNum);
+
+#endif
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
new file mode 100644
index 0000000..5e8f14d
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
@@ -0,0 +1,59 @@
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.
+#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under Hisilicon/Hi1610/Hi1610AcpiTables/
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = Hi1616AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  Dsdt/DsdtHi1616.asl
+  Facs.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  MadtHi1616.aslc
+  D05Mcfg.aslc
+  D05Iort.asl
+  D05Slit.aslc
+  D05Srat.aslc
+  D05Spcr.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
new file mode 100644
index 0000000..61a3c33
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
@@ -0,0 +1,651 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength]  FieldName : HexFieldValue
+ */
+[0004]                          Signature : "IORT"    [IO Remapping Table]
+[0004]                       Table Length : 000002e4
+[0001]                           Revision : 00
+[0001]                           Checksum : BC
+[0006]                             Oem ID : "HISI  "
+[0008]                       Oem Table ID : "HIP07   "
+[0004]                       Oem Revision : 00000000
+[0004]                    Asl Compiler ID : "INTL"
+[0004]              Asl Compiler Revision : 20151124
+
+[0004]                         Node Count : 00000008
+[0004]                        Node Offset : 00000034
+[0004]                           Reserved : 00000000
+[0004]                   Optional Padding : 00 00 00 00
+
+/* ITS 0, for peri a */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000000
+//4c
+/* ITS 1, for peri b */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000001
+//64
+/* ITS 2, for dsa a */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000002
+//7c
+/* ITS 3, for dsa b */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000003
+//94
+/*Sec CPU ITS 0, for peri a */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000004
+//ac
+/* SEC CPU ITS 1, for peri b */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000005
+//c4
+/* SEC CPU ITS 2, for dsa a */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000006
+//dc
+/* SEC CPU ITS 3, for dsa b */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000007
+
+
+
+/* mbi-gen peri b, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI0"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 000120c7 //device id
+[0004]                   Output Reference : 0000004C
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen1 dsa a, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI1"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040800    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen mbi7 - RoCE named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI9"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040b1e
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen dsa a - usb named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI5"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040080    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 dsa a, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI2"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040900    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 pcie, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI3"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040000    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 pcie, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI4"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040040    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 alg a, i2c 0 named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI6"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040B0E    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 alg a, i2c 2 named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI7"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040B10    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/*1P NA PCIe2 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000002
+
+[0004]                         Input base : 00008000
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 00008000
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+/* 1P NB PCIe0 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000004
+
+[0004]                         Input base : 00008800
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 00008800
+[0004]                   Output Reference : 0000007c
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* 1P NB PCIe1 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000005
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 00000000
+[0004]                   Output Reference : 0000007c
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* 1P NB PCIe2 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000006
+
+[0004]                         Input base : 0000c000
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 0000c000
+[0004]                   Output Reference : 0000007c
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+/* 1P NB PCIe3 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000007
+
+[0004]                         Input base : 00009000
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 00009000
+[0004]                   Output Reference : 0000007c
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+/* 2P NA PCIe2*/
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 0000000a
+
+[0004]                         Input base : 00001000
+[0004]                           ID Count : 00001000
+[0004]                        Output Base : 00001000
+[0004]                   Output Reference : 000000c4
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* 2P NB PCIe0*/
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 0000000c
+
+[0004]                         Input base : 00002000
+[0004]                           ID Count : 00001000
+[0004]                        Output Base : 00002000
+[0004]                   Output Reference : 000000dc
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+ /* 2P NB PCIe1*/
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 0000000d
+
+[0004]                         Input base : 00003000
+[0004]                           ID Count : 00001000
+[0004]                        Output Base : 00003000
+[0004]                   Output Reference : 000000dc
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* mbi-gen1 P1 dsa a, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI8"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00044800  //device id
+[0004]                   Output Reference : 000000c4
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc
new file mode 100644
index 0000000..bdf42c0
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2016 Hisilicon Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ */
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1616Platform.h"
+
+#define MCFG_VERSION  0x1
+
+#pragma pack(1)
+typedef struct
+{
+   UINT64 ullBaseAddress;
+   UINT16 usSegGroupNum;
+   UINT8  ucStartBusNum;
+   UINT8  ucEndBusNum;
+   UINT32 Reserved2;
+}EFI_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+   EFI_ACPI_DESCRIPTION_HEADER Header;
+   UINT64 Reserved1;
+}EFI_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+   EFI_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+   EFI_MCFG_CONFIG_STRUCTURE Config_Structure[8];
+}EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+  {
+      {
+        EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+        sizeof (EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+        MCFG_VERSION,
+        0x00,                                                     // Checksum will be updated at runtime
+        {EFI_ACPI_ARM_OEM_ID},
+        EFI_ACPI_ARM_OEM_TABLE_ID,
+        EFI_ACPI_ARM_OEM_REVISION,
+        EFI_ACPI_ARM_CREATOR_ID,
+        EFI_ACPI_ARM_CREATOR_REVISION
+      },
+      0x0000000000000000,                                 //Reserved
+  },
+  {
+    //1p NA PCIe2
+    {
+      0xa0000000,                                         //Base Address
+      0x2,                                                //Segment Group Number
+      0x80,                                               //Start Bus Number
+      0x87,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //1p NB PCIe0
+    {
+      0x8a0000000,                                        //Base Address
+      0x4,                                                //Segment Group Number
+      0x88,                                               //Start Bus Number
+      0x8f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //1p NB PCIe1
+    {
+      0x8b0000000,                                        //Base Address
+      0x5,                                                //Segment Group Number
+      0x0,                                                //Start Bus Number
+      0x7,                                                //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //1p NB PCIe2
+    {
+      0x8a0000000,                                        //Base Address
+      0x6,                                                //Segment Group Number
+      0xc0,                                               //Start Bus Number
+      0xc7,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //1p NB PCIe3
+    {
+      0x8b0000000,                                        //Base Address
+      0x7,                                                //Segment Group Number
+      0x90,                                               //Start Bus Number
+      0x97,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //2P NA PCIe2
+    {
+      0x64000000000,                                      //Base Address
+      0xa,                                                //Segment Group Number
+      0x10,                                               //Start Bus Number
+      0x1f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //2P NB PCIe0
+    {
+      0x74000000000,                                      //Base Address
+      0xc,                                                //Segment Group Number
+      0x20,                                               //Start Bus Number
+      0x2f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //2P NB PCIe1
+    {
+      0x78000000000,                                      //Base Address
+      0xd,                                                //Segment Group Number
+      0x30,                                               //Start Bus Number
+      0x3f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc
new file mode 100644
index 0000000..89cc4a9
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2016 Linaro Limited
+ * Copyright (c) 2016 Hisilicon Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     Yi Li - yi.li@linaro.org
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1616Platform.h"
+
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004
+
+#pragma pack(1)
+typedef struct {
+  UINT8   Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+
+typedef struct {
+  EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER    Header;
+  EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE                NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+
+} EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE;
+#pragma pack()
+
+//
+// System Locality Information Table
+// Please modify all values in Slit.h only.
+//
+EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
+  {
+    {
+      EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
+      sizeof (EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE),
+      EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
+      0x00,                                                     // Checksum will be updated at runtime
+      {EFI_ACPI_ARM_OEM_ID},
+      EFI_ACPI_ARM_OEM_TABLE_ID,
+      EFI_ACPI_ARM_OEM_REVISION,
+      EFI_ACPI_ARM_CREATOR_ID,
+      EFI_ACPI_ARM_CREATOR_REVISION,
+    },
+    //
+    // Beginning of SLIT specific fields
+    //
+    EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
+  },
+  {
+    {{0x0A, 0x0F, 0x14, 0x14}}, //Locality   0
+    {{0x0F, 0x0A, 0x14, 0x14}}, //Locality   1
+    {{0x14, 0x14, 0x0A, 0x0F}}, //Locality   2
+    {{0x14, 0x14, 0x0F, 0x0A}}, //Locality   3
+  },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Slit;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc
new file mode 100644
index 0000000..e1c26c9
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc
@@ -0,0 +1,81 @@
+/** @file
+*  Serial Port Console Redirection Table (SPCR)
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016 Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include "Hi1616Platform.h"
+
+#define SPCR_FLOW_CONTROL_NONE           0
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+  ARM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+                     EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+                     EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
+  // UINT8                                   InterfaceType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+  // UINT8                                   Reserved1[3];
+  {
+    EFI_ACPI_RESERVED_BYTE,
+    EFI_ACPI_RESERVED_BYTE,
+    EFI_ACPI_RESERVED_BYTE
+  },
+  // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  BaseAddress;
+  ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)),
+  // UINT8                                   InterruptType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+  // UINT8                                   Irq;
+  0,                                         // Not used on ARM
+  // UINT32                                  GlobalSystemInterrupt;
+  807,
+  // UINT8                                   BaudRate;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+  // UINT8                                   Parity;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+  // UINT8                                   StopBits;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+  // UINT8                                   FlowControl;
+  SPCR_FLOW_CONTROL_NONE,
+  // UINT8                                   TerminalType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+  // UINT8                                   Reserved2;
+  EFI_ACPI_RESERVED_BYTE,
+  // UINT16                                  PciDeviceId;
+  0xFFFF,
+  // UINT16                                  PciVendorId;
+  0xFFFF,
+  // UINT8                                   PciBusNumber;
+  0x00,
+  // UINT8                                   PciDeviceNumber;
+  0x00,
+  // UINT8                                   PciFunctionNumber;
+  0x00,
+  // UINT32                                  PciFlags;
+  0x00000000,
+  // UINT8                                   PciSegment;
+  0x00,
+  // UINT32                                  Reserved3;
+  EFI_ACPI_RESERVED_DWORD
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
new file mode 100644
index 0000000..00c2015
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ * Copyright (c) 2016 Hisilicon Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     Yi Li - yi.li@linaro.org
+ *
+ *  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/AcpiNextLib.h>
+#include "Hi1616Platform.h"
+
+
+//
+// Static Resource Affinity Table definition
+//
+EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
+  {
+    {EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+    sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE),
+    EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
+    0x00,                                                     // Checksum will be updated at runtime
+    {EFI_ACPI_ARM_OEM_ID},
+    EFI_ACPI_ARM_OEM_TABLE_ID,
+    EFI_ACPI_ARM_OEM_REVISION,
+    EFI_ACPI_ARM_CREATOR_ID,
+    EFI_ACPI_ARM_CREATOR_REVISION},
+    /*Reserved*/
+    0x00000001,                                  // Reserved to be 1 for backward compatibility
+    EFI_ACPI_RESERVED_QWORD
+  },
+
+  //
+  //
+  // Memory Affinity
+  //
+  {
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+  },
+
+  {
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000),   //GICC Affinity Processor 0
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000),   //GICC Affinity Processor 1
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000),   //GICC Affinity Processor 2
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000),   //GICC Affinity Processor 3
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000),   //GICC Affinity Processor 4
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000),   //GICC Affinity Processor 5
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000),   //GICC Affinity Processor 6
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000),   //GICC Affinity Processor 7
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000),   //GICC Affinity Processor 8
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000),   //GICC Affinity Processor 9
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000),   //GICC Affinity Processor 10
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000),   //GICC Affinity Processor 11
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000),   //GICC Affinity Processor 12
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000),   //GICC Affinity Processor 13
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000),   //GICC Affinity Processor 14
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000),   //GICC Affinity Processor 15
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000),   //GICC Affinity Processor 16
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000),   //GICC Affinity Processor 17
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000),   //GICC Affinity Processor 18
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000),   //GICC Affinity Processor 19
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000),   //GICC Affinity Processor 20
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000),   //GICC Affinity Processor 21
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000),   //GICC Affinity Processor 22
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000),   //GICC Affinity Processor 23
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000),   //GICC Affinity Processor 24
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000),   //GICC Affinity Processor 25
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000),   //GICC Affinity Processor 26
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000),   //GICC Affinity Processor 27
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000),   //GICC Affinity Processor 28
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000),   //GICC Affinity Processor 29
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000),   //GICC Affinity Processor 30
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000),   //GICC Affinity Processor 31
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000),   //GICC Affinity Processor 32
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000),   //GICC Affinity Processor 33
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000),   //GICC Affinity Processor 34
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000),   //GICC Affinity Processor 35
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000),   //GICC Affinity Processor 36
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000),   //GICC Affinity Processor 37
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000),   //GICC Affinity Processor 38
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000),   //GICC Affinity Processor 39
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000),   //GICC Affinity Processor 40
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000),   //GICC Affinity Processor 41
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000),   //GICC Affinity Processor 42
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000),   //GICC Affinity Processor 43
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000),   //GICC Affinity Processor 44
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000),   //GICC Affinity Processor 45
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000),   //GICC Affinity Processor 46
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000),   //GICC Affinity Processor 47
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000),   //GICC Affinity Processor 48
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000),   //GICC Affinity Processor 49
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000),   //GICC Affinity Processor 50
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000),   //GICC Affinity Processor 51
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000),   //GICC Affinity Processor 52
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000),   //GICC Affinity Processor 53
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000),   //GICC Affinity Processor 54
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000),   //GICC Affinity Processor 55
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000),   //GICC Affinity Processor 56
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000),   //GICC Affinity Processor 57
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000),   //GICC Affinity Processor 58
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000),   //GICC Affinity Processor 59
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000),   //GICC Affinity Processor 60
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000),   //GICC Affinity Processor 61
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000),   //GICC Affinity Processor 62
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000)    //GICC Affinity Processor 63
+  },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Srat;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl
new file mode 100644
index 0000000..5ecbf50
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl
@@ -0,0 +1,280 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+  //
+  // A57x16 Processor declaration
+  //
+  Device(CPU0) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 0)
+  }
+  Device(CPU1) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 1)
+  }
+  Device(CPU2) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 2)
+  }
+  Device(CPU3) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 3)
+  }
+  Device(CPU4) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 4)
+  }
+  Device(CPU5) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 5)
+  }
+  Device(CPU6) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 6)
+  }
+  Device(CPU7) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 7)
+  }
+  Device(CPU8) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 8)
+  }
+  Device(CPU9) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 9)
+  }
+  Device(CP10) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 10)
+  }
+  Device(CP11) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 11)
+  }
+  Device(CP12) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 12)
+  }
+  Device(CP13) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 13)
+  }
+  Device(CP14) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 14)
+  }
+  Device(CP15) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 15)
+  }
+  Device(CP16) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 16)
+  }
+  Device(CP17) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 17)
+  }
+  Device(CP18) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 18)
+  }
+  Device(CP19) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 19)
+  }
+  Device(CP20) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 20)
+  }
+  Device(CP21) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 21)
+  }
+  Device(CP22) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 22)
+  }
+  Device(CP23) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 23)
+  }
+  Device(CP24) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 24)
+  }
+  Device(CP25) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 25)
+  }
+  Device(CP26) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 26)
+  }
+  Device(CP27) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 27)
+  }
+  Device(CP28) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 28)
+  }
+  Device(CP29) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 29)
+  }
+  Device(CP30) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 30)
+  }
+  Device(CP31) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 31)
+  }
+  Device(CP32) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 32)
+  }
+  Device(CP33) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 33)
+  }
+  Device(CP34) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 34)
+  }
+  Device(CP35) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 35)
+  }
+  Device(CP36) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 36)
+  }
+  Device(CP37) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 37)
+  }
+  Device(CP38) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 38)
+  }
+  Device(CP39) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 39)
+  }
+  Device(CP40) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 40)
+  }
+  Device(CP41) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 41)
+  }
+  Device(CP42) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 42)
+  }
+  Device(CP43) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 43)
+  }
+  Device(CP44) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 44)
+  }
+  Device(CP45) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 45)
+  }
+  Device(CP46) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 46)
+  }
+  Device(CP47) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 47)
+  }
+  Device(CP48) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 48)
+  }
+  Device(CP49) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 49)
+  }
+  Device(CP50) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 50)
+  }
+  Device(CP51) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 51)
+  }
+  Device(CP52) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 52)
+  }
+  Device(CP53) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 53)
+  }
+  Device(CP54) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 54)
+  }
+  Device(CP55) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 55)
+  }
+  Device(CP56) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 56)
+  }
+  Device(CP57) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 57)
+  }
+  Device(CP58) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 58)
+  }
+  Device(CP59) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 59)
+  }
+  Device(CP60) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 60)
+  }
+  Device(CP61) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 61)
+  }
+  Device(CP62) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 62)
+  }
+  Device(CP63) {
+    Name(_HID, "ACPI0007")
+    Name(_UID, 63)
+  }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl
new file mode 100644
index 0000000..f0169ce
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl
@@ -0,0 +1,28 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  Device(COM0) {
+    Name(_HID, "ARMH0011")
+    Name(_CID, "PL011")
+    Name(_UID, Zero)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x602B0000, 0x1000)
+      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 807 }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
new file mode 100644
index 0000000..11c28ba
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
@@ -0,0 +1,1272 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  Device (MDIO)
+  {
+    OperationRegion(CLKR, SystemMemory, 0x60000550, 8)
+    Field(CLKR, DWordAcc, NoLock, Preserve) {
+      CLKE, 1,  // clock enable
+      , 31,
+      CLKD, 1,  // clode disable
+      , 31,
+    }
+    OperationRegion(RSTR, SystemMemory, 0x60000c40, 8)
+    Field(RSTR, DWordAcc, NoLock, Preserve) {
+      RSTE, 1,  // reset
+      , 31,
+      RSTD, 1,  // de-reset
+      , 31,
+    }
+
+    Name(_HID, "HISI0141")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)
+    })
+
+    Method(_RST, 0, Serialized) {
+      Store (0x1, RSTE)
+      Sleep (10)
+      Store (0x1, CLKD)
+      Sleep (10)
+      Store (0x1, RSTD)
+      Sleep (10)
+      Store (0x1, CLKE)
+      Sleep (10)
+    }
+  }
+
+  Device (DSF0)
+  {
+    OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
+    Field(H3SR, DWordAcc, NoLock, Preserve) {
+      H3ST, 1,
+      , 31,  //RESERVED
+    }
+    OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
+    Field(H4SR, DWordAcc, NoLock, Preserve) {
+      H4ST, 1,
+      , 31,  //RESERVED
+    }
+    // DSAF RESET
+    OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
+    Field(DRER, DWordAcc, NoLock, Preserve) {
+      DRTE, 1,
+      , 31,  //RESERVED
+      DRTD, 1,
+      , 31,  //RESERVED
+    }
+    // NT RESET
+    OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
+    Field(NRER, DWordAcc, NoLock, Preserve) {
+      NRTE, 1,
+      , 31,  //RESERVED
+      NRTD, 1,
+      , 31,  //RESERVED
+    }
+    // XGE RESET
+    OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+    Field(XRER, DWordAcc, NoLock, Preserve) {
+      XRTE, 31,
+      , 1,    //RESERVED
+      XRTD, 31,
+      , 1,    //RESERVED
+    }
+
+    // GE RESET
+    OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+    Field(GRTR, DWordAcc, NoLock, Preserve) {
+      GR0E, 30,
+      , 2,    //RESERVED
+      GR0D, 30,
+      , 2,    //RESERVED
+      GR1E, 18,
+      , 14,  //RESERVED
+      GR1D, 18,
+      , 14,  //RESERVED
+    }
+    // PPE RESET
+    OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+    Field(PRTR, DWordAcc, NoLock, Preserve) {
+      PRTE, 10,
+      , 22,  //RESERVED
+      PRTD, 10,
+      , 22,  //RESERVED
+    }
+
+    // RCB PPE COM RESET
+    OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
+    Field(RRTR, DWordAcc, NoLock, Preserve) {
+      RRTE, 1,
+      , 31,  //RESERVED
+      RRTD, 1,
+      , 31,  //RESERVED
+    }
+
+    // DSAF Channel RESET
+    OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8)
+    Field(DCRR, DWordAcc, NoLock, Preserve) {
+      DCRE, 1,
+      , 31,  //RESERVED
+      DCRD, 1,
+      , 31,  //RESERVED
+    }
+
+    // RoCE RESET
+    OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8)
+    Field(RKRR, DWordAcc, NoLock, Preserve) {
+      RKRE, 1,
+      , 31,  //RESERVED
+      RKRD, 1,
+      , 31,  //RESERVED
+    }
+
+    // RoCE Clock enable/disable
+    OperationRegion(RKCR, SystemMemory, 0xC0000328, 8)
+    Field(RKCR, DWordAcc, NoLock, Preserve) {
+      RCLE, 1,
+      , 31,  //RESERVED
+      RCLD, 1,
+      , 31,  //RESERVED
+    }
+
+    // Hilink access sel cfg reg
+    OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
+    Field(HSER, DWordAcc, NoLock, Preserve) {
+      HSEL, 2,  // hilink_access_sel & hilink_access_wr_pul
+      , 30,    // RESERVED
+    }
+
+    // Serdes
+    OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
+    Field(H4LR, DWordAcc, NoLock, Preserve) {
+      H4L0, 16,    // port0
+      , 16,    //RESERVED
+      Offset (0x400),
+      H4L1, 16,    // port1
+      , 16,    //RESERVED
+      Offset (0x800),
+      H4L2, 16,    // port2
+      , 16,    //RESERVED
+      Offset (0xc00),
+      H4L3, 16,    // port3
+      , 16,    //RESERVED
+    }
+    OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
+    Field(H3LR, DWordAcc, NoLock, Preserve) {
+      H3L2, 16,    // port4
+      , 16,    //RESERVED
+      Offset (0x400),
+      H3L3, 16,    // port5
+      , 16,    //RESERVED
+    }
+    OperationRegion(HSFP, SystemMemory, 0x78000010, 0x100)
+    Field(HSFP, ByteAcc, NoLock, Preserve) {
+      Offset (0x2),
+      HSF0, 1,  // port0
+      , 7,    //RESERVED
+      Offset (0x6),
+      HSF1, 1,    // port1
+      , 7,    //RESERVED
+    }
+    Name (_HID, "HISI00B2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_CRS, ResourceTemplate (){
+      Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
+      Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+      {
+        576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+        589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+      }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+      {
+        960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+        976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+        992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+        1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+        1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+        1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+        1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+        1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+        1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+        1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+        1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+        1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+      }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+      {
+        1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+        1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+        1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+        1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+        1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+        1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+        1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+        1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+        1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+        1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+        1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+        1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+      }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"mode", "6port-16rss"},
+        Package () {"buf-size", 4096},
+        Package () {"desc-num", 1024},
+      }
+    })
+
+    //reset XGE port
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XRST, 2, Serialized) {
+      ShiftLeft (0x2082082, Arg0, Local0)
+      Or (Local0, 0x1, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset XGE core
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XCRT, 2, Serialized) {
+      ShiftLeft (0x2080, Arg0, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset GE port
+    //Arg0 : GE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(GRST, 2, Serialized) {
+      If (LLessEqual (Arg0, 5)) {
+        //Service port
+        ShiftLeft (0x2082082, Arg0, Local0)
+        ShiftLeft (0x1, Arg0, Local1)
+
+        If (LEqual (Arg1, 0)) {
+          Store(Local1, GR1E)
+          Store(Local0, GR0E)
+        } Else  {
+          Store(Local0, GR0D)
+          Store(Local1, GR1D)
+        }
+      }
+    }
+
+    //reset PPE port
+    //Arg0 : PPE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(PRST, 2, Serialized) {
+      ShiftLeft (0x1, Arg0, Local0)
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, PRTE)
+      } Else  {
+        Store(Local0, PRTD)
+      }
+    }
+
+    //reset DSAF channels
+    //Arg0 : mask
+    //Arg1 : 0 reset, 1 de-reset
+    Method(DCRT, 2, Serialized) {
+      If (LEqual (Arg1, 0)) {
+        Store(Arg0, DCRE)
+      } Else  {
+        Store(Arg0, DCRD)
+      }
+    }
+
+    //reset RoCE
+    //Arg0 : 0 reset, 1 de-reset
+    Method(RRST, 1, Serialized) {
+      If (LEqual (Arg0, 0)) {
+        Store(0x1, RKRE)
+      } Else  {
+        Store(0x1, RCLD)
+        Store(0x1, RKRD)
+        sleep(20)
+        Store(0x1, RCLE)
+      }
+    }
+
+    // Set Serdes Loopback
+    //Arg0 : port
+    //Arg1 : 0 disable, 1 enable
+    Method(SRLP, 2, Serialized) {
+      ShiftLeft (Arg1, 10, Local0)
+      Switch (ToInteger(Arg0))
+      {
+        case (0x0){
+          Store (0, HSEL)
+          Store (H4L0, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L0)
+        }
+        case (0x1){
+          Store (0, HSEL)
+          Store (H4L1, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L1)
+        }
+        case (0x2){
+          Store (0, HSEL)
+          Store (H4L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L2)
+        }
+        case (0x3){
+          Store (0, HSEL)
+          Store (H4L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L3)
+        }
+        case (0x4){
+          Store (3, HSEL)
+          Store (H3L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L2)
+        }
+        case (0x5){
+          Store (3, HSEL)
+          Store (H3L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L3)
+        }
+      }
+    }
+
+    //Reset
+    //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:ge; 6:dchan; 7:RoCE)
+    //Arg1 : port
+    //Arg2 : 0 disable, 1 enable
+    Method(DRST, 3, Serialized)
+    {
+      Switch (ToInteger(Arg0))
+      {
+        //DSAF reset
+        case (0x1)
+        {
+          Store (Arg2, Local0)
+          If (LEqual (Local0, 0))
+          {
+            Store (0x1, DRTE)
+            Store (0x1, NRTE)
+            Sleep (10)
+            Store (0x1, RRTE)
+          }
+          Else
+          {
+            Store (0x1, DRTD)
+            Store (0x1, NRTD)
+            Sleep (10)
+            Store (0x1, RRTD)
+          }
+        }
+        //Reset PPE port
+        case (0x2)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          PRST (Local0, Local1)
+        }
+
+        //Reset XGE core
+        case (0x3)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XCRT (Local0, Local1)
+        }
+        //Reset XGE port
+        case (0x4)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XRST (Local0, Local1)
+        }
+
+        //Reset GE port
+        case (0x5)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          GRST (Local0, Local1)
+        }
+
+        //Reset DSAF Channels
+        case (0x6)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          DCRT (Local0, Local1)
+        }
+
+        //Reset RoCE
+        case (0x7)
+        {
+          // Discarding Arg1 as it is always 0
+          Store (Arg2, Local0)
+          RRST (Local0)
+        }
+      }
+    }
+
+    // _DSM Device Specific Method
+    //
+    // Arg0: UUID Unique function identifier
+    // Arg1: Integer Revision Level
+    // Arg2: Integer Function Index
+    //   0 : Return Supported Functions bit mask
+    //   1 : Reset Sequence
+    //    Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge; 6:dchan; 7:RoCE)
+    //    Arg3[1] : port index in dsaf
+    //    Arg3[2] : 0 reset, 1 cancle reset
+    //   2 : Set Serdes Loopback
+    //    Arg3[0] : port
+    //    Arg3[1] : 0 disable, 1 enable
+    //   3 : LED op set
+    //    Arg3[0] : op type
+    //    Arg3[1] : port
+    //    Arg3[2] : para
+    //   4 : Get port type (GE or XGE)
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 GE, 1 XGE
+    //   5 : Get sfp status
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 no sfp, 1 have sfp
+    // Arg3: Package Parameters
+    Method (_DSM, 4, Serialized)
+    {
+      If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+      {
+        If (LEqual (Arg1, 0x00))
+        {
+          Switch (ToInteger(Arg2))
+          {
+            case (0x0)
+            {
+              Return (Buffer () {0x3F})
+            }
+
+            //Reset Sequence
+            case (0x1)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              Store (DeRefOf (Index (Arg3, 2)), Local2)
+              DRST (Local0, Local1, Local2)
+            }
+
+            //Set Serdes Loopback
+            case (0x2)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              SRLP (Local0, Local1)
+            }
+
+            //LED op set
+            case (0x3)
+            {
+
+            }
+
+            // Get port type (GE or XGE)
+            case (0x4)
+            {
+              Store (0, Local1)
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              If (LLessEqual (Local0, 3))
+              {
+                // mac0: Hilink4 Lane0
+                // mac1: Hilink4 Lane1
+                // mac2: Hilink4 Lane2
+                // mac3: Hilink4 Lane3
+                Store (H4ST, Local1)
+              }
+              ElseIf (LLessEqual (Local0, 5))
+              {
+                // mac4: Hilink3 Lane2
+                // mac5: Hilink3 Lane3
+                Store (H3ST, Local1)
+              }
+
+              Return (Local1)
+            }
+
+            //Get sfp status
+            case (0x5)
+            {
+              Store (1, Local1) //set no sfp default
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              If (LEqual (Local0, 0))
+              {
+                // port 0:
+                Store (HSF0, Local1)
+              }
+              ElseIf (LEqual (Local0, 1))
+              {
+                // port 1
+                Store (HSF1, Local1)
+              }
+
+              XOr (Local1, 1, local1)
+              Return (Local1)
+            }
+          }
+        }
+      }
+      Return (Buffer() {0x00})
+    }
+    Device (PRT0)
+    {
+      Name (_ADR, 0x0)
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 0},
+          Package () {"media-type", "fiber"},
+        }
+      })
+    }
+    Device (PRT1)
+    {
+      Name (_ADR, 0x1)
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 1},
+          Package () {"media-type", "fiber"},
+        }
+      })
+    }
+
+    Device (PRT2)
+    {
+      Name (_ADR, 0x2)
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 2},
+          Package () {"media-type", "fiber"},
+        }
+      })
+    }
+    Device (PRT3)
+    {
+      Name (_ADR, 0x3)
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 3},
+          Package () {"media-type", "fiber"},
+        }
+      })
+    }
+
+    Device (PRT4)
+    {
+      Name (_ADR, 0x4)
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 4},
+                          Package () {"phy-mode", "sgmii"},
+          Package () {"phy-addr", 0},
+          Package () {"mdio-node", Package (){\_SB.MDIO}},
+          Package () {"media-type", "copper"},
+        }
+      })
+    }
+    Device (PRT5)
+    {
+      Name (_ADR, 0x5)
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 5},
+          Package () {"phy-mode", "sgmii"},
+          Package () {"phy-addr", 1},
+          Package () {"mdio-node", Package (){\_SB.MDIO}},
+          Package () {"media-type", "copper"},
+        }
+      })
+    }
+  }
+  Device (ETH4) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 4},
+      }
+    })
+  }
+  Device (ETH5) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 5},
+      }
+    })
+  }
+  Device (ETH0) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 0},
+      }
+    })
+  }
+  Device (ETH1) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 1},
+      }
+    })
+  }
+
+  Device (ETH2) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 2},
+      }
+    })
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0)
+    }
+  }
+  Device (ETH3) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 3},
+      }
+    })
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0)
+    }
+  }
+
+  Device (ROCE) {
+    Name(_HID, "HISI00D1")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}},
+        Package () {"dsaf-handle", Package (){\_SB.DSF0}},
+        Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes
+        Package () {"interrupt-names", Package() {"hns-roce-comp-0",
+                                                  "hns-roce-comp-1",
+                                                  "hns-roce-comp-2",
+                                                  "hns-roce-comp-3",
+                                                  "hns-roce-comp-4",
+                                                  "hns-roce-comp-5",
+                                                  "hns-roce-comp-6",
+                                                  "hns-roce-comp-7",
+                                                  "hns-roce-comp-8",
+                                                  "hns-roce-comp-9",
+                                                  "hns-roce-comp-10",
+                                                  "hns-roce-comp-11",
+                                                  "hns-roce-comp-12",
+                                                  "hns-roce-comp-13",
+                                                  "hns-roce-comp-14",
+                                                  "hns-roce-comp-15",
+                                                  "hns-roce-comp-16",
+                                                  "hns-roce-comp-17",
+                                                  "hns-roce-comp-18",
+                                                  "hns-roce-comp-19",
+                                                  "hns-roce-comp-20",
+                                                  "hns-roce-comp-21",
+                                                  "hns-roce-comp-22",
+                                                  "hns-roce-comp-23",
+                                                  "hns-roce-comp-24",
+                                                  "hns-roce-comp-25",
+                                                  "hns-roce-comp-26",
+                                                  "hns-roce-comp-27",
+                                                  "hns-roce-comp-28",
+                                                  "hns-roce-comp-29",
+                                                  "hns-roce-comp-30",
+                                                  "hns-roce-comp-31",
+                                                  "hns-roce-async",
+                                                  "hns-roce-common"}},
+      }
+    })
+    Name (_CRS, ResourceTemplate (){
+      Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000)
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI9")
+      {
+        722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+        734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+        746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+      }
+    })
+  }
+
+  /* for p1 */
+  Device (DSF1)
+  {
+
+    OperationRegion(H3SR, SystemMemory, 0x400C0000184, 4)
+    Field(H3SR, DWordAcc, NoLock, Preserve) {
+      H3ST, 1,
+      , 31,  //RESERVED
+    }
+    OperationRegion(H4SR, SystemMemory, 0x400C0000194, 4)
+    Field(H4SR, DWordAcc, NoLock, Preserve) {
+      H4ST, 1,
+      , 31,  //RESERVED
+    }
+    // DSAF RESET
+    OperationRegion(DRER, SystemMemory, 0x400C0000A00, 8)
+    Field(DRER, DWordAcc, NoLock, Preserve) {
+      DRTE, 1,
+      , 31,  //RESERVED
+      DRTD, 1,
+      , 31,  //RESERVED
+    }
+    // NT RESET
+    OperationRegion(NRER, SystemMemory, 0x400C0000A08, 8)
+    Field(NRER, DWordAcc, NoLock, Preserve) {
+      NRTE, 1,
+      , 31,  //RESERVED
+      NRTD, 1,
+      , 31,  //RESERVED
+    }
+    // XGE RESET
+    OperationRegion(XRER, SystemMemory, 0x400C0000A10, 8)
+    Field(XRER, DWordAcc, NoLock, Preserve) {
+      XRTE, 31,
+      , 1,    //RESERVED
+      XRTD, 31,
+      , 1,    //RESERVED
+    }
+
+    // GE RESET
+    OperationRegion(GRTR, SystemMemory, 0x400C0000A18, 16)
+    Field(GRTR, DWordAcc, NoLock, Preserve) {
+      GR0E, 30,
+      , 2,    //RESERVED
+      GR0D, 30,
+      , 2,    //RESERVED
+      GR1E, 18,
+      , 14,  //RESERVED
+      GR1D, 18,
+      , 14,  //RESERVED
+    }
+    // PPE RESET
+    OperationRegion(PRTR, SystemMemory, 0x400C0000A48, 8)
+    Field(PRTR, DWordAcc, NoLock, Preserve) {
+      PRTE, 10,
+      , 22,  //RESERVED
+      PRTD, 10,
+      , 22,  //RESERVED
+    }
+
+    // RCB PPE COM RESET
+    OperationRegion(RRTR, SystemMemory, 0x400C0000A88, 8)
+    Field(RRTR, DWordAcc, NoLock, Preserve) {
+      RRTE, 1,
+      , 31,  //RESERVED
+      RRTD, 1,
+      , 31,  //RESERVED
+    }
+
+    // RCB_2X COM RESET
+    OperationRegion(RBTR, SystemMemory, 0x400C0000AC0, 8)
+    Field(RBTR, DWordAcc, NoLock, Preserve) {
+      RBTE, 1,
+      , 31,  //RESERVED
+      RBTD, 1,
+      , 31,  //RESERVED
+    }
+
+    // Hilink access sel cfg reg
+    OperationRegion(HSER, SystemMemory, 0x400C2240008, 0x4)
+    Field(HSER, DWordAcc, NoLock, Preserve) {
+      HSEL, 2,  // hilink_access_sel & hilink_access_wr_pul
+      , 30,    // RESERVED
+    }
+
+    // Serdes
+    OperationRegion(H4LR, SystemMemory, 0x400C2208100, 0x1000)
+    Field(H4LR, DWordAcc, NoLock, Preserve) {
+      H4L0, 16,    // port0
+      , 16,    //RESERVED
+      Offset (0x400),
+      H4L1, 16,    // port1
+      , 16,    //RESERVED
+      Offset (0x800),
+      H4L2, 16,    // port2
+      , 16,    //RESERVED
+      Offset (0xc00),
+      H4L3, 16,    // port3
+      , 16,    //RESERVED
+    }
+    OperationRegion(H3LR, SystemMemory, 0x400C2208900, 0x800)
+    Field(H3LR, DWordAcc, NoLock, Preserve) {
+      H3L2, 16,    // port4
+      , 16,    //RESERVED
+      Offset (0x400),
+      H3L3, 16,    // port5
+      , 16,    //RESERVED
+    }
+
+    Name (_HID, "HISI00B2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_CRS, ResourceTemplate (){
+      QwordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x400c5000000, // Min Base Address
+        0x400c588ffff, // Max Base Address
+        0x0, // Translate
+        0x890000 // Length
+      )
+      QwordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x400c7000000, // Min Base Address
+        0x400c705ffff, // Max Base Address
+        0x0, // Translate
+        0x60000 // Length
+      )
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+      {
+        576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+        589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+      }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+      {
+        960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+        976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+        992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+        1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+        1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+        1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+        1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+        1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+        1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+        1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+        1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+        1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+      }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+      {
+        1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+        1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+        1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+        1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+        1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+        1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+        1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+        1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+        1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+        1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+        1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+        1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+      }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"mode", "6port-16rss"},
+        Package () {"buf-size", 4096},
+        Package () {"desc-num", 1024},
+      }
+    })
+
+    //reset XGE port
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XRST, 2, Serialized) {
+      ShiftLeft (0x2082082, Arg0, Local0)
+      Or (Local0, 0x1, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset XGE core
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XCRT, 2, Serialized) {
+      ShiftLeft (0x2080, Arg0, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset GE port
+    //Arg0 : GE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(GRST, 2, Serialized) {
+      If (LLessEqual (Arg0, 5)) {
+        //Service port
+        ShiftLeft (0x2082082, Arg0, Local0)
+        ShiftLeft (0x1, Arg0, Local1)
+
+        If (LEqual (Arg1, 0)) {
+          Store(Local1, GR1E)
+          Store(Local0, GR0E)
+        } Else  {
+          Store(Local0, GR0D)
+          Store(Local1, GR1D)
+        }
+      }
+    }
+
+    //reset PPE port
+    //Arg0 : PPE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(PRST, 2, Serialized) {
+      ShiftLeft (0x1, Arg0, Local0)
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, PRTE)
+      } Else  {
+        Store(Local0, PRTD)
+      }
+    }
+
+    // Set Serdes Loopback
+    //Arg0 : port
+    //Arg1 : 0 disable, 1 enable
+    Method(SRLP, 2, Serialized) {
+      ShiftLeft (Arg1, 10, Local0)
+      Switch (ToInteger(Arg0))
+      {
+        case (0x0){
+          Store (0, HSEL)
+          Store (H4L0, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L0)
+        }
+        case (0x1){
+          Store (0, HSEL)
+          Store (H4L1, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L1)
+        }
+        case (0x2){
+          Store (0, HSEL)
+          Store (H4L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L2)
+        }
+        case (0x3){
+          Store (0, HSEL)
+          Store (H4L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L3)
+        }
+        case (0x4){
+          Store (3, HSEL)
+          Store (H3L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L2)
+        }
+        case (0x5){
+          Store (3, HSEL)
+          Store (H3L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L3)
+        }
+      }
+    }
+
+    //Reset
+    //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
+    //Arg1 : port
+    //Arg2 : 0 disable, 1 enable
+    Method(DRST, 3, Serialized)
+    {
+      Switch (ToInteger(Arg0))
+      {
+        //DSAF reset
+        case (0x1)
+        {
+          Store (Arg2, Local0)
+          If (LEqual (Local0, 0))
+          {
+            Store (0x1, DRTE)
+            Store (0x1, NRTE)
+            Sleep (10)
+            Store (0x1, RRTE)
+            Store (0x1, RBTE)
+          }
+          Else
+          {
+            Store (0x1, DRTD)
+            Store (0x1, NRTD)
+            Sleep (10)
+            Store (0x1, RRTD)
+            Store (0x1, RBTD)
+          }
+        }
+        //Reset PPE port
+        case (0x2)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          PRST (Local0, Local1)
+        }
+
+        //Reset XGE core
+        case (0x3)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XCRT (Local0, Local1)
+        }
+        //Reset XGE port
+        case (0x4)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XRST (Local0, Local1)
+        }
+
+        //Reset GE port
+        case (0x5)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          GRST (Local0, Local1)
+        }
+      }
+    }
+
+    // _DSM Device Specific Method
+    //
+    // Arg0: UUID Unique function identifier
+    // Arg1: Integer Revision Level
+    // Arg2: Integer Function Index
+    //   0 : Return Supported Functions bit mask
+    //   1 : Reset Sequence
+    //    Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
+    //    Arg3[1] : port index in dsaf
+    //    Arg3[2] : 0 reset, 1 cancle reset
+    //   2 : Set Serdes Loopback
+    //    Arg3[0] : port
+    //    Arg3[1] : 0 disable, 1 enable
+    //   3 : LED op set
+    //    Arg3[0] : op type
+    //    Arg3[1] : port
+    //    Arg3[2] : para
+    //   4 : Get port type (GE or XGE)
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 GE, 1 XGE
+    //   5 : Get sfp status
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 no sfp, 1 have sfp
+    // Arg3: Package Parameters
+    Method (_DSM, 4, Serialized)
+    {
+      If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+      {
+        If (LEqual (Arg1, 0x00))
+        {
+          Switch (ToInteger(Arg2))
+          {
+            case (0x0)
+            {
+              Return (Buffer () {0x3F})
+            }
+
+            //Reset Sequence
+            case (0x1)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              Store (DeRefOf (Index (Arg3, 2)), Local2)
+              DRST (Local0, Local1, Local2)
+            }
+
+            //Set Serdes Loopback
+            case (0x2)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              SRLP (Local0, Local1)
+            }
+
+            //LED op set
+            case (0x3)
+            {
+
+            }
+
+            // Get port type (GE or XGE)
+            case (0x4)
+            {
+              Store (0, Local1)
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              If (LLessEqual (Local0, 3))
+              {
+                // mac0: Hilink4 Lane0
+                // mac1: Hilink4 Lane1
+                // mac2: Hilink4 Lane2
+                // mac3: Hilink4 Lane3
+                Store (H4ST, Local1)
+              }
+              ElseIf (LLessEqual (Local0, 5))
+              {
+                // mac4: Hilink3 Lane2
+                // mac5: Hilink3 Lane3
+                Store (H3ST, Local1)
+              }
+
+              Return (Local1)
+            }
+
+            //Get sfp status
+            case (0x5)
+            {
+
+            }
+          }
+        }
+      }
+      Return (Buffer() {0x00})
+    }
+
+    Device (PRT6)
+    {
+      Name (_ADR, 0x6)
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 0},
+          Package () {"media-type", "fiber"},
+        }
+      })
+    }
+    Device (PRT7)
+    {
+      Name (_ADR, 0x7)
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 1},
+          Package () {"media-type", "fiber"},
+        }
+      })
+    }
+  }
+
+  Device (ETH6) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF1}},
+        Package () {"port-idx-in-ae", 0},
+      }
+    })
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0)
+    }
+  }
+  Device (ETH7) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF1}},
+        Package () {"port-idx-in-ae", 1},
+      }
+    })
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0)
+    }
+  }
+
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl
new file mode 100644
index 0000000..eb906ef
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl
@@ -0,0 +1,56 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+  Device(I2C0) {
+    Name(_HID, "APMC0D0F")
+    Name(_CID, "APMC0D0F")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000)
+      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") { 705 }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"clock-frequency", 100000},
+        Package () {"i2c-sda-falling-time-ns", 913},
+        Package () {"i2c-scl-falling-time-ns", 303},
+        Package () {"i2c-sda-hold-time-ns", 0x9c2},
+      }
+    })
+  }
+
+  Device(I2C2) {
+    Name(_HID, "APMC0D0F")
+    Name(_CID, "APMC0D0F")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xd0100000, 0x10000)
+      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") { 707 }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"clock-frequency", 100000},
+        Package () {"i2c-sda-falling-time-ns", 913},
+        Package () {"i2c-scl-falling-time-ns", 303},
+        Package () {"i2c-sda-hold-time-ns", 0x9c2},
+      }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl
new file mode 100644
index 0000000..9ee9d83
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl
@@ -0,0 +1,438 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  // Mbi-gen peri b intc
+  Device(MBI0) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x60080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) { 807 }
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 1}
+      }
+    })
+  }
+
+  Device(MBI1) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+      {
+        576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+        589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+      }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+      {
+        960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+        976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+        992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+        1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+        1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+        1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+        1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+        1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+        1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+        1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+        1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+        1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+      }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+      {
+        1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+        1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+        1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+        1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+        1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+        1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+        1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+        1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+        1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+        1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+        1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+        1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+      }
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 409}
+      }
+    })
+  }
+
+  // Mbi-gen sas0
+  Device(MBI2) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+      {
+        64,65,66,67,68,
+        69,70,71,72,73,
+        74,75,76,77,78,
+        79,80,81,82,83,
+        84,85,86,87,88,
+        89,90,91,92,93,
+        94,95,96,97,98,
+        99,100,101,102,103,
+        104,105,106,107,108,
+        109,110,111,112,113,
+        114,115,116,117,118,
+        119,120,121,122,123,
+        124,125,126,127,128,
+        129,130,131,132,133,
+        134,135,136,137,138,
+        139,140,141,142,143,
+        144,145,146,147,148,
+        149,150,151,152,153,
+        154,155,156,157,158,
+        159,
+      }
+
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,)
+      {
+        601,602,603,604,
+        605,606,607,608,609,
+        610,611,612,613,614,
+        615,616,617,618,619,
+        620,621,622,623,624,
+        625,626,627,628,629,
+        630,631,632,
+      }
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 128}
+      }
+    })
+  }
+
+  Device(MBI3) {          // Mbi-gen sas1 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+      {
+        64,65,66,67,68,
+        69,70,71,72,73,
+        74,75,76,77,78,
+        79,80,81,82,83,
+        84,85,86,87,88,
+        89,90,91,92,93,
+        94,95,96,97,98,
+        99,100,101,102,103,
+        104,105,106,107,108,
+        109,110,111,112,113,
+        114,115,116,117,118,
+        119,120,121,122,123,
+        124,125,126,127,128,
+        129,130,131,132,133,
+        134,135,136,137,138,
+        139,140,141,142,143,
+        144,145,146,147,148,
+        149,150,151,152,153,
+        154,155,156,157,158,
+        159,
+      }
+
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+      {
+        576,577,578,579,580,
+        581,582,583,584,585,
+        586,587,588,589,590,
+        591,592,593,594,595,
+        596,597,598,599,600,
+        601,602,603,604,605,
+        606,607,
+      }
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 128}
+      }
+    })
+  }
+  Device(MBI4) {          // Mbi-gen sas2 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+      {
+        192,193,194,195,196,
+        197,198,199,200,201,
+        202,203,204,205,206,
+        207,208,209,210,211,
+        212,213,214,215,216,
+        217,218,219,220,221,
+        222,223,224,225,226,
+        227,228,229,230,231,
+        232,233,234,235,236,
+        237,238,239,240,241,
+        242,243,244,245,246,
+        247,248,249,250,251,
+        252,253,254,255,256,
+        257,258,259,260,261,
+        262,263,264,265,266,
+        267,268,269,270,271,
+        272,273,274,275,276,
+        277,278,279,280,281,
+        282,283,284,285,286,
+        287,
+      }
+
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+      {
+        608,609,610,611,
+        612,613,614,615,616,
+        617,618,619,620,621,
+        622,623,624,625,626,
+        627,628,629,630,631,
+        632,633,634,635,636,
+        637,638,639,
+      }
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 128}
+      }
+    })
+  }
+
+  Device(MBI5) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) {640,641,}
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 2}
+      }
+    })
+  }
+
+  Device(MBI6) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 705 }
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 1}
+      }
+    })
+  }
+
+  Device(MBI7) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 707 }
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 1}
+      }
+    })
+  }
+
+  Device(MBI8) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      QwordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x400c0080000, // Min Base Address
+        0x400c008ffff, // Max Base Address
+        0x0, // Translate
+        0x10000 // Length
+      )
+    })
+
+    Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+      {
+        576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+        589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+      }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+      {
+        960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+        976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+        992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+        1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+        1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+        1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+        1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+        1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+        1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+        1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+        1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+        1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+      }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+      {
+        1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+        1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+        1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+        1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+        1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+        1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+        1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+        1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+        1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+        1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+        1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+        1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+      }
+    })
+
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 409}
+      }
+    })
+  }
+/*
+  Device(MBI4) {          // Mbi-gen dsa1 dbg0 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 9}
+      }
+    })
+  }
+
+  Device(MBI5) {          // Mbi-gen dsa2 dbg1 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 9}
+      }
+    })
+  }
+
+  Device(MBI6) {          // Mbi-gen dsa sas0 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+    Name(_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 128}
+      }
+    })
+  }
+*/
+  Device(MBI9) {          // Mbi-gen roce intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+    Name (_PRS, ResourceTemplate (){
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+      {
+        722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+        734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+        746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+      }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
new file mode 100644
index 0000000..f9b4722
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -0,0 +1,605 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+  /* 0xD000E014:Hi1616 chip version reg[19:8], 0x102-after EC, 0x101/0-before EC. */
+  OperationRegion (ECRA, SystemMemory, 0xD000E014, 0x4)
+  Field (ECRA, AnyAcc, NoLock, Preserve)
+  {
+    VECA, 32,
+  }
+
+  /* RBYV:Return by chip version
+   * the pcie device should be disable for chip's reason before EC,
+   * and the pcie device should be enable after EC for OS */
+  Method (RBYV)
+  {
+    Store(VECA, local0)
+    And (local0, 0xFFF00, local1)
+    If (LEqual (local1, 0x10200)) {
+      Return (0xf)
+    } Else {
+      Return (0x0)
+    }
+  }
+
+  // 1P NA PCIe2
+  Device (PCI2)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 2) // Segment of this Root complex
+    Name(_BBN, 0x80) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x80, // AddressMinimum - Minimum Bus Number
+          0x87, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xa8800000, // Min Base Address
+          0xaffeffff, // Max Base Address
+          0x0, // Translate
+          0x77f0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0xafff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Device (RES2)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CID, "PNP0C02")  // Motherboard reserved resource
+      Name (_CRS, ResourceTemplate (){
+        Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000)
+      })
+    }
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+
+  } // Device(PCI2)
+  // 1p NB PCIe0
+  Device (PCI4)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 4) // Segment of this Root complex
+    Name(_BBN, 0x88) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x88, // AddressMinimum - Minimum Bus Number
+          0x8f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xa9000000, // Min Base Address
+          0xabfeffff, // Max Base Address
+          0x800000000, // Translate
+          0x2ff0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x8abff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Device (RES4)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CID, "PNP0C02")  // Motherboard reserved resource
+      Name (_CRS, ResourceTemplate (){
+        QwordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x8a0090000, // Min Base Address
+          0x8a009ffff, // Max Base Address
+          0x0, // Translate
+          0x10000 // Length
+       )
+      })
+    }
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (RBYV())
+    }
+
+  } // Device(PCI4)
+
+  // 1P NB PCI1
+  Device (PCI5)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 5) // Segment of this Root complex
+    Name(_BBN, 0x0) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x0, // AddressMinimum - Minimum Bus Number
+          0x7, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xb0800000, // Min Base Address
+          0xb7feffff, // Max Base Address
+          0x800000000, // Translate
+          0x77f0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x8b7ff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Device (RES5)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CID, "PNP0C02")  // Motherboard reserved resource
+      Name (_CRS, ResourceTemplate (){
+        QwordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x8a0200000, // Min Base Address
+          0x8a020ffff, // Max Base Address
+          0x0, // Translate
+          0x10000 // Length
+       )
+      })
+    }
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (RBYV())
+    }
+  } // Device(PCI5)
+
+  // 1P NB PCIe2
+  Device (PCI6)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0x6) // Segment of this Root complex
+    Name(_BBN, 0xc0) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0xc0, // AddressMinimum - Minimum Bus Number
+          0xc7, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xac900000, // Min Base Address
+          0xaffeffff, // Max Base Address
+          0x800000000, // Translate
+          0x36f0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x8afff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Device (RES6)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CID, "PNP0C02")  // Motherboard reserved resource
+      Name (_CRS, ResourceTemplate (){
+        QwordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x8a00a0000, // Min Base Address
+          0x8a00affff, // Max Base Address
+          0x0, // Translate
+          0x10000 // Length
+    )
+     })
+    }
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (RBYV())
+    }
+  } // Device(PCI6)
+  // 1P NB PCIe3
+  Device (PCI7)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0x7) // Segment of this Root complex
+    Name(_BBN, 0x90) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x90, // AddressMinimum - Minimum Bus Number
+          0x97, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xb9800000, // Min Base Address
+          0xbffeffff, // Max Base Address
+          0x800000000, // Translate
+          0x67f0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x8bfff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Device (RES7)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CID, "PNP0C02")  // Motherboard reserved resource
+      Name (_CRS, ResourceTemplate (){
+        QwordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x8a00b0000, // Min Base Address
+          0x8a00bffff, // Max Base Address
+          0x0, // Translate
+          0x10000 // Length
+        )
+      })
+    }
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (RBYV())
+    }
+  } // Device(PCI7)
+  // 2P NA PCIe2
+  Device (PCIa)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0xa) // Segment of this Root complex
+    Name(_BBN, 0x10) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x10, // AddressMinimum - Minimum Bus Number
+          0x1f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x10 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x20000000, // Min Base Address
+          0xefffffff, // Max Base Address
+          0x65000000000, // Translate
+          0xd0000000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x67fffff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Device (RESa)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CID, "PNP0C02")  // Motherboard reserved resource
+      Name (_CRS, ResourceTemplate (){
+        QwordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x600a00a0000, // Min Base Address
+          0x600a00affff, // Max Base Address
+          0x0, // Translate
+          0x10000 // Length
+        )
+      })
+    }
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  } // Device(PCIa)
+  // 2P NB PCIe0
+  Device (PCIc)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0xc) // Segment of this Root complex
+    Name(_BBN, 0x20) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x20, // AddressMinimum - Minimum Bus Number
+          0x2f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x10 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x30000000, // Min Base Address
+          0xefffffff, // Max Base Address
+          0x75000000000, // Translate
+          0xc0000000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x77fffff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Device (RESc)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CID, "PNP0C02")  // Motherboard reserved resource
+      Name (_CRS, ResourceTemplate (){
+        QwordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x700a0090000, // Min Base Address
+          0x700a009ffff, // Max Base Address
+          0x0, // Translate
+          0x10000 // Length
+        )
+      })
+    }
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (RBYV())
+    }
+  } // Device(PCIc)
+
+  //2P NB PCIe1
+  Device (PCId)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0xd) // Segment of this Root complex
+    Name(_BBN, 0x30) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x30, // AddressMinimum - Minimum Bus Number
+          0x3f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x10 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x40000000, // Min Base Address
+          0xefffffff, // Max Base Address
+          0x79000000000, // Translate
+          0xB0000000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x7bfffff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Device (RESd)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CID, "PNP0C02")  // Motherboard reserved resource
+      Name (_CRS, ResourceTemplate (){
+        QwordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x700a0200000, // Min Base Address
+          0x700a020ffff, // Max Base Address
+          0x0, // Translate
+          0x10000 // Length
+        )
+      })
+    }
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (RBYV())
+    }
+  } // Device(PCId)
+}
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
new file mode 100644
index 0000000..93beb95
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
@@ -0,0 +1,244 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  Device(SAS0) {
+    Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+      {
+        64,65,66,67,68,
+        69,70,71,72,73,
+        74,75,76,77,78,
+        79,80,81,82,83,
+        84,85,86,87,88,
+        89,90,91,92,93,
+        94,95,96,97,98,
+        99,100,101,102,103,
+        104,105,106,107,108,
+        109,110,111,112,113,
+        114,115,116,117,118,
+        119,120,121,122,123,
+        124,125,126,127,128,
+        129,130,131,132,133,
+        134,135,136,137,138,
+        139,140,141,142,143,
+        144,145,146,147,148,
+        149,150,151,152,153,
+        154,155,156,157,158,
+        159,
+      }
+
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+      {
+        601,602,603,604,
+        605,606,607,608,609,
+        610,611,612,613,614,
+        615,616,617,618,619,
+        620,621,622,623,624,
+        625,626,627,628,629,
+        630,631,632,
+      }
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},
+        Package () {"queue-count", 16},
+        Package () {"phy-count", 8},
+      }
+    })
+
+    OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x338),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xa60),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a30),
+      STS, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+    }
+  }
+
+  Device(SAS1) {
+    Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
+
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+      {
+        64,65,66,67,68,
+        69,70,71,72,73,
+        74,75,76,77,78,
+        79,80,81,82,83,
+        84,85,86,87,88,
+        89,90,91,92,93,
+        94,95,96,97,98,
+        99,100,101,102,103,
+        104,105,106,107,108,
+        109,110,111,112,113,
+        114,115,116,117,118,
+        119,120,121,122,123,
+        124,125,126,127,128,
+        129,130,131,132,133,
+        134,135,136,137,138,
+        139,140,141,142,143,
+        144,145,146,147,148,
+        149,150,151,152,153,
+        154,155,156,157,158,
+        159,
+      }
+
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+      {
+        576,577,578,579,580,
+        581,582,583,584,585,
+        586,587,588,589,590,
+        591,592,593,594,595,
+        596,597,598,599,600,
+        601,602,603,604,605,
+        606,607,
+      }
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+        Package () {"queue-count", 16},
+        Package () {"phy-count", 8},
+        Package () {"hip06-sas-v2-quirk-amt", 1},
+      }
+    })
+
+    OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x318),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xa18),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a0c),
+      STS, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+    }
+  }
+
+  Device(SAS2) {
+    Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
+
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
+      {
+        192,193,194,195,196,
+        197,198,199,200,201,
+        202,203,204,205,206,
+        207,208,209,210,211,
+        212,213,214,215,216,
+        217,218,219,220,221,
+        222,223,224,225,226,
+        227,228,229,230,231,
+        232,233,234,235,236,
+        237,238,239,240,241,
+        242,243,244,245,246,
+        247,248,249,250,251,
+        252,253,254,255,256,
+        257,258,259,260,261,
+        262,263,264,265,266,
+        267,268,269,270,271,
+        272,273,274,275,276,
+        277,278,279,280,281,
+        282,283,284,285,286,
+        287,
+      }
+
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
+      {
+        608,609,610,611,
+        612,613,614,615,616,
+        617,618,619,620,621,
+        622,623,624,625,626,
+        627,628,629,630,631,
+        632,633,634,635,636,
+        637,638,639,
+      }
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+        Package () {"queue-count", 16},
+        Package () {"phy-count", 8},
+      }
+    })
+
+    OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x3a8),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xae0),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a70),
+      STS, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+    }
+  }
+
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl
new file mode 100644
index 0000000..43e6f92
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl
@@ -0,0 +1,127 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+  Device (USB0)
+  {
+    Name (_HID, "PNP0D20")  // _HID: Hardware ID
+    Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */)  // _CID: Compatible ID
+    Name (_CCA, One)  // _CCA: Cache Coherency Attribute
+    Method (_CRS, 0, Serialized)  // _CRS: Current Resource Settings
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite,
+            0xa7020000,         // Address Base
+            0x00010000,         // Address Length
+            )
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI5")
+        {
+          641,
+        }
+      })
+      Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
+    }
+
+    Device (RHUB)
+    {
+      Name (_ADR, Zero)  // _ADR: Address
+      Device (PRT1)
+      {
+        Name (_ADR, One)  // _ADR: Address
+        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+        {
+          0xFF,
+          Zero,
+          Zero,
+          Zero
+        })
+        Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device
+        {
+          ToPLD (
+            PLD_Revision       = 0x1,
+            PLD_IgnoreColor    = 0x1,
+            PLD_Red            = 0x0,
+            PLD_Green          = 0x0,
+            PLD_Blue           = 0x0,
+            PLD_Width          = 0x0,
+            PLD_Height         = 0x0,
+            PLD_UserVisible    = 0x1,
+            PLD_Dock           = 0x0,
+            PLD_Lid            = 0x0,
+            PLD_Panel          = "UNKNOWN",
+            PLD_VerticalPosition = "UPPER",
+            PLD_HorizontalPosition = "LEFT",
+            PLD_Shape          = "UNKNOWN",
+            PLD_GroupOrientation = 0x0,
+            PLD_GroupToken     = 0x0,
+            PLD_GroupPosition  = 0x0,
+            PLD_Bay            = 0x0,
+            PLD_Ejectable      = 0x0,
+            PLD_EjectRequired  = 0x0,
+            PLD_CabinetNumber  = 0x0,
+            PLD_CardCageNumber = 0x0,
+            PLD_Reference      = 0x0,
+            PLD_Rotation       = 0x0,
+            PLD_Order          = 0x0,
+            PLD_VerticalOffset = 0x0,
+            PLD_HorizontalOffset = 0x0)
+        })
+      }
+
+      Device (PRT2)
+      {
+        Name (_ADR, 0x02)  // _ADR: Address
+        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+        {
+          Zero,
+          0xFF,
+          Zero,
+          Zero
+        })
+      }
+
+      Device (PRT3)
+      {
+        Name (_ADR, 0x03)  // _ADR: Address
+        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+        {
+          Zero,
+          0xFF,
+          Zero,
+          Zero
+        })
+      }
+
+      Device (PRT4)
+      {
+        Name (_ADR, 0x04)  // _ADR: Address
+        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+        {
+          Zero,
+          0xFF,
+          Zero,
+          Zero
+        })
+      }
+    }
+  }
+}
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl
new file mode 100644
index 0000000..b4fc538
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl
@@ -0,0 +1,31 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Hi1616Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI  ", "HIP07   ", EFI_ACPI_ARM_OEM_REVISION) {
+  include ("Lpc.asl")
+  include ("D05Mbig.asl")
+  include ("Com.asl")
+  include ("CPU.asl")
+  include ("D05I2c.asl")
+  include ("D05Usb.asl")
+  include ("D05Hns.asl")
+  include ("D05Sas.asl")
+  include ("D05Pci.asl")
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl
new file mode 100644
index 0000000..0965afc
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl
@@ -0,0 +1,25 @@
+/** @file
+*
+*  Copyright (c) 2016 Hisilicon Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// LPC
+//
+
+Device (LPC0)
+{
+  Name(_HID, "HISI0191")  // HiSi LPC
+  Name (_CRS, ResourceTemplate () {
+    Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
+  })
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc
new file mode 100644
index 0000000..2908b24
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc
@@ -0,0 +1,67 @@
+/** @file
+*  Firmware ACPI Control Structure (FACS)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32  Signature
+  sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),  // UINT32  Length
+  0xA152,                                                 // UINT32  HardwareSignature
+  0,                                                      // UINT32  FirmwareWakingVector
+  0,                                                      // UINT32  GlobalLock
+  0,                                                      // UINT32  Flags
+  0,                                                      // UINT64  XFirmwareWakingVector
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,   // UINT8   Version;
+    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[0]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[1]
+      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved0[2]
+  0,                                                      // UINT32  OspmFlags  "Platform firmware must
+                                                          //                    initialize this field to zero."
+    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[0]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[1]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[2]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[3]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[4]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[5]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[6]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[7]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[8]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[9]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[10]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[11]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[12]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[13]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[14]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[15]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[16]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[17]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[18]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[19]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[20]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[21]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[22]
+      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved1[23]
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Facs;
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..152410b
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc
@@ -0,0 +1,91 @@
+/** @file
+*  Fixed ACPI Description Table (FADT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1616Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+  ARM_ACPI_HEADER (
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+  ),
+  0,                                                                        // UINT32     FirmwareCtrl
+  0,                                                                        // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
+  EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED,                                      // UINT8      PreferredPmProfile
+  0,                                                                        // UINT16     SciInt
+  0,                                                                        // UINT32     SmiCmd
+  0,                                                                        // UINT8      AcpiEnable
+  0,                                                                        // UINT8      AcpiDisable
+  0,                                                                        // UINT8      S4BiosReq
+  0,                                                                        // UINT8      PstateCnt
+  0,                                                                        // UINT32     Pm1aEvtBlk
+  0,                                                                        // UINT32     Pm1bEvtBlk
+  0,                                                                        // UINT32     Pm1aCntBlk
+  0,                                                                        // UINT32     Pm1bCntBlk
+  0,                                                                        // UINT32     Pm2CntBlk
+  0,                                                                        // UINT32     PmTmrBlk
+  0,                                                                        // UINT32     Gpe0Blk
+  0,                                                                        // UINT32     Gpe1Blk
+  0,                                                                        // UINT8      Pm1EvtLen
+  0,                                                                        // UINT8      Pm1CntLen
+  0,                                                                        // UINT8      Pm2CntLen
+  0,                                                                        // UINT8      PmTmrLen
+  0,                                                                        // UINT8      Gpe0BlkLen
+  0,                                                                        // UINT8      Gpe1BlkLen
+  0,                                                                        // UINT8      Gpe1Base
+  0,                                                                        // UINT8      CstCnt
+  0,                                                                        // UINT16     PLvl2Lat
+  0,                                                                        // UINT16     PLvl3Lat
+  0,                                                                        // UINT16     FlushSize
+  0,                                                                        // UINT16     FlushStride
+  0,                                                                        // UINT8      DutyOffset
+  0,                                                                        // UINT8      DutyWidth
+  0,                                                                        // UINT8      DayAlrm
+  0,                                                                        // UINT8      MonAlrm
+  0,                                                                        // UINT8      Century
+  0,                                                                        // UINT16     IaPcBootArch
+  0,                                                                        // UINT8      Reserved1
+  EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  ResetReg
+  0,                                                                        // UINT8      ResetValue
+  EFI_ACPI_5_1_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
+  EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
+  0,                                                                        // UINT64     XFirmwareCtrl
+  0,                                                                        // UINT64     XDsdt
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
+  NULL_GAS                                                                  // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..b472828
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc
@@ -0,0 +1,95 @@
+/** @file
+*  Generic Timer Description Table (GTDT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include "Hi1616Platform.h"
+
+#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0
+#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL       0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+  #define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+
+#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+  EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdogs[HI1616_WATCHDOG_COUNT];
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+  {
+    ARM_ACPI_HEADER(
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES,
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+    ),
+    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
+    0,                                            // UINT32  Reserved
+    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
+    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
+    0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
+#ifdef notyet
+    PV660_WATCHDOG_COUNT,                          // UINT32  PlatformTimerCount
+    sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+  },
+  {
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
+        0, 0, 0, 0),
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
+        0, 0, 0, 0)
+  }
+#else /* !notyet */
+  0, 0
+  }
+#endif
+  };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
new file mode 100644
index 0000000..808219a
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
@@ -0,0 +1,48 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#ifndef _HI1610_PLATFORM_H_
+#define _HI1610_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
+#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('I','N','T','L')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+  }
+
+#define HI1616_WATCHDOG_COUNT  2
+
+#endif
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
new file mode 100644
index 0000000..b83c221
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
@@ -0,0 +1,282 @@
+/** @file
+*  Multiple APIC Description Table (MADT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/AcpiNextLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include "Hi1616Platform.h"
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+// 0x20000 is only for socket 0
+#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (0x10000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (0x30000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (0x50000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (0x70000 | ((ClusterId) << 8) | (CoreId))
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_5_1_GIC_STRUCTURE                            GicInterfaces[64];
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+  EFI_ACPI_6_0_GIC_ITS_STRUCTURE                      GicITS[8];
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+  {
+    ARM_ACPI_HEADER (
+      EFI_ACPI_1_0_APIC_SIGNATURE,
+      EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+      EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+    ),
+    //
+    // MADT specific fields
+    //
+    0, // LocalApicAddress
+    0, // Flags
+  },
+  {
+    // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+    //                                          GsivId, GicRBase, Mpidr)
+    // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+    //       ACPI v5.1).
+    //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+    //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        0, 0, PLATFORM_GET_MPID_TA(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        1, 1, PLATFORM_GET_MPID_TA(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        2, 2, PLATFORM_GET_MPID_TA(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        3, 3, PLATFORM_GET_MPID_TA(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        5, 5, PLATFORM_GET_MPID_TA(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        6, 6, PLATFORM_GET_MPID_TA(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        7, 7, PLATFORM_GET_MPID_TA(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        8, 8, PLATFORM_GET_MPID_TA(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        9, 9, PLATFORM_GET_MPID_TA(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        10, 10, PLATFORM_GET_MPID_TA(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        11, 11, PLATFORM_GET_MPID_TA(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        13, 13, PLATFORM_GET_MPID_TA(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        14, 14, PLATFORM_GET_MPID_TA(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        15, 15, PLATFORM_GET_MPID_TA(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        16, 16, PLATFORM_GET_MPID_TB(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        17, 17, PLATFORM_GET_MPID_TB(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        18, 18, PLATFORM_GET_MPID_TB(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        19, 19, PLATFORM_GET_MPID_TB(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        21, 21, PLATFORM_GET_MPID_TB(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        22, 22, PLATFORM_GET_MPID_TB(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        23, 23, PLATFORM_GET_MPID_TB(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x2C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        24, 24, PLATFORM_GET_MPID_TB(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x300000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        25, 25, PLATFORM_GET_MPID_TB(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        26, 26, PLATFORM_GET_MPID_TB(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x380000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        27, 27, PLATFORM_GET_MPID_TB(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x3C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x400000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        29, 29, PLATFORM_GET_MPID_TB(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x440000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        30, 30, PLATFORM_GET_MPID_TB(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x480000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        31, 31, PLATFORM_GET_MPID_TB(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x4C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        32, 32, PLATFORM_GET_MPID_TA_2(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        33, 33, PLATFORM_GET_MPID_TA_2(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        34, 34, PLATFORM_GET_MPID_TA_2(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        35, 35, PLATFORM_GET_MPID_TA_2(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        37, 37, PLATFORM_GET_MPID_TA_2(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        38, 38, PLATFORM_GET_MPID_TA_2(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        39, 39, PLATFORM_GET_MPID_TA_2(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        40, 40, PLATFORM_GET_MPID_TA_2(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        41, 41, PLATFORM_GET_MPID_TA_2(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        42, 42, PLATFORM_GET_MPID_TA_2(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        43, 43, PLATFORM_GET_MPID_TA_2(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        45, 45, PLATFORM_GET_MPID_TA_2(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        46, 46, PLATFORM_GET_MPID_TA_2(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        47, 47, PLATFORM_GET_MPID_TA_2(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        48, 48, PLATFORM_GET_MPID_TB_2(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        49, 49, PLATFORM_GET_MPID_TB_2(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        50, 50, PLATFORM_GET_MPID_TB_2(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        51, 51, PLATFORM_GET_MPID_TB_2(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        53, 53, PLATFORM_GET_MPID_TB_2(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        54, 54, PLATFORM_GET_MPID_TB_2(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        55, 55, PLATFORM_GET_MPID_TB_2(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x2C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        56, 56, PLATFORM_GET_MPID_TB_2(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x300000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        57, 57, PLATFORM_GET_MPID_TB_2(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        58, 58, PLATFORM_GET_MPID_TB_2(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x380000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        59, 59, PLATFORM_GET_MPID_TB_2(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x3C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x400000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        61, 61, PLATFORM_GET_MPID_TB_2(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x440000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        62, 62, PLATFORM_GET_MPID_TB_2(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x480000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        63, 63, PLATFORM_GET_MPID_TB_2(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x4C0000 /* GicRBase */),
+  },
+
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4),
+  {
+    EFI_ACPI_6_0_GIC_ITS_INIT(0,0x4C000000), //peri a
+    EFI_ACPI_6_0_GIC_ITS_INIT(1,0x6C000000), //peri b
+    EFI_ACPI_6_0_GIC_ITS_INIT(2,0xC6000000), //dsa a
+    EFI_ACPI_6_0_GIC_ITS_INIT(3,0x8C6000000), //dsa b
+    EFI_ACPI_6_0_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a
+    EFI_ACPI_6_0_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b
+    EFI_ACPI_6_0_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a
+    EFI_ACPI_6_0_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h
new file mode 100644
index 0000000..7ff924b
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h
@@ -0,0 +1,86 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_
+
+typedef enum {
+  EmHilink0Hccs1X8 = 0,
+  EmHilink0Pcie1X8 = 2,
+  EmHilink0Pcie1X4Pcie2X4 = 3,
+  EmHilink0Sas2X8 = 4,
+  EmHilink0Hccs1X8Width16,
+  EmHilink0Hccs1X8Width32,
+  EmHilink0Hccs1X8Speed5G,
+} HILINK0_MODE_TYPE;
+
+typedef enum {
+  EmHilink1Sas2X1 = 0,
+  EmHilink1Hccs0X8 = 1,
+  EmHilink1Pcie0X8 = 2,
+  EmHilink1Hccs0X8Width16,
+  EmHilink1Hccs0X8Width32,
+  EmHilink1Hccs0X8Speed5G,
+} HILINK1_MODE_TYPE;
+
+typedef enum {
+  EmHilink2Pcie2X8 = 0,
+  EmHilink2Hccs2X8 = 1,
+  EmHilink2Sas0X8 = 2,
+  EmHilink2Hccs2X8Width16,
+  EmHilink2Hccs2X8Width32,
+  EmHilink2Hccs2X8Speed5G,
+} HILINK2_MODE_TYPE;
+
+typedef enum {
+  EmHilink5Pcie3X4 = 0,
+  EmHilink5Pcie2X2Pcie3X2 = 1,
+  EmHilink5Sas1X4 = 2,
+} HILINK5_MODE_TYPE;
+
+
+typedef struct {
+  HILINK0_MODE_TYPE Hilink0Mode;
+  HILINK1_MODE_TYPE Hilink1Mode;
+  HILINK2_MODE_TYPE Hilink2Mode;
+  UINT32 Hilink3Mode;
+  UINT32 Hilink4Mode;
+  HILINK5_MODE_TYPE Hilink5Mode;
+  UINT32 Hilink6Mode;
+  UINT32 UseSsc;
+} SERDES_PARAM;
+
+#define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
+#define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
+#define SERDES_INVALID_RATE_MODE  0xFFFFFFFF
+
+typedef struct {
+  UINT32 MacroId;
+  UINT32 DsNum;
+  UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
+extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
+extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
+UINT32 GetEthType(UINT8 EthChannel);
+VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode);
+
+EFI_STATUS
+EfiSerdesInitWrap (VOID);
+INT32 SerdesReset(UINT32 SiclId, UINT32 Macro);
+VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
+
+#endif
diff --git a/Chips/Hisilicon/Hi6220/Hi6220.dec b/Chips/Hisilicon/Hi6220/Hi6220.dec
index 644ea31..002bc66 100644
--- a/Chips/Hisilicon/Hi6220/Hi6220.dec
+++ b/Chips/Hisilicon/Hi6220/Hi6220.dec
@@ -1,33 +1,32 @@
-#
-#  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-#  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-[Defines]
-  DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = HiKey
-  PACKAGE_GUID                   = 01be44a1-5ed3-47fc-8ecf-daa83344678c
-  PACKAGE_VERSION                = 0.1
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-#                   Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-[Includes.common]
-  Include                        # Root include for the package
-
-[Guids.common]
-  gHi6220TokenSpaceGuid      =  { 0x47fc9a0e, 0x1796, 0x4d04, { 0xaf, 0x68, 0x2b, 0xcb, 0x0d, 0x40, 0x84, 0x09} }
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = HiKey
+  PACKAGE_GUID                   = 01be44a1-5ed3-47fc-8ecf-daa83344678c
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
+
+[Guids.common]
+  gHi6220TokenSpaceGuid      =  { 0x47fc9a0e, 0x1796, 0x4d04, { 0xaf, 0x68, 0x2b, 0xcb, 0x0d, 0x40, 0x84, 0x09} }
diff --git a/Chips/Hisilicon/Hi6220/Include/Hi6220.h b/Chips/Hisilicon/Hi6220/Include/Hi6220.h
index 42a6895..0bc270e 100644
--- a/Chips/Hisilicon/Hi6220/Include/Hi6220.h
+++ b/Chips/Hisilicon/Hi6220/Include/Hi6220.h
@@ -1,75 +1,106 @@
-/** @file
-*
-*  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-*  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __HI6220_H__
-#define __HI6220_H__
-
-/***********************************************************************************
-// Platform Memory Map
-************************************************************************************/
-
-// SOC peripherals (UART, I2C, I2S, USB, etc)
-#define HI6220_PERIPH_BASE			0xF4000000
-#define HI6220_PERIPH_SZ			0x05800000
-
-#define PERI_CTRL_BASE				0xF7030000
-#define SC_PERIPH_CTRL4				0x00C
-#define CTRL4_FPGA_EXT_PHY_SEL          	BIT3
-#define CTRL4_PICO_SIDDQ			BIT6
-#define CTRL4_PICO_OGDISABLE			BIT8
-#define CTRL4_PICO_VBUSVLDEXT			BIT10
-#define CTRL4_PICO_VBUSVLDEXTSEL		BIT11
-#define CTRL4_OTG_PHY_SEL			BIT21
-
-#define SC_PERIPH_CTRL5				0x010
-
-#define CTRL5_USBOTG_RES_SEL			BIT3
-#define CTRL5_PICOPHY_ACAENB			BIT4
-#define CTRL5_PICOPHY_BC_MODE			BIT5
-#define CTRL5_PICOPHY_CHRGSEL			BIT6
-#define CTRL5_PICOPHY_VDATSRCEND		BIT7
-#define CTRL5_PICOPHY_VDATDETENB		BIT8
-#define CTRL5_PICOPHY_DCDENB			BIT9
-#define CTRL5_PICOPHY_IDDIG			BIT10
-
-#define SC_PERIPH_CTRL8				0x018
-#define SC_PERIPH_CLKEN0			0x200
-#define SC_PERIPH_CLKDIS0			0x204
-#define SC_PERIPH_CLKSTAT0			0x208
-
-#define SC_PERIPH_RSTEN0			0x300
-#define SC_PERIPH_RSTDIS0			0x304
-#define SC_PERIPH_RSTSTAT0              	0x308
-
-#define RST0_USBOTG_BUS				BIT4
-#define RST0_POR_PICOPHY			BIT5
-#define RST0_USBOTG				BIT6
-#define RST0_USBOTG_32K				BIT7
-
-#define EYE_PATTERN_PARA			0x7053348c
-
-#define MDDRC_AXI_BASE                          0xF7120000
-#define AXI_REGION_MAP_OFFSET(x)                ( 0x100 + ( x ) * 0x10 )
-
-#define AO_CTRL_BASE				0xF7800000
-#define SC_PW_MTCMOS_EN0			0x830
-#define SC_PW_MTCMOS_DIS0			0x834
-#define SC_PW_MTCMOS_STAT0			0x838
-#define SC_PW_MTCMOS_ACK_STAT0			0x83c
-#define PW_EN0_G3D				(1 << 1)
-
-#define PMUSSI_BASE                             0xF8000000
-
-#endif	/* __HI6220_H__ */
+/** @file
+*
+*  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __HI6220_H__
+#define __HI6220_H__
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// SOC peripherals (UART, I2C, I2S, USB, etc)
+#define HI6220_PERIPH_BASE                      0xF4000000
+#define HI6220_PERIPH_SZ                        0x05800000
+
+#define PERI_CTRL_BASE                          0xF7030000
+#define SC_PERIPH_CTRL4                         0x00C
+#define CTRL4_FPGA_EXT_PHY_SEL                  BIT3
+#define CTRL4_PICO_SIDDQ                        BIT6
+#define CTRL4_PICO_OGDISABLE                    BIT8
+#define CTRL4_PICO_VBUSVLDEXT                   BIT10
+#define CTRL4_PICO_VBUSVLDEXTSEL                BIT11
+#define CTRL4_OTG_PHY_SEL                       BIT21
+
+#define SC_PERIPH_CTRL5                         0x010
+
+#define CTRL5_USBOTG_RES_SEL                    BIT3
+#define CTRL5_PICOPHY_ACAENB                    BIT4
+#define CTRL5_PICOPHY_BC_MODE                   BIT5
+#define CTRL5_PICOPHY_CHRGSEL                   BIT6
+#define CTRL5_PICOPHY_VDATSRCEND                BIT7
+#define CTRL5_PICOPHY_VDATDETENB                BIT8
+#define CTRL5_PICOPHY_DCDENB                    BIT9
+#define CTRL5_PICOPHY_IDDIG                     BIT10
+
+#define SC_PERIPH_CTRL8                         0x018
+#define SC_PERIPH_CLKEN0                        0x200
+#define SC_PERIPH_CLKDIS0                       0x204
+#define SC_PERIPH_CLKSTAT0                      0x208
+
+#define SC_PERIPH_CLKEN3                        0x230
+#define SC_PERIPH_RSTEN3                        0x330
+#define SC_PERIPH_RSTEN0                        0x300
+#define SC_PERIPH_RSTDIS0                       0x304
+#define SC_PERIPH_RSTSTAT0                      0x308
+#define SC_PERIPH_RSTDIS3                       0x334
+#define SC_PERIPH_RSTSTAT3                      0x338
+
+#define RST0_USBOTG_BUS                         BIT4
+#define RST0_POR_PICOPHY                        BIT5
+#define RST0_USBOTG                             BIT6
+#define RST0_USBOTG_32K                         BIT7
+
+/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */
+#define PERIPH_RST0_MMC2                        (1 << 2)
+
+/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */
+#define PERIPH_RST3_CSSYS                       (1 << 0)
+#define PERIPH_RST3_I2C0                        (1 << 1)
+#define PERIPH_RST3_I2C1                        (1 << 2)
+#define PERIPH_RST3_I2C2                        (1 << 3)
+#define PERIPH_RST3_I2C3                        (1 << 4)
+#define PERIPH_RST3_UART1                       (1 << 5)
+#define PERIPH_RST3_UART2                       (1 << 6)
+#define PERIPH_RST3_UART3                       (1 << 7)
+#define PERIPH_RST3_UART4                       (1 << 8)
+#define PERIPH_RST3_SSP                         (1 << 9)
+#define PERIPH_RST3_PWM                         (1 << 10)
+#define PERIPH_RST3_BLPWM                       (1 << 11)
+#define PERIPH_RST3_TSENSOR                     (1 << 12)
+#define PERIPH_RST3_DAPB                        (1 << 18)
+#define PERIPH_RST3_HKADC                       (1 << 19)
+#define PERIPH_RST3_CODEC_SSI                   (1 << 20)
+#define PERIPH_RST3_PMUSSI1                     (1 << 22)
+
+#define EYE_PATTERN_PARA                        0x7053348c
+
+#define MDDRC_AXI_BASE                          0xF7120000
+#define AXI_REGION_MAP                          0x100
+#define HIKEY_REGION_SIZE_MASK                  (7 << 8)
+// (0 << 8) means 16MB, (7 << 8) means 2GB
+#define HIKEY_REGION_SIZE(x)                    (1U << ((((x) & HIKEY_REGION_SIZE_MASK) >> 8) + 24))
+
+#define AO_CTRL_BASE                            0xF7800000
+#define SC_PW_MTCMOS_EN0                        0x830
+#define SC_PW_MTCMOS_DIS0                       0x834
+#define SC_PW_MTCMOS_STAT0                      0x838
+#define SC_PW_MTCMOS_ACK_STAT0                  0x83c
+#define PW_EN0_G3D                              (1 << 1)
+
+#define PMUSSI_BASE                             0xF8000000
+
+#define PMUSSI_REG(x)                           (PMUSSI_BASE + ((x) << 2))
+
+
+#endif /* __HI6220_H__ */
diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec
new file mode 100644
index 0000000..2c02e14
--- /dev/null
+++ b/Chips/Hisilicon/HisiPkg.dec
@@ -0,0 +1,280 @@
+#/** @file
+#
+#    Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = HisiPkg
+  PACKAGE_GUID                   = c6013a10-758c-4c0d-bd07-e601e6721f86
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  Include
+
+[Ppis]
+  gIpmiInterfacePpiGuid = {0x28ae4d88, 0xb658, 0x46b9, {0xa0, 0xe7, 0xd4, 0x95, 0xe2, 0xe8, 0x97, 0xf}}
+
+
+
+[Protocols]
+  gUniNorFlashProtocolGuid = {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}}
+  gHisiSpiFlashProtocolGuid = {0x339132DC, 0xCED7, 0x4f84, {0xAA, 0xE7, 0x2E, 0xC4, 0xF9, 0x14, 0x38, 0x2F}}
+
+  gHisiBoardNicProtocolGuid = {0xb5903955, 0x31e9, 0x4aaf, {0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66}}
+  gHisiBoardXgeStatusProtocolGuid = {0xa6b8ed0e, 0xd8cc, 0x4853, {0xaa, 0x39, 0x2c, 0x3e, 0xcd, 0x7c, 0xa5, 0x97}}
+  gIpmiInterfaceProtocolGuid = {0xa37e200e, 0xda90, 0x473b, {0x8b, 0xb5, 0x1d, 0x7b, 0x11, 0xba, 0x32, 0x33}}
+  gBmcInfoProtocolGuid = {0x43fa6ffd, 0x35e4, 0x479e, {0xab, 0xec, 0x5, 0x3, 0xf6, 0x48, 0x0, 0xf5}}
+  gSataEnableFlagProtocolGuid = {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf, 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}}
+  gPlatformSasProtocolGuid = {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}}
+
+[Guids]
+  gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}}
+
+  gHisiEfiMemoryMapGuid  = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}}
+  gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
+
+[LibraryClasses]
+  PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h
+  CpldIoLib|Include/Library/CpldIoLib.h
+  OemAddressMapLib|Include/Library/OemAddressMapLib.h
+  OemMiscLib|Include/Library/OemMiscLib.h
+  I2CLib|Include/Library/I2CLib.h
+  PlatformPciLib|Include/Library/PlatformPciLib.h
+  FdtUpdateLib|Include/Library/FdtUpdateLib.h
+  LpcLib|Include/Library/LpcLib.h
+
+[PcdsFixedAtBuild]
+  gHisiTokenSpaceGuid.PcdNORFlashBase|0x00000000|UINT64|0x01000008
+  gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x1000000|UINT32|0x0100000c
+
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000|UINT32|0x01000010
+  gHisiTokenSpaceGuid.PcdUartClkInHz|24000000|UINT32|0x0100001F
+  gHisiTokenSpaceGuid.PcdSerialRegisterSpaceSize|0x10000|UINT64|0x01000019
+
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0|UINT64|0x00000047
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0|UINT64|0x00000046
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0|UINT64|0x00000048
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0|UINT64|0x00000049
+
+  gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0|UINT64|0x01000023
+  gHisiTokenSpaceGuid.PcdCpldBaseAddress|0|UINT64|0x01000024
+  gHisiTokenSpaceGuid.PcdMailBoxAddress|0|UINT64|0x01000025
+
+  gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0|UINT64|0x01000037
+  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0|UINT64|0x01000038
+
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0|UINT64|0x01000041
+
+  gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0|UINT64|0x01000042
+
+  gHisiTokenSpaceGuid.PcdFirmwareVendor|L"Huawei Corp."|VOID*|0x30000052
+  gHisiTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
+  gHisiTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
+  gHisiTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000055
+  gHisiTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000056
+  gHisiTokenSpaceGuid.PcdCPUInfo|L""|VOID*|0x30000060
+  gHisiTokenSpaceGuid.PcdBiosVersionString|L""|VOID*|0x00010069
+  gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L""|VOID*|0x00010070
+
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x0|UINT32|0x40000001
+
+  gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x0|UINT32|0x40000002
+  gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x0|UINT64|0x40000003
+
+  gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x0|UINT32|0x40000004
+
+  #FDT File Address
+  gHisiTokenSpaceGuid.FdtFileAddress|0x0|UINT64|0x40000005
+
+  #Reserved for NVRAM
+  gHisiTokenSpaceGuid.PcdReservedNvramBase|0x0|UINT64|0x40000006
+  gHisiTokenSpaceGuid.PcdReservedNvramSize|0x0|UINT64|0x40000007
+
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
+  gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
+  gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
+
+  gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c
+  gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d
+
+  gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038
+
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0|UINT32|0x00000044
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0|UINT32|0x00000045
+
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x400000000000|UINT64|0x00000051   # 4T
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0|UINT64|0x00000052
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0|UINT64|0x00000053
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0|UINT64|0x00000054
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0|UINT64|0x00000055
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0|UINT64|0x00000056
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0|UINT64|0x00000057
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000058
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0|UINT64|0x00000059
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000152
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0|UINT64|0x00000153
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000154
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0|UINT64|0x00000155
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000156
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0|UINT64|0x00000157
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000158
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0|UINT64|0x00000159
+
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0|UINT64|0x00000252
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0|UINT64|0x00000253
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0|UINT64|0x00000254
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0|UINT64|0x00000255
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0|UINT64|0x00000256
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0|UINT64|0x00000257
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000258
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0|UINT64|0x00000259
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000352
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0|UINT64|0x00000353
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000354
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0|UINT64|0x00000355
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000356
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0|UINT64|0x00000357
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000358
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0|UINT64|0x00000359
+
+  gHisiTokenSpaceGuid.PciHb0Rb0Base|0|UINT64|0x0000005a
+  gHisiTokenSpaceGuid.PciHb0Rb1Base|0|UINT64|0x0000005b
+  gHisiTokenSpaceGuid.PciHb0Rb2Base|0|UINT64|0x0000005c
+  gHisiTokenSpaceGuid.PciHb0Rb3Base|0|UINT64|0x0000005d
+  gHisiTokenSpaceGuid.PciHb0Rb4Base|0|UINT64|0x0100005a
+  gHisiTokenSpaceGuid.PciHb0Rb5Base|0|UINT64|0x0100005b
+  gHisiTokenSpaceGuid.PciHb0Rb6Base|0|UINT64|0x0100005c
+  gHisiTokenSpaceGuid.PciHb0Rb7Base|0|UINT64|0x0100005d
+  gHisiTokenSpaceGuid.PciHb1Rb0Base|0|UINT64|0x0200005a
+  gHisiTokenSpaceGuid.PciHb1Rb1Base|0|UINT64|0x0200005b
+  gHisiTokenSpaceGuid.PciHb1Rb2Base|0|UINT64|0x0200005c
+  gHisiTokenSpaceGuid.PciHb1Rb3Base|0|UINT64|0x0200005d
+  gHisiTokenSpaceGuid.PciHb1Rb4Base|0|UINT64|0x0300005a
+  gHisiTokenSpaceGuid.PciHb1Rb5Base|0|UINT64|0x0300005b
+  gHisiTokenSpaceGuid.PciHb1Rb6Base|0|UINT64|0x0300005c
+  gHisiTokenSpaceGuid.PciHb1Rb7Base|0|UINT64|0x0300005d
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0|UINT64|0x8000005a
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0|UINT64|0x8000005b
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0|UINT64|0x8000005c
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0|UINT64|0x8000005d
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0|UINT64|0x8000005e
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0|UINT64|0x8000005f
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0|UINT64|0x80000060
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0|UINT64|0x80000061
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0|UINT64|0x80000062
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0|UINT64|0x80000063
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0|UINT64|0x80000064
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0|UINT64|0x80000065
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0|UINT64|0x80000066
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0|UINT64|0x80000067
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0|UINT64|0x80000068
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0|UINT64|0x80000069
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0|UINT64|0x6000005a
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0|UINT64|0x6000005b
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0|UINT64|0x6000005c
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0|UINT64|0x6000005d
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0|UINT64|0x6000005e
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0|UINT64|0x6000005f
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0|UINT64|0x60000060
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0|UINT64|0x60000061
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0|UINT64|0x60000062
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0|UINT64|0x60000063
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0|UINT64|0x60000064
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0|UINT64|0x60000065
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0|UINT64|0x60000066
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0|UINT64|0x60000067
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0|UINT64|0x60000068
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0|UINT64|0x60000069
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0|UINT64|0x7000005a
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0|UINT64|0x7000005b
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0|UINT64|0x7000005c
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0|UINT64|0x7000005d
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0|UINT64|0x7000005e
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0|UINT64|0x7000005f
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0|UINT64|0x70000060
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0|UINT64|0x70000061
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0|UINT64|0x70000062
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0|UINT64|0x70000063
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0|UINT64|0x70000064
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0|UINT64|0x70000065
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0|UINT64|0x70000066
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0|UINT64|0x70000067
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0|UINT64|0x70000068
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0|UINT64|0x70000069
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0|UINT64|0x3000005a
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0|UINT64|0x3000005b
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0|UINT64|0x3000005c
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0|UINT64|0x3000005d
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0|UINT64|0x3000005e
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0|UINT64|0x30000070
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0|UINT64|0x30000061
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0|UINT64|0x30000062
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0|UINT64|0x30000063
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0|UINT64|0x30000064
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0|UINT64|0x30000065
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0|UINT64|0x30000066
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0|UINT64|0x30000067
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0|UINT64|0x30000068
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0|UINT64|0x30000069
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0|UINT64|0x3000006a
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0|UINT64|0x9000005a
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0|UINT64|0x9000005b
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0|UINT64|0x9000005c
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0|UINT64|0x9000005d
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0|UINT64|0x9100005a
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0|UINT64|0x9100005b
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0|UINT64|0x9100005c
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0|UINT64|0x9100005d
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0|UINT64|0x9010005a
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0|UINT64|0x9010005b
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0|UINT64|0x9010005c
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0|UINT64|0x9010005d
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0|UINT64|0x9110005a
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0|UINT64|0x9110005b
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0|UINT64|0x9110005c
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0|UINT64|0x9110005d
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0|UINT64|0x2000005a
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0|UINT64|0x2000005b
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0|UINT64|0x2000005c
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0|UINT64|0x2000005d
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0|UINT64|0x2100005a
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0|UINT64|0x2100005b
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0|UINT64|0x2100005c
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0|UINT64|0x2100005d
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0|UINT64|0x2010005a
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0|UINT64|0x2010005b
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0|UINT64|0x2010005c
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0|UINT64|0x2010005d
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0|UINT64|0x2110005a
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0|UINT64|0x2110005b
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0|UINT64|0x2110005c
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d
+
+  gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061
+  gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056
+
+[PcdsFeatureFlag]
+  gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065
+  gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066
+
+
+
diff --git a/Chips/Hisilicon/Hisilicon.dsc.inc b/Chips/Hisilicon/Hisilicon.dsc.inc
new file mode 100644
index 0000000..510ee1d
--- /dev/null
+++ b/Chips/Hisilicon/Hisilicon.dsc.inc
@@ -0,0 +1,371 @@
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  #
+  # Allow dynamic PCDs
+  #
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+  # ARM Architectural Libraries
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+
+  # Versatile Express Specific Libraries
+  ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+  NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+  EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
+  # ARM PL111 Lcd Driver
+  LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+
+  # ARM PL354 SMC Driver
+  PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
+  # ARM PL011 UART Driver
+  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+
+  SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+  # EBL Related Libraries
+  EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
+  EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+  EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+  EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+
+  UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  #
+  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+  # in the debugger will show load and unload commands for symbols. You can cut and paste this
+  # into the command window to load symbols. We should be able to use a script to do this, but
+  # the version of RVD I have does not support scripts accessing system memory.
+  #
+  #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+  #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+  SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+
+  # BDS Libraries
+  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+
+  # Use ArmCortexA5xLib to get A57 specific functions
+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
+
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # And NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+  # Add support for GCC stack protector
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+[LibraryClasses.common.SEC]
+  ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+  # Trustzone Support
+  ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEIM]
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+  ## Fixed compile error after upgrade to 14.10
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
+  DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+
+[LibraryClasses.AARCH64]
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+
+[BuildOptions]
+  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+  #
+  # Control what commands are supported from the UI
+  # Turn these on and off to add features or save size
+  #
+  ## Set PcdEmbeddedMacBoot to FALSE, or console mode will be changed when
+  ## entering EBL and not restored when exiting.
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|FALSE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE
+
+[PcdsFixedAtBuild.common]
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
+
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"VExpress"
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+  # DEBUG_ASSERT_ENABLED       0x01
+  # DEBUG_PRINT_ENABLED        0x02
+  # DEBUG_CODE_ENABLED         0x04
+  # CLEAR_MEMORY_ENABLED       0x08
+  # ASSERT_BREAKPOINT_ENABLED  0x10
+  # ASSERT_DEADLOOP_ENABLED    0x20
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+!endif
+
+  #  DEBUG_INIT      0x00000001  // Initialization
+  #  DEBUG_WARN      0x00000002  // Warnings
+  #  DEBUG_LOAD      0x00000004  // Load events
+  #  DEBUG_FS        0x00000008  // EFI File system
+  #  DEBUG_POOL      0x00000010  // Alloc & Free's
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free's
+  #  DEBUG_INFO      0x00000040  // Verbose
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+  #  DEBUG_VARIABLE  0x00000100  // Variable
+  #  DEBUG_BM        0x00000400  // Boot Manager
+  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+  #  DEBUG_NET       0x00004000  // SNI Driver
+  #  DEBUG_UNDI      0x00010000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
+  #  DEBUG_EVENT     0x00080000  // Event messages
+  #  DEBUG_ERROR     0x80000000  // Error
+
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+
+  #
+  # ARM PrimeCell
+  #
+
+  #
+  # ARM OS Loader
+  #
+  # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/MemoryMapped(0x0,0xED000000,0xED400000)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
+
+  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
+
+  # Set timer interrupt to be triggerred in 1ms to avoid missing
+  # serial terminal input characters.
+  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
+  gArmTokenSpaceGuid.PcdVFPEnabled|1
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32
+
+[PcdsDynamicHii.common.DEFAULT]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 # Variable: L"Timeout"
+
diff --git a/Chips/Hisilicon/Hisilicon.fdf.inc b/Chips/Hisilicon/Hisilicon.fdf.inc
new file mode 100644
index 0000000..ee87cd1
--- /dev/null
+++ b/Chips/Hisilicon/Hisilicon.fdf.inc
@@ -0,0 +1,139 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE Align = 4K                  $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE Align = Auto             $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE Align = Auto           $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.BINARY]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE Align = Auto           |.efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)" Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI               |.acpi
+    RAW ASL                |.aml
+  }
+
diff --git a/Chips/Hisilicon/Include/Guid/MemoryMapData.h b/Chips/Hisilicon/Include/Guid/MemoryMapData.h
new file mode 100644
index 0000000..5e418f9
--- /dev/null
+++ b/Chips/Hisilicon/Include/Guid/MemoryMapData.h
@@ -0,0 +1,28 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef _MEMORY_MAP_GUID_H_
+#define _MEMORY_MAP_GUID_H_
+
+#define EFI_MEMORY_MAP_GUID \
+  { \
+    0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \
+  }
+
+extern EFI_GUID gHisiEfiMemoryMapGuid;
+
+#endif
diff --git a/Chips/Hisilicon/Include/Guid/VersionInfoHobGuid.h b/Chips/Hisilicon/Include/Guid/VersionInfoHobGuid.h
new file mode 100644
index 0000000..a61a244
--- /dev/null
+++ b/Chips/Hisilicon/Include/Guid/VersionInfoHobGuid.h
@@ -0,0 +1,35 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _VERSION_INFO_HOB_GUID_H_
+#define _VERSION_INFO_HOB_GUID_H_
+
+// {0E13A14C-859C-4f22-82BD-180EE14212BF}
+#define VERSION_INFO_HOB_GUID \
+  {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
+
+extern GUID gVersionInfoHobGuid;
+
+#pragma pack(1)
+
+typedef struct {
+  EFI_TIME BuildTime;
+  CHAR16   String[1];
+} VERSION_INFO;
+
+#pragma pack()
+
+#endif
+
diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h
new file mode 100644
index 0000000..5a810ec
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h
@@ -0,0 +1,67 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef __ACPI_NEXT_LIB_H__
+#define __ACPI_NEXT_LIB_H__
+
+#define EFI_ACPI_6_0_GIC_ITS_INIT(GicITSHwId, GicITSBase) \
+  { \
+    EFI_ACPI_6_0_GIC_ITS, sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+    GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD\
+  }
+
+#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT(    \
+    GicRBase, GicRlength)                                   \
+  {                                                                                  \
+    EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD,   \
+     GicRBase, GicRlength \
+  }
+
+#define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(                                              \
+    ProximityDomain, ACPIProcessorUID, Flags, ClockDomain)                                      \
+  {                                                                                             \
+    3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain ,                          \
+     ACPIProcessorUID,  Flags,  ClockDomain                                                     \
+  }
+
+#define EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(                                              \
+    ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags)               \
+  {                                                                                               \
+    1, sizeof (EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD,  \
+    AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags,       \
+    EFI_ACPI_RESERVED_QWORD                                                                       \
+  }
+
+#pragma pack(1)
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  64
+#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT                10
+
+
+typedef struct {
+  EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER          Header;
+  EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE                      Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
+  EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE                        Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+
+#pragma pack()
+#endif
+
diff --git a/Chips/Hisilicon/Include/Library/CpldIoLib.h b/Chips/Hisilicon/Include/Library/CpldIoLib.h
new file mode 100644
index 0000000..afc6b91
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/CpldIoLib.h
@@ -0,0 +1,22 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _CPLD_IO_LIB_H_
+#define _CPLD_IO_LIB_H_
+
+VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue);
+UINT8 ReadCpldReg(UINTN ulRegAddr);
+
+#endif /* _CPLD_IO_LIB_H_ */
diff --git a/Chips/Hisilicon/Include/Library/FdtUpdateLib.h b/Chips/Hisilicon/Include/Library/FdtUpdateLib.h
new file mode 100644
index 0000000..94fc3d3
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/FdtUpdateLib.h
@@ -0,0 +1,45 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef _FDTUPDATELIB_H_
+#define _FDTUPDATELIB_H_
+
+#define ADD_FILE_LENGTH  0x400
+
+typedef struct
+{
+  UINT32 BaseHigh;
+  UINT32 BaseLow;
+  UINT32 LengthHigh;
+  UINT32 LengthLow;
+}PHY_MEM_REGION;
+
+typedef struct
+{
+  UINT8 data0;
+  UINT8 data1;
+  UINT8 data2;
+  UINT8 data3;
+  UINT8 data4;
+  UINT8 data5;
+}MAC_ADDRESS;
+
+extern  EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr);
+
+#endif
+
+
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h
new file mode 100644
index 0000000..2663cad
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h
@@ -0,0 +1,930 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HW_MEM_INIT_LIB_H_
+#define _HW_MEM_INIT_LIB_H_
+
+#include <PlatformArch.h>
+
+#define I2C_CHANNEL     2
+#define MAX_I2C_DEV     6
+
+#define SPD_MODULE_PART         18
+#define SPD_MODULE_PART_DDR4    20
+
+#define NVRAM_ADDR      0x00D00000
+
+typedef enum {
+    DDR_FREQ_AUTO = 0,
+    DDR_FREQ_800,
+    DDR_FREQ_1000,
+    DDR_FREQ_1066,
+    DDR_FREQ_1200,
+    DDR_FREQ_1333,
+    DDR_FREQ_1400,
+    DDR_FREQ_1600,
+    DDR_FREQ_1800,
+    DDR_FREQ_1866,
+    DDR_FREQ_2000,
+    DDR_FREQ_2133,
+    DDR_FREQ_2200,
+    DDR_FREQ_2400,
+    DDR_FREQ_2600,
+    DDR_FREQ_2666,
+    DDR_FREQ_2800,
+    DDR_FREQ_2933,
+    DDR_FREQ_3000,
+    DDR_FREQ_3200,
+    DDR_FREQ_MAX
+} DDR_FREQUENCY_INDEX;
+
+typedef struct _DDR_FREQ_TCK
+{
+    UINT32      ddrFreq;
+    UINT32      ddrCk;
+}DDR_FREQ_TCK;
+
+typedef struct _GBL_CFG{
+
+
+}GBL_CFG;
+
+typedef struct _GBL_VAR{
+
+
+}GBL_VAR;
+
+typedef struct _GBL_NVDATA{
+
+
+}GBL_NVDATA;
+
+typedef struct _GOBAL {
+    const GBL_CFG Config;  // constant input data
+    GBL_VAR       Variable;    // variable, volatile data
+    GBL_NVDATA    NvData;  // variable, non-volatile data for S3, warm boot path
+    UINT32        PreBootFailed;
+}GOBAL, *PGOBAL;
+
+struct DDR_RANK {
+    BOOLEAN     Status;
+    UINT16      RttNom;
+    UINT16      RttPark;
+    UINT16      RttWr;
+    UINT16      MR0;
+    UINT16      MR1;
+    UINT16      MR2;
+    UINT16      MR3;
+    UINT16      MR4;
+    UINT16      MR5;
+    UINT16      MR6[9];
+};
+
+struct baseMargin {
+  INT16 n;
+  INT16 p;
+};
+
+struct rankMargin {
+  struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH];
+};
+
+typedef struct _DDR_DIMM{
+    BOOLEAN     Status;
+    UINT8       mapout;
+    UINT8       DramType;           //Byte 2
+    UINT8       ModuleType;         //Byte 3
+    UINT8       ExtendModuleType;
+    UINT8       SDRAMCapacity;      //Byte 4
+    UINT8       BankNum;
+    UINT8       BGNum;              //Byte 4 For DDR4
+    UINT8       RowBits;            //Byte 5
+    UINT8       ColBits;            //Byte 5
+    UINT8       SpdVdd;             //Byte 6
+    UINT8       DramWidth;          //Byte 7
+    UINT8       RankNum;            //Byte 7
+    UINT8       PrimaryBusWidth;    //Byte 8
+    UINT8       ExtensionBusWidth;  //Byte 8
+    UINT32      Mtb;
+    UINT32      Ftb;
+    UINT32      minTck;
+    UINT8       MtbDividend;
+    UINT8       MtbDivsor;
+    UINT8       nCL;
+    UINT32      nRCD;
+    UINT32      nRP;
+    UINT8       SPDftb;
+    UINT8       SpdMinTCK;
+    UINT8       SpdMinTCKFtb;
+    UINT8       SpdMaxTCK;
+    UINT8       SpdMinTCL;
+    UINT8       SpdMinTCLFtb;
+    UINT8       SpdMinTWR;
+    UINT8       SpdMinTRCD;
+    UINT8       SpdMinTRCDFtb;
+    UINT8       SpdMinTRRD;
+    UINT8       SpdMinTRRDL;
+    UINT16      SpdMinTRAS;
+    UINT16      SpdMinTRC;
+    UINT16      SpdMinTRCFtb;
+    UINT16      SpdMinTRFC;
+    UINT8       SpdMinTWTR;
+    UINT8       SpdMinTRTP;
+    UINT8       SpdMinTAA;
+    UINT8       SpdMinTAAFtb;
+    UINT8       SpdMinTFAW;
+    UINT8       SpdMinTRP;
+    UINT8       SpdMinTRPFtb;
+    UINT8       SpdMinTCCDL;
+    UINT8       SpdMinTCCDLFtb;
+    UINT8       SpdAddrMap;
+    UINT8       SpdModuleAttr;
+
+    UINT8       SpdModPart[SPD_MODULE_PART];         // Module Part Number
+    UINT8       SpdModPartDDR4[SPD_MODULE_PART_DDR4];     // Module Part Number DDR4
+    UINT16      SpdMMfgId;              // Module Mfg Id from SPD
+    UINT16      SpdRMId;              // Register Manufacturer Id
+    UINT16      SpdMMDate;              // Module Manufacturing Date
+    UINT32      SpdSerialNum;
+    UINT16      DimmSize;
+    UINT16      DimmSpeed;
+    UINT32      RankSize;
+    UINT8       SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode
+    struct DDR_RANK  Rank[MAX_RANK_DIMM];
+}DDR_DIMM;
+
+typedef struct {
+    UINT32      ddrcTiming0;
+    UINT32      ddrcTiming1;
+    UINT32      ddrcTiming2;
+    UINT32      ddrcTiming3;
+    UINT32      ddrcTiming4;
+    UINT32      ddrcTiming5;
+    UINT32      ddrcTiming6;
+    UINT32      ddrcTiming7;
+    UINT32      ddrcTiming8;
+}DDRC_TIMING;
+
+typedef struct _MARGIN_RESULT{
+    UINT32 OptimalDramVref[12];
+    UINT32 optimalPhyVref[18];
+}MARGIN_RESULT;
+
+typedef struct _DDR_Channel{
+    BOOLEAN     Status;
+    UINT8       CurrentDimmNum;
+    UINT8       CurrentRankNum;
+    UINT16      RankPresent;
+    UINT8       DramType;
+    UINT8       DramWidth;
+    UINT8       ModuleType;
+    UINT32      MemSize;
+    UINT32      tck;
+    UINT32      ratio;
+    UINT32      CLSupport;
+    UINT32      minTck;
+    UINT32      taref;
+    UINT32      nAA;
+    UINT32      nAOND;
+    UINT32      nCKE;
+    UINT32      nCL;
+    UINT32      nCCDL;
+    UINT32      nCKSRX;
+    UINT32      nCKSRE;
+    UINT32      nCCDNSW;
+    UINT32      nCCDNSR;
+    UINT32      nFAW;
+    UINT32      nMRD;
+    UINT32      nMOD;
+    UINT32      nRCD;
+    UINT32      nRRD;
+    UINT32      nRRDL;
+    UINT32      nRAS;
+    UINT32      nRC;
+    UINT32      nRFC;
+    UINT32      nRFCAB;
+    UINT32      nRTP;
+    UINT32      nRTW;
+    UINT32      nRP;
+    UINT32      nSRE;
+    UINT32      nWL;
+    UINT32      nWR;
+    UINT32      nWTR;
+    UINT32      nWTRL;
+    UINT32      nXARD;
+    UINT32      nZQPRD;
+    UINT32      nZQINIT;
+    UINT32      nZQCS;
+    UINT8       cwl;  //tWL?
+    UINT8       pl;     //parity latency
+    UINT8       wr_pre_2t_en;
+    UINT8       rd_pre_2t_en;
+    UINT8       cmd_2t_en;
+    UINT8       parity_en;
+    UINT8       wr_dbi_en;
+    UINT8       wr_dm_en;
+    UINT8       ddr4_crc_en;
+    UINT16      emrs0;
+    UINT16      emrs1;
+    UINT16      emrs1Wr;
+    UINT16      emrs2;
+    UINT16      emrs3;
+    UINT16      emrs4;
+    UINT16      emrs5;
+    UINT16      emrs5Wr;
+    UINT16      emrs6;
+    UINT16      emrs7;
+    UINT8       phy_rddata_set;
+    UINT8       phyif_tim_rdcs;
+    UINT8       phyif_tim_rden;
+    UINT8       phyif_tim_wden;
+    UINT8       phyif_tim_wdda;
+    UINT8       phyif_tim_wdcs;
+    UINT8       per_cs_training_en;
+    UINT32      phyRdDataEnIeDly;
+    UINT32      phyPadCalConfig;
+    UINT32      phyDqsFallRiseDelay;
+    UINT32      ddrcCfgDfiLat0;
+    UINT32      ddrcCfgDfiLat1;
+    UINT32      parityLatency;
+    UINT32      dimm_parity_en;
+    DDRC_TIMING ddrcTiming;
+    DDR_DIMM    Dimm[MAX_DIMM];
+    MARGIN_RESULT sMargin;
+}DDR_CHANNEL;
+
+typedef struct _NVRAM_RANK{
+    UINT16      MR0;
+    UINT16      MR1;
+    UINT16      MR2;
+    UINT16      MR3;
+    UINT16      MR4;
+    UINT16      MR5;
+    UINT16      MR6[9];
+}NVRAM_RANK;
+
+typedef struct _NVRAM_DIMM{
+    NVRAM_RANK      Rank[MAX_RANK_DIMM];
+}NVRAM_DIMM;
+
+
+typedef struct _NVRAM_CHANNEL{
+    NVRAM_DIMM      Dimm[MAX_DIMM];
+    UINT32          DDRC_CFG_ECC;
+    UINT32          DDRC_CFG_WORKMODE;
+    UINT32          DDRC_CFG_WORKMODE1;
+    UINT32          DDRC_CFG_WORKMODE2;
+    UINT32          DDRC_CFG_DDRMODE;
+    UINT32          DDRC_CFG_DIMM;
+    UINT32          DDRC_CFG_RNKVOL_0;
+    UINT32          DDRC_CFG_RNKVOL_1;
+    UINT32          DDRC_CFG_RNKVOL_2;
+    UINT32          DDRC_CFG_RNKVOL_3;
+    UINT32          DDRC_CFG_RNKVOL_4;
+    UINT32          DDRC_CFG_RNKVOL_5;
+    UINT32          DDRC_CFG_RNKVOL_6;
+    UINT32          DDRC_CFG_RNKVOL_7;
+    UINT32          DDRC_CFG_RNKVOL_8;
+    UINT32          DDRC_CFG_RNKVOL_9;
+    UINT32          DDRC_CFG_RNKVOL_10;
+    UINT32          DDRC_CFG_RNKVOL_11;
+    UINT32          DDRC_CFG_ODT_0;
+    UINT32          DDRC_CFG_ODT_1;
+    UINT32          DDRC_CFG_ODT_2;
+    UINT32          DDRC_CFG_ODT_3;
+    UINT32          DDRC_CFG_ODT_4;
+    UINT32          DDRC_CFG_ODT_5;
+    UINT32          DDRC_CFG_ODT_6;
+    UINT32          DDRC_CFG_ODT_7;
+    UINT32          DDRC_CFG_ODT_8;
+    UINT32          DDRC_CFG_ODT_9;
+    UINT32          DDRC_CFG_ODT_10;
+    UINT32          DDRC_CFG_ODT_11;
+    UINT32          DDRC_CFG_TIMING0;
+    UINT32          DDRC_CFG_TIMING1;
+    UINT32          DDRC_CFG_TIMING2;
+    UINT32          DDRC_CFG_TIMING3;
+    UINT32          DDRC_CFG_TIMING4;
+    UINT32          DDRC_CFG_TIMING5;
+    UINT32          DDRC_CFG_TIMING6;
+    UINT32          DDRC_CFG_TIMING7;
+    UINT32          DDRC_CFG_DFI_LAT0;
+    UINT32          DDRC_CFG_DFI_LAT1;
+    UINT32          DDRC_CFG_DDRPHY;
+    UINT32          Config[24];
+    BOOLEAN         Status;
+}NVRAM_CHANNEL;
+
+typedef struct _NVRAM{
+    UINT32          NvramCrc;
+    NVRAM_CHANNEL   Channel[MAX_SOCKET][MAX_CHANNEL];
+    UINT32          DdrFreqIdx;
+
+}NVRAM;
+
+typedef struct _MEMORY{
+    UINT8           Config0;
+    UINT8           marginTest;
+    UINT8           Config1[5];
+    UINT8           ErrorBypass; //register of spd mirror mode
+    UINT32          Config2;
+}MEMORY;
+
+typedef struct _NUMAINFO{
+    UINT8           NodeId;
+    UINT64          Base;
+    UINT64          Length;
+    UINT32          ScclInterleaveEn;
+}NUMAINFO;
+
+
+typedef struct _GBL_DATA
+{
+    DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
+    UINT8       DramType;
+    UINT8       CurrentDimmNum;
+    UINT8       CurrentRankNum;
+    UINT8       MaxSPCNum;
+    UINT32      Freq;
+    UINT32      SpdTckMtb;
+    UINT32      SpdTckFtb;
+    UINT32      SpdTck;
+    UINT32      Tck;
+    UINT32      DdrFreqIdx;
+    UINT32      DevParaFreqIdx; //Maximum frequency of DDR device
+    UINT32      MemSize;
+    UINT32      EccEn;
+
+    BOOLEAN     SetupExist;
+    UINT8       warmReset;
+    UINT8       needColdReset;
+
+    UINT8       cl;
+    UINT8       cwl;
+    UINT8       pl;
+    UINT8       wr_pre_2t_en;
+    UINT8       rd_pre_2t_en;
+    UINT8       cmd_2t_en;
+    UINT8       ddr4_parity_en;
+    UINT8       wr_dbi_en;
+    UINT8       wr_dm_en;
+    UINT8       ddr4_crc_en;
+    UINT16      emrs0;
+    UINT16      emrs1;
+    UINT16      emrs2;
+    UINT16      emrs3;
+    UINT16      emrs4;
+    UINT16      emrs5;
+    UINT16      emrs6;
+    UINT16      emrs7;
+    UINT8       phy_rddata_set;
+    UINT8       phyif_tim_rdcs;
+    UINT8       phyif_tim_rden;
+    UINT8       phyif_tim_wden;
+    UINT8       phyif_tim_wdda;
+    UINT8       phyif_tim_wdcs;
+    UINT8       dimm_trtr;
+    UINT8       dimm_twtw;
+    UINT8       rnk_trtr;
+    UINT8       rnk_twtw;
+    UINT8       rnk_trtw;
+    UINT8       rnk_twtr;
+    UINT8       per_cs_training_en;
+    UINT8       scale;
+    UINT8       ddrFreq;
+    UINT8       debugNeed;
+    UINT8       ddr3OdtEnable;
+    double      fprd;
+    BOOLEAN     chipIsEc;
+    NVRAM       nvram;
+    MEMORY      mem;
+    NUMAINFO    NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
+
+}GBL_DATA, *pGBL_DATA;
+
+typedef union {
+    struct {
+        UINT16  freqIndex:4;         //Frequency Index;
+        UINT16  slot0:4;        //Channel slot0 for DIMM
+        UINT16  slot1:4;        //Channel slot1 for DIMM
+        UINT16  slot2:4;        //Channel slot2 for DIMM
+    }Bits;
+    UINT16      Data;
+}ODT_VALUE_INDEX;
+
+typedef union {
+    struct {
+        UINT8   RTTNom:3;
+        UINT8   reserved_3:1;
+        UINT8   RTTWr:2;
+        UINT8   reserved_6:2;
+    }Bits;
+    UINT8      Data;
+}ODT_RTT_VALUE_DDR3;
+
+typedef union {
+    struct {
+        UINT8   RTTNom:3;
+        UINT8   RTTPark:3;
+        UINT8   RTTWr:2;
+    }Bits;
+    UINT8      Data;
+}ODT_RTT_VALUE_DDR4;
+
+typedef union {
+    struct {
+        UINT16  tarDimm:2;      // target DIMM
+        UINT16  tarRank:2;      // target Rank
+        UINT16  slot0:4;        // Channel slot0 for DIMM
+        UINT16  slot1:4;        // Channel slot1 for DIMM
+        UINT16  slot2:4;        // Channel slot2 for DIMM
+    }Bits;
+    UINT16      Data;
+}ODT_ACTIVE_INDEX;
+
+struct ODT_VALUE_STRUCT_DDR3 {
+   UINT16       config;                                 // ODT_VALUE_INDEX
+   UINT8        dramOdt[MAX_DIMM][MAX_RANK_DIMM];       // ODT_VALUE_RTT_DDR3
+};
+
+struct ODT_VALUE_STRUCT_DDR4 {
+    UINT16      config;
+    UINT8       dramOdt[MAX_DIMM][MAX_RANK_DIMM];
+};
+
+struct ODT_ACTIVE_STRUCT {
+    UINT16      config;             // ODT config index
+    UINT16      actBits[2];         // WR :Bits[3;0] = D0_R[3:0] Bits[7:4] = D1_R[3:0] Bits[11:8] = D2_R[3:0]
+};
+
+// JEDEC manufacturer IDs from JEP-106
+#define MFGID_AENEON    0x5705
+#define MFGID_QIMONDA   0x5105
+#define MFGID_NEC       0x1000
+#define MFGID_IDT       0xB300
+#define MFGID_TI        0x9700
+#define MFGID_HYNIX     0xAD00
+#define MFGID_MICRON    0x2C00
+#define MFGID_INFINEON  0xC100
+#define MFGID_SAMSUNG   0xCE00
+#define MFGID_TEK       0x3D00
+#define MFGID_KINGSTON  0x9801
+#define MFGID_ELPIDA    0xFE02
+#define MFGID_SMART     0x9401
+#define MFGID_AGILENT   0xC802
+#define MFGID_NANYA     0x0B03
+#define MFGID_INPHI     0xB304
+#define MFGID_MONTAGE   0x3206
+#define MFGID_RAMAXEL   0x4304
+
+//
+// DDR3 frequencies 800 - 2667
+// DDR4 frequencies 1333 - 3200
+//
+#define DDR_800  0   // tCK(ns)=2.5
+#define DDR_1000 1   // tCK(ns)=2.0
+#define DDR_1066 2   // tCK(ns)=1.875
+#define DDR_1200 3   // tCK(ns)=1.667
+#define DDR_1333 4   // tCK(ns)=1.5
+#define DDR_1400 5   // tCK(ns)=1.429
+#define DDR_1600 6   // tCK(ns)=1.25
+#define DDR_1800 7   // tCK(ns)=1.11
+#define DDR_1866 8   // tCK(ns)=1.07
+#define DDR_2000 9   // tCK(ns)=1.0
+#define DDR_2133 10  // tCK(ns)=0.9375
+#define DDR_2200 11  // tCK(ns)=0.909
+#define DDR_2400 12  // tCK(ns)=0.833
+#define DDR_2600 13  // tCK(ns)=0.769
+#define DDR_2666 14  // tCK(ns)=0.750
+#define DDR_2800 15  // tCK(ns)=0.714
+#define DDR_2933 16  // tCK(ns)=0.682
+#define DDR_3000 17  // tCK(ns)=0.667
+#define DDR_3200 18  // tCK(ns)=0.625
+#define DDR_MAX  (DDR_3200)
+
+#define FREQUENCY_MTB_OFFSET            1000000
+#define FREQUENCY_FTB_OFFSET               1000
+
+//
+#define DDR_800_TCK_MIN                 25000
+#define DDR_1000_TCK_MIN                20000
+#define DDR_1067_TCK_MIN                18750
+#define DDR_1200_TCK_MIN                16670
+#define DDR_1333_TCK_MIN                15000
+#define DDR_1400_TCK_MIN                14290
+#define DDR_1600_TCK_MIN                12500
+#define DDR_1800_TCK_MIN                11100
+#define DDR_1867_TCK_MIN                10710
+#define DDR_2000_TCK_MIN                10000
+#define DDR_2133_TCK_MIN                 9380
+#define DDR_2200_TCK_MIN                 9090
+#define DDR_2400_TCK_MIN                 8330
+#define DDR_2600_TCK_MIN                 7690
+#define DDR_2667_TCK_MIN                 7500
+#define DDR_2800_TCK_MIN                 7140
+#define DDR_2933_TCK_MIN                 6820
+#define DDR_3000_TCK_MIN                 6670
+#define DDR_3200_TCK_MIN                 6250
+
+
+//
+// Serial Presence Detect bytes (JEDEC revision 1.0)
+//
+#define SPD_SIZE              0     // Bytes used, Device size, CRC coverage
+#define SPD_REVISION          1     // SPD Encoding Revision
+#define SPD_KEY_BYTE          2     // DRAM Device Type
+  #define SPD_TYPE_DDR3       0x0B  // DDR3 SDRAM
+  #define SPD_TYPE_DDR4       0x0C  // DDR4 SDRAM
+#define SPD_KEY_BYTE2         3     // Module Type and Thickness (RDIMM or UDIMM)
+  #define SPD_RDIMM           1     // Module type is RDIMM
+  #define SPD_UDIMM           2     // Module type is UDIMM
+  #define SPD_SODIMM          3     // Module type is SODIMM
+  #define SPD_MICRO_DIMM      4     // Module type is Micro-DIMM
+  #define SPD_LRDIMM_DDR4     4     // Module type is LRDIMM (DDR4)
+  #define SPD_MINI_RDIMM      5     // Module type is Mini-RDIMM
+  #define SPD_MINI_UDIMM      6     // Module type is Mini-UDIMM
+  #define SPD_MINI_CDIMM      7     // Module type is Mini-CDIMM
+  #define SPD_ECC_SO_UDIMM    9     // Module type is 72b-SO-UDIMM
+  #define SPD_ECC_SO_RDIMM    8     // Module type is 72b-SO-RDIMM
+  #define SPD_ECC_SO_CDIMM    10    // Module type is 72b-SO-CDIMM
+  #define SPD_LRDIMM          11    // Module type is LRDIMM
+  #define SPD_UDIMM_ECC       18    // Module type is UDIMM-ECC
+#define SPD_SDRAM_BANKS       4     // SDRAM Density and number of internal banks
+  #define SPD_1Gb             2     // Total SDRAM Capacity 1 Gigabits
+  #define SPD_2Gb             3     // Total SDRAM Capacity 2 Gigabits
+  #define SPD_4Gb             4     // Total SDRAM Capacity 4 Gigabits
+  #define SPD_8Gb             5     // Total SDRAM Capacity 8 Gigabits
+  #define SPD_16Gb            6     // Total SDRAM Capacity 16 Gigabits
+  #define SPD_32Gb            7     // Total SDRAM Capacity 32 Gigabits
+#define SPD_SDRAM_ADDR        5     // Number of Row and Column address bits
+  #define SPD_ROW_12          0     // 12 row bits
+  #define SPD_ROW_13          1     // 13 row bits
+  #define SPD_ROW_14          2     // 14 row bits
+  #define SPD_ROW_15          3     // 15 row bits
+  #define SPD_ROW_16          4     // 16 row bits
+  #define SPD_ROW_17          5     // 17 row bits
+  #define SPD_ROW_18          6     // 18 row bits
+  #define SPD_COL_9           0     // 9 colum bits
+  #define SPD_COL_10          1     // 10 colum bits
+  #define SPD_COL_11          2     // 11 colum bits
+  #define SPD_COL_12          3     // 12 colum bits
+#define SPD_VDD_SUPPORT       6     // Vdd DIMM supports
+  #define SPD_VDD_150         0     // Module Supports 1.50V
+  #define SPD_VDD_135         BIT1  // Module Supports 1.35V
+  #define SPD_VDD_125         BIT2  // Module Supports 1.25V
+#define SPD_MODULE_ORG_DDR3   7     // Number of Ranks and SDRAM device width
+#define SPD_MODULE_ORG_DDR4   12    // DDR4 Module Organization
+  #define DEVICE_WIDTH_X4     0     // SDRAM device width = 4 bits
+  #define DEVICE_WIDTH_X8     1     // SDRAM device width = 8 bits
+  #define DEVICE_WIDTH_X16    2     // SDRAM device width = 16 bits
+  #define SPD_NUM_RANKS_1   0
+  #define SPD_NUM_RANKS_2   1
+  #define SPD_NUM_RANKS_4   3
+  #define SPD_NUM_RANKS_8   4
+#define SPD_MEM_BUS_WID     8     // Width of SDRAM memory bus
+#define SPD_FTB             9     // Timebase for fine grain timing calculations
+#define SPD_MTB_DIVEND      10    // Medium Time Base Dividend
+#define SPD_MTB_DIVISOR     11    // Medium Time Base Divisor
+#define SPD_MIN_TCK         12    // Minimum cycle time (at max CL)
+  #define SPD_TCKMIN_800      20    // tCK(MTB)=20, tCK(ns)=2.5
+  #define SPD_TCKMIN_1067     15    // tCK(MTB)=15, tCK(ns)=1.875
+  #define SPD_TCKMIN_1333     12    // tCK(MTB)=12, tCK(ns)=1.5
+  #define SPD_TCKMIN_1600     10    // tCK(MTB)=10, tCK(ns)=1.25
+  #define SPD_TCKMIN_1867     9     // tCK(MTB)=9, tCK(ns)=1.07
+  #define SPD_TCKMIN_2133     8     // tCK(MTB)=8, tCK(ns)=0.9375
+  #define SPD_TCKMIN_2400     7     // tCK(MTB)=7, tCK(ns)=.833
+#define SPD_CAS_LT_SUP_LSB  14    // CAS Latencies Supported, Least Significant Byte
+#define SPD_CAS_LT_SUP_MSB  15    // CAS Latencies Supported, Most Significant Byte
+#define SPD_MIN_TAA         16    // Minimum CAS Latency Time (tAAmin)
+#define SPD_MIN_TWR         17    // Minimum Write Recovery Time
+#define SPD_MIN_TRCD        18    // Minimum RAS to CAS delay
+#define SPD_MIN_TRRD        19    // Minimum Row active to row active delay
+#define SPD_MIN_TRP         20    // Minimum Row Precharge time
+#define SPD_EXT_TRC_TRAS    21    // Upper nibbles for min tRAS and tRC
+#define SPD_MIN_TRAS        22    // Minimum Active to Precharge time
+#define SPD_MIN_TRC         23    // Minimum Active to Active/Refresh time
+#define SPD_MIN_TRFC_LSB    24    // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC_MSB    25    // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TWTR        26    // Minimum Internal Write to Read command delay
+#define SPD_MIN_TRTP        27    // Minimum Internal Read to Precharge command delay
+#define SPD_UN_TFAW         28    // Upper Nibble for tFAW
+#define SPD_MIN_TFAW        29    // Minimum Four Activate Window Delay Time (tFAWmin)
+#define SPD_OD_SUP          30    // SDRAM Output Drivers Supported
+#define SPD_RFSH_OPT        31    // SDRAM Refresh Options
+  #define ETR                 BIT0  // Bit location for Extended Temp Range
+  #define ETRR                BIT1  // Bit location for Extended Temp Refresh Rate
+  #define ASR                 BIT2  // Bit location for Automatic Self Refresh
+  #define ODTS                BIT3  // Bit location for On-die Thermal Sensor
+#define SPD_DIMM_TS         32    // Module Temperature Sensor
+#define SPD_SDRAM_TYPE      33    // SDRAM device type
+#define SPD_FTB_TCK         34    // Fine Offset for SDRAM tCK
+#define SPD_FTB_TAA         35    // Fine Offset for SDRAM tAA
+#define SPD_FTB_TRCD        36    // Fine Offset for SDRAM tRCD
+#define SPD_FTB_TRP         37    // Fine Offset for SDRAM tRP
+#define SPD_FTB_TRC         38    // Fine Offset for SDRAM tRC
+#define SPD_OPT_FEAT        41    // SDRAM Optional Features
+  #define SPD_PTRR          BIT7  // Indicates if the DIMM is pTRR compliant
+
+  // UDIMM specific bytes
+  // Applicable when Module Type (key byte 3) = 2, 3, 4, 6, or 8
+
+#define SPD_ADDR_MAP_FECTD  63    // Address Mapping from Edge Connector to DRAM
+
+  // RDIMM specific bytes
+  // Applicable when Module Type (key byte 3) = 1, 5, or 9
+
+#define SPD_RDIMM_ATTR      63    // RDIMM module attributes
+#define SPD_DIMM_HS         64    // Module Heat Spreader Solution
+#define SPD_REG_VEN_LSB     65    // Register Vendor ID LSB
+#define SPD_REG_VEN_MSB     66    // Register Vendor ID MSB
+#define SPD_REG_REV         67    // Register Revision
+#define SPD_CNTL_0          69    // Register Control Word 0 & 1
+#define SPD_CNTL_1          70    // Register Control Word 2 & 3
+#define SPD_CNTL_2          71    // Register Control Word 4 & 5
+#define SPD_CNTL_3          72    // Register Control Word 6 & 7   (reserved)
+#define SPD_CNTL_4          73    // Register Control Word 8 & 9   (reserved)
+#define SPD_CNTL_5          74    // Register Control Word 10 & 11 (reserved)
+#define SPD_CNTL_6          75    // Register Control Word 12 & 13 (reserved)
+#define SPD_CNTL_7          76    // Register Control Word 14 & 15 (reserved)
+
+  // LRDIMM specific bytes
+  // Applicable when Module Type (key byte 3) = 0xB
+  // Based on DDR3 SPD 1.0 Document Release 2.1 draft, dated May 27, 2011
+
+#define SPD_LRDIMM_ATTR       63    // LRDIMM module attributes
+#define SPD_LRBUF_REV         64    // LR Buffer Revision
+#define SPD_LRBUF_VEN_LSB     65    // LR Buffer Vendor ID LSB
+#define SPD_LRBUF_VEN_MSB     66    // LR Buffer Vendor ID MSB
+#define SPD_LR_F0_RC2_3       67    // LR Buffer Function 0, Control Word 2 & 3
+#define SPD_LR_F0_RC4_5       68    // LR Buffer Function 0, Control Word 4 & 5
+#define SPD_LR_F1_RC8_11      69    // LR Buffer Function 1, Control Word 8 & 11
+#define SPD_LR_F1_RC12_13     70    // LR Buffer Function 1, Control Word 12 & 13
+#define SPD_LR_F1_RC14_15     71    // LR Buffer Function 1, Control Word 14 & 15
+
+  // Speed bin 0 = 800 & 1066
+#define SPD_LR_SB0_MDQ_DS_ODT       72    // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB0_DR01_QODT_ACT    73    // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB0_DR23_QODT_ACT    74    // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB0_DR45_QODT_ACT    75    // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB0_DR67_QODT_ACT    76    // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB0_MR1_2_RTT        77    // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+  // Speed bin 1 = 1333 & 1600
+#define SPD_LR_SB1_MDQ_DS_ODT       78    // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB1_DR01_QODT_ACT    79    // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB1_DR23_QODT_ACT    80    // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB1_DR45_QODT_ACT    81    // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB1_DR67_QODT_ACT    82    // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB1_MR1_2_RTT        83    // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+  // Speed bin 2 = 1866 & 2133
+#define SPD_LR_SB2_MDQ_DS_ODT       84    // LR Buffer Function 3, Control Word 8 & 9
+#define SPD_LR_SB2_DR01_QODT_ACT    85    // LR Buffer Function 3 & 4, Control Word 10 & 11
+#define SPD_LR_SB2_DR23_QODT_ACT    86    // LR Buffer Function 5 & 6, Control Word 10 & 11
+#define SPD_LR_SB2_DR45_QODT_ACT    87    // LR Buffer Function 7 & 8, Control Word 10 & 11
+#define SPD_LR_SB2_DR67_QODT_ACT    88    // LR Buffer Function 9 & 10, Control Word 10 & 11
+#define SPD_LR_SB2_MR1_2_RTT        89    // LR Buffer SMBus offsets 0xC0 - 0xC7
+
+#define SPD_LR_150_MIN_MOD_DELAY    90    // LR DIMM minimum DQ Read propagation delay at 1.5V
+#define SPD_LR_150_MAX_MOD_DELAY    91    // LR DIMM maximum DQ Read propagation delay at 1.5V
+#define SPD_LR_135_MIN_MOD_DELAY    92    // LR DIMM minimum DQ Read propagation delay at 1.35V
+#define SPD_LR_135_MAX_MOD_DELAY    93    // LR DIMM maximum DQ Read propagation delay at 1.35V
+#define SPD_LR_12x_MIN_MOD_DELAY    94    // LR DIMM minimum DQ Read propagation delay at 1.2xV
+#define SPD_LR_12x_MAX_MOD_DELAY    95    // LR DIMM maximum DQ Read propagation delay at 1.2xV
+
+#define SPD_LR_PERS_BYTE_0          102   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_1          103   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_2          104   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_3          105   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_4          106   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_5          107   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_6          108   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_7          109   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_8          110   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_9          111   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_10         112   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_11         113   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_12         114   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_13         115   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTE_14         116   // LR DIMM Personality Byte
+#define SPD_LR_PERS_BYTES_TOTAL     15    // LR DIMM Total number of Personality Bytes
+
+  // End module specific section
+
+#define SPD_MMID_LSB        117   // Module Manufacturer ID Code, Least Significant Byte
+#define SPD_MMID_MSB        118   // Module Manufacturer ID Code, Mostst Significant Byte
+#define SPD_MM_LOC          119   // Module Manufacturing Location
+#define SPD_MM_DATE         120   // Module Manufacturing Date 120-121
+#define SPD_MODULE_SN       122   // Module Serial Number 122-125
+#define SPD_CRC_LSB         126   // LSB of 16-bit CRC
+#define SPD_CRC_MSB         127   // MSB of 16-bit CRC
+
+#define SPD_MODULE_PN       128   // Module Part Number 128-145
+#define SPD_MODULE_RC       146   // Module Revision Code 146-147
+#define SPD_DRAM_MIDC_LSB   148   // DRAM Manufacturer ID Code, Least Significant Byte
+#define SPD_DRAM_MIDC_MSB   149   // DRAM Manufacturer ID Code, Most Significant Byte
+#ifdef  MEM_NVDIMM_EN
+#define SPD_NVDIMM_ID_N     174   // If NVDIMM value will be 'N'
+#define SPD_NVDIMM_ID_V     175   // If NVDIMM value will be 'V'
+#endif  //MEM_NVDIMM_EN
+#define SPD_BYTE_200        200   // Fixed value 0xBE
+
+  //
+  // DDR4 Specific Bytes
+  //
+#define SPD_SDRAM_TYPE_DDR4   6     // SDRAM Device Type (DDR4)
+#define SPD_OPT_FEAT_DDR4     7     // SDRAM Optional Features (DDR4)
+  #define SPD_MAC_MASK        BIT0 | BIT1 | BIT2  // Mask for Maximum Active Count field
+  #define SPD_TRR_IMMUNE      BIT3  // Indicates this DIMM does not require DRAM Maintenance
+#define SPD_RFSH_OPT_DDR4     8     // SDRAM Refresh Options (DDR4)
+#define SPD_VDD_DDR4          11    // Vdd DIMM supports (DDR4)
+  #define SPD_VDD_120         3     // Module operable and endurant 1.20V
+#define SPD_MODULE_ORG_DDR4   12    // Number of Ranks and SDRAM device width (DDR4)
+#define SPD_MEM_BUS_WID_DDR4  13    // Width of SDRAM memory bus
+#define SPD_DIMM_TS_DDR4      14    // Module Thermal Sensor
+#define SPD_TB_DDR4           17    // Timebase [3:2] MTB, [1:0] FTB
+#define SPD_MIN_TCK_DDR4      18    // Minimum cycle time
+  #define SPD_TCKMIN_DDR4_1600      10  // tCK(MTB)=10, tCK(ns)=1.25
+  #define SPD_TCKMIN_DDR4_1866      9   // tCK(MTB)=9, tCK(ns)=1.071
+  #define SPD_TCKMIN_DDR4_2133      8   // tCK(MTB)=8, tCK(ns)=.938
+  #define SPD_TCKMIN_DDR4_2400      7   // tCK(MTB)=7, tCK(ns)=.833
+#define SPD_MAX_TCK_DDR4      19    // Maximum cycle time
+#define SPD_CAS_LT_SUP_1_DDR4 20    // CAS Latencies Supported, first byte
+#define SPD_CAS_LT_SUP_2_DDR4 21    // CAS Latencies Supported, second byte
+#define SPD_CAS_LT_SUP_3_DDR4 22    // CAS Latencies Supported, third byte
+#define SPD_CAS_LT_SUP_4_DDR4 23    // CAS Latencies Supported, fourth byte
+#define SPD_MIN_TAA_DDR4      24    // Minimum CAS Latency Time (tAAmin)
+#define SPD_MIN_TRCD_DDR4     25    // Minimum RAS to CAS delay
+#define SPD_MIN_TRP_DDR4      26    // Minimum Row Precharge time
+#define SPD_EXT_TRC_TRAS_DDR4 27    // Upper nibbles for min tRAS and tRC
+#define SPD_MIN_TRAS_DDR4     28    // Minimum Active to Precharge time
+#define SPD_MIN_TRC_DDR4      29    // Minimum Active to Active/Refresh time
+#define SPD_MIN_TRFC1_LSB_DDR4 30    // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC1_MSB_DDR4 31    // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TRFC2_LSB_DDR4 32    // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC2_MSB_DDR4 33    // Minimum Refresh Recovery time most-significant byte
+#define SPD_MIN_TRFC3_LSB_DDR4 34    // Minimum Refresh Recovery time least-significant byte
+#define SPD_MIN_TRFC3_MSB_DDR4 35    // Minimum Refresh Recovery time most-significant byte
+#define SPD_TFAW_UPPER_DDR4   36    // Upper nibble for tFAW
+#define SPD_MIN_TFAW_DDR4     37    // Minimum For Active Window Delay Time (tFAW)
+#define SPD_MIN_TRRDS_DDR4    38    // Minimum Active to Active Delay Time tRRD_S Different Bank Group
+#define SPD_MIN_TRRDL_DDR4    39    // Minimum Active to Active Delay Time tRRD_L Same Bank Group
+#define SPD_MIN_TCCDL_DDR4    40    // Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
+#define SPD_FTB_TCCDL_DDR4    117   // Fine offset for tCCD_L
+#define SPD_FTB_TRRDL_DDR4    118   // Fine offset for tRRD_L
+#define SPD_FTB_TRRDS_DDR4    119   // Fine offset for tRRD_S
+#define SPD_FTB_TRC_DDR4      120   // Fine offset for TRC
+#define SPD_FTB_TRP_DDR4      121   // Fine offset for TRP
+#define SPD_FTB_TRCD_DDR4     122   // Fine offset for TRCD
+#define SPD_FTB_TAA_DDR4      123   // Fine offset for TAA
+#define SPD_FTB_MAX_TCK_DDR4  124   // Fine offset for max TCK
+#define SPD_FTB_MIN_TCK_DDR4  125   // Fine offset for min TCK
+#define SPD_MIRROR_UNBUFFERED 131   // Unbuffered:Address Mapping from Edge Connector to DRAM
+#define SPD_MIRROR_REGISTERED 136   // Registered:Address Address Mapping from Register to DRAM
+
+#define SPD_MMID_LSB_DDR4     320   // Module Manufacturer ID Code, Least Significant Byte
+#define SPD_MMID_MSB_DDR4     321   // Module Manufacturer ID Code, Most Significant Byte
+#define SPD_MM_LOC_DDR4       322   // Module Manufacturing Location
+#define SPD_MM_DATE_DDR4      323   // Module Manufacturing Date 323-324
+#define SPD_MODULE_SN_DDR4    325   // Module Serial Number 325-328
+#define SPD_MODULE_PN_DDR4    329   // Module Part Number 329-348
+#define SPD_MODULE_RC_DDR4    349   // Module Revision Code
+#define SPD_DRAM_MIDC_LSB_DDR4 350  // DRAM Manufacturer ID Code, Least Significant Byte
+#define SPD_DRAM_MIDC_MSB_DDR4 351  // DRAM Manufacturer ID Code, Most Significant Byte
+#define SPD_DRAM_REV_DDR4     352   // DRAM Revision ID
+#define SPD_CRC_LSB_DDR4      382   // LSB of 16-bit CRC
+#define SPD_CRC_MSB_DDR4      383   // MSB of 16-bit CRC
+
+  // Begin DDR4 module specific section
+#define SPD_MODULE_NH_DDR4    128    // Module Nominal Height
+#define SPD_MODULE_MT_DDR4    129    // Module Maximum Thickness
+#define SPD_REF_RAW_CARD_DDR4 130    // Reference Raw Card Used
+
+  // UDIMM specific bytes
+  // Applicable when Module Type (key byte 3) = 2
+#define SPD_ADDR_MAP_FECTD_DDR4 131    // Address Mapping from Edge Connector to DRAM
+
+  // RDIMM specific bytes
+  // Applicable when Module Type (key byte 3) = 1
+#define SPD_RDIMM_ATTR_DDR4    131   // RDIMM module attributes
+#define SPD_DIMM_HS_DDR4       132   // Module Heat Spreader Solution
+#define SPD_REG_VEN_LSB_DDR4   133   // Register Vendor ID LSB
+#define SPD_REG_VEN_MSB_DDR4   134   // Register Vendor ID MSB
+#define SPD_REG_REV_DDR4       135   // Register Revision
+#define SPD_ADD_MAPPING_DDR4   136   // Address mapping from Reg to DRAM
+#define SPD_REG_OD_CTL_DDR4    137   // Register Output Drive Strength for Control
+#define SPD_REG_OD_CK_DDR4     138   // Register Output Drive Strength for Clock
+
+  // LRDIMM specific bytes
+  // Applicable when Module Type (key byte 3) = 0x4
+#define SPD_LRDIMM_ATTR_DDR4   131   // LRDIMM module attributes
+#define SPD_LRBUF_HS_DDR4      132   // LR Buffer Heat Spreader Solution
+#define SPD_LRBUF_VEN_LSB_DDR4 133   // LR Buffer Vendor ID LSB
+#define SPD_LRBUF_VEN_MSB_DDR4 134   // LR Buffer Vendor ID MSB
+#define SPD_LRBUF_REV_DDR4     135   // LR Buffer Register Revision
+#define SPD_LRBUF_DB_REV_DDR4  139   // LR Buffer Data Buffer Revision
+#define SPD_LRBUF_DRAM_VREFDQ_R0_DDR4 140 // LR Buffer DRAM VrefDQ for Package Rank 0
+#define SPD_LRBUF_DRAM_VREFDQ_R1_DDR4 141 // LR Buffer DRAM VrefDQ for Package Rank 1
+#define SPD_LRBUF_DRAM_VREFDQ_R2_DDR4 142 // LR Buffer DRAM VrefDQ for Package Rank 2
+#define SPD_LRBUF_DRAM_VREFDQ_R3_DDR4 143 // LR Buffer DRAM VrefDQ for Package Rank 3
+#define SPD_LRBUF_DB_VREFDQ_DDR4 144 // LR Data Buffer VrefDQ for DRAM Interface
+#define SPD_LRBUF_DB_DS_RTT_LE1866_DDR4 145 // LR Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
+#define SPD_LRBUF_DB_DS_RTT_GT1866_LE2400_DDR4 146 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DB_DS_RTT_GT2400_LE3200_DDR4 147 // LR Data Buffer MDQ Drive Strength and RTT for data rate > 2400 and <= 3200
+#define SPD_LRBUF_DRAM_DS_DDR4 148   // LR Buffer DRAM Drive Strength (for data rates <= 1866, 1866 < data rate <= 2400, and 2400 < data rate <= 3200)
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_LE1866_DDR4 149 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT1866_LE2400_DDR4 150 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DRAM_ODT_WR_NOM_GT2400_LE3200_DDR4 151 // LR Buffer DRAM ODT (RTT_WR and RTT_NOM) for data rate > 2400 and <= 3200
+#define SPD_LRBUF_DRAM_ODT_PARK_LE1866_DDR4 152 // LR Buffer DRAM ODT (RTT_PARK) for data rate <= 1866
+#define SPD_LRBUF_DRAM_ODT_PARK_GT1866_LE2400_DDR4 153 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 1866 and <= 2400
+#define SPD_LRBUF_DRAM_ODT_PARK_GT2400_LE3200_DDR4 154 // LR Buffer DRAM ODT (RTT_PARK) for data rate > 2400 and <= 3200
+
+  //
+  // End DDR4 Specific Bytes
+  //
+#define BANK0   0
+#define BANK1   BIT0
+#define BANK2   BIT1
+#define BANK3   BIT0 + BIT1
+#define BANK4   BIT2
+#define BANK5   BIT2 + BIT0
+#define BANK6   BIT2 + BIT1
+#define BANK7   BIT2 + BIT1 + BIT0
+
+#define RDIMM_RC00     0x00
+#define RDIMM_RC01     0x01
+#define RDIMM_RC02     0x02
+#define RDIMM_RC03     0x03
+#define RDIMM_RC04     0x04
+#define RDIMM_RC05     0x05
+#define RDIMM_RC08     0x08
+#define RDIMM_RC09     0x09
+#define RDIMM_RC0A     0x0A
+#define RDIMM_RC0B     0x0B
+#define RDIMM_RC0C     0x0C
+#define RDIMM_RC0D     0x0D
+#define RDIMM_RC0E     0x0E
+#define RDIMM_RC0F     0x0F
+#define RDIMM_RC1x     0x10
+#define RDIMM_RC2x     0x20
+#define RDIMM_RC3x     0x30
+#define RDIMM_RC4x     0x40
+#define RDIMM_RC5x     0x50
+#define RDIMM_RC6x     0x60
+#define RDIMM_RC7x     0x70
+#define RDIMM_RC8x     0x80
+#define RDIMM_RC9x     0x90
+#define RDIMM_RCAx     0xA0
+
+#define LRDIMM_BC00    0x00
+#define LRDIMM_BC01    0x01
+#define LRDIMM_BC02    0x02
+#define LRDIMM_BC03    0x03
+#define LRDIMM_BC04    0x04
+#define LRDIMM_BC05    0x05
+#define LRDIMM_BC06    0x06
+#define LRDIMM_BC07    0x07
+#define LRDIMM_BC08    0x08
+#define LRDIMM_BC09    0x09
+#define LRDIMM_BC0A    0x0A
+#define LRDIMM_BC0B    0x0B
+#define LRDIMM_BC0C    0x0C
+#define LRDIMM_BC0E    0x0E
+
+#define LRDIMM_BC0x    0x00
+#define LRDIMM_BC1x    0x10
+#define LRDIMM_BC2x    0x20
+#define LRDIMM_BC3x    0x30
+#define LRDIMM_BC4x    0x40
+#define LRDIMM_BC5x    0x50
+#define LRDIMM_BC6x    0x60
+#define LRDIMM_BC7x    0x70
+#define LRDIMM_BC8x    0x80
+#define LRDIMM_BC9x    0x90
+#define LRDIMM_BCAx    0xA0
+#define LRDIMM_BCBx    0xB0
+#define LRDIMM_BCCx    0xC0
+#define LRDIMM_BCDx    0xD0
+#define LRDIMM_BCEx    0xE0
+#define LRDIMM_BCFx    0xF0
+#define LRDIMM_F0      0x0
+#define LRDIMM_F1      0x1
+#define LRDIMM_F5      0x5
+#define LRDIMM_F6      0x6
+#define LRDIMM_F7      0x7
+#define LRDIMM_F8      0x8
+#define LRDIMM_F9      0x9
+
+#endif /* _HW_MEM_INIT_LIB_H_ */
diff --git a/Chips/Hisilicon/Include/Library/I2CLib.h b/Chips/Hisilicon/Include/Library/I2CLib.h
new file mode 100644
index 0000000..36e9f5f
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/I2CLib.h
@@ -0,0 +1,73 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _I2C_LIB_H_
+#define _I2C_LIB_H_
+
+//I2C0 or I2C1
+typedef enum {
+  DEVICE_TYPE_SPD = 0,
+  DEVICE_TYPE_E2PROM,
+  DEVICE_TYPE_CPLD_3BYTE_OPERANDS,
+  DEVICE_TYPE_CPLD_4BYTE_OPERANDS
+}I2C_DEVICE_TYPE;
+
+
+typedef enum {
+  Normal = 0,
+  Fast,
+  SPEED_MODE_MAX
+}SPEED_MODE;
+
+
+#define    I2C_PORT_MAX            10
+
+
+
+typedef struct {
+    UINT32           Socket;
+    UINT32           Port;
+    I2C_DEVICE_TYPE  DeviceType;
+    UINT32           SlaveDeviceAddress;
+}I2C_DEVICE;
+
+
+UINTN
+EFIAPI
+I2CInit(UINT32 Socket, UINT32 Port, SPEED_MODE SpeedMode);
+
+EFI_STATUS
+EFIAPI
+I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CWriteMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset, UINT32 ulLength, UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CReadMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf);
+
+EFI_STATUS
+EFIAPI
+I2CSdaConfig(UINT32 Socket, UINT32 Port);
+
+
+#endif
diff --git a/Chips/Hisilicon/Include/Library/LpcLib.h b/Chips/Hisilicon/Include/Library/LpcLib.h
new file mode 100755
index 0000000..236a52b
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/LpcLib.h
@@ -0,0 +1,113 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _LPC_LIB_H_
+#define _LPC_LIB_H_
+
+#include <Uefi.h>
+
+#define PCIE_SUBSYS_IO_MUX      0xA0170000
+#define PCIE_SUBSYS_IOMG033     (PCIE_SUBSYS_IO_MUX + 0x84)
+#define PCIE_SUBSYS_IOMG035     (PCIE_SUBSYS_IO_MUX + 0x8C)
+#define PCIE_SUBSYS_IOMG036     (PCIE_SUBSYS_IO_MUX + 0x90)
+#define PCIE_SUBSYS_IOMG045     (PCIE_SUBSYS_IO_MUX + 0xB4)
+#define PCIE_SUBSYS_IOMG046     (PCIE_SUBSYS_IO_MUX + 0xB8)
+#define PCIE_SUBSYS_IOMG047     (PCIE_SUBSYS_IO_MUX + 0xBC)
+#define PCIE_SUBSYS_IOMG048     (PCIE_SUBSYS_IO_MUX + 0xC0)
+#define PCIE_SUBSYS_IOMG049     (PCIE_SUBSYS_IO_MUX + 0xC4)
+#define PCIE_SUBSYS_IOMG050     (PCIE_SUBSYS_IO_MUX + 0xC8)
+
+#define IO_WRAP_CTRL_BASE       0xA0100000
+#define SC_LPC_CLK_EN_REG       (IO_WRAP_CTRL_BASE + 0x03a0)
+#define SC_LPC_CLK_DIS_REG      (IO_WRAP_CTRL_BASE + 0x03a4)
+#define SC_LPC_BUS_CLK_EN_REG   (IO_WRAP_CTRL_BASE + 0x03a8)
+#define SC_LPC_BUS_CLK_DIS_REG  (IO_WRAP_CTRL_BASE + 0x03ac)
+#define SC_LPC_RESET_REQ        (IO_WRAP_CTRL_BASE + 0x0ad8)
+#define SC_LPC_RESET_DREQ       (IO_WRAP_CTRL_BASE + 0x0adc)
+#define SC_LPC_BUS_RESET_REQ    (IO_WRAP_CTRL_BASE + 0x0ae0)
+#define SC_LPC_BUS_RESET_DREQ   (IO_WRAP_CTRL_BASE + 0x0ae4)
+#define SC_LPC_CTRL_REG         (IO_WRAP_CTRL_BASE + 0x2028)
+
+
+#define LPC_BASE                0xA01B0000
+#define LPC_START_REG           (LPC_BASE + 0x00)
+#define LPC_OP_STATUS_REG       (LPC_BASE + 0x04)
+#define LPC_IRQ_ST_REG          (LPC_BASE + 0x08)
+#define LPC_OP_LEN_REG          (LPC_BASE + 0x10)
+#define LPC_CMD_REG             (LPC_BASE + 0x14)
+#define LPC_FWH_ID_MSIZE_REG    (LPC_BASE + 0x18)
+#define LPC_ADDR_REG            (LPC_BASE + 0x20)
+#define LPC_WDATA_REG           (LPC_BASE + 0x24)
+#define LPC_RDATA_REG           (LPC_BASE + 0x28)
+#define LPC_LONG_CNT_REG        (LPC_BASE + 0x30)
+#define LPC_TX_FIFO_ST_REG      (LPC_BASE + 0x50)
+#define LPC_RX_FIFO_ST_REG      (LPC_BASE + 0x54)
+#define LPC_TIME_OUT_REG        (LPC_BASE + 0x58)
+#define LPC_SIRQ_CTRL0_REG      (LPC_BASE + 0x80)
+#define LPC_SIRQ_CTRL1_REG      (LPC_BASE + 0x84)
+#define LPC_SIRQ_INT_REG        (LPC_BASE + 0x90)
+#define LPC_SIRQ_INT_MASK_REG   (LPC_BASE + 0x94)
+#define LPC_SIRQ_STAT_REG       (LPC_BASE + 0xA0)
+
+#define LPC_FIFO_LEN            (16)
+
+typedef enum{
+    LPC_ADDR_MODE_INCREASE,
+    LPC_ADDR_MODE_SINGLE
+}LPC_ADDR_MODE;
+
+typedef enum{
+    LPC_TYPE_IO,
+    LPC_TYPE_MEM,
+    LPC_TYPE_FWH
+}LPC_TYPE;
+
+
+typedef union {
+    struct{
+        UINT32  lpc_wr:1;
+        UINT32  lpc_type:2;
+        UINT32  same_addr:1;
+        UINT32  resv:28;
+    }bits;
+    UINT32  u32;
+}LPC_CMD_STRUCT;
+
+typedef union {
+    struct{
+        UINT32  op_len:5;
+        UINT32  resv:27;
+    }bits;
+    UINT32  u32;
+}LPC_OP_LEN_STRUCT;
+
+
+VOID LpcInit(VOID);
+BOOLEAN LpcIdle(VOID);
+EFI_STATUS LpcByteWrite(
+    IN  UINT32              Addr,
+    IN  UINT8               Data);
+EFI_STATUS LpcByteRead(
+    IN  UINT32              Addr,
+    IN OUT  UINT8          *Data);
+
+EFI_STATUS LpcWrite(
+    IN  UINT32              Addr,
+    IN  UINT8              *Data,
+    IN  UINT8               Len);
+
+#endif
+
+
diff --git a/Chips/Hisilicon/Include/Library/OemAddressMapLib.h b/Chips/Hisilicon/Include/Library/OemAddressMapLib.h
new file mode 100644
index 0000000..21498b7
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/OemAddressMapLib.h
@@ -0,0 +1,37 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _OEM_ADDRESS_MAP_LIB_H_
+#define _OEM_ADDRESS_MAP_LIB_H_
+
+typedef struct _DDRC_BASE_ID{
+    UINTN  Base;
+    UINTN  Id;
+}DDRC_BASE_ID;
+
+// Invalid address, will cause exception when accessed by bug code
+#define ADDRESS_MAP_INVALID ((UINTN)(-1))
+
+UINTN OemGetPoeSubBase (UINT32 NodeId);
+UINTN OemGetPeriSubBase (UINT32 NodeId);
+UINTN OemGetAlgSubBase (UINT32 NodeId);
+UINTN OemGetM3SubBase (UINT32 NodeId);
+
+VOID OemAddressMapInit(VOID);
+
+extern DDRC_BASE_ID DdrcBaseId[MAX_SOCKET][MAX_CHANNEL];
+
+#endif
+
diff --git a/Chips/Hisilicon/Include/Library/OemMiscLib.h b/Chips/Hisilicon/Include/Library/OemMiscLib.h
new file mode 100644
index 0000000..6f18c0f
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/OemMiscLib.h
@@ -0,0 +1,51 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _OEM_MISC_LIB_H_
+#define _OEM_MISC_LIB_H_
+
+#include <Uefi.h>
+
+#include <PlatformArch.h>
+#include <Library/I2CLib.h>
+
+#define PCIEDEVICE_REPORT_MAX      4
+typedef struct _REPORT_PCIEDIDVID2BMC{
+    UINTN   Bus;
+    UINTN   Device;
+    UINTN   Function;
+    UINTN   Slot;
+}REPORT_PCIEDIDVID2BMC;
+extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX];
+
+BOOLEAN OemIsSocketPresent (UINTN Socket);
+VOID CoreSelectBoot(VOID);
+VOID OemPcieResetAndOffReset(void);
+extern I2C_DEVICE gDS3231RtcDevice;
+
+UINTN OemGetSocketNumber(VOID);
+UINTN OemGetDdrChannel (VOID);
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel);
+
+BOOLEAN OemIsMpBoot();
+UINT32 OemIsWarmBoot();
+
+VOID OemBiosSwitch(UINT32 Master);
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID);
+
+extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM];
+EFI_HII_HANDLE EFIAPI OemGetPackages ();
+#endif
diff --git a/Chips/Hisilicon/Include/Library/OemSetVirtualMapDesc.h b/Chips/Hisilicon/Include/Library/OemSetVirtualMapDesc.h
new file mode 100644
index 0000000..da9a720
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/OemSetVirtualMapDesc.h
@@ -0,0 +1,26 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _OEM_SET_VIRTUAL_MAP_DESC_H_
+#define _OEM_SET_VIRTUAL_MAP_DESC_H_
+
+
+UINTN OemSetVirtualMapDesc (
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable,
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes
+  );
+
+#endif
+
diff --git a/Chips/Hisilicon/Include/Library/PlatformPciLib.h b/Chips/Hisilicon/Include/Library/PlatformPciLib.h
new file mode 100644
index 0000000..9d28fec
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/PlatformPciLib.h
@@ -0,0 +1,209 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_PCI_LIB_H_
+#define _PLATFORM_PCI_LIB_H_
+
+#define PCIE_MAX_HOSTBRIDGE      2
+#define PCIE_MAX_ROOTBRIDGE      8
+//The extern pcie addresses will be initialized by oemmisclib
+extern UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+extern UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+extern UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+
+
+#define PCI_HB0RB0_PCI_BASE        FixedPcdGet64(PciHb0Rb0Base)
+#define PCI_HB0RB1_PCI_BASE        FixedPcdGet64(PciHb0Rb1Base)
+#define PCI_HB0RB2_PCI_BASE        FixedPcdGet64(PciHb0Rb2Base)
+#define PCI_HB0RB3_PCI_BASE        FixedPcdGet64(PciHb0Rb3Base)
+#define PCI_HB0RB4_PCI_BASE        FixedPcdGet64(PciHb0Rb4Base)
+#define PCI_HB0RB5_PCI_BASE        FixedPcdGet64(PciHb0Rb5Base)
+#define PCI_HB0RB6_PCI_BASE        FixedPcdGet64(PciHb0Rb6Base)
+#define PCI_HB0RB7_PCI_BASE        FixedPcdGet64(PciHb0Rb7Base)
+
+#define PCI_HB1RB0_PCI_BASE        FixedPcdGet64(PciHb1Rb0Base)
+#define PCI_HB1RB1_PCI_BASE        FixedPcdGet64(PciHb1Rb1Base)
+#define PCI_HB1RB2_PCI_BASE        FixedPcdGet64(PciHb1Rb2Base)
+#define PCI_HB1RB3_PCI_BASE        FixedPcdGet64(PciHb1Rb3Base)
+#define PCI_HB1RB4_PCI_BASE        FixedPcdGet64(PciHb1Rb4Base)
+#define PCI_HB1RB5_PCI_BASE        FixedPcdGet64(PciHb1Rb5Base)
+#define PCI_HB1RB6_PCI_BASE        FixedPcdGet64(PciHb1Rb6Base)
+#define PCI_HB1RB7_PCI_BASE        FixedPcdGet64(PciHb1Rb7Base)
+
+#define PCI_HB0RB0_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB0_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceSize)
+#define PCI_HB0RB1_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB1_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb1PciConfigurationSpaceSize)
+#define PCI_HB0RB2_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB2_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceSize)
+#define PCI_HB0RB3_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB3_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceSize)
+#define PCI_HB0RB4_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB4_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceSize)
+#define PCI_HB0RB5_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB5_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceSize)
+#define PCI_HB0RB6_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB6_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceSize)
+#define PCI_HB0RB7_ECAM_BASE      FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceBaseAddress)
+#define PCI_HB0RB7_ECAM_SIZE      FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceSize)
+
+#define PCI_HB1RB0_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB0_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceSize)
+#define PCI_HB1RB1_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB1_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceSize)
+#define PCI_HB1RB2_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB2_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceSize)
+#define PCI_HB1RB3_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB3_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceSize)
+#define PCI_HB1RB4_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB4_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceSize)
+#define PCI_HB1RB5_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB5_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceSize)
+#define PCI_HB1RB6_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB6_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceSize)
+#define PCI_HB1RB7_ECAM_BASE      FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceBaseAddress)
+#define PCI_HB1RB7_ECAM_SIZE      FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceSize)
+
+#define PCI_HB0RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb0PciRegionBaseAddress))
+#define PCI_HB0RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb0PciRegionSize))
+#define PCI_HB0RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb1PciRegionBaseAddress))
+#define PCI_HB0RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb1PciRegionSize))
+#define PCI_HB0RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb2PciRegionBaseAddress))
+#define PCI_HB0RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb2PciRegionSize))
+#define PCI_HB0RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb3PciRegionBaseAddress))
+#define PCI_HB0RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb3PciRegionSize))
+#define PCI_HB0RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb4PciRegionBaseAddress))
+#define PCI_HB0RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb4PciRegionSize))
+#define PCI_HB0RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb5PciRegionBaseAddress))
+#define PCI_HB0RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb5PciRegionSize))
+#define PCI_HB0RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb6PciRegionBaseAddress))
+#define PCI_HB0RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb6PciRegionSize))
+#define PCI_HB0RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb7PciRegionBaseAddress))
+#define PCI_HB0RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb7PciRegionSize))
+
+#define PCI_HB1RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb0PciRegionBaseAddress))
+#define PCI_HB1RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb0PciRegionSize))
+#define PCI_HB1RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb1PciRegionBaseAddress))
+#define PCI_HB1RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb1PciRegionSize))
+#define PCI_HB1RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb2PciRegionBaseAddress))
+#define PCI_HB1RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb2PciRegionSize))
+#define PCI_HB1RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb3PciRegionBaseAddress))
+#define PCI_HB1RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb3PciRegionSize))
+#define PCI_HB1RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb4PciRegionBaseAddress))
+#define PCI_HB1RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb4PciRegionSize))
+#define PCI_HB1RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb5PciRegionBaseAddress))
+#define PCI_HB1RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb5PciRegionSize))
+#define PCI_HB1RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb6PciRegionBaseAddress))
+#define PCI_HB1RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb6PciRegionSize))
+#define PCI_HB1RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb7PciRegionBaseAddress))
+#define PCI_HB1RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb7PciRegionSize))
+
+
+#define PCI_HB0RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuMemRegionBase))
+#define PCI_HB0RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuMemRegionBase))
+#define PCI_HB0RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuMemRegionBase))
+#define PCI_HB0RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuMemRegionBase))
+#define PCI_HB0RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuMemRegionBase))
+#define PCI_HB0RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuMemRegionBase))
+#define PCI_HB0RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuMemRegionBase))
+#define PCI_HB0RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuMemRegionBase))
+
+#define PCI_HB1RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuMemRegionBase))
+#define PCI_HB1RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuMemRegionBase))
+#define PCI_HB1RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuMemRegionBase))
+#define PCI_HB1RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuMemRegionBase))
+#define PCI_HB1RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuMemRegionBase))
+#define PCI_HB1RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuMemRegionBase))
+#define PCI_HB1RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuMemRegionBase))
+#define PCI_HB1RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuMemRegionBase))
+
+
+#define PCI_HB0RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuIoRegionBase))
+#define PCI_HB0RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuIoRegionBase))
+#define PCI_HB0RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuIoRegionBase))
+#define PCI_HB0RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuIoRegionBase))
+#define PCI_HB0RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuIoRegionBase))
+#define PCI_HB0RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuIoRegionBase))
+#define PCI_HB0RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuIoRegionBase))
+#define PCI_HB0RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuIoRegionBase))
+
+#define PCI_HB1RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuIoRegionBase))
+#define PCI_HB1RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuIoRegionBase))
+#define PCI_HB1RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuIoRegionBase))
+#define PCI_HB1RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuIoRegionBase))
+#define PCI_HB1RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuIoRegionBase))
+#define PCI_HB1RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuIoRegionBase))
+#define PCI_HB1RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuIoRegionBase))
+#define PCI_HB1RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuIoRegionBase))
+
+
+
+#define PCI_HB0RB0_IO_BASE (FixedPcdGet64 (PcdHb0Rb0IoBase))
+#define PCI_HB0RB1_IO_BASE (FixedPcdGet64 (PcdHb0Rb1IoBase))
+#define PCI_HB0RB2_IO_BASE (FixedPcdGet64 (PcdHb0Rb2IoBase))
+#define PCI_HB0RB3_IO_BASE (FixedPcdGet64 (PcdHb0Rb3IoBase))
+#define PCI_HB0RB4_IO_BASE (FixedPcdGet64 (PcdHb0Rb4IoBase))
+#define PCI_HB0RB5_IO_BASE (FixedPcdGet64 (PcdHb0Rb5IoBase))
+#define PCI_HB0RB6_IO_BASE (FixedPcdGet64 (PcdHb0Rb6IoBase))
+#define PCI_HB0RB7_IO_BASE (FixedPcdGet64 (PcdHb0Rb7IoBase))
+
+#define PCI_HB1RB0_IO_BASE (FixedPcdGet64 (PcdHb1Rb0IoBase))
+#define PCI_HB1RB1_IO_BASE (FixedPcdGet64 (PcdHb1Rb1IoBase))
+#define PCI_HB1RB2_IO_BASE (FixedPcdGet64 (PcdHb1Rb2IoBase))
+#define PCI_HB1RB3_IO_BASE (FixedPcdGet64 (PcdHb1Rb3IoBase))
+#define PCI_HB1RB4_IO_BASE (FixedPcdGet64 (PcdHb1Rb4IoBase))
+#define PCI_HB1RB5_IO_BASE (FixedPcdGet64 (PcdHb1Rb5IoBase))
+#define PCI_HB1RB6_IO_BASE (FixedPcdGet64 (PcdHb1Rb6IoBase))
+#define PCI_HB1RB7_IO_BASE (FixedPcdGet64 (PcdHb1Rb7IoBase))
+
+#define PCI_HB0RB0_IO_SIZE (FixedPcdGet64 (PcdHb0Rb0IoSize))
+#define PCI_HB0RB1_IO_SIZE (FixedPcdGet64 (PcdHb0Rb1IoSize))
+#define PCI_HB0RB2_IO_SIZE (FixedPcdGet64 (PcdHb0Rb2IoSize))
+#define PCI_HB0RB3_IO_SIZE (FixedPcdGet64 (PcdHb0Rb3IoSize))
+#define PCI_HB0RB4_IO_SIZE (FixedPcdGet64 (PcdHb0Rb4IoSize))
+#define PCI_HB0RB5_IO_SIZE (FixedPcdGet64 (PcdHb0Rb5IoSize))
+#define PCI_HB0RB6_IO_SIZE (FixedPcdGet64 (PcdHb0Rb6IoSize))
+#define PCI_HB0RB7_IO_SIZE (FixedPcdGet64 (PcdHb0Rb7IoSize))
+
+#define PCI_HB1RB0_IO_SIZE (FixedPcdGet64 (PcdHb1Rb0IoSize))
+#define PCI_HB1RB1_IO_SIZE (FixedPcdGet64 (PcdHb1Rb1IoSize))
+#define PCI_HB1RB2_IO_SIZE (FixedPcdGet64 (PcdHb1Rb2IoSize))
+#define PCI_HB1RB3_IO_SIZE (FixedPcdGet64 (PcdHb1Rb3IoSize))
+#define PCI_HB1RB4_IO_SIZE (FixedPcdGet64 (PcdHb1Rb4IoSize))
+#define PCI_HB1RB5_IO_SIZE (FixedPcdGet64 (PcdHb1Rb5IoSize))
+#define PCI_HB1RB6_IO_SIZE (FixedPcdGet64 (PcdHb1Rb6IoSize))
+#define PCI_HB1RB7_IO_SIZE (FixedPcdGet64 (PcdHb1Rb7IoSize))
+
+
+
+typedef struct {
+  UINT64          Ecam;
+  UINT64          BusBase;
+  UINT64          BusLimit;
+  UINT64          MemBase;
+  UINT64          MemLimit;
+  UINT64          IoBase;
+  UINT64          IoLimit;
+  UINT64          CpuMemRegionBase;
+  UINT64          CpuIoRegionBase;
+  UINT64          RbPciBar;
+  UINT64          PciRegionBase;
+  UINT64          PciRegionLimit;
+} PCI_ROOT_BRIDGE_RESOURCE_APPETURE;
+
+extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
+#endif
+
diff --git a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
new file mode 100644
index 0000000..ec2b9a3
--- /dev/null
+++ b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
@@ -0,0 +1,106 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_SYS_CTRL_LIB_H_
+#define _PLATFORM_SYS_CTRL_LIB_H_
+
+#define PACKAGE_16CORE      0
+#define PACKAGE_32CORE      1
+#define PACKAGE_RESERVED    2
+#define PACKAGE_TYPE_NUM    3
+
+UINT32 PlatformGetPackageType (VOID);
+
+VOID DisplayCpuInfo (VOID);
+UINT32 CheckChipIsEc(VOID);
+
+UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll);
+
+#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF
+#define DJTAG_CHAIN_ID_AA        1
+#define DJTAG_CHAIN_ID_LLC       4
+
+
+#define SC_DJTAG_MSTR_EN_OFFSET             0x6800
+#define SC_DJTAG_MSTR_START_EN_OFFSET       0x6804
+#define SC_DJTAG_SEC_ACC_EN_OFFSET          0x6808
+#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET    0x680C
+#define SC_DJTAG_MSTR_WR_OFFSET             0x6810
+#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET   0x6814
+#define SC_DJTAG_MSTR_ADDR_OFFSET           0x6818
+#define SC_DJTAG_MSTR_DATA_OFFSET           0x681C
+#define SC_DJTAG_TMOUT_OFFSET               0x6820
+#define SC_TDRE_OP_ADDR_OFFSET              0x6824
+#define SC_TDRE_WDATA_OFFSET                0x6828
+#define SC_TDRE_REPAIR_EN_OFFSET            0x682C
+#define SC_DJTAG_RD_DATA0_OFFSET            0xE800
+#define SC_TDRE_RDATA0_OFFSET               0xE830
+
+
+UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port);
+
+VOID PlatformAddressMapCleanUp (VOID);
+VOID PlatformDisableDdrWindow (VOID);
+
+VOID PlatformEnableArchTimer (VOID);
+
+EFI_STATUS
+DawFindFreeWindow (UINTN Socket, UINTN *DawIndex);
+
+VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value);
+
+VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
+
+VOID RemoveRoceReset(VOID);
+
+UINTN PlatformGetDdrChannel (VOID);
+
+VOID ITSCONFIG (VOID);
+
+VOID MN_CONFIG (VOID);
+
+VOID SmmuConfigForOS (VOID);
+VOID SmmuConfigForBios (VOID);
+
+VOID StartupAp (VOID);
+
+VOID LlcCleanInvalidate (VOID);
+
+UINTN PlatformGetCpuFreq (UINT8 Socket);
+VOID ClearInterruptStatus(VOID);
+
+UINTN PlatformGetCoreCount (VOID);
+VOID DAWConfigEn(UINT32 socket);
+
+VOID DResetUsb ();
+UINT32 PlatformGetEhciBase ();
+UINT32 PlatformGetOhciBase ();
+VOID PlatformPllInit();
+// PLL initialization for super IO clusters.
+VOID SiclPllInit(UINT32 SclId);
+VOID PlatformDeviceDReset();
+VOID PlatformGicdInit();
+VOID PlatformLpcInit();
+// Synchronize architecture timer counter between different super computing
+// clusters.
+VOID PlatformArchTimerSynchronize(VOID);
+VOID PlatformEventBroadcastConfig(VOID);
+UINTN GetDjtagRegBase(UINT32 NodeId);
+VOID LlcCleanInvalidateAsm(VOID);
+VOID PlatformMdioInit(VOID);
+
+#endif
diff --git a/Chips/Hisilicon/Include/PlatformArch.h b/Chips/Hisilicon/Include/PlatformArch.h
new file mode 100644
index 0000000..45995c5
--- /dev/null
+++ b/Chips/Hisilicon/Include/PlatformArch.h
@@ -0,0 +1,35 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#ifndef _PLATFORM_ARCH_H_
+#define _PLATFORM_ARCH_H_
+
+#define MAX_SOCKET      2
+#define MAX_DIE         4
+#define MAX_DDRC        2
+#define MAX_NODE        (MAX_SOCKET * MAX_DIE)
+#define MAX_CHANNEL     4
+#define MAX_DIMM        3
+#define MAX_RANK_CH     12
+#define MAX_RANK_DIMM   4
+// Max NUMA node number for each node type
+#define MAX_NUM_PER_TYPE 8
+
+#define S1_BASE               0x40000000000
+
+#endif
+
diff --git a/Chips/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h b/Chips/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h
new file mode 100644
index 0000000..8a9d13c
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/HisiBoardNicProtocol.h
@@ -0,0 +1,61 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HISI_BOARD_NIC_PROTOCOL_H_
+#define _HISI_BOARD_NIC_PROTOCOL_H_
+
+#define HISI_BOARD_NIC_PROTOCOL_GUID   \
+    { 0xb5903955, 0x31e9, 0x4aaf, { 0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66 } }
+
+#define HISI_BOARD_XGE_STATUS_PROTOCOL_GUID   \
+        { 0xa6b8ed0e, 0xd8cc, 0x4853, { 0xaa, 0x39, 0x2c, 0x3e, 0xcd, 0x7c, 0xa5, 0x97 } }
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_BOARD_NIC_GET_MAC_ADDRESS) (
+  IN OUT EFI_MAC_ADDRESS *Mac,
+  IN UINTN Port
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_BOARD_NIC_SET_MAC_ADDRESS) (
+  IN EFI_MAC_ADDRESS *Mac,
+  IN UINTN Port
+  );
+
+typedef struct {
+  HISI_BOARD_NIC_GET_MAC_ADDRESS GetMac;
+  HISI_BOARD_NIC_SET_MAC_ADDRESS SetMac;
+} HISI_BOARD_NIC_PROTOCOL;
+
+typedef
+VOID
+(*HISI_BOARD_FEEDBACK_XGE_STATUS) (
+  BOOLEAN IsLinkup,
+  BOOLEAN IsActOK,
+  UINT32 port
+  );
+
+typedef struct {
+  HISI_BOARD_FEEDBACK_XGE_STATUS FeedbackXgeStatus;
+} HISI_BOARD_XGE_STATUS_PROTOCOL;
+
+
+extern EFI_GUID gHisiBoardNicProtocolGuid;
+extern EFI_GUID gHisiBoardXgeStatusProtocolGuid;
+
+
+#endif
diff --git a/Chips/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h b/Chips/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h
new file mode 100644
index 0000000..b7ed9ce
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/HisiSpiFlashProtocol.h
@@ -0,0 +1,66 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _HISI_SPI_FLASH_PROTOCOL_H_
+#define _HISI_SPI_FLASH_PROTOCOL_H_
+
+typedef struct _HISI_SPI_FLASH_PROTOCOL HISI_SPI_FLASH_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_ERASE_INTERFACE) (
+    IN HISI_SPI_FLASH_PROTOCOL   *This,
+    IN UINT32                  Offset,
+    IN UINT32                  ulLength
+    );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_WRITE_INTERFACE) (
+    IN HISI_SPI_FLASH_PROTOCOL  *This,
+    IN  UINT32                 Offset,
+    IN  UINT8                 *Buffer,
+    IN  UINT32                 ulLength
+    );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_READ_INTERFACE) (
+    IN HISI_SPI_FLASH_PROTOCOL   *This,
+    IN UINT32                  Offset,
+    IN OUT UINT8              *Buffer,
+    IN UINT32                  ulLength
+    );
+
+typedef
+EFI_STATUS
+(EFIAPI *HISI_SPI_FLASH_ERASE_WRITE_INTERFACE) (
+    IN HISI_SPI_FLASH_PROTOCOL  *This,
+    IN  UINT32                 Offset,
+    IN  UINT8                 *Buffer,
+    IN  UINT32                 ulLength
+    );
+
+struct _HISI_SPI_FLASH_PROTOCOL {
+    HISI_SPI_FLASH_ERASE_INTERFACE             Erase;
+    HISI_SPI_FLASH_WRITE_INTERFACE             Write;
+    HISI_SPI_FLASH_READ_INTERFACE              Read;
+    HISI_SPI_FLASH_ERASE_WRITE_INTERFACE       EraseWrite;
+};
+
+extern EFI_GUID gHisiSpiFlashProtocolGuid;
+
+#endif
diff --git a/Chips/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h b/Chips/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h
new file mode 100644
index 0000000..c5f0f85
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/IpmiInterfaceProtocol.h
@@ -0,0 +1,99 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IPMI_INTERFACE_PROTOCOL_H_
+#define _IPMI_INTERFACE_PROTOCOL_H_
+
+#define IPMI_INTERFACE_PROTOCOL_GUID \
+  {0xa37e200e, 0xda90, 0x473b, {0x8b, 0xb5, 0x1d, 0x7b, 0x11, 0xba, 0x32, 0x33}}
+
+typedef struct _IPMI_INTERFACE_PROTOCOL IPMI_INTERFACE_PROTOCOL;
+
+//
+// Structure to store IPMI Network Function, LUN and command
+//
+typedef struct {
+  UINT8 Lun   : 2;
+  UINT8 NetFn : 6;
+  UINT8 Cmd;
+} IPMI_CMD_HEADER;
+
+//
+// System Interface Type
+//
+typedef enum {
+  IPMI_SYSTEM_INTERFACE_UNKNOWN,
+  IPMI_SYSTEM_INTERFACE_KCS,
+  IPMI_SYSTEM_INTERFACE_SMIC,
+  IPMI_SYSTEM_INTERFACE_BT,
+  IPMI_SYSTEM_INTERFACE_SSIF,
+  IPMI_SYSTEM_INTERFACE_MAX_TYPE
+} IPMI_SYSTEM_INTERFACE_TYPE;
+
+//
+// System Interface Address Type
+//
+typedef enum {
+  IPMI_MEMORY,
+  IPMI_IO,
+  IPMI_MAX_INTERFACE_ADDRESS_TYPE
+} IPMI_INTERFACE_ADDRESS_TYPE;
+
+typedef
+EFI_STATUS
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_EXECUTE_IPMI_CMD) (
+  IN  IPMI_INTERFACE_PROTOCOL       *This,
+  IN  IPMI_CMD_HEADER               Request,
+  IN  VOID                          *SendData OPTIONAL,
+  IN  UINT8                         SendLength,
+  OUT VOID                          *RecvData,
+  OUT UINT8                         *RecvLength,
+  OUT UINT16                        *StatusCodes OPTIONAL
+);
+typedef
+IPMI_SYSTEM_INTERFACE_TYPE
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_INTERFACE_TYPE) (
+  IN  IPMI_INTERFACE_PROTOCOL   *This
+);
+typedef
+UINT16
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS) (
+  IN  IPMI_INTERFACE_PROTOCOL   *This
+);
+typedef
+IPMI_INTERFACE_ADDRESS_TYPE
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS_TYPE) (
+  IN  IPMI_INTERFACE_PROTOCOL   *This
+);
+typedef
+UINT8
+(EFIAPI *IPMI_INTERFACE_PROTOCOL_GET_IPMI_VERSION) (
+  IN  IPMI_INTERFACE_PROTOCOL   *This
+);
+
+//
+// Structure of IPMI_INTERFACE_PROTOCOL
+//
+struct _IPMI_INTERFACE_PROTOCOL{
+  IPMI_INTERFACE_PROTOCOL_EXECUTE_IPMI_CMD             ExecuteIpmiCmd;
+  IPMI_INTERFACE_PROTOCOL_GET_IPMI_INTERFACE_TYPE      GetIpmiInterfaceType;
+  IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS        GetIpmiBaseAddress;
+  IPMI_INTERFACE_PROTOCOL_GET_IPMI_BASE_ADDRESS_TYPE   GetIpmiBaseAddressType;
+  IPMI_INTERFACE_PROTOCOL_GET_IPMI_VERSION             GetIpmiVersion;
+} ;
+
+extern EFI_GUID gIpmiInterfaceProtocolGuid;
+
+#endif
diff --git a/Chips/Hisilicon/Include/Protocol/NorFlashProtocol.h b/Chips/Hisilicon/Include/Protocol/NorFlashProtocol.h
new file mode 100644
index 0000000..29e9de8
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/NorFlashProtocol.h
@@ -0,0 +1,59 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _NOR_FLASH_PROTOCOL_H_
+#define _NOR_FLASH_PROTOCOL_H_
+
+#define UNI_NOR_FLASH_PROTOCOL_GUID   \
+    {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}}
+
+typedef struct _UNI_NOR_FLASH_PROTOCOL UNI_NOR_FLASH_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_ERASE_INTERFACE) (
+    IN UNI_NOR_FLASH_PROTOCOL   *This,
+    IN UINT32                  Offset,
+    IN UINT32                  Length
+    );
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_WRITE_INTERFACE) (
+    IN UNI_NOR_FLASH_PROTOCOL   *This,
+    IN  UINT32                 Offset,
+    IN  UINT8                 *Buffer,
+    UINT32                   ulLength
+    );
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_READ_INTERFACE) (
+    IN UNI_NOR_FLASH_PROTOCOL   *This,
+    IN UINT32                  Offset,
+    IN OUT UINT8              *Buffer,
+    IN UINT32                   ulLen
+    );
+
+
+struct _UNI_NOR_FLASH_PROTOCOL {
+    UNI_FLASH_ERASE_INTERFACE             Erase;
+    UNI_FLASH_WRITE_INTERFACE             Write;
+    UNI_FLASH_READ_INTERFACE              Read;
+};
+
+extern EFI_GUID gUniNorFlashProtocolGuid;
+
+#endif
diff --git a/Chips/Hisilicon/Include/Protocol/PlatformSasProtocol.h b/Chips/Hisilicon/Include/Protocol/PlatformSasProtocol.h
new file mode 100644
index 0000000..1e1892b
--- /dev/null
+++ b/Chips/Hisilicon/Include/Protocol/PlatformSasProtocol.h
@@ -0,0 +1,37 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PLATFORM_SAS_PROTOCOL_H_
+#define _PLATFORM_SAS_PROTOCOL_H_
+
+#define PLATFORM_SAS_PROTOCOL_GUID \
+    { \
+        0x40e9829f, 0x3a2c, 0x479a, 0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d \
+    }
+
+typedef struct _PLATFORM_SAS_PROTOCOL PLATFORM_SAS_PROTOCOL;
+
+typedef
+VOID
+(EFIAPI * SAS_INIT) (
+    IN PLATFORM_SAS_PROTOCOL   *This
+);
+
+struct _PLATFORM_SAS_PROTOCOL {
+    IN UINT64        BaseAddr;
+    SAS_INIT         Init;
+};
+
+#endif
diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
new file mode 100644
index 0000000..539d567
--- /dev/null
+++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
@@ -0,0 +1,16537 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_REG_OFFSET__
+#define __PCIE_REG_OFFSET__
+
+
+
+
+#define PCIE_EEP_PCI_CFG_HDR0_REG                 (0x0)
+#define PCIE_EEP_PCI_CFG_HDR1_REG                 (0x4)
+#define PCIE_EEP_PCI_CFG_HDR2_REG                 (0x8)
+#define PCIE_EEP_PCI_CFG_HDR3_REG                 (0xC)
+#define PCIE_EEP_PCI_CFG_HDR4_REG                 (0x10)
+#define PCIE_EEP_PCI_CFG_HDR5_REG                 (0x14)
+#define PCIE_EEP_PCI_CFG_HDR6_REG                 (0x18)
+#define PCIE_EEP_PCI_CFG_HDR7_REG                 (0x1C)
+#define PCIE_EEP_PCI_CFG_HDR8_REG                 (0x20)
+#define PCIE_EEP_PCI_CFG_HDR9_REG                 (0x24)
+#define PCIE_EEP_PCI_CFG_HDR10_REG                (0x28)
+#define PCIE_EEP_PCI_CFG_HDR11_REG                (0x2C)
+#define PCIE_EEP_PCI_CFG_HDR12_REG                (0x30)
+#define PCIE_EEP_PCI_CFG_HDR13_REG                (0x34)
+#define PCIE_EEP_PCI_CFG_HDR14_REG                (0x38)
+#define PCIE_EEP_PCI_CFG_HDR15_REG                (0x3C)
+#define PCIE_EEP_PCI_PM_CAP0_REG                  (0x40)
+#define PCIE_EEP_PCI_PM_CAP1_REG                  (0x44)
+#define PCIE_EEP_PCI_MSI_CAP0_REG                 (0x50)
+#define PCIE_EEP_PCI_MSI_CAP1_REG                 (0x54)
+#define PCIE_EEP_PCI_MSI_CAP2_REG                 (0x58)
+#define PCIE_EEP_PCI_MSI_CAP3_REG                 (0x5C)
+#define PCIE_EEP_PCIE_CAP0_REG                    (0x70)
+#define PCIE_EEP_PCIE_CAP1_REG                    (0x74)
+#define PCIE_EEP_PCIE_CAP2_REG                    (0x78)
+#define PCIE_EEP_PCIE_CAP3_REG                    (0x7C)
+#define PCIE_EEP_PCIE_CAP4_REG                    (0x80)
+#define PCIE_EEP_PCIE_CAP5_REG                    (0x84)
+#define PCIE_EEP_PCIE_CAP6_REG                    (0x88)
+#define PCIE_EEP_PCIE_CAP7_REG                    (0x8C)
+#define PCIE_EEP_PCIE_CAP8_REG                    (0x90)
+#define PCIE_EEP_PCIE_CAP9_REG                    (0x94)
+#define PCIE_EEP_PCIE_CAP10_REG                   (0x98)
+#define PCIE_EEP_PCIE_CAP11_REG                   (0x9C)
+#define PCIE_EEP_PCIE_CAP12_REG                   (0xA0)
+#define PCIE_EEP_SLOT_CAP_REG                     (0xC0)
+#define PCIE_EEP_AER_CAP0_REG                     (0x100)
+#define PCIE_EEP_AER_CAP1_REG                     (0x104)
+#define PCIE_EEP_AER_CAP2_REG                     (0x108)
+#define PCIE_EEP_AER_CAP3_REG                     (0x10C)
+#define PCIE_EEP_AER_CAP4_REG                     (0x110)
+#define PCIE_EEP_AER_CAP5_REG                     (0x114)
+#define PCIE_EEP_AER_CAP6_REG                     (0x118)
+#define PCIE_EEP_AER_CAP7_REG                     (0x11C)
+#define PCIE_EEP_AER_CAP8_REG                     (0x120)
+#define PCIE_EEP_AER_CAP9_REG                     (0x124)
+#define PCIE_EEP_AER_CAP10_REG                    (0x128)
+#define PCIE_EEP_AER_CAP11_REG                    (0x12C)
+#define PCIE_EEP_AER_CAP12_REG                    (0x130)
+#define PCIE_EEP_AER_CAP13_REG                    (0x134)
+#define PCIE_EEP_VC_CAP0_REG                      (0x140)
+#define PCIE_EEP_VC_CAP1_REG                      (0x144)
+#define PCIE_EEP_VC_CAP2_REG                      (0x148)
+#define PCIE_EEP_VC_CAP3_REG                      (0x14C)
+#define PCIE_EEP_VC_CAP4_REG                      (0x150)
+#define PCIE_EEP_VC_CAP5_REG                      (0x154)
+#define PCIE_EEP_VC_CAP6_REG                      (0x158)
+#define PCIE_EEP_VC_CAP7_REG                      (0x15C)
+#define PCIE_EEP_VC_CAP8_REG                      (0x160)
+#define PCIE_EEP_VC_CAP9_REG                      (0x164)
+#define PCIE_EEP_PORT_LOGIC0_REG                  (0x700)
+#define PCIE_EEP_PORT_LOGIC1_REG                  (0x704)
+#define PCIE_EEP_PORT_LOGIC2_REG                  (0x708)
+#define PCIE_EEP_PORT_LOGIC3_REG                  (0x70C)
+#define PCIE_EEP_PORT_LOGIC4_REG                  (0x710)
+#define PCIE_EEP_PORT_LOGIC5_REG                  (0x714)
+#define PCIE_EEP_PORT_LOGIC6_REG                  (0x718)
+#define PCIE_EEP_PORT_LOGIC7_REG                  (0x71C)
+#define PCIE_EEP_PORT_LOGIC8_REG                  (0x720)
+#define PCIE_EEP_PORT_LOGIC9_REG                  (0x724)
+#define PCIE_EEP_PORT_LOGIC10_REG                 (0x728)
+#define PCIE_EEP_PORT_LOGIC11_REG                 (0x72C)
+#define PCIE_EEP_PORT_LOGIC12_REG                 (0x730)
+#define PCIE_EEP_PORT_LOGIC13_REG                 (0x734)
+#define PCIE_EEP_PORT_LOGIC14_REG                 (0x738)
+#define PCIE_EEP_PORT_LOGIC15_REG                 (0x73C)
+#define PCIE_EEP_PORT_LOGIC16_REG                 (0x748)
+#define PCIE_EEP_PORT_LOGIC17_REG                 (0x74C)
+#define PCIE_EEP_PORT_LOGIC18_REG                 (0x750)
+#define PCIE_EEP_PORT_LOGIC19_REG                 (0x7A8)
+#define PCIE_EEP_PORT_LOGIC20_REG                 (0x7AC)
+#define PCIE_EEP_PORT_LOGIC21_REG                 (0x7B0)
+#define PCIE_EEP_PORT_LOGIC22_REG                 (0x80C)
+#define PCIE_EEP_PORTLOGIC23_REG                  (0x810)
+#define PCIE_EEP_PORTLOGIC24_REG                  (0x814)
+#define PCIE_EEP_PORTLOGIC25_REG                  (0x818)
+#define PCIE_EEP_PORTLOGIC26_REG                  (0x81C)
+#define PCIE_EEP_PORTLOGIC27_REG                  (0x820)
+#define PCIE_EEP_PORTLOGIC28_REG                  (0x824)
+#define PCIE_EEP_PORTLOGIC29_REG                  (0x828)
+#define PCIE_EEP_PORTLOGIC30_REG                  (0x82C)
+#define PCIE_EEP_PORTLOGIC31_REG                  (0x830)
+#define PCIE_EEP_PORTLOGIC32_REG                  (0x834)
+#define PCIE_EEP_PORTLOGIC33_REG                  (0x838)
+#define PCIE_EEP_PORTLOGIC34_REG                  (0x83C)
+#define PCIE_EEP_PORTLOGIC35_REG                  (0x840)
+#define PCIE_EEP_PORTLOGIC36_REG                  (0x844)
+#define PCIE_EEP_PORTLOGIC37_REG                  (0x848)
+#define PCIE_EEP_PORTLOGIC38_REG                  (0x84C)
+#define PCIE_EEP_PORTLOGIC39_REG                  (0x850)
+#define PCIE_EEP_PORTLOGIC40_REG                  (0x854)
+#define PCIE_EEP_PORTLOGIC41_REG                  (0x858)
+#define PCIE_EEP_PORTLOGIC42_REG                  (0x85C)
+#define PCIE_EEP_PORTLOGIC43_REG                  (0x860)
+#define PCIE_EEP_PORTLOGIC44_REG                  (0x864)
+#define PCIE_EEP_PORTLOGIC45_REG                  (0x868)
+#define PCIE_EEP_PORTLOGIC46_REG                  (0x86C)
+#define PCIE_EEP_PORTLOGIC47_REG                  (0x870)
+#define PCIE_EEP_PORTLOGIC48_REG                  (0x874)
+#define PCIE_EEP_PORTLOGIC49_REG                  (0x878)
+#define PCIE_EEP_PORTLOGIC50_REG                  (0x87C)
+#define PCIE_EEP_PORTLOGIC51_REG                  (0x880)
+#define PCIE_EEP_PORTLOGIC52_REG                  (0x884)
+#define PCIE_EEP_PORTLOGIC53_REG                  (0x888)
+#define PCIE_EEP_GEN3_CONTRL_REG                  (0x890)
+#define PCIE_EEP_PIPE_LOOPBACK_REG                (0x8B8)
+#define PCIE_EEP_PORTLOGIC54_REG                  (0x900)
+#define PCIE_EEP_PORTLOGIC55_REG                  (0x904)
+#define PCIE_EEP_PORTLOGIC56_REG                  (0x908)
+#define PCIE_EEP_PORTLOGIC57_REG                  (0x90C)
+#define PCIE_EEP_PORTLOGIC58_REG                  (0x910)
+#define PCIE_EEP_PORTLOGIC59_REG                  (0x914)
+#define PCIE_EEP_PORTLOGIC60_REG                  (0x918)
+#define PCIE_EEP_PORTLOGIC61_REG                  (0x91C)
+#define PCIE_EEP_PORTLOGIC62_REG                  (0x97C)
+#define PCIE_EEP_PORTLOGIC63_REG                  (0x980)
+#define PCIE_EEP_PORTLOGIC64_REG                  (0x99C)
+#define PCIE_EEP_PORTLOGIC65_REG                  (0x9A0)
+#define PCIE_EEP_PORTLOGIC66_REG                  (0x9BC)
+#define PCIE_EEP_PORTLOGIC67_REG                  (0x9C4)
+#define PCIE_EEP_PORTLOGIC68_REG                  (0x9C8)
+#define PCIE_EEP_PORTLOGIC69_REG                  (0x9CC)
+#define PCIE_EEP_PORTLOGIC70_REG                  (0x9D0)
+#define PCIE_EEP_PORTLOGIC71_REG                  (0x9D4)
+#define PCIE_EEP_PORTLOGIC72_REG                  (0x9D8)
+#define PCIE_EEP_PORTLOGIC73_REG                  (0x9DC)
+#define PCIE_EEP_PORTLOGIC74_REG                  (0x9E0)
+#define PCIE_EEP_PORTLOGIC75_REG                  (0xA00)
+#define PCIE_EEP_PORTLOGIC76_REG                  (0xA10)
+#define PCIE_EEP_PORTLOGIC77_REG                  (0xA18)
+#define PCIE_EEP_PORTLOGIC78_REG                  (0xA1C)
+#define PCIE_EEP_PORTLOGIC79_REG                  (0xA24)
+#define PCIE_EEP_PORTLOGIC80_REG                  (0xA28)
+#define PCIE_EEP_PORTLOGIC81_REG                  (0xA34)
+#define PCIE_EEP_PORTLOGIC82_REG                  (0xA3C)
+#define PCIE_EEP_PORTLOGIC83_REG                  (0xA40)
+#define PCIE_EEP_PORTLOGIC84_REG                  (0xA44)
+#define PCIE_EEP_PORTLOGIC85_REG                  (0xA48)
+#define PCIE_EEP_PORTLOGIC86_REG                  (0xA6C)
+#define PCIE_EEP_PORTLOGIC87_REG                  (0xA70)
+#define PCIE_EEP_PORTLOGIC88_REG                  (0xA78)
+#define PCIE_EEP_PORTLOGIC89_REG                  (0xA7C)
+#define PCIE_EEP_PORTLOGIC90_REG                  (0xA80)
+#define PCIE_EEP_PORTLOGIC91_REG                  (0xA84)
+#define PCIE_EEP_PORTLOGIC92_REG                  (0xA88)
+#define PCIE_EEP_PORTLOGIC93_REG                  (0xA8C)
+#define PCIE_EEP_PORTLOGIC94_REG                  (0xA90)
+
+//pcie iatu internal registers define
+#define IATU_OFFSET     0x700
+#define IATU_VIEW_POINT 0x200
+#define IATU_REGION_CTRL1 0x204
+#define IATU_REGION_CTRL2 0x208
+#define IATU_REGION_BASE_LOW 0x20C
+#define IATU_REGION_BASE_HIGH 0x210
+#define IATU_REGION_BASE_LIMIT 0x214
+#define IATU_REGION_TARGET_LOW 0x218
+#define IATU_REGION_TARGET_HIGH 0x21C
+#define IATU_SHIIF_MODE 0x90000000
+#define IATU_NORMAL_MODE 0x80000000
+#define IATU_CTRL1_TYPE_CONFIG0 0x4
+#define IATU_CTRL1_TYPE_CONFIG1 0x5
+#define IATU_CTRL1_TYPE_MEM 0
+#define IATU_CTRL1_TYPE_IO 2
+
+
+typedef union tagPipeLoopBack
+{
+    struct
+    {
+        UINT32    reserved             : 31  ;
+        UINT32    pipe_loopback_enable             : 1  ;
+    }Bits;
+    UINT32    UInt32;
+}PCIE_PIPE_LOOPBACK_U;
+
+typedef union tagEepPciCfgHdr0
+{
+
+    struct
+    {
+        UINT32    vendor_id             : 16  ;
+        UINT32    device_id             : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR0_U;
+
+
+
+typedef union tagEepPciCfgHdr1
+{
+
+    struct
+    {
+        UINT32    io_space_enable       : 1   ;
+        UINT32    memory_space_enable   : 1   ;
+        UINT32    bus_master_enable     : 1   ;
+        UINT32    specialcycleenable    : 1   ;
+        UINT32    memory_write_and_invalidate  : 1   ;
+        UINT32    vga_palette_snoop_enable  : 1   ;
+        UINT32    parity_error_response  : 1   ;
+        UINT32    idsel_stepping_waitcycle_control  : 1   ;
+        UINT32    serr_enable           : 1   ;
+        UINT32    fastback_to_backenable  : 1   ;
+        UINT32    interrupt_disable     : 1   ;
+        UINT32    Reserved_2            : 5   ;
+        UINT32    Reserved_1            : 3   ;
+        UINT32    intx_status           : 1   ;
+        UINT32    capabilitieslist      : 1   ;
+        UINT32    pcibus66mhzcapable    : 1   ;
+        UINT32    Reserved_0            : 1   ;
+        UINT32    fastback_to_back      : 1   ;
+        UINT32    masterdataparityerror  : 1   ;
+        UINT32    devsel_timing         : 2   ;
+        UINT32    signaled_target_abort  : 1   ;
+        UINT32    received_target_abort  : 1   ;
+        UINT32    received_master_abort  : 1   ;
+        UINT32    signaled_system_error  : 1   ;
+        UINT32    detected_parity_error  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR1_U;
+
+typedef union tagEepPciCfgHdr2
+{
+
+    struct
+    {
+        UINT32    revision_identification  : 8   ;
+        UINT32    Reserved_3            : 8   ;
+        UINT32    sub_class             : 8   ;
+        UINT32    baseclass             : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR2_U;
+
+
+
+typedef union tagEepPciCfgHdr3
+{
+
+    struct
+    {
+        UINT32    cache_line_size       : 8   ;
+        UINT32    mstr_lat_tmr          : 8   ;
+        UINT32    multi_function_device  : 7   ;
+        UINT32    hdr_type              : 1   ;
+        UINT32    bist                  : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR3_U;
+
+
+
+typedef union tagEepPciCfgHdr4
+{
+
+    struct
+    {
+        UINT32    sbar01_space_inicator  : 1   ;
+        UINT32    sbar01_type           : 2   ;
+        UINT32    sbar01_prefetchable   : 1   ;
+        UINT32    sbar01_lower          : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR4_U;
+
+
+
+typedef union tagEepPciCfgHdr6
+{
+
+    struct
+    {
+        UINT32    sbar23_space_inicator  : 1   ;
+        UINT32    sbar23_type           : 2   ;
+        UINT32    sbar23_prefetchable   : 1   ;
+        UINT32    Reserved_4            : 8   ;
+        UINT32    sbar23_lower          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR6_U;
+
+
+
+typedef union tagEepPciCfgHdr8
+{
+
+    struct
+    {
+        UINT32    sbar45_space_inicator  : 1   ;
+        UINT32    sbar45_type           : 2   ;
+        UINT32    sbar45_prefetchable   : 1   ;
+        UINT32    Reserved_5            : 8   ;
+        UINT32    sbar45_lower          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR8_U;
+
+
+
+typedef union tagEepPciCfgHdr11
+{
+
+    struct
+    {
+        UINT32    subsystem_vendor_id   : 16  ;
+        UINT32    subsystemid           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR11_U;
+
+
+
+typedef union tagEepPciCfgHdr13
+{
+
+    struct
+    {
+        UINT32    capptr                : 8   ;
+        UINT32    Reserved_6            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR13_U;
+
+
+
+typedef union tagEepPciCfgHdr15
+{
+
+    struct
+    {
+        UINT32    int_line              : 8   ;
+        UINT32    int_pin               : 8   ;
+        UINT32    Min_Grant             : 8   ;
+        UINT32    Max_Latency           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_CFG_HDR15_U;
+
+
+
+typedef union tagEepPciMsiCap0
+{
+
+    struct
+    {
+        UINT32    msi_cap_id            : 8   ;
+        UINT32    next_capability_pointer  : 8   ;
+        UINT32    msi_enabled           : 1   ;
+        UINT32    multiple_message_capable  : 3   ;
+        UINT32    multiple_message_enabled  : 3   ;
+        UINT32    msi_64_en             : 1   ;
+        UINT32    pvm_en                : 1   ;
+        UINT32    message_control_register  : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP0_U;
+
+
+
+typedef union tagEepPciMsiCap1
+{
+
+    struct
+    {
+        UINT32    Reserved_11           : 2   ;
+        UINT32    msi_addr_low          : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP1_U;
+
+
+
+typedef union tagEepPciMsiCap3
+{
+
+    struct
+    {
+        UINT32    msi_data              : 16  ;
+        UINT32    Reserved_12           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCI_MSI_CAP3_U;
+
+
+
+typedef union tagEepPcieCap0
+{
+
+    struct
+    {
+        UINT32    pcie_cap_id           : 8   ;
+        UINT32    pcie_next_ptr         : 8   ;
+        UINT32    pcie_capability_version  : 4   ;
+        UINT32    device_port_type      : 4   ;
+        UINT32    slot_implemented      : 1   ;
+        UINT32    interrupt_message_number  : 5   ;
+        UINT32    Reserved_13           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP0_U;
+
+
+
+typedef union tagEepPcieCap1
+{
+
+    struct
+    {
+        UINT32    max_payload_size_supported  : 3   ;
+        UINT32    phantom_function_supported  : 2   ;
+        UINT32    extended_tagEepfield_supported  : 1   ;
+        UINT32    endpoint_l0sacceptable_latency  : 3   ;
+        UINT32    endpoint_l1acceptable_latency  : 3   ;
+        UINT32    undefined             : 3   ;
+        UINT32    Reserved_16           : 3   ;
+        UINT32    captured_slot_power_limit_value  : 8   ;
+        UINT32    captured_slot_power_limit_scale  : 2   ;
+        UINT32    function_level_reset  : 1   ;
+        UINT32    Reserved_15           : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP1_U;
+
+
+
+typedef union tagEepPcieCap2
+{
+
+    struct
+    {
+        UINT32    correctable_error_reporting_enable  : 1   ;
+        UINT32    non_fatal_error_reporting_enable  : 1   ;
+        UINT32    fatal_error_reporting_enable  : 1   ;
+        UINT32    urenable              : 1   ;
+        UINT32    enable_relaxed_ordering  : 1   ;
+        UINT32    max_payload_size      : 3   ;
+        UINT32    extended_tagEepfieldenable  : 1   ;
+        UINT32    phantom_function_enable  : 1   ;
+        UINT32    auxpowerpmenable      : 1   ;
+        UINT32    enablenosnoop         : 1   ;
+        UINT32    max_read_request_size  : 3   ;
+        UINT32    Reserved_18           : 1   ;
+        UINT32    correctableerrordetected  : 1   ;
+        UINT32    non_fatalerrordetected  : 1   ;
+        UINT32    fatalerrordetected    : 1   ;
+        UINT32    unsupportedrequestdetected  : 1   ;
+        UINT32    auxpowerdetected      : 1   ;
+        UINT32    transactionpending    : 1   ;
+        UINT32    Reserved_17           : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP2_U;
+
+
+
+typedef union tagEepPcieCap3
+{
+
+    struct
+    {
+        UINT32    max_link_speed        : 4   ;
+        UINT32    max_link_width        : 6   ;
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    l0s_exitlatency       : 3   ;
+        UINT32    l1_exit_latency       : 3   ;
+        UINT32    clock_power_management  : 1   ;
+        UINT32    surprise_down_error_report_cap  : 1   ;
+        UINT32    data_link_layer_active_report_cap  : 1   ;
+        UINT32    link_bandwidth_noti_cap  : 1   ;
+        UINT32    aspm_option_compliance  : 1   ;
+        UINT32    Reserved_19           : 1   ;
+        UINT32    port_number           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagEepPcieCap4
+{
+
+    struct
+    {
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    Reserved_22           : 1   ;
+        UINT32    rcb                   : 1   ;
+        UINT32    link_disable          : 1   ;
+        UINT32    retrain_link          : 1   ;
+        UINT32    common_clock_config   : 1   ;
+        UINT32    extended_sync         : 1   ;
+        UINT32    enable_clock_pwr_management  : 1   ;
+        UINT32    hw_auto_width_disable  : 1   ;
+        UINT32    link_bandwidth_management_int_en  : 1   ;
+        UINT32    link_auto_bandwidth_int_en  : 1   ;
+        UINT32    Reserved_21           : 4   ;
+        UINT32    current_link_speed    : 4   ;
+        UINT32    negotiated_link_width  : 6   ;
+        UINT32    Reserved_20           : 1   ;
+        UINT32    link_training         : 1   ;
+        UINT32    slot_clock_configration  : 1   ;
+        UINT32    data_link_layer_active  : 1   ;
+        UINT32    link_bandwidth_management_status  : 1   ;
+        UINT32    link_auto_bandwidth_status  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagEepPcieCap5
+{
+
+    struct
+    {
+        UINT32    attentioonbuttonpresent  : 1   ;
+        UINT32    powercontrollerpresent  : 1   ;
+        UINT32    mrlsensorpresent      : 1   ;
+        UINT32    attentionindicatorpresent  : 1   ;
+        UINT32    powerindicatorpresent  : 1   ;
+        UINT32    hot_plugsurprise      : 1   ;
+        UINT32    hot_plugcapable       : 1   ;
+        UINT32    slotpowerlimitvalue   : 8   ;
+        UINT32    slotpowerlimitscale   : 2   ;
+        UINT32    electromechanicalinterlockpresen  : 1   ;
+        UINT32    no_cmd_complete_support  : 1   ;
+        UINT32    phy_slot_number       : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagEepPcieCap6
+{
+
+    struct
+    {
+        UINT32    attentionbuttonpressedenable  : 1   ;
+        UINT32    powerfaultdetectedenable  : 1   ;
+        UINT32    mrlsensorchangedenable  : 1   ;
+        UINT32    presencedetectchangedenable  : 1   ;
+        UINT32    commandcompletedinterruptenable  : 1   ;
+        UINT32    hot_pluginterruptenable  : 1   ;
+        UINT32    attentionindicatorcontrol  : 2   ;
+        UINT32    powerindicatorcontrol  : 2   ;
+        UINT32    powercontrollercontrol  : 1   ;
+        UINT32    electromechanicalinterlockcontrol  : 1   ;
+        UINT32    datalinklayerstatechangedenable  : 1   ;
+        UINT32    Reserved_23           : 3   ;
+        UINT32    attentionbuttonpressed  : 1   ;
+        UINT32    powerfaultdetected    : 1   ;
+        UINT32    mrlsensorchanged      : 1   ;
+        UINT32    presencedetectchanged  : 1   ;
+        UINT32    commandcompleted      : 1   ;
+        UINT32    mrlsensorstate        : 1   ;
+        UINT32    presencedetectstate   : 1   ;
+        UINT32    electromechanicalinterlockstatus  : 1   ;
+        UINT32    datalinklayerstatechanged  : 1   ;
+        UINT32    slot_ctrl_status      : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagEepPcieCap7
+{
+
+    struct
+    {
+        UINT32    systemerroroncorrectableerrorenable  : 1   ;
+        UINT32    systemerroronnon_fatalerrorenable  : 1   ;
+        UINT32    systemerroronfatalerrorenable  : 1   ;
+        UINT32    pmeinterruptenable    : 1   ;
+        UINT32    crssoftwarevisibilityenable  : 1   ;
+        UINT32    Reserved_24           : 11  ;
+        UINT32    crssoftwarevisibility  : 1   ;
+        UINT32    root_cap              : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagEepPcieCap8
+{
+
+    struct
+    {
+        UINT32    pmerequesterid        : 16  ;
+        UINT32    pmestatus             : 1   ;
+        UINT32    pmepending            : 1   ;
+        UINT32    root_status           : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagEepPcieCap9
+{
+
+    struct
+    {
+        UINT32    completiontimeoutrangessupported  : 4   ;
+        UINT32    completiontimeoutdisablesupported  : 1   ;
+        UINT32    ariforwardingsupported  : 1   ;
+        UINT32    atomicoproutingsupported  : 1   ;
+        UINT32    _2_bitatomicopcompletersupported  : 1   ;
+        UINT32    _4_bitatomicopcompletersupported  : 1   ;
+        UINT32    _28_bitcascompletersupported  : 1   ;
+        UINT32    noro_enabledpr_prpassing  : 1   ;
+        UINT32    Reserved_25           : 1   ;
+        UINT32    tphcompletersupported  : 2   ;
+        UINT32    dev_cap2              : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagEepPcieCap10
+{
+
+    struct
+    {
+        UINT32    completiontimeoutvalue  : 4   ;
+        UINT32    completiontimeoutdisable  : 1   ;
+        UINT32    ariforwardingsupported  : 1   ;
+        UINT32    atomicoprequesterenable  : 1   ;
+        UINT32    atomicopegressblocking  : 1   ;
+        UINT32    idorequestenable      : 1   ;
+        UINT32    idocompletionenable   : 1   ;
+        UINT32    dev_ctrl2             : 22  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagEepPcieCap11
+{
+
+    struct
+    {
+        UINT32    Reserved_27           : 1   ;
+        UINT32    gen1_suport           : 1   ;
+        UINT32    gen2_suport           : 1   ;
+        UINT32    gen3_suport           : 1   ;
+        UINT32    Reserved_26           : 4   ;
+        UINT32    crosslink_supported   : 1   ;
+        UINT32    link_cap2             : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagEepPcieCap12
+{
+
+    struct
+    {
+        UINT32    targetlinkspeed       : 4   ;
+        UINT32    entercompliance       : 1   ;
+        UINT32    hardwareautonomousspeeddisa  : 1   ;
+        UINT32    selectablede_empha    : 1   ;
+        UINT32    transmitmargin        : 3   ;
+        UINT32    _entermodifiedcompliance  : 1   ;
+        UINT32    compliancesos         : 1   ;
+        UINT32    de_emphasislevel      : 4   ;
+        UINT32    currentde_emphasislevel  : 1   ;
+        UINT32    equalizationcomplete  : 1   ;
+        UINT32    equalizationphase1successful  : 1   ;
+        UINT32    equalizationphase2successful  : 1   ;
+        UINT32    equalizationphase3successful  : 1   ;
+        UINT32    linkequalizationrequest  : 1   ;
+        UINT32    link_ctrl2_status2    : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagEepSlotCap
+{
+
+    struct
+    {
+        UINT32    slotnumberingcapabilitiesid  : 8   ;
+        UINT32    nextcapabilitypointer  : 8   ;
+        UINT32    add_incardslotsprovided  : 5   ;
+        UINT32    firstinchassis        : 1   ;
+        UINT32    Reserved_28           : 2   ;
+        UINT32    slot_cap              : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagEepAerCap0
+{
+
+    struct
+    {
+        UINT32    pciexpressextendedcapabilityid  : 16  ;
+        UINT32    capabilityversion     : 4   ;
+        UINT32    aer_cap_hdr           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP0_U;
+
+
+
+
+typedef union tagEepAerCap1
+{
+
+    struct
+    {
+        UINT32    Reserved_34           : 1   ;
+        UINT32    Reserved_33           : 3   ;
+        UINT32    datalinkprotocolerrorsta  : 1   ;
+        UINT32    surprisedownerrorstatus  : 1   ;
+        UINT32    Reserved_32           : 6   ;
+        UINT32    poisonedtlpstatu      : 1   ;
+        UINT32    flowcontrolprotocolerrorst  : 1   ;
+        UINT32    completiontimeouts    : 1   ;
+        UINT32    completerabortstatus  : 1   ;
+        UINT32    receiveroverflowstatus  : 1   ;
+        UINT32    malformedtlpstatus    : 1   ;
+        UINT32    ecrcerrorstatus       : 1   ;
+        UINT32    ecrcerrorstat         : 1   ;
+        UINT32    unsupportedrequesterrorstatus  : 1   ;
+        UINT32    Reserved_31           : 3   ;
+        UINT32    atomicopegressblockedstatus  : 1   ;
+        UINT32    uncorr_err_status     : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP1_U;
+
+
+
+
+typedef union tagEepAerCap2
+{
+
+    struct
+    {
+        UINT32    Reserved_38           : 1   ;
+        UINT32    Reserved_37           : 3   ;
+        UINT32    datalinkprotocolerrormask  : 1   ;
+        UINT32    surprisedownerrormask  : 1   ;
+        UINT32    Reserved_36           : 6   ;
+        UINT32    poisonedtlpmask       : 1   ;
+        UINT32    flowcontrolprotocolerrormask  : 1   ;
+        UINT32    completiontimeoutmask  : 1   ;
+        UINT32    completerabortmask    : 1   ;
+        UINT32    unexpectedcompletionmask  : 1   ;
+        UINT32    receiveroverflowmask  : 1   ;
+        UINT32    malformedtlpmask      : 1   ;
+        UINT32    ecrcerrormask         : 1   ;
+        UINT32    unsupportedrequesterrormask  : 1   ;
+        UINT32    Reserved_35           : 3   ;
+        UINT32    atomicopegressblockedmask  : 1   ;
+        UINT32    uncorr_err_mask       : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP2_U;
+
+
+
+
+typedef union tagEepAerCap3
+{
+
+    struct
+    {
+        UINT32    Reserved_42           : 1   ;
+        UINT32    Reserved_41           : 3   ;
+        UINT32    datalinkprotocolerrorsever  : 1   ;
+        UINT32    surprisedownerrorseverity  : 1   ;
+        UINT32    Reserved_40           : 6   ;
+        UINT32    poisonedtlpseverity   : 1   ;
+        UINT32    flowcontrolprotocolerrorseveri  : 1   ;
+        UINT32    completiontimeoutseverity  : 1   ;
+        UINT32    completerabortseverity  : 1   ;
+        UINT32    unexpectedcompletionseverity  : 1   ;
+        UINT32    receiveroverflowseverity  : 1   ;
+        UINT32    malformedtlpseverity  : 1   ;
+        UINT32    ecrcerrorseverity     : 1   ;
+        UINT32    unsupportedrequesterrorseverity  : 1   ;
+        UINT32    Reserved_39           : 3   ;
+        UINT32    atomicopegressblockedseverity  : 1   ;
+        UINT32    uncorr_err_ser        : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP3_U;
+
+
+
+
+typedef union tagEepAerCap4
+{
+
+    struct
+    {
+        UINT32    receivererrorstatus   : 1   ;
+        UINT32    Reserved_44           : 5   ;
+        UINT32    badtlpstatus          : 1   ;
+        UINT32    baddllpstatus         : 1   ;
+        UINT32    replay_numrolloverstatus  : 1   ;
+        UINT32    Reserved_43           : 3   ;
+        UINT32    replytimertimeoutstatus  : 1   ;
+        UINT32    advisorynon_fatalerrorstatus  : 1   ;
+        UINT32    corr_err_status       : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP4_U;
+
+
+
+
+typedef union tagEepAerCap5
+{
+
+    struct
+    {
+        UINT32    receivererrormask     : 1   ;
+        UINT32    Reserved_46           : 5   ;
+        UINT32    badtlpmask            : 1   ;
+        UINT32    baddllpmask           : 1   ;
+        UINT32    replay_numrollovermask  : 1   ;
+        UINT32    Reserved_45           : 3   ;
+        UINT32    replytimertimeoutmask  : 1   ;
+        UINT32    advisorynon_fatalerrormask  : 1   ;
+        UINT32    corr_err_mask         : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP5_U;
+
+
+
+
+typedef union tagEepAerCap6
+{
+
+    struct
+    {
+        UINT32    firsterrorpointer     : 5   ;
+        UINT32    ecrcgenerationcapability  : 1   ;
+        UINT32    ecrcgenerationenable  : 1   ;
+        UINT32    ecrccheckcapable      : 1   ;
+        UINT32    ecrccheckenable       : 1   ;
+        UINT32    adv_cap_ctrl          : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP6_U;
+
+typedef union tagGen3Ctrol
+{
+    struct
+    {
+        UINT32    reserved     : 16   ;
+        UINT32    equalization_disable     : 1   ;
+        UINT32    reserved2     : 15   ;
+    }Bits;
+    UINT32    UInt32;
+}PCIE_GRN3_CONTRL;
+
+
+
+
+typedef union tagEepAerCap11
+{
+
+    struct
+    {
+        UINT32    correctableerrorreportingenable  : 1   ;
+        UINT32    non_fatalerrorreportingenable  : 1   ;
+        UINT32    fatalerrorreportingenable  : 1   ;
+        UINT32    root_err_cmd          : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP11_U;
+
+
+
+
+typedef union tagEepAerCap12
+{
+
+    struct
+    {
+        UINT32    err_correceived       : 1   ;
+        UINT32    multipleerr_correceived  : 1   ;
+        UINT32    err_fatal_nonfatalreceived  : 1   ;
+        UINT32    multipleerr_fatal_nonfatalreceived  : 1   ;
+        UINT32    firstuncorrectablefatal  : 1   ;
+        UINT32    non_fatalerrormessagesreceived  : 1   ;
+        UINT32    fatalerrormessagesreceived  : 1   ;
+        UINT32    Reserved_47           : 20  ;
+        UINT32    root_err_status       : 5   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP12_U;
+
+
+
+
+typedef union tagEepAerCap13
+{
+
+    struct
+    {
+        UINT32    err_corsourceidentification  : 16  ;
+        UINT32    err_src_id            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_AER_CAP13_U;
+
+
+
+
+typedef union tagEepVcCap0
+{
+
+    struct
+    {
+        UINT32    pciexpressextendedcapabilityid  : 16  ;
+        UINT32    capabilityversion     : 4   ;
+        UINT32    vc_cap_hdr            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP0_U;
+
+
+
+
+typedef union tagEepVcCap1
+{
+
+    struct
+    {
+        UINT32    extendedvccount       : 3   ;
+        UINT32    Reserved_50           : 1   ;
+        UINT32    lowpriorityextendedvccount  : 3   ;
+        UINT32    Reserved_49           : 1   ;
+        UINT32    referenceclock        : 2   ;
+        UINT32    portarbitrationtableentrysize  : 2   ;
+        UINT32    vc_cap1               : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP1_U;
+
+
+
+
+typedef union tagEepVcCap2
+{
+
+    struct
+    {
+        UINT32    vcarbitrationcapability  : 8   ;
+        UINT32    Reserved_51           : 16  ;
+        UINT32    vc_cap2               : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP2_U;
+
+
+
+
+typedef union tagEepVcCap3
+{
+
+    struct
+    {
+        UINT32    loadvcarbitrationtable  : 1   ;
+        UINT32    vcarbitrationselect   : 3   ;
+        UINT32    Reserved_53           : 12  ;
+        UINT32    arbitrationtablestatus  : 1   ;
+        UINT32    Reserved_52           : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP3_U;
+
+
+
+
+typedef union tagEepVcCap4
+{
+
+    struct
+    {
+        UINT32    portarbitrationcapability  : 8   ;
+        UINT32    Reserved_56           : 6   ;
+        UINT32    Reserved_55           : 1   ;
+        UINT32    rejectsnooptransactions  : 1   ;
+        UINT32    maximumtimeslots      : 7   ;
+        UINT32    Reserved_54           : 1   ;
+        UINT32    vc_res_cap            : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP4_U;
+
+
+
+
+typedef union tagEepVcCap5
+{
+
+    struct
+    {
+        UINT32    tc_vcmap              : 8   ;
+        UINT32    Reserved_59           : 8   ;
+        UINT32    loadportarbitrationtable  : 1   ;
+        UINT32    portarbitrationselec  : 3   ;
+        UINT32    Reserved_58           : 4   ;
+        UINT32    vcid                  : 3   ;
+        UINT32    Reserved_57           : 4   ;
+        UINT32    vc_res_ctrl           : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP5_U;
+
+
+
+
+typedef union tagEepVcCap6
+{
+
+    struct
+    {
+        UINT32    Reserved_60           : 16  ;
+        UINT32    portarbitrationtablestatus  : 1   ;
+        UINT32    vcnegotiationpending  : 1   ;
+        UINT32    vc_res_status         : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP6_U;
+
+
+
+
+typedef union tagEepVcCap7
+{
+
+    struct
+    {
+        UINT32    portarbitrationcapability  : 8   ;
+        UINT32    Reserved_63           : 6   ;
+        UINT32    Reserved_62           : 1   ;
+        UINT32    rejectsnooptransactions  : 1   ;
+        UINT32    maximumtimeslots      : 7   ;
+        UINT32    Reserved_61           : 1   ;
+        UINT32    vc_res_cap0           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP7_U;
+
+
+
+
+typedef union tagEepVcCap8
+{
+
+    struct
+    {
+        UINT32    tc_vcmap              : 8   ;
+        UINT32    Reserved_66           : 8   ;
+        UINT32    loadportarbitrationtable  : 1   ;
+        UINT32    portarbitrationselect  : 3   ;
+        UINT32    Reserved_65           : 4   ;
+        UINT32    vcid                  : 3   ;
+        UINT32    Reserved_64           : 4   ;
+        UINT32    vc_res_ctrl0          : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP8_U;
+
+
+
+
+typedef union tagEepVcCap9
+{
+
+    struct
+    {
+        UINT32    Reserved_67           : 16  ;
+        UINT32    arbitrationtablestatus  : 1   ;
+        UINT32    vcnegotiationpending  : 1   ;
+        UINT32    vc_res_status0        : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_VC_CAP9_U;
+
+
+
+
+typedef union tagEepPortLogic0
+{
+
+    struct
+    {
+        UINT32    ack_lat_timer         : 16  ;
+        UINT32    replay_timer          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagEepPortLogic2
+{
+
+    struct
+    {
+        UINT32    linknumber            : 8   ;
+        UINT32    Reserved_70           : 7   ;
+        UINT32    forcelink             : 1   ;
+        UINT32    linkstate             : 6   ;
+        UINT32    Reserved_69           : 2   ;
+        UINT32    port_force_link       : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagEepPortLogic3
+{
+
+    struct
+    {
+        UINT32    ackfrequency          : 8   ;
+        UINT32    n_fts                 : 8   ;
+        UINT32    commonclockn_fts      : 8   ;
+        UINT32    l0sentrancelatency    : 3   ;
+        UINT32    l1entrancelatency     : 3   ;
+        UINT32    enteraspml1withoutreceiveinl0s  : 1   ;
+        UINT32    ack_aspm              : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagEepPortLogic4
+{
+
+    struct
+    {
+        UINT32    vendorspecificdllprequest  : 1   ;
+        UINT32    scrambledisable       : 1   ;
+        UINT32    loopbackenable        : 1   ;
+        UINT32    resetassert           : 1   ;
+        UINT32    Reserved_73           : 1   ;
+        UINT32    dlllinkenable         : 1   ;
+        UINT32    Reserved_72           : 1   ;
+        UINT32    fastlinkmode          : 1   ;
+        UINT32    Reserved_71           : 8   ;
+        UINT32    linkmodeenable        : 6   ;
+        UINT32    crosslinkenable       : 1   ;
+        UINT32    crosslinkactive       : 1   ;
+        UINT32    port_link_ctrl        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagEepPortLogic5
+{
+
+    struct
+    {
+        UINT32    insertlaneskewfortransmit  : 24  ;
+        UINT32    flowcontroldisable    : 1   ;
+        UINT32    ack_nakdisable        : 1   ;
+        UINT32    Reserved_74           : 5   ;
+        UINT32    lane_skew             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagEepPortLogic6
+{
+
+    struct
+    {
+        UINT32    numberoftssymbols     : 4   ;
+        UINT32    Reserved_76           : 4   ;
+        UINT32    numberofskpsymbols    : 3   ;
+        UINT32    Reserved_75           : 3   ;
+        UINT32    timermodifierforreplaytimer  : 5   ;
+        UINT32    timermodifierforack_naklatencytimer  : 5   ;
+        UINT32    timermodifierforflowcontrolwatchdogtimer  : 5   ;
+        UINT32    sym_num               : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagEepPortLogic7
+{
+
+    struct
+    {
+        UINT32    vc0posteddataqueuedepth  : 11  ;
+        UINT32    Reserved_77           : 4   ;
+        UINT32    sym_timer             : 1   ;
+        UINT32    maskfunctionmismatchfilteringfo  : 1   ;
+        UINT32    maskpoisonedtlpfiltering  : 1   ;
+        UINT32    maskbarmatchfiltering  : 1   ;
+        UINT32    masktype1configurationrequestfiltering  : 1   ;
+        UINT32    masklockedrequestfiltering  : 1   ;
+        UINT32    masktagerrorrulesforreceivedcompletions  : 1   ;
+        UINT32    maskrequesteridmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    maskfunctionmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    mask_traffic_classmis_match_error_forreceived_completions  : 1   ;
+        UINT32    mask_attributesmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    mask_length_mismatch_error_forreceive_dcompletions  : 1   ;
+        UINT32    maske_crcerror_filtering  : 1   ;
+        UINT32    maske_crcerror_filtering_forcompletions  : 1   ;
+        UINT32    message_control       : 1   ;
+        UINT32    maskfilteringofreceived  : 1   ;
+        UINT32    flt_mask1             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagEepPortLogic8
+{
+
+    struct
+    {
+        UINT32    cx_flt_mask_venmsg0_drop  : 1   ;
+        UINT32    cx_flt_mask_venmsg1_drop  : 1   ;
+        UINT32    cx_flt_mask_dabort_4ucpl  : 1   ;
+        UINT32    cx_flt_mask_handle_flush  : 1   ;
+        UINT32    flt_mask2             : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagEepPortLogic9
+{
+
+    struct
+    {
+        UINT32    amba_multi_outbound_decomp_np  : 1   ;
+        UINT32    amba_obnp_ctrl        : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagEepPortLogic12
+{
+
+    struct
+    {
+        UINT32    transmitposteddatafccredits  : 12  ;
+        UINT32    transmitpostedheaderfccredits  : 8   ;
+        UINT32    tx_pfc_status         : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagEepPortLogic13
+{
+
+    struct
+    {
+        UINT32    transmitnon_posteddatafccredits  : 12  ;
+        UINT32    transmitnon_postedheaderfccredits  : 8   ;
+        UINT32    tx_npfc_status        : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagEepPortLogic14
+{
+
+    struct
+    {
+        UINT32    transmitcompletiondatafccredits  : 12  ;
+        UINT32    transmitcompletionheaderfccredits  : 8   ;
+        UINT32    tx_cplfc_status       : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagEepPortLogic15
+{
+
+    struct
+    {
+        UINT32    rx_tlp_fc_credit_not_retured  : 1   ;
+        UINT32    tx_retry_buf_not_empty  : 1   ;
+        UINT32    rx_queue_not_empty    : 1   ;
+        UINT32    Reserved_79           : 13  ;
+        UINT32    fc_latency_timer_override_value  : 13  ;
+        UINT32    Reserved_78           : 2   ;
+        UINT32    fc_latency_timer_override_en  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagEepPortLogic16
+{
+
+    struct
+    {
+        UINT32    vc0posteddatacredits  : 12  ;
+        UINT32    vc0postedheadercredits  : 8   ;
+        UINT32    Reserved_81           : 1   ;
+        UINT32    vc0_postedtlpqueuemode  : 1   ;
+        UINT32    vc0postedtlpqueuemode  : 1   ;
+        UINT32    vc0postedtlpqueuemo   : 1   ;
+        UINT32    Reserved_80           : 6   ;
+        UINT32    tlptypeorderingforvc0  : 1   ;
+        UINT32    rx_pque_ctrl          : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagEepPortLogic17
+{
+
+    struct
+    {
+        UINT32    vc0non_posteddatacredits  : 12  ;
+        UINT32    vc0non_postedheadercredits  : 8   ;
+        UINT32    rx_npque_ctrl         : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagEepPortLogic18
+{
+
+    struct
+    {
+        UINT32    vco_comp_data_credits  : 12  ;
+        UINT32    vc0_cpl_header_credt  : 8   ;
+        UINT32    Reserved_83           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagEepPortLogic19
+{
+
+    struct
+    {
+        UINT32    vco_posted_data_que_path  : 14  ;
+        UINT32    Reserved_84           : 2   ;
+        UINT32    vco_posted_head_queue_depth  : 10  ;
+        UINT32    vc_pbuf_ctrl          : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagEepPortLogic20
+{
+
+    struct
+    {
+        UINT32    vco_np_data_que_depth  : 14  ;
+        UINT32    Reserved_86           : 2   ;
+        UINT32    vco_np_header_que_depth  : 10  ;
+        UINT32    vc_npbuf_ctrl         : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagEepPortLogic21
+{
+
+    struct
+    {
+        UINT32    vco_comp_data_queue_depth  : 14  ;
+        UINT32    Reserved_88           : 2   ;
+        UINT32    vco_posted_head_queue_depth  : 10  ;
+        UINT32    Reserved_87           : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagEepPortLogic22
+{
+
+    struct
+    {
+        UINT32    n_fts                 : 8   ;
+        UINT32    pre_determ_num_of_lane  : 9   ;
+        UINT32    det_sp_change         : 1   ;
+        UINT32    config_phy_tx_sw      : 1   ;
+        UINT32    config_tx_comp_rcv_bit  : 1   ;
+        UINT32    set_emp_level         : 1   ;
+        UINT32    Reserved_89           : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagEepPortlogic25
+{
+
+    struct
+    {
+        UINT32    remote_rd_req_size    : 3   ;
+        UINT32    Reserved_92           : 5   ;
+        UINT32    remote_max_brd_tag    : 8   ;
+        UINT32    Reserved_91           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagEepPortlogic26
+{
+
+    struct
+    {
+        UINT32    resize_master_resp_compser  : 1   ;
+        UINT32    axi_ctrl1             : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagEepPortlogic54
+{
+
+    struct
+    {
+        UINT32    region_index          : 4   ;
+        UINT32    Reserved_93           : 27  ;
+        UINT32    iatu_view             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagEepPortlogic55
+{
+
+    struct
+    {
+        UINT32    iatu1_type            : 5   ;
+        UINT32    iatu1_tc              : 3   ;
+        UINT32    iatu1_td              : 1   ;
+        UINT32    iatu1_attr            : 2   ;
+        UINT32    Reserved_97           : 5   ;
+        UINT32    iatu1_at              : 2   ;
+        UINT32    Reserved_96           : 2   ;
+        UINT32    iatu1_id              : 3   ;
+        UINT32    Reserved_95           : 9   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagEepPortlogic56
+{
+
+    struct
+    {
+        UINT32    iatu2_type            : 8   ;
+        UINT32    iatu2_bar_num         : 3   ;
+        UINT32    Reserved_101          : 3   ;
+        UINT32    iatu2_tc_match_en     : 1   ;
+        UINT32    iatu2_td_match_en     : 1   ;
+        UINT32    iatu2_attr_match_en   : 1   ;
+        UINT32    Reserved_100          : 1   ;
+        UINT32    iatu2_at_match_en     : 1   ;
+        UINT32    iatu2_func_num_match_en  : 1   ;
+        UINT32    iatu2_virtual_func_num_match_en  : 1   ;
+        UINT32    message_code_match_en  : 1   ;
+        UINT32    Reserved_99           : 2   ;
+        UINT32    iatu2_response_code   : 2   ;
+        UINT32    Reserved_98           : 1   ;
+        UINT32    iatu2_fuzzy_type_match_mode  : 1   ;
+        UINT32    iatu2_cfg_shift_mode  : 1   ;
+        UINT32    iatu2_ivert_mode      : 1   ;
+        UINT32    iatu2_match_mode      : 1   ;
+        UINT32    iatu2_region_en       : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagEepPortlogic57
+{
+
+    struct
+    {
+        UINT32    iatu_start_low        : 12  ;
+        UINT32    iatu_start_high       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagEepPortlogic59
+{
+
+    struct
+    {
+        UINT32    iatu_limit_low        : 12  ;
+        UINT32    iatu_limit_high       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagEepPortlogic60
+{
+
+    struct
+    {
+        UINT32    xlated_addr_high      : 12  ;
+        UINT32    xlated_addr_low       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagEepPortlogic62
+{
+
+    struct
+    {
+        UINT32    dma_wr_eng_en         : 1   ;
+        UINT32    dma_wr_ena            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagEepPortlogic63
+{
+
+    struct
+    {
+        UINT32    wr_doorbell_num       : 3   ;
+        UINT32    Reserved_103          : 28  ;
+        UINT32    dma_wr_dbell_stop     : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagEepPortlogic64
+{
+
+    struct
+    {
+        UINT32    dma_read_eng_en       : 1   ;
+        UINT32    Reserved_104          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagEepPortlogic65
+{
+
+    struct
+    {
+        UINT32    rd_doorbell_num       : 3   ;
+        UINT32    Reserved_106          : 28  ;
+        UINT32    dma_rd_dbell_stop     : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagEepPortlogic66
+{
+
+    struct
+    {
+        UINT32    done_int_status       : 8   ;
+        UINT32    Reserved_108          : 8   ;
+        UINT32    abort_int_status      : 8   ;
+        UINT32    Reserved_107          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagEepPortlogic67
+{
+
+    struct
+    {
+        UINT32    done_int_mask         : 8   ;
+        UINT32    Reserved_111          : 8   ;
+        UINT32    abort_int_mask        : 8   ;
+        UINT32    Reserved_110          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagEepPortlogic68
+{
+
+    struct
+    {
+        UINT32    done_int_clr          : 8   ;
+        UINT32    Reserved_114          : 8   ;
+        UINT32    abort_int_clr         : 8   ;
+        UINT32    Reserved_113          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagEepPortlogic69
+{
+
+    struct
+    {
+        UINT32    app_rd_err_det        : 8   ;
+        UINT32    Reserved_116          : 8   ;
+        UINT32    ll_element_fetch_err_det  : 8   ;
+        UINT32    Reserved_115          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagEepPortlogic74
+{
+
+    struct
+    {
+        UINT32    dma_wr_c0_imwr_data   : 16  ;
+        UINT32    dma_wr_c1_imwr_data   : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagEepPortlogic75
+{
+
+    struct
+    {
+        UINT32    wr_ch_ll_remote_abort_int_en  : 8   ;
+        UINT32    Reserved_118          : 8   ;
+        UINT32    wr_ch_ll_local_abort_int_en  : 8   ;
+        UINT32    Reserved_117          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagEepPortlogic76
+{
+
+    struct
+    {
+        UINT32    done_int_status       : 8   ;
+        UINT32    Reserved_121          : 8   ;
+        UINT32    abort_int_status      : 8   ;
+        UINT32    Reserved_120          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagEepPortlogic77
+{
+
+    struct
+    {
+        UINT32    done_int_mask         : 8   ;
+        UINT32    Reserved_123          : 8   ;
+        UINT32    abort_int_mask        : 8   ;
+        UINT32    dma_rd_int_mask       : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagEepPortlogic78
+{
+
+    struct
+    {
+        UINT32    done_int_clr          : 8   ;
+        UINT32    Reserved_125          : 8   ;
+        UINT32    abort_int_clr         : 8   ;
+        UINT32    dma_rd_int_clr        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagEepPortlogic79
+{
+
+    struct
+    {
+        UINT32    app_wr_err_det        : 8   ;
+        UINT32    Reserved_126          : 8   ;
+        UINT32    link_list_fetch_err_det  : 8   ;
+        UINT32    dma_rd_err_low        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagEepPortlogic80
+{
+
+    struct
+    {
+        UINT32    unspt_request         : 8   ;
+        UINT32    completer_abort       : 8   ;
+        UINT32    cpl_time_out          : 8   ;
+        UINT32    data_poison           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagEepPortlogic81
+{
+
+    struct
+    {
+        UINT32    remote_abort_int_en   : 8   ;
+        UINT32    Reserved_128          : 8   ;
+        UINT32    local_abort_int_en    : 8   ;
+        UINT32    dma_rd_ll_err_ena     : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagEepPortlogic86
+{
+
+    struct
+    {
+        UINT32    channel_dir           : 3   ;
+        UINT32    Reserved_131          : 28  ;
+        UINT32    dma_ch_con_idx        : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagEepPortlogic87
+{
+
+    struct
+    {
+        UINT32    cycle_bit             : 1   ;
+        UINT32    toggle_cycle_bit      : 1   ;
+        UINT32    load_link_pointer     : 1   ;
+        UINT32    local_int_en          : 1   ;
+        UINT32    remote_int_en         : 1   ;
+        UINT32    channel_status        : 2   ;
+        UINT32    Reserved_135          : 1   ;
+        UINT32    consumer_cycle_state  : 1   ;
+        UINT32    linked_list_en        : 1   ;
+        UINT32    Reserved_134          : 2   ;
+        UINT32    func_num_dma          : 5   ;
+        UINT32    Reserved_133          : 7   ;
+        UINT32    no_snoop              : 1   ;
+        UINT32    ro                    : 1   ;
+        UINT32    td                    : 1   ;
+        UINT32    tc                    : 3   ;
+        UINT32    dma_ch_ctrl           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagEepPortlogic93
+{
+
+    struct
+    {
+        UINT32    Reserved_137          : 2   ;
+        UINT32    dma_ll_ptr_low        : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EEP_PORTLOGIC93_U;
+
+
+
+#define PCIE_MEEP_SBAR23XLAT_LOWER_REG            (0x0)
+#define PCIE_MEEP_SBAR23XLAT_UPPER_REG            (0x4)
+#define PCIE_MEEP_SBAR45XLAT_LOWER_REG            (0x8)
+#define PCIE_MEEP_SBAR45XLAT_UPPER_REG            (0xC)
+#define PCIE_MEEP_SBAR23LMT_LOWER_REG             (0x10)
+#define PCIE_MEEP_SBAR23LMT_UPPER_REG             (0x14)
+#define PCIE_MEEP_SBAR45LMT_LOWER_REG             (0x18)
+#define PCIE_MEEP_SBAR45LMT_UPPER_REG             (0x1C)
+#define PCIE_MEEP_SDOORBELL_REG                   (0x20)
+#define PCIE_MEEP_SDOORBELL_MASK_REG              (0x24)
+#define PCIE_MEEP_CBDF_SBDF_REG                   (0x28)
+#define PCIE_MEEP_NTB_CNTL_REG                    (0x2C)
+#define PCIE_MEEP_PCI_CFG_HDR0_REG                (0x1000)
+#define PCIE_MEEP_PCI_CFG_HDR1_REG                (0x1004)
+#define PCIE_MEEP_PCI_CFG_HDR2_REG                (0x1008)
+#define PCIE_MEEP_PCI_CFG_HDR3_REG                (0x100C)
+#define PCIE_MEEP_PCI_CFG_HDR4_REG                (0x1010)
+#define PCIE_MEEP_PCI_CFG_HDR5_REG                (0x1014)
+#define PCIE_MEEP_PCI_CFG_HDR6_REG                (0x1018)
+#define PCIE_MEEP_PCI_CFG_HDR7_REG                (0x101C)
+#define PCIE_MEEP_PCI_CFG_HDR8_REG                (0x1020)
+#define PCIE_MEEP_PCI_CFG_HDR9_REG                (0x1024)
+#define PCIE_MEEP_PCI_CFG_HDR10_REG               (0x1028)
+#define PCIE_MEEP_PCI_CFG_HDR11_REG               (0x102C)
+#define PCIE_MEEP_PCI_CFG_HDR12_REG               (0x1030)
+#define PCIE_MEEP_PCI_CFG_HDR13_REG               (0x1034)
+#define PCIE_MEEP_PCI_CFG_HDR14_REG               (0x1038)
+#define PCIE_MEEP_PCI_CFG_HDR15_REG               (0x103C)
+#define PCIE_MEEP_PCI_PM_CAP0_REG                 (0x1040)
+#define PCIE_MEEP_PCI_PM_CAP1_REG                 (0x1044)
+#define PCIE_MEEP_PCI_MSI_CAP0_REG                (0x1050)
+#define PCIE_MEEP_PCI_MSI_CAP1_REG                (0x1054)
+#define PCIE_MEEP_PCI_MSI_CAP2_REG                (0x1058)
+#define PCIE_MEEP_PCI_MSI_CAP3_REG                (0x105C)
+#define PCIE_MEEP_PCIE_CAP0_REG                   (0x1070)
+#define PCIE_MEEP_PCIE_CAP1_REG                   (0x1074)
+#define PCIE_MEEP_PCIE_CAP2_REG                   (0x1078)
+#define PCIE_MEEP_PCIE_CAP3_REG                   (0x107C)
+#define PCIE_MEEP_PCIE_CAP4_REG                   (0x1080)
+#define PCIE_MEEP_PCIE_CAP5_REG                   (0x1084)
+#define PCIE_MEEP_PCIE_CAP6_REG                   (0x1088)
+#define PCIE_MEEP_PCIE_CAP7_REG                   (0x108C)
+#define PCIE_MEEP_PCIE_CAP8_REG                   (0x1090)
+#define PCIE_MEEP_PCIE_CAP9_REG                   (0x1094)
+#define PCIE_MEEP_PCIE_CAP10_REG                  (0x1098)
+#define PCIE_MEEP_PCIE_CAP11_REG                  (0x109C)
+#define PCIE_MEEP_PCIE_CAP12_REG                  (0x10A0)
+#define PCIE_MEEP_SLOT_CAP_REG                    (0x10C0)
+#define PCIE_MEEP_AER_CAP0_REG                    (0x1100)
+#define PCIE_MEEP_AER_CAP1_REG                    (0x1104)
+#define PCIE_MEEP_AER_CAP2_REG                    (0x1108)
+#define PCIE_MEEP_AER_CAP3_REG                    (0x110C)
+#define PCIE_MEEP_AER_CAP4_REG                    (0x1110)
+#define PCIE_MEEP_AER_CAP5_REG                    (0x1114)
+#define PCIE_MEEP_AER_CAP6_REG                    (0x1118)
+#define PCIE_MEEP_AER_CAP7_REG                    (0x11C)
+#define PCIE_MEEP_AER_CAP8_REG                    (0x120)
+#define PCIE_MEEP_AER_CAP9_REG                    (0x124)
+#define PCIE_MEEP_AER_CAP10_REG                   (0x128)
+#define PCIE_MEEP_AER_CAP11_REG                   (0x112C)
+#define PCIE_MEEP_AER_CAP12_REG                   (0x1130)
+#define PCIE_MEEP_AER_CAP13_REG                   (0x1134)
+#define PCIE_MEEP_VC_CAP0_REG                     (0x1140)
+#define PCIE_MEEP_VC_CAP1_REG                     (0x1144)
+#define PCIE_MEEP_VC_CAP2_REG                     (0x1148)
+#define PCIE_MEEP_VC_CAP3_REG                     (0x114C)
+#define PCIE_MEEP_VC_CAP4_REG                     (0x1150)
+#define PCIE_MEEP_VC_CAP5_REG                     (0x1154)
+#define PCIE_MEEP_VC_CAP6_REG                     (0x1158)
+#define PCIE_MEEP_VC_CAP7_REG                     (0x115C)
+#define PCIE_MEEP_VC_CAP8_REG                     (0x1160)
+#define PCIE_MEEP_VC_CAP9_REG                     (0x1164)
+#define PCIE_MEEP_PORT_LOGIC0_REG                 (0x1700)
+#define PCIE_MEEP_PORT_LOGIC1_REG                 (0x1704)
+#define PCIE_MEEP_PORT_LOGIC2_REG                 (0x1708)
+#define PCIE_MEEP_PORT_LOGIC3_REG                 (0x170C)
+#define PCIE_MEEP_PORT_LOGIC4_REG                 (0x1710)
+#define PCIE_MEEP_PORT_LOGIC5_REG                 (0x1714)
+#define PCIE_MEEP_PORT_LOGIC6_REG                 (0x1718)
+#define PCIE_MEEP_PORT_LOGIC7_REG                 (0x171C)
+#define PCIE_MEEP_PORT_LOGIC8_REG                 (0x1720)
+#define PCIE_MEEP_PORT_LOGIC9_REG                 (0x1724)
+#define PCIE_MEEP_PORT_LOGIC10_REG                (0x1728)
+#define PCIE_MEEP_PORT_LOGIC11_REG                (0x172C)
+#define PCIE_MEEP_PORT_LOGIC12_REG                (0x1730)
+#define PCIE_MEEP_PORT_LOGIC13_REG                (0x1734)
+#define PCIE_MEEP_PORT_LOGIC14_REG                (0x1738)
+#define PCIE_MEEP_PORT_LOGIC15_REG                (0x173C)
+#define PCIE_MEEP_PORT_LOGIC16_REG                (0x1748)
+#define PCIE_MEEP_PORT_LOGIC17_REG                (0x174C)
+#define PCIE_MEEP_PORT_LOGIC18_REG                (0x1750)
+#define PCIE_MEEP_PORT_LOGIC19_REG                (0x17A8)
+#define PCIE_MEEP_PORT_LOGIC20_REG                (0x17AC)
+#define PCIE_MEEP_PORT_LOGIC21_REG                (0x17B0)
+#define PCIE_MEEP_PORT_LOGIC22_REG                (0x180C)
+#define PCIE_MEEP_PORTLOGIC23_REG                 (0x1810)
+#define PCIE_MEEP_PORTLOGIC24_REG                 (0x1814)
+#define PCIE_MEEP_PORTLOGIC25_REG                 (0x1818)
+#define PCIE_MEEP_PORTLOGIC26_REG                 (0x181C)
+#define PCIE_MEEP_PORTLOGIC27_REG                 (0x1820)
+#define PCIE_MEEP_PORTLOGIC28_REG                 (0x1824)
+#define PCIE_MEEP_PORTLOGIC29_REG                 (0x1828)
+#define PCIE_MEEP_PORTLOGIC30_REG                 (0x182C)
+#define PCIE_MEEP_PORTLOGIC31_REG                 (0x1830)
+#define PCIE_MEEP_PORTLOGIC32_REG                 (0x1834)
+#define PCIE_MEEP_PORTLOGIC33_REG                 (0x1838)
+#define PCIE_MEEP_PORTLOGIC34_REG                 (0x183C)
+#define PCIE_MEEP_PORTLOGIC35_REG                 (0x1840)
+#define PCIE_MEEP_PORTLOGIC36_REG                 (0x1844)
+#define PCIE_MEEP_PORTLOGIC37_REG                 (0x1848)
+#define PCIE_MEEP_PORTLOGIC38_REG                 (0x184C)
+#define PCIE_MEEP_PORTLOGIC39_REG                 (0x1850)
+#define PCIE_MEEP_PORTLOGIC40_REG                 (0x1854)
+#define PCIE_MEEP_PORTLOGIC41_REG                 (0x1858)
+#define PCIE_MEEP_PORTLOGIC42_REG                 (0x185C)
+#define PCIE_MEEP_PORTLOGIC43_REG                 (0x1860)
+#define PCIE_MEEP_PORTLOGIC44_REG                 (0x1864)
+#define PCIE_MEEP_PORTLOGIC45_REG                 (0x1868)
+#define PCIE_MEEP_PORTLOGIC46_REG                 (0x186C)
+#define PCIE_MEEP_PORTLOGIC47_REG                 (0x1870)
+#define PCIE_MEEP_PORTLOGIC48_REG                 (0x1874)
+#define PCIE_MEEP_PORTLOGIC49_REG                 (0x1878)
+#define PCIE_MEEP_PORTLOGIC50_REG                 (0x187C)
+#define PCIE_MEEP_PORTLOGIC51_REG                 (0x1880)
+#define PCIE_MEEP_PORTLOGIC52_REG                 (0x1884)
+#define PCIE_MEEP_PORTLOGIC53_REG                 (0x1888)
+#define PCIE_MEEP_PORTLOGIC54_REG                 (0x1900)
+#define PCIE_MEEP_PORTLOGIC55_REG                 (0x1904)
+#define PCIE_MEEP_PORTLOGIC56_REG                 (0x908)
+#define PCIE_MEEP_PORTLOGIC57_REG                 (0x190C)
+#define PCIE_MEEP_PORTLOGIC58_REG                 (0x1910)
+#define PCIE_MEEP_PORTLOGIC59_REG                 (0x1914)
+#define PCIE_MEEP_PORTLOGIC60_REG                 (0x1918)
+#define PCIE_MEEP_PORTLOGIC61_REG                 (0x191C)
+#define PCIE_MEEP_PORTLOGIC62_REG                 (0x197C)
+#define PCIE_MEEP_PORTLOGIC63_REG                 (0x1980)
+#define PCIE_MEEP_PORTLOGIC64_REG                 (0x199C)
+#define PCIE_MEEP_PORTLOGIC65_REG                 (0x19A0)
+#define PCIE_MEEP_PORTLOGIC66_REG                 (0x19BC)
+#define PCIE_MEEP_PORTLOGIC67_REG                 (0x19C4)
+#define PCIE_MEEP_PORTLOGIC68_REG                 (0x19C8)
+#define PCIE_MEEP_PORTLOGIC69_REG                 (0x19CC)
+#define PCIE_MEEP_PORTLOGIC70_REG                 (0x19D0)
+#define PCIE_MEEP_PORTLOGIC71_REG                 (0x19D4)
+#define PCIE_MEEP_PORTLOGIC72_REG                 (0x19D8)
+#define PCIE_MEEP_PORTLOGIC73_REG                 (0x19DC)
+#define PCIE_MEEP_PORTLOGIC74_REG                 (0x19E0)
+#define PCIE_MEEP_PORTLOGIC75_REG                 (0x1A00)
+#define PCIE_MEEP_PORTLOGIC76_REG                 (0x1A10)
+#define PCIE_MEEP_PORTLOGIC77_REG                 (0x1A18)
+#define PCIE_MEEP_PORTLOGIC78_REG                 (0x1A1C)
+#define PCIE_MEEP_PORTLOGIC79_REG                 (0x1A24)
+#define PCIE_MEEP_PORTLOGIC80_REG                 (0x1A28)
+#define PCIE_MEEP_PORTLOGIC81_REG                 (0x1A34)
+#define PCIE_MEEP_PORTLOGIC82_REG                 (0x1A3C)
+#define PCIE_MEEP_PORTLOGIC83_REG                 (0x1A40)
+#define PCIE_MEEP_PORTLOGIC84_REG                 (0x1A44)
+#define PCIE_MEEP_PORTLOGIC85_REG                 (0xA48)
+#define PCIE_MEEP_PORTLOGIC86_REG                 (0xA6C)
+#define PCIE_MEEP_PORTLOGIC87_REG                 (0x1A70)
+#define PCIE_MEEP_PORTLOGIC88_REG                 (0x1A78)
+#define PCIE_MEEP_PORTLOGIC89_REG                 (0x1A7C)
+#define PCIE_MEEP_PORTLOGIC90_REG                 (0x1A80)
+#define PCIE_MEEP_PORTLOGIC91_REG                 (0x1A84)
+#define PCIE_MEEP_PORTLOGIC92_REG                 (0x1A88)
+#define PCIE_MEEP_PORTLOGIC93_REG                 (0x1A8C)
+#define PCIE_MEEP_PORTLOGIC94_REG                 (0x1A90)
+#define PCIE_MEEP_PBAR23XLAT_LOWER_REG            (0x8000)
+#define PCIE_MEEP_PBAR23XLAT_UPPER_REG            (0x8004)
+#define PCIE_MEEP_PBAR45XLAT_LOWER_REG            (0x8008)
+#define PCIE_MEEP_PBAR45XLAT_UPPER_REG            (0x800C)
+#define PCIE_MEEP_PBAR23LMT_LOWER_REG             (0x8010)
+#define PCIE_MEEP_PBAR23LMT_UPPER_REG             (0x8014)
+#define PCIE_MEEP_PBAR45LMT_LOWER_REG             (0x8018)
+#define PCIE_MEEP_PBAR45LMT_UPPER_REG             (0x801C)
+#define PCIE_MEEP_PDOORBELL_REG                   (0x8020)
+#define PCIE_MEEP_PDOORBELL_MASK_REG              (0x8024)
+#define PCIE_MEEP_B2B_BAR01XLAT_LOWER_REG         (0x8028)
+#define PCIE_MEEP_B2B_BAR01XLAT_UPPER_REG         (0x802C)
+#define PCIE_MEEP_B2B_DOORBELL_REG                (0x8030)
+#define PCIE_MEEP_SPAD0_REG                       (0x8038)
+#define PCIE_MEEP_SPAD1_REG                       (0x803C)
+#define PCIE_MEEP_SPAD2_REG                       (0x8040)
+#define PCIE_MEEP_SPAD3_REG                       (0x8044)
+#define PCIE_MEEP_SPAD4_REG                       (0x8048)
+#define PCIE_MEEP_SPAD5_REG                       (0x804C)
+#define PCIE_MEEP_SPAD6_REG                       (0x8050)
+#define PCIE_MEEP_SPAD7_REG                       (0x8054)
+#define PCIE_MEEP_SPAD8_REG                       (0x8058)
+#define PCIE_MEEP_SPAD9_REG                       (0x805C)
+#define PCIE_MEEP_SPAD10_REG                      (0x8060)
+#define PCIE_MEEP_SPAD11_REG                      (0x8064)
+#define PCIE_MEEP_SPAD12_REG                      (0x8068)
+#define PCIE_MEEP_SPAD13_REG                      (0x806C)
+#define PCIE_MEEP_SPAD14_REG                      (0x8070)
+#define PCIE_MEEP_SPAD15_REG                      (0x8074)
+#define PCIE_MEEP_SPAD16_REG                      (0x8078)
+#define PCIE_MEEP_SPAD17_REG                      (0x807C)
+#define PCIE_MEEP_SPAD18_REG                      (0x8080)
+#define PCIE_MEEP_SPAD19_REG                      (0x8084)
+#define PCIE_MEEP_SPAD20_REG                      (0x8088)
+#define PCIE_MEEP_SPAD21_REG                      (0x808C)
+#define PCIE_MEEP_SPAD22_REG                      (0x8090)
+#define PCIE_MEEP_SPAD23_REG                      (0x8094)
+#define PCIE_MEEP_SPAD24_REG                      (0x8098)
+#define PCIE_MEEP_SPAD25_REG                      (0x809C)
+#define PCIE_MEEP_SPAD26_REG                      (0x80A0)
+#define PCIE_MEEP_SPAD27_REG                      (0x80A4)
+#define PCIE_MEEP_SPAD28_REG                      (0x80A8)
+#define PCIE_MEEP_SPAD29_REG                      (0x80AC)
+#define PCIE_MEEP_SPAD30_REG                      (0x80B0)
+#define PCIE_MEEP_SPAD31_REG                      (0x80B4)
+#define PCIE_MEEP_PPD_REG                         (0x8138)
+#define PCIE_MEEP_DEVICE_VENDOR_ID_REG            (0x9000)
+#define PCIE_MEEP_PCISTS_PCICMD_REG               (0x9004)
+#define PCIE_MEEP_CCR_RID_REG                     (0x9008)
+#define PCIE_MEEP_PBAR01_BASE_LOWER_REG           (0x9010)
+#define PCIE_MEEP_PBAR01_BASE_UPPER_REG           (0x9014)
+#define PCIE_MEEP_PBAR23_BASE_LOWER_REG           (0x9018)
+#define PCIE_MEEP_PBAR23_BASE_UPPER_REG           (0x901C)
+#define PCIE_MEEP_PBAR45_BASE_LOWER_REG           (0x9020)
+#define PCIE_MEEP_PBAR45_BASE_UPPER_REG           (0x9024)
+#define PCIE_MEEP_CARDBUSCISPTR_REG               (0x9028)
+#define PCIE_MEEP_SUBSYSTEMID_REG                 (0x902C)
+#define PCIE_MEEP_EXPANSIONROM_BASE_ADDR_REG      (0x9030)
+#define PCIE_MEEP_CAPPTR_REG                      (0x9034)
+#define PCIE_MEEP_INTERRUPT_REG                   (0x903C)
+#define PCIE_MEEP_MSI_CAPABILITY_REGISTER_REG     (0x9050)
+#define PCIE_MEEP_MSI_LOWER32_BITADDRESS_REG      (0x9054)
+#define PCIE_MEEP_MSI_UPPER32_BIT_ADDRESS_REG     (0x9058)
+#define PCIE_MEEP_MSI_DATA_REG                    (0x905C)
+#define PCIE_MEEP_MSI_MASK_REG                    (0x9060)
+#define PCIE_MEEP_MSI_PENDING_REG                 (0x9064)
+#define PCIE_MEEP_PCIE_CAPABILITY_REGISTER_REG    (0x9070)
+#define PCIE_MEEP_DEVICE_CAPABILITIES_REGISTER_REG  (0x9074)
+#define PCIE_MEEP_DEVICE_STATUS_REGISTER_REG      (0x9078)
+#define PCIE_MEEP_LINK_CAPABILITY_REG             (0x907C)
+#define PCIE_MEEP_LINK_CONTROL_STATUS_REG         (0x9080)
+#define PCIE_MEEP_AER_CAP_HEADER_REG              (0x9100)
+#define PCIE_MEEP_UC_ERROR_STATUS_REG             (0x9104)
+#define PCIE_MEEP_UC_ERROR_MASK_REG               (0x9108)
+#define PCIE_MEEP_UC_ERROR_SEVERITY_REG           (0x910C)
+#define PCIE_MEEP_C_ERROR_STATUS_REG              (0x9110)
+#define PCIE_MEEP_C_ERROR_MASK_REG                (0x9114)
+#define PCIE_MEEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG  (0x9118)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_1_REG      (0x911C)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_2_REG      (0x9120)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_3_REG      (0x9124)
+#define PCIE_MEEP_HEADER_LOG_REGISTERS_4_REG      (0x9128)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_1_REG   (0x9130)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_2_REG   (0x9134)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_3_REG   (0x9138)
+#define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_4_REG   (0x913C)
+#define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_LOWER_REG  (0x9700)
+#define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_UPPER_REG  (0x9704)
+#define PCIE_MEEP_NTB_IEP_BAR01_CTRL_REG          (0x9708)
+#define PCIE_MEEP_NTB_IEP_BAR23_CTRL_REG          (0x970C)
+#define PCIE_MEEP_NTB_IEP_BAR45_CTRL_REG          (0x9710)
+#define PCIE_MEEP_MSI_CTRL_ADDRESS_LOWER_REG      (0x9714)
+#define PCIE_MEEP_MSI_CTRL_ADDRESS_UPPER_REG      (0x9718)
+#define PCIE_MEEP_MSI_CTRL_INT_EN_REG             (0x971C)
+#define PCIE_MEEP_MSI_CTRL_INT0_MASK_REG          (0x9720)
+#define PCIE_MEEP_MSI_CTRL_INT_STATUS_REG         (0x9724)
+#define PCIE_MEEP_DBI_RO_WR_EN_REG                (0x9728)
+#define PCIE_MEEP_AXI_ERR_RESPONSE_REG            (0x972C)
+
+
+
+typedef union tagMeepSbar23xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_0            : 12  ;
+        UINT32    sbar23xlat_lower      : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_SBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_1            : 12  ;
+        UINT32    sbar45xlat_lower      : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_SBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar23lmtLower
+{
+
+    struct
+    {
+        UINT32    Reserved_2            : 12  ;
+        UINT32    sbar45limit_lower     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_SBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45lmtLower
+{
+
+    struct
+    {
+        UINT32    Reserved_3            : 12  ;
+        UINT32    sbar45limit_lower     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_SBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepSbar45lmtUpper
+{
+
+    struct
+    {
+        UINT32    Reserved_4            : 12  ;
+        UINT32    sbar45limit_upper     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_SBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMeepCbdfSbdf
+{
+
+    struct
+    {
+        UINT32    sfunc                 : 3   ;
+        UINT32    sdev                  : 5   ;
+        UINT32    sbus                  : 8   ;
+        UINT32    cap_sfunc             : 3   ;
+        UINT32    cap_sdev              : 5   ;
+        UINT32    cap_sbus              : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_CBDF_SBDF_U;
+
+
+
+
+typedef union tagMeepNtbCntl
+{
+
+    struct
+    {
+        UINT32    s_link_disable        : 1   ;
+        UINT32    Reserved_6            : 1   ;
+        UINT32    eep_shadow_en         : 1   ;
+        UINT32    Reserved_5            : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_NTB_CNTL_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr0
+{
+
+    struct
+    {
+        UINT32    vendor_id             : 16  ;
+        UINT32    device_id             : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr1
+{
+
+    struct
+    {
+        UINT32    io_space_enable       : 1   ;
+        UINT32    memory_space_enable   : 1   ;
+        UINT32    bus_master_enable     : 1   ;
+        UINT32    specialcycleenable    : 1   ;
+        UINT32    memory_write_and_invalidate  : 1   ;
+        UINT32    vga_palette_snoop_enable  : 1   ;
+        UINT32    parity_error_response  : 1   ;
+        UINT32    idsel_stepping_waitcycle_control  : 1   ;
+        UINT32    serr_enable           : 1   ;
+        UINT32    fastback_to_backenable  : 1   ;
+        UINT32    interrupt_disable     : 1   ;
+        UINT32    Reserved_10           : 5   ;
+        UINT32    Reserved_9            : 3   ;
+        UINT32    intx_status           : 1   ;
+        UINT32    capabilitieslist      : 1   ;
+        UINT32    pcibus66mhzcapable    : 1   ;
+        UINT32    Reserved_8            : 1   ;
+        UINT32    fastback_to_back      : 1   ;
+        UINT32    masterdataparityerror  : 1   ;
+        UINT32    devsel_timing         : 2   ;
+        UINT32    signaled_target_abort  : 1   ;
+        UINT32    received_target_abort  : 1   ;
+        UINT32    received_master_abort  : 1   ;
+        UINT32    signaled_system_error  : 1   ;
+        UINT32    detected_parity_error  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr2
+{
+
+    struct
+    {
+        UINT32    revision_identification  : 8   ;
+        UINT32    Reserved_11           : 8   ;
+        UINT32    sub_class             : 8   ;
+        UINT32    baseclass             : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR2_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr3
+{
+
+    struct
+    {
+        UINT32    cache_line_size       : 8   ;
+        UINT32    mstr_lat_tmr          : 8   ;
+        UINT32    multi_function_device  : 7   ;
+        UINT32    hdr_type              : 1   ;
+        UINT32    bist                  : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR3_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr4
+{
+
+    struct
+    {
+        UINT32    sbar01_space_inicator  : 1   ;
+        UINT32    sbar01_type           : 2   ;
+        UINT32    sbar01_prefetchable   : 1   ;
+        UINT32    sbar01_lower          : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR4_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr6
+{
+
+    struct
+    {
+        UINT32    sbar23_space_inicator  : 1   ;
+        UINT32    sbar23_type           : 2   ;
+        UINT32    sbar23_prefetchable   : 1   ;
+        UINT32    Reserved_12           : 8   ;
+        UINT32    sbar23_lower          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR6_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr8
+{
+
+    struct
+    {
+        UINT32    sbar45_space_inicator  : 1   ;
+        UINT32    sbar45_type           : 2   ;
+        UINT32    sbar45_prefetchable   : 1   ;
+        UINT32    Reserved_13           : 8   ;
+        UINT32    sbar45_lower          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR8_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr11
+{
+
+    struct
+    {
+        UINT32    subsystem_vendor_id   : 16  ;
+        UINT32    subsystemid           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr13
+{
+
+    struct
+    {
+        UINT32    cap_ptr               : 8   ;
+        UINT32    Reserved_14           : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagMeepPciCfgHdr15
+{
+
+    struct
+    {
+        UINT32    int_line              : 8   ;
+        UINT32    int_pin               : 8   ;
+        UINT32    Min_Grant             : 8   ;
+        UINT32    Max_Latency           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagMeepPciMsiCap0
+{
+
+    struct
+    {
+        UINT32    msi_cap_id            : 8   ;
+        UINT32    next_capability_pointer  : 8   ;
+        UINT32    msi_enabled           : 1   ;
+        UINT32    multiple_message_capable  : 3   ;
+        UINT32    multiple_message_enabled  : 3   ;
+        UINT32    msi_64_en             : 1   ;
+        UINT32    pvm                   : 1   ;
+        UINT32    Reserved_18           : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagMeepPciMsiCap1
+{
+
+    struct
+    {
+        UINT32    Reserved_20           : 2   ;
+        UINT32    msi_addr_low          : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagMeepPciMsiCap3
+{
+
+    struct
+    {
+        UINT32    msi_data              : 16  ;
+        UINT32    Reserved_21           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagMeepPcieCap0
+{
+
+    struct
+    {
+        UINT32    pcie_cap_id           : 8   ;
+        UINT32    pcie_next_ptr         : 8   ;
+        UINT32    pcie_capability_version  : 4   ;
+        UINT32    device_port_type      : 4   ;
+        UINT32    slot_implemented      : 1   ;
+        UINT32    interrupt_message_number  : 5   ;
+        UINT32    Reserved_22           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagMeepPcieCap1
+{
+
+    struct
+    {
+        UINT32    max_payload_size_supported  : 3   ;
+        UINT32    phantom_function_supported  : 2   ;
+        UINT32    extended_tagfield_supported  : 1   ;
+        UINT32    endpoint_l0sacceptable_latency  : 3   ;
+        UINT32    endpoint_l1acceptable_latency  : 3   ;
+        UINT32    undefined             : 3   ;
+        UINT32    Reserved_24           : 3   ;
+        UINT32    captured_slot_power_limit_value  : 8   ;
+        UINT32    captured_slot_power_limit_scale  : 2   ;
+        UINT32    function_level_reset  : 1   ;
+        UINT32    dev_cap               : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagMeepPcieCap2
+{
+
+    struct
+    {
+        UINT32    correctable_error_reporting_enable  : 1   ;
+        UINT32    non_fatal_error_reporting_enable  : 1   ;
+        UINT32    fatal_error_reporting_enable  : 1   ;
+        UINT32    urenable              : 1   ;
+        UINT32    enable_relaxed_ordering  : 1   ;
+        UINT32    max_payload_size      : 3   ;
+        UINT32    extended_tagfieldenable  : 1   ;
+        UINT32    phantom_function_enable  : 1   ;
+        UINT32    auxpowerpmenable      : 1   ;
+        UINT32    enablenosnoop         : 1   ;
+        UINT32    max_read_request_size  : 3   ;
+        UINT32    Reserved_26           : 1   ;
+        UINT32    correctableerrordetected  : 1   ;
+        UINT32    non_fatalerrordetected  : 1   ;
+        UINT32    fatalerrordetected    : 1   ;
+        UINT32    unsupportedrequestdetected  : 1   ;
+        UINT32    auxpowerdetected      : 1   ;
+        UINT32    transactionpending    : 1   ;
+        UINT32    Reserved_25           : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagMeepPcieCap3
+{
+
+    struct
+    {
+        UINT32    max_link_speed        : 4   ;
+        UINT32    max_link_width        : 6   ;
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    l0s_exitlatency       : 3   ;
+        UINT32    l1_exit_latency       : 3   ;
+        UINT32    clock_power_management  : 1   ;
+        UINT32    surprise_down_error_report_cap  : 1   ;
+        UINT32    data_link_layer_active_report_cap  : 1   ;
+        UINT32    link_bandwidth_noti_cap  : 1   ;
+        UINT32    aspm_option_compliance  : 1   ;
+        UINT32    Reserved_27           : 1   ;
+        UINT32    port_number           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagMeepPcieCap4
+{
+
+    struct
+    {
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    Reserved_30           : 1   ;
+        UINT32    rcb                   : 1   ;
+        UINT32    link_disable          : 1   ;
+        UINT32    retrain_link          : 1   ;
+        UINT32    common_clock_config   : 1   ;
+        UINT32    extended_sync         : 1   ;
+        UINT32    enable_clock_pwr_management  : 1   ;
+        UINT32    hw_auto_width_disable  : 1   ;
+        UINT32    link_bandwidth_management_int_en  : 1   ;
+        UINT32    link_auto_bandwidth_int_en  : 1   ;
+        UINT32    Reserved_29           : 4   ;
+        UINT32    current_link_speed    : 4   ;
+        UINT32    negotiated_link_width  : 6   ;
+        UINT32    Reserved_28           : 1   ;
+        UINT32    link_training         : 1   ;
+        UINT32    slot_clock_configration  : 1   ;
+        UINT32    data_link_layer_active  : 1   ;
+        UINT32    link_bandwidth_management_status  : 1   ;
+        UINT32    link_auto_bandwidth_status  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagMeepPcieCap5
+{
+
+    struct
+    {
+        UINT32    attentionbuttonpresent  : 1   ;
+        UINT32    powercontrollerpresent  : 1   ;
+        UINT32    mrlsensorpresent      : 1   ;
+        UINT32    attentionindicatorpresent  : 1   ;
+        UINT32    powerindicatorpresent  : 1   ;
+        UINT32    hot_plugsurprise      : 1   ;
+        UINT32    hot_plugcapable       : 1   ;
+        UINT32    slotpowerlimitvalue   : 8   ;
+        UINT32    slotpowerlimitscale   : 2   ;
+        UINT32    electromechanicalinterlockpresen  : 1   ;
+        UINT32    no_cmd_complete_support  : 1   ;
+        UINT32    phy_slot_number       : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagMeepPcieCap6
+{
+
+    struct
+    {
+        UINT32    attentionbuttonpressedenable  : 1   ;
+        UINT32    powerfaultdetectedenable  : 1   ;
+        UINT32    mrlsensorchangedenable  : 1   ;
+        UINT32    presencedetectchangedenable  : 1   ;
+        UINT32    commandcompletedinterruptenable  : 1   ;
+        UINT32    hot_pluginterruptenable  : 1   ;
+        UINT32    attentionindicatorcontrol  : 2   ;
+        UINT32    powerindicatorcontrol  : 2   ;
+        UINT32    powercontrollercontrol  : 1   ;
+        UINT32    electromechanicalinterlockcontrol  : 1   ;
+        UINT32    datalinklayerstatechangedenable  : 1   ;
+        UINT32    Reserved_31           : 3   ;
+        UINT32    attentionbuttonpressed  : 1   ;
+        UINT32    powerfaultdetected    : 1   ;
+        UINT32    mrlsensorchanged      : 1   ;
+        UINT32    presencedetectchanged  : 1   ;
+        UINT32    commandcompleted      : 1   ;
+        UINT32    mrlsensorstate        : 1   ;
+        UINT32    presencedetectstate   : 1   ;
+        UINT32    electromechanicalinterlockstatus  : 1   ;
+        UINT32    datalinklayerstatechanged  : 1   ;
+        UINT32    slot_ctrl_status      : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagMeepPcieCap7
+{
+
+    struct
+    {
+        UINT32    systemerroroncorrectableerrorenable  : 1   ;
+        UINT32    systemerroronnon_fatalerrorenable  : 1   ;
+        UINT32    systemerroronfatalerrorenable  : 1   ;
+        UINT32    pmeinterruptenable    : 1   ;
+        UINT32    crssoftwarevisibilityenable  : 1   ;
+        UINT32    Reserved_32           : 11  ;
+        UINT32    crssoftwarevisibility  : 1   ;
+        UINT32    root_cap              : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagMeepPcieCap8
+{
+
+    struct
+    {
+        UINT32    pmerequesterid        : 16  ;
+        UINT32    pmestatus             : 1   ;
+        UINT32    pmepending            : 1   ;
+        UINT32    root_status           : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagMeepPcieCap9
+{
+
+    struct
+    {
+        UINT32    completiontimeoutrangessupported  : 4   ;
+        UINT32    completiontimeoutdisablesupported  : 1   ;
+        UINT32    ariforwardingsupported  : 1   ;
+        UINT32    atomicoproutingsupported  : 1   ;
+        UINT32    _2_bitatomicopcompletersupported  : 1   ;
+        UINT32    _4_bitatomicopcompletersupported  : 1   ;
+        UINT32    _28_bitcascompletersupported  : 1   ;
+        UINT32    noro_enabledpr_prpassing  : 1   ;
+        UINT32    Reserved_33           : 1   ;
+        UINT32    tphcompletersupported  : 2   ;
+        UINT32    dev_cap2              : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagMeepPcieCap10
+{
+
+    struct
+    {
+        UINT32    completiontimeoutvalue  : 4   ;
+        UINT32    completiontimeoutdisable  : 1   ;
+        UINT32    ariforwardingsupported  : 1   ;
+        UINT32    atomicoprequesterenable  : 1   ;
+        UINT32    atomicopegressblocking  : 1   ;
+        UINT32    idorequestenable      : 1   ;
+        UINT32    idocompletionenable   : 1   ;
+        UINT32    dev_ctrl2             : 22  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagMeepPcieCap11
+{
+
+    struct
+    {
+        UINT32    Reserved_35           : 1   ;
+        UINT32    gen1_suport           : 1   ;
+        UINT32    gen2_suport           : 1   ;
+        UINT32    gen3_suport           : 1   ;
+        UINT32    Reserved_34           : 4   ;
+        UINT32    crosslink_supported   : 1   ;
+        UINT32    link_cap2             : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagMeepPcieCap12
+{
+
+    struct
+    {
+        UINT32    targetlinkspeed       : 4   ;
+        UINT32    entercompliance       : 1   ;
+        UINT32    hardwareautonomousspeeddisa  : 1   ;
+        UINT32    selectablede_empha    : 1   ;
+        UINT32    transmitmargin        : 3   ;
+        UINT32    _entermodifiedcompliance  : 1   ;
+        UINT32    compliancesos         : 1   ;
+        UINT32    de_emphasislevel      : 4   ;
+        UINT32    currentde_emphasislevel  : 1   ;
+        UINT32    equalizationcomplete  : 1   ;
+        UINT32    equalizationphase1successful  : 1   ;
+        UINT32    equalizationphase2successful  : 1   ;
+        UINT32    equalizationphase3successful  : 1   ;
+        UINT32    linkequalizationrequest  : 1   ;
+        UINT32    link_ctrl2_status2    : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagMeepSlotCap
+{
+
+    struct
+    {
+        UINT32    slotnumberingcapabilitiesid  : 8   ;
+        UINT32    nextcapabilitypointer  : 8   ;
+        UINT32    add_incardslotsprovided  : 5   ;
+        UINT32    firstinchassis        : 1   ;
+        UINT32    Reserved_36           : 2   ;
+        UINT32    slot_cap              : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagMeepAerCap0
+{
+
+    struct
+    {
+        UINT32    pciexpressextendedcapabilityid  : 16  ;
+        UINT32    capabilityversion     : 4   ;
+        UINT32    aer_cap_hdr           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP0_U;
+
+
+
+
+typedef union tagMeepAerCap1
+{
+
+    struct
+    {
+        UINT32    Reserved_42           : 1   ;
+        UINT32    Reserved_41           : 3   ;
+        UINT32    datalinkprotocolerrorsta  : 1   ;
+        UINT32    surprisedownerrorstatus  : 1   ;
+        UINT32    Reserved_40           : 6   ;
+        UINT32    poisonedtlpstatu      : 1   ;
+        UINT32    flowcontrolprotocolerrorst  : 1   ;
+        UINT32    completiontimeouts    : 1   ;
+        UINT32    completerabortstatus  : 1   ;
+        UINT32    receiveroverflowstatus  : 1   ;
+        UINT32    malformedtlpstatus    : 1   ;
+        UINT32    ecrcerrorstatus       : 1   ;
+        UINT32    ecrcerrorstat         : 1   ;
+        UINT32    unsupportedrequesterrorstatus  : 1   ;
+        UINT32    Reserved_39           : 3   ;
+        UINT32    atomicopegressblockedstatus  : 1   ;
+        UINT32    uncorr_err_status     : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP1_U;
+
+
+
+
+typedef union tagMeepAerCap2
+{
+
+    struct
+    {
+        UINT32    Reserved_46           : 1   ;
+        UINT32    Reserved_45           : 3   ;
+        UINT32    datalinkprotocolerrormask  : 1   ;
+        UINT32    surprisedownerrormask  : 1   ;
+        UINT32    Reserved_44           : 6   ;
+        UINT32    poisonedtlpmask       : 1   ;
+        UINT32    flowcontrolprotocolerrormask  : 1   ;
+        UINT32    completiontimeoutmask  : 1   ;
+        UINT32    completerabortmask    : 1   ;
+        UINT32    unexpectedcompletionmask  : 1   ;
+        UINT32    receiveroverflowmask  : 1   ;
+        UINT32    malformedtlpmask      : 1   ;
+        UINT32    ecrcerrormask         : 1   ;
+        UINT32    unsupportedrequesterrormask  : 1   ;
+        UINT32    Reserved_43           : 3   ;
+        UINT32    atomicopegressblockedmask  : 1   ;
+        UINT32    uncorr_err_mask       : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP2_U;
+
+
+
+
+typedef union tagMeepAerCap3
+{
+
+    struct
+    {
+        UINT32    Reserved_50           : 1   ;
+        UINT32    Reserved_49           : 3   ;
+        UINT32    datalinkprotocolerrorsever  : 1   ;
+        UINT32    surprisedownerrorseverity  : 1   ;
+        UINT32    Reserved_48           : 6   ;
+        UINT32    poisonedtlpseverity   : 1   ;
+        UINT32    flowcontrolprotocolerrorseveri  : 1   ;
+        UINT32    completiontimeoutseverity  : 1   ;
+        UINT32    completerabortseverity  : 1   ;
+        UINT32    unexpectedcompletionseverity  : 1   ;
+        UINT32    receiveroverflowseverity  : 1   ;
+        UINT32    malformedtlpseverity  : 1   ;
+        UINT32    ecrcerrorseverity     : 1   ;
+        UINT32    unsupportedrequesterrorseverity  : 1   ;
+        UINT32    Reserved_47           : 3   ;
+        UINT32    atomicopegressblockedseverity  : 1   ;
+        UINT32    uncorr_err_ser        : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP3_U;
+
+
+
+
+typedef union tagMeepAerCap4
+{
+
+    struct
+    {
+        UINT32    receivererrorstatus   : 1   ;
+        UINT32    Reserved_52           : 5   ;
+        UINT32    badtlpstatus          : 1   ;
+        UINT32    baddllpstatus         : 1   ;
+        UINT32    replay_numrolloverstatus  : 1   ;
+        UINT32    Reserved_51           : 3   ;
+        UINT32    replytimertimeoutstatus  : 1   ;
+        UINT32    advisorynon_fatalerrorstatus  : 1   ;
+        UINT32    corr_err_status       : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP4_U;
+
+
+
+
+typedef union tagMeepAerCap5
+{
+
+    struct
+    {
+        UINT32    receivererrormask     : 1   ;
+        UINT32    Reserved_54           : 5   ;
+        UINT32    badtlpmask            : 1   ;
+        UINT32    baddllpmask           : 1   ;
+        UINT32    replay_numrollovermask  : 1   ;
+        UINT32    Reserved_53           : 3   ;
+        UINT32    replytimertimeoutmask  : 1   ;
+        UINT32    advisorynon_fatalerrormask  : 1   ;
+        UINT32    corr_err_mask         : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP5_U;
+
+
+
+
+typedef union tagMeepAerCap6
+{
+
+    struct
+    {
+        UINT32    firsterrorpointer     : 5   ;
+        UINT32    ecrcgenerationcapability  : 1   ;
+        UINT32    ecrcgenerationenable  : 1   ;
+        UINT32    ecrccheckcapable      : 1   ;
+        UINT32    ecrccheckenable       : 1   ;
+        UINT32    adv_cap_ctrl          : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP6_U;
+
+
+
+
+typedef union tagMeepAerCap11
+{
+
+    struct
+    {
+        UINT32    correctableerrorreportingenable  : 1   ;
+        UINT32    non_fatalerrorreportingenable  : 1   ;
+        UINT32    fatalerrorreportingenable  : 1   ;
+        UINT32    root_err_cmd          : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP11_U;
+
+
+
+
+typedef union tagMeepAerCap12
+{
+
+    struct
+    {
+        UINT32    err_correceived       : 1   ;
+        UINT32    multipleerr_correceived  : 1   ;
+        UINT32    err_fatal_nonfatalreceived  : 1   ;
+        UINT32    multipleerr_fatal_nonfatalreceived  : 1   ;
+        UINT32    firstuncorrectablefatal  : 1   ;
+        UINT32    non_fatalerrormessagesreceived  : 1   ;
+        UINT32    fatalerrormessagesreceived  : 1   ;
+        UINT32    Reserved_57           : 20  ;
+        UINT32    root_err_status       : 5   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP12_U;
+
+
+
+
+typedef union tagMeepAerCap13
+{
+
+    struct
+    {
+        UINT32    err_corsourceidentification  : 16  ;
+        UINT32    err_src_id            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_CAP13_U;
+
+
+
+
+typedef union tagMeepVcCap0
+{
+
+    struct
+    {
+        UINT32    pciexpressextendedcapabilityid  : 16  ;
+        UINT32    capabilityversion     : 4   ;
+        UINT32    vc_cap_hdr            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP0_U;
+
+
+
+
+typedef union tagMeepVcCap1
+{
+
+    struct
+    {
+        UINT32    extendedvccount       : 3   ;
+        UINT32    Reserved_60           : 1   ;
+        UINT32    lowpriorityextendedvccount  : 3   ;
+        UINT32    Reserved_59           : 1   ;
+        UINT32    referenceclock        : 2   ;
+        UINT32    portarbitrationtableentrysize  : 2   ;
+        UINT32    vc_cap1               : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP1_U;
+
+
+
+
+typedef union tagMeepVcCap2
+{
+
+    struct
+    {
+        UINT32    vcarbitrationcapability  : 8   ;
+        UINT32    Reserved_61           : 16  ;
+        UINT32    vc_cap2               : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP2_U;
+
+
+
+
+typedef union tagMeepVcCap3
+{
+
+    struct
+    {
+        UINT32    loadvcarbitrationtable  : 1   ;
+        UINT32    vcarbitrationselect   : 3   ;
+        UINT32    Reserved_63           : 12  ;
+        UINT32    arbitrationtablestatus  : 1   ;
+        UINT32    Reserved_62           : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP3_U;
+
+
+
+
+typedef union tagMeepVcCap4
+{
+
+    struct
+    {
+        UINT32    portarbitrationcapability  : 8   ;
+        UINT32    Reserved_66           : 6   ;
+        UINT32    Reserved_65           : 1   ;
+        UINT32    rejectsnooptransactions  : 1   ;
+        UINT32    maximumtimeslots      : 7   ;
+        UINT32    Reserved_64           : 1   ;
+        UINT32    vc_res_cap            : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP4_U;
+
+
+
+
+typedef union tagMeepVcCap5
+{
+
+    struct
+    {
+        UINT32    tc_vcmap              : 8   ;
+        UINT32    Reserved_69           : 8   ;
+        UINT32    loadportarbitrationtable  : 1   ;
+        UINT32    portarbitrationselec  : 3   ;
+        UINT32    Reserved_68           : 4   ;
+        UINT32    vcid                  : 3   ;
+        UINT32    Reserved_67           : 4   ;
+        UINT32    vc_res_ctrl           : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP5_U;
+
+
+
+
+typedef union tagMeepVcCap6
+{
+
+    struct
+    {
+        UINT32    Reserved_70           : 16  ;
+        UINT32    portarbitrationtablestatus  : 1   ;
+        UINT32    vcnegotiationpending  : 1   ;
+        UINT32    vc_res_status         : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP6_U;
+
+
+
+
+typedef union tagMeepVcCap7
+{
+
+    struct
+    {
+        UINT32    portarbitrationcapability  : 8   ;
+        UINT32    Reserved_73           : 6   ;
+        UINT32    Reserved_72           : 1   ;
+        UINT32    rejectsnooptransactions  : 1   ;
+        UINT32    maximumtimeslots      : 7   ;
+        UINT32    Reserved_71           : 1   ;
+        UINT32    vc_res_cap0           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP7_U;
+
+
+
+
+typedef union tagMeepVcCap8
+{
+
+    struct
+    {
+        UINT32    tc_vcmap              : 8   ;
+        UINT32    Reserved_76           : 8   ;
+        UINT32    loadportarbitrationtable  : 1   ;
+        UINT32    portarbitrationselect  : 3   ;
+        UINT32    Reserved_75           : 4   ;
+        UINT32    vcid                  : 3   ;
+        UINT32    Reserved_74           : 4   ;
+        UINT32    vc_res_ctrl0          : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP8_U;
+
+
+
+
+typedef union tagMeepVcCap9
+{
+
+    struct
+    {
+        UINT32    Reserved_77           : 16  ;
+        UINT32    arbitrationtablestatus  : 1   ;
+        UINT32    vcnegotiationpending  : 1   ;
+        UINT32    vc_res_status0        : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_VC_CAP9_U;
+
+
+
+
+typedef union tagMeepPortLogic0
+{
+
+    struct
+    {
+        UINT32    ack_lat_timer         : 16  ;
+        UINT32    replay_timer          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagMeepPortLogic2
+{
+
+    struct
+    {
+        UINT32    linknumber            : 8   ;
+        UINT32    Reserved_80           : 7   ;
+        UINT32    forcelink             : 1   ;
+        UINT32    linkstate             : 6   ;
+        UINT32    Reserved_79           : 2   ;
+        UINT32    port_force_link       : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagMeepPortLogic3
+{
+
+    struct
+    {
+        UINT32    ackfrequency          : 8   ;
+        UINT32    n_fts                 : 8   ;
+        UINT32    commonclockn_fts      : 8   ;
+        UINT32    l0sentrancelatency    : 3   ;
+        UINT32    l1entrancelatency     : 3   ;
+        UINT32    enteraspml1withoutreceiveinl0s  : 1   ;
+        UINT32    ack_aspm              : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagMeepPortLogic4
+{
+
+    struct
+    {
+        UINT32    vendorspecificdllprequest  : 1   ;
+        UINT32    scrambledisable       : 1   ;
+        UINT32    loopbackenable        : 1   ;
+        UINT32    resetassert           : 1   ;
+        UINT32    Reserved_83           : 1   ;
+        UINT32    dlllinkenable         : 1   ;
+        UINT32    Reserved_82           : 1   ;
+        UINT32    fastlinkmode          : 1   ;
+        UINT32    Reserved_81           : 8   ;
+        UINT32    linkmodeenable        : 6   ;
+        UINT32    crosslinkenable       : 1   ;
+        UINT32    crosslinkactive       : 1   ;
+        UINT32    port_link_ctrl        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagMeepPortLogic5
+{
+
+    struct
+    {
+        UINT32    insertlaneskewfortransmit  : 24  ;
+        UINT32    flowcontroldisable    : 1   ;
+        UINT32    ack_nakdisable        : 1   ;
+        UINT32    Reserved_84           : 5   ;
+        UINT32    lane_skew             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagMeepPortLogic6
+{
+
+    struct
+    {
+        UINT32    numberoftssymbols     : 4   ;
+        UINT32    Reserved_86           : 4   ;
+        UINT32    numberofskpsymbols    : 3   ;
+        UINT32    Reserved_85           : 3   ;
+        UINT32    timermodifierforreplaytimer  : 5   ;
+        UINT32    timermodifierforack_naklatencytimer  : 5   ;
+        UINT32    timermodifierforflowcontrolwatchdogtimer  : 5   ;
+        UINT32    sym_num               : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagMeepPortLogic7
+{
+
+    struct
+    {
+        UINT32    vc0posteddataqueuedepth  : 11  ;
+        UINT32    Reserved_87           : 4   ;
+        UINT32    sym_timer             : 1   ;
+        UINT32    maskfunctionmismatchfilteringfo  : 1   ;
+        UINT32    maskpoisonedtlpfiltering  : 1   ;
+        UINT32    maskbarmatchfiltering  : 1   ;
+        UINT32    masktype1configurationrequestfiltering  : 1   ;
+        UINT32    masklockedrequestfiltering  : 1   ;
+        UINT32    masktagerrorrulesforreceivedcompletions  : 1   ;
+        UINT32    maskrequesteridmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    maskfunctionmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    mask_traffic_classmis_match_error_forreceived_completions  : 1   ;
+        UINT32    mask_attributesmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    mask_length_mismatch_error_forreceive_dcompletions  : 1   ;
+        UINT32    maske_crcerror_filtering  : 1   ;
+        UINT32    maske_crcerror_filtering_forcompletions  : 1   ;
+        UINT32    message_control       : 1   ;
+        UINT32    maskfilteringofreceived  : 1   ;
+        UINT32    flt_mask1             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagMeepPortLogic8
+{
+
+    struct
+    {
+        UINT32    cx_flt_mask_venmsg0_drop  : 1   ;
+        UINT32    cx_flt_mask_venmsg1_drop  : 1   ;
+        UINT32    cx_flt_mask_dabort_4ucpl  : 1   ;
+        UINT32    cx_flt_mask_handle_flush  : 1   ;
+        UINT32    flt_mask2             : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagMeepPortLogic9
+{
+
+    struct
+    {
+        UINT32    amba_multi_outbound_decomp_np  : 1   ;
+        UINT32    amba_obnp_ctrl        : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagMeepPortLogic12
+{
+
+    struct
+    {
+        UINT32    transmitposteddatafccredits  : 12  ;
+        UINT32    transmitpostedheaderfccredits  : 8   ;
+        UINT32    tx_pfc_status         : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagMeepPortLogic13
+{
+
+    struct
+    {
+        UINT32    transmitnon_posteddatafccredits  : 12  ;
+        UINT32    transmitnon_postedheaderfccredits  : 8   ;
+        UINT32    tx_npfc_status        : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagMeepPortLogic14
+{
+
+    struct
+    {
+        UINT32    transmitcompletiondatafccredits  : 12  ;
+        UINT32    transmitcompletionheaderfccredits  : 8   ;
+        UINT32    tx_cplfc_status       : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagMeepPortLogic15
+{
+
+    struct
+    {
+        UINT32    rx_tlp_fc_credit_not_retured  : 1   ;
+        UINT32    tx_retry_buf_not_empty  : 1   ;
+        UINT32    rx_queue_not_empty    : 1   ;
+        UINT32    Reserved_89           : 13  ;
+        UINT32    fc_latency_timer_override_value  : 13  ;
+        UINT32    Reserved_88           : 2   ;
+        UINT32    fc_latency_timer_override_en  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagMeepPortLogic16
+{
+
+    struct
+    {
+        UINT32    vc0posteddatacredits  : 12  ;
+        UINT32    vc0postedheadercredits  : 8   ;
+        UINT32    Reserved_91           : 1   ;
+        UINT32    vc0_postedtlpqueuemode  : 1   ;
+        UINT32    vc0postedtlpqueuemode  : 1   ;
+        UINT32    vc0postedtlpqueuemo   : 1   ;
+        UINT32    Reserved_90           : 6   ;
+        UINT32    tlptypeorderingforvc0  : 1   ;
+        UINT32    rx_pque_ctrl          : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagMeepPortLogic17
+{
+
+    struct
+    {
+        UINT32    vc0non_posteddatarcredits  : 12  ;
+        UINT32    vc0non_postedheadercredits  : 8   ;
+        UINT32    Reserved_93           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagMeepPortLogic18
+{
+
+    struct
+    {
+        UINT32    vco_comp_data_credits  : 12  ;
+        UINT32    vc0_cpl_header_credt  : 8   ;
+        UINT32    Reserved_94           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagMeepPortLogic19
+{
+
+    struct
+    {
+        UINT32    vco_posted_data_que_path  : 14  ;
+        UINT32    Reserved_95           : 2   ;
+        UINT32    vco_posted_head_queue_depth  : 10  ;
+        UINT32    vc_pbuf_ctrl          : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagMeepPortLogic20
+{
+
+    struct
+    {
+        UINT32    vco_np_data_que_depth  : 14  ;
+        UINT32    Reserved_97           : 2   ;
+        UINT32    vco_np_header_que_depth  : 10  ;
+        UINT32    vc_npbuf_ctrl         : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagMeepPortLogic21
+{
+
+    struct
+    {
+        UINT32    vco_comp_data_queue_depth  : 14  ;
+        UINT32    Reserved_99           : 2   ;
+        UINT32    vco_posted_head_queue_depth  : 10  ;
+        UINT32    Reserved_98           : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagMeepPortLogic22
+{
+
+    struct
+    {
+        UINT32    n_fts                 : 8   ;
+        UINT32    pre_determ_num_of_lane  : 9   ;
+        UINT32    det_sp_change         : 1   ;
+        UINT32    config_phy_tx_sw      : 1   ;
+        UINT32    config_tx_comp_rcv_bit  : 1   ;
+        UINT32    set_emp_level         : 1   ;
+        UINT32    Reserved_100          : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagMeepPortlogic25
+{
+
+    struct
+    {
+        UINT32    remote_rd_req_size    : 3   ;
+        UINT32    Reserved_103          : 5   ;
+        UINT32    remote_max_brd_tag    : 8   ;
+        UINT32    Reserved_102          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagMeepPortlogic26
+{
+
+    struct
+    {
+        UINT32    resize_master_resp_compser  : 1   ;
+        UINT32    axi_ctrl1             : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagMeepPortlogic55
+{
+
+    struct
+    {
+        UINT32    iatu1_type            : 5   ;
+        UINT32    iatu1_tc              : 3   ;
+        UINT32    iatu1_td              : 1   ;
+        UINT32    iatu1_attr            : 2   ;
+        UINT32    Reserved_107          : 5   ;
+        UINT32    iatu1_at              : 2   ;
+        UINT32    Reserved_106          : 2   ;
+        UINT32    iatu1_id              : 3   ;
+        UINT32    Reserved_105          : 9   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagMeepPortlogic56
+{
+
+    struct
+    {
+        UINT32    iatu2_type            : 8   ;
+        UINT32    iatu2_bar_num         : 3   ;
+        UINT32    Reserved_111          : 3   ;
+        UINT32    iatu2_tc_match_en     : 1   ;
+        UINT32    iatu2_td_match_en     : 1   ;
+        UINT32    iatu2_attr_match_en   : 1   ;
+        UINT32    Reserved_110          : 1   ;
+        UINT32    iatu2_at_match_en     : 1   ;
+        UINT32    iatu2_func_num_match_en  : 1   ;
+        UINT32    iatu2_virtual_func_num_match_en  : 1   ;
+        UINT32    message_code_match_en  : 1   ;
+        UINT32    Reserved_109          : 2   ;
+        UINT32    iatu2_response_code   : 2   ;
+        UINT32    Reserved_108          : 1   ;
+        UINT32    iatu2_fuzzy_type_match_mode  : 1   ;
+        UINT32    iatu2_cfg_shift_mode  : 1   ;
+        UINT32    iatu2_ivert_mode      : 1   ;
+        UINT32    iatu2_match_mode      : 1   ;
+        UINT32    iatu2_region_en       : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagMeepPortlogic57
+{
+
+    struct
+    {
+        UINT32    iatu_start_low        : 12  ;
+        UINT32    iatu_start_high       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagMeepPortlogic59
+{
+
+    struct
+    {
+        UINT32    iatu_limit_low        : 12  ;
+        UINT32    iatu_limit_high       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagMeepPortlogic60
+{
+
+    struct
+    {
+        UINT32    xlated_addr_high      : 12  ;
+        UINT32    xlated_addr_low       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagMeepPortlogic62
+{
+
+    struct
+    {
+        UINT32    dma_wr_eng_en         : 1   ;
+        UINT32    dma_wr_ena            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagMeepPortlogic63
+{
+
+    struct
+    {
+        UINT32    wr_doorbell_num       : 3   ;
+        UINT32    Reserved_115          : 28  ;
+        UINT32    dma_wr_dbell_stop     : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagMeepPortlogic64
+{
+
+    struct
+    {
+        UINT32    dma_read_eng_en       : 1   ;
+        UINT32    dma_rd_ena            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagMeepPortlogic65
+{
+
+    struct
+    {
+        UINT32    rd_doorbell_num       : 3   ;
+        UINT32    Reserved_117          : 28  ;
+        UINT32    dma_rd_dbell_stop     : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagMeepPortlogic66
+{
+
+    struct
+    {
+        UINT32    done_int_status       : 1   ;
+        UINT32    Reserved_119          : 15  ;
+        UINT32    abort_int_status      : 1   ;
+        UINT32    Reserved_118          : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagMeepPortlogic67
+{
+
+    struct
+    {
+        UINT32    done_int_mask         : 1   ;
+        UINT32    Reserved_122          : 15  ;
+        UINT32    abort_int_mask        : 1   ;
+        UINT32    Reserved_121          : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagMeepPortlogic68
+{
+
+    struct
+    {
+        UINT32    done_int_clr          : 1   ;
+        UINT32    Reserved_125          : 15  ;
+        UINT32    abort_int_clr         : 1   ;
+        UINT32    Reserved_124          : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagMeepPortlogic69
+{
+
+    struct
+    {
+        UINT32    app_rd_err_det        : 1   ;
+        UINT32    Reserved_127          : 15  ;
+        UINT32    ll_element_fetch_err_det  : 1   ;
+        UINT32    Reserved_126          : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagMeepPortlogic74
+{
+
+    struct
+    {
+        UINT32    dma_wr_c0_imwr_data   : 16  ;
+        UINT32    dma_wr_c1_imwr_data   : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagMeepPortlogic75
+{
+
+    struct
+    {
+        UINT32    wr_ch_ll_remote_abort_int_en  : 1   ;
+        UINT32    Reserved_129          : 15  ;
+        UINT32    wr_ch_ll_local_abort_int_en  : 1   ;
+        UINT32    Reserved_128          : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagMeepPortlogic76
+{
+
+    struct
+    {
+        UINT32    done_int_status       : 1   ;
+        UINT32    Reserved_132          : 15  ;
+        UINT32    abort_int_status      : 1   ;
+        UINT32    Reserved_131          : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagMeepPortlogic77
+{
+
+    struct
+    {
+        UINT32    done_int_mask         : 1   ;
+        UINT32    Reserved_134          : 15  ;
+        UINT32    abort_int_mask        : 1   ;
+        UINT32    dma_rd_int_mask       : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagMeepPortlogic78
+{
+
+    struct
+    {
+        UINT32    done_int_clr          : 1   ;
+        UINT32    Reserved_136          : 15  ;
+        UINT32    abort_int_clr         : 1   ;
+        UINT32    dma_rd_int_clr        : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagMeepPortlogic79
+{
+
+    struct
+    {
+        UINT32    app_wr_err_det        : 1   ;
+        UINT32    Reserved_137          : 15  ;
+        UINT32    link_list_fetch_err_det  : 1   ;
+        UINT32    dma_rd_err_low        : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagMeepPortlogic80
+{
+
+    struct
+    {
+        UINT32    unspt_request         : 8   ;
+        UINT32    completer_abort       : 8   ;
+        UINT32    cpl_time_out          : 8   ;
+        UINT32    data_poison           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagMeepPortlogic81
+{
+
+    struct
+    {
+        UINT32    remote_abort_int_en   : 1   ;
+        UINT32    Reserved_139          : 15  ;
+        UINT32    local_abort_int_en    : 1   ;
+        UINT32    dma_rd_ll_err_ena     : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagMeepPortlogic86
+{
+
+    struct
+    {
+        UINT32    channel_dir           : 3   ;
+        UINT32    Reserved_143          : 28  ;
+        UINT32    dma_ch_con_idx        : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagMeepPortlogic87
+{
+
+    struct
+    {
+        UINT32    cycle_bit             : 1   ;
+        UINT32    toggle_cycle_bit      : 1   ;
+        UINT32    load_link_pointer     : 1   ;
+        UINT32    local_int_en          : 1   ;
+        UINT32    remote_int_en         : 1   ;
+        UINT32    channel_status        : 2   ;
+        UINT32    Reserved_147          : 1   ;
+        UINT32    consumer_cycle_state  : 1   ;
+        UINT32    linked_list_en        : 1   ;
+        UINT32    Reserved_146          : 2   ;
+        UINT32    func_num_dma          : 5   ;
+        UINT32    Reserved_145          : 7   ;
+        UINT32    no_snoop              : 1   ;
+        UINT32    ro                    : 1   ;
+        UINT32    td                    : 1   ;
+        UINT32    tc                    : 3   ;
+        UINT32    dma_ch_ctrl           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagMeepPortlogic93
+{
+
+    struct
+    {
+        UINT32    Reserved_150          : 2   ;
+        UINT32    dma_ll_ptr_low        : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PORTLOGIC93_U;
+
+
+
+
+typedef union tagMeepPbar23xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_151          : 12  ;
+        UINT32    PBAR23_Xlat_Lower     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_153          : 12  ;
+        UINT32    PBAR45_Xlat_Lower     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar23lmtLower
+{
+
+    struct
+    {
+        UINT32    Reserved_154          : 12  ;
+        UINT32    PBAR23_Limit_Lower    : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45lmtLower
+{
+
+    struct
+    {
+        UINT32    Reserved_155          : 12  ;
+        UINT32    PBAR45_Limit_Lower    : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45lmtUpper
+{
+
+    struct
+    {
+        UINT32    Reserved_156          : 12  ;
+        UINT32    PBAR45_Limit_Upper    : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMeepB2bBar01xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_157          : 17  ;
+        UINT32    B2B_PBAR01_Xlat_Lower  : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_B2B_BAR01XLAT_Lower_U;
+
+
+
+
+typedef union tagMeepPpd
+{
+
+    struct
+    {
+        UINT32    port_def              : 1   ;
+        UINT32    Reserved_159          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PPD_U;
+
+
+
+
+typedef union tagMeepDeviceVendorId
+{
+
+    struct
+    {
+        UINT32    Vendor_ID             : 16  ;
+        UINT32    Device_ID             : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_Device_Vendor_ID_U;
+
+
+
+
+typedef union tagMeepPcistsPcicmd
+{
+
+    struct
+    {
+        UINT32    io_space_enable       : 1   ;
+        UINT32    memory_space_enable   : 1   ;
+        UINT32    bus_master_enable     : 1   ;
+        UINT32    specialcycleenable    : 1   ;
+        UINT32    memory_write_and_invalidate  : 1   ;
+        UINT32    vga_palette_snoop_enable  : 1   ;
+        UINT32    parity_error_response  : 1   ;
+        UINT32    idsel_stepping_waitcycle_control  : 1   ;
+        UINT32    serr_enable           : 1   ;
+        UINT32    fastback_to_backenable  : 1   ;
+        UINT32    Interrupt_Disable     : 1   ;
+        UINT32    Reserved_164          : 5   ;
+        UINT32    Reserved_163          : 3   ;
+        UINT32    intx_status           : 1   ;
+        UINT32    capabilitieslist      : 1   ;
+        UINT32    pcibus66mhzcapable    : 1   ;
+        UINT32    Reserved_162          : 1   ;
+        UINT32    fastback_to_back      : 1   ;
+        UINT32    masterdataparityerror  : 1   ;
+        UINT32    devsel_timing         : 2   ;
+        UINT32    Signaled_Target_Abort  : 1   ;
+        UINT32    Received_Target_Abort  : 1   ;
+        UINT32    Received_Master_Abort  : 1   ;
+        UINT32    Signaled_System_Error  : 1   ;
+        UINT32    Detected_Parity_Error  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagMeepCcrRid
+{
+
+    struct
+    {
+        UINT32    revision_identification  : 8   ;
+        UINT32    Reserved_165          : 8   ;
+        UINT32    sub_class             : 8   ;
+        UINT32    baseclass             : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_CCR_RID_U;
+
+
+
+
+typedef union tagMeepPbar01BaseLower
+{
+
+    struct
+    {
+        UINT32    BAR01_Space_Inicator  : 1   ;
+        UINT32    BAR01_Type            : 2   ;
+        UINT32    BAR01_Prefetchable    : 1   ;
+        UINT32    Reserved_166          : 13  ;
+        UINT32    base_address_register_01_lower  : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar23BaseLower
+{
+
+    struct
+    {
+        UINT32    BAR23_Space_Inicator  : 1   ;
+        UINT32    BAR23_Type            : 2   ;
+        UINT32    BAR23_Prefetchable    : 1   ;
+        UINT32    Reserved_168          : 8   ;
+        UINT32    Base_Address_Register_23_Lower  : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepPbar45BaseLower
+{
+
+    struct
+    {
+        UINT32    BAR45_Space_Inicator  : 1   ;
+        UINT32    BAR45_Type            : 2   ;
+        UINT32    BAR45_Prefetchable    : 1   ;
+        UINT32    Reserved_169          : 8   ;
+        UINT32    Base_Address_Register_45_Lower  : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagMeepSubsystemid
+{
+
+    struct
+    {
+        UINT32    SubsystemID           : 16  ;
+        UINT32    SubsystemVendorID     : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_SubSystemId_U;
+
+
+
+
+typedef union tagMeepCapptr
+{
+
+    struct
+    {
+        UINT32    CapPtr                : 8   ;
+        UINT32    Reserved_172          : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_CapPtr_U;
+
+
+
+
+typedef union tagMeepInterrupt
+{
+
+    struct
+    {
+        UINT32    Interrupt_Line        : 8   ;
+        UINT32    interrupt_pin         : 8   ;
+        UINT32    min_grant             : 8   ;
+        UINT32    Max_Latency           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_Interrupt_U;
+
+
+
+
+typedef union tagMeepMsiCapabilityRegister
+{
+
+    struct
+    {
+        UINT32    CapabilityID          : 8   ;
+        UINT32    Next_Capability_Pointer  : 8   ;
+        UINT32    MSI_Enabled           : 1   ;
+        UINT32    Multiple_Message_Capable  : 3   ;
+        UINT32    Multiple_Message_Enabled  : 3   ;
+        UINT32    MSI_64_EN             : 1   ;
+        UINT32    PVM_EN                : 1   ;
+        UINT32    Message_Control_Register  : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_MSI_Capability_Register_U;
+
+
+
+
+typedef union tagMeepMsiLower32Bitaddress
+{
+
+    struct
+    {
+        UINT32    Reserved_175          : 2   ;
+        UINT32    Lower32_bitAddress    : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_MSI_Lower32_bitAddress_U;
+
+
+
+
+typedef union tagMeepMsiData
+{
+
+    struct
+    {
+        UINT32    MSI_Data              : 16  ;
+        UINT32    Reserved_176          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_MSI_Data_U;
+
+
+
+
+typedef union tagMeepMsiMask
+{
+
+    struct
+    {
+        UINT32    MsiMask               : 1   ;
+        UINT32    Reserved_177          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_MSI_MASK_U;
+
+
+
+
+typedef union tagMeepMsiPending
+{
+
+    struct
+    {
+        UINT32    MsiPending            : 1   ;
+        UINT32    Reserved_178          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_MSI_Pending_U;
+
+
+
+
+typedef union tagMeepPcieCapabilityRegister
+{
+
+    struct
+    {
+        UINT32    Capability_ID         : 8   ;
+        UINT32    Next_Capability_Pointer  : 8   ;
+        UINT32    PCIE_Capability_Version  : 4   ;
+        UINT32    Device_Port_Type      : 4   ;
+        UINT32    Slot_Implemented      : 1   ;
+        UINT32    Interrupt_Message_Number  : 5   ;
+        UINT32    Reserved_179          : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_PCIE_Capability_Register_U;
+
+
+
+
+typedef union tagMeepDeviceCapabilitiesRegister
+{
+
+    struct
+    {
+        UINT32    Max_Payload_Size_Supported  : 3   ;
+        UINT32    Phantom_Function_Supported  : 2   ;
+        UINT32    Extended_TagField_Supported  : 1   ;
+        UINT32    Endpoint_L0sAcceptable_Latency  : 3   ;
+        UINT32    Endpoint_L1Acceptable_Latency  : 3   ;
+        UINT32    Undefined             : 3   ;
+        UINT32    Reserved_182          : 3   ;
+        UINT32    Captured_Slot_Power_Limit_Value  : 8   ;
+        UINT32    Captured_Slot_Power_Limit_Scale  : 2   ;
+        UINT32    Function_Level_Reset  : 1   ;
+        UINT32    Reserved_181          : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_Device_Capabilities_Register_U;
+
+
+
+
+typedef union tagMeepDeviceStatusRegister
+{
+
+    struct
+    {
+        UINT32    Correctable_Error_Reporting_Enable  : 1   ;
+        UINT32    Non_Fatal_Error_Reporting_Enable  : 1   ;
+        UINT32    Fatal_Error_Reporting_Enable  : 1   ;
+        UINT32    UREnable              : 1   ;
+        UINT32    Enable_Relaxed_Ordering  : 1   ;
+        UINT32    Max_Payload_Size      : 3   ;
+        UINT32    Extended_TagFieldEnable  : 1   ;
+        UINT32    Phantom_Function_Enable  : 1   ;
+        UINT32    AUXPowerPMEnable      : 1   ;
+        UINT32    EnableNoSnoop         : 1   ;
+        UINT32    Max_Read_Request_Size  : 3   ;
+        UINT32    Reserved_184          : 1   ;
+        UINT32    CorrectableErrorDetected  : 1   ;
+        UINT32    Non_FatalErrordetected  : 1   ;
+        UINT32    FatalErrorDetected    : 1   ;
+        UINT32    UnsupportedRequestDetected  : 1   ;
+        UINT32    AuxPowerDetected      : 1   ;
+        UINT32    TransactionPending    : 1   ;
+        UINT32    Reserved_183          : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_Device_Status_Register_U;
+
+
+
+
+typedef union tagMeepLinkCapability
+{
+
+    struct
+    {
+        UINT32    Max_Link_Speed        : 4   ;
+        UINT32    Max_Link_Width        : 6   ;
+        UINT32    Active_State_Power_Management  : 2   ;
+        UINT32    L0s_ExitLatency       : 3   ;
+        UINT32    L1_Exit_Latency       : 3   ;
+        UINT32    Clock_Power_Management  : 1   ;
+        UINT32    Surprise_Down_Error_Report_Cap  : 1   ;
+        UINT32    Data_Link_Layer_Active_Report_Cap  : 1   ;
+        UINT32    Link_Bandwidth_Noti_Cap  : 1   ;
+        UINT32    ASPM_Option_Compliance  : 1   ;
+        UINT32    Reserved_185          : 1   ;
+        UINT32    Port_Number           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_Link_Capability_U;
+
+
+
+
+typedef union tagMeepLinkControlStatus
+{
+
+    struct
+    {
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    Reserved_188          : 1   ;
+        UINT32    rcb                   : 1   ;
+        UINT32    link_disable          : 1   ;
+        UINT32    retrain_link          : 1   ;
+        UINT32    common_clock_config   : 1   ;
+        UINT32    extended_sync         : 1   ;
+        UINT32    enable_clock_pwr_management  : 1   ;
+        UINT32    hw_auto_width_disable  : 1   ;
+        UINT32    link_bandwidth_management_int_en  : 1   ;
+        UINT32    link_auto_bandwidth_int_en  : 1   ;
+        UINT32    Reserved_187          : 4   ;
+        UINT32    current_link_speed    : 4   ;
+        UINT32    negotiated_link_width  : 6   ;
+        UINT32    Reserved_186          : 1   ;
+        UINT32    link_training         : 1   ;
+        UINT32    slot_clock_configration  : 1   ;
+        UINT32    data_link_layer_active  : 1   ;
+        UINT32    link_bandwidth_management_status  : 1   ;
+        UINT32    link_auto_bandwidth_status  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_Link_Control_Status_U;
+
+
+
+
+typedef union tagMeepAerCapHeader
+{
+
+    struct
+    {
+        UINT32    PCIE_Extended_Capability_ID  : 16  ;
+        UINT32    Capability_Version    : 4   ;
+        UINT32    Next_Capability_Offset  : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AER_Cap_header_U;
+
+
+
+
+typedef union tagMeepUcErrorStatus
+{
+
+    struct
+    {
+        UINT32    Reserved_193          : 1   ;
+        UINT32    Reserved_192          : 3   ;
+        UINT32    DataLinkProtocolErrorStatus  : 1   ;
+        UINT32    SurpriseDownErrorStatus  : 1   ;
+        UINT32    Reserved_191          : 6   ;
+        UINT32    PoisonedTLPStatus     : 1   ;
+        UINT32    FlowControlProtocolErrorStatus  : 1   ;
+        UINT32    CompletionTimeoutStatus  : 1   ;
+        UINT32    CompleterAbortStatus  : 1   ;
+        UINT32    UnexpectedCompletionStatus  : 1   ;
+        UINT32    ReceiverOverflowStatus  : 1   ;
+        UINT32    MalformedTLPStatus    : 1   ;
+        UINT32    ECRCErrorStatus       : 1   ;
+        UINT32    UnsupportedRequestErrorStatus  : 1   ;
+        UINT32    Reserved_190          : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_UC_Error_Status_U;
+
+
+
+
+typedef union tagMeepUcErrorMask
+{
+
+    struct
+    {
+        UINT32    Reserved_197          : 1   ;
+        UINT32    Reserved_196          : 3   ;
+        UINT32    DataLinkProtocolErrorMask  : 1   ;
+        UINT32    SurpriseDownErrorMask  : 1   ;
+        UINT32    Reserved_195          : 6   ;
+        UINT32    PoisonedTLPMask       : 1   ;
+        UINT32    FlowControlProtocolErrorMask  : 1   ;
+        UINT32    CompletionTimeoutMask  : 1   ;
+        UINT32    CompleterAbortMask    : 1   ;
+        UINT32    UnexpectedCompletionMask  : 1   ;
+        UINT32    ReceiverOverflowMask  : 1   ;
+        UINT32    MalformedTLPMask      : 1   ;
+        UINT32    ECRCErrorMask         : 1   ;
+        UINT32    UnsupportedRequestErrorMask  : 1   ;
+        UINT32    Reserved_194          : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_UC_Error_Mask_U;
+
+
+
+
+typedef union tagMeepUcErrorSeverity
+{
+
+    struct
+    {
+        UINT32    Reserved_201          : 1   ;
+        UINT32    Reserved_200          : 3   ;
+        UINT32    DataLinkProtocolErrorSeverity  : 1   ;
+        UINT32    SurpriseDownErrorSeverity  : 1   ;
+        UINT32    Reserved_199          : 6   ;
+        UINT32    PoisonedTLPSeverity   : 1   ;
+        UINT32    FlowControlProtocolErrorSeverity  : 1   ;
+        UINT32    CompletionTimeoutSeverity  : 1   ;
+        UINT32    CompleterAbortSeverity  : 1   ;
+        UINT32    UnexpectedCompletionSeverity  : 1   ;
+        UINT32    ReceiverOverflowSeverity  : 1   ;
+        UINT32    MalformedTLPSeverity  : 1   ;
+        UINT32    ECRCErrorSeverity     : 1   ;
+        UINT32    UnsupportedRequestErrorSeverity  : 1   ;
+        UINT32    Reserved_198          : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_UC_Error_Severity_U;
+
+
+
+
+typedef union tagMeepCErrorStatus
+{
+
+    struct
+    {
+        UINT32    Receiver_Error_Status  : 1   ;
+        UINT32    Reserved_204          : 5   ;
+        UINT32    Bad_TLP_Status        : 1   ;
+        UINT32    Bad_DLLP_Status       : 1   ;
+        UINT32    REPLAY_NUM_Rollover_Status  : 1   ;
+        UINT32    Reserved_203          : 3   ;
+        UINT32    Replay_Timer_Timeout_Status  : 1   ;
+        UINT32    Advisory_Non_Fatal_Error_Status  : 1   ;
+        UINT32    Reserved_202          : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_C_Error_Status_U;
+
+
+
+
+typedef union tagMeepCErrorMask
+{
+
+    struct
+    {
+        UINT32    Receiver_Error_Mask   : 1   ;
+        UINT32    Reserved_207          : 5   ;
+        UINT32    Bad_TLP_Mask          : 1   ;
+        UINT32    Bad_DLLP_Mask         : 1   ;
+        UINT32    REPLAY_NUMRollover_Mask  : 1   ;
+        UINT32    Reserved_206          : 3   ;
+        UINT32    Replay_Timer_Timeout_Mask  : 1   ;
+        UINT32    Advisory_Non_Fatal_Error_Mask  : 1   ;
+        UINT32    Reserved_205          : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_C_Error_Mask_U;
+
+
+
+
+typedef union tagMeepAdvancedErrorCapabilitiesAndControl
+{
+
+    struct
+    {
+        UINT32    First_Error_Pointer   : 5   ;
+        UINT32    ECRC_Generation_Capability  : 1   ;
+        UINT32    ECRC_Generation_Enable  : 1   ;
+        UINT32    ECRC_Check_Capable    : 1   ;
+        UINT32    ECRC_Check_Enable     : 1   ;
+        UINT32    Reserved_209          : 2   ;
+        UINT32    TLP_Prefix_Log_Present  : 1   ;
+        UINT32    Reserved_208          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_Advanced_Error_Capabilities_and_Control_U;
+
+
+
+
+typedef union tagMeepNtbIepBar01Ctrl
+{
+
+    struct
+    {
+        UINT32    bar01_type            : 5   ;
+        UINT32    bar01_tc              : 3   ;
+        UINT32    bar01_td              : 1   ;
+        UINT32    bar01_attr            : 2   ;
+        UINT32    Reserved_213          : 5   ;
+        UINT32    bar01_at              : 2   ;
+        UINT32    bar01_match_en        : 1   ;
+        UINT32    Reserved_212          : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR01_CTRL_U;
+
+
+
+
+typedef union tagMeepNtbIepBar23Ctrl
+{
+
+    struct
+    {
+        UINT32    bar23_type            : 5   ;
+        UINT32    bar23_tc              : 3   ;
+        UINT32    bar23_td              : 1   ;
+        UINT32    bar23_attr            : 2   ;
+        UINT32    Reserved_215          : 5   ;
+        UINT32    bar23_at              : 2   ;
+        UINT32    bar23_match_en        : 1   ;
+        UINT32    Reserved_214          : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR23_CTRL_U;
+
+
+
+
+typedef union tagMeepNtbIepBar45Ctrl
+{
+
+    struct
+    {
+        UINT32    bar45_type            : 5   ;
+        UINT32    bar45_tc              : 3   ;
+        UINT32    bar45_td              : 1   ;
+        UINT32    bar45_attr            : 2   ;
+        UINT32    Reserved_217          : 5   ;
+        UINT32    bar45_at              : 2   ;
+        UINT32    bar45_match_en        : 1   ;
+        UINT32    Reserved_216          : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_NTB_IEP_BAR45_CTRL_U;
+
+
+
+
+typedef union tagMeepMsiCtrlIntEn
+{
+
+    struct
+    {
+        UINT32    msi_int_en            : 1   ;
+        UINT32    Reserved_218          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT_EN_U;
+
+
+
+
+typedef union tagMeepMsiCtrlInt0Mask
+{
+
+    struct
+    {
+        UINT32    msi_int_mask          : 1   ;
+        UINT32    Reserved_219          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT0_MASK_U;
+
+
+
+
+typedef union tagMeepMsiCtrlIntStatus
+{
+
+    struct
+    {
+        UINT32    msi_int               : 1   ;
+        UINT32    Reserved_220          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_MSI_CTRL_INT_STATUS_U;
+
+
+
+
+typedef union tagMeepDbiRoWrEn
+{
+
+    struct
+    {
+        UINT32    dbi_ro_wr_en          : 1   ;
+        UINT32    Reserved_221          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_DBI_RO_WR_EN_U;
+
+
+
+
+typedef union tagAxiErrResponse
+{
+
+    struct
+    {
+        UINT32    err_resp_mode         : 4   ;
+        UINT32    Reserved_222          : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MEEP_AXI_ERR_RESPONSE_U;
+
+
+
+
+
+
+
+#define PCIE_MIEP_PBAR23XLAT_LOWER_REG            (0x0)
+#define PCIE_MIEP_PBAR23XLAT_UPPER_REG            (0x4)
+#define PCIE_MIEP_PBAR45XLAT_LOWER_REG            (0x8)
+#define PCIE_MIEP_PBAR45XLAT_UPPER_REG            (0xC)
+#define PCIE_MIEP_PBAR23LMT_LOWER_REG             (0x10)
+#define PCIE_MIEP_PBAR23LMT_UPPER_REG             (0x14)
+#define PCIE_MIEP_PBAR45LMT_LOWER_REG             (0x18)
+#define PCIE_MIEP_PBAR45LMT_UPPER_REG             (0x1C)
+#define PCIE_MIEP_PDOORBELL_REG                   (0x20)
+#define PCIE_MIEP_PDOORBELL_MASK_REG              (0x24)
+#define PCIE_MIEP_B2B_BAR01XLAT_LOWER_REG         (0x28)
+#define PCIE_MIEP_B2B_BAR01XLAT_UPPER_REG         (0x2C)
+#define PCIE_MIEP_B2BDOORBELL_REG                 (0x30)
+#define PCIE_MIEP_SPAD0_REG                       (0x38)
+#define PCIE_MIEP_SPAD1_REG                       (0x3C)
+#define PCIE_MIEP_SPAD2_REG                       (0x40)
+#define PCIE_MIEP_SPAD3_REG                       (0x44)
+#define PCIE_MIEP_SPAD4_REG                       (0x48)
+#define PCIE_MIEP_SPAD5_REG                       (0x4C)
+#define PCIE_MIEP_SPAD6_REG                       (0x50)
+#define PCIE_MIEP_SPAD7_REG                       (0x54)
+#define PCIE_MIEP_SPAD8_REG                       (0x58)
+#define PCIE_MIEP_SPAD9_REG                       (0x5C)
+#define PCIE_MIEP_SPAD10_REG                      (0x60)
+#define PCIE_MIEP_SPAD11_REG                      (0x64)
+#define PCIE_MIEP_SPAD12_REG                      (0x68)
+#define PCIE_MIEP_SPAD13_REG                      (0x6C)
+#define PCIE_MIEP_SPAD14_REG                      (0x70)
+#define PCIE_MIEP_SPAD15_REG                      (0x74)
+#define PCIE_MIEP_SPAD16_REG                      (0x78)
+#define PCIE_MIEP_SPAD17_REG                      (0x7C)
+#define PCIE_MIEP_SPAD18_REG                      (0x80)
+#define PCIE_MIEP_SPAD19_REG                      (0x84)
+#define PCIE_MIEP_SPAD20_REG                      (0x88)
+#define PCIE_MIEP_SPAD21_REG                      (0x8C)
+#define PCIE_MIEP_SPAD22_REG                      (0x90)
+#define PCIE_MIEP_SPAD23_REG                      (0x94)
+#define PCIE_MIEP_SPAD24_REG                      (0x98)
+#define PCIE_MIEP_SPAD25_REG                      (0x9C)
+#define PCIE_MIEP_SPAD26_REG                      (0xA0)
+#define PCIE_MIEP_SPAD27_REG                      (0xA4)
+#define PCIE_MIEP_SPAD28_REG                      (0xA8)
+#define PCIE_MIEP_SPAD29_REG                      (0xAC)
+#define PCIE_MIEP_SPAD30_REG                      (0xB0)
+#define PCIE_MIEP_SPAD31_REG                      (0xB4)
+#define PCIE_MIEP_B2BSPAD0_REG                    (0xB8)
+#define PCIE_MIEP_B2BSPAD1_REG                    (0xBC)
+#define PCIE_MIEP_B2BSPAD2_REG                    (0xC0)
+#define PCIE_MIEP_B2BSPAD3_REG                    (0xC4)
+#define PCIE_MIEP_B2BSPAD4_REG                    (0xC8)
+#define PCIE_MIEP_B2BSPAD5_REG                    (0xCC)
+#define PCIE_MIEP_B2BSPAD6_REG                    (0xD0)
+#define PCIE_MIEP_B2BSPAD7_REG                    (0xD4)
+#define PCIE_MIEP_B2BSPAD8_REG                    (0xD8)
+#define PCIE_MIEP_B2BSPAD9_REG                    (0xDC)
+#define PCIE_MIEP_B2BSPAD10_REG                   (0xE0)
+#define PCIE_MIEP_B2BSPAD11_REG                   (0xE4)
+#define PCIE_MIEP_B2BSPAD12_REG                   (0xE8)
+#define PCIE_MIEP_B2BSPAD13_REG                   (0xEC)
+#define PCIE_MIEP_B2BSPAD14_REG                   (0xF0)
+#define PCIE_MIEP_B2BSPAD15_REG                   (0xF4)
+#define PCIE_MIEP_B2BSPAD16_REG                   (0xF8)
+#define PCIE_MIEP_B2BSPAD17_REG                   (0xFC)
+#define PCIE_MIEP_B2BSPAD18_REG                   (0x100)
+#define PCIE_MIEP_B2BSPAD19_REG                   (0x104)
+#define PCIE_MIEP_B2BSPAD20_REG                   (0x108)
+#define PCIE_MIEP_B2BSPAD21_REG                   (0x10C)
+#define PCIE_MIEP_B2BSPAD22_REG                   (0x110)
+#define PCIE_MIEP_B2BSPAD23_REG                   (0x114)
+#define PCIE_MIEP_B2BSPAD24_REG                   (0x118)
+#define PCIE_MIEP_B2BSPAD25_REG                   (0x11C)
+#define PCIE_MIEP_B2BSPAD26_REG                   (0x120)
+#define PCIE_MIEP_B2BSPAD27_REG                   (0x124)
+#define PCIE_MIEP_B2BSPAD28_REG                   (0x128)
+#define PCIE_MIEP_B2BSPAD29_REG                   (0x12C)
+#define PCIE_MIEP_B2BSPAD30_REG                   (0x130)
+#define PCIE_MIEP_B2BSPAD31_REG                   (0x134)
+#define PCIE_MIEP_PPD_REG                         (0x138)
+#define PCIE_MIEP_P_DEVICE_VENDOR_ID_REG          (0x1000)
+#define PCIE_MIEP_P_PCISTS_PCICMD_REG             (0x1004)
+#define PCIE_MIEP_P_CCR_RID_REG                   (0x1008)
+#define PCIE_MIEP_P_BIST_TYPE_REG                 (0x100C)
+#define PCIE_MIEP_PBAR01_BASE_LOWER_REG           (0x1010)
+#define PCIE_MIEP_PBAR01_BASE_UPPER_REG           (0x1014)
+#define PCIE_MIEP_PBAR23_BASE_LOWER_REG           (0x1018)
+#define PCIE_MIEP_PBAR23_BASE_UPPER_REG           (0x101C)
+#define PCIE_MIEP_PBAR45_BASE_LOWER_REG           (0x1020)
+#define PCIE_MIEP_PBAR45_BASE_UPPER_REG           (0x1024)
+#define PCIE_MIEP_P_SUBSYSTEMID_REG               (0x102C)
+#define PCIE_MIEP_P_INTERRUPT_REG                 (0x103C)
+#define PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_REG    (0x1054)
+#define PCIE_MIEP_P_MSI_UPPER32_BIT_ADDRESS_REG   (0x1058)
+#define PCIE_MIEP_P_LINK_CAPABILITY_REG           (0x107C)
+#define PCIE_MIEP_P_AER_CAP_HEADER_REG            (0x1100)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_1_REG    (0x111C)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_2_REG    (0x1120)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_3_REG    (0x1124)
+#define PCIE_MIEP_P_HEADER_LOG_REGISTERS_4_REG    (0x1128)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_1_REG  (0x1130)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_2_REG  (0x1134)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_3_REG  (0x1138)
+#define PCIE_MIEP_P_TLP_PREFIX_LOGREGISTERS_4_REG  (0x113C)
+#define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_LOWER_REG  (0x1700)
+#define PCIE_MIEP_P_NTB_IEP_CONFIG_SPACE_UPPER_REG  (0x1704)
+#define PCIE_MIEP_P_MSI_CTRL_ADDRESS_LOWER_REG    (0x1714)
+#define PCIE_MIEP_P_MSI_CTRL_ADDRESS_UPPER_REG    (0x1718)
+#define PCIE_MIEP_SBAR23XLAT_LOWER_REG            (0x8000)
+#define PCIE_MIEP_SBAR23XLAT_UPPER_REG            (0x8004)
+#define PCIE_MIEP_SBAR45XLAT_LOWER_REG            (0x8008)
+#define PCIE_MIEP_SBAR45XLAT_UPPER_REG            (0x800C)
+#define PCIE_MIEP_SBAR23LMT_LOWER_REG             (0x8010)
+#define PCIE_MIEP_SBAR23LMT_UPPER_REG             (0x8014)
+#define PCIE_MIEP_SBAR45LMT_LOWER_REG             (0x8018)
+#define PCIE_MIEP_SBAR45LMT_UPPER_REG             (0x801C)
+#define PCIE_MIEP_SDOORBELL_REG                   (0x8020)
+#define PCIE_MIEP_SDOORBELL_MASK_REG              (0x8024)
+#define PCIE_MIEP_CBDF_SBDF_REG                   (0x8028)
+#define PCIE_MIEP_PCI_CFG_HDR0_REG                (0x9000)
+#define PCIE_MIEP_PCI_CFG_HDR1_REG                (0x9004)
+#define PCIE_MIEP_PCI_CFG_HDR9_REG                (0x9024)
+#define PCIE_MIEP_PCI_CFG_HDR10_REG               (0x9028)
+#define PCIE_MIEP_PCI_CFG_HDR11_REG               (0x902C)
+#define PCIE_MIEP_PCI_CFG_HDR12_REG               (0x9030)
+#define PCIE_MIEP_PCI_CFG_HDR13_REG               (0x9034)
+#define PCIE_MIEP_PCI_CFG_HDR14_REG               (0x9038)
+#define PCIE_MIEP_PCI_CFG_HDR15_REG               (0x903C)
+#define PCIE_MIEP_PCI_PM_CAP0_REG                 (0x9040)
+#define PCIE_MIEP_PCI_PM_CAP1_REG                 (0x9044)
+#define PCIE_MIEP_PCI_MSI_CAP0_REG                (0x9050)
+#define PCIE_MIEP_PCI_MSI_CAP1_REG                (0x9054)
+#define PCIE_MIEP_PCI_MSI_CAP2_REG                (0x9058)
+#define PCIE_MIEP_PCI_MSI_CAP3_REG                (0x905C)
+#define PCIE_MIEP_PCIE_CAP0_REG                   (0x9070)
+#define PCIE_MIEP_PCIE_CAP1_REG                   (0x9074)
+#define PCIE_MIEP_PCIE_CAP2_REG                   (0x9078)
+#define PCIE_MIEP_PCIE_CAP3_REG                   (0x907C)
+#define PCIE_MIEP_PCIE_CAP4_REG                   (0x9080)
+#define PCIE_MIEP_PCIE_CAP5_REG                   (0x9084)
+#define PCIE_MIEP_PCIE_CAP6_REG                   (0x9088)
+#define PCIE_MIEP_PCIE_CAP7_REG                   (0x908C)
+#define PCIE_MIEP_PCIE_CAP8_REG                   (0x9090)
+#define PCIE_MIEP_PCIE_CAP9_REG                   (0x9094)
+#define PCIE_MIEP_PCIE_CAP10_REG                  (0x9098)
+#define PCIE_MIEP_PCIE_CAP11_REG                  (0x909C)
+#define PCIE_MIEP_PCIE_CAP12_REG                  (0x90A0)
+#define PCIE_MIEP_SLOT_CAP_REG                    (0x90C0)
+#define PCIE_MIEP_AER_CAP0_REG                    (0x9100)
+#define PCIE_MIEP_AER_CAP1_REG                    (0x9104)
+#define PCIE_MIEP_AER_CAP2_REG                    (0x9108)
+#define PCIE_MIEP_AER_CAP3_REG                    (0x910C)
+#define PCIE_MIEP_AER_CAP4_REG                    (0x9110)
+#define PCIE_MIEP_AER_CAP5_REG                    (0x9114)
+#define PCIE_MIEP_AER_CAP6_REG                    (0x9118)
+#define PCIE_MIEP_AER_CAP7_REG                    (0x911C)
+#define PCIE_MIEP_AER_CAP8_REG                    (0x9120)
+#define PCIE_MIEP_AER_CAP9_REG                    (0x9124)
+#define PCIE_MIEP_AER_CAP10_REG                   (0x9128)
+#define PCIE_MIEP_AER_CAP11_REG                   (0x912C)
+#define PCIE_MIEP_AER_CAP12_REG                   (0x9130)
+#define PCIE_MIEP_AER_CAP13_REG                   (0x9134)
+#define PCIE_MIEP_VC_CAP0_REG                     (0x9140)
+#define PCIE_MIEP_VC_CAP1_REG                     (0x9144)
+#define PCIE_MIEP_VC_CAP2_REG                     (0x9148)
+#define PCIE_MIEP_VC_CAP3_REG                     (0x914C)
+#define PCIE_MIEP_VC_CAP4_REG                     (0x9150)
+#define PCIE_MIEP_VC_CAP5_REG                     (0x9154)
+#define PCIE_MIEP_VC_CAP6_REG                     (0x9158)
+#define PCIE_MIEP_VC_CAP7_REG                     (0x915C)
+#define PCIE_MIEP_VC_CAP8_REG                     (0x9160)
+#define PCIE_MIEP_VC_CAP9_REG                     (0x9164)
+#define PCIE_MIEP_PORT_LOGIC0_REG                 (0x9700)
+#define PCIE_MIEP_PORT_LOGIC1_REG                 (0x9704)
+#define PCIE_MIEP_PORT_LOGIC2_REG                 (0x9708)
+#define PCIE_MIEP_PORT_LOGIC3_REG                 (0x970C)
+#define PCIE_MIEP_PORT_LOGIC4_REG                 (0x9710)
+#define PCIE_MIEP_PORT_LOGIC5_REG                 (0x9714)
+#define PCIE_MIEP_PORT_LOGIC6_REG                 (0x9718)
+#define PCIE_MIEP_PORT_LOGIC7_REG                 (0x971C)
+#define PCIE_MIEP_PORT_LOGIC8_REG                 (0x9720)
+#define PCIE_MIEP_PORT_LOGIC9_REG                 (0x9724)
+#define PCIE_MIEP_PORT_LOGIC10_REG                (0x9728)
+#define PCIE_MIEP_PORT_LOGIC11_REG                (0x972C)
+#define PCIE_MIEP_PORT_LOGIC12_REG                (0x9730)
+#define PCIE_MIEP_PORT_LOGIC13_REG                (0x9734)
+#define PCIE_MIEP_PORT_LOGIC14_REG                (0x9738)
+#define PCIE_MIEP_PORT_LOGIC15_REG                (0x973C)
+#define PCIE_MIEP_PORT_LOGIC16_REG                (0x9748)
+#define PCIE_MIEP_PORT_LOGIC17_REG                (0x974C)
+#define PCIE_MIEP_PORT_LOGIC18_REG                (0x9750)
+#define PCIE_MIEP_PORT_LOGIC19_REG                (0x97A8)
+#define PCIE_MIEP_PORT_LOGIC20_REG                (0x97AC)
+#define PCIE_MIEP_PORT_LOGIC21_REG                (0x97B0)
+#define PCIE_MIEP_PORT_LOGIC22_REG                (0x980C)
+#define PCIE_MIEP_PORTLOGIC23_REG                 (0x9810)
+#define PCIE_MIEP_PORTLOGIC24_REG                 (0x9814)
+#define PCIE_MIEP_PORTLOGIC25_REG                 (0x9818)
+#define PCIE_MIEP_PORTLOGIC26_REG                 (0x981C)
+#define PCIE_MIEP_PORTLOGIC27_REG                 (0x9820)
+#define PCIE_MIEP_PORTLOGIC28_REG                 (0x9824)
+#define PCIE_MIEP_PORTLOGIC29_REG                 (0x9828)
+#define PCIE_MIEP_PORTLOGIC30_REG                 (0x982C)
+#define PCIE_MIEP_PORTLOGIC31_REG                 (0x9830)
+#define PCIE_MIEP_PORTLOGIC32_REG                 (0x9834)
+#define PCIE_MIEP_PORTLOGIC33_REG                 (0x9838)
+#define PCIE_MIEP_PORTLOGIC34_REG                 (0x983C)
+#define PCIE_MIEP_PORTLOGIC35_REG                 (0x9840)
+#define PCIE_MIEP_PORTLOGIC36_REG                 (0x9844)
+#define PCIE_MIEP_PORTLOGIC37_REG                 (0x9848)
+#define PCIE_MIEP_PORTLOGIC38_REG                 (0x984C)
+#define PCIE_MIEP_PORTLOGIC39_REG                 (0x9850)
+#define PCIE_MIEP_PORTLOGIC40_REG                 (0x9854)
+#define PCIE_MIEP_PORTLOGIC41_REG                 (0x9858)
+#define PCIE_MIEP_PORTLOGIC42_REG                 (0x985C)
+#define PCIE_MIEP_PORTLOGIC43_REG                 (0x9860)
+#define PCIE_MIEP_PORTLOGIC44_REG                 (0x9864)
+#define PCIE_MIEP_PORTLOGIC45_REG                 (0x9868)
+#define PCIE_MIEP_PORTLOGIC46_REG                 (0x986C)
+#define PCIE_MIEP_PORTLOGIC47_REG                 (0x9870)
+#define PCIE_MIEP_PORTLOGIC48_REG                 (0x9874)
+#define PCIE_MIEP_PORTLOGIC49_REG                 (0x9878)
+#define PCIE_MIEP_PORTLOGIC50_REG                 (0x987C)
+#define PCIE_MIEP_PORTLOGIC51_REG                 (0x9880)
+#define PCIE_MIEP_PORTLOGIC52_REG                 (0x9884)
+#define PCIE_MIEP_PORTLOGIC53_REG                 (0x9888)
+#define PCIE_MIEP_PORTLOGIC54_REG                 (0x9900)
+#define PCIE_MIEP_PORTLOGIC55_REG                 (0x9904)
+#define PCIE_MIEP_PORTLOGIC56_REG                 (0x9908)
+#define PCIE_MIEP_PORTLOGIC57_REG                 (0x990C)
+#define PCIE_MIEP_PORTLOGIC58_REG                 (0x9910)
+#define PCIE_MIEP_PORTLOGIC59_REG                 (0x9914)
+#define PCIE_MIEP_PORTLOGIC60_REG                 (0x9918)
+#define PCIE_MIEP_PORTLOGIC61_REG                 (0x991C)
+#define PCIE_MIEP_PORTLOGIC62_REG                 (0x997C)
+#define PCIE_MIEP_PORTLOGIC63_REG                 (0x9980)
+#define PCIE_MIEP_PORTLOGIC64_REG                 (0x999C)
+#define PCIE_MIEP_PORTLOGIC65_REG                 (0x99A0)
+#define PCIE_MIEP_PORTLOGIC66_REG                 (0x99BC)
+#define PCIE_MIEP_PORTLOGIC67_REG                 (0x99C4)
+#define PCIE_MIEP_PORTLOGIC68_REG                 (0x99C8)
+#define PCIE_MIEP_PORTLOGIC69_REG                 (0x99CC)
+#define PCIE_MIEP_PORTLOGIC70_REG                 (0x99D0)
+#define PCIE_MIEP_PORTLOGIC71_REG                 (0x99D4)
+#define PCIE_MIEP_PORTLOGIC72_REG                 (0x99D8)
+#define PCIE_MIEP_PORTLOGIC73_REG                 (0x99DC)
+#define PCIE_MIEP_PORTLOGIC74_REG                 (0x99E0)
+#define PCIE_MIEP_PORTLOGIC75_REG                 (0x9A00)
+#define PCIE_MIEP_PORTLOGIC76_REG                 (0x9A10)
+#define PCIE_MIEP_PORTLOGIC77_REG                 (0x9A18)
+#define PCIE_MIEP_PORTLOGIC78_REG                 (0x9A1C)
+#define PCIE_MIEP_PORTLOGIC79_REG                 (0x9A24)
+#define PCIE_MIEP_PORTLOGIC80_REG                 (0x9A28)
+#define PCIE_MIEP_PORTLOGIC81_REG                 (0x9A34)
+#define PCIE_MIEP_PORTLOGIC82_REG                 (0x9A3C)
+#define PCIE_MIEP_PORTLOGIC83_REG                 (0x9A40)
+#define PCIE_MIEP_PORTLOGIC84_REG                 (0x9A44)
+#define PCIE_MIEP_PORTLOGIC85_REG                 (0x9A48)
+#define PCIE_MIEP_PORTLOGIC86_REG                 (0x9A6C)
+#define PCIE_MIEP_PORTLOGIC87_REG                 (0x9A70)
+#define PCIE_MIEP_PORTLOGIC88_REG                 (0x9A78)
+#define PCIE_MIEP_PORTLOGIC89_REG                 (0x9A7C)
+#define PCIE_MIEP_PORTLOGIC90_REG                 (0x9A80)
+#define PCIE_MIEP_PORTLOGIC91_REG                 (0x9A84)
+#define PCIE_MIEP_PORTLOGIC92_REG                 (0x9A88)
+#define PCIE_MIEP_PORTLOGIC93_REG                 (0x9A8C)
+#define PCIE_MIEP_PORTLOGIC94_REG                 (0x9A90)
+
+
+
+
+typedef union tagMiepPbar23xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_0            : 12  ;
+        UINT32    pbar23_xlat_lower     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_1            : 12  ;
+        UINT32    pbar45_xlat_lower     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar23lmtLower
+{
+
+    struct
+    {
+        UINT32    Reserved_2            : 12  ;
+        UINT32    pbar23_limit_lower    : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45lmtLower
+{
+
+    struct
+    {
+        UINT32    Reserved_3            : 12  ;
+        UINT32    pbar45_limit_lower    : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepB2bBar01xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_4            : 17  ;
+        UINT32    b2b_pbar01_xlat_lower  : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_B2B_BAR01XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepPpd
+{
+
+    struct
+    {
+        UINT32    port_def              : 1   ;
+        UINT32    Reserved_6            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PPD_U;
+
+
+
+
+typedef union tagMiepPDeviceVendorId
+{
+
+    struct
+    {
+        UINT32    vendor_id             : 16  ;
+        UINT32    device_id             : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_DEVICE_VENDOR_ID_U;
+
+
+
+
+typedef union tagMiepPPcistsPcicmd
+{
+
+    struct
+    {
+        UINT32    io_space_enable       : 1   ;
+        UINT32    memory_space_enable   : 1   ;
+        UINT32    bus_master_enable     : 1   ;
+        UINT32    specialcycleenable    : 1   ;
+        UINT32    memory_write_and_invalidate  : 1   ;
+        UINT32    vga_palette_snoop_enable  : 1   ;
+        UINT32    parity_error_response  : 1   ;
+        UINT32    idsel_stepping_waitcycle_control  : 1   ;
+        UINT32    serr_enable           : 1   ;
+        UINT32    fastback_to_backenable  : 1   ;
+        UINT32    interrupt_disable     : 1   ;
+        UINT32    Reserved_10           : 5   ;
+        UINT32    Reserved_9            : 3   ;
+        UINT32    intx_status           : 1   ;
+        UINT32    capabilitieslist      : 1   ;
+        UINT32    pcibus66mhzcapable    : 1   ;
+        UINT32    Reserved_8            : 1   ;
+        UINT32    fastback_to_back      : 1   ;
+        UINT32    masterdataparityerror  : 1   ;
+        UINT32    devsel_timing         : 2   ;
+        UINT32    signaled_target_abort  : 1   ;
+        UINT32    received_target_abort  : 1   ;
+        UINT32    received_master_abort  : 1   ;
+        UINT32    signaled_system_error  : 1   ;
+        UINT32    detected_parity_error  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagMiepPCcrRid
+{
+
+    struct
+    {
+        UINT32    revision_id           : 8   ;
+        UINT32    Reserved_11           : 8   ;
+        UINT32    cfg_sub_class         : 8   ;
+        UINT32    cfg_base_class        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_CCR_RID_U;
+
+
+
+
+typedef union tagMiepPBistType
+{
+
+    struct
+    {
+        UINT32    cache_line_size       : 8   ;
+        UINT32    primary_latency_timer  : 8   ;
+        UINT32    cfg_hdr_type          : 8   ;
+        UINT32    bist                  : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_BIST_TYPE_U;
+
+
+
+
+typedef union tagMiepPbar01BaseLower
+{
+
+    struct
+    {
+        UINT32    cfg_iep_bar0_io       : 1   ;
+        UINT32    cfg_iep_bar0_type     : 2   ;
+        UINT32    cfg_iep_bar0_pref     : 1   ;
+        UINT32    Reserved_12           : 13  ;
+        UINT32    bar0_low              : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar23BaseLower
+{
+
+    struct
+    {
+        UINT32    cfg_iep_bar2_io       : 1   ;
+        UINT32    cfg_iep_bar2_type     : 2   ;
+        UINT32    cfg_iep_bar2_pref     : 1   ;
+        UINT32    Reserved_13           : 8   ;
+        UINT32    bar2_low              : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPbar45BaseLower
+{
+
+    struct
+    {
+        UINT32    cfg_iep_bar4_io       : 1   ;
+        UINT32    cfg_iep_bar4_type     : 2   ;
+        UINT32    cfg_iep_bar4_pref     : 1   ;
+        UINT32    Reserved_14           : 8   ;
+        UINT32    bar4_low              : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagMiepPSubsystemid
+{
+
+    struct
+    {
+        UINT32    subsystem_device_id   : 16  ;
+        UINT32    subsystem_vendor_id   : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_SUBSYSTEMID_U;
+
+
+
+
+typedef union tagMiepPInterrupt
+{
+
+    struct
+    {
+        UINT32    int_line_reg          : 8   ;
+        UINT32    cfg_int_pin           : 8   ;
+        UINT32    min_gnt               : 8   ;
+        UINT32    max_lat               : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_INTERRUPT_U;
+
+
+
+
+typedef union tagMiepPMsiLower32Bitaddress
+{
+
+    struct
+    {
+        UINT32    Reserved_17           : 2   ;
+        UINT32    iep_msi_addr_low32    : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_MSI_LOWER32_BITADDRESS_U;
+
+
+
+
+typedef union tagMiepPLinkCapability
+{
+
+    struct
+    {
+        UINT32    cfg_pcie_max_link_speed  : 4   ;
+        UINT32    cfg_pcie_max_link_width  : 6   ;
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    l0s_exit_latency      : 3   ;
+        UINT32    l1_exit_latency       : 3   ;
+        UINT32    clock_power_management  : 1   ;
+        UINT32    surprise_down_error_report_cap  : 1   ;
+        UINT32    data_link_layer_active_report_cap  : 1   ;
+        UINT32    link_bandwidth_noti_cap  : 1   ;
+        UINT32    aspm_option_compliance  : 1   ;
+        UINT32    Reserved_19           : 1   ;
+        UINT32    cfg_pcie_port_num     : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_LINK_CAPABILITY_U;
+
+
+
+
+typedef union tagMiepPAerCapHeader
+{
+
+    struct
+    {
+        UINT32    PCIE_Extended_Capability_ID  : 16  ;
+        UINT32    Capability_Version    : 4   ;
+        UINT32    Next_Capability_Offset  : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_P_AER_CAP_HEADER_U;
+
+
+
+
+typedef union tagMiepSbar23xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_26           : 12  ;
+        UINT32    sbar23_xlat_lower     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_SBAR23XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45xlatLower
+{
+
+    struct
+    {
+        UINT32    Reserved_28           : 12  ;
+        UINT32    sbar45_xlat_lower     : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_SBAR45XLAT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar23lmtLower
+{
+
+    struct
+    {
+        UINT32    Reserved_29           : 12  ;
+        UINT32    sbar23_limit_lower    : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_SBAR23LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45lmtLower
+{
+
+    struct
+    {
+        UINT32    Reserved_30           : 12  ;
+        UINT32    sbar45_limit_lower    : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_SBAR45LMT_LOWER_U;
+
+
+
+
+typedef union tagMiepSbar45lmtUpper
+{
+
+    struct
+    {
+        UINT32    Reserved_31           : 12  ;
+        UINT32    sbar45_limit_upper    : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_SBAR45LMT_UPPER_U;
+
+
+
+
+typedef union tagMiepCbdfSbdf
+{
+
+    struct
+    {
+        UINT32    sfunc                 : 3   ;
+        UINT32    sdev                  : 5   ;
+        UINT32    sbus                  : 8   ;
+        UINT32    cap_sfunc_num         : 3   ;
+        UINT32    cap_sdev_num          : 5   ;
+        UINT32    cap_sbus_num          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_CBDF_SBDF_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr0
+{
+
+    struct
+    {
+        UINT32    vendor_id             : 16  ;
+        UINT32    device_id             : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr1
+{
+
+    struct
+    {
+        UINT32    io_space_enable       : 1   ;
+        UINT32    memory_space_enable   : 1   ;
+        UINT32    bus_master_enable     : 1   ;
+        UINT32    specialcycleenable    : 1   ;
+        UINT32    memory_write_and_invalidate  : 1   ;
+        UINT32    vga_palette_snoop_enable  : 1   ;
+        UINT32    parity_error_response  : 1   ;
+        UINT32    idsel_stepping_waitcycle_control  : 1   ;
+        UINT32    serr_enable           : 1   ;
+        UINT32    fastback_to_backenable  : 1   ;
+        UINT32    interrupt_disable     : 1   ;
+        UINT32    Reserved_35           : 5   ;
+        UINT32    Reserved_34           : 3   ;
+        UINT32    intx_status           : 1   ;
+        UINT32    capabilitieslist      : 1   ;
+        UINT32    pcibus66mhzcapable    : 1   ;
+        UINT32    Reserved_33           : 1   ;
+        UINT32    fastback_to_back      : 1   ;
+        UINT32    masterdataparityerror  : 1   ;
+        UINT32    devsel_timing         : 2   ;
+        UINT32    signaled_target_abort  : 1   ;
+        UINT32    received_target_abort  : 1   ;
+        UINT32    received_master_abort  : 1   ;
+        UINT32    signaled_system_error  : 1   ;
+        UINT32    detected_perr         : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr11
+{
+
+    struct
+    {
+        UINT32    subsystem_vendor_id   : 16  ;
+        UINT32    subsystemid           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr13
+{
+
+    struct
+    {
+        UINT32    capptr                : 8   ;
+        UINT32    Reserved_37           : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagMiepPciCfgHdr15
+{
+
+    struct
+    {
+        UINT32    int_line              : 8   ;
+        UINT32    int_pin               : 8   ;
+        UINT32    min_grant             : 8   ;
+        UINT32    max_latency           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagMiepPciMsiCap0
+{
+
+    struct
+    {
+        UINT32    msi_cap_id            : 8   ;
+        UINT32    next_capability_pointer  : 8   ;
+        UINT32    msi_enabled           : 1   ;
+        UINT32    multiple_message_capable  : 3   ;
+        UINT32    multiple_message_enabled  : 3   ;
+        UINT32    msi_64_en             : 1   ;
+        UINT32    pvm_en                : 1   ;
+        UINT32    message_control_register  : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagMiepPciMsiCap1
+{
+
+    struct
+    {
+        UINT32    Reserved_42           : 2   ;
+        UINT32    msi_addr_low          : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagMiepPciMsiCap3
+{
+
+    struct
+    {
+        UINT32    msi_data              : 16  ;
+        UINT32    Reserved_43           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagMiepPcieCap0
+{
+
+    struct
+    {
+        UINT32    pcie_cap_id           : 8   ;
+        UINT32    pcie_next_ptr         : 8   ;
+        UINT32    pcie_capability_version  : 4   ;
+        UINT32    device_port_type      : 4   ;
+        UINT32    slot_implemented      : 1   ;
+        UINT32    interrupt_message_number  : 5   ;
+        UINT32    Reserved_44           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagMiepPcieCap1
+{
+
+    struct
+    {
+        UINT32    max_payload_size_supported  : 3   ;
+        UINT32    phantom_function_supported  : 2   ;
+        UINT32    extended_tagfield_supported  : 1   ;
+        UINT32    endpoint_l0sacceptable_latency  : 3   ;
+        UINT32    endpoint_l1acceptable_latency  : 3   ;
+        UINT32    undefined             : 3   ;
+        UINT32    Reserved_47           : 3   ;
+        UINT32    captured_slot_power_limit_value  : 8   ;
+        UINT32    captured_slot_power_limit_scale  : 2   ;
+        UINT32    function_level_reset  : 1   ;
+        UINT32    Reserved_46           : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagMiepPcieCap2
+{
+
+    struct
+    {
+        UINT32    correctable_error_reporting_enable  : 1   ;
+        UINT32    non_fatal_error_reporting_enable  : 1   ;
+        UINT32    fatal_error_reporting_enable  : 1   ;
+        UINT32    urenable              : 1   ;
+        UINT32    enable_relaxed_ordering  : 1   ;
+        UINT32    max_payload_size      : 3   ;
+        UINT32    extended_tagfieldenable  : 1   ;
+        UINT32    phantom_function_enable  : 1   ;
+        UINT32    auxpowerpmenable      : 1   ;
+        UINT32    enablenosnoop         : 1   ;
+        UINT32    max_read_request_size  : 3   ;
+        UINT32    Reserved_49           : 1   ;
+        UINT32    correctableerrordetected  : 1   ;
+        UINT32    non_fatalerrordetected  : 1   ;
+        UINT32    fatalerrordetected    : 1   ;
+        UINT32    unsupportedrequestdetected  : 1   ;
+        UINT32    auxpowerdetected      : 1   ;
+        UINT32    transactionpending    : 1   ;
+        UINT32    Reserved_48           : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagMiepPcieCap3
+{
+
+    struct
+    {
+        UINT32    max_link_speed        : 4   ;
+        UINT32    max_link_width        : 6   ;
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    l0s_exitlatency       : 3   ;
+        UINT32    l1_exit_latency       : 3   ;
+        UINT32    clock_power_management  : 1   ;
+        UINT32    surprise_down_error_report_cap  : 1   ;
+        UINT32    data_link_layer_active_report_cap  : 1   ;
+        UINT32    link_bandwidth_noti_cap  : 1   ;
+        UINT32    aspm_option_compliance  : 1   ;
+        UINT32    Reserved_50           : 1   ;
+        UINT32    port_number           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagMiepPcieCap4
+{
+
+    struct
+    {
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    Reserved_53           : 1   ;
+        UINT32    rcb                   : 1   ;
+        UINT32    link_disable          : 1   ;
+        UINT32    retrain_link          : 1   ;
+        UINT32    common_clock_config   : 1   ;
+        UINT32    extended_sync         : 1   ;
+        UINT32    enable_clock_pwr_management  : 1   ;
+        UINT32    hw_auto_width_disable  : 1   ;
+        UINT32    link_bandwidth_management_int_en  : 1   ;
+        UINT32    link_auto_bandwidth_int_en  : 1   ;
+        UINT32    Reserved_52           : 4   ;
+        UINT32    current_link_speed    : 4   ;
+        UINT32    negotiated_link_width  : 6   ;
+        UINT32    Reserved_51           : 1   ;
+        UINT32    link_training         : 1   ;
+        UINT32    slot_clock_configration  : 1   ;
+        UINT32    data_link_layer_active  : 1   ;
+        UINT32    link_bandwidth_management_status  : 1   ;
+        UINT32    link_auto_bandwidth_status  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagMiepPcieCap5
+{
+
+    struct
+    {
+        UINT32    attentioonbuttonpresent  : 1   ;
+        UINT32    powercontrollerpresent  : 1   ;
+        UINT32    mrlsensorpresent      : 1   ;
+        UINT32    attentionindicatorpresent  : 1   ;
+        UINT32    powerindicatorpresent  : 1   ;
+        UINT32    hot_plugsurprise      : 1   ;
+        UINT32    hot_plugcapable       : 1   ;
+        UINT32    slotpowerlimitvalue   : 8   ;
+        UINT32    slotpowerlimitscale   : 2   ;
+        UINT32    electromechanicalinterlockpresen  : 1   ;
+        UINT32    no_cmd_complete_support  : 1   ;
+        UINT32    phy_slot_number       : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP5_U;
+
+
+
+
+typedef union tagMiepPcieCap6
+{
+
+    struct
+    {
+        UINT32    attentionbuttonpressedenable  : 1   ;
+        UINT32    powerfaultdetectedenable  : 1   ;
+        UINT32    mrlsensorchangedenable  : 1   ;
+        UINT32    presencedetectchangedenable  : 1   ;
+        UINT32    commandcompletedinterruptenable  : 1   ;
+        UINT32    hot_pluginterruptenable  : 1   ;
+        UINT32    attentionindicatorcontrol  : 2   ;
+        UINT32    powerindicatorcontrol  : 2   ;
+        UINT32    powercontrollercontrol  : 1   ;
+        UINT32    electromechanicalinterlockcontrol  : 1   ;
+        UINT32    datalinklayerstatechangedenable  : 1   ;
+        UINT32    Reserved_54           : 3   ;
+        UINT32    attentionbuttonpressed  : 1   ;
+        UINT32    powerfaultdetected    : 1   ;
+        UINT32    mrlsensorchanged      : 1   ;
+        UINT32    presencedetectchanged  : 1   ;
+        UINT32    commandcompleted      : 1   ;
+        UINT32    mrlsensorstate        : 1   ;
+        UINT32    presencedetectstate   : 1   ;
+        UINT32    electromechanicalinterlockstatus  : 1   ;
+        UINT32    datalinklayerstatechanged  : 1   ;
+        UINT32    slot_ctrl_status      : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagMiepPcieCap7
+{
+
+    struct
+    {
+        UINT32    systemerroroncorrectableerrorenable  : 1   ;
+        UINT32    systemerroronnon_fatalerrorenable  : 1   ;
+        UINT32    systemerroronfatalerrorenable  : 1   ;
+        UINT32    pmeinterruptenable    : 1   ;
+        UINT32    crssoftwarevisibilityenable  : 1   ;
+        UINT32    Reserved_55           : 11  ;
+        UINT32    crssoftwarevisibility  : 1   ;
+        UINT32    root_cap              : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagMiepPcieCap8
+{
+
+    struct
+    {
+        UINT32    pmerequesterid        : 16  ;
+        UINT32    pmestatus             : 1   ;
+        UINT32    pmepending            : 1   ;
+        UINT32    root_status           : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagMiepPcieCap9
+{
+
+    struct
+    {
+        UINT32    completiontimeoutrangessupported  : 4   ;
+        UINT32    completiontimeoutdisablesupported  : 1   ;
+        UINT32    ariforwardingsupported  : 1   ;
+        UINT32    atomicoproutingsupported  : 1   ;
+        UINT32    _2_bitatomicopcompletersupported  : 1   ;
+        UINT32    _4_bitatomicopcompletersupported  : 1   ;
+        UINT32    _28_bitcascompletersupported  : 1   ;
+        UINT32    noro_enabledpr_prpassing  : 1   ;
+        UINT32    Reserved_56           : 1   ;
+        UINT32    tphcompletersupported  : 2   ;
+        UINT32    dev_cap2              : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagMiepPcieCap10
+{
+
+    struct
+    {
+        UINT32    completiontimeoutvalue  : 4   ;
+        UINT32    completiontimeoutdisable  : 1   ;
+        UINT32    ariforwardingsupported  : 1   ;
+        UINT32    atomicoprequesterenable  : 1   ;
+        UINT32    atomicopegressblocking  : 1   ;
+        UINT32    idorequestenable      : 1   ;
+        UINT32    idocompletionenable   : 1   ;
+        UINT32    dev_ctrl2             : 22  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagMiepPcieCap11
+{
+
+    struct
+    {
+        UINT32    Reserved_58           : 1   ;
+        UINT32    gen1_suport           : 1   ;
+        UINT32    gen2_suport           : 1   ;
+        UINT32    gen3_suport           : 1   ;
+        UINT32    Reserved_57           : 4   ;
+        UINT32    crosslink_supported   : 1   ;
+        UINT32    link_cap2             : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagMiepPcieCap12
+{
+
+    struct
+    {
+        UINT32    targetlinkspeed       : 4   ;
+        UINT32    entercompliance       : 1   ;
+        UINT32    hardwareautonomousspeeddisa  : 1   ;
+        UINT32    selectablede_empha    : 1   ;
+        UINT32    transmitmargin        : 3   ;
+        UINT32    _entermodifiedcompliance  : 1   ;
+        UINT32    compliancesos         : 1   ;
+        UINT32    de_emphasislevel      : 4   ;
+        UINT32    currentde_emphasislevel  : 1   ;
+        UINT32    equalizationcomplete  : 1   ;
+        UINT32    equalizationphase1successful  : 1   ;
+        UINT32    equalizationphase2successful  : 1   ;
+        UINT32    equalizationphase3successful  : 1   ;
+        UINT32    linkequalizationrequest  : 1   ;
+        UINT32    link_ctrl2_status2    : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagMiepSlotCap
+{
+
+    struct
+    {
+        UINT32    slotnumberingcapabilitiesid  : 8   ;
+        UINT32    nextcapabilitypointer  : 8   ;
+        UINT32    add_incardslotsprovided  : 5   ;
+        UINT32    firstinchassis        : 1   ;
+        UINT32    Reserved_59           : 2   ;
+        UINT32    slot_cap              : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_SLOT_CAP_U;
+
+
+
+
+typedef union tagMiepAerCap0
+{
+
+    struct
+    {
+        UINT32    pciexpressextendedcapabilityid  : 16  ;
+        UINT32    capabilityversion     : 4   ;
+        UINT32    aer_cap_hdr           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP0_U;
+
+
+
+
+typedef union tagMiepAerCap1
+{
+
+    struct
+    {
+        UINT32    Reserved_65           : 1   ;
+        UINT32    Reserved_64           : 3   ;
+        UINT32    datalinkprotocolerrorsta  : 1   ;
+        UINT32    surprisedownerrorstatus  : 1   ;
+        UINT32    Reserved_63           : 6   ;
+        UINT32    poisonedtlpstatu      : 1   ;
+        UINT32    flowcontrolprotocolerrorst  : 1   ;
+        UINT32    completiontimeouts    : 1   ;
+        UINT32    completerabortstatus  : 1   ;
+        UINT32    receiveroverflowstatus  : 1   ;
+        UINT32    malformedtlpstatus    : 1   ;
+        UINT32    ecrcerrorstatus       : 1   ;
+        UINT32    ecrcerrorstat         : 1   ;
+        UINT32    unsupportedrequesterrorstatus  : 1   ;
+        UINT32    Reserved_62           : 3   ;
+        UINT32    atomicopegressblockedstatus  : 1   ;
+        UINT32    uncorr_err_status     : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP1_U;
+
+
+
+
+typedef union tagMiepAerCap2
+{
+
+    struct
+    {
+        UINT32    Reserved_69           : 1   ;
+        UINT32    Reserved_68           : 3   ;
+        UINT32    datalinkprotocolerrormask  : 1   ;
+        UINT32    surprisedownerrormask  : 1   ;
+        UINT32    Reserved_67           : 6   ;
+        UINT32    poisonedtlpmask       : 1   ;
+        UINT32    flowcontrolprotocolerrormask  : 1   ;
+        UINT32    completiontimeoutmask  : 1   ;
+        UINT32    completerabortmask    : 1   ;
+        UINT32    unexpectedcompletionmask  : 1   ;
+        UINT32    receiveroverflowmask  : 1   ;
+        UINT32    malformedtlpmask      : 1   ;
+        UINT32    ecrcerrormask         : 1   ;
+        UINT32    unsupportedrequesterrormask  : 1   ;
+        UINT32    Reserved_66           : 3   ;
+        UINT32    atomicopegressblockedmask  : 1   ;
+        UINT32    uncorr_err_mask       : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP2_U;
+
+
+
+
+typedef union tagMiepAerCap3
+{
+
+    struct
+    {
+        UINT32    Reserved_73           : 1   ;
+        UINT32    Reserved_72           : 3   ;
+        UINT32    datalinkprotocolerrorsever  : 1   ;
+        UINT32    surprisedownerrorseverity  : 1   ;
+        UINT32    Reserved_71           : 6   ;
+        UINT32    poisonedtlpseverity   : 1   ;
+        UINT32    flowcontrolprotocolerrorseveri  : 1   ;
+        UINT32    completiontimeoutseverity  : 1   ;
+        UINT32    completerabortseverity  : 1   ;
+        UINT32    unexpectedcompletionseverity  : 1   ;
+        UINT32    receiveroverflowseverity  : 1   ;
+        UINT32    malformedtlpseverity  : 1   ;
+        UINT32    ecrcerrorseverity     : 1   ;
+        UINT32    unsupportedrequesterrorseverity  : 1   ;
+        UINT32    Reserved_70           : 3   ;
+        UINT32    atomicopegressblockedseverity  : 1   ;
+        UINT32    uncorr_err_ser        : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP3_U;
+
+
+
+
+typedef union tagMiepAerCap4
+{
+
+    struct
+    {
+        UINT32    receivererrorstatus   : 1   ;
+        UINT32    Reserved_75           : 5   ;
+        UINT32    badtlpstatus          : 1   ;
+        UINT32    baddllpstatus         : 1   ;
+        UINT32    replay_numrolloverstatus  : 1   ;
+        UINT32    Reserved_74           : 3   ;
+        UINT32    replytimertimeoutstatus  : 1   ;
+        UINT32    advisorynon_fatalerrorstatus  : 1   ;
+        UINT32    corr_err_status       : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP4_U;
+
+
+
+
+typedef union tagMiepAerCap5
+{
+
+    struct
+    {
+        UINT32    receivererrormask     : 1   ;
+        UINT32    Reserved_77           : 5   ;
+        UINT32    badtlpmask            : 1   ;
+        UINT32    baddllpmask           : 1   ;
+        UINT32    replay_numrollovermask  : 1   ;
+        UINT32    Reserved_76           : 3   ;
+        UINT32    replytimertimeoutmask  : 1   ;
+        UINT32    advisorynon_fatalerrormask  : 1   ;
+        UINT32    corr_err_mask         : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP5_U;
+
+
+
+
+typedef union tagMiepAerCap6
+{
+
+    struct
+    {
+        UINT32    firsterrorpointer     : 5   ;
+        UINT32    ecrcgenerationcapability  : 1   ;
+        UINT32    ecrcgenerationenable  : 1   ;
+        UINT32    ecrccheckcapable      : 1   ;
+        UINT32    ecrccheckenable       : 1   ;
+        UINT32    adv_cap_ctrl          : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP6_U;
+
+
+
+
+typedef union tagMiepAerCap11
+{
+
+    struct
+    {
+        UINT32    correctableerrorreportingenable  : 1   ;
+        UINT32    non_fatalerrorreportingenable  : 1   ;
+        UINT32    fatalerrorreportingenable  : 1   ;
+        UINT32    root_err_cmd          : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP11_U;
+
+
+
+
+typedef union tagMiepAerCap12
+{
+
+    struct
+    {
+        UINT32    err_correceived       : 1   ;
+        UINT32    multipleerr_correceived  : 1   ;
+        UINT32    err_fatal_nonfatalreceived  : 1   ;
+        UINT32    multipleerr_fatal_nonfatalreceived  : 1   ;
+        UINT32    firstuncorrectablefatal  : 1   ;
+        UINT32    non_fatalerrormessagesreceived  : 1   ;
+        UINT32    fatalerrormessagesreceived  : 1   ;
+        UINT32    Reserved_78           : 20  ;
+        UINT32    root_err_status       : 5   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP12_U;
+
+
+
+
+typedef union tagMiepAerCap13
+{
+
+    struct
+    {
+        UINT32    err_corsourceidentification  : 16  ;
+        UINT32    err_src_id            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_AER_CAP13_U;
+
+
+
+
+typedef union tagMiepVcCap0
+{
+
+    struct
+    {
+        UINT32    pciexpressextendedcapabilityid  : 16  ;
+        UINT32    capabilityversion     : 4   ;
+        UINT32    vc_cap_hdr            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP0_U;
+
+
+
+
+typedef union tagMiepVcCap1
+{
+
+    struct
+    {
+        UINT32    extendedvccount       : 3   ;
+        UINT32    Reserved_81           : 1   ;
+        UINT32    lowpriorityextendedvccount  : 3   ;
+        UINT32    Reserved_80           : 1   ;
+        UINT32    referenceclock        : 2   ;
+        UINT32    portarbitrationtableentrysize  : 2   ;
+        UINT32    vc_cap1               : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP1_U;
+
+
+
+
+typedef union tagMiepVcCap2
+{
+
+    struct
+    {
+        UINT32    vcarbitrationcapability  : 8   ;
+        UINT32    Reserved_82           : 16  ;
+        UINT32    vc_cap2               : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP2_U;
+
+
+
+
+typedef union tagMiepVcCap3
+{
+
+    struct
+    {
+        UINT32    loadvcarbitrationtable  : 1   ;
+        UINT32    vcarbitrationselect   : 3   ;
+        UINT32    Reserved_84           : 12  ;
+        UINT32    arbitrationtablestatus  : 1   ;
+        UINT32    Reserved_83           : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP3_U;
+
+
+
+
+typedef union tagMiepVcCap4
+{
+
+    struct
+    {
+        UINT32    portarbitrationcapability  : 8   ;
+        UINT32    Reserved_87           : 6   ;
+        UINT32    Reserved_86           : 1   ;
+        UINT32    rejectsnooptransactions  : 1   ;
+        UINT32    maximumtimeslots      : 7   ;
+        UINT32    Reserved_85           : 1   ;
+        UINT32    vc_res_cap            : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP4_U;
+
+
+
+
+typedef union tagMiepVcCap5
+{
+
+    struct
+    {
+        UINT32    tc_vcmap              : 8   ;
+        UINT32    Reserved_90           : 8   ;
+        UINT32    loadportarbitrationtable  : 1   ;
+        UINT32    portarbitrationselec  : 3   ;
+        UINT32    Reserved_89           : 4   ;
+        UINT32    vcid                  : 3   ;
+        UINT32    Reserved_88           : 4   ;
+        UINT32    vc_res_ctrl           : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP5_U;
+
+
+
+
+typedef union tagMiepVcCap6
+{
+
+    struct
+    {
+        UINT32    Reserved_91           : 16  ;
+        UINT32    portarbitrationtablestatus  : 1   ;
+        UINT32    vcnegotiationpending  : 1   ;
+        UINT32    vc_res_status         : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP6_U;
+
+
+
+
+typedef union tagMiepVcCap7
+{
+
+    struct
+    {
+        UINT32    portarbitrationcapability  : 8   ;
+        UINT32    Reserved_94           : 6   ;
+        UINT32    Reserved_93           : 1   ;
+        UINT32    rejectsnooptransactions  : 1   ;
+        UINT32    maximumtimeslots      : 7   ;
+        UINT32    Reserved_92           : 1   ;
+        UINT32    vc_res_cap0           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP7_U;
+
+
+
+
+typedef union tagMiepVcCap8
+{
+
+    struct
+    {
+        UINT32    tc_vcmap              : 8   ;
+        UINT32    Reserved_97           : 8   ;
+        UINT32    loadportarbitrationtable  : 1   ;
+        UINT32    portarbitrationselect  : 3   ;
+        UINT32    Reserved_96           : 4   ;
+        UINT32    vcid                  : 3   ;
+        UINT32    Reserved_95           : 4   ;
+        UINT32    vc_res_ctrl0          : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP8_U;
+
+
+
+
+typedef union tagMiepVcCap9
+{
+
+    struct
+    {
+        UINT32    Reserved_98           : 16  ;
+        UINT32    arbitrationtablestatus  : 1   ;
+        UINT32    vcnegotiationpending  : 1   ;
+        UINT32    vc_res_status0        : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_VC_CAP9_U;
+
+
+
+
+typedef union tagMiepPortLogic0
+{
+
+    struct
+    {
+        UINT32    ack_lat_timer         : 16  ;
+        UINT32    replay_timer          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagMiepPortLogic2
+{
+
+    struct
+    {
+        UINT32    linknumber            : 8   ;
+        UINT32    Reserved_101          : 7   ;
+        UINT32    forcelink             : 1   ;
+        UINT32    linkstate             : 6   ;
+        UINT32    Reserved_100          : 2   ;
+        UINT32    port_force_link       : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagMiepPortLogic3
+{
+
+    struct
+    {
+        UINT32    ackfrequency          : 8   ;
+        UINT32    n_fts                 : 8   ;
+        UINT32    commonclockn_fts      : 8   ;
+        UINT32    l0sentrancelatency    : 3   ;
+        UINT32    l1entrancelatency     : 3   ;
+        UINT32    enteraspml1withoutreceiveinl0s  : 1   ;
+        UINT32    ack_aspm              : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagMiepPortLogic4
+{
+
+    struct
+    {
+        UINT32    vendorspecificdllprequest  : 1   ;
+        UINT32    scrambledisable       : 1   ;
+        UINT32    loopbackenable        : 1   ;
+        UINT32    resetassert           : 1   ;
+        UINT32    Reserved_104          : 1   ;
+        UINT32    dlllinkenable         : 1   ;
+        UINT32    Reserved_103          : 1   ;
+        UINT32    fastlinkmode          : 1   ;
+        UINT32    Reserved_102          : 8   ;
+        UINT32    linkmodeenable        : 6   ;
+        UINT32    crosslinkenable       : 1   ;
+        UINT32    crosslinkactive       : 1   ;
+        UINT32    port_link_ctrl        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagMiepPortLogic5
+{
+
+    struct
+    {
+        UINT32    insertlaneskewfortransmit  : 24  ;
+        UINT32    flowcontroldisable    : 1   ;
+        UINT32    ack_nakdisable        : 1   ;
+        UINT32    Reserved_105          : 5   ;
+        UINT32    lane_skew             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagMiepPortLogic6
+{
+
+    struct
+    {
+        UINT32    numberoftssymbols     : 4   ;
+        UINT32    Reserved_107          : 4   ;
+        UINT32    numberofskpsymbols    : 3   ;
+        UINT32    Reserved_106          : 3   ;
+        UINT32    timermodifierforreplaytimer  : 5   ;
+        UINT32    timermodifierforack_naklatencytimer  : 5   ;
+        UINT32    timermodifierforflowcontrolwatchdogtimer  : 5   ;
+        UINT32    sym_num               : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagMiepPortLogic7
+{
+
+    struct
+    {
+        UINT32    vc0posteddataqueuedepth  : 11  ;
+        UINT32    Reserved_108          : 4   ;
+        UINT32    sym_timer             : 1   ;
+        UINT32    maskfunctionmismatchfilteringfo  : 1   ;
+        UINT32    maskpoisonedtlpfiltering  : 1   ;
+        UINT32    maskbarmatchfiltering  : 1   ;
+        UINT32    masktype1configurationrequestfiltering  : 1   ;
+        UINT32    masklockedrequestfiltering  : 1   ;
+        UINT32    masktagerrorrulesforreceivedcompletions  : 1   ;
+        UINT32    maskrequesteridmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    maskfunctionmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    mask_traffic_classmis_match_error_forreceived_completions  : 1   ;
+        UINT32    mask_attributesmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    mask_length_mismatch_error_forreceive_dcompletions  : 1   ;
+        UINT32    maske_crcerror_filtering  : 1   ;
+        UINT32    maske_crcerror_filtering_forcompletions  : 1   ;
+        UINT32    message_control       : 1   ;
+        UINT32    maskfilteringofreceived  : 1   ;
+        UINT32    flt_mask1             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagMiepPortLogic8
+{
+
+    struct
+    {
+        UINT32    cx_flt_mask_venmsg0_drop  : 1   ;
+        UINT32    cx_flt_mask_venmsg1_drop  : 1   ;
+        UINT32    cx_flt_mask_dabort_4ucpl  : 1   ;
+        UINT32    cx_flt_mask_handle_flush  : 1   ;
+        UINT32    flt_mask2             : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagMiepPortLogic9
+{
+
+    struct
+    {
+        UINT32    amba_multi_outbound_decomp_np  : 1   ;
+        UINT32    amba_obnp_ctrl        : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagMiepPortLogic12
+{
+
+    struct
+    {
+        UINT32    transmitposteddatafccredits  : 12  ;
+        UINT32    transmitpostedheaderfccredits  : 8   ;
+        UINT32    tx_pfc_status         : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagMiepPortLogic13
+{
+
+    struct
+    {
+        UINT32    transmitnon_posteddatafccredits  : 12  ;
+        UINT32    transmitnon_postedheaderfccredits  : 8   ;
+        UINT32    tx_npfc_status        : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagMiepPortLogic14
+{
+
+    struct
+    {
+        UINT32    transmitcompletiondatafccredits  : 12  ;
+        UINT32    transmitcompletionheaderfccredits  : 8   ;
+        UINT32    tx_cplfc_status       : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagMiepPortLogic15
+{
+
+    struct
+    {
+        UINT32    rx_tlp_fc_credit_not_retured  : 1   ;
+        UINT32    tx_retry_buf_not_empty  : 1   ;
+        UINT32    rx_queue_not_empty    : 1   ;
+        UINT32    Reserved_110          : 13  ;
+        UINT32    fc_latency_timer_override_value  : 13  ;
+        UINT32    Reserved_109          : 2   ;
+        UINT32    fc_latency_timer_override_en  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagMiepPortLogic16
+{
+
+    struct
+    {
+        UINT32    vc0posteddatacredits  : 12  ;
+        UINT32    vc0postedheadercredits  : 8   ;
+        UINT32    Reserved_112          : 1   ;
+        UINT32    vc0_postedtlpqueuemode  : 1   ;
+        UINT32    vc0postedtlpqueuemode  : 1   ;
+        UINT32    vc0postedtlpqueuemo   : 1   ;
+        UINT32    Reserved_111          : 6   ;
+        UINT32    tlptypeorderingforvc0  : 1   ;
+        UINT32    rx_pque_ctrl          : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagMiepPortLogic17
+{
+
+    struct
+    {
+        UINT32    vc0non_posteddatacredits  : 12  ;
+        UINT32    vc0non_postedheadercredits  : 8   ;
+        UINT32    rx_npque_ctrl         : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagMiepPortLogic18
+{
+
+    struct
+    {
+        UINT32    vco_comp_data_credits  : 12  ;
+        UINT32    vc0_cpl_header_credt  : 8   ;
+        UINT32    Reserved_114          : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagMiepPortLogic19
+{
+
+    struct
+    {
+        UINT32    vco_posted_data_que_path  : 14  ;
+        UINT32    Reserved_115          : 2   ;
+        UINT32    vco_posted_head_queue_depth  : 10  ;
+        UINT32    vc_pbuf_ctrl          : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagMiepPortLogic20
+{
+
+    struct
+    {
+        UINT32    vco_np_data_que_depth  : 14  ;
+        UINT32    Reserved_117          : 2   ;
+        UINT32    vco_np_header_que_depth  : 10  ;
+        UINT32    vc_npbuf_ctrl         : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagMiepPortLogic21
+{
+
+    struct
+    {
+        UINT32    vco_comp_data_queue_depth  : 14  ;
+        UINT32    Reserved_119          : 2   ;
+        UINT32    vco_posted_head_queue_depth  : 10  ;
+        UINT32    Reserved_118          : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagMiepPortLogic22
+{
+
+    struct
+    {
+        UINT32    n_fts                 : 8   ;
+        UINT32    pre_determ_num_of_lane  : 9   ;
+        UINT32    det_sp_change         : 1   ;
+        UINT32    config_phy_tx_sw      : 1   ;
+        UINT32    config_tx_comp_rcv_bit  : 1   ;
+        UINT32    set_emp_level         : 1   ;
+        UINT32    Reserved_120          : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagMiepPortlogic25
+{
+
+    struct
+    {
+        UINT32    remote_rd_req_size    : 3   ;
+        UINT32    Reserved_123          : 5   ;
+        UINT32    remote_max_brd_tag    : 8   ;
+        UINT32    Reserved_122          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagMiepPortlogic26
+{
+
+    struct
+    {
+        UINT32    resize_master_resp_compser  : 1   ;
+        UINT32    axi_ctrl1             : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagMiepPortlogic54
+{
+
+    struct
+    {
+        UINT32    region_index          : 4   ;
+        UINT32    Reserved_124          : 27  ;
+        UINT32    iatu_view             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagMiepPortlogic55
+{
+
+    struct
+    {
+        UINT32    iatu1_type            : 5   ;
+        UINT32    iatu1_tc              : 3   ;
+        UINT32    iatu1_td              : 1   ;
+        UINT32    iatu1_attr            : 2   ;
+        UINT32    Reserved_128          : 5   ;
+        UINT32    iatu1_at              : 2   ;
+        UINT32    Reserved_127          : 2   ;
+        UINT32    iatu1_id              : 3   ;
+        UINT32    Reserved_126          : 9   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagMiepPortlogic56
+{
+
+    struct
+    {
+        UINT32    iatu2_type            : 8   ;
+        UINT32    iatu2_bar_num         : 3   ;
+        UINT32    Reserved_132          : 3   ;
+        UINT32    iatu2_tc_match_en     : 1   ;
+        UINT32    iatu2_td_match_en     : 1   ;
+        UINT32    iatu2_attr_match_en   : 1   ;
+        UINT32    Reserved_131          : 1   ;
+        UINT32    iatu2_at_match_en     : 1   ;
+        UINT32    iatu2_func_num_match_en  : 1   ;
+        UINT32    iatu2_virtual_func_num_match_en  : 1   ;
+        UINT32    message_code_match_en  : 1   ;
+        UINT32    Reserved_130          : 2   ;
+        UINT32    iatu2_response_code   : 2   ;
+        UINT32    Reserved_129          : 1   ;
+        UINT32    iatu2_fuzzy_type_match_mode  : 1   ;
+        UINT32    iatu2_cfg_shift_mode  : 1   ;
+        UINT32    iatu2_ivert_mode      : 1   ;
+        UINT32    iatu2_match_mode      : 1   ;
+        UINT32    iatu2_region_en       : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagMiepPortlogic57
+{
+
+    struct
+    {
+        UINT32    iatu_start_low        : 12  ;
+        UINT32    iatu_start_high       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagMiepPortlogic59
+{
+
+    struct
+    {
+        UINT32    iatu_limit_low        : 12  ;
+        UINT32    iatu_limit_high       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagMiepPortlogic60
+{
+
+    struct
+    {
+        UINT32    xlated_addr_high      : 12  ;
+        UINT32    xlated_addr_low       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagMiepPortlogic62
+{
+
+    struct
+    {
+        UINT32    dma_wr_eng_en         : 1   ;
+        UINT32    dma_wr_ena            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagMiepPortlogic63
+{
+
+    struct
+    {
+        UINT32    wr_doorbell_num       : 3   ;
+        UINT32    Reserved_134          : 28  ;
+        UINT32    dma_wr_dbell_stop     : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagMiepPortlogic64
+{
+
+    struct
+    {
+        UINT32    dma_read_eng_en       : 1   ;
+        UINT32    Reserved_135          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagMiepPortlogic65
+{
+
+    struct
+    {
+        UINT32    rd_doorbell_num       : 3   ;
+        UINT32    Reserved_137          : 28  ;
+        UINT32    dma_rd_dbell_stop     : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagMiepPortlogic66
+{
+
+    struct
+    {
+        UINT32    done_int_status       : 8   ;
+        UINT32    Reserved_139          : 8   ;
+        UINT32    abort_int_status      : 8   ;
+        UINT32    Reserved_138          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagMiepPortlogic67
+{
+
+    struct
+    {
+        UINT32    done_int_mask         : 8   ;
+        UINT32    Reserved_142          : 8   ;
+        UINT32    abort_int_mask        : 8   ;
+        UINT32    Reserved_141          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagMiepPortlogic68
+{
+
+    struct
+    {
+        UINT32    done_int_clr          : 8   ;
+        UINT32    Reserved_145          : 8   ;
+        UINT32    abort_int_clr         : 8   ;
+        UINT32    Reserved_144          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagMiepPortlogic69
+{
+
+    struct
+    {
+        UINT32    app_rd_err_det        : 8   ;
+        UINT32    Reserved_147          : 8   ;
+        UINT32    ll_element_fetch_err_det  : 8   ;
+        UINT32    Reserved_146          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagMiepPortlogic74
+{
+
+    struct
+    {
+        UINT32    dma_wr_c0_imwr_data   : 16  ;
+        UINT32    dma_wr_c1_imwr_data   : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagMiepPortlogic75
+{
+
+    struct
+    {
+        UINT32    wr_ch_ll_remote_abort_int_en  : 8   ;
+        UINT32    Reserved_149          : 8   ;
+        UINT32    wr_ch_ll_local_abort_int_en  : 8   ;
+        UINT32    Reserved_148          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagMiepPortlogic76
+{
+
+    struct
+    {
+        UINT32    done_int_status       : 8   ;
+        UINT32    Reserved_152          : 8   ;
+        UINT32    abort_int_status      : 8   ;
+        UINT32    Reserved_151          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagMiepPortlogic77
+{
+
+    struct
+    {
+        UINT32    done_int_mask         : 8   ;
+        UINT32    Reserved_154          : 8   ;
+        UINT32    abort_int_mask        : 8   ;
+        UINT32    dma_rd_int_mask       : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagMiepPortlogic78
+{
+
+    struct
+    {
+        UINT32    done_int_clr          : 8   ;
+        UINT32    Reserved_156          : 8   ;
+        UINT32    abort_int_clr         : 8   ;
+        UINT32    dma_rd_int_clr        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagMiepPortlogic79
+{
+
+    struct
+    {
+        UINT32    app_wr_err_det        : 8   ;
+        UINT32    Reserved_157          : 8   ;
+        UINT32    link_list_fetch_err_det  : 8   ;
+        UINT32    dma_rd_err_low        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagMiepPortlogic80
+{
+
+    struct
+    {
+        UINT32    unspt_request         : 8   ;
+        UINT32    completer_abort       : 8   ;
+        UINT32    cpl_time_out          : 8   ;
+        UINT32    dma_rd_err_high       : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagMiepPortlogic81
+{
+
+    struct
+    {
+        UINT32    remote_abort_int_en   : 8   ;
+        UINT32    Reserved_159          : 8   ;
+        UINT32    local_abort_int_en    : 8   ;
+        UINT32    dma_rd_ll_err_ena     : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagMiepPortlogic86
+{
+
+    struct
+    {
+        UINT32    channel_dir           : 3   ;
+        UINT32    Reserved_162          : 28  ;
+        UINT32    dma_ch_con_idx        : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagMiepPortlogic87
+{
+
+    struct
+    {
+        UINT32    cycle_bit             : 1   ;
+        UINT32    toggle_cycle_bit      : 1   ;
+        UINT32    load_link_pointer     : 1   ;
+        UINT32    local_int_en          : 1   ;
+        UINT32    remote_int_en         : 1   ;
+        UINT32    channel_status        : 2   ;
+        UINT32    Reserved_166          : 1   ;
+        UINT32    consumer_cycle_state  : 1   ;
+        UINT32    linked_list_en        : 1   ;
+        UINT32    Reserved_165          : 2   ;
+        UINT32    func_num_dma          : 5   ;
+        UINT32    Reserved_164          : 7   ;
+        UINT32    no_snoop              : 1   ;
+        UINT32    ro                    : 1   ;
+        UINT32    td                    : 1   ;
+        UINT32    tc                    : 3   ;
+        UINT32    dma_ch_ctrl           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagMiepPortlogic93
+{
+
+    struct
+    {
+        UINT32    Reserved_168          : 2   ;
+        UINT32    dma_ll_ptr_low        : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_MIEP_PORTLOGIC93_U;
+
+
+
+#define PCIE_IEP_BASE                             (0x00000000)
+
+
+
+
+#define PCIE_IEP_DEVICE_VENDOR_ID_REG             (PCIE_IEP_BASE + 0x0)
+#define PCIE_IEP_PCISTS_PCICMD_REG                (PCIE_IEP_BASE + 0x4)
+#define PCIE_IEP_CCR_RID_REG                      (PCIE_IEP_BASE + 0x8)
+#define PCIE_IEP_PBAR01_BASE_LOWER_REG            (PCIE_IEP_BASE + 0x10)
+#define PCIE_IEP_PBAR01_BASE_UPPER_REG            (PCIE_IEP_BASE + 0x14)
+#define PCIE_IEP_PBAR23_BASE_LOWER_REG            (PCIE_IEP_BASE + 0x18)
+#define PCIE_IEP_PBAR23_BASE_UPPER_REG            (PCIE_IEP_BASE + 0x1C)
+#define PCIE_IEP_PBAR45_BASE_LOWER_REG            (PCIE_IEP_BASE + 0x20)
+#define PCIE_IEP_PBAR45_BASE_UPPER_REG            (PCIE_IEP_BASE + 0x24)
+#define PCIE_IEP_CARDBUSCISPTR_REG                (PCIE_IEP_BASE + 0x28)
+#define PCIE_IEP_SUBSYSTEMID_REG                  (PCIE_IEP_BASE + 0x2C)
+#define PCIE_IEP_EXPANSIONROM_BASE_ADDR_REG       (PCIE_IEP_BASE + 0x30)
+#define PCIE_IEP_CAPPTR_REG                       (PCIE_IEP_BASE + 0x34)
+#define PCIE_IEP_INTERRUPT_REG                    (PCIE_IEP_BASE + 0x3C)
+#define PCIE_IEP_MSI_CAPABILITY_REGISTER_REG      (PCIE_IEP_BASE + 0x50)
+#define PCIE_IEP_MSI_LOWER32_BITADDRESS_REG       (PCIE_IEP_BASE + 0x54)
+#define PCIE_IEP_MSI_UPPER32_BIT_ADDRESS_REG      (PCIE_IEP_BASE + 0x58)
+#define PCIE_IEP_MSI_DATA_REG                     (PCIE_IEP_BASE + 0x5C)
+#define PCIE_IEP_MSI_MASK_REG                     (PCIE_IEP_BASE + 0x60)
+#define PCIE_IEP_MSI_PENDING_REG                  (PCIE_IEP_BASE + 0x64)
+#define PCIE_IEP_PCIE_CAPABILITY_REGISTER_REG     (PCIE_IEP_BASE + 0x70)
+#define PCIE_IEP_DEVICE_CAPABILITIES_REGISTER_REG  (PCIE_IEP_BASE + 0x74)
+#define PCIE_IEP_DEVICE_STATUS_REGISTER_REG       (PCIE_IEP_BASE + 0x78)
+#define PCIE_IEP_LINK_CAPABILITY_REG              (PCIE_IEP_BASE + 0x7C)
+#define PCIE_IEP_LINK_CONTROL_STATUS_REG          (PCIE_IEP_BASE + 0x80)
+#define PCIE_IEP_AER_CAP_HEADER_REG               (PCIE_IEP_BASE + 0x100)
+#define PCIE_IEP_UC_ERROR_STATUS_REG              (PCIE_IEP_BASE + 0x104)
+#define PCIE_IEP_UC_ERROR_MASK_REG                (PCIE_IEP_BASE + 0x108)
+#define PCIE_IEP_UC_ERROR_SEVERITY_REG            (PCIE_IEP_BASE + 0x10C)
+#define PCIE_IEP_C_ERROR_STATUS_REG               (PCIE_IEP_BASE + 0x110)
+#define PCIE_IEP_C_ERROR_MASK_REG                 (PCIE_IEP_BASE + 0x114)
+#define PCIE_IEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG  (PCIE_IEP_BASE + 0x118)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_1_REG       (PCIE_IEP_BASE + 0x11C)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_2_REG       (PCIE_IEP_BASE + 0x120)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_3_REG       (PCIE_IEP_BASE + 0x124)
+#define PCIE_IEP_HEADER_LOG_REGISTERS_4_REG       (PCIE_IEP_BASE + 0x128)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_1_REG    (PCIE_IEP_BASE + 0x130)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_2_REG    (PCIE_IEP_BASE + 0x134)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_3_REG    (PCIE_IEP_BASE + 0x138)
+#define PCIE_IEP_TLP_PREFIX_LOGREGISTERS_4_REG    (PCIE_IEP_BASE + 0x13C)
+#define PCIE_IEP_NTB_IEP_CFG_SPACE_LOWER_REG      (PCIE_IEP_BASE + 0x700)
+#define PCIE_IEP_NTB_IEP_CFG_SPACE_UPPER_REG      (PCIE_IEP_BASE + 0x704)
+#define PCIE_IEP_NTB_IEP_BAR01_CTRL_REG           (PCIE_IEP_BASE + 0x708)
+#define PCIE_IEP_NTB_IEP_BAR23_CTRL_REG           (PCIE_IEP_BASE + 0x70C)
+#define PCIE_IEP_NTB_IEP_BAR45_CTRL_REG           (PCIE_IEP_BASE + 0x710)
+#define PCIE_IEP_MSI_CTRL_ADDRESS_LOWER_REG       (PCIE_IEP_BASE + 0x714)
+#define PCIE_IEP_MSI_CTRL_ADDRESS_UPPER_REG       (PCIE_IEP_BASE + 0x718)
+#define PCIE_IEP_MSI_CTRL_INT_EN_REG              (PCIE_IEP_BASE + 0x71C)
+#define PCIE_IEP_MSI_CTRL_INT0_MASK_REG           (PCIE_IEP_BASE + 0x720)
+#define PCIE_IEP_MSI_CTRL_INT_STATUS_REG          (PCIE_IEP_BASE + 0x724)
+
+
+
+typedef union tagIepDeviceVendorId
+{
+
+    struct
+    {
+        UINT32    Vendor_ID             : 16  ;
+        UINT32    Device_ID             : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_DEVICE_VENDOR_ID_U;
+
+
+
+
+typedef union tagIepPcistsPcicmd
+{
+
+    struct
+    {
+        UINT32    IO_Space_Enable       : 1   ;
+        UINT32    Memory_Space_Enable   : 1   ;
+        UINT32    Bus_Master_Enable     : 1   ;
+        UINT32    SpecialCycleEnable    : 1   ;
+        UINT32    Memory_Write_and_Invalidate  : 1   ;
+        UINT32    VGA_palette_snoop_Enable  : 1   ;
+        UINT32    Parity_Error_Response  : 1   ;
+        UINT32    IDSEL_Stepping_WaitCycle_Control  : 1   ;
+        UINT32    SERR_Enable           : 1   ;
+        UINT32    FastBack_to_BackEnable  : 1   ;
+        UINT32    Interrupt_Disable     : 1   ;
+        UINT32    Reserved_2            : 5   ;
+        UINT32    Reserved_1            : 3   ;
+        UINT32    INTx_Status           : 1   ;
+        UINT32    CapabilitiesList      : 1   ;
+        UINT32    pcibus66MHzcapable    : 1   ;
+        UINT32    Reserved_0            : 1   ;
+        UINT32    FastBack_to_Back      : 1   ;
+        UINT32    MasterDataParityError  : 1   ;
+        UINT32    DEVSEL_Timing         : 2   ;
+        UINT32    Signaled_Target_Abort  : 1   ;
+        UINT32    Received_Target_Abort  : 1   ;
+        UINT32    Received_Master_Abort  : 1   ;
+        UINT32    Signaled_System_Error  : 1   ;
+        UINT32    Detected_Parity_Error  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_PCISTS_PCICMD_U;
+
+
+
+
+typedef union tagIepCcrRid
+{
+
+    struct
+    {
+        UINT32    Revision_Identification  : 8   ;
+        UINT32    Reserved_3            : 8   ;
+        UINT32    Sub_Class             : 8   ;
+        UINT32    BaseClass             : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_CCR_RID_U;
+
+
+
+
+typedef union tagIepPbar01BaseLower
+{
+
+    struct
+    {
+        UINT32    BAR01_Space_Inicator  : 1   ;
+        UINT32    BAR01_Type            : 2   ;
+        UINT32    BAR01_Prefetchable    : 1   ;
+        UINT32    Reserved_4            : 12  ;
+        UINT32    pbar01_lower          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_PBAR01_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepPbar23BaseLower
+{
+
+    struct
+    {
+        UINT32    pbar23_space_inicator  : 1   ;
+        UINT32    pbar23_type           : 2   ;
+        UINT32    pbar23_prefetchable   : 1   ;
+        UINT32    Reserved_6            : 8   ;
+        UINT32    pbar23_lower          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_PBAR23_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepPbar45BaseLower
+{
+
+    struct
+    {
+        UINT32    pbar45_space_inicator  : 1   ;
+        UINT32    pbar45_type           : 2   ;
+        UINT32    pbar45_prefetchable   : 1   ;
+        UINT32    Reserved_7            : 8   ;
+        UINT32    pbar45_lower          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_PBAR45_BASE_LOWER_U;
+
+
+
+
+typedef union tagIepSubsystemid
+{
+
+    struct
+    {
+        UINT32    SubsystemID           : 16  ;
+        UINT32    SubsystemVendorID     : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_SubSystemId_U;
+
+
+
+
+typedef union tagIepCapptr
+{
+
+    struct
+    {
+        UINT32    CapPtr                : 8   ;
+        UINT32    Reserved_10           : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_CapPtr_U;
+
+
+
+
+typedef union tagIepInterrupt
+{
+
+    struct
+    {
+        UINT32    Interrupt_Line        : 8   ;
+        UINT32    Interrupt_Pin         : 8   ;
+        UINT32    Min_Grant             : 8   ;
+        UINT32    Max_Latency           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_Interrupt_U;
+
+
+
+
+typedef union tagIepMsiCapabilityRegister
+{
+
+    struct
+    {
+        UINT32    CapabilityID          : 8   ;
+        UINT32    Next_Capability_Pointer  : 8   ;
+        UINT32    MSI_Enabled           : 1   ;
+        UINT32    Multiple_Message_Capable  : 3   ;
+        UINT32    Multiple_Message_Enabled  : 3   ;
+        UINT32    MSI_64_EN             : 1   ;
+        UINT32    PVM_EN                : 1   ;
+        UINT32    Message_Control_Register  : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_MSI_Capability_Register_U;
+
+
+
+
+typedef union tagIepMsiLower32Bitaddress
+{
+
+    struct
+    {
+        UINT32    Reserved_13           : 2   ;
+        UINT32    Lower32_bitAddress    : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_MSI_Lower32_bitAddress_U;
+
+
+
+
+typedef union tagIepMsiData
+{
+
+    struct
+    {
+        UINT32    MSI_Data              : 16  ;
+        UINT32    Reserved_14           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_MSI_Data_U;
+
+
+
+
+typedef union tagIepMsiMask
+{
+
+    struct
+    {
+        UINT32    MsiMask               : 1   ;
+        UINT32    Reserved_15           : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_MSI_MASK_U;
+
+
+
+
+typedef union tagIepMsiPending
+{
+
+    struct
+    {
+        UINT32    MsiPending            : 1   ;
+        UINT32    Reserved_16           : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_MSI_Pending_U;
+
+
+
+
+typedef union tagIepPcieCapabilityRegister
+{
+
+    struct
+    {
+        UINT32    Capability_ID         : 8   ;
+        UINT32    Next_Capability_Pointer  : 8   ;
+        UINT32    PCIE_Capability_Version  : 4   ;
+        UINT32    Device_Port_Type      : 4   ;
+        UINT32    Slot_Implemented      : 1   ;
+        UINT32    Interrupt_Message_Number  : 5   ;
+        UINT32    Reserved_17           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_PCIE_Capability_Register_U;
+
+
+
+
+typedef union tagIepDeviceCapabilitiesRegister
+{
+
+    struct
+    {
+        UINT32    Max_Payload_Size_Supported  : 3   ;
+        UINT32    Phantom_Function_Supported  : 2   ;
+        UINT32    Extended_TagField_Supported  : 1   ;
+        UINT32    Endpoint_L0sAcceptable_Latency  : 3   ;
+        UINT32    Endpoint_L1Acceptable_Latency  : 3   ;
+        UINT32    Undefined             : 3   ;
+        UINT32    Reserved_20           : 3   ;
+        UINT32    Captured_Slot_Power_Limit_Value  : 8   ;
+        UINT32    Captured_Slot_Power_Limit_Scale  : 2   ;
+        UINT32    Function_Level_Reset  : 1   ;
+        UINT32    Reserved_19           : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_Device_Capabilities_Register_U;
+
+
+
+
+typedef union tagIepDeviceStatusRegister
+{
+
+    struct
+    {
+        UINT32    Correctable_Error_Reporting_Enable  : 1   ;
+        UINT32    Non_Fatal_Error_Reporting_Enable  : 1   ;
+        UINT32    Fatal_Error_Reporting_Enable  : 1   ;
+        UINT32    UREnable              : 1   ;
+        UINT32    Enable_Relaxed_Ordering  : 1   ;
+        UINT32    Max_Payload_Size      : 3   ;
+        UINT32    Extended_TagFieldEnable  : 1   ;
+        UINT32    Phantom_Function_Enable  : 1   ;
+        UINT32    AUXPowerPMEnable      : 1   ;
+        UINT32    EnableNoSnoop         : 1   ;
+        UINT32    Max_Read_Request_Size  : 3   ;
+        UINT32    Reserved_22           : 1   ;
+        UINT32    CorrectableErrorDetected  : 1   ;
+        UINT32    Non_FatalErrordetected  : 1   ;
+        UINT32    FatalErrorDetected    : 1   ;
+        UINT32    UnsupportedRequestDetected  : 1   ;
+        UINT32    AuxPowerDetected      : 1   ;
+        UINT32    TransactionPending    : 1   ;
+        UINT32    Reserved_21           : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_Device_Status_Register_U;
+
+
+
+
+typedef union tagIepLinkCapability
+{
+
+    struct
+    {
+        UINT32    Max_Link_Speed        : 4   ;
+        UINT32    Max_Link_Width        : 6   ;
+        UINT32    Active_State_Power_Management  : 2   ;
+        UINT32    L0s_ExitLatency       : 3   ;
+        UINT32    L1_Exit_Latency       : 3   ;
+        UINT32    Clock_Power_Management  : 1   ;
+        UINT32    Surprise_Down_Error_Report_Cap  : 1   ;
+        UINT32    Data_Link_Layer_Active_Report_Cap  : 1   ;
+        UINT32    Link_Bandwidth_Noti_Cap  : 1   ;
+        UINT32    ASPM_Option_Compliance  : 1   ;
+        UINT32    Reserved_23           : 1   ;
+        UINT32    Port_Number           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_Link_Capability_U;
+
+
+
+
+typedef union tagIepLinkControlStatus
+{
+
+    struct
+    {
+        UINT32    Active_State_Power_Management  : 2   ;
+        UINT32    Reserved_26           : 1   ;
+        UINT32    RCB                   : 1   ;
+        UINT32    Link_Disable          : 1   ;
+        UINT32    Retrain_Link          : 1   ;
+        UINT32    Common_Clock_Config   : 1   ;
+        UINT32    Extended_Sync         : 1   ;
+        UINT32    Enable_Clock_Pwr_Management  : 1   ;
+        UINT32    Hw_Auto_Width_Disable  : 1   ;
+        UINT32    Link_Bandwidth_Management_Int_En  : 1   ;
+        UINT32    Link_Auto_Bandwidth_Int_En  : 1   ;
+        UINT32    Reserved_25           : 4   ;
+        UINT32    current_link_speed    : 4   ;
+        UINT32    negotiated_link_width  : 6   ;
+        UINT32    Reserved_24           : 1   ;
+        UINT32    link_training         : 1   ;
+        UINT32    slot_clock_config     : 1   ;
+        UINT32    data_link_layer_active  : 1   ;
+        UINT32    link_bandwidth_management_status  : 1   ;
+        UINT32    link_auto_bandwidth_status  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_Link_Control_Status_U;
+
+
+
+
+typedef union tagIepAerCapHeader
+{
+
+    struct
+    {
+        UINT32    PCIE_Extended_Capability_ID  : 16  ;
+        UINT32    Capability_Version    : 4   ;
+        UINT32    Next_Capability_Offset  : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_AER_Cap_header_U;
+
+
+
+
+typedef union tagIepUcErrorStatus
+{
+
+    struct
+    {
+        UINT32    Reserved_31           : 1   ;
+        UINT32    Reserved_30           : 3   ;
+        UINT32    DataLinkProtocolErrorStatus  : 1   ;
+        UINT32    SurpriseDownErrorStatus  : 1   ;
+        UINT32    Reserved_29           : 6   ;
+        UINT32    PoisonedTLPStatus     : 1   ;
+        UINT32    FlowControlProtocolErrorStatus  : 1   ;
+        UINT32    CompletionTimeoutStatus  : 1   ;
+        UINT32    CompleterAbortStatus  : 1   ;
+        UINT32    UnexpectedCompletionStatus  : 1   ;
+        UINT32    ReceiverOverflowStatus  : 1   ;
+        UINT32    MalformedTLPStatus    : 1   ;
+        UINT32    ECRCErrorStatus       : 1   ;
+        UINT32    UnsupportedRequestErrorStatus  : 1   ;
+        UINT32    Reserved_28           : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_UC_Error_Status_U;
+
+
+
+
+typedef union tagIepUcErrorMask
+{
+
+    struct
+    {
+        UINT32    Reserved_35           : 1   ;
+        UINT32    Reserved_34           : 3   ;
+        UINT32    DataLinkProtocolErrorMask  : 1   ;
+        UINT32    SurpriseDownErrorMask  : 1   ;
+        UINT32    Reserved_33           : 6   ;
+        UINT32    PoisonedTLPMask       : 1   ;
+        UINT32    FlowControlProtocolErrorMask  : 1   ;
+        UINT32    CompletionTimeoutMask  : 1   ;
+        UINT32    CompleterAbortMask    : 1   ;
+        UINT32    UnexpectedCompletionMask  : 1   ;
+        UINT32    ReceiverOverflowMask  : 1   ;
+        UINT32    MalformedTLPMask      : 1   ;
+        UINT32    ECRCErrorMask         : 1   ;
+        UINT32    UnsupportedRequestErrorMask  : 1   ;
+        UINT32    Reserved_32           : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_UC_Error_Mask_U;
+
+
+
+
+typedef union tagIepUcErrorSeverity
+{
+
+    struct
+    {
+        UINT32    Reserved_39           : 1   ;
+        UINT32    Reserved_38           : 3   ;
+        UINT32    DataLinkProtocolErrorSeverity  : 1   ;
+        UINT32    SurpriseDownErrorSeverity  : 1   ;
+        UINT32    Reserved_37           : 6   ;
+        UINT32    PoisonedTLPSeverity   : 1   ;
+        UINT32    FlowControlProtocolErrorSeverity  : 1   ;
+        UINT32    CompletionTimeoutSeverity  : 1   ;
+        UINT32    CompleterAbortSeverity  : 1   ;
+        UINT32    UnexpectedCompletionSeverity  : 1   ;
+        UINT32    ReceiverOverflowSeverity  : 1   ;
+        UINT32    MalformedTLPSeverity  : 1   ;
+        UINT32    ECRCErrorSeverity     : 1   ;
+        UINT32    UnsupportedRequestErrorSeverity  : 1   ;
+        UINT32    Reserved_36           : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_UC_Error_Severity_U;
+
+
+
+
+typedef union tagIepCErrorStatus
+{
+
+    struct
+    {
+        UINT32    Receiver_Error_Status  : 1   ;
+        UINT32    Reserved_42           : 5   ;
+        UINT32    Bad_TLP_Status        : 1   ;
+        UINT32    Bad_DLLP_Status       : 1   ;
+        UINT32    REPLAY_NUM_Rollover_Status  : 1   ;
+        UINT32    Reserved_41           : 3   ;
+        UINT32    Replay_Timer_Timeout_Status  : 1   ;
+        UINT32    Advisory_Non_Fatal_Error_Status  : 1   ;
+        UINT32    Reserved_40           : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_C_Error_Status_U;
+
+
+
+
+typedef union tagIepCErrorMask
+{
+
+    struct
+    {
+        UINT32    Receiver_Error_Mask   : 1   ;
+        UINT32    Reserved_45           : 5   ;
+        UINT32    Bad_TLP_Mask          : 1   ;
+        UINT32    Bad_DLLP_Mask         : 1   ;
+        UINT32    REPLAY_NUMRollover_Mask  : 1   ;
+        UINT32    Reserved_44           : 3   ;
+        UINT32    Replay_Timer_Timeout_Mask  : 1   ;
+        UINT32    Advisory_Non_Fatal_Error_Mask  : 1   ;
+        UINT32    Reserved_43           : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_C_Error_Mask_U;
+
+
+
+
+typedef union tagIepAdvancedErrorCapabilitiesAndControl
+{
+
+    struct
+    {
+        UINT32    First_Error_Pointer   : 5   ;
+        UINT32    ECRC_Generation_Capability  : 1   ;
+        UINT32    ECRC_Generation_Enable  : 1   ;
+        UINT32    ECRC_Check_Capable    : 1   ;
+        UINT32    ECRC_Check_Enable     : 1   ;
+        UINT32    Reserved_47           : 2   ;
+        UINT32    TLP_Prefix_Log_Present  : 1   ;
+        UINT32    Reserved_46           : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_Advanced_Error_Capabilities_and_Control_U;
+
+
+
+
+typedef union tagIepNtbIepBar01Ctrl
+{
+
+    struct
+    {
+        UINT32    bar01_type            : 5   ;
+        UINT32    bar01_tc              : 3   ;
+        UINT32    bar01_td              : 1   ;
+        UINT32    bar01_attr            : 2   ;
+        UINT32    Reserved_51           : 5   ;
+        UINT32    bar01_at              : 2   ;
+        UINT32    bar01_match_en        : 1   ;
+        UINT32    Reserved_50           : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR01_CTRL_U;
+
+
+
+
+typedef union tagIepNtbIepBar23Ctrl
+{
+
+    struct
+    {
+        UINT32    bar23_type            : 5   ;
+        UINT32    bar23_tc              : 3   ;
+        UINT32    bar23_td              : 1   ;
+        UINT32    bar23_attr            : 2   ;
+        UINT32    Reserved_53           : 5   ;
+        UINT32    bar23_at              : 2   ;
+        UINT32    bar23_match_en        : 1   ;
+        UINT32    Reserved_52           : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR23_CTRL_U;
+
+
+
+
+typedef union tagIepNtbIepBar45Ctrl
+{
+
+    struct
+    {
+        UINT32    bar45_type            : 5   ;
+        UINT32    bar45_tc              : 3   ;
+        UINT32    bar45_td              : 1   ;
+        UINT32    bar45_attr            : 2   ;
+        UINT32    Reserved_55           : 5   ;
+        UINT32    bar45_at              : 2   ;
+        UINT32    bar45_match_en        : 1   ;
+        UINT32    Reserved_54           : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_NTB_IEP_BAR45_CTRL_U;
+
+
+
+
+typedef union tagIepMsiCtrlIntEn
+{
+
+    struct
+    {
+        UINT32    msi_int_en            : 1   ;
+        UINT32    Reserved_56           : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT_EN_U;
+
+
+
+
+typedef union tagIepMsiCtrlInt0Mask
+{
+
+    struct
+    {
+        UINT32    msi_int_mask          : 1   ;
+        UINT32    Reserved_57           : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT0_MASK_U;
+
+
+
+
+typedef union tagIepMsiCtrlIntStatus
+{
+
+    struct
+    {
+        UINT32    msi_int               : 1   ;
+        UINT32    Reserved_58           : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_IEP_MSI_CTRL_INT_STATUS_U;
+
+
+#define PCI_SYS_BASE           (0x00000000)
+
+
+
+
+#define PCIE_CTRL_0_REG  (PCI_SYS_BASE + 0xF8)
+#define PCIE_CTRL_1_REG  (PCI_SYS_BASE + 0xFC)
+#define PCIE_CTRL_2_REG  (PCI_SYS_BASE + 0x100)
+#define PCIE_CTRL_3_REG  (PCI_SYS_BASE + 0x104)
+#define PCIE_CTRL_4_REG  (PCI_SYS_BASE + 0x108)
+#define PCIE_CTRL_5_REG  (PCI_SYS_BASE + 0x10C)
+#define PCIE_CTRL_6_REG  (PCI_SYS_BASE + 0x110)
+#define PCIE_CTRL_7_REG  (PCI_SYS_BASE + 0x114)
+#define PCIE_CTRL_9_REG  (PCI_SYS_BASE + 0x11C)
+#define PCIE_CTRL_10_REG  (PCI_SYS_BASE + 0x120)
+#define PCIE_CTRL_11_REG  (PCI_SYS_BASE + 0x124)
+#define PCIE_SYS_CTRL12_REG  (PCI_SYS_BASE + 0x0)
+#define PCIE_SYS_CTRL13_REG  (PCI_SYS_BASE + 0x4)
+#define PCIE_SYS_CTRL14_REG  (PCI_SYS_BASE + 0x8)
+#define PCIE_SYS_CTRL15_REG  (PCI_SYS_BASE + 0xC)
+#define PCIE_SYS_CTRL16_REG  (PCI_SYS_BASE + 0x10)
+#define PCIE_SYS_CTRL17_REG  (PCI_SYS_BASE + 0x14)
+#define PCIE_SYS_CTRL18_REG  (PCI_SYS_BASE + 0x18)
+#define PCIE_SYS_CTRL19_REG  (PCI_SYS_BASE + 0x1C)
+#define PCIE_SYS_CTRL20_REG  (PCI_SYS_BASE + 0x20)
+#define PCIE_RD_TAB_SEL                                 BIT31
+#define PCIE_RD_TAB_EN                                  BIT30
+#define PCIE_SYS_CTRL21_REG  (PCI_SYS_BASE + 0x24)
+#define PCIE_SYS_CTRL22_REG  (PCI_SYS_BASE + 0x28)
+#define PCIE_SYS_CTRL23_REG  (PCI_SYS_BASE + 0x2C)
+#define PCIE_SYS_CTRL24_REG  (PCI_SYS_BASE + 0x1b4)
+#define PCIE_SYS_CTRL28_REG  (PCI_SYS_BASE + 0x1c4)
+#define PCIE_SYS_CTRL29_REG  (PCI_SYS_BASE + 0x1c8)
+#define PCIE_SYS_CTRL54_REG  (PCI_SYS_BASE + 0x274)
+#define PCIE_SYS_STATE5_REG  (PCI_SYS_BASE + 0x30)
+#define PCIE_SYS_STATE6_REG  (PCI_SYS_BASE + 0x34)
+#define PCIE_SYS_STATE7_REG  (PCI_SYS_BASE + 0x38)
+#define PCIE_SYS_STATE8_REG  (PCI_SYS_BASE + 0x3C)
+#define PCIE_SYS_STATE9_REG  (PCI_SYS_BASE + 0x40)
+#define PCIE_SYS_STATE10_REG  (PCI_SYS_BASE + 0x44)
+#define PCIE_SYS_STATE11_REG  (PCI_SYS_BASE + 0x48)
+#define PCIE_SYS_STATE12_REG  (PCI_SYS_BASE + 0x4C)
+#define PCIE_SYS_STATE13_REG  (PCI_SYS_BASE + 0x50)
+#define PCIE_SYS_STATE14_REG  (PCI_SYS_BASE + 0x54)
+#define PCIE_SYS_STATE15_REG  (PCI_SYS_BASE + 0x58)
+#define PCIE_SYS_STATE16_REG  (PCI_SYS_BASE + 0x5C)
+#define PCIE_SYS_STATE17_REG  (PCI_SYS_BASE + 0x60)
+#define PCIE_SYS_STATE18_REG  (PCI_SYS_BASE + 0x64)
+#define PCIE_SYS_STATE19_REG  (PCI_SYS_BASE + 0x68)
+#define PCIE_SYS_STATE20_REG  (PCI_SYS_BASE + 0x6C)
+#define PCIE_SYS_STATE21_REG  (PCI_SYS_BASE + 0x70)
+#define PCIE_SYS_STATE22_REG  (PCI_SYS_BASE + 0x74)
+#define PCIE_SYS_STATE23_REG  (PCI_SYS_BASE + 0x78)
+#define PCIE_SYS_STATE24_REG  (PCI_SYS_BASE + 0x7C)
+#define PCIE_SYS_STATE25_REG  (PCI_SYS_BASE + 0x80)
+#define PCIE_SYS_STATE26_REG  (PCI_SYS_BASE + 0x84)
+#define PCIE_SYS_STATE27_REG  (PCI_SYS_BASE + 0x88)
+#define PCIE_SYS_STATE28_REG  (PCI_SYS_BASE + 0x8C)
+#define PCIE_SYS_STATE29_REG  (PCI_SYS_BASE + 0x90)
+#define PCIE_SYS_STATE30_REG  (PCI_SYS_BASE + 0x94)
+#define PCIE_SYS_STATE31_REG  (PCI_SYS_BASE + 0x98)
+#define PCIE_SYS_STATE32_REG  (PCI_SYS_BASE + 0x9C)
+#define PCIE_SYS_STATE33_REG  (PCI_SYS_BASE + 0xA0)
+#define PCIE_SYS_STATE34_REG  (PCI_SYS_BASE + 0xA4)
+#define PCIE_SYS_STATE35_REG  (PCI_SYS_BASE + 0xA8)
+#define PCIE_SYS_STATE36_REG  (PCI_SYS_BASE + 0xAC)
+#define PCIE_SYS_STATE37_REG  (PCI_SYS_BASE + 0xB0)
+#define PCIE_SYS_STATE38_REG  (PCI_SYS_BASE + 0xB4)
+#define PCIE_SYS_STATE39_REG  (PCI_SYS_BASE + 0xB8)
+#define PCIE_SYS_STATE40_REG  (PCI_SYS_BASE + 0xBC)
+#define PCIE_SYS_STATE41_REG  (PCI_SYS_BASE + 0xC0)
+#define PCIE_SYS_STATE42_REG  (PCI_SYS_BASE + 0xC4)
+#define PCIE_SYS_STATE43_REG  (PCI_SYS_BASE + 0xC8)
+#define PCIE_SYS_STATE44_REG  (PCI_SYS_BASE + 0xCC)
+#define PCIE_SYS_STATE45_REG  (PCI_SYS_BASE + 0xD0)
+#define PCIE_SYS_STATE46_REG  (PCI_SYS_BASE + 0xD4)
+#define PCIE_SYS_STATE47_REG  (PCI_SYS_BASE + 0xD8)
+#define PCIE_SYS_STATE48_REG  (PCI_SYS_BASE + 0xDC)
+#define PCIE_SYS_STATE49_REG  (PCI_SYS_BASE + 0xE0)
+#define PCIE_SYS_STATE50_REG  (PCI_SYS_BASE + 0xE4)
+#define PCIE_SYS_STATE51_REG  (PCI_SYS_BASE + 0xE8)
+#define PCIE_SYS_STATE52_REG  (PCI_SYS_BASE + 0xEC)
+#define PCIE_SYS_STATE53_REG  (PCI_SYS_BASE + 0xF0)
+#define PCIE_SYS_STATE54_REG  (PCI_SYS_BASE + 0xF4)
+#define PCIE_STAT_0_REG  (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_1_REG  (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_2_REG  (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_3_REG  (PCI_SYS_BASE + 0x0)
+#define PCIE_STAT_4_REG  (PCI_SYS_BASE + 0x0)
+
+
+
+typedef union tagPcieCtrl0
+{
+
+    struct
+    {
+        UINT32    pcie2_slv_awmisc_info  : 22  ;
+        UINT32    pcie2_slv_resp_err_map  : 6   ;
+        UINT32    pcie2_slv_device_type  : 4   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_CTRL_0_U;
+
+
+
+
+typedef union tagPcieCtrl1
+{
+
+    struct
+    {
+        UINT32    pcie2_slv_armisc_info  : 22  ;
+        UINT32    pcie2_common_clocks   : 1   ;
+        UINT32    pcie2_app_clk_req_n   : 1   ;
+        UINT32    pcie2_ven_msg_code    : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_CTRL_1_U;
+
+
+
+
+typedef union tagPcieCtrl2
+{
+
+    struct
+    {
+        UINT32    pcie2_mstr_bmisc_info  : 14  ;
+        UINT32    pcie2_mstr_rmisc_info  : 12  ;
+        UINT32    pcie2_ven_msi_req     : 1   ;
+        UINT32    pcie2_ven_msi_vector  : 5   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_CTRL_2_U;
+
+
+
+
+typedef union tagPcieCtrl3
+{
+
+    struct
+    {
+        UINT32    pcie2_ven_msg_req     : 1   ;
+        UINT32    pcie2_ven_msg_fmt     : 2   ;
+        UINT32    pcie2_ven_msg_type    : 5   ;
+        UINT32    pcie2_ven_msg_td      : 1   ;
+        UINT32    pcie2_ven_msg_ep      : 1   ;
+        UINT32    pcie2_ven_msg_attr    : 2   ;
+        UINT32    pcie2_ven_msg_len     : 10  ;
+        UINT32    pcie2_ven_msg_tag     : 8   ;
+        UINT32    pcie_mstr_rresp_int_enable  : 1   ;
+        UINT32    pcie_mstr_bresp_int_enable  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_CTRL_3_U;
+
+
+
+
+typedef union tagPcieCtrl7
+{
+
+    struct
+    {
+        UINT32    pcie2_app_init_rst    : 1   ;
+        UINT32    pcie2_app_req_entr_l1  : 1   ;
+        UINT32    pcie2_app_ready_entr_l23  : 1   ;
+        UINT32    pcie2_app_req_exit_l1  : 1   ;
+        UINT32    pcie2_app_req_retry_en  : 1   ;
+        UINT32    pcie2_sys_int         : 1   ;
+        UINT32    pcie2_outband_pwrup_cmd  : 1   ;
+        UINT32    pcie2_app_unlock_msg  : 1   ;
+        UINT32    pcie2_apps_pm_xmt_turnoff  : 1   ;
+        UINT32    pcie2_apps_pm_xmt_pme  : 1   ;
+        UINT32    pcie2_sys_aux_pwr_det  : 1   ;
+        UINT32    pcie2_app_ltssm_enable  : 1   ;
+        UINT32    pcie2_cfg_pwr_ctrler_ctrl_pol  : 1   ;
+        UINT32    Reserved_7            : 1   ;
+        UINT32    pcie2_sys_mrl_sensor_state  : 1   ;
+        UINT32    pcie2_sys_pwr_fault_det  : 1   ;
+        UINT32    pcie2_sys_mrl_sensor_chged  : 1   ;
+        UINT32    Reserved_6            : 1   ;
+        UINT32    pcie2_sys_cmd_cpled_int  : 1   ;
+        UINT32    pcie2_sys_eml_interlock_engaged  : 1   ;
+        UINT32    pcie2_cfg_l1_clk_removal_en  : 1   ;
+        UINT32    pcie0_int_ctrl        : 8   ;
+        UINT32    pcie_linkdown_auto_rstn_enable  : 1   ;
+        UINT32    pcie_err_bresp_enable  : 1   ;
+        UINT32    pcie_err_rresp_enable  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_CTRL_7_U;
+
+
+
+
+typedef union tagPcieCtrl9
+{
+
+    struct
+    {
+        UINT32    cfg_l1_aux_clk_switch_core_clk_gate_en  : 1   ;
+        UINT32    cfg_l1_mac_powerdown_override_to_p2_en  : 1   ;
+        UINT32    Reserved_9            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_CTRL_9_U;
+
+
+
+
+typedef union tagPcieCtrl10
+{
+
+    struct
+    {
+        UINT32    cfg_aer_rc_err_msi_mask  : 1   ;
+        UINT32    cfg_sys_err_rc_mask   : 1   ;
+        UINT32    radm_correctable_err_mask  : 1   ;
+        UINT32    radm_nonfatal_err_mask  : 1   ;
+        UINT32    radm_fatal_err_mask   : 1   ;
+        UINT32    radm_pm_pme_mask      : 1   ;
+        UINT32    radm_pm_to_ack_mask   : 1   ;
+        UINT32    ven_msi_int_mask      : 1   ;
+        UINT32    radm_cpl_timeout_mask  : 1   ;
+        UINT32    radm_msg_unlock_mask  : 1   ;
+        UINT32    cfg_pme_msi_mask      : 1   ;
+        UINT32    bridge_flush_not_mask  : 1   ;
+        UINT32    link_req_rst_not_mask  : 1   ;
+        UINT32    pcie_p2_exit_int_mask  : 1   ;
+        UINT32    pcie_rx_lane_flip_en_tmp  : 1   ;
+        UINT32    pcie_tx_lane_flip_en_tmp  : 1   ;
+        UINT32    radm_pm_turnoff_mask  : 1   ;
+        UINT32    Reserved_11           : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_CTRL_10_U;
+
+
+
+
+typedef union tagPcieCtrl11
+{
+
+    struct
+    {
+        UINT32    cfg_aer_rc_err_msi_clr  : 1   ;
+        UINT32    cfg_sys_err_rc_clr    : 1   ;
+        UINT32    radm_correctable_err_clr  : 1   ;
+        UINT32    radm_nonfatal_err_clr  : 1   ;
+        UINT32    radm_fatal_err_clr    : 1   ;
+        UINT32    radm_pm_pme_clr       : 1   ;
+        UINT32    radm_pm_to_ack_clr    : 1   ;
+        UINT32    ven_msi_int_clr       : 1   ;
+        UINT32    radm_cpl_timeout_clr  : 1   ;
+        UINT32    radm_msg_unlock_clr   : 1   ;
+        UINT32    cfg_pme_msi_clr       : 1   ;
+        UINT32    bridge_flush_not_clr  : 1   ;
+        UINT32    link_req_rst_not_clr  : 1   ;
+        UINT32    pcie_p2_exit_int_clr  : 1   ;
+        UINT32    pcie_slv_err_int_clr  : 1   ;
+        UINT32    pcie_mstr_err_int_clr  : 1   ;
+        UINT32    radm_pm_turnoff_clr   : 1   ;
+        UINT32    cfg_ntb_mode          : 1   ;
+        UINT32    Reserved_13           : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_CTRL_11_U;
+
+
+
+
+typedef union tagPcieSysCtrl12
+{
+
+    struct
+    {
+        UINT32    slv_awmisc_info_func_num  : 1   ;
+        UINT32    slv_awmisc_info_vfunc_active  : 1   ;
+        UINT32    slv_awmisc_info_vfunc_num  : 1   ;
+        UINT32    Reserved_17           : 1   ;
+        UINT32    slv_armisc_info_func_num  : 1   ;
+        UINT32    slv_armisc_info_vfunc_active  : 1   ;
+        UINT32    slv_armisc_info_vfunc_num  : 1   ;
+        UINT32    Reserved_16           : 1   ;
+        UINT32    slv_awmisc_info_nw    : 1   ;
+        UINT32    slv_awmisc_info_ats   : 2   ;
+        UINT32    slv_armisc_info_nw    : 1   ;
+        UINT32    slv_armisc_info_ats   : 2   ;
+        UINT32    mstr_bmisc_info_ats   : 2   ;
+        UINT32    mstr_rmisc_info_ats   : 2   ;
+        UINT32    pcie_rfs_ctrl         : 6   ;
+        UINT32    pcie_rft_ctrl         : 7   ;
+        UINT32    Reserved_15           : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_CTRL12_U;
+
+
+
+
+typedef union tagPcieSysCtrl16
+{
+
+    struct
+    {
+        UINT32    app_flr_pf_done       : 1   ;
+        UINT32    app_flr_vf_done       : 2   ;
+        UINT32    Reserved_23           : 5   ;
+        UINT32    ven_msi_vfunc_active  : 1   ;
+        UINT32    ven_msi_vfunc_num     : 1   ;
+        UINT32    ven_msg_vfunc_active  : 1   ;
+        UINT32    ven_msg_vfunc_num     : 1   ;
+        UINT32    Reserved_22           : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_CTRL16_U;
+
+
+
+
+typedef union tagPcieSysCtrl20
+{
+
+    struct
+    {
+        UINT32    ro_sel                : 1   ;
+        UINT32    dbi_func_num          : 1   ;
+        UINT32    dbi_vfunc_num         : 1   ;
+        UINT32    dbi_vfunc_active      : 1   ;
+        UINT32    dbi_addr_h20          : 20  ;
+        UINT32    dbi_bar_num           : 3   ;
+        UINT32    dbi_rom_access        : 1   ;
+        UINT32    dbi_io_access         : 1   ;
+        UINT32    memicg_bypass         : 1   ;
+        UINT32    Reserved_28           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_CTRL20_U;
+
+
+
+
+typedef union tagPcieSysCtrl21
+{
+
+    struct
+    {
+        UINT32    pcie_sys_pre_det_state  : 1   ;
+        UINT32    pcie_sys_atten_button_pressed  : 1   ;
+        UINT32    Reserved_30           : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_CTRL21_U;
+
+
+
+
+typedef union tagPcieSysCtrl23
+{
+
+    struct
+    {
+        UINT32    Reserved_35           : 2   ;
+        UINT32    Reserved_34           : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_CTRL23_U;
+
+
+
+
+typedef union tagPcieSysState5
+{
+
+    struct
+    {
+        UINT32    mstr_awmisc_info_func_num  : 1   ;
+        UINT32    mstr_awmisc_info_vfunc_active  : 1   ;
+        UINT32    mstr_awmisc_info_vfunc_num  : 1   ;
+        UINT32    Reserved_39           : 1   ;
+        UINT32    mstr_armisc_info_func_num  : 1   ;
+        UINT32    mstr_armisc_info_vfunc_active  : 1   ;
+        UINT32    mstr_armisc_info_vfunc_num  : 1   ;
+        UINT32    Reserved_38           : 1   ;
+        UINT32    mstr_awmisc_info_nw   : 1   ;
+        UINT32    mstr_awmisc_info_ats  : 2   ;
+        UINT32    mstr_armisc_info_nw   : 1   ;
+        UINT32    mstr_armisc_info_ats  : 2   ;
+        UINT32    slv_bmisc_info_ats    : 2   ;
+        UINT32    slv_rmisc_info_ats    : 2   ;
+        UINT32    Reserved_37           : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE5_U;
+
+
+
+
+typedef union tagPcieSysState6
+{
+
+    struct
+    {
+        UINT32    cfg_flr_pf_active     : 1   ;
+        UINT32    cfg_flr_vf_active     : 2   ;
+        UINT32    Reserved_41           : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE6_U;
+
+
+
+
+typedef union tagPcieSysState7
+{
+
+    struct
+    {
+        UINT32    radm_timeout_vfunc_active  : 1   ;
+        UINT32    radm_timeout_vfunc_num  : 1   ;
+        UINT32    trgt_timeout_cpl_vfunc_active  : 1   ;
+        UINT32    trgt_timeout_cpl_vfunc_num  : 1   ;
+        UINT32    Reserved_43           : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE7_U;
+
+
+
+
+typedef union tagPcieSysState11
+{
+
+    struct
+    {
+        UINT32    cfg_msi_64            : 1   ;
+        UINT32    cfg_vf_msi_en         : 2   ;
+        UINT32    cfg_vf_msi_64         : 2   ;
+        UINT32    cfg_multi_msi_en      : 3   ;
+        UINT32    cfg_vf_multi_msi_en   : 6   ;
+        UINT32    Reserved_48           : 2   ;
+        UINT32    cfg_msi_data          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE11_U;
+
+
+
+
+typedef union tagPcieSysState12
+{
+
+    struct
+    {
+        UINT32    cfg_vf_en             : 1   ;
+        UINT32    cfg_ari_fwd_en        : 1   ;
+        UINT32    cfg_vf_bme            : 2   ;
+        UINT32    Reserved_51           : 4   ;
+        UINT32    cfg_num_vf            : 16  ;
+        UINT32    Reserved_50           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE12_U;
+
+
+
+
+typedef union tagPcieSysState20
+{
+
+    struct
+    {
+        UINT32    slv_bmisc_info        : 11  ;
+        UINT32    slv_rmisc_info        : 11  ;
+        UINT32    rtlh_rfc_upd          : 1   ;
+        UINT32    Reserved_60           : 9   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE20_U;
+
+
+
+
+typedef union tagPcieSysState21
+{
+
+    struct
+    {
+        UINT32    cfg_msix_en           : 1   ;
+        UINT32    cfg_msix_func_mask    : 1   ;
+        UINT32    cfg_vf_msix_func_mask  : 2   ;
+        UINT32    cfg_vf_msix_en        : 2   ;
+        UINT32    Reserved_62           : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE21_U;
+
+
+
+
+typedef union tagPcieSysState22
+{
+
+    struct
+    {
+        UINT32    lbc_ext_vfunc_active  : 1   ;
+        UINT32    lbc_ext_vfunc_num     : 1   ;
+        UINT32    lbc_dbi_ack           : 1   ;
+        UINT32    pcie_mstr_awmisc_info  : 24  ;
+        UINT32    Reserved_64           : 5   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE22_U;
+
+
+
+
+typedef union tagPcieSysState27
+{
+
+    struct
+    {
+        UINT32    trgt_cpl_timeout      : 1   ;
+        UINT32    trgt_timeout_cpl_func_num  : 1   ;
+        UINT32    trgt_timeout_cpl_tc   : 3   ;
+        UINT32    trgt_timeout_cpl_attr  : 2   ;
+        UINT32    trgt_timeout_cpl_len  : 12  ;
+        UINT32    trgt_lookup_empty     : 1   ;
+        UINT32    Reserved_70           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE27_U;
+
+
+
+
+typedef union tagPcieSysState28
+{
+
+    struct
+    {
+        UINT32    trgt_timeout_lookup_id  : 8   ;
+        UINT32    trgt_lookup_id        : 8   ;
+        UINT32    radm_timeout_cpl_tag  : 8   ;
+        UINT32    Reserved_72           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE28_U;
+
+
+
+
+typedef union tagPcieSysState29
+{
+
+    struct
+    {
+        UINT32    trgt_cpl_timeout      : 1   ;
+        UINT32    radm_timeout_func_num  : 1   ;
+        UINT32    radm_timeout_cpl_tc   : 3   ;
+        UINT32    radm_timeout_cpl_attr  : 2   ;
+        UINT32    radm_timeout_cpl_len  : 12  ;
+        UINT32    radm_pm_turnoff       : 1   ;
+        UINT32    Reserved_74           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE29_U;
+
+
+
+
+typedef union tagPcieSysState30
+{
+
+    struct
+    {
+        UINT32    cfg_pbus_num          : 8   ;
+        UINT32    cfg_pbus_dev_num      : 5   ;
+        UINT32    cfg_link_auto_bw_int  : 1   ;
+        UINT32    cfg_bw_mgt_int        : 1   ;
+        UINT32    Reserved_76           : 17  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE30_U;
+
+
+
+
+typedef union tagPcieSysState32
+{
+
+    struct
+    {
+        UINT32    mstr_awmisc_info_dma  : 6   ;
+        UINT32    mstr_armisc_info_dma  : 6   ;
+        UINT32    cfg_hw_auto_sp_dis    : 1   ;
+        UINT32    link_timeout_flush_not  : 1   ;
+        UINT32    mac_phy_clk_req_n     : 1   ;
+        UINT32    wake_ref_rst_n        : 1   ;
+        UINT32    pcie_wake             : 1   ;
+        UINT32    Reserved_79           : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE32_U;
+
+
+
+
+typedef union tagPcieSysState39
+{
+
+    struct
+    {
+        UINT32    radm_msg_unlock_reqid  : 16  ;
+        UINT32    radm_nonfatal_err_reqid  : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE39_U;
+
+
+
+
+typedef union tagPcieSysState44
+{
+
+    struct
+    {
+        UINT32    radm_unlock_reqid     : 16  ;
+        UINT32    radm_nonfatal_err_reqid  : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE44_U;
+
+
+
+
+typedef union tagPcieSysState49
+{
+
+    struct
+    {
+        UINT32    radm_pm_pme_reqid     : 16  ;
+        UINT32    radm_pm_ack_to_reqid  : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_SYS_STATE49_U;
+
+
+
+
+typedef union tagPcieStat0
+{
+
+    struct
+    {
+        UINT32    pcie2_gm_cmposer_lookup_err  : 1   ;
+        UINT32    pcie2_radmx_cmposer_lookup_err  : 1   ;
+        UINT32    pcie2_cfg_pwr_ind     : 2   ;
+        UINT32    pcie2_cfg_atten_ind   : 2   ;
+        UINT32    pcie2_cfg_pwr_ctrler_ctrl  : 1   ;
+        UINT32    pcie2_pm_xtlh_block_tlp  : 1   ;
+        UINT32    pcie2_cfg_mem_space_en  : 1   ;
+        UINT32    pcie2_cfg_rcb         : 1   ;
+        UINT32    pcie2_rdlh_link_up    : 1   ;
+        UINT32    pcie2_pm_curnt_state  : 3   ;
+        UINT32    pcie2_cfg_aer_rc_err_int  : 1   ;
+        UINT32    Reserved_106          : 1   ;
+        UINT32    pcie2_cfg_aer_int_msg_num  : 5   ;
+        UINT32    Reserved_105          : 1   ;
+        UINT32    pcie2_xmlh_link_up    : 1   ;
+        UINT32    pcie2_wake            : 1   ;
+        UINT32    pcie2_cfg_eml_control  : 1   ;
+        UINT32    pcie2_hp_pme          : 1   ;
+        UINT32    pcie2_hp_int          : 1   ;
+        UINT32    pcie2_hp_msi          : 1   ;
+        UINT32    pcie2_pm_status       : 1   ;
+        UINT32    pcie2_ref_clk_req_n   : 1   ;
+        UINT32    Reserved_104          : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_STAT_0_U;
+
+
+
+
+typedef union tagPcieStat1
+{
+
+    struct
+    {
+        UINT32    axi_parity_errs_reg   : 4   ;
+        UINT32    app_parity_errs_reg   : 3   ;
+        UINT32    pm_linkst_in_l1       : 1   ;
+        UINT32    pm_linkst_in_l2       : 1   ;
+        UINT32    pm_linkst_l2_exit     : 1   ;
+        UINT32    mac_phy_power_down    : 2   ;
+        UINT32    radm_correctabl_err_reg  : 1   ;
+        UINT32    radm_nonfatal_err_reg  : 1   ;
+        UINT32    radm_fatal_err_reg    : 1   ;
+        UINT32    radm_pm_to_pme_reg    : 1   ;
+        UINT32    radm_pm_to_ack_reg    : 1   ;
+        UINT32    radm_cpl_timeout_reg  : 1   ;
+        UINT32    radm_msg_unlock_reg   : 1   ;
+        UINT32    cfg_pme_msi_reg       : 1   ;
+        UINT32    bridge_flush_not_reg  : 1   ;
+        UINT32    link_req_rst_not_reg  : 1   ;
+        UINT32    pcie2_cfg_aer_rc_err_msi  : 1   ;
+        UINT32    pcie2_cfg_sys_err_rc  : 1   ;
+        UINT32    Reserved_107          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_STAT_1_U;
+
+
+
+
+typedef union tagPcieStat3
+{
+
+    struct
+    {
+        UINT32    radm_msg_req_id       : 16  ;
+        UINT32    Reserved_108          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_STAT_3_U;
+
+
+
+
+typedef union tagPcieStat4
+{
+
+    struct
+    {
+        UINT32    ltssm_state           : 6   ;
+        UINT32    mac_phy_rate          : 2   ;
+        UINT32    pcie_slv_err_int_state  : 1   ;
+        UINT32    retry_sram_addr       : 10  ;
+        UINT32    pcie_mstr_rresp_int_state  : 1   ;
+        UINT32    pcie_mstr_bresp_int_state  : 1   ;
+        UINT32    pcie_radm_inta_int_state  : 1   ;
+        UINT32    pcie_radm_intb_int_state  : 1   ;
+        UINT32    pcie_radm_intc_int_state  : 1   ;
+        UINT32    pcie_radm_intd_int_state  : 1   ;
+        UINT32    pme_int_state         : 1   ;
+        UINT32    radm_vendr_msg_int_state  : 1   ;
+        UINT32    Reserved_109          : 5   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_STAT_4_U;
+
+
+#define PCIE_MUL_BASE                             (0x1000)
+
+
+
+
+#define PCIE_MUL_MC_CTRL_REG                      (PCIE_MUL_BASE + 0x0)
+#define PCIE_MUL_CFG_WIN0_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x4)
+#define PCIE_MUL_CFG_WIN0_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x8)
+#define PCIE_MUL_CFG_WIN1_BAR_LOWER_REG           (PCIE_MUL_BASE + 0xC)
+#define PCIE_MUL_CFG_WIN1_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x10)
+#define PCIE_MUL_CFG_WIN2_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x14)
+#define PCIE_MUL_CFG_WIN2_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x18)
+#define PCIE_MUL_CFG_WIN3_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x1C)
+#define PCIE_MUL_CFG_WIN3_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x20)
+#define PCIE_MUL_CFG_WIN4_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x24)
+#define PCIE_MUL_CFG_WIN4_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x28)
+#define PCIE_MUL_CFG_WIN5_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x2C)
+#define PCIE_MUL_CFG_WIN5_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x30)
+#define PCIE_MUL_CFG_WIN6_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x34)
+#define PCIE_MUL_CFG_WIN6_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x38)
+#define PCIE_MUL_CFG_WIN7_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x3C)
+#define PCIE_MUL_CFG_WIN7_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x40)
+#define PCIE_MUL_CFG_WIN8_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x44)
+#define PCIE_MUL_CFG_WIN8_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x48)
+#define PCIE_MUL_CFG_WIN9_BAR_LOWER_REG           (PCIE_MUL_BASE + 0x4C)
+#define PCIE_MUL_CFG_WIN9_BAR_UPPER_REG           (PCIE_MUL_BASE + 0x50)
+#define PCIE_MUL_CFG_WIN10_BAR_LOWER_REG          (PCIE_MUL_BASE + 0x54)
+#define PCIE_MUL_CFG_WIN10_BAR_UPPER_REG          (PCIE_MUL_BASE + 0x58)
+#define PCIE_MUL_CFG_WIN11_BAR_LOWER_REG          (PCIE_MUL_BASE + 0x5C)
+#define PCIE_MUL_CFG_WIN11_BAR_UPPER_REG          (PCIE_MUL_BASE + 0x60)
+#define PCIE_MUL_CFG_WIN12_BAR_LOWER_REG          (PCIE_MUL_BASE + 0x64)
+#define PCIE_MUL_CFG_WIN12_BAR_UPPER_REG          (PCIE_MUL_BASE + 0x68)
+#define PCIE_MUL_CFG_WIN13_BAR_LOWER_REG          (PCIE_MUL_BASE + 0x6C)
+#define PCIE_MUL_CFG_WIN13_BAR_UPPER_REG          (PCIE_MUL_BASE + 0x70)
+#define PCIE_MUL_CFG_WIN14_BAR_LOWER_REG          (PCIE_MUL_BASE + 0x74)
+#define PCIE_MUL_CFG_WIN14_BAR_UPPER_REG          (PCIE_MUL_BASE + 0x78)
+#define PCIE_MUL_CFG_WIN15_BAR_LOWER_REG          (PCIE_MUL_BASE + 0x7C)
+#define PCIE_MUL_CFG_WIN15_BAR_UPPER_REG          (PCIE_MUL_BASE + 0x80)
+#define PCIE_MUL_CFG_WIN0_SIZE_REG                (PCIE_MUL_BASE + 0x84)
+#define PCIE_MUL_CFG_WIN1_SIZE_REG                (PCIE_MUL_BASE + 0x88)
+#define PCIE_MUL_CFG_WIN2_SIZE_REG                (PCIE_MUL_BASE + 0x8C)
+#define PCIE_MUL_CFG_WIN3_SIZE_REG                (PCIE_MUL_BASE + 0x90)
+#define PCIE_MUL_CFG_WIN4_SIZE_REG                (PCIE_MUL_BASE + 0x94)
+#define PCIE_MUL_CFG_WIN5_SIZE_REG                (PCIE_MUL_BASE + 0x98)
+#define PCIE_MUL_CFG_WIN6_SIZE_REG                (PCIE_MUL_BASE + 0x9C)
+#define PCIE_MUL_CFG_WIN7_SIZE_REG                (PCIE_MUL_BASE + 0xA0)
+#define PCIE_MUL_CFG_WIN8_SIZE_REG                (PCIE_MUL_BASE + 0xA4)
+#define PCIE_MUL_CFG_WIN9_SIZE_REG                (PCIE_MUL_BASE + 0xA8)
+#define PCIE_MUL_CFG_WIN10_SIZE_REG               (PCIE_MUL_BASE + 0xAC)
+#define PCIE_MUL_CFG_WIN11_SIZE_REG               (PCIE_MUL_BASE + 0xB0)
+#define PCIE_MUL_CFG_WIN12_SIZE_REG               (PCIE_MUL_BASE + 0xB4)
+#define PCIE_MUL_CFG_WIN13_SIZE_REG               (PCIE_MUL_BASE + 0xB8)
+#define PCIE_MUL_CFG_WIN14_SIZE_REG               (PCIE_MUL_BASE + 0xBC)
+#define PCIE_MUL_CFG_WIN15_SIZE_REG               (PCIE_MUL_BASE + 0xC0)
+#define PCIE_MUL_CFG_WIN0_XLAT_BASE_LOWER_REG     (PCIE_MUL_BASE + 0xC4)
+#define PCIE_MUL_CFG_WIN0_XLAT_BASE_UPPER_REG     (PCIE_MUL_BASE + 0xC8)
+#define PCIE_MUL_CFG_WIN1_XLAT_BASE_LOWER_REG     (PCIE_MUL_BASE + 0xCC)
+#define PCIE_MUL_CFG_WIN1_XLAT_BASE_UPPER_REG     (PCIE_MUL_BASE + 0xD0)
+#define PCIE_MUL_CFG_WIN2_XLAT_BASE_LOWER_REG     (PCIE_MUL_BASE + 0xD4)
+#define PCIE_MUL_CFG_WIN2_XLAT_BASE_UPPER_REG     (PCIE_MUL_BASE + 0xD8)
+#define PCIE_MUL_CFG_WIN3_XLAT_BASE_LOWER_REG     (PCIE_MUL_BASE + 0xDC)
+#define PCIE_MUL_CFG_WIN3_XLAT_BASE_UPPER_REG     (PCIE_MUL_BASE + 0xE0)
+#define PCIE_MUL_CFG_WIN4_XLAT_BASE_LOWER_REG     (PCIE_MUL_BASE + 0xE4)
+#define PCIE_MUL_CFG_WIN4_XLAT_BASE_UPPER_REG     (PCIE_MUL_BASE + 0xE8)
+#define PCIE_MUL_CFG_WIN5_XLAT_BASE_LOWER_REG     (PCIE_MUL_BASE + 0xEC)
+#define PCIE_MUL_CFG_WIN5_XLAT_BASE_UPPER_REG     (PCIE_MUL_BASE + 0xF0)
+#define PCIE_MUL_CFG_WIN6_XLAT_BASE_LOWER_REG     (PCIE_MUL_BASE + 0xF4)
+#define PCIE_MUL_CFG_WIN6_XLAT_BASE_UPPER_REG     (PCIE_MUL_BASE + 0xF8)
+#define PCIE_MUL_CFG_WIN7_XLAT_LOWER_REG          (PCIE_MUL_BASE + 0xFC)
+#define PCIE_MUL_CFG_WIN7_XLAT_UPPER_REG          (PCIE_MUL_BASE + 0x100)
+#define PCIE_MUL_CFG_WIN8_XLAT_LOWER_REG          (PCIE_MUL_BASE + 0x104)
+#define PCIE_MUL_CFG_WIN8_XLAT_UPPER_REG          (PCIE_MUL_BASE + 0x108)
+#define PCIE_MUL_CFG_WIN9_XLAT_LOWER_REG          (PCIE_MUL_BASE + 0x10C)
+#define PCIE_MUL_CFG_WIN9_XLAT_UPPER_REG          (PCIE_MUL_BASE + 0x110)
+#define PCIE_MUL_CFG_WIN10_XLAT_LOWER_REG         (PCIE_MUL_BASE + 0x114)
+#define PCIE_MUL_CFG_WIN10_XLAT_UPPER_REG         (PCIE_MUL_BASE + 0x118)
+#define PCIE_MUL_CFG_WIN11_XLAT_LOWER_REG         (PCIE_MUL_BASE + 0x11C)
+#define PCIE_MUL_CFG_WIN11_XLAT_UPPER_REG         (PCIE_MUL_BASE + 0x120)
+#define PCIE_MUL_CFG_WIN12_XLAT_LOWER_REG         (PCIE_MUL_BASE + 0x124)
+#define PCIE_MUL_CFG_WIN12_XLAT_UPPER_REG         (PCIE_MUL_BASE + 0x128)
+#define PCIE_MUL_CFG_WIN13_XLAT_LOWER_REG         (PCIE_MUL_BASE + 0x12C)
+#define PCIE_MUL_CFG_WIN13_XLAT_UPPER_REG         (PCIE_MUL_BASE + 0x130)
+#define PCIE_MUL_CFG_WIN14_XLAT_LOWER_REG         (PCIE_MUL_BASE + 0x134)
+#define PCIE_MUL_CFG_WIN14_XLAT_UPPER_REG         (PCIE_MUL_BASE + 0x138)
+#define PCIE_MUL_CFG_WIN15_XLAT_LOWER_REG         (PCIE_MUL_BASE + 0x13C)
+#define PCIE_MUL_CFG_WIN15_XLAT_UPPER_REG         (PCIE_MUL_BASE + 0x140)
+#define PCIE_MUL_CFG_WIN_XLAT_EN_REG              (PCIE_MUL_BASE + 0x144)
+#define PCIE_MUL_CFG_MCAST_CMD_TIMEOUT_REG        (PCIE_MUL_BASE + 0x148)
+#define PCIE_MUL_CFG_INT_STATUS_REG               (PCIE_MUL_BASE + 0x14C)
+#define PCIE_MUL_CFG_INJECT_ECC_ERR_REG           (PCIE_MUL_BASE + 0x150)
+
+
+
+
+typedef union tagMcCtrl
+{
+
+    struct
+    {
+        UINT32    cfg_mcast_en          : 1   ;
+        UINT32    cfg_win0_mcast_en     : 1   ;
+        UINT32    cfg_win1_mcast_en     : 1   ;
+        UINT32    cfg_win2_mcast_en     : 1   ;
+        UINT32    cfg_win3_mcast_en     : 1   ;
+        UINT32    cfg_win4_mcast_en     : 1   ;
+        UINT32    cfg_win5_mcast_en     : 1   ;
+        UINT32    cfg_win6_mcast_en     : 1   ;
+        UINT32    cfg_win7_mcast_en     : 1   ;
+        UINT32    cfg_win8_mcast_en     : 1   ;
+        UINT32    cfg_win9_mcast_en     : 1   ;
+        UINT32    cfg_win10_mcast_en    : 1   ;
+        UINT32    cfg_win11_mcast_en    : 1   ;
+        UINT32    cfg_win12_mcast_en    : 1   ;
+        UINT32    cfg_win13_mcast_en    : 1   ;
+        UINT32    cfg_win14_mcast_en    : 1   ;
+        UINT32    cfg_win15_mcast_en    : 1   ;
+        UINT32    Reserved_0            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_mc_ctrl_u;
+
+
+
+
+typedef union tagCfgWin0Size
+{
+
+    struct
+    {
+        UINT32    cfg_win0_size         : 6   ;
+        UINT32    Reserved_1            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win0_size_u;
+
+
+
+
+typedef union tagCfgWin1Size
+{
+
+    struct
+    {
+        UINT32    cfg_win1_size         : 6   ;
+        UINT32    Reserved_2            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win1_size_u;
+
+
+
+
+typedef union tagCfgWin2Size
+{
+
+    struct
+    {
+        UINT32    cfg_win2_size         : 6   ;
+        UINT32    Reserved_3            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win2_size_u;
+
+
+
+
+typedef union tagCfgWin3Size
+{
+
+    struct
+    {
+        UINT32    cfg_win3_size         : 6   ;
+        UINT32    Reserved_4            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win3_size_u;
+
+
+
+
+typedef union tagCfgWin4Size
+{
+
+    struct
+    {
+        UINT32    cfg_win4_size         : 6   ;
+        UINT32    Reserved_5            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win4_size_u;
+
+
+
+
+typedef union tagCfgWin5Size
+{
+
+    struct
+    {
+        UINT32    cfg_win5_size         : 6   ;
+        UINT32    Reserved_6            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win5_size_u;
+
+
+
+
+typedef union tagCfgWin6Size
+{
+
+    struct
+    {
+        UINT32    cfg_win6_size         : 6   ;
+        UINT32    Reserved_7            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win6_size_u;
+
+
+
+
+typedef union tagCfgWin7Size
+{
+
+    struct
+    {
+        UINT32    cfg_win7_size         : 6   ;
+        UINT32    Reserved_8            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win7_size_u;
+
+
+
+
+typedef union tagCfgWin8Size
+{
+
+    struct
+    {
+        UINT32    cfg_win8_size         : 6   ;
+        UINT32    Reserved_9            : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win8_size_u;
+
+
+
+
+typedef union tagCfgWin9Size
+{
+
+    struct
+    {
+        UINT32    cfg_win9_size         : 6   ;
+        UINT32    Reserved_10           : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win9_size_u;
+
+
+
+
+typedef union tagCfgWin10Size
+{
+
+    struct
+    {
+        UINT32    cfg_win10_size        : 6   ;
+        UINT32    Reserved_11           : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win10_size_u;
+
+
+
+
+typedef union tagCfgWin11Size
+{
+
+    struct
+    {
+        UINT32    cfg_win11_size        : 6   ;
+        UINT32    Reserved_12           : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win11_size_u;
+
+
+
+
+typedef union tagCfgWin12Size
+{
+
+    struct
+    {
+        UINT32    cfg_win12_size        : 6   ;
+        UINT32    Reserved_13           : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win12_size_u;
+
+
+
+
+typedef union tagCfgWin13Size
+{
+
+    struct
+    {
+        UINT32    cfg_win13_size        : 6   ;
+        UINT32    Reserved_14           : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win13_size_u;
+
+
+
+
+typedef union tagCfgWin14Size
+{
+
+    struct
+    {
+        UINT32    cfg_win14_size        : 6   ;
+        UINT32    Reserved_15           : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win14_size_u;
+
+
+
+
+typedef union tagCfgWin15Size
+{
+
+    struct
+    {
+        UINT32    cfg_win15_size        : 6   ;
+        UINT32    Reserved_16           : 26  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win15_size_u;
+
+
+
+
+typedef union tagCfgWinXlatEn
+{
+
+    struct
+    {
+        UINT32    cfg_win0_xlat_en      : 1   ;
+        UINT32    cfg_win1_xlat_en      : 1   ;
+        UINT32    cfg_win2_xlat_en      : 1   ;
+        UINT32    cfg_win3_xlat_en      : 1   ;
+        UINT32    cfg_win4_xlat_en      : 1   ;
+        UINT32    cfg_win5_xlat_en      : 1   ;
+        UINT32    cfg_win6_xlat_en      : 1   ;
+        UINT32    cfg_win7_xlat_en      : 1   ;
+        UINT32    cfg_win8_xlat_en      : 1   ;
+        UINT32    cfg_win9_xlat_en      : 1   ;
+        UINT32    cfg_win10_xlat_en     : 1   ;
+        UINT32    cfg_win11_xlat_en     : 1   ;
+        UINT32    cfg_win12_xlat_en     : 1   ;
+        UINT32    cfg_win13_xlat_en     : 1   ;
+        UINT32    cfg_win14_xlat_en     : 1   ;
+        UINT32    cfg_win15_xlat_en     : 1   ;
+        UINT32    Reserved_17           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_win_xlat_en_u;
+
+
+
+
+typedef union tagCfgMcastCmdTimeout
+{
+
+    struct
+    {
+        UINT32    cfg_mcast_cmd_timeout  : 10  ;
+        UINT32    Reserved_18           : 22  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_mcast_cmd_timeout_u;
+
+
+
+
+typedef union tagCfgIntStatus
+{
+
+    struct
+    {
+        UINT32    timeout_int           : 1   ;
+        UINT32    ecc_err1_int          : 1   ;
+        UINT32    ecc_err2_int          : 1   ;
+        UINT32    Reserved_19           : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_int_status_u;
+
+
+
+
+typedef union tagCfgInjectEccErr
+{
+
+    struct
+    {
+        UINT32    ecc_err_inject_en     : 1   ;
+        UINT32    Reserved_20           : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} pcie_mul_cfg_inject_ecc_err_u;
+
+
+#define PCIE_EP_BASE                              (0x00000000)
+
+
+
+
+#define PCIE_EP_PCI_CFG_HDR0_REG                  (PCIE_EP_BASE + 0x0)
+#define PCIE_EP_PCI_CFG_HDR1_REG                  (PCIE_EP_BASE + 0x4)
+#define PCIE_EP_PCI_CFG_HDR2_REG                  (PCIE_EP_BASE + 0x8)
+#define PCIE_EP_PCI_CFG_HDR3_REG                  (PCIE_EP_BASE + 0xC)
+#define PCIE_EP_PCI_CFG_HDR4_REG                  (PCIE_EP_BASE + 0x10)
+#define PCIE_EP_PCI_CFG_HDR5_REG                  (PCIE_EP_BASE + 0x14)
+#define PCIE_EP_PCI_CFG_HDR6_REG                  (PCIE_EP_BASE + 0x18)
+#define PCIE_EP_PCI_CFG_HDR7_REG                  (PCIE_EP_BASE + 0x1C)
+#define PCIE_EP_PCI_CFG_HDR8_REG                  (PCIE_EP_BASE + 0x20)
+#define PCIE_EP_PCI_CFG_HDR9_REG                  (PCIE_EP_BASE + 0x24)
+#define PCIE_EP_PCI_CFG_HDR10_REG                 (PCIE_EP_BASE + 0x28)
+#define PCIE_EP_PCI_CFG_HDR11_REG                 (PCIE_EP_BASE + 0x2C)
+#define PCIE_EP_PCI_CFG_HDR12_REG                 (PCIE_EP_BASE + 0x30)
+#define PCIE_EP_PCI_CFG_HDR13_REG                 (PCIE_EP_BASE + 0x34)
+#define PCIE_EP_PCI_CFG_HDR14_REG                 (PCIE_EP_BASE + 0x38)
+#define PCIE_EP_PCI_CFG_HDR15_REG                 (PCIE_EP_BASE + 0x3C)
+#define PCIE_EP_PCI_PM_CAP0_REG                   (PCIE_EP_BASE + 0x40)
+#define PCIE_EP_PCI_PM_CAP1_REG                   (PCIE_EP_BASE + 0x44)
+#define PCIE_EP_PCI_MSI_CAP0_REG                  (PCIE_EP_BASE + 0x50)
+#define PCIE_EP_PCI_MSI_CAP1_REG                  (PCIE_EP_BASE + 0x54)
+#define PCIE_EP_PCI_MSI_CAP2_REG                  (PCIE_EP_BASE + 0x58)
+#define PCIE_EP_PCI_MSI_CAP3_REG                  (PCIE_EP_BASE + 0x5C)
+#define PCIE_EP_PCIE_CAP0_REG                     (PCIE_EP_BASE + 0x70)
+#define PCIE_EP_PCIE_CAP1_REG                     (PCIE_EP_BASE + 0x74)
+#define PCIE_EP_PCIE_CAP2_REG                     (PCIE_EP_BASE + 0x78)
+#define PCIE_EP_PCIE_CAP3_REG                     (PCIE_EP_BASE + 0x7C)
+#define PCIE_EP_PCIE_CAP4_REG                     (PCIE_EP_BASE + 0x80)
+#define PCIE_EP_PCIE_CAP5_REG                     (PCIE_EP_BASE + 0x84)
+#define PCIE_EP_PCIE_CAP6_REG                     (PCIE_EP_BASE + 0x88)
+#define PCIE_EP_PCIE_CAP7_REG                     (PCIE_EP_BASE + 0x8C)
+#define PCIE_EP_PCIE_CAP8_REG                     (PCIE_EP_BASE + 0x90)
+#define PCIE_EP_PCIE_CAP9_REG                     (PCIE_EP_BASE + 0x94)
+#define PCIE_EP_PCIE_CAP10_REG                    (PCIE_EP_BASE + 0x98)
+#define PCIE_EP_PCIE_CAP11_REG                    (PCIE_EP_BASE + 0x9C)
+#define PCIE_EP_PCIE_CAP12_REG                    (PCIE_EP_BASE + 0xA0)
+#define PCIE_EP_SLOT_CAP_REG                      (PCIE_EP_BASE + 0xC0)
+#define PCIE_EP_AER_CAP0_REG                      (PCIE_EP_BASE + 0x100)
+#define PCIE_EP_AER_CAP1_REG                      (PCIE_EP_BASE + 0x104)
+#define PCIE_EP_AER_CAP2_REG                      (PCIE_EP_BASE + 0x108)
+#define PCIE_EP_AER_CAP3_REG                      (PCIE_EP_BASE + 0x10C)
+#define PCIE_EP_AER_CAP4_REG                      (PCIE_EP_BASE + 0x110)
+#define PCIE_EP_AER_CAP5_REG                      (PCIE_EP_BASE + 0x114)
+#define PCIE_EP_AER_CAP6_REG                      (PCIE_EP_BASE + 0x118)
+#define PCIE_EP_AER_CAP7_REG                      (PCIE_EP_BASE + 0x11C)
+#define PCIE_EP_AER_CAP8_REG                      (PCIE_EP_BASE + 0x120)
+#define PCIE_EP_AER_CAP9_REG                      (PCIE_EP_BASE + 0x124)
+#define PCIE_EP_AER_CAP10_REG                     (PCIE_EP_BASE + 0x128)
+#define PCIE_EP_AER_CAP11_REG                     (PCIE_EP_BASE + 0x12C)
+#define PCIE_EP_AER_CAP12_REG                     (PCIE_EP_BASE + 0x130)
+#define PCIE_EP_AER_CAP13_REG                     (PCIE_EP_BASE + 0x134)
+#define PCIE_EP_VC_CAP0_REG                       (PCIE_EP_BASE + 0x140)
+#define PCIE_EP_VC_CAP1_REG                       (PCIE_EP_BASE + 0x144)
+#define PCIE_EP_VC_CAP2_REG                       (PCIE_EP_BASE + 0x148)
+#define PCIE_EP_VC_CAP3_REG                       (PCIE_EP_BASE + 0x14C)
+#define PCIE_EP_VC_CAP4_REG                       (PCIE_EP_BASE + 0x150)
+#define PCIE_EP_VC_CAP5_REG                       (PCIE_EP_BASE + 0x154)
+#define PCIE_EP_VC_CAP6_REG                       (PCIE_EP_BASE + 0x158)
+#define PCIE_EP_VC_CAP7_REG                       (PCIE_EP_BASE + 0x15C)
+#define PCIE_EP_VC_CAP8_REG                       (PCIE_EP_BASE + 0x160)
+#define PCIE_EP_VC_CAP9_REG                       (PCIE_EP_BASE + 0x164)
+#define PCIE_EP_PORT_LOGIC0_REG                   (PCIE_EP_BASE + 0x700)
+#define PCIE_EP_PORT_LOGIC1_REG                   (PCIE_EP_BASE + 0x704)
+#define PCIE_EP_PORT_LOGIC2_REG                   (PCIE_EP_BASE + 0x708)
+#define PCIE_EP_PORT_LOGIC3_REG                   (PCIE_EP_BASE + 0x0)
+#define PCIE_EP_PORT_LOGIC4_REG                   (PCIE_EP_BASE + 0x710)
+#define PCIE_EP_PORT_LOGIC5_REG                   (PCIE_EP_BASE + 0x714)
+#define PCIE_EP_PORT_LOGIC6_REG                   (PCIE_EP_BASE + 0x718)
+#define PCIE_EP_PORT_LOGIC7_REG                   (PCIE_EP_BASE + 0x71C)
+#define PCIE_EP_PORT_LOGIC8_REG                   (PCIE_EP_BASE + 0x720)
+#define PCIE_EP_PORT_LOGIC9_REG                   (PCIE_EP_BASE + 0x724)
+#define PCIE_EP_PORT_LOGIC10_REG                  (PCIE_EP_BASE + 0x728)
+#define PCIE_EP_PORT_LOGIC11_REG                  (PCIE_EP_BASE + 0x72C)
+#define PCIE_EP_PORT_LOGIC12_REG                  (PCIE_EP_BASE + 0x730)
+#define PCIE_EP_PORT_LOGIC13_REG                  (PCIE_EP_BASE + 0x734)
+#define PCIE_EP_PORT_LOGIC14_REG                  (PCIE_EP_BASE + 0x738)
+#define PCIE_EP_PORT_LOGIC15_REG                  (PCIE_EP_BASE + 0x73C)
+#define PCIE_EP_PORT_LOGIC16_REG                  (PCIE_EP_BASE + 0x748)
+#define PCIE_EP_PORT_LOGIC17_REG                  (PCIE_EP_BASE + 0x74C)
+#define PCIE_EP_PORT_LOGIC18_REG                  (PCIE_EP_BASE + 0x750)
+#define PCIE_EP_PORT_LOGIC19_REG                  (PCIE_EP_BASE + 0x7A8)
+#define PCIE_EP_PORT_LOGIC20_REG                  (PCIE_EP_BASE + 0x7AC)
+#define PCIE_EP_PORT_LOGIC21_REG                  (PCIE_EP_BASE + 0x7B0)
+#define PCIE_EP_PORT_LOGIC22_REG                  (PCIE_EP_BASE + 0x80C)
+#define PCIE_EP_PORTLOGIC23_REG                   (PCIE_EP_BASE + 0x810)
+#define PCIE_EP_PORTLOGIC24_REG                   (PCIE_EP_BASE + 0x814)
+#define PCIE_EP_PORTLOGIC25_REG                   (PCIE_EP_BASE + 0x818)
+#define PCIE_EP_PORTLOGIC26_REG                   (PCIE_EP_BASE + 0x81C)
+#define PCIE_EP_PORTLOGIC27_REG                   (PCIE_EP_BASE + 0x820)
+#define PCIE_EP_PORTLOGIC28_REG                   (PCIE_EP_BASE + 0x824)
+#define PCIE_EP_PORTLOGIC29_REG                   (PCIE_EP_BASE + 0x828)
+#define PCIE_EP_PORTLOGIC30_REG                   (PCIE_EP_BASE + 0x82C)
+#define PCIE_EP_PORTLOGIC31_REG                   (PCIE_EP_BASE + 0x830)
+#define PCIE_EP_PORTLOGIC32_REG                   (PCIE_EP_BASE + 0x834)
+#define PCIE_EP_PORTLOGIC33_REG                   (PCIE_EP_BASE + 0x838)
+#define PCIE_EP_PORTLOGIC34_REG                   (PCIE_EP_BASE + 0x83C)
+#define PCIE_EP_PORTLOGIC35_REG                   (PCIE_EP_BASE + 0x840)
+#define PCIE_EP_PORTLOGIC36_REG                   (PCIE_EP_BASE + 0x844)
+#define PCIE_EP_PORTLOGIC37_REG                   (PCIE_EP_BASE + 0x848)
+#define PCIE_EP_PORTLOGIC38_REG                   (PCIE_EP_BASE + 0x84C)
+#define PCIE_EP_PORTLOGIC39_REG                   (PCIE_EP_BASE + 0x850)
+#define PCIE_EP_PORTLOGIC40_REG                   (PCIE_EP_BASE + 0x854)
+#define PCIE_EP_PORTLOGIC41_REG                   (PCIE_EP_BASE + 0x858)
+#define PCIE_EP_PORTLOGIC42_REG                   (PCIE_EP_BASE + 0x85C)
+#define PCIE_EP_PORTLOGIC43_REG                   (PCIE_EP_BASE + 0x860)
+#define PCIE_EP_PORTLOGIC44_REG                   (PCIE_EP_BASE + 0x864)
+#define PCIE_EP_PORTLOGIC45_REG                   (PCIE_EP_BASE + 0x868)
+#define PCIE_EP_PORTLOGIC46_REG                   (PCIE_EP_BASE + 0x86C)
+#define PCIE_EP_PORTLOGIC47_REG                   (PCIE_EP_BASE + 0x870)
+#define PCIE_EP_PORTLOGIC48_REG                   (PCIE_EP_BASE + 0x874)
+#define PCIE_EP_PORTLOGIC49_REG                   (PCIE_EP_BASE + 0x878)
+#define PCIE_EP_PORTLOGIC50_REG                   (PCIE_EP_BASE + 0x87C)
+#define PCIE_EP_PORTLOGIC51_REG                   (PCIE_EP_BASE + 0x880)
+#define PCIE_EP_PORTLOGIC52_REG                   (PCIE_EP_BASE + 0x884)
+#define PCIE_EP_PORTLOGIC53_REG                   (PCIE_EP_BASE + 0x888)
+#define PCIE_EP_LINK_TIMEOUT_OFF_REG              (PCIE_EP_BASE + 0x8d4)
+#define PCIE_EP_PORTLOGIC54_REG                   (PCIE_EP_BASE + 0x900)
+#define PCIE_EP_PORTLOGIC55_REG                   (PCIE_EP_BASE + 0x904)
+#define PCIE_EP_PORTLOGIC56_REG                   (PCIE_EP_BASE + 0x908)
+#define PCIE_EP_PORTLOGIC57_REG                   (PCIE_EP_BASE + 0x90C)
+#define PCIE_EP_PORTLOGIC58_REG                   (PCIE_EP_BASE + 0x910)
+#define PCIE_EP_PORTLOGIC59_REG                   (PCIE_EP_BASE + 0x914)
+#define PCIE_EP_PORTLOGIC60_REG                   (PCIE_EP_BASE + 0x918)
+#define PCIE_EP_PORTLOGIC61_REG                   (PCIE_EP_BASE + 0x91C)
+#define PCIE_EP_PORTLOGIC62_REG                   (PCIE_EP_BASE + 0x97C)
+#define PCIE_EP_PORTLOGIC63_REG                   (PCIE_EP_BASE + 0x980)
+#define PCIE_EP_PORTLOGIC64_REG                   (PCIE_EP_BASE + 0x99C)
+#define PCIE_EP_PORTLOGIC65_REG                   (PCIE_EP_BASE + 0x9A0)
+#define PCIE_EP_PORTLOGIC66_REG                   (PCIE_EP_BASE + 0x9BC)
+#define PCIE_EP_PORTLOGIC67_REG                   (PCIE_EP_BASE + 0x9C4)
+#define PCIE_EP_PORTLOGIC68_REG                   (PCIE_EP_BASE + 0x9C8)
+#define PCIE_EP_PORTLOGIC69_REG                   (PCIE_EP_BASE + 0x9CC)
+#define PCIE_EP_PORTLOGIC70_REG                   (PCIE_EP_BASE + 0x9D0)
+#define PCIE_EP_PORTLOGIC71_REG                   (PCIE_EP_BASE + 0x9D4)
+#define PCIE_EP_PORTLOGIC72_REG                   (PCIE_EP_BASE + 0x9D8)
+#define PCIE_EP_PORTLOGIC73_REG                   (PCIE_EP_BASE + 0x9DC)
+#define PCIE_EP_PORTLOGIC74_REG                   (PCIE_EP_BASE + 0x9E0)
+#define PCIE_EP_PORTLOGIC75_REG                   (PCIE_EP_BASE + 0xA00)
+#define PCIE_EP_PORTLOGIC76_REG                   (PCIE_EP_BASE + 0xA10)
+#define PCIE_EP_PORTLOGIC77_REG                   (PCIE_EP_BASE + 0xA18)
+#define PCIE_EP_PORTLOGIC78_REG                   (PCIE_EP_BASE + 0xA1C)
+#define PCIE_EP_PORTLOGIC79_REG                   (PCIE_EP_BASE + 0xA24)
+#define PCIE_EP_PORTLOGIC80_REG                   (PCIE_EP_BASE + 0xA28)
+#define PCIE_EP_PORTLOGIC81_REG                   (PCIE_EP_BASE + 0xA34)
+#define PCIE_EP_PORTLOGIC82_REG                   (PCIE_EP_BASE + 0xA3C)
+#define PCIE_EP_PORTLOGIC83_REG                   (PCIE_EP_BASE + 0xA40)
+#define PCIE_EP_PORTLOGIC84_REG                   (PCIE_EP_BASE + 0xA44)
+#define PCIE_EP_PORTLOGIC85_REG                   (PCIE_EP_BASE + 0xA48)
+#define PCIE_EP_PORTLOGIC86_REG                   (PCIE_EP_BASE + 0xA6C)
+#define PCIE_EP_PORTLOGIC87_REG                   (PCIE_EP_BASE + 0xA70)
+#define PCIE_EP_PORTLOGIC88_REG                   (PCIE_EP_BASE + 0xA78)
+#define PCIE_EP_PORTLOGIC89_REG                   (PCIE_EP_BASE + 0xA7C)
+#define PCIE_EP_PORTLOGIC90_REG                   (PCIE_EP_BASE + 0xA80)
+#define PCIE_EP_PORTLOGIC91_REG                   (PCIE_EP_BASE + 0xA84)
+#define PCIE_EP_PORTLOGIC92_REG                   (PCIE_EP_BASE + 0xA88)
+#define PCIE_EP_PORTLOGIC93_REG                   (PCIE_EP_BASE + 0xA8C)
+#define PCIE_EP_PORTLOGIC94_REG                   (PCIE_EP_BASE + 0xA90)
+
+
+
+typedef union tagPciCfgHdr0
+{
+
+    struct
+    {
+        UINT32    vendor_id             : 16  ;
+        UINT32    device_id             : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR0_U;
+
+
+
+
+typedef union tagPciCfgHdr1
+{
+
+    struct
+    {
+        UINT32    io_space_enable       : 1   ;
+        UINT32    memory_space_enable   : 1   ;
+        UINT32    bus_master_enable     : 1   ;
+        UINT32    specialcycleenable    : 1   ;
+        UINT32    memory_write_and_invalidate  : 1   ;
+        UINT32    vga_palette_snoop_enable  : 1   ;
+        UINT32    parity_error_response  : 1   ;
+        UINT32    idsel_stepping_waitcycle_control  : 1   ;
+        UINT32    serr_enable           : 1   ;
+        UINT32    fastback_to_backenable  : 1   ;
+        UINT32    interrupt_disable     : 1   ;
+        UINT32    Reserved_2            : 5   ;
+        UINT32    Reserved_1            : 3   ;
+        UINT32    intx_status           : 1   ;
+        UINT32    capabilitieslist      : 1   ;
+        UINT32    pcibus66mhzcapable    : 1   ;
+        UINT32    Reserved_0            : 1   ;
+        UINT32    fastback_to_back      : 1   ;
+        UINT32    masterdataparityerror  : 1   ;
+        UINT32    devsel_timing         : 2   ;
+        UINT32    signaled_target_abort  : 1   ;
+        UINT32    received_target_abort  : 1   ;
+        UINT32    received_master_abort  : 1   ;
+        UINT32    signaled_system_error  : 1   ;
+        UINT32    detected_parity_error  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR1_U;
+
+
+
+
+typedef union tagPciCfgHdr2
+{
+
+    struct
+    {
+        UINT32    revision_identification  : 8   ;
+        UINT32    Reserved_3            : 8   ;
+        UINT32    sub_class             : 8   ;
+        UINT32    baseclass             : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR2_U;
+
+
+
+
+typedef union tagPciCfgHdr3
+{
+
+    struct
+    {
+        UINT32    cache_line_size       : 8   ;
+        UINT32    mstr_lat_tmr          : 8   ;
+        UINT32    multi_function_device  : 7   ;
+        UINT32    hdr_type              : 1   ;
+        UINT32    bist                  : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR3_U;
+
+
+
+
+typedef union tagPciCfgHdr4
+{
+
+    struct
+    {
+        UINT32    sbar01_space_inicator  : 1   ;
+        UINT32    sbar01_type           : 2   ;
+        UINT32    sbar01_prefetchable   : 1   ;
+        UINT32    sbar01_lower          : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR4_U;
+
+
+
+
+typedef union tagPciCfgHdr6
+{
+
+    struct
+    {
+        UINT32    sbar23_space_inicator  : 1   ;
+        UINT32    sbar23_type           : 2   ;
+        UINT32    sbar23_prefetchable   : 1   ;
+        UINT32    Reserved_4            : 8   ;
+        UINT32    sbar23_lower          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR6_U;
+
+typedef union tagPciLinkTimeOut
+{
+
+    struct
+    {
+        UINT32    link_timeout_prepriod_default   : 8   ;
+        UINT32    link_timeout_enable_default  : 1   ;
+        UINT32    Reserved_4          : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_LINK_TIMEOUT_OFF_U;
+
+
+
+
+
+typedef union tagPciCfgHdr8
+{
+
+    struct
+    {
+        UINT32    sbar45_space_inicator  : 1   ;
+        UINT32    sbar45_type           : 2   ;
+        UINT32    sbar45_prefetchable   : 1   ;
+        UINT32    Reserved_5            : 8   ;
+        UINT32    sbar45_lower          : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR8_U;
+
+
+
+
+typedef union tagPciCfgHdr11
+{
+
+    struct
+    {
+        UINT32    subsystem_vendor_id   : 16  ;
+        UINT32    subsystemid           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR11_U;
+
+
+
+
+typedef union tagPciCfgHdr13
+{
+
+    struct
+    {
+        UINT32    capptr                : 8   ;
+        UINT32    Reserved_6            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR13_U;
+
+
+
+
+typedef union tagPciCfgHdr15
+{
+
+    struct
+    {
+        UINT32    int_line              : 8   ;
+        UINT32    int_pin               : 8   ;
+        UINT32    Min_Grant             : 8   ;
+        UINT32    Max_Latency           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_CFG_HDR15_U;
+
+
+
+
+typedef union tagPciMsiCap0
+{
+
+    struct
+    {
+        UINT32    msi_cap_id            : 8   ;
+        UINT32    next_capability_pointer  : 8   ;
+        UINT32    msi_enabled           : 1   ;
+        UINT32    multiple_message_capable  : 3   ;
+        UINT32    multiple_message_enabled  : 3   ;
+        UINT32    msi_64_en             : 1   ;
+        UINT32    pvm_en                : 1   ;
+        UINT32    message_control_register  : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_MSI_CAP0_U;
+
+
+
+
+typedef union tagPciMsiCap1
+{
+
+    struct
+    {
+        UINT32    Reserved_11           : 2   ;
+        UINT32    msi_addr_low          : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_MSI_CAP1_U;
+
+
+
+
+typedef union tagPciMsiCap3
+{
+
+    struct
+    {
+        UINT32    msi_data              : 16  ;
+        UINT32    Reserved_12           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCI_MSI_CAP3_U;
+
+
+
+
+typedef union tagPcieCap0
+{
+
+    struct
+    {
+        UINT32    pcie_cap_id           : 8   ;
+        UINT32    pcie_next_ptr         : 8   ;
+        UINT32    pcie_capability_version  : 4   ;
+        UINT32    device_port_type      : 4   ;
+        UINT32    slot_implemented      : 1   ;
+        UINT32    interrupt_message_number  : 5   ;
+        UINT32    Reserved_13           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP0_U;
+
+
+
+
+typedef union tagPcieCap1
+{
+
+    struct
+    {
+        UINT32    max_payload_size_supported  : 3   ;
+        UINT32    phantom_function_supported  : 2   ;
+        UINT32    extended_tagfield_supported  : 1   ;
+        UINT32    endpoint_l0sacceptable_latency  : 3   ;
+        UINT32    endpoint_l1acceptable_latency  : 3   ;
+        UINT32    undefined             : 3   ;
+        UINT32    Reserved_16           : 3   ;
+        UINT32    captured_slot_power_limit_value  : 8   ;
+        UINT32    captured_slot_power_limit_scale  : 2   ;
+        UINT32    function_level_reset  : 1   ;
+        UINT32    Reserved_15           : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP1_U;
+
+
+
+
+typedef union tagPcieCap2
+{
+
+    struct
+    {
+        UINT32    correctable_error_reporting_enable  : 1   ;
+        UINT32    non_fatal_error_reporting_enable  : 1   ;
+        UINT32    fatal_error_reporting_enable  : 1   ;
+        UINT32    urenable              : 1   ;
+        UINT32    enable_relaxed_ordering  : 1   ;
+        UINT32    max_payload_size      : 3   ;
+        UINT32    extended_tagfieldenable  : 1   ;
+        UINT32    phantom_function_enable  : 1   ;
+        UINT32    auxpowerpmenable      : 1   ;
+        UINT32    enablenosnoop         : 1   ;
+        UINT32    max_read_request_size  : 3   ;
+        UINT32    Reserved_18           : 1   ;
+        UINT32    correctableerrordetected  : 1   ;
+        UINT32    non_fatalerrordetected  : 1   ;
+        UINT32    fatalerrordetected    : 1   ;
+        UINT32    unsupportedrequestdetected  : 1   ;
+        UINT32    auxpowerdetected      : 1   ;
+        UINT32    transactionpending    : 1   ;
+        UINT32    Reserved_17           : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP2_U;
+
+
+
+
+typedef union tagPcieCap3
+{
+
+    struct
+    {
+        UINT32    max_link_speed        : 4   ;
+        UINT32    max_link_width        : 6   ;
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    l0s_exitlatency       : 3   ;
+        UINT32    l1_exit_latency       : 3   ;
+        UINT32    clock_power_management  : 1   ;
+        UINT32    surprise_down_error_report_cap  : 1   ;
+        UINT32    data_link_layer_active_report_cap  : 1   ;
+        UINT32    link_bandwidth_noti_cap  : 1   ;
+        UINT32    aspm_option_compliance  : 1   ;
+        UINT32    Reserved_19           : 1   ;
+        UINT32    port_number           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP3_U;
+
+
+
+
+typedef union tagPcieCap4
+{
+
+    struct
+    {
+        UINT32    active_state_power_management  : 2   ;
+        UINT32    Reserved_22           : 1   ;
+        UINT32    rcb                   : 1   ;
+        UINT32    link_disable          : 1   ;
+        UINT32    retrain_link          : 1   ;
+        UINT32    common_clock_config   : 1   ;
+        UINT32    extended_sync         : 1   ;
+        UINT32    enable_clock_pwr_management  : 1   ;
+        UINT32    hw_auto_width_disable  : 1   ;
+        UINT32    link_bandwidth_management_int_en  : 1   ;
+        UINT32    link_auto_bandwidth_int_en  : 1   ;
+        UINT32    Reserved_21           : 4   ;
+        UINT32    current_link_speed    : 4   ;
+        UINT32    negotiated_link_width  : 6   ;
+        UINT32    Reserved_20           : 1   ;
+        UINT32    link_training         : 1   ;
+        UINT32    slot_clock_configration  : 1   ;
+        UINT32    data_link_layer_active  : 1   ;
+        UINT32    link_bandwidth_management_status  : 1   ;
+        UINT32    link_auto_bandwidth_status  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP4_U;
+
+
+
+
+typedef union tagPcieCap5
+{
+
+    struct
+    {
+        UINT32    attentioonbuttonpresent  : 1   ;
+        UINT32    powercontrollerpresent  : 1   ;
+        UINT32    mrlsensorpresent      : 1   ;
+        UINT32    attentionindicatorpresent  : 1   ;
+        UINT32    powerindicatorpresent  : 1   ;
+        UINT32    hot_plugsurprise      : 1   ;
+        UINT32    hot_plugcapable       : 1   ;
+        UINT32    slotpowerlimitvalue   : 8   ;
+        UINT32    slotpowerlimitscale   : 2   ;
+        UINT32    electromechanicalinterlockpresen  : 1   ;
+        UINT32    no_cmd_complete_support  : 1   ;
+        UINT32    phy_slot_number       : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP5_U;
+
+
+
+
+
+typedef union tagPcieCap6
+{
+
+    struct
+    {
+        UINT32    attentionbuttonpressedenable  : 1   ;
+        UINT32    powerfaultdetectedenable  : 1   ;
+        UINT32    mrlsensorchangedenable  : 1   ;
+        UINT32    presencedetectchangedenable  : 1   ;
+        UINT32    commandcompletedinterruptenable  : 1   ;
+        UINT32    hot_pluginterruptenable  : 1   ;
+        UINT32    attentionindicatorcontrol  : 2   ;
+        UINT32    powerindicatorcontrol  : 2   ;
+        UINT32    powercontrollercontrol  : 1   ;
+        UINT32    electromechanicalinterlockcontrol  : 1   ;
+        UINT32    datalinklayerstatechangedenable  : 1   ;
+        UINT32    Reserved_23           : 3   ;
+        UINT32    attentionbuttonpressed  : 1   ;
+        UINT32    powerfaultdetected    : 1   ;
+        UINT32    mrlsensorchanged      : 1   ;
+        UINT32    presencedetectchanged  : 1   ;
+        UINT32    commandcompleted      : 1   ;
+        UINT32    mrlsensorstate        : 1   ;
+        UINT32    presencedetectstate   : 1   ;
+        UINT32    electromechanicalinterlockstatus  : 1   ;
+        UINT32    datalinklayerstatechanged  : 1   ;
+        UINT32    slot_ctrl_status      : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP6_U;
+
+
+
+
+typedef union tagPcieCap7
+{
+
+    struct
+    {
+        UINT32    systemerroroncorrectableerrorenable  : 1   ;
+        UINT32    systemerroronnon_fatalerrorenable  : 1   ;
+        UINT32    systemerroronfatalerrorenable  : 1   ;
+        UINT32    pmeinterruptenable    : 1   ;
+        UINT32    crssoftwarevisibilityenable  : 1   ;
+        UINT32    Reserved_24           : 11  ;
+        UINT32    crssoftwarevisibility  : 1   ;
+        UINT32    root_cap              : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP7_U;
+
+
+
+
+typedef union tagPcieCap8
+{
+
+    struct
+    {
+        UINT32    pmerequesterid        : 16  ;
+        UINT32    pmestatus             : 1   ;
+        UINT32    pmepending            : 1   ;
+        UINT32    root_status           : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP8_U;
+
+
+
+
+typedef union tagPcieCap9
+{
+
+    struct
+    {
+        UINT32    completiontimeoutrangessupported  : 4   ;
+        UINT32    completiontimeoutdisablesupported  : 1   ;
+        UINT32    ariforwardingsupported  : 1   ;
+        UINT32    atomicoproutingsupported  : 1   ;
+        UINT32    _2_bitatomicopcompletersupported  : 1   ;
+        UINT32    _4_bitatomicopcompletersupported  : 1   ;
+        UINT32    _28_bitcascompletersupported  : 1   ;
+        UINT32    noro_enabledpr_prpassing  : 1   ;
+        UINT32    Reserved_25           : 1   ;
+        UINT32    tphcompletersupported  : 2   ;
+        UINT32    dev_cap2              : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP9_U;
+
+
+
+
+typedef union tagPcieCap10
+{
+
+    struct
+    {
+        UINT32    completiontimeoutvalue  : 4   ;
+        UINT32    completiontimeoutdisable  : 1   ;
+        UINT32    ariforwardingsupported  : 1   ;
+        UINT32    atomicoprequesterenable  : 1   ;
+        UINT32    atomicopegressblocking  : 1   ;
+        UINT32    idorequestenable      : 1   ;
+        UINT32    idocompletionenable   : 1   ;
+        UINT32    dev_ctrl2             : 22  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP10_U;
+
+
+
+
+typedef union tagPcieCap11
+{
+
+    struct
+    {
+        UINT32    Reserved_27           : 1   ;
+        UINT32    gen1_suport           : 1   ;
+        UINT32    gen2_suport           : 1   ;
+        UINT32    gen3_suport           : 1   ;
+        UINT32    Reserved_26           : 4   ;
+        UINT32    crosslink_supported   : 1   ;
+        UINT32    link_cap2             : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP11_U;
+
+
+
+
+typedef union tagPcieCap12
+{
+
+    struct
+    {
+        UINT32    targetlinkspeed       : 4   ;
+        UINT32    entercompliance       : 1   ;
+        UINT32    hardwareautonomousspeeddisa  : 1   ;
+        UINT32    selectablede_empha    : 1   ;
+        UINT32    transmitmargin        : 3   ;
+        UINT32    _entermodifiedcompliance  : 1   ;
+        UINT32    compliancesos         : 1   ;
+        UINT32    de_emphasislevel      : 4   ;
+        UINT32    currentde_emphasislevel  : 1   ;
+        UINT32    equalizationcomplete  : 1   ;
+        UINT32    equalizationphase1successful  : 1   ;
+        UINT32    equalizationphase2successful  : 1   ;
+        UINT32    equalizationphase3successful  : 1   ;
+        UINT32    linkequalizationrequest  : 1   ;
+        UINT32    link_ctrl2_status2    : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PCIE_CAP12_U;
+
+
+
+
+typedef union tagSlotCap
+{
+
+    struct
+    {
+        UINT32    slotnumberingcapabilitiesid  : 8   ;
+        UINT32    nextcapabilitypointer  : 8   ;
+        UINT32    add_incardslotsprovided  : 5   ;
+        UINT32    firstinchassis        : 1   ;
+        UINT32    Reserved_28           : 2   ;
+        UINT32    slot_cap              : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_SLOT_CAP_U;
+
+
+
+
+typedef union tagAerCap0
+{
+
+    struct
+    {
+        UINT32    pciexpressextendedcapabilityid  : 16  ;
+        UINT32    capabilityversion     : 4   ;
+        UINT32    aer_cap_hdr           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP0_U;
+
+
+
+
+typedef union tagAerCap1
+{
+
+    struct
+    {
+        UINT32    Reserved_34           : 1   ;
+        UINT32    Reserved_33           : 3   ;
+        UINT32    datalinkprotocolerrorsta  : 1   ;
+        UINT32    surprisedownerrorstatus  : 1   ;
+        UINT32    Reserved_32           : 6   ;
+        UINT32    poisonedtlpstatu      : 1   ;
+        UINT32    flowcontrolprotocolerrorst  : 1   ;
+        UINT32    completiontimeouts    : 1   ;
+        UINT32    completerabortstatus  : 1   ;
+        UINT32    receiveroverflowstatus  : 1   ;
+        UINT32    malformedtlpstatus    : 1   ;
+        UINT32    ecrcerrorstatus       : 1   ;
+        UINT32    ecrcerrorstat         : 1   ;
+        UINT32    unsupportedrequesterrorstatus  : 1   ;
+        UINT32    Reserved_31           : 3   ;
+        UINT32    atomicopegressblockedstatus  : 1   ;
+        UINT32    uncorr_err_status     : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP1_U;
+
+
+
+
+typedef union tagAerCap2
+{
+
+    struct
+    {
+        UINT32    Reserved_38           : 1   ;
+        UINT32    Reserved_37           : 3   ;
+        UINT32    datalinkprotocolerrormask  : 1   ;
+        UINT32    surprisedownerrormask  : 1   ;
+        UINT32    Reserved_36           : 6   ;
+        UINT32    poisonedtlpmask       : 1   ;
+        UINT32    flowcontrolprotocolerrormask  : 1   ;
+        UINT32    completiontimeoutmask  : 1   ;
+        UINT32    completerabortmask    : 1   ;
+        UINT32    unexpectedcompletionmask  : 1   ;
+        UINT32    receiveroverflowmask  : 1   ;
+        UINT32    malformedtlpmask      : 1   ;
+        UINT32    ecrcerrormask         : 1   ;
+        UINT32    unsupportedrequesterrormask  : 1   ;
+        UINT32    Reserved_35           : 3   ;
+        UINT32    atomicopegressblockedmask  : 1   ;
+        UINT32    uncorr_err_mask       : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP2_U;
+
+
+
+
+typedef union tagAerCap3
+{
+
+    struct
+    {
+        UINT32    Reserved_42           : 1   ;
+        UINT32    Reserved_41           : 3   ;
+        UINT32    datalinkprotocolerrorsever  : 1   ;
+        UINT32    surprisedownerrorseverity  : 1   ;
+        UINT32    Reserved_40           : 6   ;
+        UINT32    poisonedtlpseverity   : 1   ;
+        UINT32    flowcontrolprotocolerrorseveri  : 1   ;
+        UINT32    completiontimeoutseverity  : 1   ;
+        UINT32    completerabortseverity  : 1   ;
+        UINT32    unexpectedcompletionseverity  : 1   ;
+        UINT32    receiveroverflowseverity  : 1   ;
+        UINT32    malformedtlpseverity  : 1   ;
+        UINT32    ecrcerrorseverity     : 1   ;
+        UINT32    unsupportedrequesterrorseverity  : 1   ;
+        UINT32    Reserved_39           : 3   ;
+        UINT32    atomicopegressblockedseverity  : 1   ;
+        UINT32    uncorr_err_ser        : 7   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP3_U;
+
+
+
+
+typedef union tagAerCap4
+{
+
+    struct
+    {
+        UINT32    receivererrorstatus   : 1   ;
+        UINT32    Reserved_44           : 5   ;
+        UINT32    badtlpstatus          : 1   ;
+        UINT32    baddllpstatus         : 1   ;
+        UINT32    replay_numrolloverstatus  : 1   ;
+        UINT32    Reserved_43           : 3   ;
+        UINT32    replytimertimeoutstatus  : 1   ;
+        UINT32    advisorynon_fatalerrorstatus  : 1   ;
+        UINT32    corr_err_status       : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP4_U;
+
+
+
+
+typedef union tagAerCap5
+{
+
+    struct
+    {
+        UINT32    receivererrormask     : 1   ;
+        UINT32    Reserved_46           : 5   ;
+        UINT32    badtlpmask            : 1   ;
+        UINT32    baddllpmask           : 1   ;
+        UINT32    replay_numrollovermask  : 1   ;
+        UINT32    Reserved_45           : 3   ;
+        UINT32    replytimertimeoutmask  : 1   ;
+        UINT32    advisorynon_fatalerrormask  : 1   ;
+        UINT32    corr_err_mask         : 18  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP5_U;
+
+
+
+
+typedef union tagAerCap6
+{
+
+    struct
+    {
+        UINT32    firsterrorpointer     : 5   ;
+        UINT32    ecrcgenerationcapability  : 1   ;
+        UINT32    ecrcgenerationenable  : 1   ;
+        UINT32    ecrccheckcapable      : 1   ;
+        UINT32    ecrccheckenable       : 1   ;
+        UINT32    adv_cap_ctrl          : 23  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP6_U;
+
+
+
+
+typedef union tagAerCap11
+{
+
+    struct
+    {
+        UINT32    correctableerrorreportingenable  : 1   ;
+        UINT32    non_fatalerrorreportingenable  : 1   ;
+        UINT32    fatalerrorreportingenable  : 1   ;
+        UINT32    root_err_cmd          : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP11_U;
+
+
+
+
+typedef union tagAerCap12
+{
+
+    struct
+    {
+        UINT32    err_correceived       : 1   ;
+        UINT32    multipleerr_correceived  : 1   ;
+        UINT32    err_fatal_nonfatalreceived  : 1   ;
+        UINT32    multipleerr_fatal_nonfatalreceived  : 1   ;
+        UINT32    firstuncorrectablefatal  : 1   ;
+        UINT32    non_fatalerrormessagesreceived  : 1   ;
+        UINT32    fatalerrormessagesreceived  : 1   ;
+        UINT32    Reserved_47           : 20  ;
+        UINT32    root_err_status       : 5   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP12_U;
+
+
+
+
+typedef union tagAerCap13
+{
+
+    struct
+    {
+        UINT32    err_corsourceidentification  : 16  ;
+        UINT32    err_src_id            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_AER_CAP13_U;
+
+
+
+
+typedef union tagVcCap0
+{
+
+    struct
+    {
+        UINT32    pciexpressextendedcapabilityid  : 16  ;
+        UINT32    capabilityversion     : 4   ;
+        UINT32    vc_cap_hdr            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP0_U;
+
+
+
+
+typedef union tagVcCap1
+{
+
+    struct
+    {
+        UINT32    extendedvccount       : 3   ;
+        UINT32    Reserved_50           : 1   ;
+        UINT32    lowpriorityextendedvccount  : 3   ;
+        UINT32    Reserved_49           : 1   ;
+        UINT32    referenceclock        : 2   ;
+        UINT32    portarbitrationtableentrysize  : 2   ;
+        UINT32    vc_cap1               : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP1_U;
+
+
+
+
+typedef union tagVcCap2
+{
+
+    struct
+    {
+        UINT32    vcarbitrationcapability  : 8   ;
+        UINT32    Reserved_51           : 16  ;
+        UINT32    vc_cap2               : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP2_U;
+
+
+
+
+typedef union tagVcCap3
+{
+
+    struct
+    {
+        UINT32    loadvcarbitrationtable  : 1   ;
+        UINT32    vcarbitrationselect   : 3   ;
+        UINT32    Reserved_53           : 12  ;
+        UINT32    arbitrationtablestatus  : 1   ;
+        UINT32    Reserved_52           : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP3_U;
+
+
+
+
+typedef union tagVcCap4
+{
+
+    struct
+    {
+        UINT32    portarbitrationcapability  : 8   ;
+        UINT32    Reserved_56           : 6   ;
+        UINT32    Reserved_55           : 1   ;
+        UINT32    rejectsnooptransactions  : 1   ;
+        UINT32    maximumtimeslots      : 7   ;
+        UINT32    Reserved_54           : 1   ;
+        UINT32    vc_res_cap            : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP4_U;
+
+
+
+
+typedef union tagVcCap5
+{
+
+    struct
+    {
+        UINT32    tc_vcmap              : 8   ;
+        UINT32    Reserved_59           : 8   ;
+        UINT32    loadportarbitrationtable  : 1   ;
+        UINT32    portarbitrationselec  : 3   ;
+        UINT32    Reserved_58           : 4   ;
+        UINT32    vcid                  : 3   ;
+        UINT32    Reserved_57           : 4   ;
+        UINT32    vc_res_ctrl           : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP5_U;
+
+
+
+
+typedef union tagVcCap6
+{
+
+    struct
+    {
+        UINT32    Reserved_60           : 16  ;
+        UINT32    portarbitrationtablestatus  : 1   ;
+        UINT32    vcnegotiationpending  : 1   ;
+        UINT32    vc_res_status         : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP6_U;
+
+
+
+
+typedef union tagVcCap7
+{
+
+    struct
+    {
+        UINT32    portarbitrationcapability  : 8   ;
+        UINT32    Reserved_63           : 6   ;
+        UINT32    Reserved_62           : 1   ;
+        UINT32    rejectsnooptransactions  : 1   ;
+        UINT32    maximumtimeslots      : 7   ;
+        UINT32    Reserved_61           : 1   ;
+        UINT32    vc_res_cap0           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP7_U;
+
+
+
+
+typedef union tagVcCap8
+{
+
+    struct
+    {
+        UINT32    tc_vcmap              : 8   ;
+        UINT32    Reserved_66           : 8   ;
+        UINT32    loadportarbitrationtable  : 1   ;
+        UINT32    portarbitrationselect  : 3   ;
+        UINT32    Reserved_65           : 4   ;
+        UINT32    vcid                  : 3   ;
+        UINT32    Reserved_64           : 4   ;
+        UINT32    vc_res_ctrl0          : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP8_U;
+
+
+
+
+typedef union tagVcCap9
+{
+
+    struct
+    {
+        UINT32    Reserved_67           : 16  ;
+        UINT32    arbitrationtablestatus  : 1   ;
+        UINT32    vcnegotiationpending  : 1   ;
+        UINT32    vc_res_status0        : 14  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_VC_CAP9_U;
+
+
+
+
+typedef union tagPortLogic0
+{
+
+    struct
+    {
+        UINT32    ack_lat_timer         : 16  ;
+        UINT32    replay_timer          : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC0_U;
+
+
+
+
+typedef union tagPortLogic2
+{
+
+    struct
+    {
+        UINT32    linknumber            : 8   ;
+        UINT32    Reserved_70           : 7   ;
+        UINT32    forcelink             : 1   ;
+        UINT32    linkstate             : 6   ;
+        UINT32    Reserved_69           : 2   ;
+        UINT32    port_force_link       : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC2_U;
+
+
+
+
+typedef union tagPortLogic3
+{
+
+    struct
+    {
+        UINT32    ackfrequency          : 8   ;
+        UINT32    n_fts                 : 8   ;
+        UINT32    commonclockn_fts      : 8   ;
+        UINT32    l0sentrancelatency    : 3   ;
+        UINT32    l1entrancelatency     : 3   ;
+        UINT32    enteraspml1withoutreceiveinl0s  : 1   ;
+        UINT32    ack_aspm              : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC3_U;
+
+
+
+
+typedef union tagPortLogic4
+{
+
+    struct
+    {
+        UINT32    vendorspecificdllprequest  : 1   ;
+        UINT32    scrambledisable       : 1   ;
+        UINT32    loopbackenable        : 1   ;
+        UINT32    resetassert           : 1   ;
+        UINT32    Reserved_73           : 1   ;
+        UINT32    dlllinkenable         : 1   ;
+        UINT32    Reserved_72           : 1   ;
+        UINT32    fastlinkmode          : 1   ;
+        UINT32    Reserved_71           : 8   ;
+        UINT32    linkmodeenable        : 6   ;
+        UINT32    crosslinkenable       : 1   ;
+        UINT32    crosslinkactive       : 1   ;
+        UINT32    port_link_ctrl        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC4_U;
+
+
+
+
+typedef union tagPortLogic5
+{
+
+    struct
+    {
+        UINT32    insertlaneskewfortransmit  : 24  ;
+        UINT32    flowcontroldisable    : 1   ;
+        UINT32    ack_nakdisable        : 1   ;
+        UINT32    Reserved_75           : 5   ;
+        UINT32    lane_skew             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC5_U;
+
+
+
+
+typedef union tagPortLogic6
+{
+
+    struct
+    {
+        UINT32    numberoftssymbols     : 4   ;
+        UINT32    Reserved_77           : 4   ;
+        UINT32    numberofskpsymbols    : 3   ;
+        UINT32    Reserved_76           : 3   ;
+        UINT32    timermodifierforreplaytimer  : 5   ;
+        UINT32    timermodifierforack_naklatencytimer  : 5   ;
+        UINT32    timermodifierforflowcontrolwatchdogtimer  : 5   ;
+        UINT32    sym_num               : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC6_U;
+
+
+
+
+typedef union tagPortLogic7
+{
+
+    struct
+    {
+        UINT32    vc0posteddataqueuedepth  : 11  ;
+        UINT32    Reserved_78           : 4   ;
+        UINT32    sym_timer             : 1   ;
+        UINT32    maskfunctionmismatchfilteringfo  : 1   ;
+        UINT32    maskpoisonedtlpfiltering  : 1   ;
+        UINT32    maskbarmatchfiltering  : 1   ;
+        UINT32    masktype1configurationrequestfiltering  : 1   ;
+        UINT32    masklockedrequestfiltering  : 1   ;
+        UINT32    masktagerrorrulesforreceivedcompletions  : 1   ;
+        UINT32    maskrequesteridmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    maskfunctionmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    mask_traffic_classmis_match_error_forreceived_completions  : 1   ;
+        UINT32    mask_attributesmismatcherrorforreceivedcompletions  : 1   ;
+        UINT32    mask_length_mismatch_error_forreceive_dcompletions  : 1   ;
+        UINT32    maske_crcerror_filtering  : 1   ;
+        UINT32    maske_crcerror_filtering_forcompletions  : 1   ;
+        UINT32    message_control       : 1   ;
+        UINT32    maskfilteringofreceived  : 1   ;
+        UINT32    flt_mask1             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC7_U;
+
+
+
+
+typedef union tagPortLogic8
+{
+
+    struct
+    {
+        UINT32    cx_flt_mask_venmsg0_drop  : 1   ;
+        UINT32    cx_flt_mask_venmsg1_drop  : 1   ;
+        UINT32    cx_flt_mask_dabort_4ucpl  : 1   ;
+        UINT32    cx_flt_mask_handle_flush  : 1   ;
+        UINT32    flt_mask2             : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC8_U;
+
+
+
+
+typedef union tagPortLogic9
+{
+
+    struct
+    {
+        UINT32    amba_multi_outbound_decomp_np  : 1   ;
+        UINT32    amba_obnp_ctrl        : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC9_U;
+
+
+
+
+typedef union tagPortLogic12
+{
+
+    struct
+    {
+        UINT32    transmitposteddatafccredits  : 12  ;
+        UINT32    transmitpostedheaderfccredits  : 8   ;
+        UINT32    tx_pfc_status         : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC12_U;
+
+
+
+
+typedef union tagPortLogic13
+{
+
+    struct
+    {
+        UINT32    transmitnon_posteddatafccredits  : 12  ;
+        UINT32    transmitnon_postedheaderfccredits  : 8   ;
+        UINT32    tx_npfc_status        : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC13_U;
+
+
+
+
+typedef union tagPortLogic14
+{
+
+    struct
+    {
+        UINT32    transmitcompletiondatafccredits  : 12  ;
+        UINT32    transmitcompletionheaderfccredits  : 8   ;
+        UINT32    tx_cplfc_status       : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC14_U;
+
+
+
+
+typedef union tagPortLogic15
+{
+
+    struct
+    {
+        UINT32    rx_tlp_fc_credit_not_retured  : 1   ;
+        UINT32    tx_retry_buf_not_empty  : 1   ;
+        UINT32    rx_queue_not_empty    : 1   ;
+        UINT32    Reserved_80           : 13  ;
+        UINT32    fc_latency_timer_override_value  : 13  ;
+        UINT32    Reserved_79           : 2   ;
+        UINT32    fc_latency_timer_override_en  : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC15_U;
+
+
+
+
+typedef union tagPortLogic16
+{
+
+    struct
+    {
+        UINT32    vc0posteddatacredits  : 12  ;
+        UINT32    vc0postedheadercredits  : 8   ;
+        UINT32    Reserved_82           : 1   ;
+        UINT32    vc0_postedtlpqueuemode  : 1   ;
+        UINT32    vc0postedtlpqueuemode  : 1   ;
+        UINT32    vc0postedtlpqueuemo   : 1   ;
+        UINT32    Reserved_81           : 6   ;
+        UINT32    tlptypeorderingforvc0  : 1   ;
+        UINT32    rx_pque_ctrl          : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC16_U;
+
+
+
+
+typedef union tagPortLogic17
+{
+
+    struct
+    {
+        UINT32    vc0non_posteddatacredits  : 12  ;
+        UINT32    vc0non_postedheadercredits  : 8   ;
+        UINT32    rx_npque_ctrl         : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC17_U;
+
+
+
+
+typedef union tagPortLogic18
+{
+
+    struct
+    {
+        UINT32    vco_comp_data_credits  : 12  ;
+        UINT32    vc0_cpl_header_credt  : 8   ;
+        UINT32    Reserved_84           : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC18_U;
+
+
+
+
+typedef union tagPortLogic19
+{
+
+    struct
+    {
+        UINT32    vco_posted_data_que_path  : 14  ;
+        UINT32    Reserved_85           : 2   ;
+        UINT32    vco_posted_head_queue_depth  : 10  ;
+        UINT32    vc_pbuf_ctrl          : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC19_U;
+
+
+
+
+typedef union tagPortLogic20
+{
+
+    struct
+    {
+        UINT32    vco_np_data_que_depth  : 14  ;
+        UINT32    Reserved_87           : 2   ;
+        UINT32    vco_np_header_que_depth  : 10  ;
+        UINT32    vc_npbuf_ctrl         : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC20_U;
+
+
+
+
+typedef union tagPortLogic21
+{
+
+    struct
+    {
+        UINT32    vco_comp_data_queue_depth  : 14  ;
+        UINT32    Reserved_89           : 2   ;
+        UINT32    vco_posted_head_queue_depth  : 10  ;
+        UINT32    Reserved_88           : 6   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC21_U;
+
+
+
+
+typedef union tagPortLogic22
+{
+
+    struct
+    {
+        UINT32    n_fts                 : 8   ;
+        UINT32    pre_determ_num_of_lane  : 9   ;
+        UINT32    det_sp_change         : 1   ;
+        UINT32    config_phy_tx_sw      : 1   ;
+        UINT32    config_tx_comp_rcv_bit  : 1   ;
+        UINT32    set_emp_level         : 1   ;
+        UINT32    Reserved_90           : 11  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORT_LOGIC22_U;
+
+
+
+
+typedef union tagPortlogic25
+{
+
+    struct
+    {
+        UINT32    remote_rd_req_size    : 3   ;
+        UINT32    Reserved_93           : 5   ;
+        UINT32    remote_max_brd_tag    : 8   ;
+        UINT32    Reserved_92           : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC25_U;
+
+
+
+
+typedef union tagPortlogic26
+{
+
+    struct
+    {
+        UINT32    resize_master_resp_compser  : 1   ;
+        UINT32    axi_ctrl1             : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC26_U;
+
+
+
+
+typedef union tagPortlogic54
+{
+
+    struct
+    {
+        UINT32    region_index          : 4   ;
+        UINT32    Reserved_94           : 27  ;
+        UINT32    iatu_view             : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC54_U;
+
+
+
+
+typedef union tagPortlogic55
+{
+
+    struct
+    {
+        UINT32    iatu1_type            : 5   ;
+        UINT32    iatu1_tc              : 3   ;
+        UINT32    iatu1_td              : 1   ;
+        UINT32    iatu1_attr            : 2   ;
+        UINT32    Reserved_98           : 5   ;
+        UINT32    iatu1_at              : 2   ;
+        UINT32    Reserved_97           : 2   ;
+        UINT32    iatu1_id              : 3   ;
+        UINT32    Reserved_96           : 9   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC55_U;
+
+
+
+
+typedef union tagPortlogic56
+{
+
+    struct
+    {
+        UINT32    iatu2_type            : 8   ;
+        UINT32    iatu2_bar_num         : 3   ;
+        UINT32    Reserved_102          : 3   ;
+        UINT32    iatu2_tc_match_en     : 1   ;
+        UINT32    iatu2_td_match_en     : 1   ;
+        UINT32    iatu2_attr_match_en   : 1   ;
+        UINT32    Reserved_101          : 1   ;
+        UINT32    iatu2_at_match_en     : 1   ;
+        UINT32    iatu2_func_num_match_en  : 1   ;
+        UINT32    iatu2_virtual_func_num_match_en  : 1   ;
+        UINT32    message_code_match_en  : 1   ;
+        UINT32    Reserved_100          : 2   ;
+        UINT32    iatu2_response_code   : 2   ;
+        UINT32    Reserved_99           : 1   ;
+        UINT32    iatu2_fuzzy_type_match_mode  : 1   ;
+        UINT32    iatu2_cfg_shift_mode  : 1   ;
+        UINT32    iatu2_ivert_mode      : 1   ;
+        UINT32    iatu2_match_mode      : 1   ;
+        UINT32    iatu2_region_en       : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC56_U;
+
+
+
+
+typedef union tagPortlogic57
+{
+
+    struct
+    {
+        UINT32    iatu_start_low        : 12  ;
+        UINT32    iatu_start_high       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC57_U;
+
+
+
+
+typedef union tagPortlogic59
+{
+
+    struct
+    {
+        UINT32    iatu_limit_low        : 12  ;
+        UINT32    iatu_limit_high       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC59_U;
+
+
+
+
+typedef union tagPortlogic60
+{
+
+    struct
+    {
+        UINT32    xlated_addr_high      : 12  ;
+        UINT32    xlated_addr_low       : 20  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC60_U;
+
+
+
+
+typedef union tagPortlogic62
+{
+
+    struct
+    {
+        UINT32    dma_wr_eng_en         : 1   ;
+        UINT32    dma_wr_ena            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC62_U;
+
+
+
+
+typedef union tagPortlogic63
+{
+
+    struct
+    {
+        UINT32    wr_doorbell_num       : 3   ;
+        UINT32    Reserved_104          : 28  ;
+        UINT32    dma_wr_dbell_stop     : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC63_U;
+
+
+
+
+typedef union tagPortlogic64
+{
+
+    struct
+    {
+        UINT32    dma_read_eng_en       : 1   ;
+        UINT32    Reserved_105          : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC64_U;
+
+
+
+
+typedef union tagPortlogic65
+{
+
+    struct
+    {
+        UINT32    rd_doorbell_num       : 3   ;
+        UINT32    Reserved_107          : 28  ;
+        UINT32    dma_rd_dbell_stop     : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC65_U;
+
+
+
+
+typedef union tagPortlogic66
+{
+
+    struct
+    {
+        UINT32    done_int_status       : 8   ;
+        UINT32    Reserved_109          : 8   ;
+        UINT32    abort_int_status      : 8   ;
+        UINT32    Reserved_108          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC66_U;
+
+
+
+
+typedef union tagPortlogic67
+{
+
+    struct
+    {
+        UINT32    done_int_mask         : 8   ;
+        UINT32    Reserved_112          : 8   ;
+        UINT32    abort_int_mask        : 8   ;
+        UINT32    Reserved_111          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC67_U;
+
+
+
+
+typedef union tagPortlogic68
+{
+
+    struct
+    {
+        UINT32    done_int_clr          : 8   ;
+        UINT32    Reserved_115          : 8   ;
+        UINT32    abort_int_clr         : 8   ;
+        UINT32    Reserved_114          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC68_U;
+
+
+
+
+typedef union tagPortlogic69
+{
+
+    struct
+    {
+        UINT32    app_rd_err_det        : 8   ;
+        UINT32    Reserved_117          : 8   ;
+        UINT32    ll_element_fetch_err_det  : 8   ;
+        UINT32    Reserved_116          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC69_U;
+
+
+
+
+typedef union tagPortlogic74
+{
+
+    struct
+    {
+        UINT32    dma_wr_c0_imwr_data   : 16  ;
+        UINT32    dma_wr_c1_imwr_data   : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC74_U;
+
+
+
+
+typedef union tagPortlogic75
+{
+
+    struct
+    {
+        UINT32    wr_ch_ll_remote_abort_int_en  : 8   ;
+        UINT32    Reserved_119          : 8   ;
+        UINT32    wr_ch_ll_local_abort_int_en  : 8   ;
+        UINT32    Reserved_118          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC75_U;
+
+
+
+
+typedef union tagPortlogic76
+{
+
+    struct
+    {
+        UINT32    done_int_status       : 8   ;
+        UINT32    Reserved_122          : 8   ;
+        UINT32    abort_int_status      : 8   ;
+        UINT32    Reserved_121          : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC76_U;
+
+
+
+
+typedef union tagPortlogic77
+{
+
+    struct
+    {
+        UINT32    done_int_mask         : 8   ;
+        UINT32    Reserved_124          : 8   ;
+        UINT32    abort_int_mask        : 8   ;
+        UINT32    dma_rd_int_mask       : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC77_U;
+
+
+
+
+typedef union tagPortlogic78
+{
+
+    struct
+    {
+        UINT32    done_int_clr          : 8   ;
+        UINT32    Reserved_126          : 8   ;
+        UINT32    abort_int_clr         : 8   ;
+        UINT32    dma_rd_int_clr        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC78_U;
+
+
+
+
+typedef union tagPortlogic79
+{
+
+    struct
+    {
+        UINT32    app_wr_err_det        : 8   ;
+        UINT32    Reserved_127          : 8   ;
+        UINT32    link_list_fetch_err_det  : 8   ;
+        UINT32    dma_rd_err_low        : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC79_U;
+
+
+
+
+typedef union tagPortlogic80
+{
+
+    struct
+    {
+        UINT32    unspt_request         : 8   ;
+        UINT32    completer_abort       : 8   ;
+        UINT32    cpl_time_out          : 8   ;
+        UINT32    data_poison           : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC80_U;
+
+
+
+
+typedef union tagPortlogic81
+{
+
+    struct
+    {
+        UINT32    remote_abort_int_en   : 8   ;
+        UINT32    Reserved_129          : 8   ;
+        UINT32    local_abort_int_en    : 8   ;
+        UINT32    dma_rd_ll_err_ena     : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC81_U;
+
+
+
+
+typedef union tagPortlogic86
+{
+
+    struct
+    {
+        UINT32    channel_dir           : 3   ;
+        UINT32    Reserved_132          : 28  ;
+        UINT32    dma_ch_con_idx        : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC86_U;
+
+
+
+
+typedef union tagPortlogic87
+{
+
+    struct
+    {
+        UINT32    cycle_bit             : 1   ;
+        UINT32    toggle_cycle_bit      : 1   ;
+        UINT32    load_link_pointer     : 1   ;
+        UINT32    local_int_en          : 1   ;
+        UINT32    remote_int_en         : 1   ;
+        UINT32    channel_status        : 2   ;
+        UINT32    Reserved_136          : 1   ;
+        UINT32    consumer_cycle_state  : 1   ;
+        UINT32    linked_list_en        : 1   ;
+        UINT32    Reserved_135          : 2   ;
+        UINT32    func_num_dma          : 5   ;
+        UINT32    Reserved_134          : 7   ;
+        UINT32    no_snoop              : 1   ;
+        UINT32    ro                    : 1   ;
+        UINT32    td                    : 1   ;
+        UINT32    tc                    : 3   ;
+        UINT32    dma_ch_ctrl           : 2   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC87_U;
+
+
+
+
+typedef union tagPortlogic93
+{
+
+    struct
+    {
+        UINT32    Reserved_138          : 2   ;
+        UINT32    dma_ll_ptr_low        : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} PCIE_EP_PORTLOGIC93_U;
+
+
+#define PCIE_SUBCTRL_BASE                       (0x0)
+
+
+
+
+
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG                   (PCIE_SUBCTRL_BASE + 0x300)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(port_id) \
+  (PCIE_SUBCTRL_SC_PCIE0_CLK_EN_REG + (port_id << 3))
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG                  (PCIE_SUBCTRL_BASE + 0x304)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(port_id) \
+  (PCIE_SUBCTRL_SC_PCIE0_CLK_DIS_REG + (port_id << 3))
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_EN_REG                   (PCIE_SUBCTRL_BASE + 0x308)
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_DIS_REG                  (PCIE_SUBCTRL_BASE + 0x30C)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_EN_REG                   (PCIE_SUBCTRL_BASE + 0x310)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_DIS_REG                  (PCIE_SUBCTRL_BASE + 0x314)
+#define PCIE_SUBCTRL_SC_SAS_CLK_EN_REG                     (PCIE_SUBCTRL_BASE + 0x318)
+#define PCIE_SUBCTRL_SC_SAS_CLK_DIS_REG                    (PCIE_SUBCTRL_BASE + 0x31C)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG                   (PCIE_SUBCTRL_BASE + 0x320)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG                  (PCIE_SUBCTRL_BASE + 0x324)
+#define PCIE_SUBCTRL_SC_ITS_CLK_EN_REG                     (PCIE_SUBCTRL_BASE + 0x328)
+#define PCIE_SUBCTRL_SC_ITS_CLK_DIS_REG                    (PCIE_SUBCTRL_BASE + 0x32C)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_EN_REG                    (PCIE_SUBCTRL_BASE + 0x360)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_DIS_REG                   (PCIE_SUBCTRL_BASE + 0x364)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG                (PCIE_SUBCTRL_BASE + 0xA00)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG               (PCIE_SUBCTRL_BASE + 0xA04)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_REQ_REG                (PCIE_SUBCTRL_BASE + 0xA08)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_DREQ_REG               (PCIE_SUBCTRL_BASE + 0xA0C)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_REQ_REG                (PCIE_SUBCTRL_BASE + 0xA10)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_DREQ_REG               (PCIE_SUBCTRL_BASE + 0xA14)
+#define PCIE_SUBCTRL_SC_SAS_RESET_REQ_REG                  (PCIE_SUBCTRL_BASE + 0xA18)
+#define PCIE_SUBCTRL_SC_SAS_RESET_DREQ_REG                 (PCIE_SUBCTRL_BASE + 0xA1C)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_REQ_REG                (PCIE_SUBCTRL_BASE + 0xA20)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_DREQ_REG               (PCIE_SUBCTRL_BASE + 0xA24)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_REQ_REG                (PCIE_SUBCTRL_BASE + 0xA28)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_DREQ_REG               (PCIE_SUBCTRL_BASE + 0xA2C)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_REQ_REG                (PCIE_SUBCTRL_BASE + 0xA30)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_DREQ_REG               (PCIE_SUBCTRL_BASE + 0xA34)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_REQ_REG           (PCIE_SUBCTRL_BASE + 0xA58)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_DREQ_REG          (PCIE_SUBCTRL_BASE + 0xA5C)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG      (PCIE_SUBCTRL_BASE + 0xA60)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG     (PCIE_SUBCTRL_BASE + 0xA64)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG                (PCIE_SUBCTRL_BASE + 0xA68)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG               (PCIE_SUBCTRL_BASE + 0xA6C)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_REQ_REG                (PCIE_SUBCTRL_BASE + 0xA70)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_DREQ_REG               (PCIE_SUBCTRL_BASE + 0xA74)
+#define PCIE_SUBCTRL_SC_ITS_RESET_REQ_REG                  (PCIE_SUBCTRL_BASE + 0xA80)
+#define PCIE_SUBCTRL_SC_ITS_RESET_DREQ_REG                 (PCIE_SUBCTRL_BASE + 0xA84)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_REQ_REG                 (PCIE_SUBCTRL_BASE + 0xAA0)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_DREQ_REG                (PCIE_SUBCTRL_BASE + 0xAA4)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG            (PCIE_SUBCTRL_BASE + 0xAC0)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG           (PCIE_SUBCTRL_BASE + 0xAC4)
+#define PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG              (PCIE_SUBCTRL_BASE + 0xAC8)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG                    (PCIE_SUBCTRL_BASE + 0x1000)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY0_REG            (PCIE_SUBCTRL_BASE + 0x1004)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY1_REG            (PCIE_SUBCTRL_BASE + 0x1008)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY2_REG            (PCIE_SUBCTRL_BASE + 0x100C)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG            (PCIE_SUBCTRL_BASE + 0x1010)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG            (PCIE_SUBCTRL_BASE + 0x1014)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG            (PCIE_SUBCTRL_BASE + 0x1018)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG            (PCIE_SUBCTRL_BASE + 0x101C)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG            (PCIE_SUBCTRL_BASE + 0x1020)
+#define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG         (PCIE_SUBCTRL_BASE + 0x1030)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG               (PCIE_SUBCTRL_BASE + 0x1100)
+#define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG                (PCIE_SUBCTRL_BASE + 0x1104)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTSTAT_REG               (PCIE_SUBCTRL_BASE + 0x1108)
+#define PCIE_SUBCTRL_SC_DISPATCH_INTCLR_REG                (PCIE_SUBCTRL_BASE + 0x110C)
+#define PCIE_SUBCTRL_SC_DISPATCH_ERRSTAT_REG               (PCIE_SUBCTRL_BASE + 0x1110)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG                     (PCIE_SUBCTRL_BASE + 0x1200)
+#define PCIE_SUBCTRL_SC_FTE_MUX_CTRL_REG                   (PCIE_SUBCTRL_BASE + 0x2200)
+#define PCIE_SUBCTRL_SC_HILINK0_MUX_CTRL_REG               (PCIE_SUBCTRL_BASE + 0x2300)
+#define PCIE_SUBCTRL_SC_HILINK1_MUX_CTRL_REG               (PCIE_SUBCTRL_BASE + 0x2304)
+#define PCIE_SUBCTRL_SC_HILINK2_MUX_CTRL_REG               (PCIE_SUBCTRL_BASE + 0x2308)
+#define PCIE_SUBCTRL_SC_HILINK5_MUX_CTRL_REG               (PCIE_SUBCTRL_BASE + 0x2314)
+#define PCIE_SUBCTRL_SC_HILINK1_AHB_MUX_CTRL_REG           (PCIE_SUBCTRL_BASE + 0x2324)
+#define PCIE_SUBCTRL_SC_HILINK2_AHB_MUX_CTRL_REG           (PCIE_SUBCTRL_BASE + 0x2328)
+#define PCIE_SUBCTRL_SC_HILINK5_AHB_MUX_CTRL_REG           (PCIE_SUBCTRL_BASE + 0x2334)
+#define PCIE_SUBCTRL_SC_HILINK5_LRSTB_MUX_CTRL_REG         (PCIE_SUBCTRL_BASE + 0x2340)
+#define PCIE_SUBCTRL_SC_HILINK6_LRSTB_MUX_CTRL_REG         (PCIE_SUBCTRL_BASE + 0x2344)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_SS_REFCLK_REG        (PCIE_SUBCTRL_BASE + 0x2400)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2404)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LIFECLK2DIG_SEL_REG  (PCIE_SUBCTRL_BASE + 0x2408)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SELEXT_REG  (PCIE_SUBCTRL_BASE + 0x240C)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CORE_CLK_SEL_REG     (PCIE_SUBCTRL_BASE + 0x2410)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_CTRL_BUS_MODE_REG    (PCIE_SUBCTRL_BASE + 0x2414)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_MACROPWRDB_REG       (PCIE_SUBCTRL_BASE + 0x2418)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_GRSTB_REG            (PCIE_SUBCTRL_BASE + 0x241C)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_BIT_SLIP_REG         (PCIE_SUBCTRL_BASE + 0x2420)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LRSTB_REG            (PCIE_SUBCTRL_BASE + 0x2424)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_SS_REFCLK_REG        (PCIE_SUBCTRL_BASE + 0x2500)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2504)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LIFECLK2DIG_SEL_REG  (PCIE_SUBCTRL_BASE + 0x2508)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SELEXT_REG  (PCIE_SUBCTRL_BASE + 0x250C)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CORE_CLK_SEL_REG     (PCIE_SUBCTRL_BASE + 0x2510)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_CTRL_BUS_MODE_REG    (PCIE_SUBCTRL_BASE + 0x2514)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_MACROPWRDB_REG       (PCIE_SUBCTRL_BASE + 0x2518)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_GRSTB_REG            (PCIE_SUBCTRL_BASE + 0x251C)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_BIT_SLIP_REG         (PCIE_SUBCTRL_BASE + 0x2520)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LRSTB_REG            (PCIE_SUBCTRL_BASE + 0x2524)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_SS_REFCLK_REG        (PCIE_SUBCTRL_BASE + 0x2600)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2604)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LIFECLK2DIG_SEL_REG  (PCIE_SUBCTRL_BASE + 0x2608)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SELEXT_REG  (PCIE_SUBCTRL_BASE + 0x260C)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CORE_CLK_SEL_REG     (PCIE_SUBCTRL_BASE + 0x2610)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_CTRL_BUS_MODE_REG    (PCIE_SUBCTRL_BASE + 0x2614)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_MACROPWRDB_REG       (PCIE_SUBCTRL_BASE + 0x2618)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_GRSTB_REG            (PCIE_SUBCTRL_BASE + 0x261C)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_BIT_SLIP_REG         (PCIE_SUBCTRL_BASE + 0x2620)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LRSTB_REG            (PCIE_SUBCTRL_BASE + 0x2624)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_SS_REFCLK_REG        (PCIE_SUBCTRL_BASE + 0x2700)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CS_REFCLK_DIRSEL_REG (PCIE_SUBCTRL_BASE + 0x2704)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LIFECLK2DIG_SEL_REG  (PCIE_SUBCTRL_BASE + 0x2708)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SELEXT_REG  (PCIE_SUBCTRL_BASE + 0x270C)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CORE_CLK_SEL_REG     (PCIE_SUBCTRL_BASE + 0x2710)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_CTRL_BUS_MODE_REG    (PCIE_SUBCTRL_BASE + 0x2714)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_MACROPWRDB_REG       (PCIE_SUBCTRL_BASE + 0x2718)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_GRSTB_REG            (PCIE_SUBCTRL_BASE + 0x271C)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_BIT_SLIP_REG         (PCIE_SUBCTRL_BASE + 0x2720)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LRSTB_REG            (PCIE_SUBCTRL_BASE + 0x2724)
+#define PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG                   (PCIE_SUBCTRL_BASE + 0x2800)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_CFG_REG      (PCIE_SUBCTRL_BASE + 0x2880)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_CFG_REG      (PCIE_SUBCTRL_BASE + 0x2890)
+#define PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG                   (PCIE_SUBCTRL_BASE + 0x2900)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_CFG_REG      (PCIE_SUBCTRL_BASE + 0x2980)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_CFG_REG      (PCIE_SUBCTRL_BASE + 0x2990)
+#define PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG                   (PCIE_SUBCTRL_BASE + 0x2A00)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_CFG_REG      (PCIE_SUBCTRL_BASE + 0x2A80)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_CFG_REG      (PCIE_SUBCTRL_BASE + 0x2A90)
+#define PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG                   (PCIE_SUBCTRL_BASE + 0x2B00)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL0_REG                 (PCIE_SUBCTRL_BASE + 0x3000)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL1_REG                 (PCIE_SUBCTRL_BASE + 0x3004)
+#define PCIE_SUBCTRL_SC_SMMU_MEM_CTRL2_REG                 (PCIE_SUBCTRL_BASE + 0x3008)
+#define PCIE_SUBCTRL_SC_SLLC0_MEM_CTRL_REG                 (PCIE_SUBCTRL_BASE + 0x3010)
+#define PCIE_SUBCTRL_SC_SAS_MEM_CTRL_REG                   (PCIE_SUBCTRL_BASE + 0x3030)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL0_REG                 (PCIE_SUBCTRL_BASE + 0x3040)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL1_REG                 (PCIE_SUBCTRL_BASE + 0x3044)
+#define PCIE_SUBCTRL_SC_PCIE_MEM_CTRL2_REG                 (PCIE_SUBCTRL_BASE + 0x3048)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_0_REG                  (PCIE_SUBCTRL_BASE + 0x3400)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_1_REG                  (PCIE_SUBCTRL_BASE + 0x3404)
+#define PCIE_SUBCTRL_SC_SKEW_COMMON_2_REG                  (PCIE_SUBCTRL_BASE + 0x3408)
+#define PCIE_SUBCTRL_SC_SKEW_A_0_REG                       (PCIE_SUBCTRL_BASE + 0x3500)
+#define PCIE_SUBCTRL_SC_SKEW_A_1_REG                       (PCIE_SUBCTRL_BASE + 0x3504)
+#define PCIE_SUBCTRL_SC_SKEW_A_2_REG                       (PCIE_SUBCTRL_BASE + 0x3508)
+#define PCIE_SUBCTRL_SC_SKEW_A_3_REG                       (PCIE_SUBCTRL_BASE + 0x350C)
+#define PCIE_SUBCTRL_SC_SKEW_A_4_REG                       (PCIE_SUBCTRL_BASE + 0x3510)
+#define PCIE_SUBCTRL_SC_SKEW_A_5_REG                       (PCIE_SUBCTRL_BASE + 0x3514)
+#define PCIE_SUBCTRL_SC_SKEW_A_6_REG                       (PCIE_SUBCTRL_BASE + 0x3518)
+#define PCIE_SUBCTRL_SC_SKEW_A_7_REG                       (PCIE_SUBCTRL_BASE + 0x351C)
+#define PCIE_SUBCTRL_SC_SKEW_A_8_REG                       (PCIE_SUBCTRL_BASE + 0x3520)
+#define PCIE_SUBCTRL_SC_SKEW_B_0_REG                       (PCIE_SUBCTRL_BASE + 0x3600)
+#define PCIE_SUBCTRL_SC_SKEW_B_1_REG                       (PCIE_SUBCTRL_BASE + 0x3604)
+#define PCIE_SUBCTRL_SC_SKEW_B_2_REG                       (PCIE_SUBCTRL_BASE + 0x3608)
+#define PCIE_SUBCTRL_SC_SKEW_B_3_REG                       (PCIE_SUBCTRL_BASE + 0x360C)
+#define PCIE_SUBCTRL_SC_SKEW_B_4_REG                       (PCIE_SUBCTRL_BASE + 0x3610)
+#define PCIE_SUBCTRL_SC_SKEW_B_5_REG                       (PCIE_SUBCTRL_BASE + 0x3614)
+#define PCIE_SUBCTRL_SC_SKEW_B_6_REG                       (PCIE_SUBCTRL_BASE + 0x3618)
+#define PCIE_SUBCTRL_SC_SKEW_B_7_REG                       (PCIE_SUBCTRL_BASE + 0x361C)
+#define PCIE_SUBCTRL_SC_SKEW_B_8_REG                       (PCIE_SUBCTRL_BASE + 0x3620)
+#define PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG                   (PCIE_SUBCTRL_BASE + 0x5300)
+#define PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(port_id) \
+  (PCIE_SUBCTRL_SC_PCIE0_CLK_ST_REG + (port_id << 2))
+#define PCIE_SUBCTRL_SC_PCIE1_CLK_ST_REG                   (PCIE_SUBCTRL_BASE + 0x5304)
+#define PCIE_SUBCTRL_SC_PCIE2_CLK_ST_REG                   (PCIE_SUBCTRL_BASE + 0x5308)
+#define PCIE_SUBCTRL_SC_SAS_CLK_ST_REG                     (PCIE_SUBCTRL_BASE + 0x530C)
+#define PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG                   (PCIE_SUBCTRL_BASE + 0x5310)
+#define PCIE_SUBCTRL_SC_ITS_CLK_ST_REG                     (PCIE_SUBCTRL_BASE + 0x5314)
+#define PCIE_SUBCTRL_SC_SLLC_CLK_ST_REG                    (PCIE_SUBCTRL_BASE + 0x5330)
+#define PCIE_SUBCTRL_SC_PCIE0_RESET_ST_REG                 (PCIE_SUBCTRL_BASE + 0x5A00)
+#define PCIE_SUBCTRL_SC_PCIE1_RESET_ST_REG                 (PCIE_SUBCTRL_BASE + 0x5A04)
+#define PCIE_SUBCTRL_SC_PCIE2_RESET_ST_REG                 (PCIE_SUBCTRL_BASE + 0x5A08)
+#define PCIE_SUBCTRL_SC_SAS_RESET_ST_REG                   (PCIE_SUBCTRL_BASE + 0x5A0C)
+#define PCIE_SUBCTRL_SC_MCTP0_RESET_ST_REG                 (PCIE_SUBCTRL_BASE + 0x5A10)
+#define PCIE_SUBCTRL_SC_MCTP1_RESET_ST_REG                 (PCIE_SUBCTRL_BASE + 0x5A14)
+#define PCIE_SUBCTRL_SC_MCTP2_RESET_ST_REG                 (PCIE_SUBCTRL_BASE + 0x5A18)
+#define PCIE_SUBCTRL_SC_SLLC_TSVRX_RESET_ST_REG            (PCIE_SUBCTRL_BASE + 0x5A2C)
+#define PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG       (PCIE_SUBCTRL_BASE + 0x5A30)
+#define PCIE_SUBCTRL_SC_PCIE3_RESET_ST_REG                 (PCIE_SUBCTRL_BASE + 0x5A34)
+#define PCIE_SUBCTRL_SC_MCTP3_RESET_ST_REG                 (PCIE_SUBCTRL_BASE + 0x5A38)
+#define PCIE_SUBCTRL_SC_ITS_RESET_ST_REG                   (PCIE_SUBCTRL_BASE + 0x5A40)
+#define PCIE_SUBCTRL_SC_SLLC_RESET_ST_REG                  (PCIE_SUBCTRL_BASE + 0x5A50)
+#define PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG             (PCIE_SUBCTRL_BASE + 0x5A60)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_PLLOUTOFLOCK_REG     (PCIE_SUBCTRL_BASE + 0x6400)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_PRBS_ERR_REG         (PCIE_SUBCTRL_BASE + 0x6404)
+#define PCIE_SUBCTRL_SC_HILINK0_MACRO_LOS_REG              (PCIE_SUBCTRL_BASE + 0x6408)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_PLLOUTOFLOCK_REG     (PCIE_SUBCTRL_BASE + 0x6500)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_PRBS_ERR_REG         (PCIE_SUBCTRL_BASE + 0x6504)
+#define PCIE_SUBCTRL_SC_HILINK1_MACRO_LOS_REG              (PCIE_SUBCTRL_BASE + 0x6508)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_PLLOUTOFLOCK_REG     (PCIE_SUBCTRL_BASE + 0x6600)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_PRBS_ERR_REG         (PCIE_SUBCTRL_BASE + 0x6604)
+#define PCIE_SUBCTRL_SC_HILINK5_MACRO_LOS_REG              (PCIE_SUBCTRL_BASE + 0x6608)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_PLLOUTOFLOCK_REG     (PCIE_SUBCTRL_BASE + 0x6700)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_PRBS_ERR_REG         (PCIE_SUBCTRL_BASE + 0x6704)
+#define PCIE_SUBCTRL_SC_HILINK6_MACRO_LOS_REG              (PCIE_SUBCTRL_BASE + 0x6708)
+#define PCIE_SUBCTRL_SC_PCIE0_RXEQINPRO_STAT_REG           (PCIE_SUBCTRL_BASE + 0x6800)
+#define PCIE_SUBCTRL_SC_PCIE0_LINKINT_RCVRY_STAT_REG       (PCIE_SUBCTRL_BASE + 0x6804)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE0_REG               (PCIE_SUBCTRL_BASE + 0x6808)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE1_REG               (PCIE_SUBCTRL_BASE + 0x680C)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE2_REG               (PCIE_SUBCTRL_BASE + 0x6810)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG               (PCIE_SUBCTRL_BASE + 0x6814)
+#define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG               (PCIE_SUBCTRL_BASE + 0x6818)
+#define PCIE_LTSSM_STATE_MASK  (0x3f)
+#define PCIE_LTSSM_LINKUP_STATE  (0x11)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG     (PCIE_SUBCTRL_BASE + 0x6880)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG     (PCIE_SUBCTRL_BASE + 0x6884)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS0_REG     (PCIE_SUBCTRL_BASE + 0x6890)
+#define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS1_REG     (PCIE_SUBCTRL_BASE + 0x6894)
+#define PCIE_SUBCTRL_SC_PCIE0_DSIZE_BRG_ECC_ERR_REG        (PCIE_SUBCTRL_BASE + 0x68A0)
+#define PCIE_SUBCTRL_SC_PCIE0_PCIEPHY_CTRL_ERROR_REG       (PCIE_SUBCTRL_BASE + 0x68C0)
+#define PCIE_SUBCTRL_SC_PCIE1_RXEQINPRO_STAT_REG           (PCIE_SUBCTRL_BASE + 0x6900)
+#define PCIE_SUBCTRL_SC_PCIE1_LINKINT_RCVRY_STAT_REG       (PCIE_SUBCTRL_BASE + 0x6904)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE0_REG               (PCIE_SUBCTRL_BASE + 0x6908)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE1_REG               (PCIE_SUBCTRL_BASE + 0x690C)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE2_REG               (PCIE_SUBCTRL_BASE + 0x6910)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE3_REG               (PCIE_SUBCTRL_BASE + 0x6914)
+#define PCIE_SUBCTRL_SC_PCIE1_SYS_STATE4_REG               (PCIE_SUBCTRL_BASE + 0x6918)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS0_REG     (PCIE_SUBCTRL_BASE + 0x6980)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_WR_STS1_REG     (PCIE_SUBCTRL_BASE + 0x6984)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS0_REG     (PCIE_SUBCTRL_BASE + 0x6990)
+#define PCIE_SUBCTRL_SC_PCIE1_AXI_MSTR_OOO_RD_STS1_REG     (PCIE_SUBCTRL_BASE + 0x6994)
+#define PCIE_SUBCTRL_SC_PCIE1_DSIZE_BRG_ECC_ERR_REG        (PCIE_SUBCTRL_BASE + 0x69A0)
+#define PCIE_SUBCTRL_SC_PCIE1_PCIEPHY_CTRL_ERROR_REG       (PCIE_SUBCTRL_BASE + 0x69C0)
+#define PCIE_SUBCTRL_SC_PCIE2_RXEQINPRO_STAT_REG           (PCIE_SUBCTRL_BASE + 0x6A00)
+#define PCIE_SUBCTRL_SC_PCIE2_LINKINT_RCVRY_STAT_REG       (PCIE_SUBCTRL_BASE + 0x6A04)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE0_REG               (PCIE_SUBCTRL_BASE + 0x6A08)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE1_REG               (PCIE_SUBCTRL_BASE + 0x6A0C)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE2_REG               (PCIE_SUBCTRL_BASE + 0x6A10)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE3_REG               (PCIE_SUBCTRL_BASE + 0x6A14)
+#define PCIE_SUBCTRL_SC_PCIE2_SYS_STATE4_REG               (PCIE_SUBCTRL_BASE + 0x6A18)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS0_REG     (PCIE_SUBCTRL_BASE + 0x6A80)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_WR_STS1_REG     (PCIE_SUBCTRL_BASE + 0x6A84)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS0_REG     (PCIE_SUBCTRL_BASE + 0x6A90)
+#define PCIE_SUBCTRL_SC_PCIE2_AXI_MSTR_OOO_RD_STS1_REG     (PCIE_SUBCTRL_BASE + 0x6A94)
+#define PCIE_SUBCTRL_SC_PCIE2_DSIZE_BRG_ECC_ERR_REG        (PCIE_SUBCTRL_BASE + 0x6AA0)
+#define PCIE_SUBCTRL_SC_PCIE2_PCIEPHY_CTRL_ERROR_REG       (PCIE_SUBCTRL_BASE + 0x6AC0)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE0_REG               (PCIE_SUBCTRL_BASE + 0x6B08)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE1_REG               (PCIE_SUBCTRL_BASE + 0x6B0C)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE2_REG               (PCIE_SUBCTRL_BASE + 0x6B10)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE3_REG               (PCIE_SUBCTRL_BASE + 0x6B14)
+#define PCIE_SUBCTRL_SC_PCIE3_SYS_STATE4_REG               (PCIE_SUBCTRL_BASE + 0x6B18)
+#define PCIE_SUBCTRL_SC_PCIE3_PCIEPHY_CTRL_ERROR_REG       (PCIE_SUBCTRL_BASE + 0x6BC0)
+#define PCIE_SUBCTRL_SC_SKEW_ST_0_REG                      (PCIE_SUBCTRL_BASE + 0x7400)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_0_REG                    (PCIE_SUBCTRL_BASE + 0x7500)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_1_REG                    (PCIE_SUBCTRL_BASE + 0x7504)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_2_REG                    (PCIE_SUBCTRL_BASE + 0x7508)
+#define PCIE_SUBCTRL_SC_SKEW_ST_A_3_REG                    (PCIE_SUBCTRL_BASE + 0x750C)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_0_REG                    (PCIE_SUBCTRL_BASE + 0x7600)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_1_REG                    (PCIE_SUBCTRL_BASE + 0x7604)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_2_REG                    (PCIE_SUBCTRL_BASE + 0x7608)
+#define PCIE_SUBCTRL_SC_SKEW_ST_B_3_REG                    (PCIE_SUBCTRL_BASE + 0x760C)
+#define PCIE_SUBCTRL_SC_ECO_RSV0_REG                       (PCIE_SUBCTRL_BASE + 0x8000)
+#define PCIE_SUBCTRL_SC_ECO_RSV1_REG                       (PCIE_SUBCTRL_BASE + 0x8004)
+#define PCIE_SUBCTRL_SC_ECO_RSV2_REG                       (PCIE_SUBCTRL_BASE + 0x8008)
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie0_enb         : 1   ;
+        UINT32    clk_pcie0_pipe_enb    : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_clk_en;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie0_dsb         : 1   ;
+        UINT32    clk_pcie0_pipe_dsb    : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_clk_dis;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie1_enb         : 1   ;
+        UINT32    clk_pcie1_pipe_enb    : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_clk_en;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie1_dsb         : 1   ;
+        UINT32    clk_pcie1_pipe_dsb    : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_clk_dis;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie2_enb         : 1   ;
+        UINT32    clk_pcie2_pipe_enb    : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_clk_en;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie2_dsb         : 1   ;
+        UINT32    clk_pcie2_pipe_dsb    : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_clk_dis;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_sas_enb           : 1   ;
+        UINT32    clk_sas_mem_enb       : 1   ;
+        UINT32    clk_sas_ahb_enb       : 1   ;
+        UINT32    clk_sas_oob_enb       : 1   ;
+        UINT32    clk_sas_ch0_rx_enb    : 1   ;
+        UINT32    clk_sas_ch1_rx_enb    : 1   ;
+        UINT32    clk_sas_ch2_rx_enb    : 1   ;
+        UINT32    clk_sas_ch3_rx_enb    : 1   ;
+        UINT32    clk_sas_ch4_rx_enb    : 1   ;
+        UINT32    clk_sas_ch5_rx_enb    : 1   ;
+        UINT32    clk_sas_ch6_rx_enb    : 1   ;
+        UINT32    clk_sas_ch7_rx_enb    : 1   ;
+        UINT32    clk_sas_ch0_tx_enb    : 1   ;
+        UINT32    clk_sas_ch1_tx_enb    : 1   ;
+        UINT32    clk_sas_ch2_tx_enb    : 1   ;
+        UINT32    clk_sas_ch3_tx_enb    : 1   ;
+        UINT32    clk_sas_ch4_tx_enb    : 1   ;
+        UINT32    clk_sas_ch5_tx_enb    : 1   ;
+        UINT32    clk_sas_ch6_tx_enb    : 1   ;
+        UINT32    clk_sas_ch7_tx_enb    : 1   ;
+        UINT32    reserved_0            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sas_clk_en;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_sas_dsb           : 1   ;
+        UINT32    clk_sas_mem_dsb       : 1   ;
+        UINT32    clk_sas_ahb_dsb       : 1   ;
+        UINT32    clk_sas_oob_dsb       : 1   ;
+        UINT32    clk_sas_ch0_rx_dsb    : 1   ;
+        UINT32    clk_sas_ch1_rx_dsb    : 1   ;
+        UINT32    clk_sas_ch2_rx_dsb    : 1   ;
+        UINT32    clk_sas_ch3_rx_dsb    : 1   ;
+        UINT32    clk_sas_ch4_rx_dsb    : 1   ;
+        UINT32    clk_sas_ch5_rx_dsb    : 1   ;
+        UINT32    clk_sas_ch6_rx_dsb    : 1   ;
+        UINT32    clk_sas_ch7_rx_dsb    : 1   ;
+        UINT32    clk_sas_ch0_tx_dsb    : 1   ;
+        UINT32    clk_sas_ch1_tx_dsb    : 1   ;
+        UINT32    clk_sas_ch2_tx_dsb    : 1   ;
+        UINT32    clk_sas_ch3_tx_dsb    : 1   ;
+        UINT32    clk_sas_ch4_tx_dsb    : 1   ;
+        UINT32    clk_sas_ch5_tx_dsb    : 1   ;
+        UINT32    clk_sas_ch6_tx_dsb    : 1   ;
+        UINT32    clk_sas_ch7_tx_dsb    : 1   ;
+        UINT32    reserved_0            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sas_clk_dis;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie3_enb         : 1   ;
+        UINT32    clk_pcie3_pipe_enb    : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_clk_en;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie3_dsb         : 1   ;
+        UINT32    clk_pcie3_pipe_dsb    : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_clk_dis;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_its_enb           : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_its_clk_en;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_its_dsb           : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_its_clk_dis;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_sllc_enb          : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_clk_en;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_sllc_dsb          : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_clk_dis;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_srst_req        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_srst_dreq       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_srst_req        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_srst_dreq       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_srst_req        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_srst_dreq       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sas_srst_req          : 1   ;
+        UINT32    sas_oob_srst_req      : 1   ;
+        UINT32    sas_ahb_srst_req      : 1   ;
+        UINT32    sas_ch0_rx_srst_req   : 1   ;
+        UINT32    sas_ch1_rx_srst_req   : 1   ;
+        UINT32    sas_ch2_rx_srst_req   : 1   ;
+        UINT32    sas_ch3_rx_srst_req   : 1   ;
+        UINT32    sas_ch4_rx_srst_req   : 1   ;
+        UINT32    sas_ch5_rx_srst_req   : 1   ;
+        UINT32    sas_ch6_rx_srst_req   : 1   ;
+        UINT32    sas_ch7_rx_srst_req   : 1   ;
+        UINT32    sas_ch0_tx_srst_req   : 1   ;
+        UINT32    sas_ch1_tx_srst_req   : 1   ;
+        UINT32    sas_ch2_tx_srst_req   : 1   ;
+        UINT32    sas_ch3_tx_srst_req   : 1   ;
+        UINT32    sas_ch4_tx_srst_req   : 1   ;
+        UINT32    sas_ch5_tx_srst_req   : 1   ;
+        UINT32    sas_ch6_tx_srst_req   : 1   ;
+        UINT32    sas_ch7_tx_srst_req   : 1   ;
+        UINT32    reserved_0            : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sas_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sas_srst_dreq         : 1   ;
+        UINT32    sas_oob_srst_dreq     : 1   ;
+        UINT32    sas_ahb_srst_dreq     : 1   ;
+        UINT32    sas_ch0_rx_srst_dreq  : 1   ;
+        UINT32    sas_ch1_rx_srst_dreq  : 1   ;
+        UINT32    sas_ch2_rx_srst_dreq  : 1   ;
+        UINT32    sas_ch3_rx_srst_dreq  : 1   ;
+        UINT32    sas_ch4_rx_srst_dreq  : 1   ;
+        UINT32    sas_ch5_rx_srst_dreq  : 1   ;
+        UINT32    sas_ch6_rx_srst_dreq  : 1   ;
+        UINT32    sas_ch7_rx_srst_dreq  : 1   ;
+        UINT32    sas_ch0_tx_srst_dreq  : 1   ;
+        UINT32    sas_ch1_tx_srst_dreq  : 1   ;
+        UINT32    sas_ch2_tx_srst_dreq  : 1   ;
+        UINT32    sas_ch3_tx_srst_dreq  : 1   ;
+        UINT32    sas_ch4_tx_srst_dreq  : 1   ;
+        UINT32    sas_ch5_tx_srst_dreq  : 1   ;
+        UINT32    sas_ch6_tx_srst_dreq  : 1   ;
+        UINT32    sas_ch7_tx_srst_dreq  : 1   ;
+        UINT32    reserved_0            : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sas_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp0_srst_req        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp0_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp0_srst_dreq       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp0_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp1_srst_req        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp1_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp1_srst_dreq       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp1_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp2_srst_req        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp2_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp2_srst_dreq       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp2_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sllc_tsvrx0_srst_req  : 1   ;
+        UINT32    sllc_tsvrx1_srst_req  : 1   ;
+        UINT32    sllc_tsvrx2_srst_req  : 1   ;
+        UINT32    sllc_tsvrx3_srst_req  : 1   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_tsvrx_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sllc_tsvrx0_srst_dreq : 1   ;
+        UINT32    sllc_tsvrx1_srst_dreq : 1   ;
+        UINT32    sllc_tsvrx2_srst_dreq : 1   ;
+        UINT32    sllc_tsvrx3_srst_dreq : 1   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_tsvrx_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_hilink_pcs_lane0_srst_req : 1   ;
+        UINT32    pcie0_hilink_pcs_lane1_srst_req : 1   ;
+        UINT32    pcie0_hilink_pcs_lane2_srst_req : 1   ;
+        UINT32    pcie0_hilink_pcs_lane3_srst_req : 1   ;
+        UINT32    pcie0_hilink_pcs_lane4_srst_req : 1   ;
+        UINT32    pcie0_hilink_pcs_lane5_srst_req : 1   ;
+        UINT32    pcie0_hilink_pcs_lane6_srst_req : 1   ;
+        UINT32    pcie0_hilink_pcs_lane7_srst_req : 1   ;
+        UINT32    pcie1_hilink_pcs_lane0_srst_req : 1   ;
+        UINT32    pcie1_hilink_pcs_lane1_srst_req : 1   ;
+        UINT32    pcie1_hilink_pcs_lane2_srst_req : 1   ;
+        UINT32    pcie1_hilink_pcs_lane3_srst_req : 1   ;
+        UINT32    pcie1_hilink_pcs_lane4_srst_req : 1   ;
+        UINT32    pcie1_hilink_pcs_lane5_srst_req : 1   ;
+        UINT32    pcie1_hilink_pcs_lane6_srst_req : 1   ;
+        UINT32    pcie1_hilink_pcs_lane7_srst_req : 1   ;
+        UINT32    pcie2_hilink_pcs_lane0_srst_req : 1   ;
+        UINT32    pcie2_hilink_pcs_lane1_srst_req : 1   ;
+        UINT32    pcie2_hilink_pcs_lane2_srst_req : 1   ;
+        UINT32    pcie2_hilink_pcs_lane3_srst_req : 1   ;
+        UINT32    pcie2_hilink_pcs_lane4_srst_req : 1   ;
+        UINT32    pcie2_hilink_pcs_lane5_srst_req : 1   ;
+        UINT32    pcie2_hilink_pcs_lane6_srst_req : 1   ;
+        UINT32    pcie2_hilink_pcs_lane7_srst_req : 1   ;
+        UINT32    pcie3_hilink_pcs_lane0_srst_req : 1   ;
+        UINT32    pcie3_hilink_pcs_lane1_srst_req : 1   ;
+        UINT32    pcie3_hilink_pcs_lane2_srst_req : 1   ;
+        UINT32    pcie3_hilink_pcs_lane3_srst_req : 1   ;
+        UINT32    pcie3_hilink_pcs_lane4_srst_req : 1   ;
+        UINT32    pcie3_hilink_pcs_lane5_srst_req : 1   ;
+        UINT32    pcie3_hilink_pcs_lane6_srst_req : 1   ;
+        UINT32    pcie3_hilink_pcs_lane7_srst_req : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_hilink_pcs_lane0_srst_dreq : 1   ;
+        UINT32    pcie0_hilink_pcs_lane1_srst_dreq : 1   ;
+        UINT32    pcie0_hilink_pcs_lane2_srst_dreq : 1   ;
+        UINT32    pcie0_hilink_pcs_lane3_srst_dreq : 1   ;
+        UINT32    pcie0_hilink_pcs_lane4_srst_dreq : 1   ;
+        UINT32    pcie0_hilink_pcs_lane5_srst_dreq : 1   ;
+        UINT32    pcie0_hilink_pcs_lane6_srst_dreq : 1   ;
+        UINT32    pcie0_hilink_pcs_lane7_srst_dreq : 1   ;
+        UINT32    pcie1_hilink_pcs_lane0_srst_dreq : 1   ;
+        UINT32    pcie1_hilink_pcs_lane1_srst_dreq : 1   ;
+        UINT32    pcie1_hilink_pcs_lane2_srst_dreq : 1   ;
+        UINT32    pcie1_hilink_pcs_lane3_srst_dreq : 1   ;
+        UINT32    pcie1_hilink_pcs_lane4_srst_dreq : 1   ;
+        UINT32    pcie1_hilink_pcs_lane5_srst_dreq : 1   ;
+        UINT32    pcie1_hilink_pcs_lane6_srst_dreq : 1   ;
+        UINT32    pcie1_hilink_pcs_lane7_srst_dreq : 1   ;
+        UINT32    pcie2_hilink_pcs_lane0_srst_dreq : 1   ;
+        UINT32    pcie2_hilink_pcs_lane1_srst_dreq : 1   ;
+        UINT32    pcie2_hilink_pcs_lane2_srst_dreq : 1   ;
+        UINT32    pcie2_hilink_pcs_lane3_srst_dreq : 1   ;
+        UINT32    pcie2_hilink_pcs_lane4_srst_dreq : 1   ;
+        UINT32    pcie2_hilink_pcs_lane5_srst_dreq : 1   ;
+        UINT32    pcie2_hilink_pcs_lane6_srst_dreq : 1   ;
+        UINT32    pcie2_hilink_pcs_lane7_srst_dreq : 1   ;
+        UINT32    pcie3_hilink_pcs_lane0_srst_dreq : 1   ;
+        UINT32    pcie3_hilink_pcs_lane1_srst_dreq : 1   ;
+        UINT32    pcie3_hilink_pcs_lane2_srst_dreq : 1   ;
+        UINT32    pcie3_hilink_pcs_lane3_srst_dreq : 1   ;
+        UINT32    pcie3_hilink_pcs_lane4_srst_dreq : 1   ;
+        UINT32    pcie3_hilink_pcs_lane5_srst_dreq : 1   ;
+        UINT32    pcie3_hilink_pcs_lane6_srst_dreq : 1   ;
+        UINT32    pcie3_hilink_pcs_lane7_srst_dreq : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie3_srst_req        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie3_srst_dreq       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp3_srst_req        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp3_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp3_srst_dreq       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp3_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    its_srst_req          : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_its_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    its_srst_dreq         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_its_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sllc_srst_req         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sllc_srst_dreq        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_pcs_local_srst_req : 1   ;
+        UINT32    pcie1_pcs_local_srst_req : 1   ;
+        UINT32    pcie2_pcs_local_srst_req : 1   ;
+        UINT32    pcie3_pcs_local_srst_req : 1   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcs_local_reset_req;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_pcs_local_srst_dreq : 1   ;
+        UINT32    pcie1_pcs_local_srst_dreq : 1   ;
+        UINT32    pcie2_pcs_local_srst_dreq : 1   ;
+        UINT32    pcie3_pcs_local_srst_dreq : 1   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcs_local_reset_dreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    dispatch_daw_en       : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_disp_daw_en;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    daw_array0_did        : 3   ;
+        UINT32    daw_array0_size       : 5   ;
+        UINT32    daw_array0_sync       : 1   ;
+        UINT32    reserved_0            : 4   ;
+        UINT32    daw_array0_addr       : 19  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_daw_array0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    daw_array1_did        : 3   ;
+        UINT32    daw_array1_size       : 5   ;
+        UINT32    daw_array1_sync       : 1   ;
+        UINT32    reserved_0            : 4   ;
+        UINT32    daw_array1_addr       : 19  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_daw_array1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    daw_array2_did        : 3   ;
+        UINT32    daw_array2_size       : 5   ;
+        UINT32    daw_array2_sync       : 1   ;
+        UINT32    reserved_0            : 4   ;
+        UINT32    daw_array2_addr       : 19  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_daw_array2;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    daw_array3_did        : 3   ;
+        UINT32    daw_array3_size       : 5   ;
+        UINT32    daw_array3_sync       : 1   ;
+        UINT32    reserved_0            : 4   ;
+        UINT32    daw_array3_addr       : 19  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_daw_array3;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    daw_array4_did        : 3   ;
+        UINT32    daw_array4_size       : 5   ;
+        UINT32    daw_array4_sync       : 1   ;
+        UINT32    reserved_0            : 4   ;
+        UINT32    daw_array4_addr       : 19  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_daw_array4;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    daw_array5_did        : 3   ;
+        UINT32    daw_array5_size       : 5   ;
+        UINT32    daw_array5_sync       : 1   ;
+        UINT32    reserved_0            : 4   ;
+        UINT32    daw_array5_addr       : 19  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_daw_array5;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    daw_array6_did        : 3   ;
+        UINT32    daw_array6_size       : 5   ;
+        UINT32    daw_array6_sync       : 1   ;
+        UINT32    reserved_0            : 4   ;
+        UINT32    daw_array6_addr       : 19  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_daw_array6;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    daw_array7_did        : 3   ;
+        UINT32    daw_array7_size       : 5   ;
+        UINT32    daw_array7_sync       : 1   ;
+        UINT32    reserved_0            : 4   ;
+        UINT32    daw_array7_addr       : 19  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_daw_array7;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    retry_num_limit       : 16  ;
+        UINT32    retry_en              : 1   ;
+        UINT32    reserved_0            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_retry_control;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    intmask               : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_intmask;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    rawint                : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_rawint;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    intsts                : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_intstat;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    intclr                : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_intclr;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    err_opcode            : 5   ;
+        UINT32    err_addr              : 17  ;
+        UINT32    reserved_0            : 10  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_dispatch_errstat;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sys_remap_vld         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_remap_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mux_sel_fte           : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_fte_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_mux_sel       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_mux_sel       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink2_mux_sel       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink2_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_mux_sel       : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_ahb_mux_sel   : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink2_ahb_mux_sel   : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink2_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_ahb_mux_sel   : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_ahb_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_lrstb_mux_sel : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_lrstb_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_lrstb_mux_sel : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_lrstb_mux_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_ss_refclk0_x2s : 2   ;
+        UINT32    hilink0_ss_refclk0_x2n : 2   ;
+        UINT32    hilink0_ss_refclk0_x2e : 2   ;
+        UINT32    hilink0_ss_refclk0_x2w : 2   ;
+        UINT32    hilink0_ss_refclk1_x2s : 2   ;
+        UINT32    hilink0_ss_refclk1_x2n : 2   ;
+        UINT32    hilink0_ss_refclk1_x2e : 2   ;
+        UINT32    hilink0_ss_refclk1_x2w : 2   ;
+        UINT32    reserved_0            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_ss_refclk;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_cs_refclk0_dirsel0 : 2   ;
+        UINT32    hilink0_cs_refclk0_dirsel1 : 2   ;
+        UINT32    hilink0_cs_refclk0_dirsel2 : 2   ;
+        UINT32    hilink0_cs_refclk0_dirsel3 : 2   ;
+        UINT32    hilink0_cs_refclk0_dirsel4 : 2   ;
+        UINT32    hilink0_cs_refclk1_dirsel0 : 2   ;
+        UINT32    hilink0_cs_refclk1_dirsel1 : 2   ;
+        UINT32    hilink0_cs_refclk1_dirsel2 : 2   ;
+        UINT32    hilink0_cs_refclk1_dirsel3 : 2   ;
+        UINT32    hilink0_cs_refclk1_dirsel4 : 2   ;
+        UINT32    reserved_0            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_lifeclk2dig_sel : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_core_clk_selext : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_core_clk_selext;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_core_clk_sel  : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_core_clk_sel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_ctrl_bus_mode : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_macropwrdb    : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_macropwrdb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_grstb         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_grstb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_bit_slip      : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_bit_slip;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_lrstb         : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_lrstb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_ss_refclk0_x2s : 2   ;
+        UINT32    hilink1_ss_refclk0_x2n : 2   ;
+        UINT32    hilink1_ss_refclk0_x2e : 2   ;
+        UINT32    hilink1_ss_refclk0_x2w : 2   ;
+        UINT32    hilink1_ss_refclk1_x2s : 2   ;
+        UINT32    hilink1_ss_refclk1_x2n : 2   ;
+        UINT32    hilink1_ss_refclk1_x2e : 2   ;
+        UINT32    hilink1_ss_refclk1_x2w : 2   ;
+        UINT32    reserved_0            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_ss_refclk;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_cs_refclk0_dirsel0 : 2   ;
+        UINT32    hilink1_cs_refclk0_dirsel1 : 2   ;
+        UINT32    hilink1_cs_refclk0_dirsel2 : 2   ;
+        UINT32    hilink1_cs_refclk0_dirsel3 : 2   ;
+        UINT32    hilink1_cs_refclk0_dirsel4 : 2   ;
+        UINT32    hilink1_cs_refclk1_dirsel0 : 2   ;
+        UINT32    hilink1_cs_refclk1_dirsel1 : 2   ;
+        UINT32    hilink1_cs_refclk1_dirsel2 : 2   ;
+        UINT32    hilink1_cs_refclk1_dirsel3 : 2   ;
+        UINT32    hilink1_cs_refclk1_dirsel4 : 2   ;
+        UINT32    reserved_0            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_lifeclk2dig_sel : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_core_clk_selext : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_core_clk_selext;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_core_clk_sel  : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_core_clk_sel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_ctrl_bus_mode : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_macropwrdb    : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_macropwrdb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_grstb         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_grstb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_bit_slip      : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_bit_slip;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_lrstb         : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_lrstb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_ss_refclk0_x2s : 2   ;
+        UINT32    hilink5_ss_refclk0_x2n : 2   ;
+        UINT32    hilink5_ss_refclk0_x2e : 2   ;
+        UINT32    hilink5_ss_refclk0_x2w : 2   ;
+        UINT32    hilink5_ss_refclk1_x2s : 2   ;
+        UINT32    hilink5_ss_refclk1_x2n : 2   ;
+        UINT32    hilink5_ss_refclk1_x2e : 2   ;
+        UINT32    hilink5_ss_refclk1_x2w : 2   ;
+        UINT32    reserved_0            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_ss_refclk;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_cs_refclk0_dirsel0 : 2   ;
+        UINT32    hilink5_cs_refclk0_dirsel1 : 2   ;
+        UINT32    hilink5_cs_refclk0_dirsel2 : 2   ;
+        UINT32    hilink5_cs_refclk0_dirsel3 : 2   ;
+        UINT32    hilink5_cs_refclk0_dirsel4 : 2   ;
+        UINT32    hilink5_cs_refclk1_dirsel0 : 2   ;
+        UINT32    hilink5_cs_refclk1_dirsel1 : 2   ;
+        UINT32    hilink5_cs_refclk1_dirsel2 : 2   ;
+        UINT32    hilink5_cs_refclk1_dirsel3 : 2   ;
+        UINT32    hilink5_cs_refclk1_dirsel4 : 2   ;
+        UINT32    reserved_0            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_lifeclk2dig_sel : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_core_clk_selext : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_core_clk_selext;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_core_clk_sel  : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_core_clk_sel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_ctrl_bus_mode : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_macropwrdb    : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_macropwrdb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_grstb         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_grstb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_bit_slip      : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_bit_slip;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_lrstb         : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_lrstb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_ss_refclk0_x2s : 2   ;
+        UINT32    hilink6_ss_refclk0_x2n : 2   ;
+        UINT32    hilink6_ss_refclk0_x2e : 2   ;
+        UINT32    hilink6_ss_refclk0_x2w : 2   ;
+        UINT32    hilink6_ss_refclk1_x2s : 2   ;
+        UINT32    hilink6_ss_refclk1_x2n : 2   ;
+        UINT32    hilink6_ss_refclk1_x2e : 2   ;
+        UINT32    hilink6_ss_refclk1_x2w : 2   ;
+        UINT32    reserved_0            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_ss_refclk;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_cs_refclk0_dirsel0 : 2   ;
+        UINT32    hilink6_cs_refclk0_dirsel1 : 2   ;
+        UINT32    hilink6_cs_refclk0_dirsel2 : 2   ;
+        UINT32    hilink6_cs_refclk0_dirsel3 : 2   ;
+        UINT32    hilink6_cs_refclk0_dirsel4 : 2   ;
+        UINT32    hilink6_cs_refclk1_dirsel0 : 2   ;
+        UINT32    hilink6_cs_refclk1_dirsel1 : 2   ;
+        UINT32    hilink6_cs_refclk1_dirsel2 : 2   ;
+        UINT32    hilink6_cs_refclk1_dirsel3 : 2   ;
+        UINT32    hilink6_cs_refclk1_dirsel4 : 2   ;
+        UINT32    reserved_0            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_cs_refclk_dirsel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_lifeclk2dig_sel : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_lifeclk2dig_sel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_core_clk_selext : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_core_clk_selext;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_core_clk_sel  : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_core_clk_sel;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_ctrl_bus_mode : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_ctrl_bus_mode;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_macropwrdb    : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_macropwrdb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_grstb         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_grstb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_bit_slip      : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_bit_slip;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_lrstb         : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_lrstb;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_phy_clk_req_n   : 1   ;
+        UINT32    pcie0_apb_cfg_sel     : 2   ;
+        UINT32    reserved_0            : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_clkreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_cfg_max_wr_trans : 6   ;
+        UINT32    reserved_0            : 2   ;
+        UINT32    pcie0_wr_rate_limit   : 4   ;
+        UINT32    pcie0_ctrl_lat_stat_wr_en : 1   ;
+        UINT32    reserved_1            : 3   ;
+        UINT32    pcie0_en_device_wr_ooo : 1   ;
+        UINT32    reserved_2            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_cfg_max_rd_trans : 6   ;
+        UINT32    reserved_0            : 2   ;
+        UINT32    pcie0_rd_rate_limit   : 4   ;
+        UINT32    pcie0_ctrl_lat_stat_rd_en : 1   ;
+        UINT32    reserved_1            : 3   ;
+        UINT32    pcie0_en_device_rd_ooo : 1   ;
+        UINT32    reserved_2            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1hilink_phy_clk_req_n : 1   ;
+        UINT32    pcie1vsemi_phy_clk_req_n : 1   ;
+        UINT32    pcie1_apb_cfg_sel     : 2   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_clkreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_cfg_max_wr_trans : 6   ;
+        UINT32    reserved_0            : 2   ;
+        UINT32    pcie1_wr_rate_limit   : 4   ;
+        UINT32    pcie1_ctrl_lat_stat_wr_en : 1   ;
+        UINT32    reserved_1            : 3   ;
+        UINT32    pcie1_en_device_wr_ooo : 1   ;
+        UINT32    reserved_2            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_cfg_max_rd_trans : 6   ;
+        UINT32    reserved_0            : 2   ;
+        UINT32    pcie1_rd_rate_limit   : 4   ;
+        UINT32    pcie1_ctrl_lat_stat_rd_en : 1   ;
+        UINT32    reserved_1            : 3   ;
+        UINT32    pcie1_en_device_rd_ooo : 1   ;
+        UINT32    reserved_2            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2hilink_phy_clk_req_n : 1   ;
+        UINT32    pcie2vsemi_phy_clk_req_n : 1   ;
+        UINT32    pcie2_apb_cfg_sel     : 2   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_clkreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_cfg_max_wr_trans : 6   ;
+        UINT32    reserved_0            : 2   ;
+        UINT32    pcie2_wr_rate_limit   : 4   ;
+        UINT32    pcie2_ctrl_lat_stat_wr_en : 1   ;
+        UINT32    reserved_1            : 3   ;
+        UINT32    pcie2_en_device_wr_ooo : 1   ;
+        UINT32    reserved_2            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_wr_cfg;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_cfg_max_rd_trans : 6   ;
+        UINT32    reserved_0            : 2   ;
+        UINT32    pcie2_rd_rate_limit   : 4   ;
+        UINT32    pcie2_ctrl_lat_stat_rd_en : 1   ;
+        UINT32    reserved_1            : 3   ;
+        UINT32    pcie2_en_device_rd_ooo : 1   ;
+        UINT32    reserved_2            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_rd_cfg;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie3_phy_clk_req_n   : 1   ;
+        UINT32    pcie3_apb_cfg_sel     : 2   ;
+        UINT32    reserved_0            : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_clkreq;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    ctrl_rfs_smmu         : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_smmu_mem_ctrl0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    tsel_hc_smmu          : 3   ;
+        UINT32    reserved_0            : 29  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_smmu_mem_ctrl1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    test_hc_smmu          : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_smmu_mem_ctrl2;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    ctrl_rft_sllc0        : 10  ;
+        UINT32    reserved_0            : 22  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc0_mem_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    ctrl_rfs_sas          : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sas_mem_ctrl;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    ctrl_rft_pcie         : 10  ;
+        UINT32    reserved_0            : 22  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie_mem_ctrl0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    ctrl_rashsd_pcie      : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie_mem_ctrl1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    ctrl_rfs_pcie         : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie_mem_ctrl2;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_en               : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_common_0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_addr_offset      : 5   ;
+        UINT32    reserved_0            : 27  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_common_1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_config_in        : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_common_2;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_bypass_a         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_a_0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_config_in_a      : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_a_1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_out_delay_sel_a  : 2   ;
+        UINT32    skew_in_delay_sel_a   : 2   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_a_2;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_sel_a_1          : 1   ;
+        UINT32    skew_sel_a_0          : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_a_3;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_update_en_a      : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_a_4;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_varible_set_a    : 16  ;
+        UINT32    reserved_0            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_a_5;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_dcell_set_a_h    : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_a_7;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_sel_osc_a        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_a_8;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_bypass_b         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_b_0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_config_in_b      : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_b_1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_out_delay_sel_b  : 2   ;
+        UINT32    skew_in_delay_sel_b   : 2   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_b_2;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_sel_b_1          : 1   ;
+        UINT32    skew_sel_b_0          : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_b_3;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_update_en_b      : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_b_4;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_varible_set_b    : 16  ;
+        UINT32    reserved_0            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_b_5;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_dcell_set_b_h    : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_b_7;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_sel_osc_b        : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_b_8;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie0_st          : 1   ;
+        UINT32    clk_pcie0_pipe_st     : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_clk_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie1_st          : 1   ;
+        UINT32    clk_pcie1_pipe_st     : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_clk_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie2_st          : 1   ;
+        UINT32    clk_pcie2_pipe_st     : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_clk_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_sas_st            : 1   ;
+        UINT32    clk_sas_mem_st        : 1   ;
+        UINT32    clk_sas_ahb_st        : 1   ;
+        UINT32    clk_sas_oob_st        : 1   ;
+        UINT32    clk_sas_ch0_rx_st     : 1   ;
+        UINT32    clk_sas_ch1_rx_st     : 1   ;
+        UINT32    clk_sas_ch2_rx_st     : 1   ;
+        UINT32    clk_sas_ch3_rx_st     : 1   ;
+        UINT32    clk_sas_ch4_rx_st     : 1   ;
+        UINT32    clk_sas_ch5_rx_st     : 1   ;
+        UINT32    clk_sas_ch6_rx_st     : 1   ;
+        UINT32    clk_sas_ch7_rx_st     : 1   ;
+        UINT32    clk_sas_ch0_tx_st     : 1   ;
+        UINT32    clk_sas_ch1_tx_st     : 1   ;
+        UINT32    clk_sas_ch2_tx_st     : 1   ;
+        UINT32    clk_sas_ch3_tx_st     : 1   ;
+        UINT32    clk_sas_ch4_tx_st     : 1   ;
+        UINT32    clk_sas_ch5_tx_st     : 1   ;
+        UINT32    clk_sas_ch6_tx_st     : 1   ;
+        UINT32    clk_sas_ch7_tx_st     : 1   ;
+        UINT32    reserved_0            : 12  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sas_clk_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_pcie3_st          : 1   ;
+        UINT32    clk_pcie3_pipe_st     : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_clk_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_its_st            : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_its_clk_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    clk_sllc_st           : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_clk_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_srst_st         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_srst_st         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_srst_st         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sas_srst_st           : 1   ;
+        UINT32    sas_oob_srst_st       : 1   ;
+        UINT32    sas_ahb_srst_st       : 1   ;
+        UINT32    sas_ch0_rx_srst_st    : 1   ;
+        UINT32    sas_ch1_rx_srst_st    : 1   ;
+        UINT32    sas_ch2_rx_srst_st    : 1   ;
+        UINT32    sas_ch3_rx_srst_st    : 1   ;
+        UINT32    sas_ch4_rx_srst_st    : 1   ;
+        UINT32    sas_ch5_rx_srst_st    : 1   ;
+        UINT32    sas_ch6_rx_srst_st    : 1   ;
+        UINT32    sas_ch7_rx_srst_st    : 1   ;
+        UINT32    sas_ch0_tx_srst_st    : 1   ;
+        UINT32    sas_ch1_tx_srst_st    : 1   ;
+        UINT32    sas_ch2_tx_srst_st    : 1   ;
+        UINT32    sas_ch3_tx_srst_st    : 1   ;
+        UINT32    sas_ch4_tx_srst_st    : 1   ;
+        UINT32    sas_ch5_tx_srst_st    : 1   ;
+        UINT32    sas_ch6_tx_srst_st    : 1   ;
+        UINT32    sas_ch7_tx_srst_st    : 1   ;
+        UINT32    reserved_0            : 13  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sas_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp0_srst_st         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp0_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp1_srst_st         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp1_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp2_srst_st         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp2_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sllc_tsvrx0_srst_st   : 1   ;
+        UINT32    sllc_tsvrx1_srst_st   : 1   ;
+        UINT32    sllc_tsvrx2_srst_st   : 1   ;
+        UINT32    sllc_tsvrx3_srst_st   : 1   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_tsvrx_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_hilink_pcs_lane0_srst_st : 1   ;
+        UINT32    pcie0_hilink_pcs_lane1_srst_st : 1   ;
+        UINT32    pcie0_hilink_pcs_lane2_srst_st : 1   ;
+        UINT32    pcie0_hilink_pcs_lane3_srst_st : 1   ;
+        UINT32    pcie0_hilink_pcs_lane4_srst_st : 1   ;
+        UINT32    pcie0_hilink_pcs_lane5_srst_st : 1   ;
+        UINT32    pcie0_hilink_pcs_lane6_srst_st : 1   ;
+        UINT32    pcie0_hilink_pcs_lane7_srst_st : 1   ;
+        UINT32    pcie1_hilink_pcs_lane0_srst_st : 1   ;
+        UINT32    pcie1_hilink_pcs_lane1_srst_st : 1   ;
+        UINT32    pcie1_hilink_pcs_lane2_srst_st : 1   ;
+        UINT32    pcie1_hilink_pcs_lane3_srst_st : 1   ;
+        UINT32    pcie1_hilink_pcs_lane4_srst_st : 1   ;
+        UINT32    pcie1_hilink_pcs_lane5_srst_st : 1   ;
+        UINT32    pcie1_hilink_pcs_lane6_srst_st : 1   ;
+        UINT32    pcie1_hilink_pcs_lane7_srst_st : 1   ;
+        UINT32    pcie2_hilink_pcs_lane0_srst_st : 1   ;
+        UINT32    pcie2_hilink_pcs_lane1_srst_st : 1   ;
+        UINT32    pcie2_hilink_pcs_lane2_srst_st : 1   ;
+        UINT32    pcie2_hilink_pcs_lane3_srst_st : 1   ;
+        UINT32    pcie2_hilink_pcs_lane4_srst_st : 1   ;
+        UINT32    pcie2_hilink_pcs_lane5_srst_st : 1   ;
+        UINT32    pcie2_hilink_pcs_lane6_srst_st : 1   ;
+        UINT32    pcie2_hilink_pcs_lane7_srst_st : 1   ;
+        UINT32    pcie3_hilink_pcs_lane0_srst_st : 1   ;
+        UINT32    pcie3_hilink_pcs_lane1_srst_st : 1   ;
+        UINT32    pcie3_hilink_pcs_lane2_srst_st : 1   ;
+        UINT32    pcie3_hilink_pcs_lane3_srst_st : 1   ;
+        UINT32    pcie3_hilink_pcs_lane4_srst_st : 1   ;
+        UINT32    pcie3_hilink_pcs_lane5_srst_st : 1   ;
+        UINT32    pcie3_hilink_pcs_lane6_srst_st : 1   ;
+        UINT32    pcie3_hilink_pcs_lane7_srst_st : 1   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie_hilink_pcs_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie3_srst_st         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    mctp3_srst_st         : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_mctp3_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    its_srst_st           : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_its_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    sllc_srst_st          : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_sllc_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_pcs_local_srst_st : 1   ;
+        UINT32    pcie1_pcs_local_srst_st : 1   ;
+        UINT32    pcie2_pcs_local_srst_st : 1   ;
+        UINT32    pcie3_pcs_local_srst_st : 1   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcs_local_reset_st;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_plloutoflock  : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_plloutoflock;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_prbs_err      : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_prbs_err;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink0_los           : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink0_macro_los;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_plloutoflock  : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_plloutoflock;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_prbs_err      : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_prbs_err;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink1_los           : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink1_macro_los;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_plloutoflock  : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_plloutoflock;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_prbs_err      : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_prbs_err;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink5_los           : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink5_macro_los;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_plloutoflock  : 2   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_plloutoflock;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_prbs_err      : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_prbs_err;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    hilink6_los           : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_hilink6_macro_los;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_mac_phy_rxeqinprogress : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_rxeqinpro_stat;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_cfg_link_eq_req_int : 1   ;
+        UINT32    pcie0_xmlh_ltssm_state_rcvry_eq : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_gm_cmposer_lookup_err : 1   ;
+        UINT32    pcie0_radmx_cmposer_lookup_err : 1   ;
+        UINT32    pcie0_pm_xtlh_block_tlp : 1   ;
+        UINT32    pcie0_cfg_mem_space_en : 1   ;
+        UINT32    pcie0_cfg_rcb         : 1   ;
+        UINT32    pcie0_rdlh_link_up    : 1   ;
+        UINT32    pcie0_pm_curnt_state  : 3   ;
+        UINT32    pcie0_cfg_aer_rc_err_int : 1   ;
+        UINT32    pcie0_cfg_aer_int_msg_num : 5   ;
+        UINT32    pcie0_xmlh_link_up    : 1   ;
+        UINT32    pcie0_wake            : 1   ;
+        UINT32    pcie0_cfg_eml_control : 1   ;
+        UINT32    pcie0_hp_pme          : 1   ;
+        UINT32    pcie0_hp_int          : 1   ;
+        UINT32    pcie0_hp_msi          : 1   ;
+        UINT32    pcie0_pm_status       : 1   ;
+        UINT32    pcie0_ref_clk_req_n   : 1   ;
+        UINT32    pcie0_p2_exit_reg     : 1   ;
+        UINT32    pcie0_radm_msg_req_id_low : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+}U_SC_PCIE0_SYS_STATE0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_axi_parity_errs_reg : 4   ;
+        UINT32    pcie0_app_parity_errs_reg : 3   ;
+        UINT32    pcie0_pm_linkst_in_l1 : 1   ;
+        UINT32    pcie0_pm_linkst_in_l2 : 1   ;
+        UINT32    pcie0_pm_linkst_l2_exit : 1   ;
+        UINT32    pcie0_mac_phy_power_down : 2   ;
+        UINT32    pcie0_radm_correctabl_err_reg : 1   ;
+        UINT32    pcie0_radm_nonfatal_err_reg : 1   ;
+        UINT32    pcie0_radm_fatal_err_reg : 1   ;
+        UINT32    pcie0_radm_pm_to_pme_reg : 1   ;
+        UINT32    pcie0_radm_pm_to_ack_reg : 1   ;
+        UINT32    pcie0_radm_cpl_timeout_reg : 1   ;
+        UINT32    pcie0_radm_msg_unlock_reg : 1   ;
+        UINT32    pcie0_cfg_pme_msi_reg : 1   ;
+        UINT32    pcie0_bridge_flush_not_reg : 1   ;
+        UINT32    pcie0_link_req_rst_not_reg : 1   ;
+        UINT32    pcie0_cfg_aer_rc_err_msi : 1   ;
+        UINT32    pcie0_cfg_sys_err_rc  : 1   ;
+        UINT32    pcie0_radm_msg_req_id_high : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} U_SC_PCIE0_SYS_STATE1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_ltssm_state     : 6   ;
+        UINT32    pcie0_mac_phy_rate    : 2   ;
+        UINT32    pcie0_slv_err_int     : 1   ;
+        UINT32    pcie0_retry_sram_addr : 10  ;
+        UINT32    pcie0_mstr_rresp_int  : 1   ;
+        UINT32    pcie0_mstr_bresp_int  : 1   ;
+        UINT32    pcie0_radm_inta_reg   : 1   ;
+        UINT32    pcie0_radm_intb_reg   : 1   ;
+        UINT32    pcie0_radm_intc_reg   : 1   ;
+        UINT32    pcie0_radm_intd_reg   : 1   ;
+        UINT32    pcie0_cfg_pme_int_reg : 1   ;
+        UINT32    pcie0_radm_vendor_msg_reg : 1   ;
+        UINT32    pcie0_bridge_flush_not : 1   ;
+        UINT32    pcie0_link_req_rst_not : 1   ;
+        UINT32    reserved_0            : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} U_SC_PCIE0_SYS_STATE4;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_curr_wr_latency : 16  ;
+        UINT32    pcie0_curr_wr_port_sts : 1   ;
+        UINT32    reserved_0            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_curr_rd_latency : 16  ;
+        UINT32    pcie0_curr_rd_port_sts : 1   ;
+        UINT32    reserved_0            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_rob_ecc_err_detect : 1   ;
+        UINT32    pcie0_rob_ecc_err_multpl : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie0_pciephy_ctrl_error : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie0_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_mac_phy_rxeqinprogress : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_rxeqinpro_stat;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_cfg_link_eq_req_int : 1   ;
+        UINT32    pcie1_xmlh_ltssm_state_rcvry_eq : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_gm_cmposer_lookup_err : 1   ;
+        UINT32    pcie1_radmx_cmposer_lookup_err : 1   ;
+        UINT32    pcie1_pm_xtlh_block_tlp : 1   ;
+        UINT32    pcie1_cfg_mem_space_en : 1   ;
+        UINT32    pcie1_cfg_rcb         : 1   ;
+        UINT32    pcie1_rdlh_link_up    : 1   ;
+        UINT32    pcie1_pm_curnt_state  : 3   ;
+        UINT32    pcie1_cfg_aer_rc_err_int : 1   ;
+        UINT32    pcie1_cfg_aer_int_msg_num : 5   ;
+        UINT32    pcie1_xmlh_link_up    : 1   ;
+        UINT32    pcie1_wake            : 1   ;
+        UINT32    pcie1_cfg_eml_control : 1   ;
+        UINT32    pcie1_hp_pme          : 1   ;
+        UINT32    pcie1_hp_int          : 1   ;
+        UINT32    pcie1_hp_msi          : 1   ;
+        UINT32    pcie1_pm_status       : 1   ;
+        UINT32    pcie1_ref_clk_req_n   : 1   ;
+        UINT32    pcie1_p2_exit_reg     : 1   ;
+        UINT32    pcie1_radm_msg_req_id_low : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_sys_state0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_axi_parity_errs_reg : 4   ;
+        UINT32    pcie1_app_parity_errs_reg : 3   ;
+        UINT32    pcie1_pm_linkst_in_l1 : 1   ;
+        UINT32    pcie1_pm_linkst_in_l2 : 1   ;
+        UINT32    pcie1_pm_linkst_l2_exit : 1   ;
+        UINT32    pcie1_mac_phy_power_down : 2   ;
+        UINT32    pcie1_radm_correctabl_err_reg : 1   ;
+        UINT32    pcie1_radm_nonfatal_err_reg : 1   ;
+        UINT32    pcie1_radm_fatal_err_reg : 1   ;
+        UINT32    pcie1_radm_pm_to_pme_reg : 1   ;
+        UINT32    pcie1_radm_pm_to_ack_reg : 1   ;
+        UINT32    pcie1_radm_cpl_timeout_reg : 1   ;
+        UINT32    pcie1_radm_msg_unlock_reg : 1   ;
+        UINT32    pcie1_cfg_pme_msi_reg : 1   ;
+        UINT32    pcie1_bridge_flush_not_reg : 1   ;
+        UINT32    pcie1_link_req_rst_not_reg : 1   ;
+        UINT32    pcie1_cfg_aer_rc_err_msi : 1   ;
+        UINT32    pcie1_cfg_sys_err_rc  : 1   ;
+        UINT32    pcie1_radm_msg_req_id_high : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_sys_state1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_ltssm_state     : 6   ;
+        UINT32    pcie1_mac_phy_rate    : 2   ;
+        UINT32    pcie1_slv_err_int     : 1   ;
+        UINT32    pcie1_retry_sram_addr : 10  ;
+        UINT32    pcie1_mstr_rresp_int  : 1   ;
+        UINT32    pcie1_mstr_bresp_int  : 1   ;
+        UINT32    pcie1_radm_inta_reg   : 1   ;
+        UINT32    pcie1_radm_intb_reg   : 1   ;
+        UINT32    pcie1_radm_intc_reg   : 1   ;
+        UINT32    pcie1_radm_intd_reg   : 1   ;
+        UINT32    pcie1_cfg_pme_int_reg : 1   ;
+        UINT32    pcie1_radm_vendor_msg_reg : 1   ;
+        UINT32    pcie1_bridge_flush_not : 1   ;
+        UINT32    pcie1_link_req_rst_not : 1   ;
+        UINT32    reserved_0            : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_sys_state4;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_curr_wr_latency : 16  ;
+        UINT32    pcie1_curr_wr_port_sts : 1   ;
+        UINT32    reserved_0            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_curr_rd_latency : 16  ;
+        UINT32    pcie1_curr_rd_port_sts : 1   ;
+        UINT32    reserved_0            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_rob_ecc_err_detect : 1   ;
+        UINT32    pcie1_rob_ecc_err_multpl : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie1_pciephy_ctrl_error : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie1_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_mac_phy_rxeqinprogress : 8   ;
+        UINT32    reserved_0            : 24  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_rxeqinpro_stat;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_cfg_link_eq_req_int : 1   ;
+        UINT32    pcie2_xmlh_ltssm_state_rcvry_eq : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_linkint_rcvry_stat;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_gm_cmposer_lookup_err : 1   ;
+        UINT32    pcie2_radmx_cmposer_lookup_err : 1   ;
+        UINT32    pcie2_pm_xtlh_block_tlp : 1   ;
+        UINT32    pcie2_cfg_mem_space_en : 1   ;
+        UINT32    pcie2_cfg_rcb         : 1   ;
+        UINT32    pcie2_rdlh_link_up    : 1   ;
+        UINT32    pcie2_pm_curnt_state  : 3   ;
+        UINT32    pcie2_cfg_aer_rc_err_int : 1   ;
+        UINT32    pcie2_cfg_aer_int_msg_num : 5   ;
+        UINT32    pcie2_xmlh_link_up    : 1   ;
+        UINT32    pcie2_wake            : 1   ;
+        UINT32    pcie2_cfg_eml_control : 1   ;
+        UINT32    pcie2_hp_pme          : 1   ;
+        UINT32    pcie2_hp_int          : 1   ;
+        UINT32    pcie2_hp_msi          : 1   ;
+        UINT32    pcie2_pm_status       : 1   ;
+        UINT32    pcie2_ref_clk_req_n   : 1   ;
+        UINT32    pcie2_p2_exit_reg     : 1   ;
+        UINT32    pcie2_radm_msg_req_id_low : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_sys_state0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_axi_parity_errs_reg : 4   ;
+        UINT32    pcie2_app_parity_errs_reg : 3   ;
+        UINT32    pcie2_pm_linkst_in_l1 : 1   ;
+        UINT32    pcie2_pm_linkst_in_l2 : 1   ;
+        UINT32    pcie2_pm_linkst_l2_exit : 1   ;
+        UINT32    pcie2_mac_phy_power_down : 2   ;
+        UINT32    pcie2_radm_correctabl_err_reg : 1   ;
+        UINT32    pcie2_radm_nonfatal_err_reg : 1   ;
+        UINT32    pcie2_radm_fatal_err_reg : 1   ;
+        UINT32    pcie2_radm_pm_to_pme_reg : 1   ;
+        UINT32    pcie2_radm_pm_to_ack_reg : 1   ;
+        UINT32    pcie2_radm_cpl_timeout_reg : 1   ;
+        UINT32    pcie2_radm_msg_unlock_reg : 1   ;
+        UINT32    pcie2_cfg_pme_msi_reg : 1   ;
+        UINT32    pcie2_bridge_flush_not_reg : 1   ;
+        UINT32    pcie2_link_req_rst_not_reg : 1   ;
+        UINT32    pcie2_cfg_aer_rc_err_msi : 1   ;
+        UINT32    pcie2_cfg_sys_err_rc  : 1   ;
+        UINT32    pcie2_radm_msg_req_id_high : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_sys_state1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_ltssm_state     : 6   ;
+        UINT32    pcie2_mac_phy_rate    : 2   ;
+        UINT32    pcie2_slv_err_int     : 1   ;
+        UINT32    pcie2_retry_sram_addr : 10  ;
+        UINT32    pcie2_mstr_rresp_int  : 1   ;
+        UINT32    pcie2_mstr_bresp_int  : 1   ;
+        UINT32    pcie2_radm_inta_reg   : 1   ;
+        UINT32    pcie2_radm_intb_reg   : 1   ;
+        UINT32    pcie2_radm_intc_reg   : 1   ;
+        UINT32    pcie2_radm_intd_reg   : 1   ;
+        UINT32    pcie2_cfg_pme_int_reg : 1   ;
+        UINT32    pcie2_radm_vendor_msg_reg : 1   ;
+        UINT32    pcie2_bridge_flush_not : 1   ;
+        UINT32    pcie2_link_req_rst_not : 1   ;
+        UINT32    reserved_0            : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_sys_state4;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_curr_wr_latency : 16  ;
+        UINT32    pcie2_curr_wr_port_sts : 1   ;
+        UINT32    reserved_0            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_wr_sts1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_curr_rd_latency : 16  ;
+        UINT32    pcie2_curr_rd_port_sts : 1   ;
+        UINT32    reserved_0            : 15  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_axi_mstr_ooo_rd_sts1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_rob_ecc_err_detect : 1   ;
+        UINT32    pcie2_rob_ecc_err_multpl : 1   ;
+        UINT32    reserved_0            : 30  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_dsize_brg_ecc_err;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie2_pciephy_ctrl_error : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie2_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie3_gm_cmposer_lookup_err : 1   ;
+        UINT32    pcie3_radmx_cmposer_lookup_err : 1   ;
+        UINT32    pcie3_pm_xtlh_block_tlp : 1   ;
+        UINT32    pcie3_cfg_mem_space_en : 1   ;
+        UINT32    pcie3_cfg_rcb         : 1   ;
+        UINT32    pcie3_rdlh_link_up    : 1   ;
+        UINT32    pcie3_pm_curnt_state  : 3   ;
+        UINT32    pcie3_cfg_aer_rc_err_int : 1   ;
+        UINT32    pcie3_cfg_aer_int_msg_num : 5   ;
+        UINT32    pcie3_xmlh_link_up    : 1   ;
+        UINT32    pcie3_wake            : 1   ;
+        UINT32    pcie3_cfg_eml_control : 1   ;
+        UINT32    pcie3_hp_pme          : 1   ;
+        UINT32    pcie3_hp_int          : 1   ;
+        UINT32    pcie3_hp_msi          : 1   ;
+        UINT32    pcie3_pm_status       : 1   ;
+        UINT32    pcie3_ref_clk_req_n   : 1   ;
+        UINT32    pcie3_p2_exit_reg     : 1   ;
+        UINT32    pcie3_radm_msg_req_id_low : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_sys_state0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie3_axi_parity_errs_reg : 4   ;
+        UINT32    pcie3_app_parity_errs_reg : 3   ;
+        UINT32    pcie3_pm_linkst_in_l1 : 1   ;
+        UINT32    pcie3_pm_linkst_in_l2 : 1   ;
+        UINT32    pcie3_pm_linkst_l2_exit : 1   ;
+        UINT32    pcie3_mac_phy_power_down : 2   ;
+        UINT32    pcie3_radm_correctabl_err_reg : 1   ;
+        UINT32    pcie3_radm_nonfatal_err_reg : 1   ;
+        UINT32    pcie3_radm_fatal_err_reg : 1   ;
+        UINT32    pcie3_radm_pm_to_pme_reg : 1   ;
+        UINT32    pcie3_radm_pm_to_ack_reg : 1   ;
+        UINT32    pcie3_radm_cpl_timeout_reg : 1   ;
+        UINT32    pcie3_radm_msg_unlock_reg : 1   ;
+        UINT32    pcie3_cfg_pme_msi_reg : 1   ;
+        UINT32    pcie3_bridge_flush_not_reg : 1   ;
+        UINT32    pcie3_link_req_rst_not_reg : 1   ;
+        UINT32    pcie3_cfg_aer_rc_err_msi : 1   ;
+        UINT32    pcie3_cfg_sys_err_rc  : 1   ;
+        UINT32    pcie3_radm_msg_req_id_high : 8   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_sys_state1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie3_ltssm_state     : 6   ;
+        UINT32    pcie3_mac_phy_rate    : 2   ;
+        UINT32    pcie3_slv_err_int     : 1   ;
+        UINT32    pcie3_retry_sram_addr : 10  ;
+        UINT32    pcie3_mstr_rresp_int  : 1   ;
+        UINT32    pcie3_mstr_bresp_int  : 1   ;
+        UINT32    pcie3_radm_inta_reg   : 1   ;
+        UINT32    pcie3_radm_intb_reg   : 1   ;
+        UINT32    pcie3_radm_intc_reg   : 1   ;
+        UINT32    pcie3_radm_intd_reg   : 1   ;
+        UINT32    pcie3_cfg_pme_int_reg : 1   ;
+        UINT32    pcie3_radm_vendor_msg_reg : 1   ;
+        UINT32    pcie3_bridge_flush_not : 1   ;
+        UINT32    pcie3_link_req_rst_not : 1   ;
+        UINT32    reserved_0            : 3   ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_sys_state4;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    pcie3_pciephy_ctrl_error : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_pcie3_pciephy_ctrl_error;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_lock_a           : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_st_a_0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_varible_out_a    : 16  ;
+        UINT32    reserved_0            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_st_a_1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_dcell_out_a_h    : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_st_a_3;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_lock_b           : 1   ;
+        UINT32    reserved_0            : 31  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_st_b_0;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_varible_out_b    : 16  ;
+        UINT32    reserved_0            : 16  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_st_b_1;
+
+
+typedef union
+{
+
+    struct
+    {
+        UINT32    skew_dcell_out_b_h    : 4   ;
+        UINT32    reserved_0            : 28  ;
+    } Bits;
+
+
+    UINT32    UInt32;
+
+} u_sc_skew_st_b_3;
+
+#endif
+
+
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S
new file mode 100644
index 0000000..3422df2
--- /dev/null
+++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S
@@ -0,0 +1,61 @@
+//
+//  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+//  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+//  Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//  Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
+  ret
+
+# IN None
+# OUT x0 = number of cores present in the system
+ASM_FUNC(ArmGetCpuCountPerCluster)
+  MOV32 (w0, FixedPcdGet32(PcdCoreCount))
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+  MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
+  cmp   w0, w1
+  cset  x0, eq
+  ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #6
+  ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c
new file mode 100644
index 0000000..07ab0d1
--- /dev/null
+++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c
@@ -0,0 +1,107 @@
+/** @file
+*
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+UINTN
+ArmGetCpuCountPerCluster (
+  VOID
+  );
+
+extern  EFI_STATUS MemInitEntry (VOID);
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  return RETURN_SUCCESS;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+  // Nothing to do here
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &mArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof(gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
new file mode 100644
index 0000000..e86e53e
--- /dev/null
+++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
@@ -0,0 +1,69 @@
+#/* @file
+#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmPlatformLibPv660
+  FILE_GUID                      = 6887500D-32AD-41cd-855E-F8A5D5B0D4D2
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  MemoryAllocationLib
+  SerialPortLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  ArmPlatformLibMem.c
+
+[Sources.AARCH64]
+  AArch64/Helper.S
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+  gHisiTokenSpaceGuid.PcdNORFlashBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gHisiTokenSpaceGuid.PcdSysControlBaseAddress
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
+  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase
+
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c
new file mode 100644
index 0000000..b7bc75d
--- /dev/null
+++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c
@@ -0,0 +1,97 @@
+/** @file
+*
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Library/OemSetVirtualMapDesc.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          32
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  UINTN                         Index;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+  EFI_PEI_HOB_POINTERS          NextHob;
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+      return;
+  }
+
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+      CacheAttributes = DDR_ATTRIBUTES_CACHED;
+  } else {
+      CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+  }
+
+  Index = OemSetVirtualMapDesc(VirtualMemoryTable, CacheAttributes);
+
+  // Search for System Memory Hob that contains the EFI resource system memory
+  NextHob.Raw = GetHobList ();
+  while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL)
+  {
+    if (NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)
+    {
+        if (NextHob.ResourceDescriptor->PhysicalStart > BASE_4GB)
+        {
+            VirtualMemoryTable[++Index].PhysicalBase = NextHob.ResourceDescriptor->PhysicalStart;
+            VirtualMemoryTable[Index].VirtualBase  = NextHob.ResourceDescriptor->PhysicalStart;
+            VirtualMemoryTable[Index].Length       =NextHob.ResourceDescriptor->ResourceLength;
+            VirtualMemoryTable[Index].Attributes   =  CacheAttributes;
+        }
+    }
+
+    NextHob.Raw = GET_NEXT_HOB (NextHob);
+  }
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase = 0;
+  VirtualMemoryTable[Index].VirtualBase  = 0;
+  VirtualMemoryTable[Index].Length       = 0;
+  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+  DEBUG((EFI_D_INFO, "[%a]:[%dL] discriptor count=%d\n", __FUNCTION__, __LINE__, Index+1));
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardLib.inf b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
index b6c76a1..fa308bd 100755..100644
--- a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardLib.inf
+++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
@@ -1,5 +1,7 @@
 #/* @file
-#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -9,12 +11,14 @@
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
+#  Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/
+#
 #*/
 
 [Defines]
   INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardLib
-  FILE_GUID                      = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+  BASE_NAME                      = ArmPlatformLibPv660Sec
+  FILE_GUID                      = a79eed97-4b98-4974-9690-37b32d6a5b56
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = ArmPlatformLib
@@ -25,30 +29,28 @@
   EmbeddedPkg/EmbeddedPkg.dec
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-  OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dec
 
 [LibraryClasses]
   IoLib
   ArmLib
-  MemoryAllocationLib
+  SerialPortLib
 
 [Sources.common]
-  BeagleBoardHelper.asm  | RVCT
-  BeagleBoardHelper.S    | GCC
-  BeagleBoard.c
-  BeagleBoardMem.c
-  PadConfiguration.c
-  Clock.c
-  BeagleBoardHelper.S    | GCC
-  BeagleBoardHelper.asm  | RVCT
+  ArmPlatformLib.c
+
+[Sources.AARCH64]
+  AArch64/Helper.S
 
 [FeaturePcd]
   gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
 
 [FixedPcd]
-  gArmTokenSpaceGuid.PcdFdBaseAddress
-  gArmTokenSpaceGuid.PcdFdSize
-
   gArmTokenSpaceGuid.PcdSystemMemoryBase
   gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.c b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.c
new file mode 100644
index 0000000..72bb7f5
--- /dev/null
+++ b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.c
@@ -0,0 +1,53 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CpldIoLib.h>
+
+
+VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue)
+{
+    MmioWrite8 (ulRegAddr + PcdGet64(PcdCpldBaseAddress), ulValue);
+}
+
+
+UINT8 ReadCpldReg(UINTN ulRegAddr)
+{
+    return MmioRead8 (ulRegAddr + PcdGet64(PcdCpldBaseAddress));
+}
+
+
+VOID ReadCpldBytes(UINT16 Addr, UINT8 *Data, UINT8 Bytes)
+{
+    UINT8 i;
+
+    for(i = 0;i < Bytes; i++)
+    {
+        *(Data + i) = ReadCpldReg(Addr + i);
+    }
+}
+
+VOID WriteCpldBytes(UINT16 Addr, UINT8 *Data, UINT8 Bytes)
+{
+    UINT8 i;
+
+    for(i = 0; i < Bytes; i++)
+    {
+        WriteCpldReg(Addr + i, *(Data + i));
+    }
+}
diff --git a/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
new file mode 100644
index 0000000..d6e23cc
--- /dev/null
+++ b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
@@ -0,0 +1,47 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = CpldIoLib
+  FILE_GUID                      = 4633665C-0029-464E-9788-58B8D49FF57E
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = CpldIoLib
+
+[Sources.common]
+  CpldIoLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  BaseLib
+  ArmLib
+  TimerLib
+
+[BuildOptions]
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdCpldBaseAddress
diff --git a/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.c b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.c
new file mode 100644
index 0000000..d327527
--- /dev/null
+++ b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.c
@@ -0,0 +1,104 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Guid/EventGroup.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/CpldIoLib.h>
+
+UINTN           mCpldRegAddr;
+EFI_EVENT       mCpldVirtualAddressChangeEvent;
+
+
+VOID
+EFIAPI
+CpldVirtualAddressChange (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  EfiConvertPointer (0, (VOID **) &mCpldRegAddr);
+
+  return;
+}
+
+RETURN_STATUS
+EFIAPI
+CpldRuntimeLibConstructor (
+    VOID
+)
+{
+    EFI_STATUS              Status;
+    EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0};
+
+    mCpldRegAddr = PcdGet64(PcdCpldBaseAddress);
+    Status = gDS->GetMemorySpaceDescriptor(mCpldRegAddr,&desp);
+    if(EFI_ERROR(Status)){
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL] GetMemorySpaceDescriptor failed: %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+    desp.Attributes |= EFI_MEMORY_RUNTIME;
+    Status = gDS->SetMemorySpaceAttributes(mCpldRegAddr,0x10000, desp.Attributes);
+    if(EFI_ERROR(Status)){
+        DEBUG ((EFI_D_ERROR, "[%a]:[%dL] SetMemorySpaceAttributes failed: %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+    //
+    // Register notify function for EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
+    //
+    Status = gBS->CreateEventEx (
+                    EVT_NOTIFY_SIGNAL,
+                    TPL_NOTIFY,
+                    CpldVirtualAddressChange,
+                    NULL,
+                    &gEfiEventVirtualAddressChangeGuid,
+                    &mCpldVirtualAddressChangeEvent
+                    );
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+}
+
+EFI_STATUS
+EFIAPI
+CpldRuntimeLibDestructor (
+    VOID
+  )
+{
+  EFI_STATUS  Status = EFI_SUCCESS;
+
+  if(!mCpldVirtualAddressChangeEvent ){
+     return Status;
+  }
+
+  Status = gBS->CloseEvent(mCpldVirtualAddressChangeEvent);
+  return Status;
+}
+
+VOID WriteCpldReg(UINTN ulRegAddr, UINT8 ulValue)
+{
+    MmioWrite8 (ulRegAddr + mCpldRegAddr, ulValue);
+}
+
+UINT8 ReadCpldReg(UINTN ulRegAddr)
+{
+    return MmioRead8 (ulRegAddr + mCpldRegAddr);
+}
+
+
diff --git a/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
new file mode 100644
index 0000000..894e45b
--- /dev/null
+++ b/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = CpldIoLibRuntime
+  FILE_GUID                      = C0939398-4AF5-43d0-B6FF-37996D642C04
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = CpldIoLib
+  CONSTRUCTOR                    = CpldRuntimeLibConstructor
+  DESTRUCTOR                     = CpldRuntimeLibDestructor
+
+[Sources.common]
+  CpldIoLibRuntime.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+  UefiRuntimeLib
+  UefiBootServicesTableLib
+  DxeServicesTableLib
+  DebugLib
+  IoLib
+  BaseLib
+  TimerLib
+  PcdLib
+
+[BuildOptions]
+
+[Guids]
+  gEfiEventVirtualAddressChangeGuid
+[Pcd]
+  gHisiTokenSpaceGuid.PcdCpldBaseAddress
diff --git a/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h
new file mode 100644
index 0000000..d1e6c41
--- /dev/null
+++ b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h
@@ -0,0 +1,178 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+**/
+
+
+#ifndef __DS3231_REAL_TIME_CLOCK_H__
+#define __DS3231_REAL_TIME_CLOCK_H__
+
+#define DS3231_REGADDR_SECONDS      0x00
+#define DS3231_REGADDR_MIUTES       0x01
+#define DS3231_REGADDR_HOURS        0x02
+#define DS3231_REGADDR_DAY          0x03
+#define DS3231_REGADDR_DATE         0x04
+#define DS3231_REGADDR_MONTH        0x05
+#define DS3231_REGADDR_YEAR         0x06
+#define DS3231_REGADDR_ALARM1SEC    0x07
+#define DS3231_REGADDR_ALARM1MIN    0x08
+#define DS3231_REGADDR_ALARM1HOUR   0x09
+#define DS3231_REGADDR_ALARM1DAY    0x0A
+#define DS3231_REGADDR_ALARM2MIN    0x0B
+#define DS3231_REGADDR_ALARM2HOUR   0x0C
+#define DS3231_REGADDR_ALARM2DAY    0x0D
+#define DS3231_REGADDR_CONTROL      0x0E
+#define DS3231_REGADDR_STATUS       0x0F
+#define DS3231_REGADDR_AGOFFSET     0x10
+#define DS3231_REGADDR_TEMPMSB      0x11
+#define DS3231_REGADDR_TEMPLSB      0x12
+
+
+typedef union {
+  struct{
+    UINT8 A1IE:1;
+    UINT8 A2IE:1;
+    UINT8 INTCN:1;
+    UINT8 RSV:2;
+    UINT8 CONV:1;
+    UINT8 BBSQW:1;
+    UINT8 EOSC_N:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_CONTROL;
+
+typedef union {
+  struct{
+    UINT8 A1F:1;
+    UINT8 A2F:1;
+    UINT8 BSY:1;
+    UINT8 EN32KHZ:2;
+    UINT8 Rsv:3;
+    UINT8 OSF:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_STATUS;
+
+
+typedef union {
+  struct{
+    UINT8 Data:7;
+    UINT8 Sign:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_AGOFFSET;
+
+typedef union {
+  struct{
+    UINT8 Data:7;
+    UINT8 Sign:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_TEMPMSB;
+
+
+typedef union {
+  struct{
+    UINT8 Rsv:6;
+    UINT8 Data:2;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_TEMPLSB;
+
+typedef union {
+  struct{
+    UINT8 Seconds:4;
+    UINT8 Seconds10:3;
+    UINT8 Rsv:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_SECONDS;
+
+typedef union {
+  struct{
+    UINT8 Minutes:4;
+    UINT8 Minutes10:3;
+    UINT8 Rsv:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_MINUTES;
+
+typedef union {
+  struct{
+    UINT8 Hour:4;
+    UINT8 Hours10:1;
+    UINT8 PM_20Hours:1;
+    UINT8 Hour24_n:1;
+    UINT8 Rsv:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_HOURS;
+
+typedef union {
+  struct{
+    UINT8 Day:3;
+    UINT8 Rsv:5;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_DAY;
+
+typedef union {
+  struct{
+    UINT8 Month:4;
+    UINT8 Month10:1;
+    UINT8 Rsv:2;
+    UINT8 Century:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_MONTH;
+
+typedef union {
+  struct{
+    UINT8 Year:4;
+    UINT8 Year10:4;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_YEAR;
+
+typedef union {
+  struct{
+    UINT8 Seconds:4;
+    UINT8 Seconds10:3;
+    UINT8 A1M1:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_ALARM1SEC;
+
+typedef union {
+  struct{
+    UINT8 Minutes:4;
+    UINT8 Minutes10:3;
+    UINT8 A1M2:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_ALARM1MIN;
+
+typedef union {
+  struct{
+    UINT8 Hour:4;
+    UINT8 Hours10:1;
+    UINT8 PM_20Hours:1;
+    UINT8 Hours24:1;
+    UINT8 A1M3:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_ALARM1HOUR;
+
+#endif
diff --git a/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
new file mode 100644
index 0000000..693ddd8
--- /dev/null
+++ b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
@@ -0,0 +1,433 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Currently this driver does not support runtime virtual calling.
+
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+// Use EfiAtRuntime to check stage
+#include <Library/UefiRuntimeLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/TimerLib.h>
+#include <Library/EfiTimeBaseLib.h>
+#include <Protocol/RealTimeClock.h>
+#include <Library/I2CLib.h>
+#include "DS3231RealTimeClock.h"
+
+extern I2C_DEVICE gDS3231RtcDevice;
+
+STATIC BOOLEAN       mDS3231Initialized = FALSE;
+
+EFI_STATUS
+IdentifyDS3231 (
+  VOID
+  )
+{
+  EFI_STATUS    Status;
+
+  Status = EFI_SUCCESS;
+  return Status;
+}
+
+EFI_STATUS
+InitializeDS3231 (
+  VOID
+  )
+{
+  EFI_STATUS    Status;
+  I2C_DEVICE    Dev;
+  RTC_DS3231_CONTROL Temp;
+  RTC_DS3231_HOURS   Hours;
+
+  // Prepare the hardware
+  (VOID)IdentifyDS3231();
+
+  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+  Status = I2CInit(Dev.Socket,Dev.Port,Normal);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+  // Ensure interrupts are masked. We do not want RTC interrupts in UEFI
+  Status = I2CRead(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+  Temp.bits.INTCN = 0;
+  Status = I2CWrite(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+
+  MicroSecondDelay(2000);
+  Status = I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+  Hours.bits.Hour24_n = 0;
+  Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+
+
+  mDS3231Initialized = TRUE;
+
+  EXIT:
+  return Status;
+}
+
+
+/**
+  Returns the current time and date information, and the time-keeping capabilities
+  of the hardware platform.
+
+  @param  Time                   A pointer to storage to receive a snapshot of the current time.
+  @param  Capabilities           An optional pointer to a buffer to receive the real time clock
+                                 device's capabilities.
+
+  @retval EFI_SUCCESS            The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER  Time is NULL.
+  @retval EFI_DEVICE_ERROR       The time could not be retrieved due to hardware error.
+  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT EFI_TIME                *Time,
+  OUT EFI_TIME_CAPABILITIES   *Capabilities
+  )
+{
+  EFI_STATUS  Status = EFI_SUCCESS;
+  UINT8       Temp;
+  UINT8       BaseHour = 0;
+  UINT16      BaseYear = 1900;
+
+  I2C_DEVICE    Dev;
+
+  // Ensure Time is a valid pointer
+  if (NULL == Time) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Initialize the hardware if not already done
+  if (!mDS3231Initialized) {
+    Status = InitializeDS3231 ();
+    if (EFI_ERROR (Status)) {
+      return EFI_NOT_READY;
+    }
+  }
+
+  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+
+  Time->Month = ((Temp>>4)&1)*10+(Temp&0x0F);
+
+
+  if(Temp&0x80){
+    BaseYear = 2000;
+  }
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_YEAR,1,&Temp);
+
+  Time->Year  = BaseYear+(Temp>>4) *10 + (Temp&0x0F);
+
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_DATE,1,&Temp);
+
+  Time->Day   = ((Temp>>4)&3) *10 + (Temp&0x0F);
+
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Temp);
+
+  BaseHour = 0;
+  if((Temp&0x30) == 0x30){
+    return EFI_DEVICE_ERROR;
+  }else if(Temp&0x20){
+    BaseHour = 20;
+  }else if(Temp&0x10){
+    BaseHour = 10;
+  }
+  Time->Hour        = BaseHour + (Temp&0x0F);
+
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_MIUTES,1,&Temp);
+
+  Time->Minute      = ((Temp>>4)&7) * 10 + (Temp&0x0F);
+
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_SECONDS,1,&Temp);
+
+  Time->Second      = (Temp>>4) * 10 + (Temp&0x0F);
+
+  Time->Nanosecond  = 0;
+  Time->Daylight    = 0;
+  Time->TimeZone    = EFI_UNSPECIFIED_TIMEZONE;
+
+  if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time                  A pointer to the current time.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+  IN  EFI_TIME                *Time
+  )
+{
+  EFI_STATUS  Status = EFI_SUCCESS;
+  I2C_DEVICE    Dev;
+  UINT8 Temp;
+  UINT16 BaseYear = 1900;
+
+  // Check the input parameters are within the range specified by UEFI
+  if(!IsTimeValid(Time)){
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Initialize the hardware if not already done
+  if (!mDS3231Initialized) {
+    Status = InitializeDS3231 ();
+    if (EFI_ERROR (Status)) {
+      goto EXIT;
+    }
+  }
+
+  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+  Temp = ((Time->Second/10)<<4) | (Time->Second%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_SECONDS,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = ((Time->Minute/10)<<4) | (Time->Minute%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_MIUTES,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = 0;
+  if(Time->Hour > 19){
+    Temp = 2;
+  } else if(Time->Hour > 9){
+    Temp = 1;
+  }
+  Temp = (Temp << 4) | (Time->Hour%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = ((Time->Day/10)<<4) | (Time->Day%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_DATE,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = 0;
+  if(Time->Year >= 2000){
+    Temp = 0x8;
+    BaseYear = 2000;
+  }
+
+  if(Time->Month > 9){
+    Temp |= 0x1;
+  }
+  Temp = (Temp<<4) | (Time->Month%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = (((Time->Year-BaseYear)/10)<<4) | (Time->Year%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_YEAR,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  EXIT:
+  return Status;
+}
+
+
+/**
+  Returns the current wakeup alarm clock setting.
+
+  @param  Enabled               Indicates if the alarm is currently enabled or disabled.
+  @param  Pending               Indicates if the alarm signal is pending and requires acknowledgement.
+  @param  Time                  The current alarm setting.
+
+  @retval EFI_SUCCESS           The alarm settings were returned.
+  @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+  OUT BOOLEAN     *Enabled,
+  OUT BOOLEAN     *Pending,
+  OUT EFI_TIME    *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+
+/**
+  Sets the system wakeup alarm clock time.
+
+  @param  Enabled               Enable or disable the wakeup alarm.
+  @param  Time                  If Enable is TRUE, the time to set the wakeup alarm for.
+
+  @retval EFI_SUCCESS           If Enable is TRUE, then the wakeup alarm was enabled. If
+                                Enable is FALSE, then the wakeup alarm was disabled.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be set due to a hardware error.
+  @retval EFI_UNSUPPORTED       A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+  IN BOOLEAN      Enabled,
+  OUT EFI_TIME    *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+  This is the declaration of an EFI image entry point. This can be the entry point to an application
+  written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+  @param  ImageHandle           Handle that identifies the loaded image.
+  @param  SystemTable           System Table for this image.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS    Status;
+  EFI_HANDLE    Handle;
+
+
+  EFI_TIME      EfiTime;
+
+  // Setup the setters and getters
+  gRT->GetTime       = LibGetTime;
+  gRT->SetTime       = LibSetTime;
+  gRT->GetWakeupTime = LibGetWakeupTime;
+  gRT->SetWakeupTime = LibSetWakeupTime;
+
+  Status = gRT->GetTime (&EfiTime, NULL);
+  if(EFI_ERROR (Status) || (EfiTime.Year < 2000) || (EfiTime.Year > 2099)){
+      EfiTime.Year          = 2000;
+      EfiTime.Month         = 1;
+      EfiTime.Day           = 1;
+      EfiTime.Hour          = 0;
+      EfiTime.Minute        = 0;
+      EfiTime.Second        = 0;
+      EfiTime.Nanosecond    = 0;
+      EfiTime.Daylight      = 0;
+      EfiTime.TimeZone      = EFI_UNSPECIFIED_TIMEZONE;
+
+      Status = gRT->SetTime(&EfiTime);
+      if (EFI_ERROR(Status))
+      {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status));
+      }
+  }
+
+  // Install the protocol
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gEfiRealTimeClockArchProtocolGuid,  NULL,
+                  NULL
+                 );
+
+  return Status;
+}
+
+
+/**
+  Fixup internal data so that EFI can be call in virtual mode.
+  Call the passed in Child Notify event and convert any pointers in
+  lib to virtual mode.
+
+  @param[in]    Event   The Event that is being processed
+  @param[in]    Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  //
+  // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+  // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+  // to virtual address. After the OS transitions to calling in virtual mode, all future
+  // runtime calls will be made in virtual mode.
+  //
+  return;
+}
diff --git a/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
new file mode 100644
index 0000000..10ce5ff
--- /dev/null
+++ b/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
@@ -0,0 +1,49 @@
+#/** @file
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#  Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = DS3231RealTimeClockLib
+  FILE_GUID                      = 470DFB96-E205-4515-A75E-2E60F853E79D
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RealTimeClockLib
+
+[Sources.common]
+  DS3231RealTimeClockLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/OpenPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  IoLib
+  UefiLib
+  DebugLib
+  PcdLib
+  I2CLib
+  TimerLib
+# Use EFiAtRuntime to check stage
+  UefiRuntimeLib
+  EfiTimeBaseLib
+
+[Pcd]
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c
new file mode 100644
index 0000000..ce70ca5
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c
@@ -0,0 +1,302 @@
+/** @file
+  UART Serial Port library functions
+
+  Copyright (c) 2006 - 2009, Intel Corporation
+  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
+  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+**/
+#include <Uefi.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/IoLib.h>
+#include <Protocol/SerialIo.h>
+
+#include "Dw8250SerialPortLib.h"
+
+
+/**
+  Initialize the serial device hardware.
+
+  If no initialization is required, then return RETURN_SUCCESS.
+  If the serial device was successfuly initialized, then return RETURN_SUCCESS.
+  If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+  @retval RETURN_SUCCESS        The serial device was initialized.
+  @retval RETURN_DEVICE_ERROR   The serail device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+  VOID
+  )
+{
+    UINT32 ulUartClkFreq;
+
+    MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8);
+    MmioWrite8 (UART_FCR_REG, UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR);
+    MmioWrite8 (UART_LCR_REG, UART_LCR_DLAB | UART_LCR_DLS8);
+
+    ulUartClkFreq = PcdGet32(PcdUartClkInHz);
+
+    MmioWrite8 (UART_DLL_REG, (ulUartClkFreq / (16 * (UINT32)BAUDRATE) ) & 0xff);
+    MmioWrite8 (UART_DLH_REG, ((ulUartClkFreq/ (16 * (UINT32)BAUDRATE) ) >> 8 ) & 0xff);
+    MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8);
+    MmioWrite8 (UART_IEL_REG, 0x00);
+
+    return RETURN_SUCCESS;
+}
+
+
+/**
+  Write data from buffer to serial device.
+
+  Writes NumberOfBytes data bytes from Buffer to the serial device.
+  The number of bytes actually written to the serial device is returned.
+  If the return value is less than NumberOfBytes, then the write operation failed.
+
+  If Buffer is NULL, then ASSERT().
+
+  If NumberOfBytes is zero, then return 0.
+
+  @param  Buffer           Pointer to the data buffer to be written.
+  @param  NumberOfBytes    Number of bytes to written to the serial device.
+
+  @retval 0                NumberOfBytes is 0.
+  @retval >0               The number of bytes written to the serial device.
+                           If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+  IN UINT8     *Buffer,
+  IN UINTN     NumberOfBytes
+)
+{
+  UINTN  Result;
+
+  if (NULL == Buffer) {
+    return 0;
+  }
+
+  Result = NumberOfBytes;
+
+  while (NumberOfBytes--) {
+
+    SerialPortWriteChar(*Buffer);
+    Buffer++;
+  }
+
+  return Result;
+}
+
+
+/**
+  Reads data from a serial device into a buffer.
+
+  @param  Buffer           Pointer to the data buffer to store the data read from the serial device.
+  @param  NumberOfBytes    Number of bytes to read from the serial device.
+
+  @retval 0                NumberOfBytes is 0.
+  @retval >0               The number of bytes read from the serial device.
+                           If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+  OUT UINT8     *Buffer,
+  IN  UINTN     NumberOfBytes
+)
+{
+  UINTN  Result;
+
+  if (NULL == Buffer) {
+    return 0;
+  }
+
+  Result = 0;
+
+  while (NumberOfBytes--) {
+    //
+    // Wait for the serail port to be ready.
+    //
+    *Buffer=SerialPortReadChar();
+    Buffer++ ;
+    Result++;
+  }
+
+  return Result;
+}
+
+/**
+  Polls a serial device to see if there is any data waiting to be read.
+
+  Polls aserial device to see if there is any data waiting to be read.
+  If there is data waiting to be read from the serial device, then TRUE is returned.
+  If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+  @retval TRUE             Data is waiting to be read from the serial device.
+  @retval FALSE            There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+  VOID
+  )
+{
+
+  return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR);
+
+}
+
+
+VOID SerialPortWriteChar(UINT8 scShowChar)
+{
+    UINT32 ulLoop = 0;
+
+    while(ulLoop < (UINT32)UART_SEND_DELAY)
+    {
+
+        if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02)
+        {
+            break;
+        }
+
+        ulLoop++;
+    }
+    MmioWrite8 (UART_THR_REG, (UINT8)scShowChar);
+
+    ulLoop = 0;
+    while(ulLoop < (UINT32)UART_SEND_DELAY)
+    {
+        if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04)
+        {
+            break;
+        }
+        ulLoop++;
+    }
+
+    return;
+}
+
+
+UINT8 SerialPortReadChar(VOID)
+{
+    UINT8 recvchar = 0;
+
+    while(1)
+    {
+        if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR)
+        {
+            break;
+        }
+    }
+
+    recvchar = MmioRead8 (UART_RBR_REG);
+
+    return recvchar;
+}
+
+/**
+  Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+  data bits, and stop bits on a serial device.
+
+  @param BaudRate           The requested baud rate. A BaudRate value of 0 will use the
+                            device's default interface speed.
+                            On output, the value actually set.
+  @param ReveiveFifoDepth   The requested depth of the FIFO on the receive side of the
+                            serial interface. A ReceiveFifoDepth value of 0 will use
+                            the device's default FIFO depth.
+                            On output, the value actually set.
+  @param Timeout            The requested time out for a single character in microseconds.
+                            This timeout applies to both the transmit and receive side of the
+                            interface. A Timeout value of 0 will use the device's default time
+                            out value.
+                            On output, the value actually set.
+  @param Parity             The type of parity to use on this serial device. A Parity value of
+                            DefaultParity will use the device's default parity value.
+                            On output, the value actually set.
+  @param DataBits           The number of data bits to use on the serial device. A DataBits
+                            vaule of 0 will use the device's default data bit setting.
+                            On output, the value actually set.
+  @param StopBits           The number of stop bits to use on this serial device. A StopBits
+                            value of DefaultStopBits will use the device's default number of
+                            stop bits.
+                            On output, the value actually set.
+
+  @retval RETURN_SUCCESS            The new attributes were set on the serial device.
+  @retval RETURN_UNSUPPORTED        The serial device does not support this operation.
+  @retval RETURN_INVALID_PARAMETER  One or more of the attributes has an unsupported value.
+  @retval RETURN_DEVICE_ERROR       The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+  IN OUT UINT64             *BaudRate,
+  IN OUT UINT32             *ReceiveFifoDepth,
+  IN OUT UINT32             *Timeout,
+  IN OUT EFI_PARITY_TYPE    *Parity,
+  IN OUT UINT8              *DataBits,
+  IN OUT EFI_STOP_BITS_TYPE *StopBits
+  )
+{
+  return RETURN_UNSUPPORTED;
+}
+
+/**
+  Set the serial device control bits.
+
+  @param  Control                 Control bits which are to be set on the serial device.
+
+  @retval EFI_SUCCESS             The new control bits were set on the serial device.
+  @retval EFI_UNSUPPORTED         The serial device does not support this operation.
+  @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+  IN UINT32                  Control
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Get the serial device control bits.
+
+  @param  Control                 Control signals read from the serial device.
+
+  @retval EFI_SUCCESS             The control bits were read from the serial device.
+  @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+  OUT UINT32                  *Control
+  )
+{
+
+    if (SerialPortPoll ()) {
+        // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY
+        *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+    } else {
+        *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+    }
+    return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h
new file mode 100644
index 0000000..5e80257
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h
@@ -0,0 +1,116 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+**/
+
+#ifndef __DW8250_SERIALPORTLIB_H__
+#define __DW8250_SERIALPORTLIB_H__
+
+
+#define SERIAL_0_BASE_ADR     (PcdGet64(PcdSerialRegisterBase))
+
+
+#define UART_SEND_DELAY      (PcdGet32(PcdSerialPortSendDelay))
+#define BAUDRATE             (PcdGet64(PcdUartDefaultBaudRate))
+
+
+#define UART_THR_REG         (SERIAL_0_BASE_ADR + UART_THR)
+#define UART_RBR_REG         (SERIAL_0_BASE_ADR + UART_RBR)
+#define UART_DLL_REG         (SERIAL_0_BASE_ADR + UART_DLL)
+#define UART_DLH_REG         (SERIAL_0_BASE_ADR + UART_DLH)
+#define UART_IEL_REG         (SERIAL_0_BASE_ADR + UART_IEL)
+#define UART_IIR_REG         (SERIAL_0_BASE_ADR + UART_IIR)
+#define UART_FCR_REG         (SERIAL_0_BASE_ADR + UART_FCR)
+#define UART_LCR_REG         (SERIAL_0_BASE_ADR + UART_LCR)
+#define UART_LSR_REG         (SERIAL_0_BASE_ADR + UART_LSR)
+#define UART_USR_REG         (SERIAL_0_BASE_ADR + UART_USR)
+
+
+#define UART_RBR     0x00
+#define UART_THR     0x00
+#define UART_DLL     0x00
+#define UART_DLH     0x04
+#define UART_IEL     0x04
+#define UART_IIR     0x08
+#define UART_FCR     0x08
+#define UART_LCR     0x0C
+#define UART_MCR     0x10
+#define UART_LSR     0x14
+#define UART_USR     0x7C
+
+/* register definitions */
+
+#define UART_FCR_EN          0x01
+#define UART_FCR_RXCLR       0x02
+#define UART_FCR_TXCLR       0x04
+#define UART_FCR_CLEARFIFO   0x00
+#define UART_FCR_RXL1        0x00
+#define UART_FCR_RXL4        0x40
+#define UART_FCR_RXL8        0x80
+#define UART_FCR_RXL14       0xc0
+#define UART_FCR_TXL0        0x00
+#define UART_FCR_TXL4        0x20
+#define UART_FCR_TXL8        0x30
+#define UART_FCR_TXL14       0x10
+
+/*LCR Name: Line Control Register fields*/
+#define UART_LCR_DLAB   0x80
+#define UART_LCR_EPS    0x10
+#define UART_LCR_PEN    0x08
+#define UART_LCR_STOP   0x04
+#define UART_LCR_DLS8   0x03
+#define UART_LCR_DLS7   0x02
+#define UART_LCR_DLS6   0x01
+#define UART_LCR_DLS5   0x00
+
+
+#define UART_DLH_AND_DLL_WIDTH 0xFF
+
+
+#define UART_IER_PTIME  0x80
+#define UART_IER_ELSI   0x04
+#define UART_IER_ETBEI  0x02
+#define UART_IER_ERBFI  0x01
+
+
+#define UART_IIR_FIFOSE         0xC0
+
+
+#define UART_IIR_InterruptID   0x01
+#define UART_IIR_INTIDTE       0x02
+#define UART_IIR_INTIDRA       0x04
+#define UART_IIR_INTIDRLS      0x06
+#define UART_IIR_INTMASK       0x0f
+#define UART_IIR_RDA           0x04
+#define UART_IIR_TE            0x02
+
+#define UART_LSR_TEMT       0x40
+#define UART_LSR_THRE       0x20
+#define UART_LSR_BI         0x10
+#define UART_LSR_FE         0x08
+#define UART_LSR_PE         0x04
+#define UART_LSR_R          0x02
+#define UART_LSR_DR         0x01
+
+
+#define UART_USR_BUSY  0x01
+
+#define FIFO_MAXSIZE    32
+
+extern UINT8 SerialPortReadChar(VOID);
+extern VOID SerialPortWriteChar(UINT8 scShowChar);
+
+#endif
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
new file mode 100644
index 0000000..6161e95
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
@@ -0,0 +1,45 @@
+#/** @file
+#
+#  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Dw8250SerialPortLib
+  FILE_GUID                      = 16D53E86-7EA6-47bd-861F-511ED9B8ABE0
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SerialPortLib
+
+
+[Sources.common]
+  Dw8250SerialPortLib.c
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay
+  gHisiTokenSpaceGuid.PcdUartClkInHz
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c
new file mode 100644
index 0000000..d092659
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.c
@@ -0,0 +1,356 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+**/
+#include <Uefi.h>
+#include <PiDxe.h>
+
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+
+#include <Protocol/SerialIo.h>
+#include <Guid/EventGroup.h>
+#include "Dw8250SerialPortRuntimeLib.h"
+
+UINT64    mSerialRegBaseAddr = 0;
+
+EFI_EVENT   mSerialVirtualAddressChangeEvent = NULL;
+
+VOID
+EFIAPI
+SerialVirtualAddressChangeCallBack (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  EfiConvertPointer (0, (VOID **) &mSerialRegBaseAddr);
+
+  return;
+}
+
+
+EFI_STATUS
+EFIAPI
+SerialPortLibDestructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS  Status = EFI_SUCCESS;
+
+  if(!mSerialVirtualAddressChangeEvent ){
+     return Status;
+  }
+
+  Status = gBS->CloseEvent(mSerialVirtualAddressChangeEvent);
+  return Status;
+}
+
+/**
+  Initialize the serial device hardware.
+
+  If no initialization is required, then return RETURN_SUCCESS.
+  If the serial device was successfuly initialized, then return RETURN_SUCCESS.
+  If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+  @retval RETURN_SUCCESS        The serial device was initialized.
+  @retval RETURN_DEVICE_ERROR   The serail device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+  VOID
+  )
+{
+    EFI_STATUS  Status = EFI_SUCCESS;
+    EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0};
+
+    mSerialRegBaseAddr = PcdGet64(PcdSerialRegisterBase);
+
+    Status = gDS->GetMemorySpaceDescriptor(PcdGet64(PcdSerialRegisterBase),&desp);
+    if(EFI_ERROR(Status)){
+        return Status;
+    }
+    desp.Attributes |= EFI_MEMORY_RUNTIME;
+    Status = gDS->SetMemorySpaceAttributes(PcdGet64(PcdSerialRegisterBase),PcdGet64(PcdSerialRegisterSpaceSize), desp.Attributes);
+    if(EFI_ERROR(Status)){
+        return Status;
+    }
+
+    Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  SerialVirtualAddressChangeCallBack,
+                  NULL,
+                  &gEfiEventVirtualAddressChangeGuid,
+                  &mSerialVirtualAddressChangeEvent
+                  );
+
+    if(EFI_ERROR(Status)){
+        mSerialVirtualAddressChangeEvent = NULL;
+    }
+
+    return Status;
+}
+
+
+/**
+  Write data from buffer to serial device.
+
+  Writes NumberOfBytes data bytes from Buffer to the serial device.
+  The number of bytes actually written to the serial device is returned.
+  If the return value is less than NumberOfBytes, then the write operation failed.
+
+  If Buffer is NULL, then ASSERT().
+
+  If NumberOfBytes is zero, then return 0.
+
+  @param  Buffer           Pointer to the data buffer to be written.
+  @param  NumberOfBytes    Number of bytes to written to the serial device.
+
+  @retval 0                NumberOfBytes is 0.
+  @retval >0               The number of bytes written to the serial device.
+                           If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+  IN UINT8     *Buffer,
+  IN UINTN     NumberOfBytes
+)
+{
+  UINTN  Result;
+
+  if (NULL == Buffer) {
+    return 0;
+  }
+
+  Result = NumberOfBytes;
+
+  while (NumberOfBytes--) {
+
+    SerialPortWriteChar(*Buffer);
+    Buffer++;
+  }
+
+  return Result;
+}
+
+
+/**
+  Reads data from a serial device into a buffer.
+
+  @param  Buffer           Pointer to the data buffer to store the data read from the serial device.
+  @param  NumberOfBytes    Number of bytes to read from the serial device.
+
+  @retval 0                NumberOfBytes is 0.
+  @retval >0               The number of bytes read from the serial device.
+                           If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+  OUT UINT8     *Buffer,
+  IN  UINTN     NumberOfBytes
+)
+{
+  UINTN  Result;
+
+  if (NULL == Buffer) {
+    return 0;
+  }
+
+  Result = 0;
+
+  while (NumberOfBytes--) {
+    //
+    // Wait for the serail port to be ready.
+    //
+    *Buffer=SerialPortReadChar();
+    Buffer++ ;
+    Result++;
+  }
+
+  return Result;
+}
+
+/**
+  Polls a serial device to see if there is any data waiting to be read.
+
+  Polls aserial device to see if there is any data waiting to be read.
+  If there is data waiting to be read from the serial device, then TRUE is returned.
+  If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+  @retval TRUE             Data is waiting to be read from the serial device.
+  @retval FALSE            There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+  VOID
+  )
+{
+
+  return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR);
+
+}
+
+
+VOID SerialPortWriteChar(UINT8 scShowChar)
+{
+    UINT32 ulLoop = 0;
+
+    while(ulLoop < (UINT32)UART_SEND_DELAY)
+    {
+
+        if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02)
+        {
+            break;
+        }
+
+        ulLoop++;
+    }
+    MmioWrite8 (UART_THR_REG, (UINT8)scShowChar);
+
+    ulLoop = 0;
+    while(ulLoop < (UINT32)UART_SEND_DELAY)
+    {
+        if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04)
+        {
+            break;
+        }
+        ulLoop++;
+    }
+
+    return;
+}
+
+
+UINT8 SerialPortReadChar(VOID)
+{
+  UINT8 recvchar = 0;
+
+  do
+  {
+    if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR) {
+      break;
+    }
+
+  }while(MmioRead8 (UART_USR_REG) & UART_USR_BUSY);
+
+  recvchar = MmioRead8 (UART_RBR_REG);
+
+  return recvchar;
+}
+
+/**
+  Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+  data bits, and stop bits on a serial device.
+
+  @param BaudRate           The requested baud rate. A BaudRate value of 0 will use the
+                            device's default interface speed.
+                            On output, the value actually set.
+  @param ReveiveFifoDepth   The requested depth of the FIFO on the receive side of the
+                            serial interface. A ReceiveFifoDepth value of 0 will use
+                            the device's default FIFO depth.
+                            On output, the value actually set.
+  @param Timeout            The requested time out for a single character in microseconds.
+                            This timeout applies to both the transmit and receive side of the
+                            interface. A Timeout value of 0 will use the device's default time
+                            out value.
+                            On output, the value actually set.
+  @param Parity             The type of parity to use on this serial device. A Parity value of
+                            DefaultParity will use the device's default parity value.
+                            On output, the value actually set.
+  @param DataBits           The number of data bits to use on the serial device. A DataBits
+                            vaule of 0 will use the device's default data bit setting.
+                            On output, the value actually set.
+  @param StopBits           The number of stop bits to use on this serial device. A StopBits
+                            value of DefaultStopBits will use the device's default number of
+                            stop bits.
+                            On output, the value actually set.
+
+  @retval RETURN_SUCCESS            The new attributes were set on the serial device.
+  @retval RETURN_UNSUPPORTED        The serial device does not support this operation.
+  @retval RETURN_INVALID_PARAMETER  One or more of the attributes has an unsupported value.
+  @retval RETURN_DEVICE_ERROR       The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+  IN OUT UINT64             *BaudRate,
+  IN OUT UINT32             *ReceiveFifoDepth,
+  IN OUT UINT32             *Timeout,
+  IN OUT EFI_PARITY_TYPE    *Parity,
+  IN OUT UINT8              *DataBits,
+  IN OUT EFI_STOP_BITS_TYPE *StopBits
+  )
+{
+  return RETURN_UNSUPPORTED;
+}
+
+/**
+  Set the serial device control bits.
+
+  @param  Control                 Control bits which are to be set on the serial device.
+
+  @retval EFI_SUCCESS             The new control bits were set on the serial device.
+  @retval EFI_UNSUPPORTED         The serial device does not support this operation.
+  @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+  IN UINT32                  Control
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Get the serial device control bits.
+
+  @param  Control                 Control signals read from the serial device.
+
+  @retval EFI_SUCCESS             The control bits were read from the serial device.
+  @retval EFI_DEVICE_ERROR        The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+  OUT UINT32                  *Control
+  )
+{
+
+    if (SerialPortPoll ()) {
+        // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY
+        *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+    } else {
+        *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+    }
+    return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h
new file mode 100644
index 0000000..f5dcb9e
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.h
@@ -0,0 +1,116 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+**/
+
+#ifndef __DW8250_SERIALPORTLIB_H__
+#define __DW8250_SERIALPORTLIB_H__
+
+
+#define SERIAL_0_BASE_ADR     (mSerialRegBaseAddr)
+
+
+#define UART_SEND_DELAY      (PcdGet32(PcdSerialPortSendDelay))
+#define BAUDRATE             (PcdGet64(PcdUartDefaultBaudRate))
+
+
+#define UART_THR_REG         (SERIAL_0_BASE_ADR + UART_THR)
+#define UART_RBR_REG         (SERIAL_0_BASE_ADR + UART_RBR)
+#define UART_DLL_REG         (SERIAL_0_BASE_ADR + UART_DLL)
+#define UART_DLH_REG         (SERIAL_0_BASE_ADR + UART_DLH)
+#define UART_IEL_REG         (SERIAL_0_BASE_ADR + UART_IEL)
+#define UART_IIR_REG         (SERIAL_0_BASE_ADR + UART_IIR)
+#define UART_FCR_REG         (SERIAL_0_BASE_ADR + UART_FCR)
+#define UART_LCR_REG         (SERIAL_0_BASE_ADR + UART_LCR)
+#define UART_LSR_REG         (SERIAL_0_BASE_ADR + UART_LSR)
+#define UART_USR_REG         (SERIAL_0_BASE_ADR + UART_USR)
+
+
+#define UART_RBR     0x00
+#define UART_THR     0x00
+#define UART_DLL     0x00
+#define UART_DLH     0x04
+#define UART_IEL     0x04
+#define UART_IIR     0x08
+#define UART_FCR     0x08
+#define UART_LCR     0x0C
+#define UART_MCR     0x10
+#define UART_LSR     0x14
+#define UART_USR     0x7C
+
+/* register definitions */
+
+#define UART_FCR_EN          0x01
+#define UART_FCR_RXCLR       0x02
+#define UART_FCR_TXCLR       0x04
+#define UART_FCR_CLEARFIFO   0x00
+#define UART_FCR_RXL1        0x00
+#define UART_FCR_RXL4        0x40
+#define UART_FCR_RXL8        0x80
+#define UART_FCR_RXL14       0xc0
+#define UART_FCR_TXL0        0x00
+#define UART_FCR_TXL4        0x20
+#define UART_FCR_TXL8        0x30
+#define UART_FCR_TXL14       0x10
+
+/*LCR Name: Line Control Register fields*/
+#define UART_LCR_DLAB   0x80
+#define UART_LCR_EPS    0x10
+#define UART_LCR_PEN    0x08
+#define UART_LCR_STOP   0x04
+#define UART_LCR_DLS8   0x03
+#define UART_LCR_DLS7   0x02
+#define UART_LCR_DLS6   0x01
+#define UART_LCR_DLS5   0x00
+
+
+#define UART_DLH_AND_DLL_WIDTH 0xFF
+
+
+#define UART_IER_PTIME  0x80
+#define UART_IER_ELSI   0x04
+#define UART_IER_ETBEI  0x02
+#define UART_IER_ERBFI  0x01
+
+
+#define UART_IIR_FIFOSE         0xC0
+
+
+#define UART_IIR_InterruptID   0x01
+#define UART_IIR_INTIDTE       0x02
+#define UART_IIR_INTIDRA       0x04
+#define UART_IIR_INTIDRLS      0x06
+#define UART_IIR_INTMASK       0x0f
+#define UART_IIR_RDA           0x04
+#define UART_IIR_TE            0x02
+
+#define UART_LSR_TEMT       0x40
+#define UART_LSR_THRE       0x20
+#define UART_LSR_BI         0x10
+#define UART_LSR_FE         0x08
+#define UART_LSR_PE         0x04
+#define UART_LSR_R          0x02
+#define UART_LSR_DR         0x01
+
+
+#define UART_USR_BUSY  0x01
+
+#define FIFO_MAXSIZE    32
+
+extern UINT8 SerialPortReadChar(VOID);
+extern VOID SerialPortWriteChar(UINT8 scShowChar);
+
+#endif
+
diff --git a/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
new file mode 100644
index 0000000..c4ff57c
--- /dev/null
+++ b/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
@@ -0,0 +1,52 @@
+#/** @file
+#
+#  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Dw8250SerialPortLib
+  FILE_GUID                      = 16D53E86-7EA6-47bd-861F-511ED9B8ABE0
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SerialPortLib
+  DESTRUCTOR                     = SerialPortLibDestructor
+
+[Sources.common]
+  Dw8250SerialPortRuntimeLib.c
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  UefiRuntimeLib
+  UefiBootServicesTableLib
+  DxeServicesTableLib
+
+[Guids]
+  gEfiEventVirtualAddressChangeGuid             ## CONSUMES ## Event
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gHisiTokenSpaceGuid.PcdSerialRegisterSpaceSize
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay
+  gHisiTokenSpaceGuid.PcdUartClkInHz
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CHw.h b/Chips/Hisilicon/Library/I2CLib/I2CHw.h
new file mode 100644
index 0000000..aa561e9
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CHw.h
@@ -0,0 +1,269 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _I2C_HW_H_
+#define _I2C_HW_H_
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+
+#define I2C_READ_TIMEOUT             500
+#define I2C_DRV_ONCE_WRITE_BYTES_NUM 8
+#define I2C_DRV_ONCE_READ_BYTES_NUM  8
+#define I2C_READ_SIGNAL              0x0100
+#define I2C_TXRX_THRESHOLD           0x7
+#define I2C_SS_SCLHCNT               0x493
+#define I2C_SS_SCLLCNT               0x4fe
+#define I2C_CMD_STOP_BIT             BIT9
+
+#define I2C_REG_WRITE(reg,data) \
+     MmioWrite32 ((reg), (data))
+
+#define I2C_REG_READ(reg,result) \
+     (result) = MmioRead32 ((reg))
+
+ #define    I2C_CON_OFFSET                 0x0
+ #define    I2C_TAR_OFFSET                 0x4
+ #define    I2C_SAR_OFFSET                 0x8
+ #define    I2C_DATA_CMD_OFFSET            0x10
+ #define    I2C_SS_SCL_HCNT_OFFSET         0x14
+ #define    I2C_SS_SCL_LCNT_OFFSET         0x18
+ #define    I2C_FS_SCL_HCNT_OFFSET         0x1c
+ #define    I2C_FS_SCL_LCNT_OFFSET         0x20
+ #define    I2C_INTR_STAT_OFFSET           0x2c
+ #define    I2C_INTR_MASK_OFFSET           0x30
+ #define    I2C_RAW_INTR_STAT_OFFSET       0x34
+ #define    I2C_RX_TL_OFFSET               0x38
+ #define    I2C_TX_TL_OFFSET               0x3c
+ #define    I2C_CLR_INTR_OFFSET            0x40
+ #define    I2C_CLR_RX_UNDER_OFFSET        0x44
+ #define    I2C_CLR_RX_OVER_OFFSET         0x48
+ #define    I2C_CLR_TX_OVER_OFFSET         0x4c
+ #define    I2C_CLR_RD_REQ_OFFSET          0x50
+ #define    I2C_CLR_TX_ABRT_OFFSET         0x54
+ #define    I2C_CLR_RX_DONE_OFFSET         0x58
+ #define    I2C_CLR_ACTIVITY_OFFSET        0x5c
+ #define    I2C_CLR_STOP_DET_OFFSET        0x60
+ #define    I2C_CLR_START_DET_OFFSET       0x64
+ #define    I2C_CLR_GEN_CALL_OFFSET        0x68
+ #define    I2C_ENABLE_OFFSET              0x6c
+ #define    I2C_STATUS_OFFSET              0x70
+ #define    I2C_TXFLR_OFFSET               0x74
+ #define    I2C_RXFLR_OFFSET               0x78
+ #define    I2C_SDA_HOLD                   0x7c
+ #define    I2C_TX_ABRT_SOURCE_OFFSET      0x80
+ #define    I2C_SLV_DATA_ONLY_OFFSET       0x84
+ #define    I2C_DMA_CR_OFFSET              0x88
+ #define    I2C_DMA_TDLR_OFFSET            0x8c
+ #define    I2C_DMA_RDLR_OFFSET            0x90
+ #define    I2C_SDA_SETUP_OFFSET           0x94
+ #define    I2C_ACK_GENERAL_CALL_OFFSET    0x98
+ #define    I2C_ENABLE_STATUS_OFFSET       0x9c
+
+
+ typedef union tagI2c0Con
+ {
+     struct
+     {
+        UINT32      master                : 1   ;
+        UINT32      spedd                 : 2   ;
+        UINT32      slave_10bit           : 1   ;
+        UINT32      master_10bit          : 1   ;
+        UINT32      restart_en            : 1   ;
+        UINT32      slave_disable         : 1   ;
+        UINT32      Reserved_0            : 25  ;
+     } bits;
+     UINT32     Val32;
+ } I2C0_CON_U;
+
+
+ typedef union tagI2c0Tar
+ {
+     struct
+     {
+         UINT32      ic_tar                : 10  ;
+         UINT32      gc_or_start           : 1   ;
+         UINT32      special               : 1   ;
+         UINT32      ic_10bitaddr_master   : 1   ;
+         UINT32      Reserved_1            : 19  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_TAR_U;
+
+
+ typedef union tagI2c0DataCmd
+ {
+     struct
+     {
+         UINT32      dat                   : 8   ;
+         UINT32      cmd                   : 1   ;
+         UINT32      Reserved_5            : 23  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_DATA_CMD_U;
+
+
+ typedef union tagI2c0SsSclHcnt
+ {
+     struct
+     {
+         UINT32      ic_ss_scl_hcnt        : 16  ;
+         UINT32      Reserved_7            : 16  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_SS_SCL_HCNT_U;
+
+
+ typedef union tagI2c0SsSclLcnt
+ {
+     struct
+     {
+         UINT32      ic_ss_scl_lcnt        : 16  ;
+         UINT32      Reserved_9            : 16  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_SS_SCL_LCNT_U;
+
+
+ typedef union tagI2c0FsSclHcnt
+ {
+     struct
+     {
+         UINT32      ic_fs_scl_hcnt        : 16  ;
+         UINT32      Reserved_11           : 16  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_FS_SCL_HCNT_U;
+
+
+ typedef union tagI2c0FsSclLcnt
+ {
+     struct
+     {
+         UINT32      ic_fs_scl_lcnt        : 16  ;
+         UINT32      Reserved_13           : 16  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_FS_SCL_LCNT_U;
+
+
+ typedef union tagI2c0IntrMask
+ {
+     struct
+     {
+         UINT32      m_rx_under            : 1   ;
+         UINT32      m_rx_over             : 1   ;
+         UINT32      m_rx_full             : 1   ;
+         UINT32      m_tx_over             : 1   ;
+         UINT32      m_tx_empty            : 1   ;
+         UINT32      m_rd_req              : 1   ;
+         UINT32      m_tx_abrt             : 1   ;
+         UINT32      m_rx_done             : 1   ;
+         UINT32      m_activity            : 1   ;
+         UINT32      m_stop_det            : 1   ;
+         UINT32      m_start_det           : 1   ;
+         UINT32      m_gen_call            : 1   ;
+         UINT32      Reserved_17           : 20  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_INTR_MASK_U;
+
+
+ typedef union tagI2c0RxTl
+ {
+     struct
+     {
+         UINT32      rx_tl                 : 8   ;
+         UINT32      Reserved_21           : 24  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_RX_TL_U;
+
+
+ typedef union tagI2c0TxTl
+ {
+     struct
+     {
+         UINT32      tx_tl                 : 8   ;
+         UINT32      Reserved_23           : 24  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_TX_TL_U;
+
+
+ typedef union tagI2c0Enable
+ {
+     struct
+     {
+         UINT32      enable                : 1   ;
+         UINT32      Reserved_47           : 31  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_ENABLE_U;
+
+
+ typedef union tagI2c0Status
+ {
+     struct
+     {
+         UINT32      activity              : 1   ;
+         UINT32      tfnf                  : 1   ;
+         UINT32      tfe                   : 1   ;
+         UINT32      rfne                  : 1   ;
+         UINT32      rff                   : 1   ;
+         UINT32      mst_activity          : 1   ;
+         UINT32      slv_activity          : 1   ;
+         UINT32      Reserved_49           : 25  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_STATUS_U;
+
+
+ typedef union tagI2c0Txflr
+ {
+     struct
+     {
+         UINT32      txflr                 : 4   ;
+         UINT32      Reserved_51           : 28  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_TXFLR_U;
+
+
+ typedef union tagI2c0Rxflr
+ {
+     struct
+     {
+         UINT32      rxflr                 : 4   ;
+         UINT32      Reserved_53           : 28  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_RXFLR_U;
+
+
+ typedef union tagI2c0EnableStatus
+ {
+     struct
+     {
+         UINT32      ic_en                 : 1   ;
+         UINT32      slv_disable_while_busy: 1   ;
+         UINT32      slv_rx_data_lost      : 1   ;
+         UINT32      Reserved_69           : 29  ;
+     } bits;
+     UINT32      Val32;
+ } I2C0_ENABLE_STATUS_U;
+
+
+#endif
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLib.c b/Chips/Hisilicon/Library/I2CLib/I2CLib.c
new file mode 100644
index 0000000..b5b388d
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLib.c
@@ -0,0 +1,655 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/I2CLib.h>
+#include <Library/TimerLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+
+#include "I2CLibInternal.h"
+#include "I2CHw.h"
+
+VOID I2C_Delay(UINT32 ulCount)
+{
+    MicroSecondDelay(ulCount);
+    return;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2C_Disable(UINT32 Socket,UINT8 Port)
+{
+    UINT32                  ulTimeCnt = I2C_READ_TIMEOUT;
+    I2C0_STATUS_U           I2cStatusReg;
+    I2C0_ENABLE_U           I2cEnableReg;
+    I2C0_ENABLE_STATUS_U    I2cEnableStatusReg;
+
+    UINTN Base = GetI2cBase(Socket, Port);
+
+    I2C_REG_READ((Base + I2C_STATUS_OFFSET), I2cStatusReg.Val32);
+
+    while (I2cStatusReg.bits.activity)
+    {
+        I2C_Delay(10000);
+
+        ulTimeCnt--;
+        I2C_REG_READ(Base + I2C_STATUS_OFFSET, I2cStatusReg.Val32);
+        if (0 == ulTimeCnt)
+        {
+            return EFI_DEVICE_ERROR;
+        }
+    }
+
+
+    I2C_REG_READ(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+    I2cEnableReg.bits.enable = 0;
+    I2C_REG_WRITE(Base + I2C_ENABLE_OFFSET,I2cEnableReg.Val32);
+
+    I2C_REG_READ(Base + I2C_ENABLE_OFFSET,I2cEnableStatusReg.Val32);
+    if (0 == I2cEnableStatusReg.bits.ic_en)
+    {
+        return EFI_SUCCESS;
+    }
+    else
+    {
+        return EFI_DEVICE_ERROR;
+    }
+}
+
+
+EFI_STATUS
+EFIAPI
+I2C_Enable(UINT32 Socket,UINT8 Port)
+{
+    I2C0_ENABLE_U           I2cEnableReg;
+    I2C0_ENABLE_STATUS_U    I2cEnableStatusReg;
+
+    UINTN Base = GetI2cBase(Socket, Port);
+
+
+    I2C_REG_READ(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+    I2cEnableReg.bits.enable = 1;
+    I2C_REG_WRITE(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+
+
+    I2C_REG_READ(Base + I2C_ENABLE_STATUS_OFFSET, I2cEnableStatusReg.Val32);
+    if (1 == I2cEnableStatusReg.bits.ic_en)
+    {
+        return EFI_SUCCESS;
+    }
+    else
+    {
+        return EFI_DEVICE_ERROR;
+    }
+}
+
+void I2C_SetTarget(UINT32 Socket,UINT8 Port,UINT32 I2cDeviceAddr)
+{
+    I2C0_TAR_U    I2cTargetReg;
+    UINTN Base = GetI2cBase(Socket, Port);
+
+
+    I2C_REG_READ(Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
+    I2cTargetReg.bits.ic_tar = I2cDeviceAddr;
+    I2C_REG_WRITE(Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
+
+    return;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2CInit(UINT32 Socket, UINT32 Port, SPEED_MODE SpeedMode)
+{
+    I2C0_CON_U              I2cControlReg;
+    I2C0_SS_SCL_HCNT_U      I2cStandardSpeedSclHighCount;
+    I2C0_SS_SCL_LCNT_U      I2cStandardSpeedSclLowCount;
+    I2C0_RX_TL_U            I2cRxFifoReg;
+    I2C0_TX_TL_U            I2cTxFifoReg;
+    I2C0_INTR_MASK_U        I2cIntrMask;
+    EFI_STATUS              Status;
+
+    UINTN Base = GetI2cBase(Socket, Port);
+
+    if((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX) || (SpeedMode >= SPEED_MODE_MAX)){
+        return EFI_INVALID_PARAMETER;
+    }
+
+
+    Status = I2C_Disable(Socket,Port);
+    if(EFI_ERROR(Status))
+    {
+        return EFI_DEVICE_ERROR;
+    }
+
+
+    I2C_REG_READ(Base + I2C_CON_OFFSET, I2cControlReg.Val32);
+    I2cControlReg.bits.master = 1;
+    I2cControlReg.bits.spedd = 0x1;
+    I2cControlReg.bits.restart_en = 1;
+    I2cControlReg.bits.slave_disable = 1;
+    I2C_REG_WRITE(Base + I2C_CON_OFFSET,I2cControlReg.Val32);
+
+
+    if(Normal == SpeedMode)
+    {
+        I2C_REG_READ(Base + I2C_SS_SCL_HCNT_OFFSET,I2cStandardSpeedSclHighCount.Val32);
+        I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
+        I2C_REG_WRITE(Base + I2C_SS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
+        I2C_REG_READ(Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+        I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
+        I2C_REG_WRITE(Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+    }
+    else
+    {
+        I2C_REG_READ(Base + I2C_FS_SCL_HCNT_OFFSET,I2cStandardSpeedSclHighCount.Val32);
+        I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
+        I2C_REG_WRITE(Base + I2C_FS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
+        I2C_REG_READ(Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+        I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
+        I2C_REG_WRITE(Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+    }
+
+
+    I2C_REG_READ(Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
+    I2cRxFifoReg.bits.rx_tl = I2C_TXRX_THRESHOLD;
+    I2C_REG_WRITE(Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
+    I2C_REG_READ(Base + I2C_TX_TL_OFFSET,I2cTxFifoReg.Val32);
+    I2cTxFifoReg.bits.tx_tl = I2C_TXRX_THRESHOLD;
+    I2C_REG_WRITE(Base + I2C_TX_TL_OFFSET, I2cTxFifoReg.Val32);
+
+
+    I2C_REG_READ(Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
+    I2cIntrMask.Val32 = 0x0;
+    I2C_REG_WRITE(Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
+
+
+    Status = I2C_Enable(Socket,Port);
+    if(EFI_ERROR(Status))
+    {
+        return EFI_DEVICE_ERROR;
+    }
+
+    return I2cLibRuntimeSetup (Socket, Port);
+}
+
+EFI_STATUS
+EFIAPI
+I2CSdaConfig(UINT32 Socket, UINT32 Port)
+{
+
+    UINTN Base = GetI2cBase(Socket, Port);
+
+    if((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX)){
+        return EFI_INVALID_PARAMETER;
+    }
+
+    I2C_REG_WRITE(Base + I2C_SDA_HOLD, 0x14);
+
+    return EFI_SUCCESS;
+}
+
+
+
+UINT32 I2C_GetTxStatus(UINT32 Socket,UINT8 Port)
+{
+    I2C0_TXFLR_U ulFifo;
+    UINTN Base = GetI2cBase(Socket, Port);
+
+    I2C_REG_READ(Base + I2C_TXFLR_OFFSET, ulFifo.Val32);
+    return ulFifo.bits.txflr;
+}
+
+UINT32
+I2C_GetRxStatus(UINT32 Socket,UINT8 Port)
+{
+    I2C0_RXFLR_U ulFifo;
+    UINTN Base = GetI2cBase(Socket, Port);
+
+    I2C_REG_READ(Base + I2C_RXFLR_OFFSET, ulFifo.Val32);
+    return ulFifo.bits.rxflr;
+}
+
+EFI_STATUS
+EFIAPI
+WriteBeforeRead(I2C_DEVICE *I2cInfo, UINT32 ulLength, UINT8 *pBuf)
+{
+    UINT32 ulFifo;
+    UINT32 ulCnt;
+    UINT32 ulTimes = 0;
+
+    UINTN  Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+
+    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    while(0 != ulFifo)
+    {
+        I2C_Delay(2);
+        if(++ulTimes > I2C_READ_TIMEOUT)
+        {
+            return EFI_TIMEOUT;
+        }
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+
+    for(ulCnt = 0; ulCnt < ulLength; ulCnt++)
+    {
+        ulTimes = 0;
+        while(ulFifo > I2C_TXRX_THRESHOLD)
+        {
+            I2C_Delay(2);
+            if(++ulTimes > I2C_READ_TIMEOUT)
+            {
+                return EFI_TIMEOUT;
+            }
+            ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+        }
+
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+
+    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    ulTimes = 0;
+    while(0 != ulFifo)
+    {
+        I2C_Delay(2);
+
+        if(++ulTimes > I2C_READ_TIMEOUT)
+        {
+            return EFI_TIMEOUT;
+        }
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf)
+{
+    UINT32 ulFifo;
+    UINT32 ulTimes = 0;
+    UINT32  Idx;
+    UINTN  Base;
+
+
+    if(I2cInfo->Port >= I2C_PORT_MAX)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+    (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+
+    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    while(0 != ulFifo)
+    {
+        I2C_Delay(2);
+        if(++ulTimes > I2C_READ_TIMEOUT)
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_TIMEOUT;
+        }
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+
+
+    if(I2cInfo->DeviceType)
+    {
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+    }
+    else
+    {
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+    }
+
+    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    ulTimes = 0;
+    while(0 != ulFifo)
+    {
+        I2C_Delay(2);
+        if(++ulTimes > I2C_READ_TIMEOUT)
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_TIMEOUT;
+        }
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+
+    for(Idx = 0; Idx < ulLength; Idx++)
+    {
+        ulTimes = 0;
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+        while(ulFifo > I2C_TXRX_THRESHOLD)
+        {
+            I2C_Delay(2);
+            if(++ulTimes > I2C_READ_TIMEOUT)
+            {
+                (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+                return EFI_TIMEOUT;
+            }
+            ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+        }
+
+        if (Idx < ulLength - 1) {
+            I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++));
+        } else {
+            //Send command stop bit for the last transfer
+            I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++) | I2C_CMD_STOP_BIT);
+        }
+    }
+
+    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    ulTimes = 0;
+    while(0 != ulFifo)
+    {
+        I2C_Delay(2);
+
+        if(++ulTimes > I2C_READ_TIMEOUT)
+        {
+            DEBUG ((EFI_D_ERROR, "I2C Write try to finished,time out!\n"));
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_TIMEOUT;
+        }
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+    (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf)
+{
+    UINT32 ulFifo;
+    UINT32 ulTimes = 0;
+    UINT8  I2CWAddr[2];
+    EFI_STATUS  Status;
+    UINT32  Idx = 0;
+    UINTN Base;
+
+
+    if(I2cInfo->Port >= I2C_PORT_MAX)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+    Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+    if(I2cInfo->DeviceType)
+    {
+        I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
+        I2CWAddr[1] = (InfoOffset & 0xff);
+        Status = WriteBeforeRead(I2cInfo, 2,I2CWAddr);
+        if(EFI_ERROR(Status))
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_ABORTED;
+        }
+    }
+    else
+    {
+        I2CWAddr[0] = (InfoOffset & 0xff);
+        Status = WriteBeforeRead(I2cInfo, 1,I2CWAddr);
+        if(EFI_ERROR(Status))
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_ABORTED;
+        }
+    }
+
+    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    while(0 != ulFifo)
+    {
+        I2C_Delay(2);
+
+        while(++ulTimes > I2C_READ_TIMEOUT)
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_TIMEOUT;
+        }
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+
+    while (ulRxLen > 0) {
+        if (ulRxLen > 1) {
+            I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+        } else {
+            //Send command stop bit for the last transfer
+            I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL | I2C_CMD_STOP_BIT);
+        }
+
+        ulTimes = 0;
+        do {
+            I2C_Delay(2);
+
+            while(++ulTimes > I2C_READ_TIMEOUT) {
+                (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+                return EFI_TIMEOUT;
+            }
+            ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+        }while(0 == ulFifo);
+
+        I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+
+        ulRxLen --;
+    }
+    (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CReadMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf)
+{
+    UINT32 ulCnt;
+    UINT16 usTotalLen = 0;
+    UINT32 ulFifo;
+    UINT32 ulTimes = 0;
+    UINT8  I2CWAddr[4];
+    EFI_STATUS  Status;
+    UINT32  BytesLeft;
+    UINT32  Idx = 0;
+    UINTN Base;
+
+
+    if(I2cInfo->Port >= I2C_PORT_MAX)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+    Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+    if(I2cInfo->DeviceType == DEVICE_TYPE_E2PROM)
+    {
+        I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
+        I2CWAddr[1] = (InfoOffset & 0xff);
+        Status = WriteBeforeRead(I2cInfo, 2,I2CWAddr);
+        if(EFI_ERROR(Status))
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_ABORTED;
+        }
+    }
+
+    else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS)
+    {
+        I2CWAddr[0] = (InfoOffset >> 16) & 0xff;
+        I2CWAddr[1] = (InfoOffset >> 8) & 0xff;
+        I2CWAddr[2] = (InfoOffset & 0xff);
+        Status = WriteBeforeRead(I2cInfo, 3,I2CWAddr);
+        if(EFI_ERROR(Status))
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_ABORTED;
+        }
+    }
+
+    else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS)
+    {
+        I2CWAddr[0] = (InfoOffset >> 24) & 0xff;
+        I2CWAddr[1] = (InfoOffset >> 16) & 0xff;
+        I2CWAddr[2] = (InfoOffset >> 8) & 0xff;
+        I2CWAddr[3] = (InfoOffset & 0xff);
+        Status = WriteBeforeRead(I2cInfo, 4,I2CWAddr);
+        if(EFI_ERROR(Status))
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_ABORTED;
+        }
+    }
+
+    else
+    {
+        I2CWAddr[0] = (InfoOffset & 0xff);
+        Status = WriteBeforeRead(I2cInfo, 1,I2CWAddr);
+        if(EFI_ERROR(Status))
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_ABORTED;
+        }
+    }
+
+
+    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+    usTotalLen = ulRxLen;
+    BytesLeft = usTotalLen;
+
+    for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+    }
+
+
+    for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+        ulTimes = 0;
+        do {
+            I2C_Delay(2);
+
+            while(++ulTimes > I2C_READ_TIMEOUT) {
+                (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+                return EFI_TIMEOUT;
+            }
+            ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+        }while(0 == ulFifo);
+
+        I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+    }
+    (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+I2CWriteMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset, UINT32 ulLength, UINT8 *pBuf)
+{
+    UINT32 ulFifo;
+    UINT32 ulTimes = 0;
+    UINT32  Idx;
+    UINTN  Base;
+
+
+    if(I2cInfo->Port >= I2C_PORT_MAX)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+
+    (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+
+    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+
+    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    while(0 != ulFifo)
+    {
+        I2C_Delay(2);
+        if(++ulTimes > I2C_READ_TIMEOUT)
+        {
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_TIMEOUT;
+        }
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+
+
+    if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS)
+    {
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+    }
+
+    else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS)
+    {
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 24) & 0xff);
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+    }
+
+    else
+    {
+
+    }
+
+    ulTimes = 0;
+    for(Idx = 0; Idx < ulLength; Idx++)
+    {
+
+       I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+
+    }
+
+    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    ulTimes = 0;
+    while(0 != ulFifo)
+    {
+        I2C_Delay(2);
+
+        if(++ulTimes > I2C_READ_TIMEOUT)
+        {
+            DEBUG ((EFI_D_ERROR, "I2C Write try to finished,time out!\n"));
+            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+            return EFI_TIMEOUT;
+        }
+        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+    }
+    (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+
+    return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLib.inf b/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
new file mode 100644
index 0000000..b5cbfc3
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
@@ -0,0 +1,49 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = I2CLib
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = I2CLib
+
+[Sources.common]
+  I2CLib.c
+  I2CLibCommon.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  BaseLib
+  ArmLib
+  TimerLib
+
+  PlatformSysCtrlLib
+
+[BuildOptions]
+
+[Pcd]
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLibCommon.c b/Chips/Hisilicon/Library/I2CLib/I2CLibCommon.c
new file mode 100644
index 0000000..499c2d7
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLibCommon.c
@@ -0,0 +1,35 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include "I2CLibInternal.h"
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port)
+{
+  return PlatformGetI2cBase(Socket, Port);
+}
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port)
+{
+  return EFI_SUCCESS;
+}
+
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLibInternal.h b/Chips/Hisilicon/Library/I2CLib/I2CLibInternal.h
new file mode 100644
index 0000000..1429729
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLibInternal.h
@@ -0,0 +1,29 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _I2C_LIB_INTERNAL_H_
+#define _I2C_LIB_INTERNAL_H_
+
+#include <PlatformArch.h>
+#include <Library/I2CLib.h>
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port);
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port);
+
+
+#endif
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.c b/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.c
new file mode 100644
index 0000000..678b5a0
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.c
@@ -0,0 +1,109 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Guid/EventGroup.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include "I2CLibInternal.h"
+
+STATIC EFI_EVENT              mI2cLibVirtualAddrChangeEvent;
+
+STATIC UINTN gI2cBase[MAX_SOCKET][I2C_PORT_MAX];
+
+UINTN GetI2cBase (UINT32 Socket, UINT8 Port)
+{
+  if (gI2cBase[Socket][Port] == 0) {
+    gI2cBase[Socket][Port] = PlatformGetI2cBase(Socket, Port);
+  }
+
+  return gI2cBase[Socket][Port];
+}
+
+VOID
+EFIAPI
+I2cLibVirtualNotifyEvent (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  UINT32 Socket;
+  UINT8  Port;
+
+  // We assume that all I2C ports used in one runtime driver need to be
+  // converted into virtual address.
+  for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
+    for (Port = 0; Port < I2C_PORT_MAX; Port++) {
+      if (gI2cBase[Socket][Port] != 0) {
+        EfiConvertPointer (0x0, (VOID **)&gI2cBase[Socket][Port]);
+      }
+    }
+  }
+
+  return;
+}
+
+EFI_STATUS
+I2cLibRuntimeSetup (UINT32 Socket, UINT8 Port)
+{
+  EFI_STATUS Status;
+
+  UINTN Base = GetI2cBase (Socket, Port);
+
+  // Declare the controller as EFI_MEMORY_RUNTIME
+  Status = gDS->AddMemorySpace (
+      EfiGcdMemoryTypeMemoryMappedIo,
+      Base, SIZE_64KB,
+      EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+      );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_WARN, "[%a:%d] AddMemorySpace failed: %r\n", __FUNCTION__, __LINE__, Status));
+  }
+
+  Status = gDS->SetMemorySpaceAttributes (Base, SIZE_64KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "[%a:%d] SetMemorySpaceAttributes failed: %r\n", __FUNCTION__, __LINE__, Status));
+    return Status;
+  }
+
+  //
+  // Register for the virtual address change event
+  //
+  // Only create event once
+  if (mI2cLibVirtualAddrChangeEvent == NULL) {
+    Status = gBS->CreateEventEx (
+        EVT_NOTIFY_SIGNAL,
+        TPL_NOTIFY,
+        I2cLibVirtualNotifyEvent,
+        NULL,
+        &gEfiEventVirtualAddressChangeGuid,
+        &mI2cLibVirtualAddrChangeEvent
+    );
+    if (EFI_ERROR (Status)) {
+      DEBUG ((EFI_D_ERROR, "[%a:%d] Create event failed: %r\n", __FUNCTION__, __LINE__, Status));
+      return Status;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
new file mode 100644
index 0000000..24a232f
--- /dev/null
+++ b/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = I2CLibRuntime
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = I2CLib
+
+[Sources.common]
+  I2CLib.c
+  I2CLibRuntime.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  BaseLib
+  ArmLib
+  TimerLib
+  DxeServicesTableLib
+  UefiRuntimeLib
+
+  PlatformSysCtrlLib
+
+[BuildOptions]
+
+[Pcd]
+
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c
new file mode 100644
index 0000000..efefeb6
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c
@@ -0,0 +1,526 @@
+/** @file
+  Implementation for PlatformBdsLib library class interfaces.
+
+  Copyright (C) 2015, Red Hat, Inc.
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+  Copyright (c) 2015, Linaro Limited. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmVirtPkg/Library/PlatformIntelBdsLib/
+
+**/
+
+#include <IndustryStandard/Pci22.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformBdsLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#include "IntelBdsPlatform.h"
+
+
+//3CEF354A-3B7A-4519-AD70-72A134698311
+GUID gEblFileGuid = {0x3CEF354A, 0x3B7A, 0x4519, {0xAD, 0x70,
+  0x72, 0xA1, 0x34, 0x69, 0x83, 0x11} };
+
+// Need to keep the same with FlashStartOs.inf
+// 282cae50-940e-11e5-b7b8-774201c0f2d8
+GUID gFlashStartOsAppGuid = { 0x282cae50, 0x940e, 0x11e5, {0xb7, 0xb8,
+  0x77, 0x42, 0x01, 0xc0, 0xf2, 0xd8} };
+
+// Need to keep the same with EslStartOs.inf
+// 8880a72c-9411-11e5-b6f0-97310bc151d1
+GUID gEslStartOsAppGuid = { 0x8880a72c, 0x9411, 0x11e5, {0xb6, 0xf0,
+  0x97, 0x31, 0x0b, 0xc1, 0x51, 0xd1} };
+
+EFI_STATUS
+BdsDeleteAllInvalidEfiBootOption (
+  VOID
+  );
+
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
+
+
+#pragma pack (1)
+typedef struct {
+  VENDOR_DEVICE_PATH         SerialDxe;
+  UART_DEVICE_PATH           Uart;
+  VENDOR_DEFINED_DEVICE_PATH Vt100;
+  EFI_DEVICE_PATH_PROTOCOL   End;
+} PLATFORM_SERIAL_CONSOLE;
+#pragma pack ()
+
+#define SERIAL_DXE_FILE_GUID { \
+          0xD3987D4B, 0x971A, 0x435F, \
+          { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \
+          }
+
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+  //
+  // VENDOR_DEVICE_PATH SerialDxe
+  //
+  {
+    { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
+    SERIAL_DXE_FILE_GUID
+  },
+
+  //
+  // UART_DEVICE_PATH Uart
+  //
+  {
+    { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+    0,                                      // Reserved
+    FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+    FixedPcdGet8 (PcdUartDefaultDataBits),  // DataBits
+    FixedPcdGet8 (PcdUartDefaultParity),    // Parity
+    FixedPcdGet8 (PcdUartDefaultStopBits)   // StopBits
+  },
+
+  //
+  // VENDOR_DEFINED_DEVICE_PATH Vt100
+  //
+  {
+    {
+      MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
+      DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
+    },
+    EFI_VT_100_GUID
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+    END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
+
+#pragma pack (1)
+typedef struct {
+  USB_CLASS_DEVICE_PATH    Keyboard;
+  EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_USB_KEYBOARD;
+#pragma pack ()
+
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+  //
+  // USB_CLASS_DEVICE_PATH Keyboard
+  //
+  {
+    {
+      MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,
+      DP_NODE_LEN (USB_CLASS_DEVICE_PATH)
+    },
+    0xFFFF, // VendorId: any
+    0xFFFF, // ProductId: any
+    3,      // DeviceClass: HID
+    1,      // DeviceSubClass: boot
+    1       // DeviceProtocol: keyboard
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+    END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
+
+//
+// BDS Platform Functions
+//
+/**
+  Platform Bds init. Include the platform firmware vendor, revision
+  and so crc check.
+
+**/
+VOID
+EFIAPI
+PlatformBdsInit (
+  VOID
+  )
+{
+  //Signal EndofDxe Event
+  EfiEventGroupSignal(&gEfiEndOfDxeEventGroupGuid);
+}
+
+
+/**
+  Check if the handle satisfies a particular condition.
+
+  @param[in] Handle      The handle to check.
+  @param[in] ReportText  A caller-allocated string passed in for reporting
+                         purposes. It must never be NULL.
+
+  @retval TRUE   The condition is satisfied.
+  @retval FALSE  Otherwise. This includes the case when the condition could not
+                 be fully evaluated due to an error.
+**/
+typedef
+BOOLEAN
+(EFIAPI *FILTER_FUNCTION) (
+  IN EFI_HANDLE   Handle,
+  IN CONST CHAR16 *ReportText
+  );
+
+
+/**
+  Process a handle.
+
+  @param[in] Handle      The handle to process.
+  @param[in] ReportText  A caller-allocated string passed in for reporting
+                         purposes. It must never be NULL.
+**/
+typedef
+VOID
+(EFIAPI *CALLBACK_FUNCTION)  (
+  IN EFI_HANDLE   Handle,
+  IN CONST CHAR16 *ReportText
+  );
+
+/**
+  Locate all handles that carry the specified protocol, filter them with a
+  callback function, and pass each handle that passes the filter to another
+  callback.
+
+  @param[in] ProtocolGuid  The protocol to look for.
+
+  @param[in] Filter        The filter function to pass each handle to. If this
+                           parameter is NULL, then all handles are processed.
+
+  @param[in] Process       The callback function to pass each handle to that
+                           clears the filter.
+**/
+STATIC
+VOID
+FilterAndProcess (
+  IN EFI_GUID          *ProtocolGuid,
+  IN FILTER_FUNCTION   Filter         OPTIONAL,
+  IN CALLBACK_FUNCTION Process
+  )
+{
+  EFI_STATUS Status;
+  EFI_HANDLE *Handles;
+  UINTN      NoHandles;
+  UINTN      Idx;
+
+  Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
+                  NULL /* SearchKey */, &NoHandles, &Handles);
+  if (EFI_ERROR (Status)) {
+    //
+    // This is not an error, just an informative condition.
+    //
+    DEBUG ((EFI_D_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
+      Status));
+    return;
+  }
+
+  ASSERT (NoHandles > 0);
+  for (Idx = 0; Idx < NoHandles; ++Idx) {
+    CHAR16        *DevicePathText;
+    STATIC CHAR16 Fallback[] = L"<device path unavailable>";
+
+    //
+    // The ConvertDevicePathToText() function handles NULL input transparently.
+    //
+    DevicePathText = ConvertDevicePathToText (
+                       DevicePathFromHandle (Handles[Idx]),
+                       FALSE, // DisplayOnly
+                       FALSE  // AllowShortcuts
+                       );
+    if (DevicePathText == NULL) {
+      DevicePathText = Fallback;
+    }
+
+    if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {
+      Process (Handles[Idx], DevicePathText);
+    }
+
+    if (DevicePathText != Fallback) {
+      FreePool (DevicePathText);
+    }
+  }
+  gBS->FreePool (Handles);
+}
+
+
+/**
+  This FILTER_FUNCTION checks if a handle corresponds to a PCI display device.
+**/
+STATIC
+BOOLEAN
+EFIAPI
+IsPciDisplay (
+  IN EFI_HANDLE   Handle,
+  IN CONST CHAR16 *ReportText
+  )
+{
+  EFI_STATUS          Status;
+  EFI_PCI_IO_PROTOCOL *PciIo;
+  PCI_TYPE00          Pci;
+
+  Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid,
+                  (VOID**)&PciIo);
+  if (EFI_ERROR (Status)) {
+    //
+    // This is not an error worth reporting.
+    //
+    return FALSE;
+  }
+
+  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */,
+                        sizeof Pci / sizeof (UINT32), &Pci);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status));
+    return FALSE;
+  }
+
+  return IS_PCI_DISPLAY (&Pci);
+}
+
+
+/**
+  This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking
+  the matching driver to produce all first-level child handles.
+**/
+STATIC
+VOID
+EFIAPI
+Connect (
+  IN EFI_HANDLE   Handle,
+  IN CONST CHAR16 *ReportText
+  )
+{
+  EFI_STATUS Status;
+
+  Status = gBS->ConnectController (
+                  Handle, // ControllerHandle
+                  NULL,   // DriverImageHandle
+                  NULL,   // RemainingDevicePath -- produce all children
+                  FALSE   // Recursive
+                  );
+  DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE, "%a: %s: %r\n",
+    __FUNCTION__, ReportText, Status));
+}
+
+
+/**
+  This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the
+  handle, and adds it to ConOut and ErrOut.
+**/
+STATIC
+VOID
+EFIAPI
+AddOutput (
+  IN EFI_HANDLE   Handle,
+  IN CONST CHAR16 *ReportText
+  )
+{
+  EFI_STATUS               Status;
+  EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+  DevicePath = DevicePathFromHandle (Handle);
+  if (DevicePath == NULL) {
+    DEBUG ((EFI_D_ERROR, "%a: %s: handle %p: device path not found\n",
+      __FUNCTION__, ReportText, Handle));
+    return;
+  }
+
+  Status = BdsLibUpdateConsoleVariable (L"ConOut", DevicePath, NULL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,
+      ReportText, Status));
+    return;
+  }
+
+  Status = BdsLibUpdateConsoleVariable (L"ErrOut", DevicePath, NULL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,
+      ReportText, Status));
+    return;
+  }
+
+  DEBUG ((EFI_D_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,
+    ReportText));
+}
+
+
+/**
+  The function will execute with as the platform policy, current policy
+  is driven by boot mode. IBV/OEM can customize this code for their specific
+  policy action.
+
+  @param  DriverOptionList        The header of the driver option link list
+  @param  BootOptionList          The header of the boot option link list
+  @param  ProcessCapsules         A pointer to ProcessCapsules()
+  @param  BaseMemoryTest          A pointer to BaseMemoryTest()
+
+**/
+VOID
+EFIAPI
+PlatformBdsPolicyBehavior (
+  IN LIST_ENTRY                      *DriverOptionList,
+  IN LIST_ENTRY                      *BootOptionList,
+  IN PROCESS_CAPSULES                ProcessCapsules,
+  IN BASEM_MEMORY_TEST               BaseMemoryTest
+  )
+{
+  EFI_STATUS Status;
+  //
+  // Locate the PCI root bridges and make the PCI bus driver connect each,
+  // non-recursively. This will produce a number of child handles with PciIo on
+  // them.
+  //
+  FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect);
+
+  //
+  // Find all display class PCI devices (using the handles from the previous
+  // step), and connect them non-recursively. This should produce a number of
+  // child handles with GOPs on them.
+  //
+  FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect);
+
+  //
+  // Now add the device path of all handles with GOP on them to ConOut and
+  // ErrOut.
+  //
+  FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput);
+
+  //
+  // Add the hardcoded short-form USB keyboard device path to ConIn.
+  //
+  BdsLibUpdateConsoleVariable (L"ConIn",
+    (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);
+
+  //
+  // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
+  //
+  BdsLibUpdateConsoleVariable (L"ConIn",
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+  BdsLibUpdateConsoleVariable (L"ConOut",
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+  BdsLibUpdateConsoleVariable (L"ErrOut",
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+
+  //
+  // Connect the consoles based on the above variables.
+  //
+  BdsLibConnectAllDefaultConsoles ();
+
+  //
+  // Show the splash screen.
+  //
+  EnableQuietBoot (PcdGetPtr (PcdLogoFile));
+
+  //
+  // Connect the rest of the devices.
+  //
+  BdsLibConnectAll ();
+
+  //
+  // Add memory test to convert memory above 4GB to be tested
+  //
+  Status = BaseMemoryTest (QUICK);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "[%a:%d] - Base memory test failed: %r\n", __FUNCTION__, __LINE__, Status));
+  }
+
+  //
+  // Process QEMU's -kernel command line option. Note that the kernel booted
+  // this way should receive ACPI tables, which is why we connect all devices
+  // first (see above) -- PCI enumeration blocks ACPI table installation, if
+  // there is a PCI host.
+  //
+  //TryRunningQemuKernel ();
+
+  BdsLibEnumerateAllBootOption (BootOptionList);
+
+  // Add Flash Start OS and ESL Start OS boot option
+  (VOID) HwBdsLibRegisterAppBootOption (BootOptionList, &gFlashStartOsAppGuid, L"Flash Start OS");
+  (VOID) HwBdsLibRegisterAppBootOption (BootOptionList, &gEslStartOsAppGuid, L"ESL Start OS");
+
+  // Add EBL as boot option
+  (VOID) HwBdsLibRegisterAppBootOption (BootOptionList, &gEblFileGuid, L"Embedded Boot Loader (EBL)");
+
+  // Remove EFI Misc Device Boot Options
+  BdsDeleteAllInvalidEfiBootOption ();
+
+  //SetBootOrderFromQemu (BootOptionList);
+  //
+  // The BootOrder variable may have changed, reload the in-memory list with
+  // it.
+  //
+  BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");
+
+  //PlatformBdsEnterFrontPage (GetFrontPageTimeoutFromQemu(), TRUE);
+  Print (L"Press Enter to boot OS immediately.\n");
+  Print (L"Press any other key in %d seconds to stop automatical booting...\n", PcdGet16(PcdPlatformBootTimeOut));
+  PlatformBdsEnterFrontPage (PcdGet16(PcdPlatformBootTimeOut), TRUE);
+}
+
+/**
+  Hook point after a boot attempt succeeds. We don't expect a boot option to
+  return, so the UEFI 2.0 specification defines that you will default to an
+  interactive mode and stop processing the BootOrder list in this case. This
+  is also a platform implementation and can be customized by IBV/OEM.
+
+  @param  Option                  Pointer to Boot Option that succeeded to boot.
+
+**/
+VOID
+EFIAPI
+PlatformBdsBootSuccess (
+  IN  BDS_COMMON_OPTION *Option
+  )
+{
+}
+
+/**
+  Hook point after a boot attempt fails.
+
+  @param  Option                  Pointer to Boot Option that failed to boot.
+  @param  Status                  Status returned from failed boot.
+  @param  ExitData                Exit data returned from failed boot.
+  @param  ExitDataSize            Exit data size returned from failed boot.
+
+**/
+VOID
+EFIAPI
+PlatformBdsBootFail (
+  IN  BDS_COMMON_OPTION  *Option,
+  IN  EFI_STATUS         Status,
+  IN  CHAR16             *ExitData,
+  IN  UINTN              ExitDataSize
+  )
+{
+}
+
+/**
+  This function locks platform flash that is not allowed to be updated during normal boot path.
+  The flash layout is platform specific.
+**/
+VOID
+EFIAPI
+PlatformBdsLockNonUpdatableFlash (
+  VOID
+  )
+{
+  return;
+}
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.h b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.h
new file mode 100644
index 0000000..4a91262
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.h
@@ -0,0 +1,61 @@
+/** @file
+  Head file for BDS Platform specific code
+
+  Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmVirtPkg/Library/PlatformIntelBdsLib/
+
+**/
+
+#ifndef _INTEL_BDS_PLATFORM_H_
+#define _INTEL_BDS_PLATFORM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+#include "IntelBdsPlatformCommon.h"
+
+VOID
+PlatformBdsEnterFrontPage (
+  IN UINT16                 TimeoutDefault,
+  IN BOOLEAN                ConnectAllHappened
+  );
+
+/**
+  Download the kernel, the initial ramdisk, and the kernel command line from
+  QEMU's fw_cfg. Construct a minimal SimpleFileSystem that contains the two
+  image files, and load and start the kernel from it.
+
+  The kernel will be instructed via its command line to load the initrd from
+  the same Simple FileSystem.
+
+  @retval EFI_NOT_FOUND         Kernel image was not found.
+  @retval EFI_OUT_OF_RESOURCES  Memory allocation failed.
+  @retval EFI_PROTOCOL_ERROR    Unterminated kernel command line.
+
+  @return                       Error codes from any of the underlying
+                                functions. On success, the function doesn't
+                                return.
+**/
+EFI_STATUS
+EFIAPI
+TryRunningQemuKernel (
+  VOID
+  );
+
+#endif // _INTEL_BDS_PLATFORM_H
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.c b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.c
new file mode 100644
index 0000000..9ea701d
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.c
@@ -0,0 +1,118 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "IntelBdsPlatform.h"
+#include <Library/UefiLib.h>
+#include <Library/GenericBdsLib.h>
+#include <Protocol/FirmwareVolume2.h>
+
+VOID
+EFIAPI
+BdsLibBuildOptionFromApp (
+  IN EFI_HANDLE                  Handle,
+  IN OUT LIST_ENTRY              *BdsBootOptionList,
+  IN GUID                        *FileGuid,
+  IN CHAR16                      *Description
+  )
+{
+  EFI_DEVICE_PATH_PROTOCOL          *DevicePath;
+  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH ShellNode;
+
+  DevicePath = DevicePathFromHandle (Handle);
+
+  //
+  // Build the shell device path
+  //
+  EfiInitializeFwVolDevicepathNode (&ShellNode, FileGuid);
+
+  DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *) &ShellNode);
+
+  //
+  // Create and register the shell boot option
+  //
+  BdsLibRegisterNewOption (BdsBootOptionList, DevicePath, Description, L"BootOrder");
+
+}
+EFI_STATUS
+EFIAPI
+HwBdsLibRegisterAppBootOption (
+  IN OUT LIST_ENTRY              *BdsBootOptionList,
+  IN GUID                        *FileGuid,
+  IN CHAR16                      *Description
+  )
+{
+  EFI_STATUS                    Status;
+  UINTN                         Index;
+  UINTN                         FvHandleCount;
+  EFI_HANDLE                    *FvHandleBuffer;
+  EFI_FV_FILETYPE               Type;
+  UINTN                         Size;
+  EFI_FV_FILE_ATTRIBUTES        Attributes;
+  UINT32                        AuthenticationStatus;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+  UINTN                         Count = 0;
+
+  //
+  // Check if we have on flash shell
+  //
+  gBS->LocateHandleBuffer (
+        ByProtocol,
+        &gEfiFirmwareVolume2ProtocolGuid,
+        NULL,
+        &FvHandleCount,
+        &FvHandleBuffer
+        );
+  for (Index = 0; Index < FvHandleCount; Index++) {
+    gBS->HandleProtocol (
+          FvHandleBuffer[Index],
+          &gEfiFirmwareVolume2ProtocolGuid,
+          (VOID **) &Fv
+          );
+
+    Status = Fv->ReadFile (
+                  Fv,
+                  FileGuid,
+                  NULL,
+                  &Size,
+                  &Type,
+                  &Attributes,
+                  &AuthenticationStatus
+                  );
+    if (EFI_ERROR (Status)) {
+      //
+      // Skip if no shell file in the FV
+      //
+      continue;
+    }
+    //
+    // Build the shell boot option
+    //
+    BdsLibBuildOptionFromApp (FvHandleBuffer[Index], BdsBootOptionList,
+        FileGuid, Description);
+
+    Count++;
+  }
+
+  if (FvHandleCount != 0) {
+    FreePool (FvHandleBuffer);
+  }
+
+  if (Count == 0) {
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.h b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.h
new file mode 100644
index 0000000..73b901a
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatformCommon.h
@@ -0,0 +1,27 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _HW_BDS_LIB_H_
+#define _HW_BDS_LIB_H_
+
+EFI_STATUS
+EFIAPI
+HwBdsLibRegisterAppBootOption (
+  IN OUT LIST_ENTRY              *BdsBootOptionList,
+  IN GUID                        *FileGuid,
+  IN CHAR16                      *Description
+  );
+
+#endif
diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
new file mode 100644
index 0000000..baceb57
--- /dev/null
+++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
@@ -0,0 +1,80 @@
+## @file
+#  Implementation for PlatformBdsLib library class interfaces.
+#
+#  Copyright (C) 2015, Red Hat, Inc.
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+#  IMPLIED.
+#
+#  Based on the files under ArmVirtPkg/Library/PlatformIntelBdsLib/
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformIntelBdsLib
+  FILE_GUID                      = 46DF84EB-F603-4D39-99D8-E1E86B50BCC2
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PlatformBdsLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = ARM AARCH64
+#
+
+[Sources]
+  IntelBdsPlatform.c
+  IntelBdsPlatformCommon.c
+
+[Packages]
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  DevicePathLib
+  GenericBdsLib
+  MemoryAllocationLib
+  PcdLib
+  PrintLib
+  UefiBootServicesTableLib
+  UefiRuntimeServicesTableLib
+  UefiLib
+
+[FixedPcd]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+
+[Guids]
+  gEfiEndOfDxeEventGroupGuid
+  gEfiFileInfoGuid
+  gEfiFileSystemInfoGuid
+  gEfiFileSystemVolumeLabelInfoIdGuid
+
+[Protocols]
+  gEfiDevicePathProtocolGuid
+  gEfiGraphicsOutputProtocolGuid
+  gEfiLoadedImageProtocolGuid
+  gEfiPciRootBridgeIoProtocolGuid
+  gEfiSimpleFileSystemProtocolGuid
diff --git a/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.c b/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.c
new file mode 100644
index 0000000..0139077
--- /dev/null
+++ b/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.c
@@ -0,0 +1,429 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/IoLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/EfiTimeBaseLib.h>
+
+#include <Protocol/RealTimeClock.h>
+
+#include <Guid/GlobalVariable.h>
+#include <Guid/EventGroup.h>
+
+#include <Library/ArmArchTimer.h>
+
+STATIC CONST CHAR16           mTimeZoneVariableName[] = L"PV660VirtualRtcTimeZone";
+STATIC CONST CHAR16           mDaylightVariableName[] = L"PV660VirtualRtcDaylight";
+STATIC EFI_EVENT              mRtcVirtualAddrChangeEvent;
+STATIC EFI_RUNTIME_SERVICES   *mRT;
+
+
+STATIC INTN mEpochDiff = 0;
+
+/**
+  Returns the current time and date information, and the time-keeping capabilities
+  of the hardware platform.
+
+  @param  Time                   A pointer to storage to receive a snapshot of the current time.
+  @param  Capabilities           An optional pointer to a buffer to receive the real time clock
+                                 device's capabilities.
+
+  @retval EFI_SUCCESS            The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER  Time is NULL.
+  @retval EFI_DEVICE_ERROR       The time could not be retrieved due to hardware error.
+  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT EFI_TIME                *Time,
+  OUT EFI_TIME_CAPABILITIES   *Capabilities
+  )
+{
+  EFI_STATUS  Status = EFI_SUCCESS;
+  UINT64      Temp;
+  UINT32      EpochSeconds;
+  INT16       TimeZone = 0;
+  UINT8       Daylight = 0;
+  UINTN       Size;
+
+  // Ensure Time is a valid pointer
+  if (Time == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  ArmArchTimerReadReg(CntPct,&Temp);
+
+  // UINT32 force convertion for PC-LINT
+  EpochSeconds = mEpochDiff + Temp / (UINT32) PcdGet32(PcdArmArchTimerFreqInHz);
+
+  // Get the current time zone information from non-volatile storage
+  Size = sizeof (TimeZone);
+  Status = mRT->GetVariable (
+                  (CHAR16 *)mTimeZoneVariableName,
+                  &gEfiCallerIdGuid,
+                  NULL,
+                  &Size,
+                  (VOID *)&TimeZone
+                  );
+
+  if (EFI_ERROR (Status)) {
+    ASSERT(Status != EFI_INVALID_PARAMETER);
+    ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+
+    if (Status != EFI_NOT_FOUND)
+      goto EXIT;
+
+    // The time zone variable does not exist in non-volatile storage, so create it.
+    Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+    // Store it
+    Status = mRT->SetVariable (
+                    (CHAR16 *)mTimeZoneVariableName,
+                    &gEfiCallerIdGuid,
+                    EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+                    Size,
+                    (VOID *)&(Time->TimeZone)
+                    );
+    if (EFI_ERROR (Status)) {
+      DEBUG ((
+        EFI_D_ERROR,
+        "LibGetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+        mTimeZoneVariableName,
+        Status
+        ));
+      goto EXIT;
+    }
+  } else {
+    // Got the time zone
+    Time->TimeZone = TimeZone;
+
+    // Check TimeZone bounds:   -1440 to 1440 or 2047
+    if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440))
+        && (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE)) {
+      Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+    }
+
+    // Adjust for the correct time zone
+    if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
+      EpochSeconds += Time->TimeZone * SEC_PER_MIN;
+    }
+  }
+
+  // Get the current daylight information from non-volatile storage
+  Size = sizeof (Daylight);
+  Status = mRT->GetVariable (
+                  (CHAR16 *)mDaylightVariableName,
+                  &gEfiCallerIdGuid,
+                  NULL,
+                  &Size,
+                  (VOID *)&Daylight
+                  );
+
+  if (EFI_ERROR (Status)) {
+    ASSERT(Status != EFI_INVALID_PARAMETER);
+    ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+
+    if (Status != EFI_NOT_FOUND)
+      goto EXIT;
+
+    // The daylight variable does not exist in non-volatile storage, so create it.
+    Time->Daylight = 0;
+    // Store it
+    Status = mRT->SetVariable (
+                    (CHAR16 *)mDaylightVariableName,
+                    &gEfiCallerIdGuid,
+                    EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+                    Size,
+                    (VOID *)&(Time->Daylight)
+                    );
+    if (EFI_ERROR (Status)) {
+      DEBUG ((
+        EFI_D_ERROR,
+        "LibGetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+        mDaylightVariableName,
+        Status
+        ));
+      goto EXIT;
+    }
+  } else {
+    // Got the daylight information
+    Time->Daylight = Daylight;
+
+    // Adjust for the correct period
+    if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
+      // Convert to adjusted time, i.e. spring forwards one hour
+      EpochSeconds += SEC_PER_HOUR;
+    }
+  }
+
+  // Convert from internal 32-bit time to UEFI time
+  EpochToEfiTime (EpochSeconds, Time);
+
+  // Update the Capabilities info
+  if (Capabilities != NULL) {
+    Capabilities->Resolution  = 1;
+    // Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000
+
+    Capabilities->Accuracy    = PcdGet32 (PcdArmArchTimerFreqInHz);
+    // FALSE: Setting the time does not clear the values below the resolution level
+    Capabilities->SetsToZero  = FALSE;
+  }
+
+  EXIT:
+  return Status;
+}
+
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time                  A pointer to the current time.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+  IN  EFI_TIME                *Time
+  )
+{
+  EFI_STATUS  Status;
+  UINTN       EpochSeconds;
+  UINTN       Temp;
+
+  // Check the input parameters are within the range specified by UEFI
+  if (!IsTimeValid (Time)) {
+    Status = EFI_INVALID_PARAMETER;
+    goto EXIT;
+  }
+
+  // Because the PL031 is a 32-bit counter counting seconds,
+  // the maximum time span is just over 136 years.
+  // Time is stored in Unix Epoch format, so it starts in 1970,
+  // Therefore it can not exceed the year 2106.
+  if ((Time->Year < 1970) || (Time->Year >= 2106)) {
+    Status = EFI_UNSUPPORTED;
+    goto EXIT;
+  }
+
+  EpochSeconds = EfiTimeToEpoch (Time);
+
+  // Adjust for the correct time zone, i.e. convert to UTC time zone
+  if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
+    EpochSeconds -= Time->TimeZone * SEC_PER_MIN;
+  }
+
+  // TODO: Automatic Daylight activation
+
+  // Adjust for the correct period
+  if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
+    // Convert to un-adjusted time, i.e. fall back one hour
+    EpochSeconds -= SEC_PER_HOUR;
+  }
+
+  ArmArchTimerReadReg(CntPct,&Temp);
+
+  // UINT32 force convertion for PC-LINT
+  mEpochDiff = EpochSeconds - Temp / (UINT32) PcdGet32(PcdArmArchTimerFreqInHz);
+
+  // The accesses to Variable Services can be very slow, because we may be writing to Flash.
+  // Do this after having set the RTC.
+
+  // Save the current time zone information into non-volatile storage
+  Status = mRT->SetVariable (
+                  (CHAR16 *)mTimeZoneVariableName,
+                  &gEfiCallerIdGuid,
+                  EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+                  sizeof (Time->TimeZone),
+                  (VOID *)&(Time->TimeZone)
+                  );
+  if (EFI_ERROR (Status)) {
+      DEBUG ((
+        EFI_D_ERROR,
+        "LibSetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+        mTimeZoneVariableName,
+        Status
+        ));
+    goto EXIT;
+  }
+
+  // Save the current daylight information into non-volatile storage
+  Status = mRT->SetVariable (
+                  (CHAR16 *)mDaylightVariableName,
+                  &gEfiCallerIdGuid,
+                  EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+                  sizeof(Time->Daylight),
+                  (VOID *)&(Time->Daylight)
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      EFI_D_ERROR,
+      "LibSetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+      mDaylightVariableName,
+      Status
+      ));
+    goto EXIT;
+  }
+
+  EXIT:
+  return Status;
+}
+
+
+/**
+  Returns the current wakeup alarm clock setting.
+
+  @param  Enabled               Indicates if the alarm is currently enabled or disabled.
+  @param  Pending               Indicates if the alarm signal is pending and requires acknowledgement.
+  @param  Time                  The current alarm setting.
+
+  @retval EFI_SUCCESS           The alarm settings were returned.
+  @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+  OUT BOOLEAN     *Enabled,
+  OUT BOOLEAN     *Pending,
+  OUT EFI_TIME    *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+
+/**
+  Sets the system wakeup alarm clock time.
+
+  @param  Enabled               Enable or disable the wakeup alarm.
+  @param  Time                  If Enable is TRUE, the time to set the wakeup alarm for.
+
+  @retval EFI_SUCCESS           If Enable is TRUE, then the wakeup alarm was enabled. If
+                                Enable is FALSE, then the wakeup alarm was disabled.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be set due to a hardware error.
+  @retval EFI_UNSUPPORTED       A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+  IN BOOLEAN      Enabled,
+  OUT EFI_TIME    *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Fixup internal data so that EFI can be call in virtual mode.
+  Call the passed in Child Notify event and convert any pointers in
+  lib to virtual mode.
+
+  @param[in]    Event   The Event that is being processed
+  @param[in]    Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  //
+  // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+  // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+  // to virtual address. After the OS transitions to calling in virtual mode, all future
+  // runtime calls will be made in virtual mode.
+  //
+  EfiConvertPointer (0x0, (VOID**)&mRT);
+  return;
+}
+
+/**
+  This is the declaration of an EFI image entry point. This can be the entry point to an application
+  written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+  @param  ImageHandle           Handle that identifies the loaded image.
+  @param  SystemTable           System Table for this image.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS    Status;
+  EFI_HANDLE    Handle;
+
+  // Setup the setters and getters
+  gRT->GetTime       = LibGetTime;
+  gRT->SetTime       = LibSetTime;
+  gRT->GetWakeupTime = LibGetWakeupTime;
+  gRT->SetWakeupTime = LibSetWakeupTime;
+
+  mRT = gRT;
+
+  // Install the protocol
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gEfiRealTimeClockArchProtocolGuid,  NULL,
+                  NULL
+                 );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Register for the virtual address change event
+  //
+  Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  LibRtcVirtualNotifyEvent,
+                  NULL,
+                  &gEfiEventVirtualAddressChangeGuid,
+                  &mRtcVirtualAddrChangeEvent
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.inf b/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.inf
new file mode 100644
index 0000000..84528bd
--- /dev/null
+++ b/Chips/Hisilicon/Library/VirtualRealTimeClockLib/RealTimeClockLib.inf
@@ -0,0 +1,47 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = RealTimeClockLibVirtual
+  FILE_GUID                      = 432B35C1-A0CC-4720-A4B9-1EFD70050107
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RealTimeClockLib
+
+[Sources.common]
+  RealTimeClockLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/OpenPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  UefiLib
+  DebugLib
+  PcdLib
+  DxeServicesTableLib
+  UefiRuntimeLib
+  ArmLib
+  EfiTimeBaseLib
+
+[Guids]
+  gEfiEventVirtualAddressChangeGuid
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
diff --git a/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c
new file mode 100644
index 0000000..49e330b
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c
@@ -0,0 +1,94 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerdesLib.h>
+
+#include "Smmu.h"
+
+SMMU_DEVICE mSpecialSmmu[] = {
+  {FixedPcdGet64 (PcdM3SmmuBaseAddress), 0},
+  {FixedPcdGet64 (PcdPcieSmmuBaseAddress), 0},
+};
+
+VOID
+SpecialSmmuConfig (VOID)
+{
+  UINTN Index;
+
+  for (Index = 0; Index < sizeof (mSpecialSmmu) / sizeof (mSpecialSmmu[0]); Index++) {
+    (VOID) SmmuConfigSwitch (&mSpecialSmmu[Index]);
+  }
+}
+
+VOID
+SpecialSmmuEnable (VOID)
+{
+  UINTN Index;
+
+  for (Index = 0; Index < sizeof (mSpecialSmmu) / sizeof (mSpecialSmmu[0]); Index++) {
+    (VOID) SmmuEnableTable (&mSpecialSmmu[Index]);
+  }
+}
+
+VOID
+EFIAPI
+ExitBootServicesEventSmmu (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+  SmmuConfigForOS ();
+  SpecialSmmuEnable ();
+  DEBUG((EFI_D_ERROR,"SMMU ExitBootServicesEvent\n"));
+}
+
+
+EFI_STATUS
+EFIAPI
+IoInitDxeEntry (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable)
+{
+  EFI_STATUS Status;
+  EFI_EVENT  Event = NULL;
+
+  (VOID) EfiSerdesInitWrap ();
+
+  SmmuConfigForBios ();
+
+  SpecialSmmuConfig ();
+
+  Status = gBS->CreateEvent (
+      EVT_SIGNAL_EXIT_BOOT_SERVICES,
+      TPL_CALLBACK,
+      ExitBootServicesEventSmmu,
+      NULL,
+      &Event
+      );
+
+  if (EFI_ERROR(Status))
+  {
+    DEBUG ((EFI_D_ERROR, "[%a:%d] - CreateEvent failed: %r\n", __FUNCTION__,
+        __LINE__, Status));
+  }
+
+  return Status;
+}
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf
new file mode 100644
index 0000000..a429cf3
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf
@@ -0,0 +1,58 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IoInitDxe
+  FILE_GUID                      = e99c606a-5626-11e5-b09e-bb93f4e4c400
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = IoInitDxeEntry
+
+[Sources.common]
+  IoInitDxe.c
+  Smmu.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+  BaseLib
+  PcdLib
+  CacheMaintenanceLib
+  SerdesLib
+  PlatformSysCtrlLib
+  MemoryAllocationLib
+
+[Guids]
+
+[Protocols]
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+[Depex]
+  TRUE
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c
new file mode 100644
index 0000000..5ccb7d1
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c
@@ -0,0 +1,442 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ArmLib.h>
+
+#include "Smmu.h"
+
+/* Maximum number of context banks per SMMU */
+#define SMMU_MAX_CBS    256
+
+#ifdef CONFIG_MM_OUTER_SHAREABLE
+#define SH_DOMAIN               2       /* outer shareable */
+#else
+#define SH_DOMAIN               3       /* inner shareable */
+#endif
+
+#define SMMU_OS_VMID    0
+#define SMMU_CB_NUMIRPT    8
+#define SMMU_S1CBT_SIZE    0x10000
+#define SMMU_S2CBT_SIZE    0x2000
+#define SMMU_S1CBT_SHIFT  16
+#define SMMU_S2CBT_SHIFT  12
+
+
+#define SMMU_CTRL_CR0      0x0
+#define SMMU_CTRL_ACR      0x8
+#define SMMU_CFG_S2CTBAR    0xc
+#define SMMU_IDR0      0x10
+#define SMMU_IDR1      0x14
+#define SMMU_IDR2      0x18
+#define SMMU_HIS_GFAR_LOW    0x20
+#define SMMU_HIS_GFAR_HIGH    0x24
+#define SMMU_RINT_GFSR      0x28
+#define SMMU_RINT_GFSYNR    0x2c
+#define SMMU_CFG_GFIM      0x30
+#define SMMU_CFG_CBF      0x34
+#define SMMU_TLBIALL      0x40
+#define SMMU_TLBIVMID      0x44
+#define SMMU_TLBISID      0x48
+#define SMMU_TLBIVA_LOW      0x4c
+#define SMMU_TLBIVA_HIGH    0x50
+#define SMMU_TLBGSYNC      0x54
+#define SMMU_TLBGSTATUS      0x58
+#define SMMU_CXTIALL      0x60
+#define SMMU_CXTIVMID      0x64
+#define SMMU_CXTISID      0x68
+#define SMMU_CXTGSYNC      0x6c
+#define SMMU_CXTGSTATUS      0x70
+#define SMMU_RINT_CB_FSR(n)    (0x100 + ((n) << 2))
+#define SMMU_RINT_CB_FSYNR(n)    (0x120 + ((n) << 2))
+#define SMMU_HIS_CB_FAR_LOW(n)    (0x140 + ((n) << 3))
+#define SMMU_HIS_CB_FAR_HIGH(n)    (0x144 + ((n) << 3))
+#define SMMU_CTRL_CB_RESUME(n)    (0x180 + ((n) << 2))
+#define SMMU_RINT_CB_FSYNR_MSTID  0x1a0
+
+#define SMMU_CB_S2CR(n)      (0x0  + ((n) << 5))
+#define SMMU_CB_CBAR(n)      (0x4  + ((n) << 5))
+#define SMMU_CB_S1CTBAR(n)    (0x18 + ((n) << 5))
+
+#define SMMU_S1_MAIR0      0x0
+#define SMMU_S1_MAIR1      0x4
+#define SMMU_S1_TTBR0_L      0x8
+#define SMMU_S1_TTBR0_H      0xc
+#define SMMU_S1_TTBR1_L      0x10
+#define SMMU_S1_TTBR1_H      0x14
+#define SMMU_S1_TTBCR      0x18
+#define SMMU_S1_SCTLR      0x1c
+
+#define CFG_CBF_S1_ORGN_WA    (1 << 12)
+#define CFG_CBF_S1_IRGN_WA    (1 << 10)
+#define CFG_CBF_S1_SHCFG    (SH_DOMAIN << 8)
+#define CFG_CBF_S2_ORGN_WA    (1 << 4)
+#define CFG_CBF_S2_IRGN_WA    (1 << 2)
+#define CFG_CBF_S2_SHCFG    (SH_DOMAIN << 0)
+
+/* Configuration registers */
+#define sCR0_CLIENTPD      (1 << 0)
+#define sCR0_GFRE      (1 << 1)
+#define sCR0_GFIE      (1 << 2)
+#define sCR0_GCFGFRE      (1 << 4)
+#define sCR0_GCFGFIE      (1 << 5)
+
+#define sACR_WC_EN      (7 << 0)
+
+#define ID0_S1TS      (1 << 30)
+#define ID0_S2TS      (1 << 29)
+#define ID0_NTS        (1 << 28)
+#define ID0_PTFS_SHIFT      24
+#define ID0_PTFS_MASK      0x2
+#define ID0_PTFS_V8_ONLY    0x2
+#define ID0_CTTW      (1 << 14)
+
+#define ID2_OAS_SHIFT      8
+#define ID2_OAS_MASK      0xff
+#define ID2_IAS_SHIFT      0
+#define ID2_IAS_MASK      0xff
+
+#define S2CR_TYPE_SHIFT      16
+#define S2CR_TYPE_MASK      0x3
+#define S2CR_TYPE_TRANS      (0 << S2CR_TYPE_SHIFT)
+#define S2CR_TYPE_BYPASS    (1 << S2CR_TYPE_SHIFT)
+#define S2CR_TYPE_FAULT      (2 << S2CR_TYPE_SHIFT)
+#define S2CR_SHCFG_NS      (3 << 8)
+#define S2CR_MTCFG      (1 << 11)
+#define S2CR_MEMATTR_OIWB    (0xf << 12)
+#define S2CR_MTSH_WEAKEST    (S2CR_SHCFG_NS | \
+        S2CR_MTCFG | S2CR_MEMATTR_OIWB)
+
+/* Context bank attribute registers */
+#define CBAR_VMID_SHIFT      0
+#define CBAR_VMID_MASK      0xff
+#define CBAR_S1_BPSHCFG_SHIFT    8
+#define CBAR_S1_BPSHCFG_MASK    3
+#define CBAR_S1_BPSHCFG_NSH    3
+#define CBAR_S1_MEMATTR_SHIFT    12
+#define CBAR_S1_MEMATTR_MASK    0xf
+#define CBAR_S1_MEMATTR_WB    0xf
+#define CBAR_TYPE_SHIFT      16
+#define CBAR_TYPE_MASK      0x3
+#define CBAR_TYPE_S2_TRANS    (0 << CBAR_TYPE_SHIFT)
+#define CBAR_TYPE_S1_TRANS_S2_BYPASS  (1 << CBAR_TYPE_SHIFT)
+#define CBAR_TYPE_S1_TRANS_S2_FAULT  (2 << CBAR_TYPE_SHIFT)
+#define CBAR_TYPE_S1_TRANS_S2_TRANS  (3 << CBAR_TYPE_SHIFT)
+#define CBAR_IRPTNDX_SHIFT    24
+#define CBAR_IRPTNDX_MASK    0xff
+
+#define SMMU_CB_BASE(smmu)    ((smmu)->s1cbt)
+#define SMMU_CB(n)    ((n) << 5)
+
+#define sTLBGSTATUS_GSACTIVE    (1 << 0)
+#define TLB_LOOP_TIMEOUT    1000000  /* 1s! */
+
+#define SCTLR_WACFG_WA    (2 << 26)
+#define SCTLR_RACFG_RA    (2 << 24)
+#ifdef CONFIG_P660_2P
+#define SCTLR_SHCFG    (1 << 22)
+#else
+#define SCTLR_SHCFG    (2 << 22)
+#endif
+#define SCTLR_MTCFG    (1 << 20)
+#define SCTLR_MEMATTR_WB  (0xf << 16)
+#define SCTLR_MEMATTR_NC  (0x5 << 16)
+#define SCTLR_MEMATTR_NGNRE  (0x1 << 16)
+#define SCTLR_CACHE_WBRAWA  (SCTLR_WACFG_WA | SCTLR_RACFG_RA | \
+      SCTLR_SHCFG | SCTLR_MTCFG | SCTLR_MEMATTR_WB)
+#define SCTLR_CACHE_NC    (SCTLR_SHCFG | \
+      SCTLR_MTCFG | SCTLR_MEMATTR_NC)
+#define SCTLR_CACHE_NGNRE  (SCTLR_SHCFG | \
+      SCTLR_MTCFG | SCTLR_MEMATTR_NGNRE)
+
+#define SCTLR_CFCFG      (1 << 7)
+#define SCTLR_CFIE      (1 << 6)
+#define SCTLR_CFRE      (1 << 5)
+#define SCTLR_E        (1 << 4)
+#define SCTLR_AFED      (1 << 3)
+#define SCTLR_M        (1 << 0)
+#define SCTLR_EAE_SBOP      (SCTLR_AFED)
+
+#define RESUME_RETRY      (0 << 0)
+#define RESUME_TERMINATE    (1 << 0)
+
+#define TTBCR_TG0_4K      (0 << 14)
+#define TTBCR_TG0_64K      (3 << 14)
+
+#define TTBCR_SH0_SHIFT      12
+#define TTBCR_SH0_MASK      0x3
+#define TTBCR_SH_NS      0
+#define TTBCR_SH_OS      2
+#define TTBCR_SH_IS      3
+#define TTBCR_ORGN0_SHIFT    10
+#define TTBCR_IRGN0_SHIFT    8
+#define TTBCR_RGN_MASK      0x3
+#define TTBCR_RGN_NC      0
+#define TTBCR_RGN_WBWA      1
+#define TTBCR_RGN_WT      2
+#define TTBCR_RGN_WB      3
+#define TTBCR_T1SZ_SHIFT    16
+#define TTBCR_T0SZ_SHIFT    0
+#define TTBCR_SZ_MASK      0xf
+
+#define MAIR_ATTR_SHIFT(n)    ((n) << 3)
+#define MAIR_ATTR_MASK      0xff
+#define MAIR_ATTR_DEVICE    0x04
+#define MAIR_ATTR_NC      0x44
+#define MAIR_ATTR_WBRWA      0xff
+#define MAIR_ATTR_IDX_NC    0
+#define MAIR_ATTR_IDX_CACHE    1
+#define MAIR_ATTR_IDX_DEV    2
+
+#define FSR_MULTI    (1 << 31)
+#define FSR_EF      (1 << 4)
+#define FSR_PF      (1 << 3)
+#define FSR_AFF      (1 << 2)
+#define FSR_TF      (1 << 1)
+#define FSR_IGN      (FSR_AFF)
+#define FSR_FAULT    (FSR_MULTI | FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
+
+#define FSYNR0_ASID(n)      (0xff & ((n) >> 24))
+#define FSYNR0_VMID(n)      (0xff & ((n) >> 16))
+#define FSYNR0_WNR      (1 << 4)
+#define FSYNR0_SS      (1 << 2)
+#define FSYNR0_CF      (1 << 0)
+
+#define SMMU_FEAT_COHERENT_WALK    (1 << 0)
+#define SMMU_FEAT_STREAM_MATCH    (1 << 1)
+#define SMMU_FEAT_TRANS_S1    (1 << 2)
+#define SMMU_FEAT_TRANS_S2    (1 << 3)
+#define SMMU_FEAT_TRANS_NESTED    (1 << 4)
+
+static UINT32 hisi_bypass_vmid = 0xff;
+
+VOID writel_relaxed (UINT32 Value, UINTN Base)
+{
+  MmioWrite32 (Base, Value);
+}
+
+UINT32 readl_relaxed (UINTN Base)
+{
+  return MmioRead32 (Base);
+}
+
+/* Wait for any pending TLB invalidations to complete */
+static void hisi_smmu_tlb_sync(SMMU_DEVICE *smmu)
+{
+  int count = 0;
+  UINTN gr0_base = smmu->Base;
+
+  writel_relaxed(0, gr0_base + SMMU_TLBGSYNC);
+  while (readl_relaxed(gr0_base + SMMU_TLBGSTATUS)
+         & sTLBGSTATUS_GSACTIVE) {
+    if (++count == TLB_LOOP_TIMEOUT) {
+      DEBUG ((EFI_D_ERROR, "TLB sync timed out -- SMMU (0x%p) may be deadlocked\n", gr0_base));
+      return;
+    }
+    MicroSecondDelay (1);
+  }
+}
+
+
+VOID *
+SmmuAllocateTable (
+  UINTN Size,
+  UINTN Alignment
+  )
+{
+  return AllocateAlignedReservedPages (EFI_SIZE_TO_PAGES (Size), Alignment);
+}
+
+
+EFI_STATUS
+SmmuInit (
+  SMMU_DEVICE       *Smmu
+  )
+{
+  UINT32 Value;
+  UINTN  Base = Smmu->Base;
+  UINTN  Index;
+
+  /* Clear Global FSR */
+  Value = MmioRead32 (Base + SMMU_RINT_GFSR);
+  MmioWrite32 (Base + SMMU_RINT_GFSR, Value);
+
+  /* mask all global interrupt */
+  MmioWrite32 (Base + SMMU_CFG_GFIM, 0xFFFFFFFF);
+
+  Value  = CFG_CBF_S1_ORGN_WA | CFG_CBF_S1_IRGN_WA | CFG_CBF_S1_SHCFG;
+  Value |= CFG_CBF_S2_ORGN_WA | CFG_CBF_S2_IRGN_WA | CFG_CBF_S2_SHCFG;
+  MmioWrite32 (Base + SMMU_CFG_CBF, Value);
+
+  /* Clear CB_FSR  */
+  for (Index = 0; Index < SMMU_CB_NUMIRPT; Index++) {
+    MmioWrite32 (Base + SMMU_RINT_CB_FSR(Index), FSR_FAULT);
+  }
+
+  return EFI_SUCCESS;
+}
+
+VOID *
+SmmuCreateS2Cbt (VOID)
+{
+  VOID  *Table;
+  UINTN  Index;
+
+  Table = SmmuAllocateTable (SMMU_S2CBT_SIZE, LShiftU64 (1, SMMU_S2CBT_SHIFT));
+  if (Table == NULL) {
+    DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Allocate table failed!\n", __FUNCTION__, __LINE__));
+    return NULL;
+  }
+  ZeroMem (Table, SMMU_S2CBT_SIZE);
+
+  for (Index = 0; Index < SMMU_MAX_CBS; Index++) {
+    MmioWrite32 ((UINTN)Table + SMMU_CB_S1CTBAR(Index), 0);
+    MmioWrite32 ((UINTN)Table + SMMU_CB_S2CR(Index), S2CR_TYPE_BYPASS);
+  }
+  return Table;
+}
+
+VOID *
+SmmuCreateS1Cbt (VOID)
+{
+  VOID  *Table;
+
+  Table = SmmuAllocateTable (SMMU_S1CBT_SIZE, LShiftU64 (1, SMMU_S1CBT_SHIFT));
+  if (Table == NULL) {
+    DEBUG ((EFI_D_ERROR, "[%a]:[%dL] Allocate table failed!\n", __FUNCTION__, __LINE__));
+    return NULL;
+  }
+  ZeroMem (Table, SMMU_S1CBT_SIZE);
+
+  return Table;
+}
+
+EFI_STATUS
+SmmuConfigSwitch (
+  SMMU_DEVICE       *Smmu
+  )
+{
+  VOID*  S2;
+  VOID*  S1;
+  UINT32 reg;
+
+  S2 = SmmuCreateS2Cbt ();
+  if (S2 == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  Smmu->S2Cbt = (UINTN) S2;
+
+  S1 = SmmuCreateS1Cbt ();
+  if (S1 == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S1CTBAR(SMMU_OS_VMID), (UINT32) RShiftU64 ((UINT64)S1, SMMU_S1CBT_SHIFT));
+
+  // Force device for VMID 0 ASID 0
+  MmioWrite32 ((UINTN)S1 + SMMU_CB(0) + SMMU_S1_SCTLR, SCTLR_CACHE_WBRAWA);
+  // Force device for VMID 0 ASID 1
+  MmioWrite32 ((UINTN)S1 + SMMU_CB(1) + SMMU_S1_SCTLR, SCTLR_CACHE_NGNRE);
+
+  /*
+   * Use the weakest attribute, so no impact stage 1 output attribute.
+   */
+  reg = CBAR_TYPE_S1_TRANS_S2_BYPASS |
+    (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
+    (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
+  MmioWrite32 (Smmu->S2Cbt + SMMU_CB_CBAR(SMMU_OS_VMID), reg);
+
+  /* Mark S2CR as translation */
+  reg = S2CR_TYPE_TRANS | S2CR_MTSH_WEAKEST;
+  MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S2CR(SMMU_OS_VMID), reg);
+
+  /* Bypass need use another S2CR */
+  reg = S2CR_TYPE_BYPASS;
+  MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S2CR(hisi_bypass_vmid), reg);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SmmuFlushCbt (
+  SMMU_DEVICE       *Smmu
+  )
+{
+  UINTN Index;
+
+  if (Smmu->S2Cbt == 0) {
+    DEBUG ((EFI_D_ERROR, "[%a]:[%dL] S2Cbt is null!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  WriteBackInvalidateDataCacheRange ((VOID *)Smmu->S2Cbt, SMMU_S2CBT_SIZE);
+  for (Index = 0; Index < SMMU_MAX_CBS; Index++) {
+    UINTN S1Ctb = MmioRead32 (Smmu->S2Cbt + SMMU_CB_S1CTBAR(SMMU_OS_VMID));
+    if (S1Ctb) {
+      // TODO: shall we really need to flush 64KB? Or 8KB is enough?
+      WriteBackInvalidateDataCacheRange ((VOID *)LShiftU64 (S1Ctb, SMMU_S1CBT_SHIFT), SMMU_S1CBT_SIZE);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SmmuEnableTable (
+  SMMU_DEVICE       *Smmu
+  )
+{
+  UINT32 reg;
+  UINTN  gr0_base = Smmu->Base;
+
+  (VOID) SmmuFlushCbt (Smmu);
+
+  /* Clear Global FSR */
+  reg = readl_relaxed(gr0_base + SMMU_RINT_GFSR);
+  writel_relaxed(reg, gr0_base + SMMU_RINT_GFSR);
+
+  /* unmask all global interrupt */
+  writel_relaxed(0, gr0_base + SMMU_CFG_GFIM);
+
+  reg  = CFG_CBF_S1_ORGN_WA | CFG_CBF_S1_IRGN_WA | CFG_CBF_S1_SHCFG;
+  reg |= CFG_CBF_S2_ORGN_WA | CFG_CBF_S2_IRGN_WA | CFG_CBF_S2_SHCFG;
+  writel_relaxed(reg, gr0_base + SMMU_CFG_CBF);
+
+  reg = (UINT32) RShiftU64 (Smmu->S2Cbt, SMMU_S2CBT_SHIFT);
+  writel_relaxed(reg, gr0_base + SMMU_CFG_S2CTBAR);
+
+  /* Invalidate all TLB, just in case */
+  writel_relaxed(0, gr0_base + SMMU_TLBIALL);
+  hisi_smmu_tlb_sync(Smmu);
+
+  writel_relaxed(sACR_WC_EN, gr0_base + SMMU_CTRL_ACR);
+
+  /* Enable fault reporting */
+  reg  = (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
+  reg &= ~sCR0_CLIENTPD;
+
+  writel_relaxed(reg, gr0_base + SMMU_CTRL_CR0);
+  ArmDataSynchronizationBarrier ();
+
+  return EFI_SUCCESS;
+};
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h
new file mode 100644
index 0000000..16e7305
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h
@@ -0,0 +1,36 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SMMU_H_
+#define _SMMU_H_
+
+typedef struct {
+  UINTN       Base;
+  UINTN       S2Cbt;
+} SMMU_DEVICE;
+
+EFI_STATUS
+SmmuConfigSwitch (
+  SMMU_DEVICE       *Smmu
+  );
+
+EFI_STATUS
+SmmuEnableTable (
+  SMMU_DEVICE       *Smmu
+  );
+
+
+#endif
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c
new file mode 100644
index 0000000..88ad718
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c
@@ -0,0 +1,103 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include "PcieInit.h"
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+
+extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
+extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
+extern EFI_STATUS PciePortInit (UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
+
+PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] =
+{
+    //Port 0
+    {
+        0x0,                        //Portindex
+
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        }, //PortInfo
+
+    },
+
+    //Port 1
+    {
+        0x1,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+
+    //Port 2
+    {
+        0x2,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+
+    //Port 3
+    {
+        0x3,                        //Portindex
+        {
+            PCIE_ROOT_COMPLEX,      //PortType
+            PCIE_WITDH_X8,          //PortWidth
+            PCIE_GEN3_0,            //PortGen
+        },
+
+    },
+};
+
+EFI_STATUS
+PcieInitEntry (
+  IN EFI_HANDLE                 ImageHandle,
+  IN EFI_SYSTEM_TABLE           *SystemTable
+  )
+
+{
+    UINT32             Port;
+    EFI_STATUS         Status = EFI_SUCCESS;
+    UINT32             HostBridgeNum = 0;
+
+    for (HostBridgeNum = 0; HostBridgeNum < PCIE_HOST_BRIDGE_NUM; HostBridgeNum++)
+    {
+        for (Port = 0; Port < PCIE_MAX_PORT_NUM; Port++)
+        {
+            if (!((((PcdGet32(PcdPcieRootBridgeMask) >> (4 * HostBridgeNum))) >> Port) & 0x1))
+            {
+                continue;
+            }
+
+            Status = PciePortInit(HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
+            if(EFI_ERROR(Status))
+            {
+                DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
+            }
+
+        }
+    }
+
+    return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h
new file mode 100644
index 0000000..d837416
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h
@@ -0,0 +1,93 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_H__
+#define __PCIE_INIT_H__
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+
+extern EFI_GUID gEfiPcieRootBridgeProtocolGuid;
+
+#define PCIE_LOG_ID                             1
+
+#define PCIE_CONFIG_SPACE_SIZE                  0x1000      //4k
+#define PCIE_MEMORY_SPACE_SIZE                  0x800000        //8M
+#define PCIE_IO_SPACE_SIZE          0x800000    //8M
+#define PCIE_TYPE1_MEM_SIZE          (PCIE_MEMORY_SPACE_SIZE + PCIE_IO_SPACE_SIZE)
+
+#define CONFIG_SPACE_BASE_ADDR_LOW 0xe2000000
+#define CONFIG_SPACE_BASE_ADDR_HIGH 0x0
+#define CONFIG_SPACE_ADDR_LIMIT      (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_MEM_BASE_ADDR_LOW   (CONFIG_SPACE_BASE_ADDR_LOW + PCIE_CONFIG_SPACE_SIZE)
+#define PCIE_MEM_BASE_ADDR_HIGH 0x0
+#define PCIE_MEM_ADDR_LIMIT      (PCIE_MEM_BASE_ADDR_LOW + PCIE_MEMORY_SPACE_SIZE - PCIE_CONFIG_SPACE_SIZE - 1)
+
+#define PCIE_IO_BASE_ADDR_LOW   (PCIE_MEM_ADDR_LIMIT - 1)
+#define PCIE_IO_BASE_ADDR_HIGH  0x0
+#define PCIE_IO_ADDR_LIMIT      (PCIE_IO_BASE_ADDR_LOW + PCIE_IO_SPACE_SIZE - 1)
+
+#define PCIE_INBOUND_BASE        0xD0000000
+
+
+#define PCIE_ALL_DMA_BASE               (0x100000000)
+#define PCIE0_ALL_DMA_BASE              (PCIE_ALL_DMA_BASE)
+#define PCIE0_ALL_DMA_SIZE              (0x8000000)
+#define PCIE0_ALL_BAR01_BASE             (0x10000000)
+#define PCIE0_ALL_BAR23_BASE             (PCIE0_ALL_BAR01_BASE + PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE01_BASE         0x2c0000000  //(HRD_ATTR_TRAN_ADDR_BASE_HOST_ADDR)
+#define PCIE0_ALL_TRANSLATE01_SIZE         (PCIE_MAX_AXI_SIZE)
+#define PCIE0_ALL_TRANSLATE23_BASE         (PCIE0_ALL_TRANSLATE01_BASE + PCIE0_ALL_TRANSLATE01_SIZE)
+#define PCIE0_ALL_TRANSLATE23_SIZE         (PCIE0_ALL_DMA_SIZE)
+
+
+#define PCIE0_REG_BASE        (0xb0070000)
+#define PCIE1_REG_BASE        (0xb0080000)
+#define PCIE2_REG_BASE        (0xb0090000)
+#define PCIE3_REG_BASE        (0xb00a0000)
+
+#define PCIE_BASE_BAR               (0xf0000000)
+#define PCIE_BAR_SIZE                (0x1000000)
+
+
+#define PCIE_AXI_SIZE         (0x1000000)
+#define PCIE0_AXI_BASE        (0xb3000000)
+#define PCIE1_AXI_BASE        (PCIE0_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE2_AXI_BASE        (PCIE1_AXI_BASE + PCIE_AXI_SIZE)
+#define PCIE3_AXI_BASE        (PCIE2_AXI_BASE + PCIE_AXI_SIZE)
+
+//#define PCIE_CONFIG_SPACE_SIZE     (0x1000)
+#define PCIE0_CONFIG_BASE     (PCIE1_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE1_CONFIG_BASE     (PCIE2_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE2_CONFIG_BASE     (PCIE3_AXI_BASE - PCIE_CONFIG_SPACE_SIZE)
+#define PCIE3_CONFIG_BASE     (PCIE3_AXI_BASE +  PCIE_AXI_SIZE - PCIE_CONFIG_SPACE_SIZE)
+
+
+#define PCIE0_TRANSLATE_BASE            (0x30000000)
+#define PCIE1_TRANSLATE_BASE            (PCIE0_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE2_TRANSLATE_BASE            (PCIE1_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+#define PCIE3_TRANSLATE_BASE            (PCIE2_TRANSLATE_BASE + PCIE_TRANSLATE_SIZE)
+
+#define PCIE0_BAR_BASE              (PCIE0_AXI_BASE)
+#define PCIE1_BAR_BASE              (PCIE1_AXI_BASE)
+#define PCIE2_BAR_BASE              (PCIE2_AXI_BASE)
+#define PCIE3_BAR_BASE              (PCIE3_AXI_BASE)
+
+
+#endif
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf
new file mode 100644
index 0000000..4bbb54f
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf
@@ -0,0 +1,56 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PcieInitDxe
+  FILE_GUID                      = 2D53A704-A544-4A82-83DF-FFECF4B4AA97
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = PcieInitEntry
+
+[Sources]
+  PcieInit.c
+  PcieInitLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  UefiLib
+  BaseLib
+  DebugLib
+  ArmLib
+  TimerLib
+  PcdLib
+  IoLib
+
+[Protocols]
+
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask
+
+[depex]
+  TRUE
+
+
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c
new file mode 100644
index 0000000..3581b41
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c
@@ -0,0 +1,1048 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "PcieInitLib.h"
+#include <Library/DebugLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+
+static PCIE_INIT_CFG mPcieIntCfg;
+UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000};
+UINT64 pcie_serders_base[2][4] = {{0xB2080000,0xB2000000,0xB2100000,0xB2200000},{BASE_4TB + 0xB2080000,BASE_4TB + 0xB2000000,BASE_4TB + 0xB2100000,BASE_4TB + 0xB2200000}};
+UINT64 io_sub0_base = 0xa0000000;
+UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000};
+#define PCIE_REG_BASE(HostBridgeNum,port)              (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000))
+UINT32 loop_test_flag[4] = {0,0,0,0};
+UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR;
+#define PCIE_GEN1 0    /* PCIE 1.0 */
+#define  PCIE_GEN2 1    /* PCIE 2.0 */
+#define  PCIE_GEN3 2    /* PCIE 3.0 */
+#define DS_API(lane)           ((0x1FF6c + 8*(15-lane))*2)
+
+extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
+extern PCIE_IATU gastr_pcie_iatu_cfg;
+extern PCIE_IATU_VA mPcieIatuTable;
+
+VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value)
+{
+    RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+
+}
+
+UINT32 PcieRegRead(UINT32 Port, UINTN Offset)
+{
+    UINT32 Value = 0;
+
+    RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
+    return Value;
+}
+
+VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
+{
+    RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+}
+
+UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
+{
+    UINT32 Value = 0;
+    RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
+    return Value;
+}
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode)
+{
+    u_sc_pcie0_clkreq pcie0;
+    u_sc_pcie1_clkreq pcie1;
+    u_sc_pcie2_clkreq pcie2;
+    u_sc_pcie3_clkreq pcie3;
+
+    switch(Port)
+    {
+        case 0:
+            RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+            pcie0.Bits.pcie0_apb_cfg_sel = Mode;
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
+            break;
+        case 1:
+            RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+            pcie1.Bits.pcie1_apb_cfg_sel = Mode;
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
+            break;
+        case 2:
+            RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+            pcie2.Bits.pcie2_apb_cfg_sel = Mode;
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
+            break;
+        case 3:
+            RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+            pcie3.Bits.pcie3_apb_cfg_sel = Mode;
+            RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
+            break;
+        default:
+            break;
+    }
+}
+
+
+
+EFI_STATUS PcieEnableItssm(UINT32 HostBridgeNum, UINT32 Port)
+{
+    PCIE_CTRL_7_U pcie_ctrl7;
+
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if(mPcieIntCfg.PortIsInitilized[Port])
+    {
+        return PCIE_ERR_ALREADY_INIT;
+    }
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+    pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+    pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1;
+    PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieDisableItssm(UINT32 HostBridgeNum, UINT32 Port)
+{
+    PCIE_CTRL_7_U pcie_ctrl7;
+
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return PCIE_ERR_PARAM_INVALID;
+    }
+
+
+    if(mPcieIntCfg.PortIsInitilized[Port])
+    {
+        return PCIE_ERR_ALREADY_INIT;
+    }
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+    pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
+    pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0;
+    PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)
+{
+    PCIE_EP_PCIE_CAP12_U pcie_cap12;
+
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG);
+    pcie_cap12.Bits.targetlinkspeed = Speed;
+    PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+
+    if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+        mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+    {
+        pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG);
+        pcie_cap12.Bits.targetlinkspeed = Speed;
+        PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+    PCIE_EP_PORT_LOGIC4_U pcie_logic4;
+    PCIE_EP_PORT_LOGIC22_U logic22;
+
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return PCIE_ERR_PARAM_INVALID;
+    }
+
+    pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+    pcie_logic4.Bits.linkmodeenable = Width;
+    pcie_logic4.Bits.crosslinkenable = 0;
+    pcie_logic4.Bits.fastlinkmode = 1;
+    PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+    logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+    logic22.Bits.n_fts = 0xff;
+    if(Width == PCIE_WITDH_X1)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 1;
+    }
+    else if(Width == PCIE_WITDH_X2)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 2;
+    }
+    else
+    {
+        logic22.Bits.pre_determ_num_of_lane = 3;
+    }
+    PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+    if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
+        mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
+    {
+        pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG);
+        pcie_logic4.Bits.linkmodeenable = Width;
+        pcie_logic4.Bits.crosslinkenable = 0;
+        pcie_logic4.Bits.fastlinkmode = 1;
+        PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
+
+        logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG);
+        logic22.Bits.n_fts = 0xff;
+        if(Width == PCIE_WITDH_X1)
+        {
+            logic22.Bits.pre_determ_num_of_lane = 1;
+        }
+        else if(Width == PCIE_WITDH_X2)
+        {
+            logic22.Bits.pre_determ_num_of_lane = 2;
+        }
+        else
+        {
+            logic22.Bits.pre_determ_num_of_lane = 3;
+        }
+        PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width)
+{
+    PCIE_EP_PORT_LOGIC22_U logic22;
+    PCIE_EEP_PCI_CFG_HDR15_U hdr15;
+    UINT32 Value = 0;
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
+    Value &= ~(0x3f<<16);
+
+    if(Width == PCIE_WITDH_X1)
+    {
+        Value |= (0x1 << 16);
+    }
+    else if(Width == PCIE_WITDH_X2)
+    {
+        Value |= (0x3 << 16);
+    }
+    else if(Width == PCIE_WITDH_X4)
+    {
+        Value |= (0x7 << 16);
+    }
+    else if(Width == PCIE_WITDH_X8)
+    {
+        Value |= (0xf << 16);
+    }
+    else
+    {
+        DEBUG((EFI_D_ERROR,"Width is not invalid\n"));
+    }
+
+    PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value);
+
+    logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
+    logic22.UInt32 &= ~(0x1f<<8);
+
+    if(Width == PCIE_WITDH_X1)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 1;
+    }
+    else if(Width == PCIE_WITDH_X2)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 2;
+    }
+    else if(Width == PCIE_WITDH_X4)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 4;
+    }
+    else if(Width == PCIE_WITDH_X8)
+    {
+        logic22.Bits.pre_determ_num_of_lane = 8;
+    }
+    else
+    {
+        DEBUG((EFI_D_ERROR,"Width is not invalid\n"));
+    }
+
+    PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
+
+    /* setup RC BARs */
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004);
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000);
+
+    /* setup interrupt pins */
+    hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG);
+    hdr15.UInt32 &= 0xffff00ff;
+    hdr15.UInt32 |= 0x00000100;
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32);
+
+    /* setup bus numbers */
+    Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG);
+    Value &= 0xff000000;
+    Value |= 0x00010100;
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value);
+
+    /* setup command register */
+    Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG);
+    Value &= 0xffff0000;
+    Value |= 0x1|0x2|0x4|0x100;
+    PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value);
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS PcieModeSet(UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType)
+{
+    PCIE_CTRL_0_U str_pcie_ctrl_0;
+
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if(mPcieIntCfg.PortIsInitilized[Port])
+    {
+        return PCIE_ERR_ALREADY_INIT;
+    }
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+    str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG);
+    if(PcieType == PCIE_END_POINT)
+    {
+        str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE;
+    }
+    else
+    {
+        str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC;
+    }
+    PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32);
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+    return EFI_SUCCESS;
+}
+
+VOID PciePcsInit(UINT32 HostBridgeNum, UINT32 Port)
+{
+
+    if(Port<=2)
+    {
+        RegWrite(pcie_serders_base[HostBridgeNum][Port] + 0xc088, 0x212);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044);
+
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0);
+    }
+    else
+
+    {
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000);
+
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001);
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001);
+
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff);
+    }
+
+}
+
+VOID PcieEqualization(UINT32 Port)
+{
+    UINT32  Value;
+
+    PcieRegWrite(Port, 0x890, 0x1400);
+    PcieRegWrite(Port, 0x894, 0xfd7);
+
+    PcieRegWrite(Port, 0x89c, 0x0);
+    PcieRegWrite(Port, 0x898, 0xfc00);
+    PcieRegWrite(Port, 0x89c, 0x1);
+    PcieRegWrite(Port, 0x898, 0xbd00);
+    PcieRegWrite(Port, 0x89c, 0x2);
+    PcieRegWrite(Port, 0x898, 0xccc0);
+    PcieRegWrite(Port, 0x89c, 0x3);
+    PcieRegWrite(Port, 0x898, 0x8dc0);
+    PcieRegWrite(Port, 0x89c, 0x4);
+    PcieRegWrite(Port, 0x898, 0xfc0);
+    PcieRegWrite(Port, 0x89c, 0x5);
+    PcieRegWrite(Port, 0x898, 0xe46);
+    PcieRegWrite(Port, 0x89c, 0x6);
+    PcieRegWrite(Port, 0x898, 0xdc8);
+    PcieRegWrite(Port, 0x89c, 0x7);
+    PcieRegWrite(Port, 0x898, 0xcb46);
+    PcieRegWrite(Port, 0x89c, 0x8);
+    PcieRegWrite(Port, 0x898, 0x8c07);
+    PcieRegWrite(Port, 0x89c, 0x9);
+    PcieRegWrite(Port, 0x898, 0xd0b);
+    PcieRegWrite(Port, 0x8a8, 0x103ff21);
+
+    Value = PcieRegRead(Port, 0x80);
+    Value |= 0x80;
+    PcieRegWrite(Port, 0x80, Value);
+
+    PcieRegWrite(Port, 0x184, 0x44444444);
+    PcieRegWrite(Port, 0x188, 0x44444444);
+    PcieRegWrite(Port, 0x18c, 0x44444444);
+    PcieRegWrite(Port, 0x190, 0x44444444);
+
+}
+
+
+EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+    {
+        (VOID)PcieDisableItssm(HostBridgeNum, Port);
+    }
+
+    mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+    mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+    ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+    if(Port <= 2)
+    {
+        RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+        MicroSecondDelay(0x1000);
+
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+        MicroSecondDelay(0x1000);
+    }
+    else
+    {
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+        MicroSecondDelay(0x1000);
+
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+        MicroSecondDelay(0x1000);
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+    {
+        (VOID)PcieDisableItssm(HostBridgeNum, Port);
+    }
+
+    mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+    mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+    ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+    if(Port <= 2)
+    {
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
+        MicroSecondDelay(0x1000);
+    }
+    else
+    {
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
+        MicroSecondDelay(0x1000);
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
+    {
+        (VOID)PcieDisableItssm(HostBridgeNum, Port);
+    }
+
+    mPcieIntCfg.PortIsInitilized[Port] = FALSE;
+    mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
+    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
+    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
+    ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
+
+    if(Port <= 2)
+    {
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
+        MicroSecondDelay(0x1000);
+    }
+    else
+    {
+        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
+        MicroSecondDelay(0x1000);
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port)
+{
+    u_sc_pcie_hilink_pcs_reset_req reset_req;
+    UINT32 pcs_local_reset_status;
+    UINT32 pcs_local_status_checked;
+    UINT32 hilink_reset_status;
+    UINT32 hilink_status_checked;
+    UINT32 count = 0;
+
+    reset_req.UInt32 = 0;
+    reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
+
+    reset_req.UInt32 = 0;
+    reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
+    MicroSecondDelay(0x1000);
+
+  /* read reset status, make sure pcs is reset */
+  do {
+        MicroSecondDelay(1000);
+        count ++;
+        RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_reset_status);
+    pcs_local_status_checked =
+        ((pcs_local_reset_status & (1 << Port)) !=
+         (1 << Port));
+
+  } while ((pcs_local_status_checked) && (count < 1000));
+
+  if (pcs_local_status_checked)
+        DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n"));
+
+    count = 0;
+  do {
+        MicroSecondDelay(1000);
+        count ++;
+        RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
+    hilink_status_checked =
+        ((hilink_reset_status & (0xff << (Port << 3))) !=
+         (0xff << (Port << 3)));
+  } while ((hilink_status_checked) && (count < 1000));
+
+  if (hilink_status_checked)
+        DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n"));
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port)
+{
+    u_sc_pcie_hilink_pcs_reset_req reset_req;
+    UINT32 pcs_local_status;
+    UINT32 pcs_local_status_checked;
+    UINT32 hilink_reset_status;
+    UINT32 hilink_status_checked;
+    UINT32 count = 0;
+
+
+    reset_req.UInt32 = 0;
+    reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
+    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
+
+    reset_req.UInt32 = 0;
+    reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
+    RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
+
+  /* read reset status, make sure pcs is deassert */
+  do {
+        MicroSecondDelay(1000);
+        count ++;
+        RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_status);
+    pcs_local_status_checked = (pcs_local_status & (1 << Port));
+  } while ((pcs_local_status_checked) && (count < 1000));
+
+  /* get a timeout error */
+  if (pcs_local_status_checked)
+        DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
+
+    count = 0;
+  do {
+        MicroSecondDelay(1000);
+        RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
+    hilink_status_checked = (hilink_reset_status &
+           (0xff << (Port << 3)));
+  } while ((hilink_status_checked) && (count < 1000));
+
+  if (hilink_status_checked)
+        DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
+
+    return EFI_SUCCESS;
+}
+
+VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port)
+{
+  UINT32 val;
+    UINT32 current_speed;
+  UINT32 ltssm_state;
+  UINT32 timeout = 0;
+  UINT32 eq = 0;
+  UINT32 loop = 100000;
+    U_SC_PCIE0_SYS_STATE4      PcieStat;
+
+  while (loop)
+  {
+      MicroSecondDelay(10);
+      RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+        val = PcieStat.UInt32;
+      current_speed = (val >> 6) & 0x3;
+      if (current_speed == PCIE_GEN3)
+        break;
+      loop--;
+  }
+  if (!loop) {
+        DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+    return;
+  }
+
+  ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+  while ((current_speed == PCIE_GEN3) &&
+         (ltssm_state != PCIE_LTSSM_LINKUP_STATE) && (timeout < 200)) {
+    if ((ltssm_state & 0x30) == 0x20)
+      eq = 1;
+
+        if ((ltssm_state == 0xd) && (eq == 1))
+        {
+            MicroSecondDelay(5000);
+      RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+            val = PcieStat.UInt32;
+      ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+      current_speed = (val >> 6) & 0x3;
+            if (ltssm_state == 0xd)
+            {
+                DEBUG((EFI_D_ERROR, "Do symbol align reset rate %d ltssm 0x%x\n",current_speed, ltssm_state));
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x8000000);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x8000000);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x8000000);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x8000000);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x8000000);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x8000000);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x8000000);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x8000000);
+
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0);
+                RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0);
+      }
+            break;
+    }
+
+        RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+        val = PcieStat.UInt32;
+    ltssm_state = val & PCIE_LTSSM_STATE_MASK;
+    current_speed = (val >> 6) & 0x3;
+
+    MicroSecondDelay(1000);
+    timeout++;
+  }
+
+  if (timeout >= 200) {
+    DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+    return;
+  }
+  DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1));
+}
+
+VOID Gen3DfeEnable(UINT32 HostBridgeNum, UINT32 Port)
+{
+  UINT32 val;
+  UINT32 lane;
+  UINT32 current_speed;
+    U_SC_PCIE0_SYS_STATE4      PcieStat;
+
+  if (Port == 3)
+    return;
+  RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+    val = PcieStat.UInt32;
+  current_speed = (val >> 6) & 0x3;
+  if (current_speed != PCIE_GEN3)
+    return;
+  for (lane = 0; lane < 8; lane++)
+    RegWrite(pcie_serders_base[HostBridgeNum][Port] +  (UINT32)DS_API(lane) + 4, 0x3851);
+
+    DEBUG((EFI_D_ERROR, "enable DFE success\n"));
+}
+
+EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock)
+{
+  UINT32 reg_clock_disable;
+  UINT32 reg_clock_enable;
+  UINT32 reg_clock_status;
+    UINT32 clock_status;
+    UINT32 clock_status_checked;
+    UINT32  clock_ctrl;
+    UINT32 count = 0;
+
+  if (Port == 3) {
+    reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG;
+    reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG;
+    reg_clock_status = PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG;
+  } else {
+    reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port);
+    reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port);
+    reg_clock_status = PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(Port);
+  }
+
+    if (0x1610 == soctype)
+    {
+        clock_ctrl = 0x7;
+    }
+    else
+    {
+        clock_ctrl = 0x3;
+        if (Clock)
+          RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, clock_ctrl);
+        else
+          RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, clock_ctrl);
+    }
+
+    do {
+        count ++;
+        MicroSecondDelay(1000);
+        RegRead(pcie_subctrl_base[HostBridgeNum] + reg_clock_status, clock_status);
+    if (Clock)
+      clock_status_checked =
+          ((clock_status & clock_ctrl) != clock_ctrl);
+    else
+      clock_status_checked =
+          ((clock_status & clock_ctrl) != 0);
+  } while ((clock_status_checked) && (count < 1000)); //1S
+
+  /* get a timeout error */
+  if (clock_status_checked)
+        DEBUG((EFI_D_ERROR, "clock operation failed!\n"));
+
+    return EFI_SUCCESS;
+}
+
+VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
+{
+    UINT32 Value = 0;
+
+    if (0x1610 == soctype)
+    {
+    }
+    else
+    {
+        RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value);
+        Value &= ~(0xf);
+      Value |= Spd;
+      RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value);
+        return;
+    }
+    return;
+}
+
+VOID PcieSpdControl(UINT32 HostBridgeNum, UINT32 Port)
+{
+  UINT32 Value = 0;;
+
+  /* set link width speed control register */
+    RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value);
+  /*
+   * set the Directed Speed Change field of the Link Width and Speed
+   * Change Control register
+   */
+  Value |= (1 << 17);
+    RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value);
+}
+
+VOID PcieSetDb2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 enable)
+{
+    UINT32 dbi_ctrl;
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+    RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl);
+  if (enable)
+    dbi_ctrl |= BIT0;
+  else
+    dbi_ctrl &= ~BIT0;
+    RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl);
+
+  PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+}
+
+VOID PcieDisabledBar0(UINT32 HostBridgeNum, UINT32 Port)
+{
+  PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_ENABLE);
+    RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x10,0);
+  PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_DISABLE);
+}
+
+/* Configure vmid/asid table in PCIe host */
+VOID PcieConfigContextP660(UINT32 HostBridgeNum, UINT32 Port)
+{
+  UINT32 i = 0;
+  UINTN val = 0;;
+
+  /*
+   * enable to clean vmid and asid tables though apb bus
+   * */
+  PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+    RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+  /* enable ar channel */
+  val |= PCIE_RD_TAB_SEL | PCIE_RD_TAB_EN;
+  RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+  PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE);
+  for (i = 0; i < 0x800; i++)
+        PcieRegWrite(Port, i * 4, 0);
+
+  PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+  /* enable aw channel */
+  val &= (~PCIE_RD_TAB_SEL);
+  val |= PCIE_RD_TAB_EN;
+  RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+  PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE);
+
+  /*
+   * init vmid and asid tables for all PCIe devices as 0
+   * vmid table: 0 ~ 0x3ff, asid table: 0x400 ~ 0x7ff
+   */
+  for (i = 0; i < 0x800; i++)
+        PcieRegWrite(Port, i * 4, 0);
+
+  PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+
+    RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+  /* disable ar channel */
+  val |= PCIE_RD_TAB_SEL;
+  val &= (~PCIE_RD_TAB_EN);
+  RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+  /* disable aw channel */
+  val &= ((~PCIE_RD_TAB_SEL) & (~PCIE_RD_TAB_EN));
+    RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val);
+
+  RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL24_REG, 0xb7010040 & 0xffffffff);
+    RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL28_REG, 0);
+
+    RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL16_REG, (1<<12)|(1<<16));
+    RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL29_REG, (1<<12));
+
+  PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);;
+}
+
+EFI_STATUS PcieMaskLinkUpInit(UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32 Value = 0;
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+    Value = PcieRegRead(Port, 0x1d0);
+    Value |= 1 << 12;
+    PcieRegWrite(Port,0x1d0, Value);
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+    return EFI_SUCCESS;
+}
+
+BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port)
+{
+    UINT32                     Value = 0;
+    U_SC_PCIE0_SYS_STATE4      PcieStat;
+
+    RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
+    Value = PcieStat.UInt32;
+    if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
+        return TRUE;
+
+    return FALSE;
+}
+
+VOID PcieWriteOwnConfig(UINT32 Port, UINT32 Offset)
+{
+    UINT32 Value = 0;
+    Value = PcieRegRead(Port,Offset & (~0x3));
+    Value &= 0x0000ffff;
+    Value |= 0x06040000;
+    PcieRegWrite(Port, Offset & (~0x3), Value);
+    return;
+}
+
+EFI_STATUS
+EFIAPI
+PciePortInit (
+  IN UINT32                 HostBridgeNum,
+  IN PCIE_DRIVER_CFG        *PcieCfg
+  )
+{
+     UINT32              Count = 0;
+     UINT32             PortIndex = PcieCfg->PortIndex;
+     UINT32             Value = 0;
+
+
+     if(PortIndex >= PCIE_MAX_PORT_NUM)
+     {
+        return EFI_INVALID_PARAMETER;
+     }
+
+     if(mPcieIntCfg.PortIsInitilized[PortIndex])
+     {
+        return PCIE_ERR_ALREADY_INIT;
+     }
+
+     mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
+
+     /* assert reset signals */
+     (VOID)AssertPcieCoreReset(HostBridgeNum, PortIndex);
+     (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 0);
+     (VOID)AssertPciePcsReset(HostBridgeNum, PortIndex);
+
+     /* de-assert phy reset */
+     (VOID)DeassertPciePcsReset(HostBridgeNum, PortIndex);
+
+     /* de-assert core reset */
+     (VOID)DeassertPcieCoreReset(HostBridgeNum, PortIndex);
+     (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 1);
+
+     do {
+    RegRead(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(PortIndex * 0x10000) + 0x8108, Value);
+        if (Count == 10) {
+            DEBUG((EFI_D_ERROR, "PCIe Failed! PLL Locked: 0x%x\n\n",Value));
+      return EFI_NOT_READY;
+        }
+        Count++;
+    MicroSecondDelay(100000);
+   } while ((Value & 0x3) == 0);
+   Count = 0;
+
+     /* initialize phy */
+     (VOID)PciePcsInit(HostBridgeNum, PortIndex);
+
+     (VOID)PcieModeSet(HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType);
+     (VOID)PcieSpdSet(0x660, HostBridgeNum, PortIndex, 3);
+     (VOID)PcieSpdControl(HostBridgeNum, PortIndex);
+     /* setup root complex */
+     (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
+
+     /* Pcie Equalization*/
+     (VOID)PcieEqualization(PortIndex);
+
+     /* assert LTSSM enable */
+     (VOID)PcieEnableItssm(HostBridgeNum, PortIndex);
+
+     /*
+      * This is a PCS hardware bug, we fix it by resetting
+      * PCS symalign module state machine
+     */
+     (VOID)PcieGen3Config(HostBridgeNum, PortIndex);
+     PcieConfigContextP660(HostBridgeNum, PortIndex);
+     (VOID)PcieDisabledBar0(HostBridgeNum, PortIndex);
+     (VOID)PcieWriteOwnConfig(PortIndex, 0xa);
+     /* check if the link is up or not */
+   while (!PcieIsLinkUp(HostBridgeNum, PortIndex)) {
+         MicroSecondDelay(1000);
+     Count++;
+     if (Count >= 1000) {
+      DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex));
+      return PCIE_ERR_LINK_OVER_TIME;
+     }
+   }
+     DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex));
+
+     /* dfe enable is just for 660 */
+     (VOID)Gen3DfeEnable(HostBridgeNum, PortIndex);
+
+
+     PcieRegWrite(PortIndex, 0x80c, 0x208FF);
+
+     return EFI_SUCCESS;
+}
+
+
+
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable)
+{
+    PCIE_SYS_CTRL20_U dbi_ro_enable;
+
+    if(Port >= PCIE_MAX_PORT_NUM)
+    {
+        return EFI_INVALID_PARAMETER;
+    }
+
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
+    dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG);
+    dbi_ro_enable.Bits.ro_sel = Enable;
+    PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32);
+    PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
+
+    return EFI_SUCCESS;
+
+}
+
+VOID PcieDelay(UINT32 dCount)
+{
+    volatile UINT32 *uwCnt = &dCount;
+
+    while(*uwCnt > 0)
+    {
+        *uwCnt = *uwCnt - 1;
+    }
+
+}
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h
new file mode 100644
index 0000000..00a2b27
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h
@@ -0,0 +1,239 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_INIT_LIB_H__
+#define __PCIE_INIT_LIB_H__
+
+#include <Uefi.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+#include "PcieKernelApi.h"
+
+#define PCIE_AXI_SLAVE_BASE             (0xb3000000)
+#define PCIE_MAX_AXI_SIZE               (0x1000000)
+#define PCIE_AXI_BASE(port)             (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE)
+#define PCIE_SMMU_BASE                  (0xb0040000)
+
+
+#define PCIE_DMA_CHANNEL_NUM            (2)
+#define PCIE_DMA_RESOURCE_MODE_SIZE     (0x40000)
+#define PCIE_DMA_BURST_SIZE             (0x80000000)
+
+#define PCIE_ADDR_BASE_OFFSET                       0x46C00000
+#define PCIE_ADDR_BASE_HOST_ADDR                    (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST)
+#define NP_DDR_BASE_ADDR_HOST                       0x236E00000ULL
+
+
+
+#define PCIE_GIC_MSI_ITS_BASE       (0xb7010040)
+#define PCIE_INT_BASE               (13824)
+#define PCIE_INT_LIMIT              (PCIE_INT_BASE + 64)
+
+#define PCIE_NTB_MEM_SIZE             (0x1000000)
+#define PCIE_NTB_BAR01_SIZE           (0x10000) // 64K
+#define PCIE_NTB_BAR23_SIZE           (0x800000) // 8M
+#define PCIE_NTB_BAR45_SIZE           (0x800000)
+
+#define PCIE_IATU_END               {PCIE_IATU_OUTBOUND,0,0,0}
+#define PCIE_IATU_INBOUND_MASK      (0x80000000)
+#define PCIE_IATU_INDEX_MASK         (0x7f)
+#define PCIE_IATU_TYPE_MASK         (0x1f)
+#define PCIE_IATU_EN                     (0x1 << 0)
+#define PCIE_IATU_SHIFT_MODE             (0x1 << 1)
+#define PCIE_IATU_BAR_MODE               (0x1 << 2)
+#define PCIE_IATU_FUNC_MODE               (0x1 << 3)
+#define PCIE_IATU_AT_MODE                 (0x1 << 4)
+#define PCIE_IATU_ATTR_MODE               (0x1 << 5)
+#define PCIE_IATU_TD_MODE                 (0x1 << 6) //TD
+#define PCIE_IATU_TC_MODE                 (0x1 << 7) // TC
+#define PCIE_IATU_PREFETCH_MODE             (0x1 << 8)
+#define PCIE_IATU_DMA_BY_PASS_MODE          (0x1 << 9) //DMA bypass untranslate
+
+#define PCIE_BAR_MASK_SIZE          (0x800000)
+#define PCIE_BAR_TYPE_32            (0)
+#define PCIE_BAR_TYPE_64            (2)
+#define PCIE_BAR_PREFETCH_MODE      (1)
+
+#define RegWrite(addr,data)            (*(volatile UINT32*)(UINTN)(addr) = (data))
+#define RegRead(addr,data)             ((data) = *(volatile UINT32*)(UINTN)(addr))
+
+
+typedef struct tagPcieDebugInfo
+{
+    UINT32 pcie_rdma_start_cnt;
+    UINT32 pcie_wdma_start_cnt;
+    UINT64 pcie_wdma_transfer_len;
+    UINT64 pcie_rdma_transfer_len;
+    UINT32 pcie_rdma_fail_cnt;
+    UINT32 pcie_wdma_fail_cnt;
+}pcie_debug_info_s;
+
+
+#define bdf_2_b(bdf)    ((bdf >> 8) & 0xFF)
+#define bdf_2_d(bdf)    ((bdf >> 3) & 0x1F)
+#define bdf_2_f(bdf)    ((bdf >> 0) & 0x7)
+#define b_d_f_2_bdf(b,d,f)    (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0))
+
+
+
+typedef UINT32 (*pcie_dma_func_int)(UINT32  ulErrno, UINT32 ulReserved);
+
+
+typedef struct {
+     UINT32             ViewPort;            //iATU Viewport Register
+     UINT32             RegionCtrl1;         //Region Control 1 Register
+     UINT32             RegionCtrl2;         //Region Control 2 Register
+     UINT32             BaseLow;             //Lower Base Address Register
+     UINT32             BaseHigh;            //Upper Base Address Register
+     UINT32             Limit;               //Limit Address Register
+     UINT32             TargetLow;           //Lower Target Address Register
+     UINT32             TargetHigh;          //Upper Target Address Register
+} PCIE_IATU_VA;
+
+typedef enum {
+    PCIE_IATU_OUTBOUND    = 0x0,
+    PCIE_IATU_INBOUND     = 0x1,
+} PCIE_IATU_DIR;
+
+typedef struct {
+    PCIE_IATU_DIR       IatuType;
+    UINT64              IatuBase;
+    UINT64              IatuSize;
+    UINT64              IatuTarget;
+} PCIE_IATU;
+
+typedef struct {
+    UINT32              IatuType;
+    UINT64              IatuBase;
+    UINT32              IatuLimit;
+    UINT64              IatuTarget;
+    UINT32              Valid;
+} PCIE_IATU_HW;
+
+typedef struct {
+    UINT32              PortIndex;
+    PCIE_PORT_INFO      PortInfo;
+    PCIE_IATU_HW        OutBound[PCIE_MAX_OUTBOUND];
+    PCIE_IATU_HW        InBound[PCIE_MAX_INBOUND];
+} PCIE_DRIVER_CFG;
+
+typedef enum {
+    PCIE_CONFIG_REG     = 0x0,
+    PCIE_SYS_CONTROL    = 0x1,
+    PCIE_SLV_CONTENT_MODE = 0x2,
+} PCIE_RW_MODE;
+
+typedef union {
+    PCIE_DRIVER_CFG     PcieDevice;
+    PCIE_NTB_CFG        NtbDevice;
+} DRIVER_CFG_U;
+
+typedef struct {
+    VOID                *MappedOutbound[PCIE_MAX_OUTBOUND];
+    UINT32              OutboundType[PCIE_MAX_OUTBOUND];
+    UINT32              OutboundEn[PCIE_MAX_OUTBOUND];
+} PCIE_MAPPED_IATU_ADDR;
+
+typedef struct {
+    BOOLEAN             PortIsInitilized[PCIE_MAX_PORT_NUM];
+    DRIVER_CFG_U        Dev[PCIE_MAX_PORT_NUM];
+    VOID                *DmaResource[PCIE_MAX_PORT_NUM];
+    UINT32              DmaChannel[PCIE_MAX_PORT_NUM][2];
+    VOID                *RegResource[PCIE_MAX_PORT_NUM];
+    VOID                *CfgResource[PCIE_MAX_PORT_NUM];
+} PCIE_INIT_CFG;
+
+typedef enum {
+    PCIE_MMIO_IEP_CFG  = 0x1000,
+    PCIE_MMIO_IEP_CTRL = 0x0,
+    PCIE_MMIO_EEP_CFG  = 0x9000,
+    PCIE_MMIO_EEP_CTRL = 0x8000,
+} NTB_MMIO_MODE;
+
+typedef struct tagPcieDmaDes
+{
+    UINT32 uwChanCtrl;
+    UINT32 uwLen;
+    UINT32 uwLocalLow;
+    UINT32 uwLocalHigh;
+    UINT32 uwTagetLow;
+    UINT32 uwTagetHigh;
+}pcie_dma_des_s,*pcie_dma_des_ps;
+
+typedef enum {
+    PCIE_IATU_MEM,
+    PCIE_IATU_CFG = 0x4,
+    PCIE_IATU_IO
+} PCIE_IATU_OUT_TYPE;
+
+typedef enum {
+    PCIE_PAYLOAD_128B = 0,
+    PCIE_PAYLOAD_256B,
+    PCIE_PAYLOAD_512B,
+    PCIE_PAYLOAD_1024B,
+    PCIE_PAYLOAD_2048B,
+    PCIE_PAYLOAD_4096B,
+    PCIE_RESERVED_PAYLOAD
+} PCIE_PAYLOAD_SIZE;
+
+typedef struct tagPcieDfxInfo
+{
+    PCIE_EP_AER_CAP0_U aer_cap0;
+    PCIE_EP_AER_CAP1_U aer_cap1;
+    PCIE_EP_AER_CAP2_U aer_cap2;
+    PCIE_EP_AER_CAP3_U aer_cap3;
+    PCIE_EP_AER_CAP4_U aer_cap4;
+    PCIE_EP_AER_CAP5_U aer_cap5;
+    PCIE_EP_AER_CAP6_U aer_cap6;
+    UINT32 hdr_log0;
+    UINT32 hdr_log1;
+    UINT32 hdr_log2;
+    UINT32 hdr_log3;
+    PCIE_EP_AER_CAP11_U aer_cap11;
+    PCIE_EP_AER_CAP12_U aer_cap12;
+    PCIE_EP_AER_CAP13_U aer_cap13;
+
+    PCIE_EP_PORTLOGIC62_U port_logic62;
+    PCIE_EP_PORTLOGIC64_U port_logic64;
+    PCIE_EP_PORTLOGIC66_U port_logic66;
+    PCIE_EP_PORTLOGIC67_U port_logic67;
+    PCIE_EP_PORTLOGIC69_U port_logic69;
+    PCIE_EP_PORTLOGIC75_U port_logic75;
+    PCIE_EP_PORTLOGIC76_U port_logic76;
+    PCIE_EP_PORTLOGIC77_U port_logic77;
+    PCIE_EP_PORTLOGIC79_U port_logic79;
+    PCIE_EP_PORTLOGIC80_U port_logic80;
+    PCIE_EP_PORTLOGIC81_U port_logic81;
+    PCIE_EP_PORTLOGIC87_U port_logic87;
+
+    PCIE_CTRL_10_U  pcie_ctrl10;
+    UINT32 slve_rerr_addr_low;
+    UINT32 slve_rerr_addr_up;
+    UINT32 slve_werr_addr_low;
+    UINT32 slve_werr_addr_up;
+    UINT32 pcie_state4;
+    UINT32 pcie_state5;
+}PCIE_DFX_INFO_S;
+
+VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode);
+
+UINT32 PcieIsLinkDown(UINT32 Port);
+
+BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port);
+
+EFI_STATUS PcieWaitLinkUp(UINT32 Port);
+
+EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h
new file mode 100644
index 0000000..d1ba1c8
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h
@@ -0,0 +1,346 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCIE_KERNEL_API_H__
+#define __PCIE_KERNEL_API_H__
+
+#define PCIE_HOST_BRIDGE_NUM            (1)
+#define PCIE_MAX_PORT_NUM               (4)
+#define PCIE_MAX_OUTBOUND               (6)
+#define PCIE_MAX_INBOUND               (4)
+#define PCIE3_MAX_OUTBOUND               (16)
+#define PCIE3_MAX_INBOUND                (16)
+
+#define PCIE_LINK_LOOP_CNT          (0x1000)
+#define PCIE_IATU_ADDR_MASK         (0xFFFFF000)
+#define PCIE_1M_ALIGN_SHIRFT        (20)
+#define PCIE_BDF_MASK               (0xF0000FFF)
+#define PCIE_BUS_SHIRFT             (20)
+#define PCIE_DEV_SHIRFT             (15)
+#define PCIE_FUNC_SHIRFT            (12)
+
+#define PCIE_DBI_CS2_ENABLE              (0x1)
+#define PCIE_DBI_CS2_DISABLE             (0x0)
+
+#define PCIE_DMA_CHANLE_READ             (0x1)
+#define PCIE_DMA_CHANLE_WRITE             (0x0)
+
+
+#define PCIE_ERR_IATU_TABLE_NULL            EFIERR (1)
+#define PCIE_ERR_LINK_OVER_TIME             EFIERR (2)
+#define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE      EFIERR (3)
+#define PCIE_ERR_ALREADY_INIT               EFIERR (4)
+#define PCIE_ERR_PARAM_INVALID              EFIERR (5)
+#define PCIE_ERR_MEM_OPT_OVER               EFIERR (6)
+#define PCIE_ERR_NOT_INIT                   EFIERR (7)
+#define PCIE_ERR_CFG_OPT_OVER               EFIERR (8)
+#define PCIE_ERR_DMA_READ_CHANLE_BUSY       EFIERR (9)
+#define PCIE_ERR_DMA_WRITE_CHANLE_BUSY      EFIERR (10)
+#define PCIE_ERR_DMAR_NO_RESORCE            EFIERR (11)
+#define PCIE_ERR_DMAW_NO_RESORCE            EFIERR (12)
+#define PCIE_ERR_DMA_OVER_MAX_RESORCE       EFIERR (13)
+#define PCIE_ERR_NO_IATU_WINDOW             EFIERR (14)
+#define PCIE_ERR_DMA_TRANSPORT_OVER_TIME    EFIERR (15)
+#define PCIE_ERR_DMA_MEM_ALLOC_ERROR        EFIERR (16)
+#define PCIE_ERR_DMA_ABORT                  EFIERR (17)
+#define PCIE_ERR_UNSUPPORT_BAR_TYPE         EFIERR (18)
+
+typedef enum {
+    PCIE_ROOT_COMPLEX,
+    PCIE_END_POINT,
+    PCIE_NTB_TO_NTB,
+    PCIE_NTB_TO_RP,
+} PCIE_PORT_TYPE;
+
+typedef enum {
+    PCIE_GEN1_0 = 1,    //PCIE 1.0
+    PCIE_GEN2_0 = 2,    //PCIE 2.0
+    PCIE_GEN3_0 = 4     //PCIE 3.0
+} PCIE_PORT_GEN;
+
+typedef enum {
+    PCIE_WITDH_X1 = 0x1,
+    PCIE_WITDH_X2 = 0x3,
+    PCIE_WITDH_X4 = 0x7,
+    PCIE_WITDH_X8 = 0xf,
+    PCIE_WITDH_INVALID
+} PCIE_PORT_WIDTH;
+
+
+typedef struct {
+    PCIE_PORT_TYPE      PortType;
+    PCIE_PORT_WIDTH     PortWidth;
+    PCIE_PORT_GEN       PortGen;
+    UINT8               PcieLinkUp;
+} PCIE_PORT_INFO;
+
+typedef struct tagPciecfg_params
+{
+    UINT32 preemphasis;
+    UINT32 deemphasis;
+    UINT32 swing;
+    UINT32 balance;
+}pcie_cfg_params_s;
+
+typedef enum {
+    PCIE_CORRECTABLE_ERROR = 0,
+    PCIE_NON_FATAL_ERROR,
+    PCIE_FATAL_ERROR,
+    PCIE_UNSUPPORTED_REQUEST_ERROR,
+    PCIE_ALL_ERROR
+} PCIE_ERROR_TYPE;
+
+typedef union tagPcieDeviceStatus
+{
+       struct
+        {
+            UINT16 correctable_error : 1;
+            UINT16 non_fatal_error : 1;
+            UINT16 fatal_error : 1;
+            UINT16 unsupported_error : 1;
+            UINT16 aux_power : 1;
+            UINT16 transaction_pending : 1;
+            UINT16 reserved_6_15 : 10;
+       }Bits;
+
+    UINT16 Value;
+}pcie_device_status_u;
+
+
+typedef union tagPcieUcAerStatus
+{
+      struct
+        {
+            UINT32    undefined   : 1   ; /* [0] undefined  */
+            UINT32    reserved_1_3   : 3   ; /* reserved */
+            UINT32    data_link_proto_error   : 1   ; /* Data Link Protocol Error Status */
+            UINT32    reserved_5_11   : 7   ; /* reserved */
+            UINT32    poisoned_tlp_status   : 1   ; /* Poisoned TLP Status */
+            UINT32    flow_control_proto_error   : 1   ; /* Flow Control Protocol Error Status */
+            UINT32    completion_time_out   : 1   ; /* Completion Timeout Status */
+            UINT32    compler_abort_status   : 1   ; /* Completer Abort Status */
+            UINT32    unexpect_completion_status   : 1   ; /* Unexpected Completion Status */
+            UINT32    receiver_overflow_status   : 1   ; /*Receiver Overflow Status */
+            UINT32    malformed_tlp_status   : 1   ; /* Malformed TLP Status*/
+            UINT32    ecrc_error_status   : 1   ; /* ECRC Error Status */
+            UINT32    unsupport_request_error_status   : 1   ; /* Unsupported Request Error Status */
+            UINT32    reserved_21   : 1   ; /*  reserved */
+            UINT32    uncorrectable_interal_error   : 1   ; /* Uncorrectable Internal Error Status */
+            UINT32    reserved_23   : 1   ; /* reserved*/
+            UINT32    atomicop_egress_blocked_status   : 1   ; /* AtomicOp Egress Blocked Status */
+            UINT32    tlp_prefix_blocked_error_status   : 1   ; /* TLP Prefix Blocked Error Status */
+            UINT32    reserved_26_31   : 1   ; /* reserved */
+       }Bits;
+
+       UINT32 Value;
+}pcie_uc_aer_status_u;
+
+typedef union tagPcieCoAerStatus
+{
+       struct
+        {
+            UINT32    receiver_error_status   : 1   ; /* Receiver Error Status  */
+            UINT32    reserved_1_5   : 5   ; /* Reserved */
+            UINT32    bad_tlp_status   : 1   ; /* Bad TLP Status */
+            UINT32    bad_dllp_status   : 1   ; /* Bad DLLP Status */
+            UINT32    reply_num_rollover_status   : 1   ; /* REPLAY_NUM Rollover Status*/
+            UINT32    reserved_9_11   : 3   ; /* Reserved */
+            UINT32    reply_timer_timeout   : 1   ; /* Replay Timer Timeout Status */
+            UINT32    advisory_nonfatal_error   : 1   ; /* Advisory Non-Fatal Error Status*/
+            UINT32    corrected_internal_error   : 1   ; /*Corrected Internal Error Status*/
+            UINT32    reserved_15_31   : 1   ; /* Reserved */
+       }Bits;
+       UINT32 Value;
+}pcie_co_aer_status_u;
+
+typedef struct tagPcieAerStatus
+{
+    pcie_uc_aer_status_u uc_aer_status;
+    pcie_co_aer_status_u co_aer_status;
+}pcie_aer_status_s;
+
+
+
+typedef struct tagPcieLoopTestResult
+{
+   UINT32 tx_pkts_cnt;
+   UINT32 rx_pkts_cnt;
+   UINT32 error_pkts_cnt;
+   UINT32 droped_pkts_cnt;
+   UINT32 push_cnt;
+   pcie_device_status_u device_status;
+   pcie_aer_status_s    pcie_aer_status;
+} pcie_loop_test_result_s;
+
+typedef struct tagPcieDmaChannelAttrs {
+    UINT32 dma_chan_en;
+    UINT32 dma_mode;
+    UINT32 channel_status;
+}pcie_dma_channel_attrs_s;
+
+typedef enum tagPcieDmaChannelStatus
+{
+    PCIE_DMA_CS_RESERVED = 0,
+    PCIE_DMA_CS_RUNNING = 1,
+    PCIE_DMA_CS_HALTED = 2,
+    PCIE_DMA_CS_STOPPED = 3
+}pcie_dma_channel_status_e;
+
+typedef enum tagPcieDmaIntType{
+    PCIE_DMA_INT_TYPE_DONE=0,
+    PCIE_DMA_INT_TYPE_ABORT,
+    PCIE_DMA_INT_ALL,
+    PCIE_DMA_INT_NONE
+}pcie_dma_int_type_e;
+
+typedef enum tagPcieMulWinSize
+{
+    WIN_SIZE_4K = 0xc,
+    WIN_SIZE_8K,
+    WIN_SIZE_16K,
+    WIN_SIZE_32K,
+    WIN_SIZE_64K,
+    WIN_SIZE_128K,
+    WIN_SIZE_256K,
+    WIN_SIZE_512K,
+    WIN_SIZE_1M,
+    WIN_SIZE_2M,
+    WIN_SIZE_4M,
+    WIN_SIZE_8M,
+    WIN_SIZE_16M,
+    WIN_SIZE_32M,
+    WIN_SIZE_64M,
+    WIN_SIZE_128M,
+    WIN_SIZE_256M,
+    WIN_SIZE_512M,
+    WIN_SIZE_1G,
+    WIN_SIZE_2G,
+    WIN_SIZE_4G,
+    WIN_SIZE_8G,
+    WIN_SIZE_16G,
+    WIN_SIZE_32G,
+    WIN_SIZE_64G,
+    WIN_SIZE_128G,
+    WIN_SIZE_256G,
+    WIN_SIZE_512G = 0x27,
+}pcie_mul_win_size_e;
+
+typedef struct tagPcieMultiCastCfg
+{
+    UINT64 multicast_base_addr;
+    pcie_mul_win_size_e base_addr_size;
+    UINT64 base_translate_addr;
+}pcie_multicast_cfg_s;
+
+typedef enum tagPcieMode
+{
+    PCIE_EP_DEVICE = 0x0,
+    LEGACY_PCIE_EP_DEVICE = 0x1,
+    RP_OF_PCIE_RC = 0x4,
+    PCIE_INVALID = 0x100
+}pcie_mode_e;
+
+typedef struct{
+    UINT32              PortIndex;
+    PCIE_PORT_INFO      PortInfo;
+    UINT64              iep_bar01; /*iep bar 01*/
+    UINT64              iep_bar23;
+    UINT64              iep_bar45;
+    UINT64              iep_bar01_xlat;
+    UINT64              iep_bar23_xlat;
+    UINT64              iep_bar45_xlat;
+    UINT64              iep_bar_lmt23;
+    UINT64              iep_bar_lmt45; /*bar limit*/
+    UINT64              eep_bar01;
+    UINT64              eep_bar23;
+    UINT64              eep_bar45;
+    UINT64              eep_bar23_xlat;
+    UINT64              eep_bar45_xlat;
+    UINT64              eep_bar_lmt23; /*bar limit*/
+    UINT64              eep_bar_lmt45; /*bar limit*/
+} PCIE_NTB_CFG;
+
+extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info);
+
+extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl);
+
+extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed);
+
+extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params);
+
+
+extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control);
+
+extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute);
+
+extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status);
+
+extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type);
+
+extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel);
+
+
+extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status);
+
+extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type);
+
+
+extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size);
+
+extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num);
+
+extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg);
+
+extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell);
+
+extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type);
+
+extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result);
+extern int pcie_port_reset(UINT32 Port);
+
+extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error);
+
+extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \
+pcie_device_status_u *pcie_stat);
+extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
+
+extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status);
+extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
+
+extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type);
+
+
+extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length);
+
+extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length);
+
+extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length);
+
+extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length);
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.c b/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.c
new file mode 100644
index 0000000..055cc37
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.c
@@ -0,0 +1,114 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/PlatformSasProtocol.h>
+
+#define SAS0_BASE                   0xc0000000
+#define SAS0_RESET                  0xa60
+#define SAS0_DISABLE_CLK            0x33c
+#define SAS0_DERESET                0xa64
+#define SAS0_ENABLE_CLK             0x338
+
+#define SAS1_BASE                   0xb0000000
+#define SAS1_RESET                  0xa18
+#define SAS1_DISABLE_CLK            0x31c
+#define SAS1_DERESET                0xa1c
+#define SAS1_ENABLE_CLK             0x318
+
+#define SAS_RESET_VALUE             0x7ffff
+
+STATIC
+VOID
+SasInit_0 (
+    IN PLATFORM_SAS_PROTOCOL   *This
+)
+{
+  // Apply reset and disable clock
+  MmioWrite32(SAS0_BASE + SAS0_RESET, SAS_RESET_VALUE);
+  MmioWrite32(SAS0_BASE + SAS0_DISABLE_CLK, SAS_RESET_VALUE);
+  // Wait 1ms for reset takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+  MicroSecondDelay(1000);
+  // De-reset and enable clock
+  MmioWrite32(SAS0_BASE + SAS0_DERESET, SAS_RESET_VALUE);
+  MmioWrite32(SAS0_BASE + SAS0_ENABLE_CLK, SAS_RESET_VALUE);
+  // Wait 1ms for de-reset takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+  MicroSecondDelay(1000);
+}
+
+PLATFORM_SAS_PROTOCOL Sas0 = {
+  0xc1000000,
+  SasInit_0
+};
+
+STATIC
+VOID
+SasInit_1 (
+    IN PLATFORM_SAS_PROTOCOL   *This
+)
+{
+  // Apply reset and disable clock
+  MmioWrite32(SAS1_BASE + SAS1_RESET, SAS_RESET_VALUE);
+  MmioWrite32(SAS1_BASE + SAS1_DISABLE_CLK, SAS_RESET_VALUE);
+  // Wait 1ms for reset takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+  MicroSecondDelay(1000);
+  // De-reset and enable clock
+  MmioWrite32(SAS1_BASE + SAS1_DERESET, SAS_RESET_VALUE);
+  MmioWrite32(SAS1_BASE + SAS1_ENABLE_CLK, SAS_RESET_VALUE);
+  // Wait 1ms for de-reset takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+  MicroSecondDelay(1000);
+}
+
+PLATFORM_SAS_PROTOCOL Sas1 = {
+  0xb1000000,
+  SasInit_1
+};
+
+EFI_STATUS
+EFIAPI
+SasV1InitEntry (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_HANDLE  Handle;
+  EFI_STATUS  Status;
+
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces(
+                  &Handle,
+                  &gPlatformSasProtocolGuid, &Sas0,
+                  NULL
+                 );
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces(
+                  &Handle,
+                  &gPlatformSasProtocolGuid, &Sas1,
+                  NULL
+                 );
+  return Status;
+}
diff --git a/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf b/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf
new file mode 100644
index 0000000..484e54f
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf
@@ -0,0 +1,48 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SasV1InitDxe
+  FILE_GUID                      = 6e673d64-4801-4cbd-a7c0-20a26a9d5919
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = SasV1InitEntry
+
+[Sources.common]
+  SasV1Init.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  IoLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Pcd]
+
+[Protocols]
+  gPlatformSasProtocolGuid
+
+[Depex]
+  TRUE
diff --git a/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c
new file mode 100644
index 0000000..90adc25
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c
@@ -0,0 +1,119 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Uefi.h>
+#include <Pi/PiDxeCis.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/PrintLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Protocol/AcpiTable.h>
+#include <IndustryStandard/Acpi.h>
+#include <Uefi/UefiSpec.h>
+#include <Guid/Acpi.h>
+#include "UnInstallAcpiTable.h"
+
+#define EFI_ACPI_MAX_NUM_TABLES         20
+EFI_GUID  gSataControlGuid = EFI_SATA_CONTROL_GUID;
+
+EFI_STATUS
+UnInstallSsdtTable (
+ IN EFI_HANDLE         ImageHandle,
+ IN EFI_SYSTEM_TABLE  *SystemTable)
+{
+  EFI_STATUS              Status;
+  EFI_ACPI_SDT_PROTOCOL   *AcpiTableProtocol;
+  EFI_ACPI_SDT_HEADER     *Table;
+  EFI_ACPI_TABLE_VERSION  TableVersion;
+  UINTN                   TableKey;
+  UINTN                   i;
+  EFI_ACPI_TABLE_PROTOCOL               *AcpiTable;
+  UINT8                   DataPtr1 = 2;
+  UINTN                   DataPtr1Size;
+  UINT32                  SsdtName;
+
+  DataPtr1Size = sizeof(DataPtr1);
+
+  Status = gRT->GetVariable (
+                          SATA_ENABLE_FLAG,
+                          &gSataControlGuid,
+                          NULL,
+                          &DataPtr1Size,
+                          &DataPtr1
+                          );
+  if (!EFI_ERROR (Status)) {
+     DEBUG((EFI_D_ERROR,"Get Variable ok\n"));
+
+  }
+
+  if (SATAENABLE == DataPtr1) {
+    Status = gBS->InstallProtocolInterface (
+                   &ImageHandle,
+                   &gSataEnableFlagProtocolGuid,
+                   EFI_NATIVE_INTERFACE,
+                   NULL
+                   );
+    if (!EFI_ERROR (Status)) {
+      DEBUG((EFI_D_ERROR,"Install SataEnableFlag Protocol ok, %r\n",Status));
+
+    }
+    DEBUG((EFI_D_ERROR, "Current SataEnable Flag is Sata, try to uninstall Sas SSDT table\n"));
+    SsdtName = EFI_SAS_SIGNATURE;
+  }
+  else {
+    DEBUG((EFI_D_ERROR, "Current SataEnable Flag is Sas, try to uninstall Sata SSDT table\n"));
+    SsdtName = EFI_SATA_SIGNATURE;
+  }
+
+  //Locate AcpiTableProtocol
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+  if (EFI_ERROR (Status)) {
+     DEBUG((EFI_D_ERROR,"Unable to locate ACPI table protocol\n"));
+    return EFI_ABORTED;
+  }
+  //
+  // Find the Acpi Sdt protocol
+  Status = gBS->LocateProtocol(&gEfiAcpiSdtProtocolGuid, NULL, (VOID**) &AcpiTableProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG((EFI_D_ERROR,"Unable to locate ACPI Sdt protocol\n"));
+    return EFI_ABORTED;
+  }
+
+  //
+  // Search for SSDT Table and delete the matched SSDT table
+  for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) {
+    Status = AcpiTableProtocol->GetAcpiTable(i, &Table, &TableVersion, &TableKey);
+    if (EFI_ERROR(Status))
+      break;
+    if (Table->Signature == EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
+
+       if(*(UINT64*)Table->OemTableId == SsdtName) {
+          Status = AcpiTable->UninstallAcpiTable (AcpiTable, TableKey);
+          if (!EFI_ERROR (Status)) {
+            DEBUG((EFI_D_ERROR,"Successfully remove the SSDT table\n"));
+            return EFI_SUCCESS;
+          }
+       }
+    }
+
+  }
+  return EFI_SUCCESS;
+
+}
+
+
diff --git a/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h
new file mode 100644
index 0000000..67e89e4
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h
@@ -0,0 +1,30 @@
+/*
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#ifndef _EFI_UNINSTALL_ACPI_H_
+#define _EFI_UNINSTALL_ACPI_H_
+
+#define EFI_SATA_CONTROL_GUID \
+  { \
+    0x287e41a8, 0x5108, 0x4faf, { 0xbe, 0x3d, 0xd4, 0xdd, 0xff, 0xcd, 0x4e, 0x9f } \
+  }
+
+#define SATA_ENABLE_FLAG       (L"SataEnableFlag")
+#define EFI_SAS_SIGNATURE SIGNATURE_32 ('S', 'A', 'S', '0')
+#define EFI_SATA_SIGNATURE SIGNATURE_32 ('S', 'A', 'T', 'A')
+#define SATAENABLE 1
+#define SATADISABLE 0
+
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf
new file mode 100644
index 0000000..f83dd28
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf
@@ -0,0 +1,57 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = UnInstallSsdt
+  FILE_GUID                      = E39977F0-20A4-4551-B0ED-BCE246592E78
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = UnInstallSsdtTable
+
+[Sources.common]
+  UnInstallAcpiTable.c
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+  BaseLib
+  DxeServicesTableLib
+
+[Guids]
+ gEfiAcpiTableGuid
+ gEfiAcpi20TableGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid
+ gEfiAcpiSdtProtocolGuid
+ gSataEnableFlagProtocolGuid
+
+[Pcd]
+
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiVariableArchProtocolGuid
+
+
diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h
new file mode 100644
index 0000000..64c7b42
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h
@@ -0,0 +1,120 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_
+
+
+typedef enum {
+  EmHilink0Pcie1X8 = 0,
+  EmHilink0Pcie1X4Pcie2X4 = 1,
+} HILINK0_MODE_TYPE;
+
+typedef enum {
+  EmHilink1Pcie0X8 = 0,
+  EmHilink1HccsX8 = 1,
+} HILINK1_MODE_TYPE;
+
+typedef enum {
+  EmHilink2Pcie2X8 = 0,
+  EmHilink2Sas0X8 = 1,
+} HILINK2_MODE_TYPE;
+
+typedef enum {
+  EmHilink3GeX4 = 0,
+  EmHilink3GeX2XgeX2 = 1, //lane0,lane1-ge,lane2,lane3 xge
+} HILINK3_MODE_TYPE;
+
+
+typedef enum {
+  EmHilink4GeX4 = 0,
+  EmHilink4XgeX4 = 1,
+} HILINK4_MODE_TYPE;
+
+typedef enum {
+  EmHilink5Sas1X4 = 0,
+  EmHilink5Pcie3X4 = 1,
+} HILINK5_MODE_TYPE;
+
+
+typedef struct {
+  HILINK0_MODE_TYPE Hilink0Mode;
+  HILINK1_MODE_TYPE Hilink1Mode;
+  HILINK2_MODE_TYPE Hilink2Mode;
+  HILINK3_MODE_TYPE Hilink3Mode;
+  HILINK4_MODE_TYPE Hilink4Mode;
+  HILINK5_MODE_TYPE Hilink5Mode;
+} SERDES_PARAM;
+
+
+#define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
+#define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
+
+typedef struct {
+    UINT32 MacroId;
+    UINT32 DsNum;
+} SERDES_POLARITY_INVERT;
+
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
+extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
+extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
+UINT32 GetEthType(UINT8 EthChannel);
+
+EFI_STATUS
+EfiSerdesInitWrap (VOID);
+
+void serdes_state_show(UINT32 macro1);
+//uniBIOS__l00228991_start DTS2015042210118 2015-4-22 20:06:34
+
+void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg);
+//uniBIOS__l00228991_end DTS2015042210118 2015-4-22 20:06:34
+
+//uniBIOS_l00306713_000_start 2015-3-19 17:37:06
+
+//EYE test
+UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData);
+
+UINT32 Serdes_ReadBert(UINT32   ulMacroId , UINT32   ulDsNum);
+
+//PRBS test
+int serdes_prbs_test(UINT8   ulMacroId , UINT8   ulDsNum,UINT8 PrbsType);
+
+int serdes_prbs_test_cancle(UINT8  ulMacroId,UINT8 ulDsNum);
+
+//CTLE/DFE
+void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane);
+
+void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane);
+
+void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane);
+
+void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane);
+
+void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane);
+//uniBIOS_l00306713_000_end   2015-3-19 17:37:06
+
+
+//uniBIOS_l00306713_000_start 2015-7-15 9:13:55
+
+int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+
+int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+
+int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
+//uniBIOS_l00306713_000_end   2015-7-15 9:13:55
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf b/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000..1096175
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf
@@ -0,0 +1,60 @@
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Pv660AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  Dsdt/Dsdt.asl
+  Facs.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  Madt.aslc
+  Mcfg.aslc
+  Iort.asl
+  Spcr.aslc
+  Dbg2.aslc
+  SASSSDT.ASL
+  SATASSDT.ASL
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc
new file mode 100644
index 0000000..93b2c90
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc
@@ -0,0 +1,94 @@
+/** @file
+*  Debug Port Table 2 (DBG2)
+*
+*  Copyright (c) 2012 - 2014, Linaro Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Pv660Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+
+#define NUMBER_DEBUG_DEVICE_INFO    1
+#define NUMBER_OF_GENERIC_ADDRESS   1
+#define NAMESPACE_STRING_SIZE       8
+
+#pragma pack(1)
+
+typedef struct {
+  EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS];
+  UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];
+  CHAR8  NamespaceString[NAMESPACE_STRING_SIZE];
+} EFI_ACPI_DBG2_DDI_STRUCT;
+
+typedef struct {
+  EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;
+  EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];
+} EFI_ACPI_DEBUG_PORT_2_TABLE;
+
+#pragma pack()
+
+EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = {
+  {
+    ARM_ACPI_HEADER(
+      EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE,
+      EFI_ACPI_DEBUG_PORT_2_TABLE,
+      EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION
+      ),
+    OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),
+    NUMBER_DEBUG_DEVICE_INFO
+  },
+  {
+    {
+      {
+        EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+        sizeof(EFI_ACPI_DBG2_DDI_STRUCT),
+        NUMBER_OF_GENERIC_ADDRESS,
+        NAMESPACE_STRING_SIZE,
+        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),
+        0,  //OemDataLength
+        0,  //OemDataOffset
+        EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+        EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550,
+        {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address),
+        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),
+      },
+      {
+        {
+          EFI_ACPI_6_0_SYSTEM_MEMORY,
+          32,
+          0,
+          EFI_ACPI_6_0_BYTE,
+          FixedPcdGet64(PcdSerialRegisterBase)
+        }
+      },
+      {
+        0x1000
+      },
+      "COM0"
+    }
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Dbg2;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl
new file mode 100644
index 0000000..e995295
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl
@@ -0,0 +1,88 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+    //
+    // A57x16 Processor declaration
+    //
+    Device(CPU0) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 0)
+    }
+    Device(CPU1) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 1)
+    }
+    Device(CPU2) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 2)
+    }
+    Device(CPU3) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 3)
+    }
+    Device(CPU4) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 4)
+    }
+    Device(CPU5) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 5)
+    }
+    Device(CPU6) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 6)
+    }
+    Device(CPU7) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 7)
+    }
+    Device(CPU8) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 8)
+    }
+    Device(CPU9) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 9)
+    }
+    Device(CP10) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 10)
+    }
+    Device(CP11) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 11)
+    }
+    Device(CP12) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 12)
+    }
+    Device(CP13) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 13)
+    }
+    Device(CP14) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 14)
+    }
+    Device(CP15) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 15)
+    }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
new file mode 100644
index 0000000..e3fc0d3
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
@@ -0,0 +1,38 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+  Device(COM0) {
+    Name(_HID, "HISI0031") //it is not 16550 compatible
+    Name(_CID, "8250dw")
+    Name(_UID, Zero)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x80300000, 0x1000)
+      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"clock-frequency", 200000000},
+        Package () {"reg-io-width", 4},
+        Package () {"reg-shift", 2},
+      }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl
new file mode 100644
index 0000000..5188060
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl
@@ -0,0 +1,38 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  // sysctl dsa
+  Device(CTL0) {
+    Name(_HID, "HISI0061")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xC0000000, 0x10000)
+    })
+  }
+  // sysctl pcie
+  Device(CTL1) {
+    Name(_HID, "HISI0061")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xB0000000, 0x10000)
+    })
+  }
+  // sysctl peri_c
+  Device(CTL2) {
+    Name(_HID, "HISI0061")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x80000000, 0x10000)
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl
new file mode 100644
index 0000000..c0cc6d2
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl
@@ -0,0 +1,29 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Pv660Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI  ", "HIP05   ", EFI_ACPI_ARM_OEM_REVISION) {
+  include ("Mbig.asl")
+  include ("CPU.asl")
+  include ("Com.asl")
+  include ("Usb.asl")
+  include ("Ctl.asl")
+  include ("Hns.asl")
+  include ("Pci.asl")
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl
new file mode 100644
index 0000000..881aa14
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl
@@ -0,0 +1,956 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  Device (MDIO)
+  {
+      OperationRegion(CLKR, SystemMemory, 0x80000338, 8)
+    Field(CLKR, DWordAcc, NoLock, Preserve) {
+      CLKE, 1,  // clock enable
+      , 31,
+      CLKD, 1,  // clode disable
+      , 31,
+    }
+      OperationRegion(RSTR, SystemMemory, 0x80000A38, 8)
+    Field(RSTR, DWordAcc, NoLock, Preserve) {
+      RSTE, 1,  // reset
+      , 31,
+      RSTD, 1,  // de-reset
+      , 31,
+    }
+
+    Name(_HID, "HISI0141")
+    Name (_CRS, ResourceTemplate (){
+      Memory32Fixed (ReadWrite, 0x803c0000 , 0x10000)
+            })
+
+    Method(_RST, 0, Serialized) {
+      Store (0x1, RSTE)
+      Sleep (10)
+      Store (0x1, CLKD)
+      Sleep (10)
+      Store (0x1, RSTD)
+      Sleep (10)
+      Store (0x1, CLKE)
+      Sleep (10)
+    }
+  }
+
+  Device (DSF0)
+  {
+    OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+    Field(H3SR, DWordAcc, NoLock, Preserve) {
+          H3ST, 1,
+          , 31,  //RESERVED
+        }
+    OperationRegion(H4SR, SystemMemory, 0xC0000190, 4)
+    Field(H4SR, DWordAcc, NoLock, Preserve) {
+          H4ST, 1,
+          , 31,  //RESERVED
+        }
+    // DSAF RESET
+    OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
+    Field(DRER, DWordAcc, NoLock, Preserve) {
+          DRTE, 1,
+          , 31,  //RESERVED
+          DRTD, 1,
+          , 31,  //RESERVED
+        }
+    // NT RESET
+    OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
+    Field(NRER, DWordAcc, NoLock, Preserve) {
+          NRTE, 1,
+          , 31,  //RESERVED
+          NRTD, 1,
+          , 31,  //RESERVED
+        }
+    // XGE RESET
+    OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+    Field(XRER, DWordAcc, NoLock, Preserve) {
+          XRTE, 31,
+          , 1,    //RESERVED
+          XRTD, 31,
+          , 1,    //RESERVED
+        }
+
+    // GE RESET
+    OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+    Field(GRTR, DWordAcc, NoLock, Preserve) {
+          GR0E, 30,
+          , 2,    //RESERVED
+          GR0D, 30,
+          , 2,    //RESERVED
+          GR1E, 18,
+          , 14,  //RESERVED
+          GR1D, 18,
+          , 14,  //RESERVED
+        }
+    // PPE RESET
+    OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+    Field(PRTR, DWordAcc, NoLock, Preserve) {
+          PRTE, 10,
+          , 22,  //RESERVED
+          PRTD, 10,
+          , 22,  //RESERVED
+        }
+
+    // RCB PPE COM RESET
+    OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
+    Field(RRTR, DWordAcc, NoLock, Preserve) {
+          RRTE, 1,
+          , 31,  //RESERVED
+          RRTD, 1,
+          , 31,  //RESERVED
+        }
+
+    // ROCE
+
+    // CPLD LED
+
+    // Serdes
+    OperationRegion(H4LR, SystemMemory, 0xC2288100, 0x1000)
+    Field(H4LR, DWordAcc, NoLock, Preserve) {
+          H4L0, 16,    // port0
+          H4R0, 16,    //RESERVED
+          Offset (0x400),
+          H4L1, 16,    // port1
+          H4R1, 16,    //RESERVED
+          Offset (0x800),
+          H4L2, 16,    // port2
+          H4R2, 16,    //RESERVED
+          Offset (0xc00),
+          H4L3, 16,    // port3
+          H4R3, 16,    //RESERVED
+        }
+    OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
+    Field(H3LR, DWordAcc, NoLock, Preserve) {
+          H3L2, 16,    // port4
+          , 16,    //RESERVED
+          Offset (0x400),
+          H3L3, 16,    // port5
+          , 16,    //RESERVED
+        }
+    Name (_HID, "HISI00B1")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_CRS, ResourceTemplate (){
+      Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
+                        Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+        {
+          149,150,151,152,153,154,26,27,155,156,157,158,159,160,  //[14] ge fifo err 8 / xge 6
+          6,7,8,9,16,17,18,19,22,23,24,25,      //[12] rcb com 4*3
+          0,1,2,3,4,5,12,13,          //[8] ppe tnl 0-7
+          128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,  //[21] dsaf event int 3+18
+          161,162,163,164,
+        }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+        {
+          384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399,  //[256] sevice rcb 2*128
+          400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415,
+          416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431,
+          432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447,
+          448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463,
+          464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479,
+          480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495,
+          496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511,
+          512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527,
+          528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543,
+          544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559,
+          560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575,
+        }
+                })
+                Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+                                Package () {"mode", "6port-16rss"},
+                                Package () {"buf-size", 4096},
+                                Package () {"desc-num", 1024},
+        Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+                        }
+                })
+
+    //reset XGE port
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XRST, 2, Serialized) {
+      ShiftLeft (0x2082082, Arg0, Local0)
+      Or (Local0, 0x1, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset XGE core
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XCRT, 2, Serialized) {
+      ShiftLeft (0x2080, Arg0, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset GE port
+    //Arg0 : GE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(GRST, 2, Serialized) {
+      If (LLessEqual (Arg0, 5)) {
+        //Service port
+        ShiftLeft (0x1041041, Arg0, Local0)
+        ShiftLeft (0x1, Arg0, Local1)
+
+        If (LEqual (Arg1, 0)) {
+          Store(Local1, GR1E)
+          Store(Local0, GR0E)
+        } Else  {
+          Store(Local0, GR0D)
+          Store(Local1, GR1D)
+        }
+      }
+    }
+
+    //reset PPE port
+    //Arg0 : PPE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(PRST, 2, Serialized) {
+      ShiftLeft (0x1, Arg0, Local0)
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, PRTE)
+      } Else  {
+        Store(Local0, PRTD)
+      }
+    }
+
+    // Set Serdes Loopback
+    //Arg0 : port
+    //Arg1 : 0 disable, 1 enable
+    Method(SRLP, 2, Serialized) {
+      ShiftLeft (Arg1, 10, Local0)
+      Switch (ToInteger(Arg0))
+      {
+        case (0x0){
+          Store (H4L0, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L0)
+        }
+        case (0x1){
+          Store (H4L1, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L1)
+        }
+        case (0x2){
+          Store (H4L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L2)
+        }
+        case (0x3){
+          Store (H4L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L3)
+        }
+        case (0x4){
+          Store (H3L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L2)
+        }
+        case (0x5){
+          Store (H3L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L3)
+        }
+      }
+    }
+
+    //Reset
+    //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
+    //Arg1 : port
+    //Arg2 : 0 disable, 1 enable
+    Method(DRST, 3, Serialized)
+    {
+      Switch (ToInteger(Arg0))
+      {
+        //DSAF reset
+        case (0x1)
+        {
+          Store (Arg2, Local0)
+          If (LEqual (Local0, 0))
+          {
+            Store (0x1, DRTE)
+            Store (0x1, NRTE)
+            Sleep (10)
+            Store (0x1, RRTE)
+          }
+          Else
+          {
+            Store (0x1, DRTD)
+            Store (0x1, NRTD)
+            Sleep (10)
+            Store (0x1, RRTD)
+          }
+        }
+        //Reset PPE port
+        case (0x2)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          PRST (Local0, Local1)
+        }
+
+        //Reset XGE core
+        case (0x3)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XCRT (Local0, Local1)
+        }
+        //Reset XGE port
+        case (0x4)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XRST (Local0, Local1)
+        }
+
+        //Reset GE port
+        case (0x5)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          GRST (Local0, Local1)
+        }
+      }
+    }
+
+    // _DSM Device Specific Method
+    //
+    // Arg0: UUID Unique function identifier
+    // Arg1: Integer Revision Level
+    // Arg2: Integer Function Index
+    //   0 : Return Supported Functions bit mask
+    //   1 : Reset Sequence
+    //    Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
+    //    Arg3[1] : port index in dsaf
+    //    Arg3[2] : 0 reset, 1 cancle reset
+    //   2 : Set Serdes Loopback
+    //    Arg3[0] : port
+    //    Arg3[1] : 0 disable, 1 enable
+    //   3 : LED op set
+    //    Arg3[0] : op type
+    //    Arg3[1] : port
+    //    Arg3[2] : para
+    //   4 : Get port type (GE or XGE)
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 GE, 1 XGE
+    //   5 : Get sfp status
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 no sfp, 1 have sfp
+    // Arg3: Package Parameters
+    Method (_DSM, 4, Serialized)
+    {
+      If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+      {
+        If (LEqual (Arg1, 0x00))
+        {
+          Switch (ToInteger(Arg2))
+          {
+            case (0x0)
+            {
+              Return (Buffer () {0x3F})
+            }
+
+            //Reset Sequence
+            case (0x1)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              Store (DeRefOf (Index (Arg3, 2)), Local2)
+              DRST (Local0, Local1, Local2)
+            }
+
+            //Set Serdes Loopback
+            case (0x2)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              SRLP (Local0, Local1)
+            }
+
+            //LED op set
+            case (0x3)
+            {
+
+            }
+
+            // Get port type (GE or XGE)
+            case (0x4)
+            {
+              Store (0, Local1)
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              If (LLessEqual (Local0, 3))
+              {
+                Store (H4ST, Local1)
+              }
+              ElseIf (LLessEqual (Local0, 5))
+              {
+                Store (H3ST, Local1)
+              }
+
+              Return (Local1)
+            }
+
+            //Get sfp status
+            case (0x5)
+            {
+
+            }
+          }
+        }
+      }
+      Return (Buffer() {0x00})
+    }
+    Device (PRT0)
+    {
+      Name (_ADR, 0x0)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 0},
+          Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+    Device (PRT1)
+    {
+      Name (_ADR, 0x1)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 1},
+          Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+    Device (PRT4)
+    {
+      Name (_ADR, 0x4)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 4},
+          Package () {"phy-mode", "sgmii"},
+          Package () {"phy-addr", 0},
+          Package () {"mdio-node", Package (){\_SB.MDIO}},
+          Package () {"media-type", "copper"},
+                        }
+                })
+    }
+    Device (PRT5)
+    {
+      Name (_ADR, 0x5)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 5},
+          Package () {"phy-mode", "sgmii"},
+          Package () {"phy-addr", 1},
+          Package () {"mdio-node", Package (){\_SB.MDIO}},
+          Package () {"media-type", "copper"},
+                        }
+                })
+    }
+  }
+/*
+  Device (DSF1)
+  {
+    OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+    Field(H3SR, DWordAcc, NoLock, Preserve) {
+          H3ST, 1,
+          , 31,  //RESERVED
+        }
+
+    // XGE RESET
+    OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+    Field(XRER, DWordAcc, NoLock, Preserve) {
+          XRTE, 31,
+          , 1,    //RESERVED
+          XRTD, 31,
+          , 1,    //RESERVED
+        }
+
+    // GE RESET
+    OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+    Field(GRTR, DWordAcc, NoLock, Preserve) {
+          GR0E, 30,
+          , 2,    //RESERVED
+          GR0D, 30,
+          , 2,    //RESERVED
+          GR1E, 18,
+          , 14,  //RESERVED
+          GR1D, 18,
+          , 14,  //RESERVED
+        }
+
+    // PPE RESET
+    OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+    Field(PRTR, DWordAcc, NoLock, Preserve) {
+          PRTE, 10,
+          , 22,  //RESERVED
+          PRTD, 10,
+          , 22,  //RESERVED
+        }
+
+    // ROCE
+
+    // CPLD LED
+
+    // Serdes
+    OperationRegion(H3LR, SystemMemory, 0xC2208100, 0x4)
+    Field(H3LR, DWordAcc, NoLock, Preserve) {
+          H3L0, 16,    // debug port0
+          , 16,    //RESERVED
+        }
+                Name(_HID, "HISI00B1")
+                Name (_CCA, 1) // Cache-coherent controller
+                Name (_CRS, ResourceTemplate (){
+                        Memory32Fixed (ReadWrite, 0xc2000000 , 0x890000)
+
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+        {
+          14, 15,
+        }
+                })
+                Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+                                Package () {"mode", "single-port"},
+                                Package () {"buf-size", 4096},
+                                Package () {"desc-num", 1024},
+        Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+                        }
+                })
+
+      // Set Serdes Loopback
+    //Arg0 : port
+    //Arg1 : 0 disable, 1 enable
+    Method(SRLP, 1, Serialized) {
+      ShiftLeft (Arg0, 10, Local0)
+      Store (H3L0, Local1)
+      And (Local1, 0xfffffbff, Local1)
+      Or (Local0, Local1, Local0)
+      Store (Local1, H3L0)
+    }
+
+    //Reset
+    //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3)
+    //Arg1 : 0 disable, 1 enable
+    Method(DRST, 2, Serialized)
+    {
+      Switch (ToInteger(Arg0))
+      {
+        //DSAF reset
+        case (0x1)
+        {
+          If (LEqual (Arg1, 0)) {
+            Store (0x100, PRTE)
+          } Else {
+            Store (0x100, PRTD)
+          }
+        }
+        //Reset PPE port
+        case (0x2)
+        {
+          If (LEqual (Arg1, 0)) {
+            Store(0x40, PRTE)
+          } Else  {
+            Store(0x40, PRTD)
+          }
+        }
+
+        //Reset GE port
+        case (0x5)
+        {
+          If (LEqual (Arg1, 0)) {
+            Store(0x15540, GR1E)
+            Store(0x100, PRTE)
+          } Else {
+            Store(0x15540, GR1D)
+            Store(0x100, PRTD)
+          }
+        }
+      }
+    }
+    // _DSM Device Specific Method
+    //
+    // Arg0: UUID Unique function identifier
+    // Arg1: Integer Revision Level
+    // Arg2: Integer Function Index
+    //   0 : Return Supported Functions bit mask
+    //   1 : Reset Sequence
+    //    Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge)
+    //    Arg3[1] : reserved
+    //    Arg3[2] : 0 reset, 1 cancle reset
+    //   2 : Set Serdes Loopback
+    //    Arg3[0] : reserved
+    //    Arg3[1] : 0 disable, 1 enable
+    //   3 : LED op set
+    //    Arg3[0] : op type
+    //    Arg3[1] : reserved
+    //    Arg3[2] : para
+    //   4 : Get port type (GE or XGE)
+    //    Arg3[0] : reserved
+    //    Return : 0 GE, 1 XGE
+    //   5 : Get sfp status
+    //    Arg3[0] : reserved
+    //    Return : 0 no sfp, 1 have sfp
+    // Arg3: Package Parameters
+    Method (_DSM, 4, Serialized)
+    {
+      If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+      {
+        If (LEqual (Arg1, 0x00))
+        {
+          Switch (ToInteger(Arg2))
+          {
+            case (0x0)
+            {
+              Return (Buffer () {0x3F})
+            }
+
+            //Reset Sequence
+            case (0x1)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 2)), Local2)
+              DRST (Local0, Local2)
+            }
+
+            //Set Serdes Loopback
+            case (0x2)
+            {
+              Store (DeRefOf (Index (Arg3, 2)), Local0)
+              SRLP (Local0)
+            }
+
+            //LED op set
+            case (0x3)
+            {
+
+            }
+
+            // Get port type (GE or XGE)
+            case (0x4)
+            {
+              Store (H3ST, Local0)
+              Return (Local0)
+            }
+
+            //Get sfp status
+            case (0x5)
+            {
+
+            }
+          }
+        }
+      }
+      Return (Buffer() {0x00})
+    }
+
+    Device (PRT0)
+    {
+      Name (_ADR, 0x0)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 0},
+          Package () {"phy-mode", "sgmii"},
+          Package () {"phy-addr", 0},
+          Package () {"mdio-node", Package (){\_SB.MDIO}},
+                        }
+                })
+    }
+  }
+  Device (DSF2)
+  {
+    OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+    Field(H3SR, DWordAcc, NoLock, Preserve) {
+          H3ST, 1,
+          , 31,  //RESERVED
+        }
+
+    // XGE RESET
+    OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+    Field(XRER, DWordAcc, NoLock, Preserve) {
+          XRTE, 31,
+          , 1,    //RESERVED
+          XRTD, 31,
+          , 1,    //RESERVED
+        }
+
+    // GE RESET
+    OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+    Field(GRTR, DWordAcc, NoLock, Preserve) {
+          GR0E, 30,
+          , 2,    //RESERVED
+          GR0D, 30,
+          , 2,    //RESERVED
+          GR1E, 18,
+          , 14,  //RESERVED
+          GR1D, 18,
+          , 14,  //RESERVED
+        }
+
+    // PPE RESET
+    OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+    Field(PRTR, DWordAcc, NoLock, Preserve) {
+          PRTE, 10,
+          , 22,  //RESERVED
+          PRTD, 10,
+          , 22,  //RESERVED
+        }
+
+    // ROCE
+
+    // CPLD LED
+
+    // Serdes
+    OperationRegion(H3LR, SystemMemory, 0xC2208500, 0x4)
+    Field(H3LR, DWordAcc, NoLock, Preserve) {
+          H3L1, 16,    // debug port1
+          , 16,    //RESERVED
+        }
+                Name(_HID, "HISI00B1")
+                Name (_CCA, 1) // Cache-coherent controller
+                Name (_CRS, ResourceTemplate (){
+                        Memory32Fixed (ReadWrite, 0xc2100000 , 0x890000)
+
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+        {
+          20, 21,
+        }
+                })
+                Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+                                Package () {"mode", "single-port"},
+                                Package () {"buf-size", 4096},
+                                Package () {"desc-num", 1024},
+        Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+                        }
+                })
+
+      // Set Serdes Loopback
+    //Arg0 : port
+    //Arg1 : 0 disable, 1 enable
+    Method(SRLP, 1, Serialized) {
+      ShiftLeft (Arg0, 10, Local0)
+      Store (H3L1, Local1)
+      And (Local1, 0xfffffbff, Local1)
+      Or (Local0, Local1, Local0)
+      Store (Local1, H3L1)
+    }
+
+    //Reset
+    //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3)
+    //Arg1 : 0 disable, 1 enable
+    Method(DRST, 2, Serialized)
+    {
+      Switch (ToInteger(Arg0))
+      {
+        //DSAF reset
+        case (0x1)
+        {
+          If (LEqual (Arg1, 0)) {
+            Store (0x200, PRTE)
+          } Else {
+            Store (0x2200, PRTD)
+          }
+        }
+
+        //Reset PPE port
+        case (0x2)
+        {
+          If (LEqual (Arg1, 0)) {
+            Store(0x80, PRTE)
+          } Else  {
+            Store(0x80, PRTD)
+          }
+        }
+
+        //Reset GE port
+        case (0x5)
+        {
+          If (LEqual (Arg1, 0)) {
+            Store(0x2aa80, GR1E)
+            Store(0x200, PRTE)
+          } Else {
+            Store(0x2aa80, GR1D)
+            Store(0x200, PRTD)
+          }
+        }
+      }
+    }
+    // _DSM Device Specific Method
+    //
+    // Arg0: UUID Unique function identifier
+    // Arg1: Integer Revision Level
+    // Arg2: Integer Function Index
+    //   0 : Return Supported Functions bit mask
+    //   1 : Reset sequence
+    //    Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge)
+    //    Arg3[1] : reserved
+    //    Arg3[2] : 0 reset, 1 cancle reset
+    //   2 : Set Serdes Loopback
+    //    Arg3[0] : reserved
+    //    Arg3[1] : 0 disable, 1 enable
+    //   3 : LED op set
+    //    Arg3[0] : op type
+    //    Arg3[1] : reserved
+    //    Arg3[2] : para
+    //   4 : Get port type (GE or XGE)
+    //    Arg3[0] : reserved
+    //    Return : 0 GE, 1 XGE
+    //   5 : Get sfp status
+    //    Arg3[0] : reserved
+    //    Return : 0 no sfp, 1 have sfp
+    // Arg3: Package Parameters
+    Method (_DSM, 4, Serialized)
+    {
+      If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+      {
+        If (LEqual (Arg1, 0x00))
+        {
+          Switch (ToInteger(Arg2))
+          {
+            case (0x0)
+            {
+              Return (Buffer () {0x3F})
+            }
+
+            //Reset Sequence
+            case (0x1)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 2)), Local2)
+              DRST (Local0, Local2)
+            }
+
+            //Set Serdes Loopback
+            case (0x2)
+            {
+              Store (DeRefOf (Index (Arg3, 2)), Local0)
+              SRLP (Local0)
+            }
+
+            //LED op set
+            case (0x3)
+            {
+
+            }
+
+            // Get port type (GE or XGE)
+            case (0x4)
+            {
+              Store (H3ST, Local0)
+              Return (Local0)
+            }
+
+            //Get sfp status
+            case (0x5)
+            {
+
+            }
+          }
+        }
+      }
+      Return (Buffer() {0x00})
+    }
+
+    Device (PRT0)
+    {
+      Name (_ADR, 0x0)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"reg", 0},
+          Package () {"phy-mode", "sgmii"},
+          Package () {"phy-addr", 1},
+          Package () {"mdio-node", Package (){\_SB.MDIO}},
+                        }
+                })
+    }
+  }
+*/
+  Device (ETH5) {
+    Name(_HID, "HISI00C1")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 5},
+      }
+    })
+  }
+  Device (ETH4) {
+    Name(_HID, "HISI00C1")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 4},
+      }
+    })
+  }
+  Device (ETH0) {
+    Name(_HID, "HISI00C1")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 0},
+      }
+    })
+  }
+  Device (ETH1) {
+    Name(_HID, "HISI00C1")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 1},
+      }
+    })
+  }
+
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl
new file mode 100644
index 0000000..e7d3f72
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl
@@ -0,0 +1,86 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  // Mbi-gen totem
+  Device(MBI0) {
+    Name(_HID, "HISI0151")
+    Name(_CID, "MBIGen")
+    Name(_UID, 0)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x8c030000, 0x10000)
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 256}
+      }
+    })
+  }
+
+  // mbi-gen dsa
+  Device(MBI1) {
+    Name(_HID, "HISI0151")
+    Name(_CID, "MBIGen")
+    Name(_UID, 1)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc6030000, 0x10000)
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 640}
+      }
+    })
+  }
+
+  // mbi-gen m3
+  Device(MBI2) {
+    Name(_HID, "HISI0151")
+    Name(_CID, "MBIGen")
+    Name(_UID, 2)
+    Name(_CRS, ResourceTemplate() {
+    Memory32Fixed(ReadWrite, 0xa3030000, 0x10000)
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 256}
+      }
+    })
+  }
+
+  // mbi-gen pcie
+  Device(MBI3) {
+    Name(_HID, "HISI0151")
+    Name(_CID, "MBIGen")
+    Name(_UID, 3)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xb7030000, 0x10000)
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package ()
+      {
+        Package () {"num-pins", 640}
+      }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl
new file mode 100644
index 0000000..244ff93
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl
@@ -0,0 +1,181 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+Scope(_SB)
+{
+  // PCIe Root bus
+  Device (PCI1)
+  {
+    Name (_HID, "HISI0080") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 1) // Segment of this Root complex
+    Name(_BBN, 64) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          64, // AddressMinimum - Minimum Bus Number
+          127, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          64 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0000000000000000, // Granularity
+          0x00000000b0000000, // Min Base Address pci address
+          0x00000000b7feffff, // Max Base Address
+          0x0000021f58000000, // Translate
+          0x0000000007ff0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0000000000000000, // Granularity
+          0x0000000000000000, // Min Base Address
+          0x000000000000ffff, // Max Base Address
+          0x000002200fff0000, // Translate
+          0x0000000000010000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+
+    Device (RES1)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CRS, ResourceTemplate (){
+        Memory32Fixed (ReadWrite, 0xb0080000 , 0x10000)
+      })
+    }
+
+    OperationRegion(SCTR, SystemMemory, 0xb0006918, 4)
+    Field(SCTR, AnyAcc, NoLock, Preserve) {
+      LSTA, 32,
+    }
+    Method(_DSM, 0x4, Serialized) {
+      If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
+
+        switch(ToInteger(Arg2))
+        {
+          // Function 0: Return LinkStatus
+          case(0) {
+              Store (0, Local0)
+              Store (LSTA, Local0)
+              Return (Local0)
+          }
+          default {
+          }
+        }
+      }
+      // If not one of the function identifiers we recognize, then return a buffer
+      // with bit 0 set to 0 indicating no functions supported.
+      return(Buffer(){0})
+    }
+  } // Device(PCI1)
+
+  // PCIe Root bus
+  Device (PCI2)
+  {
+    Name (_HID, "HISI0080") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 2) // Segment of this Root complex
+    Name(_BBN, 128) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          128, // AddressMinimum - Minimum Bus Number
+          191, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          64 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0000000000000000, // Granularity
+          0x00000000c0000000, // Min Base Address
+          0x00000000c3feffff, // Max Base Address
+          0x0000023f4c000000, // Translate
+          0x0000000003ff0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0000000000000000, // Granularity
+          0x0000000000000000, // Min Base Address
+          0x000000000000ffff, // Max Base Address
+          0x000002400fff0000, // Translate
+          0x0000000000010000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+
+    Device (RES2)
+    {
+      Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+      Name (_CRS, ResourceTemplate (){
+        Memory32Fixed (ReadWrite, 0xb0090000 , 0x10000)
+      })
+    }
+
+    OperationRegion(SCTR, SystemMemory, 0xb0006a18, 4)
+    Field(SCTR, AnyAcc, NoLock, Preserve) {
+      LSTA, 32,
+    }
+    Method(_DSM, 0x4, Serialized) {
+      If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949")))
+      {
+        switch(ToInteger(Arg2))
+        {
+          // Function 0: Return LinkStatus
+          case(0) {
+              Store (0, Local0)
+              Store (LSTA, Local0)
+              Return (Local0)
+          }
+          default {
+          }
+        }
+      }
+      // If not one of the function identifiers we recognize, then return a buffer
+      // with bit 0 set to 0 indicating no functions supported.
+      return(Buffer(){0})
+    }
+  } // Device(PCI2)
+}
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl
new file mode 100644
index 0000000..a0082af
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl
@@ -0,0 +1,136 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+  Device (USB0)
+        {
+            Name (_HID, "PNP0D20")  // _HID: Hardware ID
+            Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */)  // _CID: Compatible ID
+            Name (_CCA, One)  // _CCA: Cache Coherency Attribute
+            Method (_CRS, 0, Serialized)  // _CRS: Current Resource Settings
+            {
+                Name (RBUF, ResourceTemplate ()
+                {
+                    Memory32Fixed (ReadWrite,
+                        0xA1000000,         // Address Base
+                        0x00010000,         // Address Length
+                        )
+                    Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+                    {
+                        0x00000014,
+                    }
+                })
+                Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
+            }
+
+  Name (_DSD, Package () {
+              ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+              Package ()
+              {
+                  Package () {"interrupt-parent",Package() {\_SB.MBI2}}
+              }
+    })
+
+            Device (RHUB)
+            {
+                Name (_ADR, Zero)  // _ADR: Address
+                Device (PRT1)
+                {
+                    Name (_ADR, One)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        0xFF,
+                        Zero,
+                        Zero,
+                        Zero
+                    })
+                    Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device
+                    {
+                        ToPLD (
+                            PLD_Revision       = 0x1,
+                            PLD_IgnoreColor    = 0x1,
+                            PLD_Red            = 0x0,
+                            PLD_Green          = 0x0,
+                            PLD_Blue           = 0x0,
+                            PLD_Width          = 0x0,
+                            PLD_Height         = 0x0,
+                            PLD_UserVisible    = 0x1,
+                            PLD_Dock           = 0x0,
+                            PLD_Lid            = 0x0,
+                            PLD_Panel          = "UNKNOWN",
+                            PLD_VerticalPosition = "UPPER",
+                            PLD_HorizontalPosition = "LEFT",
+                            PLD_Shape          = "UNKNOWN",
+                            PLD_GroupOrientation = 0x0,
+                            PLD_GroupToken     = 0x0,
+                            PLD_GroupPosition  = 0x0,
+                            PLD_Bay            = 0x0,
+                            PLD_Ejectable      = 0x0,
+                            PLD_EjectRequired  = 0x0,
+                            PLD_CabinetNumber  = 0x0,
+                            PLD_CardCageNumber = 0x0,
+                            PLD_Reference      = 0x0,
+                            PLD_Rotation       = 0x0,
+                            PLD_Order          = 0x0,
+                            PLD_VerticalOffset = 0x0,
+                            PLD_HorizontalOffset = 0x0)
+
+                    })
+                }
+
+                Device (PRT2)
+                {
+                    Name (_ADR, 0x02)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+
+                Device (PRT3)
+                {
+                    Name (_ADR, 0x03)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+
+                Device (PRT4)
+                {
+                    Name (_ADR, 0x04)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+            }
+        }
+}
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc
new file mode 100644
index 0000000..72cc66c
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc
@@ -0,0 +1,67 @@
+/** @file
+*  Firmware ACPI Control Structure (FACS)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32  Signature
+  sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),  // UINT32  Length
+  0xA152,                                                 // UINT32  HardwareSignature
+  0,                                                      // UINT32  FirmwareWakingVector
+  0,                                                      // UINT32  GlobalLock
+  0,                                                      // UINT32  Flags
+  0,                                                      // UINT64  XFirmwareWakingVector
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,   // UINT8   Version;
+    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[0]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[1]
+      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved0[2]
+  0,                                                      // UINT32  OspmFlags  "Platform firmware must
+                                                          //                    initialize this field to zero."
+    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[0]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[1]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[2]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[3]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[4]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[5]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[6]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[7]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[8]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[9]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[10]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[11]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[12]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[13]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[14]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[15]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[16]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[17]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[18]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[19]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[20]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[21]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[22]
+      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved1[23]
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Facs;
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..5907c65
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc
@@ -0,0 +1,92 @@
+/** @file
+*  Fixed ACPI Description Table (FADT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//#include "ArmPlatform.h"
+#include "Pv660Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+  ARM_ACPI_HEADER (
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+  ),
+  0,                                                                        // UINT32     FirmwareCtrl
+  0,                                                                        // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
+  EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED,                                      // UINT8      PreferredPmProfile
+  0,                                                                        // UINT16     SciInt
+  0,                                                                        // UINT32     SmiCmd
+  0,                                                                        // UINT8      AcpiEnable
+  0,                                                                        // UINT8      AcpiDisable
+  0,                                                                        // UINT8      S4BiosReq
+  0,                                                                        // UINT8      PstateCnt
+  0,                                                                        // UINT32     Pm1aEvtBlk
+  0,                                                                        // UINT32     Pm1bEvtBlk
+  0,                                                                        // UINT32     Pm1aCntBlk
+  0,                                                                        // UINT32     Pm1bCntBlk
+  0,                                                                        // UINT32     Pm2CntBlk
+  0,                                                                        // UINT32     PmTmrBlk
+  0,                                                                        // UINT32     Gpe0Blk
+  0,                                                                        // UINT32     Gpe1Blk
+  0,                                                                        // UINT8      Pm1EvtLen
+  0,                                                                        // UINT8      Pm1CntLen
+  0,                                                                        // UINT8      Pm2CntLen
+  0,                                                                        // UINT8      PmTmrLen
+  0,                                                                        // UINT8      Gpe0BlkLen
+  0,                                                                        // UINT8      Gpe1BlkLen
+  0,                                                                        // UINT8      Gpe1Base
+  0,                                                                        // UINT8      CstCnt
+  0,                                                                        // UINT16     PLvl2Lat
+  0,                                                                        // UINT16     PLvl3Lat
+  0,                                                                        // UINT16     FlushSize
+  0,                                                                        // UINT16     FlushStride
+  0,                                                                        // UINT8      DutyOffset
+  0,                                                                        // UINT8      DutyWidth
+  0,                                                                        // UINT8      DayAlrm
+  0,                                                                        // UINT8      MonAlrm
+  0,                                                                        // UINT8      Century
+  0,                                                                        // UINT16     IaPcBootArch
+  0,                                                                        // UINT8      Reserved1
+  EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  ResetReg
+  0,                                                                        // UINT8      ResetValue
+  EFI_ACPI_5_1_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
+  EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
+  0,                                                                        // UINT64     XFirmwareCtrl
+  0,                                                                        // UINT64     XDsdt
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
+  NULL_GAS                                                                  // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..f677feb
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc
@@ -0,0 +1,96 @@
+/** @file
+*  Generic Timer Description Table (GTDT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Pv660Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0
+#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL       0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+  #define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+
+#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+  EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdogs[PV660_WATCHDOG_COUNT];
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+  {
+    ARM_ACPI_HEADER(
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES,
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+    ),
+    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
+    0,                                            // UINT32  Reserved
+    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
+    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
+    0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
+#ifdef notyet
+    PV660_WATCHDOG_COUNT,                          // UINT32  PlatformTimerCount
+    sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+  },
+  {
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
+        0, 0, 0, 0),
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
+        0, 0, 0, 0)
+  }
+#else /* !notyet */
+  0, 0
+  }
+#endif
+  };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
+
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl
new file mode 100644
index 0000000..bcd31d6
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl
@@ -0,0 +1,274 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength]  FieldName : HexFieldValue
+ */
+[0004]                          Signature : "IORT"    [IO Remapping Table]
+[0004]                       Table Length : 0000010C
+[0001]                           Revision : 00
+[0001]                           Checksum : BC
+[0006]                             Oem ID : "HISI  "
+[0008]                       Oem Table ID : "HIP05   "
+[0004]                       Oem Revision : 00000000
+[0004]                    Asl Compiler ID : "INTL"
+[0004]              Asl Compiler Revision : 20151124
+
+[0004]                         Node Count : 0000000A
+[0004]                        Node Offset : 00000034
+[0004]                           Reserved : 00000000
+[0004]                   Optional Padding : 00 00 00 00
+
+/* ITS 0, for totem */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000000
+
+/* ITS 1, for dsa */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000001
+
+/* ITS 2, m3 */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000002
+
+/* ITS 3, pcie */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000003
+
+/* mbi-gen pc, named component */
+[0001]                               Type : 01
+[0002]                             Length : 003B
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000027
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0012]                        Device Name : "\_SB_.MBI0"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 0000FFCC
+[0004]                   Output Reference : 00000034  // point to its totem
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 1
+
+/* mbi-gen dsa, named component */
+[0001]                               Type : 01
+[0002]                             Length : 003B
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000027
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0011]                        Device Name : "\_SB_.MBI1"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 0000FFCC
+[0004]                   Output Reference : 0000004C
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 1
+
+/* mbi-gen m3, named component */
+[0001]                               Type : 01
+[0002]                             Length : 003B
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000027
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0011]                        Device Name : "\_SB_.MBI2"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 0000FFCC
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 1
+
+/* mbi-gen pcie, named component */
+[0001]                               Type : 01
+[0002]                             Length : 003B
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000027
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0011]                        Device Name : "\_SB_.MBI3"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 0000FFCC
+[0004]                   Output Reference : 0000007C
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 1
+
+               /* RC 0 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000001
+
+[0004]                         Input base : 00004000
+[0004]                           ID Count : 00004000
+[0004]                        Output Base : 00004000
+[0004]                   Output Reference : 0000007C
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* RC 1 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000002
+
+[0004]                         Input base : 00008000
+[0004]                           ID Count : 00004000
+[0004]                        Output Base : 00008000
+[0004]                   Output Reference : 0000007C
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/*
+[0001]                               Type : 03
+[0002]                             Length : 005C
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 0000005C
+
+[0008]                       Base Address : 0000000000000000
+[0008]                               Span : 0000000000000000
+[0004]                              Model : 00000000
+[0004]              Flags (decoded below) : 00000000
+                            DVM Supported : 0
+                            Coherent Walk : 0
+[0004]            Global Interrupt Offset : 0000003C
+[0004]            Context Interrupt Count : 00000001
+[0004]           Context Interrupt Offset : 0000004C
+[0004]                PMU Interrupt Count : 00000001
+[0004]               PMU Interrupt Offset : 00000054
+
+[0008]             SMMU_NSgIrpt Interrupt : 0000000000000000
+[0008]          SMMU_NSgCfgIrpt Interrupt : 0000000000000000
+[0008]                  Context Interrupt : 0000000000000000
+[0008]                      PMU Interrupt : 0000000000000000
+*/
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc
new file mode 100644
index 0000000..4edb95d
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc
@@ -0,0 +1,130 @@
+/** @file
+*  Multiple APIC Description Table (MADT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Pv660Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiNextLib.h>
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+// 0x20000 is only for socket 0
+#define PLATFORM_GET_MPID(ClusterId, CoreId)   (0x20000 | ((ClusterId) << 8) | (CoreId))
+
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_5_1_GIC_STRUCTURE                            GicInterfaces[16];
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+  EFI_ACPI_6_0_GIC_ITS_STRUCTURE                        GicITS[4];
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+  {
+    ARM_ACPI_HEADER (
+      EFI_ACPI_1_0_APIC_SIGNATURE,
+      EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+      EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+    ),
+    //
+    // MADT specific fields
+    //
+    0, // LocalApicAddress
+    0, // Flags
+  },
+  {
+    // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+    //                                          GsivId, GicRBase, Mpidr)
+    // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+    //       ACPI v5.1).
+    //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+    //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        0, 0, PLATFORM_GET_MPID(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        1, 1, PLATFORM_GET_MPID(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        2, 2, PLATFORM_GET_MPID(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        3, 3, PLATFORM_GET_MPID(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        5, 5, PLATFORM_GET_MPID(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        6, 6, PLATFORM_GET_MPID(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        7, 7, PLATFORM_GET_MPID(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        8, 8, PLATFORM_GET_MPID(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        9, 9, PLATFORM_GET_MPID(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        10, 10, PLATFORM_GET_MPID(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        11, 11, PLATFORM_GET_MPID(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        13, 13, PLATFORM_GET_MPID(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        14, 14, PLATFORM_GET_MPID(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        15, 15, PLATFORM_GET_MPID(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */),
+  },
+
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4),
+  {
+    EFI_ACPI_6_0_GIC_ITS_INIT(0,0x8C000000), // pc
+    EFI_ACPI_6_0_GIC_ITS_INIT(1,0xC6000000), // dsa
+    EFI_ACPI_6_0_GIC_ITS_INIT(2,0xA3000000), // m3
+    EFI_ACPI_6_0_GIC_ITS_INIT(3,0xB7000000)  // pcie
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc
new file mode 100644
index 0000000..f783534
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     Yi Li - yi.li@linaro.org
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Pv660Platform.h"
+
+#define ACPI_5_0_MCFG_VERSION  0x1
+
+#pragma pack(1)
+typedef struct
+{
+   UINT64 ullBaseAddress;
+   UINT16 usSegGroupNum;
+   UINT8  ucStartBusNum;
+   UINT8  ucEndBusNum;
+   UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+   EFI_ACPI_DESCRIPTION_HEADER Header;
+   UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+   EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+   EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+  {
+      {
+        EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+        sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+        ACPI_5_0_MCFG_VERSION,
+        0x00,                                                     // Checksum will be updated at runtime
+        {EFI_ACPI_ARM_OEM_ID},
+        EFI_ACPI_ARM_OEM_TABLE_ID,
+        EFI_ACPI_ARM_OEM_REVISION,
+        EFI_ACPI_ARM_CREATOR_ID,
+        EFI_ACPI_ARM_CREATOR_REVISION
+      },
+      0x0000000000000000,                                 //Reserved
+  },
+  {
+
+    {
+      0x0000022000000000,                                 //Base Address
+      0x0001,                                             //Segment Group Number
+      0x40,                                               //Start Bus Number
+      0x7f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    {
+      0x0000024000000000,                                 //Base Address
+      0x0002,                                             //Segment Group Number
+      0x80,                                               //Start Bus Number
+      0xbf,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h
new file mode 100644
index 0000000..5c5b0f1
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h
@@ -0,0 +1,48 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#ifndef _PV660_PLATFORM_H_
+#define _PV660_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('H','I','P','0','5',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
+#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('I','N','T','L')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+  }
+
+#define PV660_WATCHDOG_COUNT  2
+
+#endif
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL
new file mode 100644
index 0000000..fa2c2d8
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL
@@ -0,0 +1,169 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+#include "Pv660Platform.h"
+DefinitionBlock (
+    "SASSSDT.aml", // Output Filename
+    "SSDT",         // Signature
+    0x01,           // SSDT Compliance Revision
+    "HISI  ",       // OEM ID
+    "SAS0",     // Table ID
+    EFI_ACPI_ARM_OEM_REVISION          // OEM Revision
+    )
+{
+    External(\_SB.MBI1)
+    External(\_SB.MBI3)
+    Scope(_SB) {
+         Device(SAS0) {
+              Name(_HID, "HISI0161")
+        Name(_CCA, 1)
+              Name(_CRS, ResourceTemplate() {
+                      Memory32Fixed(ReadWrite, 0xc1000000, 0x10000)
+                      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+                      {
+          //phy irq(0~79)
+          259,263,264,
+          269,273,274,
+          279,283,284,
+          289,293,294,
+          299,303,304,
+          309,313,314,
+          319,323,324,
+          329,333,334,
+          }
+
+                      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+                      {
+          //cq irq (80~111)
+          336,337,338,339,340,341,342,343,
+          344,345,346,347,348,349,350,351,
+          352,353,354,355,356,357,358,359,
+          360,361,362,363,364,365,366,367,
+          }
+
+                      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+                      {
+          376, //chip fatal error irq(120)
+          381, //chip fatal error irq(125)
+                      }
+              })
+
+              Name (_DSD, Package () {
+                  ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                  Package () {
+                      Package () {"interrupt-parent",Package() {\_SB.MBI1}},
+          Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x0a}},
+          Package () {"queue-count", 32},
+          Package () {"phy-count", 8},
+                  }
+              })
+
+        OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
+        Field (CTL, AnyAcc, NoLock, Preserve)
+        {
+          Offset (0x338),
+          CLK, 32,
+          CLKD, 32,
+          Offset (0xa60),
+          RST, 32,
+          DRST, 32,
+          Offset (0x5a30),
+          STS, 32,
+        }
+
+        Method (_RST, 0x0, Serialized)
+        {
+          Store(0x7ffff, RST)
+          Store(0x7ffff, CLKD)
+          Sleep(1)
+          Store(0x7ffff, DRST)
+          Store(0x7ffff, CLK)
+          Sleep(1)
+        }
+        }
+
+        Device(SAS1) {
+              Name(_HID, "HISI0161")
+        Name(_CCA, 1)
+              Name(_CRS, ResourceTemplate() {
+                      Memory32Fixed(ReadWrite, 0xb1000000, 0x10000)
+                      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+                      {
+          //phy irq(0~79)
+          259,263,264,
+          269,273,274,
+          279,283,284,
+          289,293,294,
+          299,303,304,
+          309,313,314,
+          319,323,324,
+          329,333,334,
+          }
+
+                      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+                      {
+          //cq irq (80~111)
+          336,337,338,339,340,341,342,343,
+          344,345,346,347,348,349,350,351,
+          352,353,354,355,356,357,358,359,
+          360,361,362,363,364,365,366,367,
+          }
+
+                      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+                      {
+          376, //chip fatal error irq(120)
+          381, //chip fatal error irq(125)
+                      }
+              })
+
+              Name (_DSD, Package () {
+                  ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                  Package () {
+                      Package () {"interrupt-parent",Package() {\_SB.MBI3}},
+          Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+          Package () {"queue-count", 32},
+          Package () {"phy-count", 8},
+                  }
+              })
+
+        OperationRegion (CTL, SystemMemory, 0xB0000000, 0x10000)
+        Field (CTL, AnyAcc, NoLock, Preserve)
+        {
+          Offset (0x318),
+          CLK, 32,
+          CLKD, 32,
+          Offset (0xa18),
+          RST, 32,
+          DRST, 32,
+          Offset (0x5a0c),
+          STS, 32,
+        }
+
+        Method (_RST, 0x0, Serialized)
+        {
+          Store(0x7ffff, RST)
+          Store(0x7ffff, CLKD)
+          Sleep(1)
+          Store(0x7ffff, DRST)
+          Store(0x7ffff, CLK)
+          Sleep(1)
+        }
+        }
+
+    }
+
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL
new file mode 100644
index 0000000..f00664c
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL
@@ -0,0 +1,51 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+#include "Pv660Platform.h"
+
+DefinitionBlock (
+    "SATASSDT.aml", // Output Filename
+    "SSDT",         // Signature
+    0x01,           // DSDT Compliance Revision
+    "HISI  ",       // OEM ID
+    "SATA",     // Table ID
+    EFI_ACPI_ARM_OEM_REVISION          // OEM Revision
+    )
+{
+External(\_SB.MBI3)
+Scope(_SB) {
+    Device (AHCI)
+    {
+      Name(_HID, "HISI0001")  // HiSi AHCI
+      Name (_CCA, 1)           // Cache-coherent controller
+      Name (_CRS, ResourceTemplate () {
+        Memory32Fixed (ReadWrite, 0xb1002800, 0x00000B00)
+        Memory32Fixed (ReadWrite, 0xb1000000, 0x00002800)
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 382 }
+      })
+
+      Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package () {"interrupt-parent",Package() {\_SB.MBI3}}
+        }
+      })
+    }
+
+}
+
+}
diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc
new file mode 100644
index 0000000..7eef5f9
--- /dev/null
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc
@@ -0,0 +1,64 @@
+/** @file
+*  Serial Port Console Redirection Table (SPCR)
+*
+*  Copyright (c) 2012 - 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include "Pv660Platform.h"
+
+EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+  //Header;
+  ARM_ACPI_HEADER(
+    EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+    EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+    EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION
+  ),
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //InterfaceType;
+  {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, //Reserved1[3];
+  //BaseAddress;
+  {
+    EFI_ACPI_6_0_SYSTEM_MEMORY,
+    32,
+    0,
+    EFI_ACPI_6_0_BYTE,
+    FixedPcdGet64(PcdSerialRegisterBase)
+  },
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //InterruptType;
+  0, //Irq;
+  349, //GlobalSystemInterrupt;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,   //BaudRate;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,   //Parity;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,        //StopBits;
+  0, //FlowControl;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //TerminalType;
+  EFI_ACPI_RESERVED_BYTE, //Language;
+  0xFFFF, //PciDeviceId;
+  0xFFFF, //PciVendorId;
+  0,      //PciBusNumber;
+  0,      //PciDeviceNumber;
+  0,      //PciFunctionNumber;
+  0,      //PciFlags;
+  0,      //PciSegment;
+  EFI_ACPI_RESERVED_DWORD  //Reserved2;
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Chips/TexasInstruments/Omap35xx/Contributions.txt b/Chips/TexasInstruments/Omap35xx/Contributions.txt
deleted file mode 100644
index f87cbd7..0000000
--- a/Chips/TexasInstruments/Omap35xx/Contributions.txt
+++ /dev/null
@@ -1,218 +0,0 @@
-
-======================
-= Code Contributions =
-======================
-
-To make a contribution to a TianoCore project, follow these steps.
-1. Create a change description in the format specified below to
-   use in the source control commit log.
-2. Your commit message must include your "Signed-off-by" signature,
-   and "Contributed-under" message.
-3. Your "Contributed-under" message explicitly states that the
-   contribution is made under the terms of the specified
-   contribution agreement.  Your "Contributed-under" message
-   must include the name of contribution agreement and version.
-   For example: Contributed-under: TianoCore Contribution Agreement 1.0
-   The "TianoCore Contribution Agreement" is included below in
-   this document.
-4. Submit your code to the TianoCore project using the process
-   that the project documents on its web page.  If the process is
-   not documented, then submit the code on development email list
-   for the project.
-5. It is preferred that contributions are submitted using the same
-   copyright license as the base project. When that is not possible,
-   then contributions using the following licenses can be accepted:
-   * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
-   * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
-   * MIT: http://opensource.org/licenses/MIT
-   * Python-2.0: http://opensource.org/licenses/Python-2.0
-   * Zlib: http://opensource.org/licenses/Zlib
-
-   Contributions of code put into the public domain can also be
-   accepted.
-
-   Contributions using other licenses might be accepted, but further
-   review will be required.
-
-=====================================================
-= Change Description / Commit Message / Patch Email =
-=====================================================
-
-Your change description should use the standard format for a
-commit message, and must include your "Signed-off-by" signature
-and the "Contributed-under" message.
-
-== Sample Change Description / Commit Message =
-
-=== Start of sample patch email message ===
-
-From: Contributor Name <contributor@example.com>
-Subject: [PATCH] CodeModule: Brief-single-line-summary
-
-Full-commit-message
-
-Contributed-under: TianoCore Contribution Agreement 1.0
-Signed-off-by: Contributor Name <contributor@example.com>
----
-
-An extra message for the patch email which will not be considered part
-of the commit message can be added here.
-
-Patch content inline or attached
-
-=== End of sample patch email message ===
-
-=== Notes for sample patch email ===
-
-* The first line of commit message is taken from the email's subject
-  line following [PATCH]. The remaining portion of the commit message
-  is the email's content until the '---' line.
-* git format-patch is one way to create this format
-
-=== Definitions for sample patch email ===
-
-* "CodeModule" is a short idenfier for the affected code.  For
-  example MdePkg, or MdeModulePkg UsbBusDxe.
-* "Brief-single-line-summary" is a short summary of the change.
-* The entire first line should be less than ~70 characters.
-* "Full-commit-message" a verbose multiple line comment describing
-  the change.  Each line should be less than ~70 characters.
-* "Contributed-under" explicitely states that the contribution is
-  made under the terms of the contribtion agreement.  This
-  agreement is included below in this document.
-* "Signed-off-by" is the contributor's signature identifying them
-  by their real/legal name and their email address.
-
-========================================
-= TianoCore Contribution Agreement 1.0 =
-========================================
-
-INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
-INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
-PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
-TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
-TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
-REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
-CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
-OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
-BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
-AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
-AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
-USE THE CONTENT.
-
-Unless otherwise indicated, all Content made available on the TianoCore
-site is provided to you under the terms and conditions of the BSD
-License ("BSD"). A copy of the BSD License is available at
-http://opensource.org/licenses/bsd-license.php
-or when applicable, in the associated License.txt file.
-
-Certain other content may be made available under other licenses as
-indicated in or with such Content. (For example, in a License.txt file.)
-
-You accept and agree to the following terms and conditions for Your
-present and future Contributions submitted to TianoCore site. Except
-for the license granted to Intel hereunder, You reserve all right,
-title, and interest in and to Your Contributions.
-
-== SECTION 1: Definitions ==
-* "You" or "Contributor" shall mean the copyright owner or legal
-  entity authorized by the copyright owner that is making a
-  Contribution hereunder. All other entities that control, are
-  controlled by, or are under common control with that entity are
-  considered to be a single Contributor. For the purposes of this
-  definition, "control" means (i) the power, direct or indirect, to
-  cause the direction or management of such entity, whether by
-  contract or otherwise, or (ii) ownership of fifty percent (50%)
-  or more of the outstanding shares, or (iii) beneficial ownership
-  of such entity.
-* "Contribution" shall mean any original work of authorship,
-  including any modifications or additions to an existing work,
-  that is intentionally submitted by You to the TinaoCore site for
-  inclusion in, or documentation of, any of the Content. For the
-  purposes of this definition, "submitted" means any form of
-  electronic, verbal, or written communication sent to the
-  TianoCore site or its representatives, including but not limited
-  to communication on electronic mailing lists, source code
-  control systems, and issue tracking systems that are managed by,
-  or on behalf of, the TianoCore site for the purpose of
-  discussing and improving the Content, but excluding
-  communication that is conspicuously marked or otherwise
-  designated in writing by You as "Not a Contribution."
-
-== SECTION 2: License for Contributions ==
-* Contributor hereby agrees that redistribution and use of the
-  Contribution in source and binary forms, with or without
-  modification, are permitted provided that the following
-  conditions are met:
-** Redistributions of source code must retain the Contributor's
-   copyright notice, this list of conditions and the following
-   disclaimer.
-** Redistributions in binary form must reproduce the Contributor's
-   copyright notice, this list of conditions and the following
-   disclaimer in the documentation and/or other materials provided
-   with the distribution.
-* Disclaimer. None of the names of Contributor, Intel, or the names
-  of their respective contributors may be used to endorse or
-  promote products derived from this software without specific
-  prior written permission.
-* Contributor grants a license (with the right to sublicense) under
-  claims of Contributor's patents that Contributor can license that
-  are infringed by the Contribution (as delivered by Contributor) to
-  make, use, distribute, sell, offer for sale, and import the
-  Contribution and derivative works thereof solely to the minimum
-  extent necessary for licensee to exercise the granted copyright
-  license; this patent license applies solely to those portions of
-  the Contribution that are unmodified. No hardware per se is
-  licensed.
-* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
-  CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
-  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-  CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
-  CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-  DAMAGE.
-
-== SECTION 3: Representations ==
-* You represent that You are legally entitled to grant the above
-  license. If your employer(s) has rights to intellectual property
-  that You create that includes Your Contributions, You represent
-  that You have received permission to make Contributions on behalf
-  of that employer, that Your employer has waived such rights for
-  Your Contributions.
-* You represent that each of Your Contributions is Your original
-  creation (see Section 4 for submissions on behalf of others).
-  You represent that Your Contribution submissions include complete
-  details of any third-party license or other restriction
-  (including, but not limited to, related patents and trademarks)
-  of which You are personally aware and which are associated with
-  any part of Your Contributions.
-
-== SECTION 4: Third Party Contributions ==
-* Should You wish to submit work that is not Your original creation,
-  You may submit it to TianoCore site separately from any
-  Contribution, identifying the complete details of its source
-  and of any license or other restriction (including, but not
-  limited to, related patents, trademarks, and license agreements)
-  of which You are personally aware, and conspicuously marking the
-  work as "Submitted on behalf of a third-party: [named here]".
-
-== SECTION 5: Miscellaneous ==
-* Applicable Laws. Any claims arising under or relating to this
-  Agreement shall be governed by the internal substantive laws of
-  the State of Delaware or federal courts located in Delaware,
-  without regard to principles of conflict of laws.
-* Language. This Agreement is in the English language only, which
-  language shall be controlling in all respects, and all versions
-  of this Agreement in any other language shall be for accommodation
-  only and shall not be binding. All communications and notices made
-  or given pursuant to this Agreement, and all documentation and
-  support to be provided, unless otherwise noted, shall be in the
-  English language.
-
diff --git a/Chips/TexasInstruments/Omap35xx/Flash/Flash.c b/Chips/TexasInstruments/Omap35xx/Flash/Flash.c
deleted file mode 100644
index b8de109..0000000
--- a/Chips/TexasInstruments/Omap35xx/Flash/Flash.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "Flash.h"
-
-NAND_PART_INFO_TABLE gNandPartInfoTable[1] = {
-  { 0x2C, 0xBA, 17, 11 }
-};
-
-NAND_FLASH_INFO *gNandFlashInfo = NULL;
-UINT8           *gEccCode;
-UINTN           gNum512BytesChunks = 0;
-
-//
-
-// Device path for SemiHosting. It contains our autogened Caller ID GUID.
-
-//
-
-typedef struct {
-
-  VENDOR_DEVICE_PATH        Guid;
-
-  EFI_DEVICE_PATH_PROTOCOL  End;
-
-} FLASH_DEVICE_PATH;
-
-
-
-FLASH_DEVICE_PATH gDevicePath = {
-  {
-    { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } },
-    EFI_CALLER_ID_GUID
-  },
-  { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }
-};
-
-
-
-//Actual page address = Column address + Page address + Block address.
-UINTN
-GetActualPageAddressInBytes (
-  UINTN BlockIndex,
-  UINTN PageIndex
-)
-{
-  //BlockAddressStart = Start of the Block address in actual NAND
-  //PageAddressStart = Start of the Page address in actual NAND
-  return ((BlockIndex << gNandFlashInfo->BlockAddressStart) + (PageIndex << gNandFlashInfo->PageAddressStart));
-}
-
-VOID
-NandSendCommand (
-  UINT8 Command
-)
-{
-  MmioWrite16(GPMC_NAND_COMMAND_0, Command);
-}
-
-VOID
-NandSendAddress (
-  UINT8 Address
-)
-{
-  MmioWrite16(GPMC_NAND_ADDRESS_0, Address);
-}
-
-UINT16
-NandReadStatus (
-  VOID
-  )
-{
-  //Send READ STATUS command
-  NandSendCommand(READ_STATUS_CMD);
-
-  //Read status.
-  return MmioRead16(GPMC_NAND_DATA_0);
-}
-
-VOID
-NandSendAddressCycles (
-  UINTN Address
-)
-{
-  //Column address
-  NandSendAddress(Address & 0xff);
-  Address >>= 8;
-
-  //Column address
-  NandSendAddress(Address & 0x07);
-  Address >>= 3;
-
-  //Page and Block address
-  NandSendAddress(Address & 0xff);
-  Address >>= 8;
-
-  //Block address
-  NandSendAddress(Address & 0xff);
-  Address >>= 8;
-
-  //Block address
-  NandSendAddress(Address & 0x01);
-}
-
-VOID
-GpmcInit (
-  VOID
-  )
-{
-  //Enable Smart-idle mode.
-  MmioWrite32 (GPMC_SYSCONFIG, SMARTIDLEMODE);
-
-  //Set IRQSTATUS and IRQENABLE to the reset value
-  MmioWrite32 (GPMC_IRQSTATUS, 0x0);
-  MmioWrite32 (GPMC_IRQENABLE, 0x0);
-
-  //Disable GPMC timeout control.
-  MmioWrite32 (GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
-
-  //Set WRITEPROTECT bit to enable write access.
-  MmioWrite32 (GPMC_CONFIG, WRITEPROTECT_HIGH);
-
-  //NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
-  MmioWrite32 (GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
-  MmioWrite32 (GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
-  MmioWrite32 (GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
-  MmioWrite32 (GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
-  MmioWrite32 (GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
-  MmioWrite32 (GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
-  MmioWrite32 (GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
-}
-
-EFI_STATUS
-NandDetectPart (
-  VOID
-)
-{
-  UINT8      NandInfo = 0;
-  UINT8      PartInfo[5];
-  UINTN      Index;
-  BOOLEAN    Found = FALSE;
-
-  //Send READ ID command
-  NandSendCommand(READ_ID_CMD);
-
-  //Send one address cycle.
-  NandSendAddress(0);
-
-  //Read 5-bytes to idenfity code programmed into the NAND flash devices.
-  //BYTE 0 = Manufacture ID
-  //Byte 1 = Device ID
-  //Byte 2, 3, 4 = Nand part specific information (Page size, Block size etc)
-  for (Index = 0; Index < sizeof(PartInfo); Index++) {
-    PartInfo[Index] = MmioRead16(GPMC_NAND_DATA_0);
-  }
-
-  //Check if the ManufactureId and DeviceId are part of the currently supported nand parts.
-  for (Index = 0; Index < sizeof(gNandPartInfoTable)/sizeof(NAND_PART_INFO_TABLE); Index++) {
-    if (gNandPartInfoTable[Index].ManufactureId == PartInfo[0] && gNandPartInfoTable[Index].DeviceId == PartInfo[1]) {
-      gNandFlashInfo->BlockAddressStart = gNandPartInfoTable[Index].BlockAddressStart;
-      gNandFlashInfo->PageAddressStart = gNandPartInfoTable[Index].PageAddressStart;
-      Found = TRUE;
-      break;
-    }
-  }
-
-  if (Found == FALSE) {
-    DEBUG ((EFI_D_ERROR, "Nand part is not currently supported. Manufacture id: %x, Device id: %x\n", PartInfo[0], PartInfo[1]));
-    return EFI_NOT_FOUND;
-  }
-
-  //Populate NAND_FLASH_INFO based on the result of READ ID command.
-  gNandFlashInfo->ManufactureId = PartInfo[0];
-  gNandFlashInfo->DeviceId = PartInfo[1];
-  NandInfo = PartInfo[3];
-
-  if (PAGE_SIZE(NandInfo) == PAGE_SIZE_2K_VAL) {
-    gNandFlashInfo->PageSize = PAGE_SIZE_2K;
-  } else {
-    DEBUG ((EFI_D_ERROR, "Unknown Page size.\n"));
-    return EFI_DEVICE_ERROR;
-  }
-
-  if (SPARE_AREA_SIZE(NandInfo) == SPARE_AREA_SIZE_64B_VAL) {
-    gNandFlashInfo->SparePageSize = SPARE_AREA_SIZE_64B;
-  } else {
-    DEBUG ((EFI_D_ERROR, "Unknown Spare area size.\n"));
-    return EFI_DEVICE_ERROR;
-  }
-
-  if (BLOCK_SIZE(NandInfo) == BLOCK_SIZE_128K_VAL) {
-    gNandFlashInfo->BlockSize = BLOCK_SIZE_128K;
-  } else {
-    DEBUG ((EFI_D_ERROR, "Unknown Block size.\n"));
-    return EFI_DEVICE_ERROR;
-  }
-
-  if (ORGANIZATION(NandInfo) == ORGANIZATION_X8) {
-    gNandFlashInfo->Organization = 0;
-  } else if (ORGANIZATION(NandInfo) == ORGANIZATION_X16) {
-    gNandFlashInfo->Organization = 1;
-  }
-
-  //Calculate total number of blocks.
-  gNandFlashInfo->NumPagesPerBlock = DivU64x32(gNandFlashInfo->BlockSize, gNandFlashInfo->PageSize);
-
-  return EFI_SUCCESS;
-}
-
-VOID
-NandConfigureEcc (
-  VOID
-  )
-{
-  //Define ECC size 0 and size 1 to 512 bytes
-  MmioWrite32 (GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
-}
-
-VOID
-NandEnableEcc (
-  VOID
-  )
-{
-  //Clear all the ECC result registers and select ECC result register 1
-  MmioWrite32 (GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
-
-  //Enable ECC engine on CS0
-  MmioWrite32 (GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
-}
-
-VOID
-NandDisableEcc (
-  VOID
-  )
-{
-  //Turn off ECC engine.
-  MmioWrite32 (GPMC_ECC_CONFIG, ECCDISABLE);
-}
-
-VOID
-NandCalculateEcc (
-  VOID
-  )
-{
-  UINTN Index;
-  UINTN EccResultRegister;
-  UINTN EccResult;
-
-  //Capture 32-bit ECC result for each 512-bytes chunk.
-  //In our case PageSize is 2K so read ECC1-ECC4 result registers and
-  //generate total of 12-bytes of ECC code for the particular page.
-
-  EccResultRegister = GPMC_ECC1_RESULT;
-
-  for (Index = 0; Index < gNum512BytesChunks; Index++) {
-
-    EccResult = MmioRead32 (EccResultRegister);
-
-    //Calculate ECC code from 32-bit ECC result value.
-    //NOTE: Following calculation is not part of TRM. We got this information
-    //from Beagleboard mailing list.
-    gEccCode[Index * 3] = EccResult & 0xFF;
-    gEccCode[(Index * 3) + 1] = (EccResult >> 16) & 0xFF;
-    gEccCode[(Index * 3) + 2] = (((EccResult >> 20) & 0xF0) | ((EccResult >> 8) & 0x0F));
-
-    //Point to next ECC result register.
-    EccResultRegister += 4;
-  }
-}
-
-EFI_STATUS
-NandReadPage (
-  IN  UINTN                         BlockIndex,
-  IN  UINTN                         PageIndex,
-  OUT VOID                          *Buffer,
-  OUT UINT8                         *SpareBuffer
-)
-{
-  UINTN      Address;
-  UINTN      Index;
-  UINTN      NumMainAreaWords = (gNandFlashInfo->PageSize/2);
-  UINTN      NumSpareAreaWords = (gNandFlashInfo->SparePageSize/2);
-  UINT16     *MainAreaWordBuffer = Buffer;
-  UINT16     *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
-  UINTN      Timeout = MAX_RETRY_COUNT;
-
-  //Generate device address in bytes to access specific block and page index
-  Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
-
-  //Send READ command
-  NandSendCommand(PAGE_READ_CMD);
-
-  //Send 5 Address cycles to access specific device address
-  NandSendAddressCycles(Address);
-
-  //Send READ CONFIRM command
-  NandSendCommand(PAGE_READ_CONFIRM_CMD);
-
-  //Poll till device is busy.
-  while (Timeout) {
-    if ((NandReadStatus() & NAND_READY) == NAND_READY) {
-      break;
-    }
-    Timeout--;
-  }
-
-  if (Timeout == 0) {
-    DEBUG ((EFI_D_ERROR, "Read page timed out.\n"));
-    return EFI_TIMEOUT;
-  }
-
-  //Reissue READ command
-  NandSendCommand(PAGE_READ_CMD);
-
-  //Enable ECC engine.
-  NandEnableEcc();
-
-  //Read data into the buffer.
-  for (Index = 0; Index < NumMainAreaWords; Index++) {
-    *MainAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
-  }
-
-  //Read spare area into the buffer.
-  for (Index = 0; Index < NumSpareAreaWords; Index++) {
-    *SpareAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
-  }
-
-  //Calculate ECC.
-  NandCalculateEcc();
-
-  //Turn off ECC engine.
-  NandDisableEcc();
-
-  //Perform ECC correction.
-  //Need to implement..
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-NandWritePage (
-  IN  UINTN                         BlockIndex,
-  IN  UINTN                         PageIndex,
-  OUT VOID                          *Buffer,
-  IN  UINT8                         *SpareBuffer
-)
-{
-  UINTN      Address;
-  UINT16     *MainAreaWordBuffer = Buffer;
-  UINT16     *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
-  UINTN      Index;
-  UINTN      NandStatus;
-  UINTN      Timeout = MAX_RETRY_COUNT;
-
-  //Generate device address in bytes to access specific block and page index
-  Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
-
-  //Send SERIAL DATA INPUT command
-  NandSendCommand(PROGRAM_PAGE_CMD);
-
-  //Send 5 Address cycles to access specific device address
-  NandSendAddressCycles(Address);
-
-  //Enable ECC engine.
-  NandEnableEcc();
-
-  //Data input from Buffer
-  for (Index = 0; Index < (gNandFlashInfo->PageSize/2); Index++) {
-    MmioWrite16(GPMC_NAND_DATA_0, *MainAreaWordBuffer++);
-
-    //After each write access, device has to wait to accept data.
-    //Currently we may not be programming proper timing parameters to
-    //the GPMC_CONFIGi_0 registers and we would need to figure that out.
-    //Without following delay, page programming fails.
-    gBS->Stall(1);
-  }
-
-  //Calculate ECC.
-  NandCalculateEcc();
-
-  //Turn off ECC engine.
-  NandDisableEcc();
-
-  //Prepare Spare area buffer with ECC codes.
-  SetMem(SpareBuffer, gNandFlashInfo->SparePageSize, 0xFF);
-  CopyMem(&SpareBuffer[ECC_POSITION], gEccCode, gNum512BytesChunks * 3);
-
-  //Program spare area with calculated ECC.
-  for (Index = 0; Index < (gNandFlashInfo->SparePageSize/2); Index++) {
-    MmioWrite16(GPMC_NAND_DATA_0, *SpareAreaWordBuffer++);
-  }
-
-  //Send PROGRAM command
-  NandSendCommand(PROGRAM_PAGE_CONFIRM_CMD);
-
-  //Poll till device is busy.
-  NandStatus = 0;
-  while (Timeout) {
-    NandStatus = NandReadStatus();
-    if ((NandStatus & NAND_READY) == NAND_READY) {
-      break;
-    }
-    Timeout--;
-  }
-
-  if (Timeout == 0) {
-    DEBUG ((EFI_D_ERROR, "Program page timed out.\n"));
-    return EFI_TIMEOUT;
-  }
-
-  //Bit0 indicates Pass/Fail status
-  if (NandStatus & NAND_FAILURE) {
-    return EFI_DEVICE_ERROR;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-NandEraseBlock (
-  IN UINTN BlockIndex
-)
-{
-  UINTN      Address;
-  UINTN      NandStatus;
-  UINTN      Timeout = MAX_RETRY_COUNT;
-
-  //Generate device address in bytes to access specific block and page index
-  Address = GetActualPageAddressInBytes(BlockIndex, 0);
-
-  //Send ERASE SETUP command
-  NandSendCommand(BLOCK_ERASE_CMD);
-
-  //Send 3 address cycles to device to access Page address and Block address
-  Address >>= 11; //Ignore column addresses
-
-  NandSendAddress(Address & 0xff);
-  Address >>= 8;
-
-  NandSendAddress(Address & 0xff);
-  Address >>= 8;
-
-  NandSendAddress(Address & 0xff);
-
-  //Send ERASE CONFIRM command
-  NandSendCommand(BLOCK_ERASE_CONFIRM_CMD);
-
-  //Poll till device is busy.
-  NandStatus = 0;
-  while (Timeout) {
-    NandStatus = NandReadStatus();
-    if ((NandStatus & NAND_READY) == NAND_READY) {
-      break;
-    }
-    Timeout--;
-    gBS->Stall(1);
-  }
-
-  if (Timeout == 0) {
-    DEBUG ((EFI_D_ERROR, "Erase block timed out for Block: %d.\n", BlockIndex));
-    return EFI_TIMEOUT;
-  }
-
-  //Bit0 indicates Pass/Fail status
-  if (NandStatus & NAND_FAILURE) {
-    return EFI_DEVICE_ERROR;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-NandReadBlock (
-  IN UINTN                          StartBlockIndex,
-  IN UINTN                          EndBlockIndex,
-  OUT VOID                          *Buffer,
-  OUT VOID                          *SpareBuffer
-)
-{
-  UINTN      BlockIndex;
-  UINTN      PageIndex;
-  EFI_STATUS Status = EFI_SUCCESS;
-
-  for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
-    //For each block read number of pages
-    for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
-      Status = NandReadPage(BlockIndex, PageIndex, Buffer, SpareBuffer);
-      if (EFI_ERROR(Status)) {
-        return Status;
-      }
-      Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
-    }
-  }
-
-  return Status;
-}
-
-EFI_STATUS
-NandWriteBlock (
-  IN UINTN                          StartBlockIndex,
-  IN UINTN                          EndBlockIndex,
-  OUT VOID                          *Buffer,
-  OUT VOID                          *SpareBuffer
-  )
-{
-  UINTN      BlockIndex;
-  UINTN      PageIndex;
-  EFI_STATUS Status = EFI_SUCCESS;
-
-  for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
-    //Page programming.
-    for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
-      Status = NandWritePage(BlockIndex, PageIndex, Buffer, SpareBuffer);
-      if (EFI_ERROR(Status)) {
-        return Status;
-      }
-      Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
-    }
-  }
-
-  return Status;
-}
-
-EFI_STATUS
-EFIAPI
-NandFlashReset (
-  IN EFI_BLOCK_IO_PROTOCOL          *This,
-  IN BOOLEAN                        ExtendedVerification
-  )
-{
-  UINTN BusyStall = 50;                            // microSeconds
-  UINTN ResetBusyTimeout = (1000000 / BusyStall);  // 1 Second
-
-  //Send RESET command to device.
-  NandSendCommand(RESET_CMD);
-
-  //Wait for 1ms before we check status register.
-  gBS->Stall(1000);
-
-  //Check BIT#5 & BIT#6 in Status register to make sure RESET is done.
-  while ((NandReadStatus() & NAND_RESET_STATUS) != NAND_RESET_STATUS) {
-
-    //In case of extended verification, wait for extended amount of time
-    //to make sure device is reset.
-    if (ExtendedVerification) {
-      if (ResetBusyTimeout == 0) {
-        return EFI_DEVICE_ERROR;
-      }
-
-      gBS->Stall(BusyStall);
-      ResetBusyTimeout--;
-    }
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-NandFlashReadBlocks (
-  IN EFI_BLOCK_IO_PROTOCOL          *This,
-  IN UINT32                         MediaId,
-  IN EFI_LBA                        Lba,
-  IN UINTN                          BufferSize,
-  OUT VOID                          *Buffer
-  )
-{
-  UINTN      NumBlocks;
-  UINTN      EndBlockIndex;
-  EFI_STATUS Status;
-  UINT8      *SpareBuffer = NULL;
-
-  if (Buffer == NULL) {
-    Status = EFI_INVALID_PARAMETER;
-    goto exit;
-  }
-
-  if (Lba > LAST_BLOCK) {
-    Status = EFI_INVALID_PARAMETER;
-    goto exit;
-  }
-
-  if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
-    Status = EFI_BAD_BUFFER_SIZE;
-    goto exit;
-  }
-
-  NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
-  EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
-
-  SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
-  if (SpareBuffer == NULL) {
-    Status = EFI_OUT_OF_RESOURCES;
-    goto exit;
-  }
-
-  //Read block
-  Status = NandReadBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
-  if (EFI_ERROR(Status)) {
-    DEBUG((EFI_D_ERROR, "Read block fails: %x\n", Status));
-    goto exit;
-  }
-
-exit:
-  if (SpareBuffer != NULL) {
-    FreePool (SpareBuffer);
-  }
-
-  return Status;
-}
-
-EFI_STATUS
-EFIAPI
-NandFlashWriteBlocks (
-  IN EFI_BLOCK_IO_PROTOCOL          *This,
-  IN UINT32                         MediaId,
-  IN EFI_LBA                        Lba,
-  IN UINTN                          BufferSize,
-  IN VOID                           *Buffer
-  )
-{
-  UINTN      BlockIndex;
-  UINTN      NumBlocks;
-  UINTN      EndBlockIndex;
-  EFI_STATUS Status;
-  UINT8      *SpareBuffer = NULL;
-
-  if (Buffer == NULL) {
-    Status = EFI_INVALID_PARAMETER;
-    goto exit;
-  }
-
-  if (Lba > LAST_BLOCK) {
-    Status = EFI_INVALID_PARAMETER;
-    goto exit;
-  }
-
-  if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
-    Status = EFI_BAD_BUFFER_SIZE;
-    goto exit;
-  }
-
-  NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
-  EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
-
-  SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
-  if (SpareBuffer == NULL) {
-    Status = EFI_OUT_OF_RESOURCES;
-    goto exit;
-  }
-
-  // Erase block
-  for (BlockIndex = (UINTN)Lba; BlockIndex <= EndBlockIndex; BlockIndex++) {
-    Status = NandEraseBlock(BlockIndex);
-    if (EFI_ERROR(Status)) {
-      DEBUG((EFI_D_ERROR, "Erase block failed. Status: %x\n", Status));
-      goto exit;
-    }
-  }
-
-  // Program data
-  Status = NandWriteBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
-  if (EFI_ERROR(Status)) {
-    DEBUG((EFI_D_ERROR, "Block write fails: %x\n", Status));
-    goto exit;
-  }
-
-exit:
-  if (SpareBuffer != NULL) {
-    FreePool (SpareBuffer);
-  }
-
-  return Status;
-}
-
-EFI_STATUS
-EFIAPI
-NandFlashFlushBlocks (
-  IN EFI_BLOCK_IO_PROTOCOL  *This
-  )
-{
-  return EFI_SUCCESS;
-}
-
-
-
-EFI_BLOCK_IO_MEDIA gNandFlashMedia = {
-  SIGNATURE_32('n','a','n','d'),            // MediaId
-  FALSE,                                    // RemovableMedia
-  TRUE,                                     // MediaPresent
-  FALSE,                                    // LogicalPartition
-  FALSE,                                    // ReadOnly
-  FALSE,                                    // WriteCaching
-  0,                                        // BlockSize
-  2,                                        // IoAlign
-  0,                                        // Pad
-  0                                         // LastBlock
-};
-
-EFI_BLOCK_IO_PROTOCOL BlockIo =
-{
-  EFI_BLOCK_IO_INTERFACE_REVISION,  // Revision
-  &gNandFlashMedia,                  // *Media
-  NandFlashReset,                   // Reset
-  NandFlashReadBlocks,              // ReadBlocks
-  NandFlashWriteBlocks,             // WriteBlocks
-  NandFlashFlushBlocks              // FlushBlocks
-};
-
-EFI_STATUS
-NandFlashInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS  Status;
-
-  gNandFlashInfo = (NAND_FLASH_INFO *)AllocateZeroPool (sizeof(NAND_FLASH_INFO));
-
-  //Initialize GPMC module.
-  GpmcInit();
-
-  //Reset NAND part
-  NandFlashReset(&BlockIo, FALSE);
-
-  //Detect NAND part and populate gNandFlashInfo structure
-  Status = NandDetectPart ();
-  if (EFI_ERROR(Status)) {
-    DEBUG((EFI_D_ERROR, "Nand part id detection failure: Status: %x\n", Status));
-    return Status;
-  }
-
-  //Count total number of 512Bytes chunk based on the page size.
-  if (gNandFlashInfo->PageSize == PAGE_SIZE_512B) {
-    gNum512BytesChunks = 1;
-  } else if (gNandFlashInfo->PageSize == PAGE_SIZE_2K) {
-    gNum512BytesChunks = 4;
-  } else if (gNandFlashInfo->PageSize == PAGE_SIZE_4K) {
-    gNum512BytesChunks = 8;
-  }
-
-  gEccCode = (UINT8 *)AllocatePool(gNum512BytesChunks * 3);
-  if (gEccCode == NULL) {
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  //Configure ECC
-  NandConfigureEcc ();
-
-  //Patch EFI_BLOCK_IO_MEDIA structure.
-  gNandFlashMedia.BlockSize = gNandFlashInfo->BlockSize;
-  gNandFlashMedia.LastBlock = LAST_BLOCK;
-
-  //Publish BlockIO.
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &ImageHandle,
-                  &gEfiBlockIoProtocolGuid, &BlockIo,
-                  &gEfiDevicePathProtocolGuid, &gDevicePath,
-                  NULL
-                  );
-  return Status;
-}
-
diff --git a/Chips/TexasInstruments/Omap35xx/Flash/Flash.h b/Chips/TexasInstruments/Omap35xx/Flash/Flash.h
deleted file mode 100644
index 46ec4db..0000000
--- a/Chips/TexasInstruments/Omap35xx/Flash/Flash.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef FLASH_H
-#define FLASH_H
-
-#include <Uefi.h>
-
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/IoLib.h>
-
-#include <Protocol/BlockIo.h>
-#include <Protocol/Cpu.h>
-#include <Omap3530/Omap3530.h>
-
-#define PAGE_SIZE(x)             ((x) & 0x01)
-#define PAGE_SIZE_2K_VAL         (0x01UL)
-
-#define SPARE_AREA_SIZE(x)       (((x) >> 2) & 0x01)
-#define SPARE_AREA_SIZE_64B_VAL  (0x1UL)
-
-#define BLOCK_SIZE(x)            (((x) >> 4) & 0x01)
-#define BLOCK_SIZE_128K_VAL      (0x01UL)
-
-#define ORGANIZATION(x)          (((x) >> 6) & 0x01)
-#define ORGANIZATION_X8          (0x0UL)
-#define ORGANIZATION_X16         (0x1UL)
-
-#define PAGE_SIZE_512B           (512)
-#define PAGE_SIZE_2K             (2048)
-#define PAGE_SIZE_4K             (4096)
-#define SPARE_AREA_SIZE_16B      (16)
-#define SPARE_AREA_SIZE_64B      (64)
-
-#define BLOCK_SIZE_16K           (16*1024)
-#define BLOCK_SIZE_128K          (128*1024)
-
-#define BLOCK_COUNT              (2048)
-#define LAST_BLOCK               (BLOCK_COUNT - 1)
-
-#define ECC_POSITION             2
-
-//List of commands.
-#define RESET_CMD                0xFF
-#define READ_ID_CMD              0x90
-
-#define READ_STATUS_CMD          0x70
-
-#define PAGE_READ_CMD            0x00
-#define PAGE_READ_CONFIRM_CMD    0x30
-
-#define BLOCK_ERASE_CMD          0x60
-#define BLOCK_ERASE_CONFIRM_CMD  0xD0
-
-#define PROGRAM_PAGE_CMD         0x80
-#define PROGRAM_PAGE_CONFIRM_CMD 0x10
-
-//Nand status register bit definition
-#define NAND_SUCCESS             (0x0UL << 0)
-#define NAND_FAILURE             BIT0
-
-#define NAND_BUSY                (0x0UL << 6)
-#define NAND_READY               BIT6
-
-#define NAND_RESET_STATUS        (0x60UL << 0)
-
-#define MAX_RETRY_COUNT          1500
-
-
-typedef struct {
-  UINT8 ManufactureId;
-  UINT8 DeviceId;
-  UINT8 BlockAddressStart; //Start of the Block address in actual NAND
-  UINT8 PageAddressStart;  //Start of the Page address in actual NAND
-} NAND_PART_INFO_TABLE;
-
-typedef struct {
-  UINT8     ManufactureId;
-  UINT8     DeviceId;
-  UINT8     Organization;      //x8 or x16
-  UINT32    PageSize;
-  UINT32    SparePageSize;
-  UINT32    BlockSize;
-  UINT32    NumPagesPerBlock;
-  UINT8     BlockAddressStart; //Start of the Block address in actual NAND
-  UINT8     PageAddressStart;  //Start of the Page address in actual NAND
-} NAND_FLASH_INFO;
-
-#endif //FLASH_H
diff --git a/Chips/TexasInstruments/Omap35xx/Flash/Flash.inf b/Chips/TexasInstruments/Omap35xx/Flash/Flash.inf
deleted file mode 100644
index 4d9b630..0000000
--- a/Chips/TexasInstruments/Omap35xx/Flash/Flash.inf
+++ /dev/null
@@ -1,48 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = NandFlash
-  FILE_GUID                      = 4d00ef14-c4e0-426b-81b7-30a00a14aad6
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = NandFlashInitialize
-
-
-[Sources.common]
-  Flash.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  PcdLib
-  UefiLib
-  UefiDriverEntryPoint
-  MemoryAllocationLib
-  IoLib
-
-[Guids]
-
-[Protocols]
-  gEfiBlockIoProtocolGuid
-  gEfiCpuArchProtocolGuid
-
-[Pcd]
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset
-
-[depex]
-  TRUE
diff --git a/Chips/TexasInstruments/Omap35xx/Gpio/Gpio.c b/Chips/TexasInstruments/Omap35xx/Gpio/Gpio.c
deleted file mode 100644
index 4d713f7..0000000
--- a/Chips/TexasInstruments/Omap35xx/Gpio/Gpio.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Uefi.h>
-
-#include <Library/IoLib.h>
-#include <Library/OmapLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Protocol/EmbeddedGpio.h>
-
-#include <Omap3530/Omap3530.h>
-
-EFI_STATUS
-Get (
-  IN  EMBEDDED_GPIO     *This,
-  IN  EMBEDDED_GPIO_PIN Gpio,
-  OUT UINTN               *Value
-  )
-{
-  UINTN  Port;
-  UINTN  Pin;
-  UINT32 DataInRegister;
-
-  if (Value == NULL)
-  {
-    return EFI_UNSUPPORTED;
-  }
-
-  Port    = GPIO_PORT(Gpio);
-  Pin     = GPIO_PIN(Gpio);
-
-  DataInRegister = GpioBase(Port) + GPIO_DATAIN;
-
-  if (MmioRead32 (DataInRegister) & GPIO_DATAIN_MASK(Pin)) {
-    *Value = 1;
-  } else {
-    *Value = 0;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-Set (
-  IN  EMBEDDED_GPIO       *This,
-  IN  EMBEDDED_GPIO_PIN   Gpio,
-  IN  EMBEDDED_GPIO_MODE  Mode
-  )
-{
-  UINTN  Port;
-  UINTN  Pin;
-  UINT32 OutputEnableRegister;
-  UINT32 SetDataOutRegister;
-  UINT32 ClearDataOutRegister;
-
-  Port    = GPIO_PORT(Gpio);
-  Pin     = GPIO_PIN(Gpio);
-
-  OutputEnableRegister = GpioBase(Port) + GPIO_OE;
-  SetDataOutRegister   = GpioBase(Port) + GPIO_SETDATAOUT;
-  ClearDataOutRegister = GpioBase(Port) + GPIO_CLEARDATAOUT;
-
-  switch (Mode)
-  {
-    case GPIO_MODE_INPUT:
-      MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin));
-      break;
-
-    case GPIO_MODE_OUTPUT_0:
-      MmioWrite32 (ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
-      MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
-      break;
-
-    case GPIO_MODE_OUTPUT_1:
-      MmioWrite32 (SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
-      MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
-      break;
-
-    default:
-      return EFI_UNSUPPORTED;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-GetMode (
-  IN  EMBEDDED_GPIO       *This,
-  IN  EMBEDDED_GPIO_PIN   Gpio,
-  OUT EMBEDDED_GPIO_MODE  *Mode
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-SetPull (
-  IN  EMBEDDED_GPIO       *This,
-  IN  EMBEDDED_GPIO_PIN   Gpio,
-  IN  EMBEDDED_GPIO_PULL  Direction
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-EMBEDDED_GPIO Gpio = {
-  Get,
-  Set,
-  GetMode,
-  SetPull
-};
-
-EFI_STATUS
-GpioInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS  Status;
-
-  Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedGpioProtocolGuid, &Gpio, NULL);
-  return Status;
-}
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Library/OmapDmaLib.h b/Chips/TexasInstruments/Omap35xx/Include/Library/OmapDmaLib.h
deleted file mode 100755
index dfac36f..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Library/OmapDmaLib.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/** @file
-
-  Abstractions for simple OMAP DMA.
-  OMAP_DMA4 structure elements are described in the OMAP35xx TRM.
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP_DMA_LIB_H__
-#define __OMAP_DMA_LIB_H__
-
-
-// Example from DMA chapter of the OMAP35xx spec
-typedef struct {
-  UINT8     DataType;                      // DMA4_CSDPi[1:0]
-  UINT8     ReadPortAccessType;            // DMA4_CSDPi[8:7]
-  UINT8     WritePortAccessType;           // DMA4_CSDPi[15:14]
-  UINT8     SourceEndiansim;               // DMA4_CSDPi[21]
-  UINT8     DestinationEndianism;          // DMA4_CSDPi[19]
-  UINT8     WriteMode;                     // DMA4_CSDPi[17:16]
-  UINT8     SourcePacked;                  // DMA4_CSDPi[6]
-  UINT8     DestinationPacked;             // DMA4_CSDPi[13]
-  UINT32    NumberOfElementPerFrame;       // DMA4_CENi
-  UINT32    NumberOfFramePerTransferBlock; // DMA4_CFNi
-  UINT32    SourceStartAddress;            // DMA4_CSSAi
-  UINT32    DestinationStartAddress;       // DMA4_CDSAi
-  UINT32    SourceElementIndex;            // DMA4_CSEi
-  UINT32    SourceFrameIndex;              // DMA4_CSFi
-  UINT32    DestinationElementIndex;       // DMA4_CDEi
-  UINT32    DestinationFrameIndex;         // DMA4_CDFi
-  UINT8     ReadPortAccessMode;            // DMA4_CCRi[13:12]
-  UINT8     WritePortAccessMode;           // DMA4_CCRi[15:14]
-  UINT8     ReadPriority;                  // DMA4_CCRi[6]
-  UINT8     WritePriority;                 // DMA4_CCRi[23]
-  UINT8     ReadRequestNumber;             // DMA4_CCRi[4:0]
-  UINT8     WriteRequestNumber;            // DMA4_CCRi[20:19]
-} OMAP_DMA4;
-
-
-/**
-  Configure OMAP DMA Channel
-
-  @param  Channel               DMA Channel to configure
-  @param  Dma4                  Pointer to structure used to initialize DMA registers for the Channel
-
-  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
-  @retval EFI_INVALID_PARAMETER Channel is not valid
-  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.
-
-**/
-EFI_STATUS
-EFIAPI
-EnableDmaChannel (
-  IN  UINTN       Channel,
-  IN  OMAP_DMA4   *Dma4
-  );
-
-/**
-  Turn of DMA channel configured by EnableDma().
-
-  @param  Channel               DMA Channel to configure
-  @param  SuccesMask            Bits in DMA4_CSR register indicate EFI_SUCCESS
-  @param  ErrorMask             Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
-
-  @retval EFI_SUCCESS           DMA hardware disabled
-  @retval EFI_INVALID_PARAMETER Channel is not valid
-  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.
-
-**/
-EFI_STATUS
-EFIAPI
-DisableDmaChannel (
-  IN  UINTN       Channel,
-  IN  UINT32      SuccessMask,
-  IN  UINT32      ErrorMask
-  );
-
-
-
-#endif
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Library/OmapLib.h b/Chips/TexasInstruments/Omap35xx/Include/Library/OmapLib.h
deleted file mode 100644
index ec14603..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Library/OmapLib.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAPLIB_H__
-#define __OMAPLIB_H__
-
-UINT32
-EFIAPI
-GpioBase (
-  IN  UINTN Port
-  );
-
-UINT32
-EFIAPI
-TimerBase (
-  IN  UINTN Timer
-  );
-
-UINTN
-EFIAPI
-InterruptVectorForTimer (
-  IN  UINTN TImer
-  );
-
-UINT32
-EFIAPI
-UartBase (
-  IN  UINTN Uart
-  );
-
-
-#endif // __OMAPLIB_H__
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530.h
deleted file mode 100644
index 4d37815..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530_H__
-#define __OMAP3530_H__
-
-#include "Omap3530Gpio.h"
-#include "Omap3530Interrupt.h"
-#include "Omap3530Prcm.h"
-#include "Omap3530Timer.h"
-#include "Omap3530Uart.h"
-#include "Omap3530Usb.h"
-#include "Omap3530MMCHS.h"
-#include "Omap3530I2c.h"
-#include "Omap3530PadConfiguration.h"
-#include "Omap3530Gpmc.h"
-#include "Omap3530Dma.h"
-
-
-//CONTROL_PBIAS_LITE
-#define CONTROL_PBIAS_LITE    0x48002520
-#define PBIASLITEVMODE0       BIT0
-#define PBIASLITEPWRDNZ0      BIT1
-#define PBIASSPEEDCTRL0       BIT2
-#define PBIASLITEVMODE1       BIT8
-#define PBIASLITEWRDNZ1       BIT9
-
-#endif // __OMAP3530_H__
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Dma.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Dma.h
deleted file mode 100755
index a6e070d..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Dma.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530DMA_H__
-#define __OMAP3530DMA_H__
-
-
-#define DMA4_MAX_CHANNEL 31
-
-#define DMA4_IRQENABLE_L(_i)  (0x48056018 + (0x4*(_i)))
-
-#define DMA4_CCR(_i)  (0x48056080 + (0x60*(_i)))
-#define DMA4_CICR(_i) (0x48056088 + (0x60*(_i)))
-#define DMA4_CSR(_i)  (0x4805608c + (0x60*(_i)))
-#define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i)))
-#define DMA4_CEN(_i)  (0x48056094 + (0x60*(_i)))
-#define DMA4_CFN(_i)  (0x48056098 + (0x60*(_i)))
-#define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i)))
-#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i)))
-#define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i)))
-#define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i)))
-#define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i)))
-#define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i)))
-
-#define DMA4_GCR      (0x48056078)
-
-// Channel Source Destination parameters
-#define DMA4_CSDP_DATA_TYPE8    0
-#define DMA4_CSDP_DATA_TYPE16   1
-#define DMA4_CSDP_DATA_TYPE32   2
-
-#define DMA4_CSDP_SRC_PACKED      BIT6
-#define DMA4_CSDP_SRC_NONPACKED   0
-
-#define DMA4_CSDP_SRC_BURST_EN    (0x0 << 7)
-#define DMA4_CSDP_SRC_BURST_EN16  (0x1 << 7)
-#define DMA4_CSDP_SRC_BURST_EN32  (0x2 << 7)
-#define DMA4_CSDP_SRC_BURST_EN64  (0x3 << 7)
-
-#define DMA4_CSDP_DST_PACKED      BIT13
-#define DMA4_CSDP_DST_NONPACKED   0
-
-#define DMA4_CSDP_BURST_EN        (0x0 << 14)
-#define DMA4_CSDP_BURST_EN16      (0x1 << 14)
-#define DMA4_CSDP_BURST_EN32      (0x2 << 14)
-#define DMA4_CSDP_BURST_EN64      (0x3 << 14)
-
-#define DMA4_CSDP_WRITE_MODE_NONE_POSTED      (0x0 << 16)
-#define DMA4_CSDP_WRITE_MODE_POSTED           (0x1 << 16)
-#define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED  (0x2 << 16)
-
-#define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK    BIT18
-#define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT   0
-
-#define DMA4_CSDP_DST_ENDIAN_BIG          BIT19
-#define DMA4_CSDP_DST_ENDIAN_LITTLE       0
-
-#define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK    BIT20
-#define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT   0
-
-#define DMA4_CSDP_SRC_ENDIAN_BIG          BIT21
-#define DMA4_CSDP_SRC_ENDIAN_LITTLE       0
-
-// Channel Control
-#define DMA4_CCR_SYNCHRO_CONTROL_MASK     0x1f
-
-#define DMA4_CCR_FS_ELEMENT     (0    | 0)
-#define DMA4_CCR_FS_BLOCK       (0    | BIT18)
-#define DMA4_CCR_FS_FRAME       (BIT5 | 0)
-#define DMA4_CCR_FS_PACKET      (BIT5 | BIT18)
-
-#define DMA4_CCR_READ_PRIORITY_HIGH   BIT6
-#define DMA4_CCR_READ_PRIORITY_LOW    0
-
-#define DMA4_CCR_ENABLE               BIT7
-#define DMA4_CCR_DISABLE              0
-
-#define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8
-#define DMA4_CCR_SUSPEND_SENSITIVE        0
-
-#define DMA4_CCR_RD_ACTIVE                BIT9
-#define DMA4_CCR_WR_ACTIVE                BIT10
-
-#define DMA4_CCR_SRC_AMODE                (0     | 0)
-#define DMA4_CCR_SRC_AMODE_POST_INC       (0     | BIT12)
-#define DMA4_CCR_SRC_AMODE_SINGLE_INDEX   (BIT13 | 0)
-#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX   (BIT13 | BIT12)
-
-#define DMA4_CCR_DST_AMODE                (0     | 0)
-#define DMA4_CCR_DST_AMODE_POST_INC       (0     | BIT14)
-#define DMA4_CCR_DST_AMODE_SINGLE_INDEX   (BIT15 | 0)
-#define DMA4_CCR_DST_AMODE_DOUBLE_INDEX   (BIT15 | BIT14)
-
-#define DMA4_CCR_CONST_FILL_ENABLE        BIT16
-#define DMA4_CCR_TRANSPARENT_COPY_ENABLE  BIT17
-
-#define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24
-
-#define DMA4_CSR_DROP                     BIT1
-#define DMA4_CSR_HALF                     BIT2
-#define DMA4_CSR_FRAME                    BIT3
-#define DMA4_CSR_LAST                     BIT4
-#define DMA4_CSR_BLOCK                    BIT5
-#define DMA4_CSR_SYNC                     BIT6
-#define DMA4_CSR_PKT                      BIT7
-#define DMA4_CSR_TRANS_ERR                BIT8
-#define DMA4_CSR_SECURE_ERR               BIT9
-#define DMA4_CSR_SUPERVISOR_ERR           BIT10
-#define DMA4_CSR_MISALIGNED_ADRS_ERR      BIT11
-#define DMA4_CSR_DRAIN_END                BIT12
-#define DMA4_CSR_RESET                    0x1FE
-#define DMA4_CSR_ERR                      (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR)
-
-// same mapping as CSR except for SYNC. Enable all since we are polling
-#define DMA4_CICR_ENABLE_ALL              0x1FBE
-
-
-#endif
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Gpio.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Gpio.h
deleted file mode 100644
index e45a0f2..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Gpio.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530GPIO_H__
-#define __OMAP3530GPIO_H__
-
-#define GPIO1_BASE (0x48310000)
-#define GPIO2_BASE (0x49050000)
-#define GPIO3_BASE (0x49052000)
-#define GPIO4_BASE (0x49054000)
-#define GPIO5_BASE (0x49056000)
-#define GPIO6_BASE (0x49058000)
-
-#define GPIO_SYSCONFIG        (0x0010)
-#define GPIO_SYSSTATUS        (0x0014)
-#define GPIO_IRQSTATUS1       (0x0018)
-#define GPIO_IRQENABLE1       (0x001C)
-#define GPIO_WAKEUPENABLE     (0x0020)
-#define GPIO_IRQSTATUS2       (0x0028)
-#define GPIO_IRQENABLE2       (0x002C)
-#define GPIO_CTRL             (0x0030)
-#define GPIO_OE               (0x0034)
-#define GPIO_DATAIN           (0x0038)
-#define GPIO_DATAOUT          (0x003C)
-#define GPIO_LEVELDETECT0     (0x0040)
-#define GPIO_LEVELDETECT1     (0x0044)
-#define GPIO_RISINGDETECT     (0x0048)
-#define GPIO_FALLINGDETECT    (0x004C)
-#define GPIO_DEBOUNCENABLE    (0x0050)
-#define GPIO_DEBOUNCINGTIME   (0x0054)
-#define GPIO_CLEARIRQENABLE1  (0x0060)
-#define GPIO_SETIRQENABLE1    (0x0064)
-#define GPIO_CLEARIRQENABLE2  (0x0070)
-#define GPIO_SETIRQENABLE2    (0x0074)
-#define GPIO_CLEARWKUENA      (0x0080)
-#define GPIO_SETWKUENA        (0x0084)
-#define GPIO_CLEARDATAOUT     (0x0090)
-#define GPIO_SETDATAOUT       (0x0094)
-
-#define GPIO_SYSCONFIG_IDLEMODE_MASK      (3UL << 3)
-#define GPIO_SYSCONFIG_IDLEMODE_FORCE     (0UL << 3)
-#define GPIO_SYSCONFIG_IDLEMODE_NONE      BIT3
-#define GPIO_SYSCONFIG_IDLEMODE_SMART     (2UL << 3)
-#define GPIO_SYSCONFIG_ENAWAKEUP_MASK     BIT2
-#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE  (0UL << 2)
-#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE   BIT2
-#define GPIO_SYSCONFIG_SOFTRESET_MASK     BIT1
-#define GPIO_SYSCONFIG_SOFTRESET_NORMAL   (0UL << 1)
-#define GPIO_SYSCONFIG_SOFTRESET_RESET    BIT1
-#define GPIO_SYSCONFIG_AUTOIDLE_MASK      BIT0
-#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN  (0UL << 0)
-#define GPIO_SYSCONFIG_AUTOIDLE_ON        BIT0
-
-#define GPIO_SYSSTATUS_RESETDONE_MASK     BIT0
-#define GPIO_SYSSTATUS_RESETDONE_ONGOING  (0UL << 0)
-#define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0
-
-#define GPIO_IRQSTATUS_MASK(x)            (1UL << (x))
-#define GPIO_IRQSTATUS_NOT_TRIGGERED(x)   (0UL << (x))
-#define GPIO_IRQSTATUS_TRIGGERED(x)       (1UL << (x))
-#define GPIO_IRQSTATUS_CLEAR(x)           (1UL << (x))
-
-#define GPIO_IRQENABLE_MASK(x)            (1UL << (x))
-#define GPIO_IRQENABLE_DISABLE(x)         (0UL << (x))
-#define GPIO_IRQENABLE_ENABLE(x)          (1UL << (x))
-
-#define GPIO_WAKEUPENABLE_MASK(x)         (1UL << (x))
-#define GPIO_WAKEUPENABLE_DISABLE(x)      (0UL << (x))
-#define GPIO_WAKEUPENABLE_ENABLE(x)       (1UL << (x))
-
-#define GPIO_CTRL_GATINGRATIO_MASK        (3UL << 1)
-#define GPIO_CTRL_GATINGRATIO_DIV_1       (0UL << 1)
-#define GPIO_CTRL_GATINGRATIO_DIV_2       BIT1
-#define GPIO_CTRL_GATINGRATIO_DIV_4       (2UL << 1)
-#define GPIO_CTRL_GATINGRATIO_DIV_8       (3UL << 1)
-#define GPIO_CTRL_DISABLEMODULE_MASK      BIT0
-#define GPIO_CTRL_DISABLEMODULE_ENABLE    (0UL << 0)
-#define GPIO_CTRL_DISABLEMODULE_DISABLE   BIT0
-
-#define GPIO_OE_MASK(x)                   (1UL << (x))
-#define GPIO_OE_OUTPUT(x)                 (0UL << (x))
-#define GPIO_OE_INPUT(x)                  (1UL << (x))
-
-#define GPIO_DATAIN_MASK(x)               (1UL << (x))
-
-#define GPIO_DATAOUT_MASK(x)              (1UL << (x))
-
-#define GPIO_LEVELDETECT_MASK(x)          (1UL << (x))
-#define GPIO_LEVELDETECT_DISABLE(x)       (0UL << (x))
-#define GPIO_LEVELDETECT_ENABLE(x)        (1UL << (x))
-
-#define GPIO_RISINGDETECT_MASK(x)         (1UL << (x))
-#define GPIO_RISINGDETECT_DISABLE(x)      (0UL << (x))
-#define GPIO_RISINGDETECT_ENABLE(x)       (1UL << (x))
-
-#define GPIO_FALLINGDETECT_MASK(x)        (1UL << (x))
-#define GPIO_FALLINGDETECT_DISABLE(x)     (0UL << (x))
-#define GPIO_FALLINGDETECT_ENABLE(x)      (1UL << (x))
-
-#define GPIO_DEBOUNCENABLE_MASK(x)        (1UL << (x))
-#define GPIO_DEBOUNCENABLE_DISABLE(x)     (0UL << (x))
-#define GPIO_DEBOUNCENABLE_ENABLE(x)      (1UL << (x))
-
-#define GPIO_DEBOUNCINGTIME_MASK          (0xFF)
-#define GPIO_DEBOUNCINGTIME_US(x)         ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)
-
-#define GPIO_CLEARIRQENABLE_BIT(x)        (1UL << (x))
-
-#define GPIO_SETIRQENABLE_BIT(x)          (1UL << (x))
-
-#define GPIO_CLEARWKUENA_BIT(x)           (1UL << (x))
-
-#define GPIO_SETWKUENA_BIT(x)             (1UL << (x))
-
-#define GPIO_CLEARDATAOUT_BIT(x)          (1UL << (x))
-
-#define GPIO_SETDATAOUT_BIT(x)            (1UL << (x))
-
-#endif // __OMAP3530GPIO_H__
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Gpmc.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Gpmc.h
deleted file mode 100644
index 6943d30..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Gpmc.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530GPMC_H__
-#define __OMAP3530GPMC_H__
-
-#define GPMC_BASE             (0x6E000000)
-
-//GPMC NAND definitions.
-#define GPMC_SYSCONFIG        (GPMC_BASE + 0x10)
-#define SMARTIDLEMODE         (0x2UL << 3)
-
-#define GPMC_SYSSTATUS        (GPMC_BASE + 0x14)
-#define GPMC_IRQSTATUS        (GPMC_BASE + 0x18)
-#define GPMC_IRQENABLE        (GPMC_BASE + 0x1C)
-
-#define GPMC_TIMEOUT_CONTROL  (GPMC_BASE + 0x40)
-#define TIMEOUTENABLE         BIT0
-#define TIMEOUTDISABLE        (0x0UL << 0)
-
-#define GPMC_ERR_ADDRESS      (GPMC_BASE + 0x44)
-#define GPMC_ERR_TYPE         (GPMC_BASE + 0x48)
-
-#define GPMC_CONFIG           (GPMC_BASE + 0x50)
-#define WRITEPROTECT_HIGH     BIT4
-#define WRITEPROTECT_LOW      (0x0UL << 4)
-
-#define GPMC_STATUS           (GPMC_BASE + 0x54)
-
-#define GPMC_CONFIG1_0        (GPMC_BASE + 0x60)
-#define DEVICETYPE_NOR        (0x0UL << 10)
-#define DEVICETYPE_NAND       (0x2UL << 10)
-#define DEVICESIZE_X8         (0x0UL << 12)
-#define DEVICESIZE_X16        BIT12
-
-#define GPMC_CONFIG2_0        (GPMC_BASE + 0x64)
-#define CSONTIME              (0x0UL << 0)
-#define CSRDOFFTIME           (0x14UL << 8)
-#define CSWROFFTIME           (0x14UL << 16)
-
-#define GPMC_CONFIG3_0        (GPMC_BASE + 0x68)
-#define ADVRDOFFTIME          (0x14UL << 8)
-#define ADVWROFFTIME          (0x14UL << 16)
-
-#define GPMC_CONFIG4_0        (GPMC_BASE + 0x6C)
-#define OEONTIME              BIT0
-#define OEOFFTIME             (0xFUL << 8)
-#define WEONTIME              BIT16
-#define WEOFFTIME             (0xFUL << 24)
-
-#define GPMC_CONFIG5_0        (GPMC_BASE + 0x70)
-#define RDCYCLETIME           (0x14UL << 0)
-#define WRCYCLETIME           (0x14UL << 8)
-#define RDACCESSTIME          (0xCUL << 16)
-#define PAGEBURSTACCESSTIME   BIT24
-
-#define GPMC_CONFIG6_0        (GPMC_BASE + 0x74)
-#define CYCLE2CYCLESAMECSEN   BIT7
-#define CYCLE2CYCLEDELAY      (0xAUL << 8)
-#define WRDATAONADMUXBUS      (0xFUL << 16)
-#define WRACCESSTIME          BIT24
-
-#define GPMC_CONFIG7_0        (GPMC_BASE + 0x78)
-#define BASEADDRESS           (0x30UL << 0)
-#define CSVALID               BIT6
-#define MASKADDRESS_128MB     (0x8UL << 8)
-
-#define GPMC_NAND_COMMAND_0   (GPMC_BASE + 0x7C)
-#define GPMC_NAND_ADDRESS_0   (GPMC_BASE + 0x80)
-#define GPMC_NAND_DATA_0      (GPMC_BASE + 0x84)
-
-#define GPMC_ECC_CONFIG       (GPMC_BASE + 0x1F4)
-#define ECCENABLE             BIT0
-#define ECCDISABLE            (0x0UL << 0)
-#define ECCCS_0               (0x0UL << 1)
-#define ECC16B                BIT7
-
-#define GPMC_ECC_CONTROL      (GPMC_BASE + 0x1F8)
-#define ECCPOINTER_REG1       BIT0
-#define ECCCLEAR              BIT8
-
-#define GPMC_ECC_SIZE_CONFIG  (GPMC_BASE + 0x1FC)
-#define ECCSIZE0_512BYTES     (0xFFUL << 12)
-#define ECCSIZE1_512BYTES     (0xFFUL << 22)
-
-#define GPMC_ECC1_RESULT      (GPMC_BASE + 0x200)
-#define GPMC_ECC2_RESULT      (GPMC_BASE + 0x204)
-#define GPMC_ECC3_RESULT      (GPMC_BASE + 0x208)
-#define GPMC_ECC4_RESULT      (GPMC_BASE + 0x20C)
-#define GPMC_ECC5_RESULT      (GPMC_BASE + 0x210)
-#define GPMC_ECC6_RESULT      (GPMC_BASE + 0x214)
-#define GPMC_ECC7_RESULT      (GPMC_BASE + 0x218)
-#define GPMC_ECC8_RESULT      (GPMC_BASE + 0x21C)
-#define GPMC_ECC9_RESULT      (GPMC_BASE + 0x220)
-
-#endif //__OMAP3530GPMC_H__
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530I2c.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530I2c.h
deleted file mode 100644
index 31d4d5e..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530I2c.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530I2C_H__
-#define __OMAP3530I2C_H__
-
-//I2C register definitions.
-#define I2C1BASE        0x48070000
-
-#define I2C_IE          (I2C1BASE + 0x4)
-#define XRDY_IE         BIT4
-#define RRDY_IE         BIT3
-#define ARDY_IE         BIT2
-#define NACK_IE         BIT1
-
-#define I2C_STAT        (I2C1BASE + 0x8)
-#define BB              BIT12
-#define XRDY            BIT4
-#define RRDY            BIT3
-#define ARDY            BIT2
-#define NACK            BIT1
-
-#define I2C_WE          (I2C1BASE + 0xC)
-#define I2C_SYSS        (I2C1BASE + 0x10)
-#define I2C_BUF         (I2C1BASE + 0x14)
-#define I2C_CNT         (I2C1BASE + 0x18)
-#define I2C_DATA        (I2C1BASE + 0x1C)
-#define I2C_SYSC        (I2C1BASE + 0x20)
-
-#define I2C_CON         (I2C1BASE + 0x24)
-#define STT             BIT0
-#define STP             BIT1
-#define XSA             BIT8
-#define TRX             BIT9
-#define MST             BIT10
-#define I2C_EN          BIT15
-
-#define I2C_OA0         (I2C1BASE + 0x28)
-#define I2C_SA          (I2C1BASE + 0x2C)
-#define I2C_PSC         (I2C1BASE + 0x30)
-#define I2C_SCLL        (I2C1BASE + 0x34)
-#define I2C_SCLH        (I2C1BASE + 0x38)
-#define I2C_SYSTEST     (I2C1BASE + 0x3C)
-#define I2C_BUFSTAT     (I2C1BASE + 0x40)
-#define I2C_OA1         (I2C1BASE + 0x44)
-#define I2C_OA2         (I2C1BASE + 0x48)
-#define I2C_OA3         (I2C1BASE + 0x4C)
-#define I2C_ACTOA       (I2C1BASE + 0x50)
-#define I2C_SBLOCK      (I2C1BASE + 0x54)
-
-#endif //__OMAP3530I2C_H__
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Interrupt.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Interrupt.h
deleted file mode 100644
index 774d873..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Interrupt.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530INTERRUPT_H__
-#define __OMAP3530INTERRUPT_H__
-
-#define INTERRUPT_BASE (0x48200000)
-
-#define INT_NROF_VECTORS      (96)
-#define MAX_VECTOR            (INT_NROF_VECTORS - 1)
-#define INTCPS_SYSCONFIG      (INTERRUPT_BASE + 0x0010)
-#define INTCPS_SYSSTATUS      (INTERRUPT_BASE + 0x0014)
-#define INTCPS_SIR_IRQ        (INTERRUPT_BASE + 0x0040)
-#define INTCPS_SIR_IFQ        (INTERRUPT_BASE + 0x0044)
-#define INTCPS_CONTROL        (INTERRUPT_BASE + 0x0048)
-#define INTCPS_PROTECTION     (INTERRUPT_BASE + 0x004C)
-#define INTCPS_IDLE           (INTERRUPT_BASE + 0x0050)
-#define INTCPS_IRQ_PRIORITY   (INTERRUPT_BASE + 0x0060)
-#define INTCPS_FIQ_PRIORITY   (INTERRUPT_BASE + 0x0064)
-#define INTCPS_THRESHOLD      (INTERRUPT_BASE + 0x0068)
-#define INTCPS_ITR(n)         (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))
-#define INTCPS_MIR(n)         (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))
-#define INTCPS_MIR_CLEAR(n)   (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))
-#define INTCPS_MIR_SET(n)     (INTERRUPT_BASE + 0x008C + (0x20 * (n)))
-#define INTCPS_ISR_SET(n)     (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))
-#define INTCPS_ISR_CLEAR(n)   (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))
-#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))
-#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
-#define INTCPS_ILR(m)         (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
-
-#define INTCPS_ILR_FIQ            BIT0
-#define INTCPS_SIR_IRQ_MASK       (0x7F)
-#define INTCPS_CONTROL_NEWIRQAGR  BIT0
-#define INTCPS_CONTROL_NEWFIQAGR  BIT1
-
-#endif // __OMAP3530INTERRUPT_H__
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530MMCHS.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530MMCHS.h
deleted file mode 100644
index 88b43de..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530MMCHS.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530SDIO_H__
-#define __OMAP3530SDIO_H__
-
-//MMC/SD/SDIO1 register definitions.
-#define MMCHS1BASE        0x4809C000
-#define MMC_REFERENCE_CLK (96000000)
-
-#define MMCHS_SYSCONFIG   (MMCHS1BASE + 0x10)
-#define SOFTRESET         BIT1
-#define ENAWAKEUP         BIT2
-
-#define MMCHS_SYSSTATUS   (MMCHS1BASE + 0x14)
-#define RESETDONE_MASK    BIT0
-#define RESETDONE         BIT0
-
-#define MMCHS_CSRE        (MMCHS1BASE + 0x24)
-#define MMCHS_SYSTEST     (MMCHS1BASE + 0x28)
-
-#define MMCHS_CON         (MMCHS1BASE + 0x2C)
-#define OD                BIT0
-#define NOINIT            (0x0UL << 1)
-#define INIT              BIT1
-#define HR                BIT2
-#define STR               BIT3
-#define MODE              BIT4
-#define DW8_1_4_BIT       (0x0UL << 5)
-#define DW8_8_BIT         BIT5
-#define MIT               BIT6
-#define CDP               BIT7
-#define WPP               BIT8
-#define CTPL              BIT11
-#define CEATA_OFF         (0x0UL << 12)
-#define CEATA_ON          BIT12
-
-#define MMCHS_PWCNT       (MMCHS1BASE + 0x30)
-
-#define MMCHS_BLK         (MMCHS1BASE + 0x104)
-#define BLEN_512BYTES     (0x200UL << 0)
-
-#define MMCHS_ARG         (MMCHS1BASE + 0x108)
-
-#define MMCHS_CMD         (MMCHS1BASE + 0x10C)
-#define DE_ENABLE         BIT0
-#define BCE_ENABLE        BIT1
-#define ACEN_ENABLE       BIT2
-#define DDIR_READ         BIT4
-#define DDIR_WRITE        (0x0UL << 4)
-#define MSBS_SGLEBLK      (0x0UL << 5)
-#define MSBS_MULTBLK      BIT5
-#define RSP_TYPE_MASK     (0x3UL << 16)
-#define RSP_TYPE_136BITS  BIT16
-#define RSP_TYPE_48BITS   (0x2UL << 16)
-#define CCCE_ENABLE       BIT19
-#define CICE_ENABLE       BIT20
-#define DP_ENABLE         BIT21
-#define INDX(CMD_INDX)    ((CMD_INDX & 0x3F) << 24)
-
-#define MMCHS_RSP10       (MMCHS1BASE + 0x110)
-#define MMCHS_RSP32       (MMCHS1BASE + 0x114)
-#define MMCHS_RSP54       (MMCHS1BASE + 0x118)
-#define MMCHS_RSP76       (MMCHS1BASE + 0x11C)
-#define MMCHS_DATA        (MMCHS1BASE + 0x120)
-
-#define MMCHS_PSTATE      (MMCHS1BASE + 0x124)
-#define CMDI_MASK         BIT0
-#define CMDI_ALLOWED      (0x0UL << 0)
-#define CMDI_NOT_ALLOWED  BIT0
-#define DATI_MASK         BIT1
-#define DATI_ALLOWED      (0x0UL << 1)
-#define DATI_NOT_ALLOWED  BIT1
-
-#define MMCHS_HCTL        (MMCHS1BASE + 0x128)
-#define DTW_1_BIT         (0x0UL << 1)
-#define DTW_4_BIT         BIT1
-#define SDBP_MASK         BIT8
-#define SDBP_OFF          (0x0UL << 8)
-#define SDBP_ON           BIT8
-#define SDVS_1_8_V        (0x5UL << 9)
-#define SDVS_3_0_V        (0x6UL << 9)
-#define IWE               BIT24
-
-#define MMCHS_SYSCTL      (MMCHS1BASE + 0x12C)
-#define ICE               BIT0
-#define ICS_MASK          BIT1
-#define ICS               BIT1
-#define CEN               BIT2
-#define CLKD_MASK         (0x3FFUL << 6)
-#define CLKD_80KHZ        (0x258UL) //(96*1000/80)/2
-#define CLKD_400KHZ       (0xF0UL)
-#define DTO_MASK          (0xFUL << 16)
-#define DTO_VAL           (0xEUL << 16)
-#define SRA               BIT24
-#define SRC_MASK          BIT25
-#define SRC               BIT25
-#define SRD               BIT26
-
-#define MMCHS_STAT        (MMCHS1BASE + 0x130)
-#define CC                BIT0
-#define TC                BIT1
-#define BWR               BIT4
-#define BRR               BIT5
-#define ERRI              BIT15
-#define CTO               BIT16
-#define DTO               BIT20
-#define DCRC              BIT21
-#define DEB               BIT22
-
-#define MMCHS_IE          (MMCHS1BASE + 0x134)
-#define CC_EN             BIT0
-#define TC_EN             BIT1
-#define BWR_EN            BIT4
-#define BRR_EN            BIT5
-#define CTO_EN            BIT16
-#define CCRC_EN           BIT17
-#define CEB_EN            BIT18
-#define CIE_EN            BIT19
-#define DTO_EN            BIT20
-#define DCRC_EN           BIT21
-#define DEB_EN            BIT22
-#define CERR_EN           BIT28
-#define BADA_EN           BIT29
-
-#define MMCHS_ISE         (MMCHS1BASE + 0x138)
-#define CC_SIGEN          BIT0
-#define TC_SIGEN          BIT1
-#define BWR_SIGEN         BIT4
-#define BRR_SIGEN         BIT5
-#define CTO_SIGEN         BIT16
-#define CCRC_SIGEN        BIT17
-#define CEB_SIGEN         BIT18
-#define CIE_SIGEN         BIT19
-#define DTO_SIGEN         BIT20
-#define DCRC_SIGEN        BIT21
-#define DEB_SIGEN         BIT22
-#define CERR_SIGEN        BIT28
-#define BADA_SIGEN        BIT29
-
-#define MMCHS_AC12        (MMCHS1BASE + 0x13C)
-
-#define MMCHS_CAPA        (MMCHS1BASE + 0x140)
-#define VS30              BIT25
-#define VS18              BIT26
-
-#define MMCHS_CUR_CAPA    (MMCHS1BASE + 0x148)
-#define MMCHS_REV         (MMCHS1BASE + 0x1FC)
-
-#define CMD0              INDX(0)
-#define CMD0_INT_EN       (CC_EN | CEB_EN)
-
-#define CMD1              (INDX(1) | RSP_TYPE_48BITS)
-#define CMD1_INT_EN       (CC_EN | CEB_EN | CTO_EN)
-
-#define CMD2              (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
-#define CMD2_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#define CMD3              (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
-#define CMD3_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#define CMD5              (INDX(5) | RSP_TYPE_48BITS)
-#define CMD5_INT_EN       (CC_EN | CEB_EN | CTO_EN)
-
-#define CMD7              (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
-#define CMD7_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#define CMD8              (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
-#define CMD8_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
-#define CMD8_ARG          (0x0UL << 12 | BIT8 | 0xCEUL << 0)
-
-#define CMD9              (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
-#define CMD9_INT_EN       (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#define CMD16             (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
-#define CMD16_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#define CMD17             (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
-#define CMD17_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
-
-#define CMD18             (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
-#define CMD18_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
-
-#define CMD23             (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
-#define CMD23_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#define CMD24             (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
-#define CMD24_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
-
-#define CMD25             (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
-#define CMD25_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
-
-#define CMD55             (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
-#define CMD55_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#define ACMD41            (INDX(41) | RSP_TYPE_48BITS)
-#define ACMD41_INT_EN     (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#define ACMD6             (INDX(6) | RSP_TYPE_48BITS)
-#define ACMD6_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
-
-#endif //__OMAP3530SDIO_H__
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530PadConfiguration.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530PadConfiguration.h
deleted file mode 100644
index 1588e1d..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530PadConfiguration.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530_PAD_CONFIGURATION_H__
-#define __OMAP3530_PAD_CONFIGURATION_H__
-
-#define SYSTEM_CONTROL_MODULE_BASE  0x48002000
-
-//Pin definition
-#define SDRC_D0             (SYSTEM_CONTROL_MODULE_BASE + 0x030)
-#define SDRC_D1             (SYSTEM_CONTROL_MODULE_BASE + 0x032)
-#define SDRC_D2             (SYSTEM_CONTROL_MODULE_BASE + 0x034)
-#define SDRC_D3             (SYSTEM_CONTROL_MODULE_BASE + 0x036)
-#define SDRC_D4             (SYSTEM_CONTROL_MODULE_BASE + 0x038)
-#define SDRC_D5             (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
-#define SDRC_D6             (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
-#define SDRC_D7             (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
-#define SDRC_D8             (SYSTEM_CONTROL_MODULE_BASE + 0x040)
-#define SDRC_D9             (SYSTEM_CONTROL_MODULE_BASE + 0x042)
-#define SDRC_D10            (SYSTEM_CONTROL_MODULE_BASE + 0x044)
-#define SDRC_D11            (SYSTEM_CONTROL_MODULE_BASE + 0x046)
-#define SDRC_D12            (SYSTEM_CONTROL_MODULE_BASE + 0x048)
-#define SDRC_D13            (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
-#define SDRC_D14            (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
-#define SDRC_D15            (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
-#define SDRC_D16            (SYSTEM_CONTROL_MODULE_BASE + 0x050)
-#define SDRC_D17            (SYSTEM_CONTROL_MODULE_BASE + 0x052)
-#define SDRC_D18            (SYSTEM_CONTROL_MODULE_BASE + 0x054)
-#define SDRC_D19            (SYSTEM_CONTROL_MODULE_BASE + 0x056)
-#define SDRC_D20            (SYSTEM_CONTROL_MODULE_BASE + 0x058)
-#define SDRC_D21            (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
-#define SDRC_D22            (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
-#define SDRC_D23            (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
-#define SDRC_D24            (SYSTEM_CONTROL_MODULE_BASE + 0x060)
-#define SDRC_D25            (SYSTEM_CONTROL_MODULE_BASE + 0x062)
-#define SDRC_D26            (SYSTEM_CONTROL_MODULE_BASE + 0x064)
-#define SDRC_D27            (SYSTEM_CONTROL_MODULE_BASE + 0x066)
-#define SDRC_D28            (SYSTEM_CONTROL_MODULE_BASE + 0x068)
-#define SDRC_D29            (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
-#define SDRC_D30            (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
-#define SDRC_D31            (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
-#define SDRC_CLK            (SYSTEM_CONTROL_MODULE_BASE + 0x070)
-#define SDRC_DQS0           (SYSTEM_CONTROL_MODULE_BASE + 0x072)
-#define SDRC_CKE0           (SYSTEM_CONTROL_MODULE_BASE + 0x262)
-#define SDRC_CKE1           (SYSTEM_CONTROL_MODULE_BASE + 0x264)
-#define SDRC_DQS1           (SYSTEM_CONTROL_MODULE_BASE + 0x074)
-#define SDRC_DQS2           (SYSTEM_CONTROL_MODULE_BASE + 0x076)
-#define SDRC_DQS3           (SYSTEM_CONTROL_MODULE_BASE + 0x078)
-#define GPMC_A1             (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
-#define GPMC_A2             (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
-#define GPMC_A3             (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
-#define GPMC_A4             (SYSTEM_CONTROL_MODULE_BASE + 0x080)
-#define GPMC_A5             (SYSTEM_CONTROL_MODULE_BASE + 0x082)
-#define GPMC_A6             (SYSTEM_CONTROL_MODULE_BASE + 0x084)
-#define GPMC_A7             (SYSTEM_CONTROL_MODULE_BASE + 0x086)
-#define GPMC_A8             (SYSTEM_CONTROL_MODULE_BASE + 0x088)
-#define GPMC_A9             (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
-#define GPMC_A10            (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
-#define GPMC_D0             (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
-#define GPMC_D1             (SYSTEM_CONTROL_MODULE_BASE + 0x090)
-#define GPMC_D2             (SYSTEM_CONTROL_MODULE_BASE + 0x092)
-#define GPMC_D3             (SYSTEM_CONTROL_MODULE_BASE + 0x094)
-#define GPMC_D4             (SYSTEM_CONTROL_MODULE_BASE + 0x096)
-#define GPMC_D5             (SYSTEM_CONTROL_MODULE_BASE + 0x098)
-#define GPMC_D6             (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
-#define GPMC_D7             (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
-#define GPMC_D8             (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
-#define GPMC_D9             (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
-#define GPMC_D10            (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
-#define GPMC_D11            (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
-#define GPMC_D12            (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
-#define GPMC_D13            (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
-#define GPMC_D14            (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
-#define GPMC_D15            (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
-#define GPMC_NCS0           (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
-#define GPMC_NCS1           (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
-#define GPMC_NCS2           (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
-#define GPMC_NCS3           (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
-#define GPMC_NCS4           (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
-#define GPMC_NCS5           (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
-#define GPMC_NCS6           (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
-#define GPMC_NCS7           (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
-#define GPMC_CLK            (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
-#define GPMC_NADV_ALE       (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
-#define GPMC_NOE            (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
-#define GPMC_NWE            (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
-#define GPMC_NBE0_CLE       (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
-#define GPMC_NBE1           (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
-#define GPMC_NWP            (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
-#define GPMC_WAIT0          (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
-#define GPMC_WAIT1          (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
-#define GPMC_WAIT2          (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
-#define GPMC_WAIT3          (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
-#define DSS_PCLK            (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
-#define DSS_HSYNC           (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
-#define DSS_PSYNC           (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
-#define DSS_ACBIAS          (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
-#define DSS_DATA0           (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
-#define DSS_DATA1           (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
-#define DSS_DATA2           (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
-#define DSS_DATA3           (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
-#define DSS_DATA4           (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
-#define DSS_DATA5           (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
-#define DSS_DATA6           (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
-#define DSS_DATA7           (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
-#define DSS_DATA8           (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
-#define DSS_DATA9           (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
-#define DSS_DATA10          (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
-#define DSS_DATA11          (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
-#define DSS_DATA12          (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
-#define DSS_DATA13          (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
-#define DSS_DATA14          (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
-#define DSS_DATA15          (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
-#define DSS_DATA16          (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
-#define DSS_DATA17          (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
-#define DSS_DATA18          (SYSTEM_CONTROL_MODULE_BASE + 0x100)
-#define DSS_DATA19          (SYSTEM_CONTROL_MODULE_BASE + 0x102)
-#define DSS_DATA20          (SYSTEM_CONTROL_MODULE_BASE + 0x104)
-#define DSS_DATA21          (SYSTEM_CONTROL_MODULE_BASE + 0x106)
-#define DSS_DATA22          (SYSTEM_CONTROL_MODULE_BASE + 0x108)
-#define DSS_DATA23          (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
-#define CAM_HS              (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
-#define CAM_VS              (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
-#define CAM_XCLKA           (SYSTEM_CONTROL_MODULE_BASE + 0x110)
-#define CAM_PCLK            (SYSTEM_CONTROL_MODULE_BASE + 0x112)
-#define CAM_FLD             (SYSTEM_CONTROL_MODULE_BASE + 0x114)
-#define CAM_D0              (SYSTEM_CONTROL_MODULE_BASE + 0x116)
-#define CAM_D1              (SYSTEM_CONTROL_MODULE_BASE + 0x118)
-#define CAM_D2              (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
-#define CAM_D3              (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
-#define CAM_D4              (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
-#define CAM_D5              (SYSTEM_CONTROL_MODULE_BASE + 0x120)
-#define CAM_D6              (SYSTEM_CONTROL_MODULE_BASE + 0x122)
-#define CAM_D7              (SYSTEM_CONTROL_MODULE_BASE + 0x124)
-#define CAM_D8              (SYSTEM_CONTROL_MODULE_BASE + 0x126)
-#define CAM_D9              (SYSTEM_CONTROL_MODULE_BASE + 0x128)
-#define CAM_D10             (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
-#define CAM_D11             (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
-#define CAM_XCLKB           (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
-#define CAM_WEN             (SYSTEM_CONTROL_MODULE_BASE + 0x130)
-#define CAM_STROBE          (SYSTEM_CONTROL_MODULE_BASE + 0x132)
-#define CSI2_DX0            (SYSTEM_CONTROL_MODULE_BASE + 0x134)
-#define CSI2_DY0            (SYSTEM_CONTROL_MODULE_BASE + 0x136)
-#define CSI2_DX1            (SYSTEM_CONTROL_MODULE_BASE + 0x138)
-#define CSI2_DY1            (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
-#define MCBSP2_FSX          (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
-#define MCBSP2_CLKX         (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
-#define MCBSP2_DR           (SYSTEM_CONTROL_MODULE_BASE + 0x140)
-#define MCBSP2_DX           (SYSTEM_CONTROL_MODULE_BASE + 0x142)
-#define MMC1_CLK            (SYSTEM_CONTROL_MODULE_BASE + 0x144)
-#define MMC1_CMD            (SYSTEM_CONTROL_MODULE_BASE + 0x146)
-#define MMC1_DAT0           (SYSTEM_CONTROL_MODULE_BASE + 0x148)
-#define MMC1_DAT1           (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
-#define MMC1_DAT2           (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
-#define MMC1_DAT3           (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
-#define MMC1_DAT4           (SYSTEM_CONTROL_MODULE_BASE + 0x150)
-#define MMC1_DAT5           (SYSTEM_CONTROL_MODULE_BASE + 0x152)
-#define MMC1_DAT6           (SYSTEM_CONTROL_MODULE_BASE + 0x154)
-#define MMC1_DAT7           (SYSTEM_CONTROL_MODULE_BASE + 0x156)
-#define MMC2_CLK            (SYSTEM_CONTROL_MODULE_BASE + 0x158)
-#define MMC2_CMD            (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
-#define MMC2_DAT0           (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
-#define MMC2_DAT1           (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
-#define MMC2_DAT2           (SYSTEM_CONTROL_MODULE_BASE + 0x160)
-#define MMC2_DAT3           (SYSTEM_CONTROL_MODULE_BASE + 0x162)
-#define MMC2_DAT4           (SYSTEM_CONTROL_MODULE_BASE + 0x164)
-#define MMC2_DAT5           (SYSTEM_CONTROL_MODULE_BASE + 0x166)
-#define MMC2_DAT6           (SYSTEM_CONTROL_MODULE_BASE + 0x168)
-#define MMC2_DAT7           (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
-#define MCBSP3_DX           (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
-#define MCBSP3_DR           (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
-#define MCBSP3_CLKX         (SYSTEM_CONTROL_MODULE_BASE + 0x170)
-#define MCBSP3_FSX          (SYSTEM_CONTROL_MODULE_BASE + 0x172)
-#define UART2_CTS           (SYSTEM_CONTROL_MODULE_BASE + 0x174)
-#define UART2_RTS           (SYSTEM_CONTROL_MODULE_BASE + 0x176)
-#define UART2_TX            (SYSTEM_CONTROL_MODULE_BASE + 0x178)
-#define UART2_RX            (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
-#define UART1_TX            (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
-#define UART1_RTS           (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
-#define UART1_CTS           (SYSTEM_CONTROL_MODULE_BASE + 0x180)
-#define UART1_RX            (SYSTEM_CONTROL_MODULE_BASE + 0x182)
-#define MCBSP4_CLKX         (SYSTEM_CONTROL_MODULE_BASE + 0x184)
-#define MCBSP4_DR           (SYSTEM_CONTROL_MODULE_BASE + 0x186)
-#define MCBSP4_DX           (SYSTEM_CONTROL_MODULE_BASE + 0x188)
-#define MCBSP4_FSX          (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
-#define MCBSP1_CLKR         (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
-#define MCBSP1_FSR          (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
-#define MCBSP1_DX           (SYSTEM_CONTROL_MODULE_BASE + 0x190)
-#define MCBSP1_DR           (SYSTEM_CONTROL_MODULE_BASE + 0x192)
-#define MCBSP1_CLKS         (SYSTEM_CONTROL_MODULE_BASE + 0x194)
-#define MCBSP1_FSX          (SYSTEM_CONTROL_MODULE_BASE + 0x196)
-#define MCBSP1_CLKX         (SYSTEM_CONTROL_MODULE_BASE + 0x198)
-#define UART3_CTS_RCTX      (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
-#define UART3_RTS_SD        (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
-#define UART3_RX_IRRX       (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
-#define UART3_TX_IRTX       (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
-#define HSUSB0_CLK          (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
-#define HSUSB0_STP          (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
-#define HSUSB0_DIR          (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
-#define HSUSB0_NXT          (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
-#define HSUSB0_DATA0        (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
-#define HSUSB0_DATA1        (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
-#define HSUSB0_DATA2        (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
-#define HSUSB0_DATA3        (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
-#define HSUSB0_DATA4        (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
-#define HSUSB0_DATA5        (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
-#define HSUSB0_DATA6        (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
-#define HSUSB0_DATA7        (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
-#define I2C1_SCL            (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
-#define I2C1_SDA            (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
-#define I2C2_SCL            (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
-#define I2C2_SDA            (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
-#define I2C3_SCL            (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
-#define I2C3_SDA            (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
-#define HDQ_SIO             (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
-#define MCSPI1_CLK          (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
-#define MCSPI1_SIMO         (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
-#define MCSPI1_SOMI         (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
-#define MCSPI1_CS0          (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
-#define MCSPI1_CS1          (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
-#define MCSPI1_CS2          (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
-#define MCSPI1_CS3          (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
-#define MCSPI2_CLK          (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
-#define MCSPI2_SIMO         (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
-#define MCSPI2_SOMI         (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
-#define MCSPI2_CS0          (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
-#define MCSPI2_CS1          (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
-#define SYS_NIRQ            (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
-#define SYS_CLKOUT2         (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
-#define ETK_CLK             (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
-#define ETK_CTL             (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
-#define ETK_D0              (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
-#define ETK_D1              (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
-#define ETK_D2              (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
-#define ETK_D3              (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
-#define ETK_D4              (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
-#define ETK_D5              (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
-#define ETK_D6              (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
-#define ETK_D7              (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
-#define ETK_D8              (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
-#define ETK_D9              (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
-#define ETK_D10             (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
-#define ETK_D11             (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
-#define ETK_D12             (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
-#define ETK_D13             (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
-#define ETK_D14             (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
-#define ETK_D15             (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
-#define SYS_BOOT0           (SYSTEM_CONTROL_MODULE_BASE + 0xA0A)
-#define SYS_BOOT1           (SYSTEM_CONTROL_MODULE_BASE + 0xA0C)
-#define SYS_BOOT3           (SYSTEM_CONTROL_MODULE_BASE + 0xA10)
-#define SYS_BOOT4           (SYSTEM_CONTROL_MODULE_BASE + 0xA12)
-#define SYS_BOOT5           (SYSTEM_CONTROL_MODULE_BASE + 0xA14)
-#define SYS_BOOT6           (SYSTEM_CONTROL_MODULE_BASE + 0xA16)
-
-//Mux modes
-#define MUXMODE0            (0x0UL)
-#define MUXMODE1            (0x1UL)
-#define MUXMODE2            (0x2UL)
-#define MUXMODE3            (0x3UL)
-#define MUXMODE4            (0x4UL)
-#define MUXMODE5            (0x5UL)
-#define MUXMODE6            (0x6UL)
-#define MUXMODE7            (0x7UL)
-
-//Pad configuration register.
-#define PAD_CONFIG_MASK      (0xFFFFUL)
-#define MUXMODE_OFFSET       0
-#define MUXMODE_MASK         (0x7UL << MUXMODE_OFFSET)
-#define PULL_CONFIG_OFFSET   3
-#define PULL_CONFIG_MASK     (0x3UL << PULL_CONFIG_OFFSET)
-#define INPUTENABLE_OFFSET   8
-#define INPUTENABLE_MASK     (0x1UL << INPUTENABLE_OFFSET)
-#define OFFMODE_VALUE_OFFSET 9
-#define OFFMODE_VALUE_MASK   (0x1FUL << OFFMODE_VALUE_OFFSET)
-#define WAKEUP_OFFSET        14
-#define WAKEUP_MASK          (0x2UL << WAKEUP_OFFSET)
-
-#define PULL_DOWN_SELECTED   ((0x0UL << 1) | BIT0)
-#define PULL_UP_SELECTED     (BIT1 | BIT0)
-#define PULL_DISABLED        (0x0UL << 0)
-
-#define OUTPUT               (0x0UL) //Pin is configured in output only mode.
-#define INPUT                (0x1UL) //Pin is configured in bi-directional mode.
-
-typedef struct {
-  UINTN   Pin;
-  UINTN   MuxMode;
-  UINTN   PullConfig;
-  UINTN   InputEnable;
-} PAD_CONFIGURATION;
-
-#endif //__OMAP3530_PAD_CONFIGURATION_H__
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Prcm.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Prcm.h
deleted file mode 100644
index 1871dbb..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Prcm.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530PRCM_H__
-#define __OMAP3530PRCM_H__
-
-#define CM_FCLKEN1_CORE   (0x48004A00)
-#define CM_FCLKEN3_CORE   (0x48004A08)
-#define CM_ICLKEN1_CORE   (0x48004A10)
-#define CM_ICLKEN3_CORE   (0x48004A18)
-#define CM_CLKEN2_PLL     (0x48004D04)
-#define CM_CLKSEL4_PLL    (0x48004D4C)
-#define CM_CLKSEL5_PLL    (0x48004D50)
-#define CM_FCLKEN_USBHOST  (0x48005400)
-#define CM_ICLKEN_USBHOST  (0x48005410)
-#define CM_CLKSTST_USBHOST (0x4800544c)
-
-//Wakeup clock defintion
-#define CM_FCLKEN_WKUP    (0x48004C00)
-#define CM_ICLKEN_WKUP    (0x48004C10)
-
-//Peripheral clock definition
-#define CM_FCLKEN_PER     (0x48005000)
-#define CM_ICLKEN_PER     (0x48005010)
-#define CM_CLKSEL_PER     (0x48005040)
-
-//Reset management definition
-#define PRM_RSTCTRL       (0x48307250)
-#define PRM_RSTST         (0x48307258)
-
-//CORE clock
-#define CM_FCLKEN1_CORE_EN_I2C1_MASK    BIT15
-#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
-#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE  BIT15
-
-#define CM_ICLKEN1_CORE_EN_I2C1_MASK    BIT15
-#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
-#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE  BIT15
-
-#define CM_FCLKEN1_CORE_EN_MMC1_MASK    BIT24
-#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
-#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE  BIT24
-
-#define CM_FCLKEN3_CORE_EN_USBTLL_MASK    BIT2
-#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
-#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE  BIT2
-
-#define CM_ICLKEN1_CORE_EN_MMC1_MASK    BIT24
-#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
-#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE  BIT24
-
-#define CM_ICLKEN3_CORE_EN_USBTLL_MASK    BIT2
-#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
-#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE  BIT2
-
-#define CM_CLKEN_FREQSEL_075_100        (0x03UL << 4)
-#define CM_CLKEN_ENABLE                 (7UL << 0)
-
-#define CM_CLKSEL_PLL_MULT(x)           (((x) & 0x07FF) << 8)
-#define CM_CLKSEL_PLL_DIV(x)            ((((x) - 1) & 0x7F) << 0)
-
-#define CM_CLKSEL_DIV_120M(x)           (((x) & 0x1F) << 0)
-
-#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK    BIT1
-#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
-#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE  BIT1
-
-#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK    BIT0
-#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
-#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE  BIT0
-
-#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK     BIT0
-#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE  (0UL << 0)
-#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE   BIT0
-
-//Wakeup functional clock
-#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE       (0UL << 3)
-#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE        BIT3
-
-#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE        (0UL << 5)
-#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE         BIT5
-
-//Wakeup interface clock
-#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE       (0UL << 3)
-#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE        BIT3
-
-#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE        (0UL << 5)
-#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE         BIT5
-
-//Peripheral functional clock
-#define CM_FCLKEN_PER_EN_GPT3_DISABLE         (0UL << 4)
-#define CM_FCLKEN_PER_EN_GPT3_ENABLE          BIT4
-
-#define CM_FCLKEN_PER_EN_GPT4_DISABLE         (0UL << 5)
-#define CM_FCLKEN_PER_EN_GPT4_ENABLE          BIT5
-
-#define CM_FCLKEN_PER_EN_UART3_DISABLE        (0UL << 11)
-#define CM_FCLKEN_PER_EN_UART3_ENABLE         BIT11
-
-#define CM_FCLKEN_PER_EN_GPIO2_DISABLE        (0UL << 13)
-#define CM_FCLKEN_PER_EN_GPIO2_ENABLE         BIT13
-
-#define CM_FCLKEN_PER_EN_GPIO3_DISABLE        (0UL << 14)
-#define CM_FCLKEN_PER_EN_GPIO3_ENABLE         BIT14
-
-#define CM_FCLKEN_PER_EN_GPIO4_DISABLE        (0UL << 15)
-#define CM_FCLKEN_PER_EN_GPIO4_ENABLE         BIT15
-
-#define CM_FCLKEN_PER_EN_GPIO5_DISABLE        (0UL << 16)
-#define CM_FCLKEN_PER_EN_GPIO5_ENABLE         BIT16
-
-#define CM_FCLKEN_PER_EN_GPIO6_DISABLE        (0UL << 17)
-#define CM_FCLKEN_PER_EN_GPIO6_ENABLE         BIT17
-
-//Peripheral interface clock
-#define CM_ICLKEN_PER_EN_GPT3_DISABLE         (0UL << 4)
-#define CM_ICLKEN_PER_EN_GPT3_ENABLE          BIT4
-
-#define CM_ICLKEN_PER_EN_GPT4_DISABLE         (0UL << 5)
-#define CM_ICLKEN_PER_EN_GPT4_ENABLE          BIT5
-
-#define CM_ICLKEN_PER_EN_UART3_DISABLE        (0UL << 11)
-#define CM_ICLKEN_PER_EN_UART3_ENABLE         BIT11
-
-#define CM_ICLKEN_PER_EN_GPIO2_DISABLE        (0UL << 13)
-#define CM_ICLKEN_PER_EN_GPIO2_ENABLE         BIT13
-
-#define CM_ICLKEN_PER_EN_GPIO3_DISABLE        (0UL << 14)
-#define CM_ICLKEN_PER_EN_GPIO3_ENABLE         BIT14
-
-#define CM_ICLKEN_PER_EN_GPIO4_DISABLE        (0UL << 15)
-#define CM_ICLKEN_PER_EN_GPIO4_ENABLE         BIT15
-
-#define CM_ICLKEN_PER_EN_GPIO5_DISABLE        (0UL << 16)
-#define CM_ICLKEN_PER_EN_GPIO5_ENABLE         BIT16
-
-#define CM_ICLKEN_PER_EN_GPIO6_DISABLE        (0UL << 17)
-#define CM_ICLKEN_PER_EN_GPIO6_ENABLE         BIT17
-
-//Timer source clock selection
-#define CM_CLKSEL_PER_CLKSEL_GPT3_32K         (0UL << 1)
-#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS         BIT1
-
-#define CM_CLKSEL_PER_CLKSEL_GPT4_32K         (0UL << 2)
-#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS         BIT2
-
-//Reset management (Global and Cold reset)
-#define RST_GS            BIT1
-#define RST_DPLL3         BIT2
-#define GLOBAL_SW_RST     BIT1
-#define GLOBAL_COLD_RST   (0x0UL << 0)
-
-#endif // __OMAP3530PRCM_H__
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Timer.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Timer.h
deleted file mode 100644
index d66da8d..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Timer.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530TIMER_H__
-#define __OMAP3530TIMER_H__
-
-#define GPTIMER1_BASE   (0x48313000)
-#define GPTIMER2_BASE   (0x49032000)
-#define GPTIMER3_BASE   (0x49034000)
-#define GPTIMER4_BASE   (0x49036000)
-#define GPTIMER5_BASE   (0x49038000)
-#define GPTIMER6_BASE   (0x4903A000)
-#define GPTIMER7_BASE   (0x4903C000)
-#define GPTIMER8_BASE   (0x4903E000)
-#define GPTIMER9_BASE   (0x49040000)
-#define GPTIMER10_BASE  (0x48086000)
-#define GPTIMER11_BASE  (0x48088000)
-#define GPTIMER12_BASE  (0x48304000)
-#define WDTIMER2_BASE   (0x48314000)
-
-#define GPTIMER_TIOCP_CFG (0x0010)
-#define GPTIMER_TISTAT    (0x0014)
-#define GPTIMER_TISR      (0x0018)
-#define GPTIMER_TIER      (0x001C)
-#define GPTIMER_TWER      (0x0020)
-#define GPTIMER_TCLR      (0x0024)
-#define GPTIMER_TCRR      (0x0028)
-#define GPTIMER_TLDR      (0x002C)
-#define GPTIMER_TTGR      (0x0030)
-#define GPTIMER_TWPS      (0x0034)
-#define GPTIMER_TMAR      (0x0038)
-#define GPTIMER_TCAR1     (0x003C)
-#define GPTIMER_TSICR     (0x0040)
-#define GPTIMER_TCAR2     (0x0044)
-#define GPTIMER_TPIR      (0x0048)
-#define GPTIMER_TNIR      (0x004C)
-#define GPTIMER_TCVR      (0x0050)
-#define GPTIMER_TOCR      (0x0054)
-#define GPTIMER_TOWR      (0x0058)
-
-#define WSPR              (0x048)
-
-#define TISR_TCAR_IT_FLAG_MASK  BIT2
-#define TISR_OVF_IT_FLAG_MASK   BIT1
-#define TISR_MAT_IT_FLAG_MASK   BIT0
-#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
-
-#define TISR_TCAR_IT_FLAG_NOT_PENDING   (0UL << 2)
-#define TISR_OVF_IT_FLAG_NOT_PENDING    (0UL << 1)
-#define TISR_MAT_IT_FLAG_NOT_PENDING    (0UL << 0)
-#define TISR_NO_INTERRUPTS_PENDING      (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
-
-#define TISR_TCAR_IT_FLAG_CLEAR BIT2
-#define TISR_OVF_IT_FLAG_CLEAR  BIT1
-#define TISR_MAT_IT_FLAG_CLEAR  BIT0
-#define TISR_CLEAR_ALL          (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
-
-#define TCLR_AR_AUTORELOAD      BIT1
-#define TCLR_AR_ONESHOT         (0UL << 1)
-#define TCLR_ST_ON              BIT0
-#define TCLR_ST_OFF             (0UL << 0)
-
-#define TIER_TCAR_IT_ENABLE     (BIT2
-#define TIER_TCAR_IT_DISABLE    (0UL << 2)
-#define TIER_OVF_IT_ENABLE      BIT1
-#define TIER_OVF_IT_DISABLE     (0UL << 1)
-#define TIER_MAT_IT_ENABLE      BIT0
-#define TIER_MAT_IT_DISABLE     (0UL << 0)
-
-#endif // __OMAP3530TIMER_H__
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Uart.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Uart.h
deleted file mode 100644
index 62cbe30..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Uart.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530UART_H__
-#define __OMAP3530UART_H__
-
-#define UART1_BASE  (0x4806A000)
-#define UART2_BASE  (0x4806C000)
-#define UART3_BASE  (0x49020000)
-
-#define UART_DLL_REG  (0x0000)
-#define UART_RBR_REG  (0x0000)
-#define UART_THR_REG  (0x0000)
-#define UART_DLH_REG  (0x0004)
-#define UART_FCR_REG  (0x0008)
-#define UART_LCR_REG  (0x000C)
-#define UART_MCR_REG  (0x0010)
-#define UART_LSR_REG  (0x0014)
-#define UART_MDR1_REG (0x0020)
-
-#define UART_FCR_TX_FIFO_CLEAR          BIT2
-#define UART_FCR_RX_FIFO_CLEAR          BIT1
-#define UART_FCR_FIFO_ENABLE            BIT0
-
-#define UART_LCR_DIV_EN_ENABLE          BIT7
-#define UART_LCR_DIV_EN_DISABLE         (0UL << 7)
-#define UART_LCR_CHAR_LENGTH_8          (BIT1 | BIT0)
-
-#define UART_MCR_RTS_FORCE_ACTIVE       BIT1
-#define UART_MCR_DTR_FORCE_ACTIVE       BIT0
-
-#define UART_LSR_TX_FIFO_E_MASK         BIT5
-#define UART_LSR_TX_FIFO_E_NOT_EMPTY    (0UL << 5)
-#define UART_LSR_TX_FIFO_E_EMPTY        BIT5
-#define UART_LSR_RX_FIFO_E_MASK         BIT0
-#define UART_LSR_RX_FIFO_E_NOT_EMPTY    BIT0
-#define UART_LSR_RX_FIFO_E_EMPTY        (0UL << 0)
-
-// BIT2:BIT0
-#define UART_MDR1_MODE_SELECT_DISABLE   (7UL)
-#define UART_MDR1_MODE_SELECT_UART_16X  (0UL)
-
-#endif // __OMAP3530UART_H__
diff --git a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Usb.h b/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Usb.h
deleted file mode 100644
index 5d64caf..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/Omap3530/Omap3530Usb.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3530USB_H__
-#define __OMAP3530USB_H__
-
-#define USB_BASE            (0x48060000)
-
-#define UHH_SYSCONFIG       (USB_BASE + 0x4010)
-#define UHH_HOSTCONFIG      (USB_BASE + 0x4040)
-#define UHH_SYSSTATUS       (USB_BASE + 0x4014)
-
-#define USB_EHCI_HCCAPBASE  (USB_BASE + 0x4800)
-
-#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY  BIT12
-#define UHH_SYSCONFIG_CLOCKACTIVITY_ON      BIT8
-#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY  BIT3
-#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE      BIT2
-#define UHH_SYSCONFIG_SOFTRESET             BIT1
-#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN   (0UL <<  0)
-
-#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
-#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL <<  9)
-#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL <<  8)
-#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE       (0UL <<  5)
-#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE            BIT4
-#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE             BIT3
-#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE             BIT2
-#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON     (0UL <<  1)
-#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE     (0UL <<  0)
-
-#define UHH_SYSSTATUS_RESETDONE                (BIT0 | BIT1 | BIT2)
-
-#endif // __OMAP3530USB_H__
-
-
-
diff --git a/Chips/TexasInstruments/Omap35xx/Include/TPS65950.h b/Chips/TexasInstruments/Omap35xx/Include/TPS65950.h
deleted file mode 100644
index 1db8b6d..0000000
--- a/Chips/TexasInstruments/Omap35xx/Include/TPS65950.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __TPS65950_H__
-#define __TPS65950_H__
-
-#define EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(x)     (((x) >> 8) & 0xFF)
-#define EXTERNAL_DEVICE_REGISTER_TO_REGISTER(x)          ((x) & 0xFF)
-#define EXTERNAL_DEVICE_REGISTER(SlaveAddress, Register) (((SlaveAddress) & 0xFF) << 8 | ((Register) & 0xFF))
-
-// I2C Address group
-#define I2C_ADDR_GRP_ID1      0x48
-#define I2C_ADDR_GRP_ID2      0x49
-#define I2C_ADDR_GRP_ID3      0x4A
-#define I2C_ADDR_GRP_ID4      0x4B
-#define I2C_ADDR_GRP_ID5      0x12
-
-// MMC definitions.
-#define VMMC1_DEV_GRP         0x82
-#define DEV_GRP_P1            BIT5
-
-#define VMMC1_DEDICATED_REG   0x85
-#define VSEL_1_85V            0x0
-#define VSEL_2_85V            0x1
-#define VSEL_3_00V            0x2
-#define VSEL_3_15V            0x3
-
-#define TPS65950_GPIO_CTRL    0xaa  //I2C_ADDR_GRP_ID2
-#define CARD_DETECT_ENABLE    (BIT2 | BIT0) // GPIO ON + GPIO CD1 enabled
-
-
-#define GPIODATAIN1           0x98  //I2C_ADDR_GRP_ID2
-#define CARD_DETECT_BIT       BIT0
-
-// LEDEN register
-#define LEDEN                 0xEE
-#define LEDAON                BIT0
-#define LEDBON                BIT1
-#define LEDAPWM               BIT4
-#define LEDBPWM               BIT5
-
-// RTC registers
-#define SECONDS_REG           0x1C
-#define MINUTES_REG           0x1D
-#define HOURS_REG             0x1E
-#define DAYS_REG              0x1F
-#define MONTHS_REG            0x20
-#define YEARS_REG             0x21
-#define WEEKS_REG             0x22
-#define RTC_CTRL_REG          0x29
-
-// USB PHY power
-#define VAUX2_DEDICATED       0x79
-#define VAUX2_DEV_GRP         0x76
-
-#define VAUX_DEV_GRP_NONE     0x00
-#define VAUX_DEV_GRP_P1       0x20
-#define VAUX_DEV_GRP_P2       0x40
-#define VAUX_DEV_GRP_P3       0x80
-#define VAUX_DEDICATED_18V    0x05
-
-// Display subsystem
-#define VPLL2_DEDICATED       0x91
-#define VPLL2_DEV_GRP         0x8E
-
-#define GPIODATADIR1          0x9B
-#define SETGPIODATAOUT1       0xA4
-
-#endif //__TPS65950_H__
diff --git a/Chips/TexasInstruments/Omap35xx/InterruptDxe/HardwareInterrupt.c b/Chips/TexasInstruments/Omap35xx/InterruptDxe/HardwareInterrupt.c
deleted file mode 100644
index 09e22b5..0000000
--- a/Chips/TexasInstruments/Omap35xx/InterruptDxe/HardwareInterrupt.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/** @file
-  Handle OMAP35xx interrupt controller
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-#include <PiDxe.h>
-
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/ArmLib.h>
-
-#include <Protocol/Cpu.h>
-#include <Protocol/HardwareInterrupt.h>
-
-#include <Omap3530/Omap3530.h>
-
-//
-// Notifications
-//
-EFI_EVENT EfiExitBootServicesEvent      = (EFI_EVENT)NULL;
-
-
-HARDWARE_INTERRUPT_HANDLER  gRegisteredInterruptHandlers[INT_NROF_VECTORS];
-
-/**
-  Shutdown our hardware
-
-  DXE Core will disable interrupts and turn off the timer and disable interrupts
-  after all the event handlers have run.
-
-  @param[in]  Event   The Event that is being processed
-  @param[in]  Context Event Context
-**/
-VOID
-EFIAPI
-ExitBootServicesEvent (
-  IN EFI_EVENT  Event,
-  IN VOID       *Context
-  )
-{
-  // Disable all interrupts
-  MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
-  MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
-  MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
-  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
-
-  // Add code here to disable all FIQs as debugger may have turned one on
-}
-
-/**
-  Register Handler for the specified interrupt source.
-
-  @param This     Instance pointer for this protocol
-  @param Source   Hardware source of the interrupt
-  @param Handler  Callback for interrupt. NULL to unregister
-
-  @retval EFI_SUCCESS Source was updated to support Handler.
-  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-RegisterInterruptSource (
-  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
-  IN HARDWARE_INTERRUPT_SOURCE          Source,
-  IN HARDWARE_INTERRUPT_HANDLER         Handler
-  )
-{
-  if (Source > MAX_VECTOR) {
-    ASSERT(FALSE);
-    return EFI_UNSUPPORTED;
-  }
-
-  if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {
-    // This vector has been programmed as FIQ so we can't use it for IRQ
-    // EFI does not use FIQ, but the debugger can use it to check for
-    // ctrl-c. So this ASSERT means you have a conflict with the debug agent
-    ASSERT (FALSE);
-    return EFI_UNSUPPORTED;
-  }
-
-  if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
-    return EFI_ALREADY_STARTED;
-  }
-
-  gRegisteredInterruptHandlers[Source] = Handler;
-  return This->EnableInterruptSource(This, Source);
-}
-
-
-/**
-  Enable interrupt source Source.
-
-  @param This     Instance pointer for this protocol
-  @param Source   Hardware source of the interrupt
-
-  @retval EFI_SUCCESS       Source interrupt enabled.
-  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-EnableInterruptSource (
-  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
-  IN HARDWARE_INTERRUPT_SOURCE          Source
-  )
-{
-  UINTN Bank;
-  UINTN Bit;
-
-  if (Source > MAX_VECTOR) {
-    ASSERT(FALSE);
-    return EFI_UNSUPPORTED;
-  }
-
-  Bank = Source / 32;
-  Bit  = 1UL << (Source % 32);
-
-  MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
-
-  return EFI_SUCCESS;
-}
-
-
-/**
-  Disable interrupt source Source.
-
-  @param This     Instance pointer for this protocol
-  @param Source   Hardware source of the interrupt
-
-  @retval EFI_SUCCESS       Source interrupt disabled.
-  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-DisableInterruptSource (
-  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
-  IN HARDWARE_INTERRUPT_SOURCE          Source
-  )
-{
-  UINTN Bank;
-  UINTN Bit;
-
-  if (Source > MAX_VECTOR) {
-    ASSERT(FALSE);
-    return EFI_UNSUPPORTED;
-  }
-
-  Bank = Source / 32;
-  Bit  = 1UL << (Source % 32);
-
-  MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
-
-  return EFI_SUCCESS;
-}
-
-
-
-/**
-  Return current state of interrupt source Source.
-
-  @param This     Instance pointer for this protocol
-  @param Source   Hardware source of the interrupt
-  @param InterruptState  TRUE: source enabled, FALSE: source disabled.
-
-  @retval EFI_SUCCESS       InterruptState is valid
-  @retval EFI_DEVICE_ERROR  InterruptState is not valid
-
-**/
-EFI_STATUS
-EFIAPI
-GetInterruptSourceState (
-  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
-  IN HARDWARE_INTERRUPT_SOURCE          Source,
-  IN BOOLEAN                            *InterruptState
-  )
-{
-  UINTN Bank;
-  UINTN Bit;
-
-  if (InterruptState == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  if (Source > MAX_VECTOR) {
-    ASSERT(FALSE);
-    return EFI_UNSUPPORTED;
-  }
-
-  Bank = Source / 32;
-  Bit  = 1UL << (Source % 32);
-
-  if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {
-    *InterruptState = FALSE;
-  } else {
-    *InterruptState = TRUE;
-  }
-
-  return EFI_SUCCESS;
-}
-
-/**
-  Signal to the hardware that the End Of Intrrupt state
-  has been reached.
-
-  @param This     Instance pointer for this protocol
-  @param Source   Hardware source of the interrupt
-
-  @retval EFI_SUCCESS       Source interrupt EOI'ed.
-  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-EndOfInterrupt (
-  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,
-  IN HARDWARE_INTERRUPT_SOURCE          Source
-  )
-{
-  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
-  ArmDataSynchronizationBarrier ();
-  return EFI_SUCCESS;
-}
-
-
-/**
-  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
-
-  @param  InterruptType    Defines the type of interrupt or exception that
-                           occurred on the processor.This parameter is processor architecture specific.
-  @param  SystemContext    A pointer to the processor context when
-                           the interrupt occurred on the processor.
-
-  @return None
-
-**/
-VOID
-EFIAPI
-IrqInterruptHandler (
-  IN EFI_EXCEPTION_TYPE           InterruptType,
-  IN EFI_SYSTEM_CONTEXT           SystemContext
-  )
-{
-  UINT32                     Vector;
-  HARDWARE_INTERRUPT_HANDLER InterruptHandler;
-
-  Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
-
-  // Needed to prevent infinite nesting when Time Driver lowers TPL
-  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
-  ArmDataSynchronizationBarrier ();
-
-  InterruptHandler = gRegisteredInterruptHandlers[Vector];
-  if (InterruptHandler != NULL) {
-    // Call the registered interrupt handler.
-    InterruptHandler (Vector, SystemContext);
-  }
-
-  // Needed to clear after running the handler
-  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
-  ArmDataSynchronizationBarrier ();
-}
-
-//
-// Making this global saves a few bytes in image size
-//
-EFI_HANDLE  gHardwareInterruptHandle = NULL;
-
-//
-// The protocol instance produced by this driver
-//
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
-  RegisterInterruptSource,
-  EnableInterruptSource,
-  DisableInterruptSource,
-  GetInterruptSourceState,
-  EndOfInterrupt
-};
-
-/**
-  Initialize the state information for the CPU Architectural Protocol
-
-  @param  ImageHandle   of the loaded driver
-  @param  SystemTable   Pointer to the System Table
-
-  @retval EFI_SUCCESS           Protocol registered
-  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
-  @retval EFI_DEVICE_ERROR      Hardware problems
-
-**/
-EFI_STATUS
-InterruptDxeInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS  Status;
-  EFI_CPU_ARCH_PROTOCOL   *Cpu;
-
-  // Make sure the Interrupt Controller Protocol is not already installed in the system.
-  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
-
-  // Make sure all interrupts are disabled by default.
-  MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
-  MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
-  MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
-  MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
-
-  Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
-                                                  &gHardwareInterruptProtocolGuid,   &gHardwareInterruptProtocol,
-                                                  NULL);
-  ASSERT_EFI_ERROR(Status);
-
-  //
-  // Get the CPU protocol that this driver requires.
-  //
-  Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
-  ASSERT_EFI_ERROR(Status);
-
-  //
-  // Unregister the default exception handler.
-  //
-  Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
-  ASSERT_EFI_ERROR(Status);
-
-  //
-  // Register to receive interrupts
-  //
-  Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
-  ASSERT_EFI_ERROR(Status);
-
-  // Register for an ExitBootServicesEvent
-  Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
-  ASSERT_EFI_ERROR(Status);
-
-  return Status;
-}
-
diff --git a/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c b/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c
deleted file mode 100644
index 418328a..0000000
--- a/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/** @file
-
- Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution.  The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- **/
-
-#include <PiDxe.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/MemoryAllocationLib.h>
-
-#include <Guid/GlobalVariable.h>
-
-#include "LcdGraphicsOutputDxe.h"
-
-extern BOOLEAN mDisplayInitialized;
-
-//
-// Function Definitions
-//
-
-STATIC
-EFI_STATUS
-VideoCopyNoHorizontalOverlap (
-  IN UINTN          BitsPerPixel,
-  IN volatile VOID  *FrameBufferBase,
-  IN UINT32         HorizontalResolution,
-  IN UINTN          SourceX,
-  IN UINTN          SourceY,
-  IN UINTN          DestinationX,
-  IN UINTN          DestinationY,
-  IN UINTN          Width,
-  IN UINTN          Height
-  )
-{
-  EFI_STATUS    Status = EFI_SUCCESS;
-  UINTN         SourceLine;
-  UINTN         DestinationLine;
-  UINTN         WidthInBytes;
-  UINTN         LineCount;
-  INTN          Step;
-  VOID          *SourceAddr;
-  VOID          *DestinationAddr;
-
-  if( DestinationY <= SourceY ) {
-    // scrolling up (or horizontally but without overlap)
-    SourceLine       = SourceY;
-    DestinationLine  = DestinationY;
-    Step             = 1;
-  } else {
-    // scrolling down
-    SourceLine       = SourceY + Height;
-    DestinationLine  = DestinationY + Height;
-    Step             = -1;
-  }
-
-  WidthInBytes = Width * 2;
-
-  for( LineCount = 0; LineCount < Height; LineCount++ ) {
-    // Update the start addresses of source & destination using 16bit pointer arithmetic
-    SourceAddr      = (VOID *)((UINT16 *)FrameBufferBase + SourceLine      * HorizontalResolution + SourceX     );
-    DestinationAddr = (VOID *)((UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationX);
-
-    // Copy the entire line Y from video ram to the temp buffer
-    CopyMem( DestinationAddr, SourceAddr, WidthInBytes);
-
-    // Update the line numbers
-    SourceLine      += Step;
-    DestinationLine += Step;
-  }
-
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-VideoCopyHorizontalOverlap (
-  IN UINTN          BitsPerPixel,
-  IN volatile VOID  *FrameBufferBase,
-  UINT32            HorizontalResolution,
-  IN UINTN          SourceX,
-  IN UINTN          SourceY,
-  IN UINTN          DestinationX,
-  IN UINTN          DestinationY,
-  IN UINTN          Width,
-  IN UINTN          Height
-  )
-{
-  EFI_STATUS      Status = EFI_SUCCESS;
-
-  UINT16 *PixelBuffer16bit;
-  UINT16 *SourcePixel16bit;
-  UINT16 *DestinationPixel16bit;
-
-  UINT32          SourcePixelY;
-  UINT32          DestinationPixelY;
-  UINTN           SizeIn16Bits;
-
-  // Allocate a temporary buffer
-  PixelBuffer16bit = (UINT16 *) AllocatePool((Height * Width) * sizeof(UINT16));
-
-  if (PixelBuffer16bit == NULL) {
-    Status = EFI_OUT_OF_RESOURCES;
-    goto EXIT;
-  }
-
-  // Access each pixel inside the source area of the Video Memory and copy it to the temp buffer
-
-  SizeIn16Bits = Width * 2;
-
-  for (SourcePixelY = SourceY, DestinationPixel16bit = PixelBuffer16bit;
-       SourcePixelY < SourceY + Height;
-       SourcePixelY++, DestinationPixel16bit += Width)
-  {
-    // Calculate the source address:
-    SourcePixel16bit = (UINT16 *)FrameBufferBase + SourcePixelY * HorizontalResolution + SourceX;
-
-    // Copy the entire line Y from Video to the temp buffer
-    CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits);
-  }
-
-  // Copy from the temp buffer into the destination area of the Video Memory
-
-  for (DestinationPixelY = DestinationY, SourcePixel16bit = PixelBuffer16bit;
-       DestinationPixelY < DestinationY + Height;
-       DestinationPixelY++, SourcePixel16bit += Width)
-  {
-    // Calculate the target address:
-    DestinationPixel16bit = (UINT16 *)FrameBufferBase + (DestinationPixelY * HorizontalResolution + DestinationX);
-
-    // Copy the entire line Y from the temp buffer to Video
-    CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits);
-  }
-
-  // Free the allocated memory
-  FreePool((VOID *) PixelBuffer16bit);
-
-
-EXIT:
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-BltVideoFill (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL        *This,
-  IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL   *EfiSourcePixel,     OPTIONAL
-  IN UINTN                               SourceX,
-  IN UINTN                               SourceY,
-  IN UINTN                               DestinationX,
-  IN UINTN                               DestinationY,
-  IN UINTN                               Width,
-  IN UINTN                               Height,
-  IN UINTN                               Delta           OPTIONAL   // Number of BYTES in a row of the BltBuffer
-  )
-{
-  EFI_PIXEL_BITMASK*  PixelInformation;
-  EFI_STATUS          Status;
-  UINT32              HorizontalResolution;
-  VOID                *FrameBufferBase;
-  UINT16              *DestinationPixel16bit;
-  UINT16              Pixel16bit;
-  UINT32              DestinationPixelX;
-  UINT32              DestinationLine;
-
-  Status           = EFI_SUCCESS;
-  PixelInformation = &This->Mode->Info->PixelInformation;
-  FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
-  HorizontalResolution = This->Mode->Info->HorizontalResolution;
-
-  // Convert the EFI pixel at the start of the BltBuffer(0,0) into a video display pixel
-  Pixel16bit = (UINT16) (
-      ( (EfiSourcePixel->Red      <<  8) & PixelInformation->RedMask      )
-    | ( (EfiSourcePixel->Green    <<  3) & PixelInformation->GreenMask    )
-    | ( (EfiSourcePixel->Blue     >>  3) & PixelInformation->BlueMask     )
-   );
-
-  // Copy the SourcePixel into every pixel inside the target rectangle
-  for (DestinationLine = DestinationY;
-       DestinationLine < DestinationY + Height;
-       DestinationLine++)
-  {
-    for (DestinationPixelX = DestinationX;
-         DestinationPixelX < DestinationX + Width;
-         DestinationPixelX++)
-    {
-      // Calculate the target address:
-      DestinationPixel16bit =  (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution  + DestinationPixelX;
-
-      // Copy the pixel into the new target
-      *DestinationPixel16bit = Pixel16bit;
-    }
-  }
-
-
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-BltVideoToBltBuffer (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL        *This,
-  IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL   *BltBuffer,     OPTIONAL
-  IN UINTN                               SourceX,
-  IN UINTN                               SourceY,
-  IN UINTN                               DestinationX,
-  IN UINTN                               DestinationY,
-  IN UINTN                               Width,
-  IN UINTN                               Height,
-  IN UINTN                               Delta           OPTIONAL   // Number of BYTES in a row of the BltBuffer
-  )
-{
-  EFI_STATUS         Status;
-  UINT32             HorizontalResolution;
-  EFI_PIXEL_BITMASK  *PixelInformation;
-  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiDestinationPixel;
-  VOID               *FrameBufferBase;
-  UINT16             *SourcePixel16bit;
-  UINT16             Pixel16bit;
-  UINT32             SourcePixelX;
-  UINT32             SourceLine;
-  UINT32             DestinationPixelX;
-  UINT32             DestinationLine;
-  UINT32             BltBufferHorizontalResolution;
-
-  Status = EFI_SUCCESS;
-  PixelInformation = &This->Mode->Info->PixelInformation;
-  HorizontalResolution = This->Mode->Info->HorizontalResolution;
-  FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
-
-  if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
-    // Delta is not zero and it is different from the width.
-    // Divide it by the size of a pixel to find out the buffer's horizontal resolution.
-    BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
-  } else {
-    BltBufferHorizontalResolution = Width;
-  }
-
-  // Access each pixel inside the Video Memory
-  for (SourceLine = SourceY, DestinationLine = DestinationY;
-       SourceLine < SourceY + Height;
-       SourceLine++, DestinationLine++)
-  {
-    for (SourcePixelX = SourceX, DestinationPixelX = DestinationX;
-         SourcePixelX < SourceX + Width;
-         SourcePixelX++, DestinationPixelX++)
-    {
-      // Calculate the source and target addresses:
-      SourcePixel16bit = (UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourcePixelX;
-      EfiDestinationPixel = BltBuffer + DestinationLine * BltBufferHorizontalResolution + DestinationPixelX;
-
-      // Snapshot the pixel from the video buffer once, to speed up the operation.
-      // If we were dereferencing the pointer, as it is volatile, we would perform 3 memory read operations.
-      Pixel16bit = *SourcePixel16bit;
-
-      // Copy the pixel into the new target
-      EfiDestinationPixel->Red      = (UINT8) ( (Pixel16bit & PixelInformation->RedMask     ) >>  8 );
-      EfiDestinationPixel->Green    = (UINT8) ( (Pixel16bit & PixelInformation->GreenMask   ) >>  3 );
-      EfiDestinationPixel->Blue     = (UINT8) ( (Pixel16bit & PixelInformation->BlueMask    ) <<  3 );
-    }
-  }
-
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-BltBufferToVideo (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL        *This,
-  IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL   *BltBuffer,     OPTIONAL
-  IN UINTN                               SourceX,
-  IN UINTN                               SourceY,
-  IN UINTN                               DestinationX,
-  IN UINTN                               DestinationY,
-  IN UINTN                               Width,
-  IN UINTN                               Height,
-  IN UINTN                               Delta           OPTIONAL   // Number of BYTES in a row of the BltBuffer
-  )
-{
-  EFI_STATUS         Status;
-  UINT32             HorizontalResolution;
-  EFI_PIXEL_BITMASK  *PixelInformation;
-  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel;
-  VOID               *FrameBufferBase;
-  UINT16             *DestinationPixel16bit;
-  UINT32             SourcePixelX;
-  UINT32             SourceLine;
-  UINT32             DestinationPixelX;
-  UINT32             DestinationLine;
-  UINT32             BltBufferHorizontalResolution;
-
-  Status = EFI_SUCCESS;
-  PixelInformation = &This->Mode->Info->PixelInformation;
-  HorizontalResolution = This->Mode->Info->HorizontalResolution;
-  FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
-
-  if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
-    // Delta is not zero and it is different from the width.
-    // Divide it by the size of a pixel to find out the buffer's horizontal resolution.
-    BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
-  } else {
-    BltBufferHorizontalResolution = Width;
-  }
-
-  // Access each pixel inside the BltBuffer Memory
-  for (SourceLine = SourceY, DestinationLine = DestinationY;
-       SourceLine < SourceY + Height;
-       SourceLine++, DestinationLine++) {
-
-    for (SourcePixelX = SourceX, DestinationPixelX = DestinationX;
-         SourcePixelX < SourceX + Width;
-         SourcePixelX++, DestinationPixelX++)
-    {
-      // Calculate the source and target addresses:
-      EfiSourcePixel  = BltBuffer + SourceLine * BltBufferHorizontalResolution + SourcePixelX;
-      DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX;
-
-      // Copy the pixel into the new target
-      // Only the most significant bits will be copied across:
-      // To convert from 8 bits to 5 bits per pixel we throw away the 3 least significant bits
-        *DestinationPixel16bit = (UINT16) (
-              ( (EfiSourcePixel->Red      <<  8) & PixelInformation->RedMask      )
-            | ( (EfiSourcePixel->Green    <<  3) & PixelInformation->GreenMask    )
-            | ( (EfiSourcePixel->Blue     >>  3) & PixelInformation->BlueMask     )
-            );
-      }
-    }
-
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-BltVideoToVideo (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL        *This,
-  IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL   *BltBuffer,     OPTIONAL
-  IN UINTN                               SourceX,
-  IN UINTN                               SourceY,
-  IN UINTN                               DestinationX,
-  IN UINTN                               DestinationY,
-  IN UINTN                               Width,
-  IN UINTN                               Height,
-  IN UINTN                               Delta           OPTIONAL   // Number of BYTES in a row of the BltBuffer
-  )
-{
-  EFI_STATUS         Status;
-  UINT32             HorizontalResolution;
-  UINTN              BitsPerPixel;
-  VOID               *FrameBufferBase;
-
-  BitsPerPixel = 16;
-
-  HorizontalResolution = This->Mode->Info->HorizontalResolution;
-  FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
-
-  //
-  // BltVideo to BltVideo:
-  //
-  //  Source is the Video Memory,
-  //  Destination is the Video Memory
-
-  FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
-
-  // The UEFI spec currently states:
-  // "There is no limitation on the overlapping of the source and destination rectangles"
-  // Therefore, we must be careful to avoid overwriting the source data
-  if( SourceY == DestinationY ) {
-    // Copying within the same height, e.g. horizontal shift
-    if( SourceX == DestinationX ) {
-      // Nothing to do
-      Status = EFI_SUCCESS;
-    } else if( ((SourceX>DestinationX)?(SourceX - DestinationX):(DestinationX - SourceX)) < Width ) {
-      // There is overlap
-      Status = VideoCopyHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height );
-    } else {
-      // No overlap
-      Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height );
-    }
-  } else {
-    // Copying from different heights
-    Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height );
-  }
-
-  return Status;
-}
-
-EFI_STATUS
-EFIAPI
-LcdGraphicsBlt (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL        *This,
-  IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL   *BltBuffer,     OPTIONAL
-  IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION   BltOperation,
-  IN UINTN                               SourceX,
-  IN UINTN                               SourceY,
-  IN UINTN                               DestinationX,
-  IN UINTN                               DestinationY,
-  IN UINTN                               Width,
-  IN UINTN                               Height,
-  IN UINTN                               Delta           OPTIONAL   // Number of BYTES in a row of the BltBuffer
-  )
-{
-  EFI_STATUS    Status;
-  LCD_INSTANCE  *Instance;
-
-  Instance = LCD_INSTANCE_FROM_GOP_THIS(This);
-
-  if (!mDisplayInitialized) {
-    InitializeDisplay (Instance);
-  }
-
-  switch (BltOperation) {
-  case EfiBltVideoFill:
-    Status = BltVideoFill (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta);
-    break;
-
-  case EfiBltVideoToBltBuffer:
-    Status = BltVideoToBltBuffer (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta);
-    break;
-
-  case EfiBltBufferToVideo:
-    Status = BltBufferToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta);
-    break;
-
-  case EfiBltVideoToVideo:
-    Status = BltVideoToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta);
-    break;
-
-  case EfiGraphicsOutputBltOperationMax:
-  default:
-    DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: Invalid Operation\n"));
-    Status = EFI_INVALID_PARAMETER;
-    break;
-}
-
-  return Status;
-}
diff --git a/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c b/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c
deleted file mode 100644
index 4364dd7..0000000
--- a/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/** @file
-
- Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution.  The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "LcdGraphicsOutputDxe.h"
-
-BOOLEAN mDisplayInitialized = FALSE;
-
-LCD_MODE LcdModes[] = {
-  {
-    0, 640, 480,
-    9, 4,
-    96, 16, 48,
-    2, 10, 33
-  },
-  {
-    1, 800, 600,
-    11, 2,
-    120, 56, 64,
-    5, 37, 22
-  },
-  {
-    2, 1024, 768,
-    6, 2,
-    96, 16, 48,
-    2, 10, 33
-  },
-};
-
-LCD_INSTANCE mLcdTemplate = {
-  LCD_INSTANCE_SIGNATURE,
-  NULL, // Handle
-  { // ModeInfo
-    0, // Version
-    0, // HorizontalResolution
-    0, // VerticalResolution
-    PixelBltOnly, // PixelFormat
-    {
-      0xF800, //RedMask;
-      0x7E0, //GreenMask;
-      0x1F, //BlueMask;
-      0x0//ReservedMask
-    }, // PixelInformation
-    0, // PixelsPerScanLine
-  },
-  { // Mode
-    3, // MaxMode;
-    0, // Mode;
-    NULL, // Info;
-    0, // SizeOfInfo;
-    0, // FrameBufferBase;
-    0 // FrameBufferSize;
-  },
-  { // Gop
-    LcdGraphicsQueryMode,  // QueryMode
-    LcdGraphicsSetMode,    // SetMode
-    LcdGraphicsBlt,        // Blt
-    NULL                     // *Mode
-  },
-  { // DevicePath
-    {
-      {
-        HARDWARE_DEVICE_PATH, HW_VENDOR_DP,
-        { (UINT8) (sizeof(VENDOR_DEVICE_PATH)), (UINT8) ((sizeof(VENDOR_DEVICE_PATH)) >> 8) },
-      },
-      // Hardware Device Path for Lcd
-      EFI_CALLER_ID_GUID // Use the driver's GUID
-    },
-    {
-      END_DEVICE_PATH_TYPE,
-      END_ENTIRE_DEVICE_PATH_SUBTYPE,
-      { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0}
-    }
-  }
-};
-
-EFI_STATUS
-LcdInstanceContructor (
-  OUT LCD_INSTANCE** NewInstance
-  )
-{
-  LCD_INSTANCE* Instance;
-
-  Instance = AllocateCopyPool (sizeof(LCD_INSTANCE), &mLcdTemplate);
-  if (Instance == NULL) {
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  Instance->Gop.Mode          = &Instance->Mode;
-  Instance->Mode.Info         = &Instance->ModeInfo;
-
-  *NewInstance = Instance;
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-LcdPlatformGetVram (
-  OUT EFI_PHYSICAL_ADDRESS*  VramBaseAddress,
-  OUT UINTN*                 VramSize
-  )
-{
-  EFI_STATUS             Status;
-  EFI_CPU_ARCH_PROTOCOL  *Cpu;
-  UINTN                  MaxSize;
-
-  MaxSize = 0x500000;
-  *VramSize = MaxSize;
-
-  // Allocate VRAM from DRAM
-  Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES((MaxSize)), VramBaseAddress);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  // Ensure the Cpu architectural protocol is already installed
-  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
-  ASSERT_EFI_ERROR(Status);
-
-  // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable.
-  Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);
-  if (EFI_ERROR(Status)) {
-    gBS->FreePool (VramBaseAddress);
-    return Status;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DssSetMode (
-  UINT32 VramBaseAddress,
-  UINTN  ModeNumber
-  )
-{
-  // Make sure the interface clock is running
-  MmioWrite32 (CM_ICLKEN_DSS, EN_DSS);
-
-  // Stop the functional clocks
-  MmioAnd32 (CM_FCLKEN_DSS, ~(EN_DSS1 | EN_DSS2 | EN_TV));
-
-  // Program the DSS clock divisor
-  MmioWrite32 (CM_CLKSEL_DSS, 0x1000 | (LcdModes[ModeNumber].DssDivisor));
-
-  // Start the functional clocks
-  MmioOr32 (CM_FCLKEN_DSS, (EN_DSS1 | EN_DSS2 | EN_TV));
-
-  // Wait for DSS to stabilize
-  gBS->Stall(1);
-
-  // Reset the subsystem
-  MmioWrite32(DSS_SYSCONFIG, DSS_SOFTRESET);
-  while (!(MmioRead32 (DSS_SYSSTATUS) & DSS_RESETDONE));
-
-  // Configure LCD parameters
-  MmioWrite32 (DISPC_SIZE_LCD,
-               ((LcdModes[ModeNumber].HorizontalResolution - 1)
-               | ((LcdModes[ModeNumber].VerticalResolution - 1) << 16))
-              );
-  MmioWrite32 (DISPC_TIMING_H,
-               ( (LcdModes[ModeNumber].HSync - 1)
-               | ((LcdModes[ModeNumber].HFrontPorch - 1) << 8)
-               | ((LcdModes[ModeNumber].HBackPorch - 1) << 20))
-              );
-  MmioWrite32 (DISPC_TIMING_V,
-               ( (LcdModes[ModeNumber].VSync - 1)
-               | ((LcdModes[ModeNumber].VFrontPorch - 1) << 8)
-               | ((LcdModes[ModeNumber].VBackPorch - 1) << 20))
-              );
-
-  // Set the framebuffer to only load frames (no gamma tables)
-  MmioAnd32 (DISPC_CONFIG, CLEARLOADMODE);
-  MmioOr32  (DISPC_CONFIG, LOAD_FRAME_ONLY);
-
-  // Divisor for the pixel clock
-  MmioWrite32(DISPC_DIVISOR, ((1 << 16) | LcdModes[ModeNumber].DispcDivisor) );
-
-  // Set up the graphics layer
-  MmioWrite32 (DISPC_GFX_PRELD, 0x2D8);
-  MmioWrite32 (DISPC_GFX_BA0, VramBaseAddress);
-  MmioWrite32 (DISPC_GFX_SIZE,
-               ((LcdModes[ModeNumber].HorizontalResolution - 1)
-               | ((LcdModes[ModeNumber].VerticalResolution - 1) << 16))
-              );
-
-  MmioWrite32(DISPC_GFX_ATTR, (GFXENABLE | RGB16 | BURSTSIZE16));
-
-  // Start it all
-  MmioOr32 (DISPC_CONTROL, (LCDENABLE | ACTIVEMATRIX | DATALINES24 | BYPASS_MODE | LCDENABLESIGNAL));
-  MmioOr32 (DISPC_CONTROL, GOLCD);
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-HwInitializeDisplay (
-  UINTN VramBaseAddress,
-  UINTN VramSize
-  )
-{
-  EFI_STATUS    Status;
-  UINT8         Data;
-  EFI_TPL       OldTpl;
-  EMBEDDED_EXTERNAL_DEVICE   *gTPS65950;
-
-  // Enable power lines used by TFP410
-  Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
-  ASSERT_EFI_ERROR (Status);
-
-  OldTpl = gBS->RaiseTPL(TPL_NOTIFY);
-  Data = VAUX_DEV_GRP_P1;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VPLL2_DEV_GRP), 1, &Data);
-  ASSERT_EFI_ERROR(Status);
-
-  Data = VAUX_DEDICATED_18V;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VPLL2_DEDICATED), 1, &Data);
-  ASSERT_EFI_ERROR (Status);
-
-  // Power up TFP410 (set GPIO2 on TPS - for BeagleBoard-xM)
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATADIR1), 1, &Data);
-  ASSERT_EFI_ERROR (Status);
-  Data |= BIT2;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATADIR1), 1, &Data);
-  ASSERT_EFI_ERROR (Status);
-
-  Data = BIT2;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, SETGPIODATAOUT1), 1, &Data);
-  ASSERT_EFI_ERROR (Status);
-
-  gBS->RestoreTPL(OldTpl);
-
-  // Power up TFP410 (set GPIO 170 - for older BeagleBoards)
-  MmioAnd32 (GPIO6_BASE + GPIO_OE, ~BIT10);
-  MmioOr32  (GPIO6_BASE + GPIO_SETDATAOUT, BIT10);
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-InitializeDisplay (
-  IN LCD_INSTANCE* Instance
-  )
-{
-  EFI_STATUS           Status;
-  UINTN                VramSize;
-  EFI_PHYSICAL_ADDRESS VramBaseAddress;
-
-  Status = LcdPlatformGetVram (&VramBaseAddress, &VramSize);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Instance->Mode.FrameBufferBase = VramBaseAddress;
-  Instance->Mode.FrameBufferSize = VramSize;
-
-  Status = HwInitializeDisplay((UINTN)VramBaseAddress, VramSize);
-  if (!EFI_ERROR (Status)) {
-    mDisplayInitialized = TRUE;
-  }
-
-  return Status;
-}
-
-EFI_STATUS
-EFIAPI
-LcdGraphicsQueryMode (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL            *This,
-  IN UINT32                                  ModeNumber,
-  OUT UINTN                                  *SizeOfInfo,
-  OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION   **Info
-  )
-{
-  LCD_INSTANCE  *Instance;
-
-  Instance = LCD_INSTANCE_FROM_GOP_THIS(This);
-
-  if (!mDisplayInitialized) {
-    InitializeDisplay (Instance);
-  }
-
-  // Error checking
-  if ( (This == NULL) || (Info == NULL) || (SizeOfInfo == NULL) || (ModeNumber >= This->Mode->MaxMode) ) {
-    DEBUG((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d : Invalid Parameter.\n", ModeNumber ));
-    return EFI_INVALID_PARAMETER;
-  }
-
-  *Info = AllocateCopyPool(sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), &Instance->ModeInfo);
-  if (*Info == NULL) {
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  *SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION);
-
-  (*Info)->Version = 0;
-  (*Info)->HorizontalResolution = LcdModes[ModeNumber].HorizontalResolution;
-  (*Info)->VerticalResolution = LcdModes[ModeNumber].VerticalResolution;
-  (*Info)->PixelFormat = PixelBltOnly;
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-LcdGraphicsSetMode (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL   *This,
-  IN UINT32                         ModeNumber
-  )
-{
-  LCD_INSTANCE  *Instance;
-
-  Instance = LCD_INSTANCE_FROM_GOP_THIS(This);
-
-  if (ModeNumber >= Instance->Mode.MaxMode) {
-    return EFI_UNSUPPORTED;
-  }
-
-  if (!mDisplayInitialized) {
-    InitializeDisplay (Instance);
-  }
-
-  DssSetMode((UINT32)Instance->Mode.FrameBufferBase, ModeNumber);
-
-  Instance->Mode.Mode = ModeNumber;
-  Instance->ModeInfo.HorizontalResolution = LcdModes[ModeNumber].HorizontalResolution;
-  Instance->ModeInfo.VerticalResolution = LcdModes[ModeNumber].VerticalResolution;
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-LcdGraphicsOutputDxeInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS Status = EFI_SUCCESS;
-  LCD_INSTANCE* Instance;
-
-  Status = LcdInstanceContructor (&Instance);
-  if (EFI_ERROR(Status)) {
-    goto EXIT;
-  }
-
-  // Install the Graphics Output Protocol and the Device Path
-  Status = gBS->InstallMultipleProtocolInterfaces(
-             &Instance->Handle,
-             &gEfiGraphicsOutputProtocolGuid, &Instance->Gop,
-             &gEfiDevicePathProtocolGuid,     &Instance->DevicePath,
-             NULL
-             );
-
-  if (EFI_ERROR(Status)) {
-    DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the protocol. Exit Status=%r\n", Status));
-    goto EXIT;
-  }
-
-  // Register for an ExitBootServicesEvent
-  // When ExitBootServices starts, this function here will make sure that the graphics driver will shut down properly,
-  // i.e. it will free up all allocated memory and perform any necessary hardware re-configuration.
-  /*Status = gBS->CreateEvent (
-               EVT_SIGNAL_EXIT_BOOT_SERVICES,
-               TPL_NOTIFY,
-               LcdGraphicsExitBootServicesEvent, NULL,
-               &Instance->ExitBootServicesEvent
-               );
-
-  if (EFI_ERROR(Status)) {
-    DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the ExitBootServicesEvent handler. Exit Status=%r\n", Status));
-    goto EXIT_ERROR_UNINSTALL_PROTOCOL;
-  }*/
-
-  // To get here, everything must be fine, so just exit
-  goto EXIT;
-
-//EXIT_ERROR_UNINSTALL_PROTOCOL:
-  /* The following function could return an error message,
-   * however, to get here something must have gone wrong already,
-   * so preserve the original error, i.e. don't change
-   * the Status variable, even it fails to uninstall the protocol.
-   */
-  /*  gBS->UninstallMultipleProtocolInterfaces (
-        Instance->Handle,
-        &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, // Uninstall Graphics Output protocol
-        &gEfiDevicePathProtocolGuid,     &Instance->DevicePath,     // Uninstall device path
-        NULL
-        );*/
-
-EXIT:
-  return Status;
-
-}
diff --git a/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h b/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h
deleted file mode 100644
index a1bd7af..0000000
--- a/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/** @file
-
- Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution.  The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __OMAP3_DSS_GRAPHICS__
-#define __OMAP3_DSS_GRAPHICS__
-
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/DebugLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/IoLib.h>
-
-#include <Protocol/DevicePathToText.h>
-#include <Protocol/EmbeddedExternalDevice.h>
-#include <Protocol/Cpu.h>
-
-#include <Guid/GlobalVariable.h>
-
-#include <Omap3530/Omap3530.h>
-#include <TPS65950.h>
-
-typedef struct {
-  VENDOR_DEVICE_PATH            Guid;
-  EFI_DEVICE_PATH_PROTOCOL      End;
-} LCD_GRAPHICS_DEVICE_PATH;
-
-typedef struct {
-  UINTN                                 Signature;
-  EFI_HANDLE                            Handle;
-  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  ModeInfo;
-  EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE     Mode;
-  EFI_GRAPHICS_OUTPUT_PROTOCOL          Gop;
-  LCD_GRAPHICS_DEVICE_PATH              DevicePath;
-//  EFI_EVENT                             ExitBootServicesEvent;
-} LCD_INSTANCE;
-
-#define LCD_INSTANCE_SIGNATURE  SIGNATURE_32('l', 'c', 'd', '0')
-#define LCD_INSTANCE_FROM_GOP_THIS(a)     CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE)
-
-typedef struct {
-  UINTN             Mode;
-  UINTN             HorizontalResolution;
-  UINTN             VerticalResolution;
-
-  UINT32            DssDivisor;
-  UINT32            DispcDivisor;
-
-  UINT32            HSync;
-  UINT32            HFrontPorch;
-  UINT32            HBackPorch;
-
-  UINT32            VSync;
-  UINT32            VFrontPorch;
-  UINT32            VBackPorch;
-} LCD_MODE;
-
-EFI_STATUS
-InitializeDisplay (
-  IN LCD_INSTANCE* Instance
-);
-
-EFI_STATUS
-EFIAPI
-LcdGraphicsQueryMode (
-  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL          *This,
-  IN  UINT32                                ModeNumber,
-  OUT UINTN                                 *SizeOfInfo,
-  OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  **Info
-);
-
-EFI_STATUS
-EFIAPI
-LcdGraphicsSetMode (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL  *This,
-  IN UINT32                        ModeNumber
-);
-
-EFI_STATUS
-EFIAPI
-LcdGraphicsBlt (
-  IN EFI_GRAPHICS_OUTPUT_PROTOCOL        *This,
-  IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL   *BltBuffer,     OPTIONAL
-  IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION   BltOperation,
-  IN UINTN                               SourceX,
-  IN UINTN                               SourceY,
-  IN UINTN                               DestinationX,
-  IN UINTN                               DestinationY,
-  IN UINTN                               Width,
-  IN UINTN                               Height,
-  IN UINTN                               Delta           OPTIONAL   // Number of BYTES in a row of the BltBuffer
-);
-
-// HW registers
-#define CM_FCLKEN_DSS   0x48004E00
-#define CM_ICLKEN_DSS   0x48004E10
-
-#define DSS_CONTROL     0x48050040
-#define DSS_SYSCONFIG   0x48050010
-#define DSS_SYSSTATUS   0x48050014
-
-#define DISPC_CONTROL   0x48050440
-#define DISPC_CONFIG    0x48050444
-#define DISPC_SIZE_LCD  0x4805047C
-#define DISPC_TIMING_H  0x48050464
-#define DISPC_TIMING_V  0x48050468
-
-#define CM_CLKSEL_DSS   0x48004E40
-#define DISPC_DIVISOR   0x48050470
-#define DISPC_POL_FREQ  0x4805046C
-
-#define DISPC_GFX_TABLE_BA 0x480504B8
-#define DISPC_GFX_BA0   0x48050480
-#define DISPC_GFX_BA1   0x48050484
-#define DISPC_GFX_POS   0x48050488
-#define DISPC_GFX_SIZE  0x4805048C
-#define DISPC_GFX_ATTR  0x480504A0
-#define DISPC_GFX_PRELD 0x4805062C
-
-#define DISPC_DEFAULT_COLOR_0 0x4805044C
-
-//#define DISPC_IRQSTATUS
-
-// Bits
-#define EN_TV           0x4
-#define EN_DSS2         0x2
-#define EN_DSS1         0x1
-#define EN_DSS          0x1
-
-#define DSS_SOFTRESET   0x2
-#define DSS_RESETDONE   0x1
-
-#define BYPASS_MODE     (BIT15 | BIT16)
-
-#define LCDENABLE       BIT0
-#define ACTIVEMATRIX    BIT3
-#define GOLCD           BIT5
-#define DATALINES24     (BIT8 | BIT9)
-#define LCDENABLESIGNAL BIT28
-
-#define GFXENABLE       BIT0
-#define RGB16           (0x6 << 1)
-#define BURSTSIZE16     (0x2 << 6)
-
-#define CLEARLOADMODE   ~(BIT2 | BIT1)
-#define LOAD_FRAME_ONLY BIT2
-
-#endif
diff --git a/Chips/TexasInstruments/Omap35xx/Library/DebugAgentTimerLib/DebugAgentTimerLib.c b/Chips/TexasInstruments/Omap35xx/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
deleted file mode 100755
index 11f0bdd..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/** @file
-  Debug Agent timer lib for OMAP 35xx.
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-#include <Base.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/OmapLib.h>
-#include <Library/ArmLib.h>
-#include <Library/PcdLib.h>
-
-#include <Omap3530/Omap3530.h>
-
-
-volatile UINT32 gVector;
-
-// Cached registers
-volatile UINT32 gTISR;
-volatile UINT32 gTCLR;
-volatile UINT32 gTLDR;
-volatile UINT32 gTCRR;
-volatile UINT32 gTIER;
-
-VOID
-EnableInterruptSource (
-  VOID
-  )
-{
-  UINTN Bank;
-  UINTN Bit;
-
-  // Map vector to FIQ, IRQ is default
-  MmioWrite32 (INTCPS_ILR (gVector), 1);
-
-  Bank = gVector / 32;
-  Bit  = 1UL << (gVector % 32);
-
-  MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
-}
-
-VOID
-DisableInterruptSource (
-  VOID
-  )
-{
-  UINTN Bank;
-  UINTN Bit;
-
-  Bank = gVector / 32;
-  Bit  = 1UL << (gVector % 32);
-
-  MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
-}
-
-
-
-/**
-  Setup all the hardware needed for the debug agents timer.
-
-  This function is used to set up debug enviroment. It may enable interrupts.
-
-**/
-VOID
-EFIAPI
-DebugAgentTimerIntialize (
-  VOID
-  )
-{
-  UINT32      TimerBaseAddress;
-  UINT32      TimerNumber;
-
-  TimerNumber = PcdGet32(PcdOmap35xxDebugAgentTimer);
-  gVector = InterruptVectorForTimer (TimerNumber);
-
-  // Set up the timer registers
-  TimerBaseAddress = TimerBase (TimerNumber);
-  gTISR = TimerBaseAddress + GPTIMER_TISR;
-  gTCLR = TimerBaseAddress + GPTIMER_TCLR;
-  gTLDR = TimerBaseAddress + GPTIMER_TLDR;
-  gTCRR = TimerBaseAddress + GPTIMER_TCRR;
-  gTIER = TimerBaseAddress + GPTIMER_TIER;
-
-  if ((TimerNumber < 2) || (TimerNumber > 9)) {
-    // This code assumes one the General Purpose timers is used
-    // GPT2 - GPT9
-    CpuDeadLoop ();
-  }
-  // Set source clock for GPT2 - GPT9 to SYS_CLK
-  MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2));
-
-}
-
-
-/**
-  Set the period for the debug agent timer. Zero means disable the timer.
-
-  @param[in] TimerPeriodMilliseconds    Frequency of the debug agent timer.
-
-**/
-VOID
-EFIAPI
-DebugAgentTimerSetPeriod (
-  IN  UINT32  TimerPeriodMilliseconds
-  )
-{
-  UINT64      TimerCount;
-  INT32       LoadValue;
-
-  if (TimerPeriodMilliseconds == 0) {
-    // Turn off GPTIMER3
-    MmioWrite32 (gTCLR, TCLR_ST_OFF);
-
-    DisableInterruptSource ();
-  } else {
-    // Calculate required timer count
-    TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds));
-
-    // Set GPTIMER5 Load register
-    LoadValue = (INT32) -TimerCount;
-    MmioWrite32 (gTLDR, LoadValue);
-    MmioWrite32 (gTCRR, LoadValue);
-
-    // Enable Overflow interrupt
-    MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
-
-    // Turn on GPTIMER3, it will reload at overflow
-    MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
-
-    EnableInterruptSource ();
-  }
-}
-
-
-/**
-  Perform End Of Interrupt for the debug agent timer. This is called in the
-  interrupt handler after the interrupt has been processed.
-
-**/
-VOID
-EFIAPI
-DebugAgentTimerEndOfInterrupt (
-  VOID
-  )
-{
-   // Clear all timer interrupts
-  MmioWrite32 (gTISR, TISR_CLEAR_ALL);
-
-  // Poll interrupt status bits to ensure clearing
-  while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
-
-  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);
-  ArmDataSynchronizationBarrier ();
-
-}
-
diff --git a/Chips/TexasInstruments/Omap35xx/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf b/Chips/TexasInstruments/Omap35xx/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
deleted file mode 100755
index bf09b11..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
+++ /dev/null
@@ -1,46 +0,0 @@
-#/** @file
-# Component description file for Base PCI Cf8 Library.
-#
-# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.
-#  Layers on top of an I/O Library instance.
-# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = DebugAgentTimerLibNull
-  FILE_GUID                      = E82F99DE-74ED-4e56-BBA1-B143FCA3F69A
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = DebugAgentTimerLib|SEC BASE DXE_CORE
-
-
-[Sources.common]
-  DebugAgentTimerLib.c
-
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-  ArmPkg/ArmPkg.dec
-
-
-[LibraryClasses]
-  BaseLib
-  IoLib
-  OmapLib
-  ArmLib
-
-[Pcd]
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxDebugAgentTimer
-  gOmap35xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds
diff --git a/Chips/TexasInstruments/Omap35xx/Library/EblCmdLib/EblCmdLib.c b/Chips/TexasInstruments/Omap35xx/Library/EblCmdLib/EblCmdLib.c
deleted file mode 100644
index 4716175..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/EblCmdLib/EblCmdLib.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/** @file
-  Add custom commands for BeagleBoard development.
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-#include <Library/ArmLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/EblCmdLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiLib.h>
-#include <Library/PcdLib.h>
-#include <Library/EfiFileLib.h>
-
-
-//PcdEmbeddedFdBaseAddress
-
-/**
-  Fill Me In
-
-  Argv[0] - "%CommandName%"
-
-  @param  Argc   Number of command arguments in Argv
-  @param  Argv   Array of strings that represent the parsed command line.
-                 Argv[0] is the command name
-
-  @return EFI_SUCCESS
-
-**/
-EFI_STATUS
-EblEdk2Cmd (
-  IN UINTN  Argc,
-  IN CHAR8  **Argv
-  )
-{
-  return EFI_SUCCESS;
-}
-
-
-GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] =
-{
-  {
-    "edk2",
-    " filename ; Load FD into memory and boot from it",
-    NULL,
-    EblEdk2Cmd
-  }
-};
-
-
-VOID
-EblInitializeExternalCmd (
-  VOID
-  )
-{
-  EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE));
-  return;
-}
diff --git a/Chips/TexasInstruments/Omap35xx/Library/EblCmdLib/EblCmdLib.inf b/Chips/TexasInstruments/Omap35xx/Library/EblCmdLib/EblCmdLib.inf
deleted file mode 100644
index dd7a13c..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/EblCmdLib/EblCmdLib.inf
+++ /dev/null
@@ -1,48 +0,0 @@
-#/** @file
-# Component description file for the entry point to a EFIDXE Drivers
-#
-# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification
-# Copyright (c) 2007 - 2007, Intel Corporation. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardEblCmdLib
-  FILE_GUID                      = ea62bdc3-1063-425f-8851-98cb47f213a8
-  MODULE_TYPE                    = UEFI_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER
-
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC
-#
-
-[Sources.common]
-  EblCmdLib.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  ArmPkg/ArmPkg.dec
-
-[LibraryClasses]
-  BaseLib
-  DebugLib
-
-[Protocols]
-
-[Guids]
-
-[Pcd]
diff --git a/Chips/TexasInstruments/Omap35xx/Library/GdbSerialLib/GdbSerialLib.c b/Chips/TexasInstruments/Omap35xx/Library/GdbSerialLib/GdbSerialLib.c
deleted file mode 100644
index dcc5182..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/GdbSerialLib/GdbSerialLib.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/** @file
-  Basic serial IO abstaction for GDB
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Uefi.h>
-#include <Library/GdbSerialLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Library/OmapLib.h>
-#include <Omap3530/Omap3530.h>
-
-RETURN_STATUS
-EFIAPI
-GdbSerialLibConstructor (
-  VOID
-  )
-{
-  return RETURN_SUCCESS;
-}
-
-RETURN_STATUS
-EFIAPI
-GdbSerialInit (
-  IN UINT64     BaudRate,
-  IN UINT8      Parity,
-  IN UINT8      DataBits,
-  IN UINT8      StopBits
-  )
-{
-  return RETURN_SUCCESS;
-}
-
-BOOLEAN
-EFIAPI
-GdbIsCharAvailable (
-  VOID
-  )
-{
-  UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-
-  if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-CHAR8
-EFIAPI
-GdbGetChar (
-  VOID
-  )
-{
-  UINT32  LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-  UINT32  RBR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_RBR_REG;
-  CHAR8   Char;
-
-  while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
-  Char = MmioRead8(RBR);
-
-  return Char;
-}
-
-VOID
-EFIAPI
-GdbPutChar (
-  IN  CHAR8   Char
-  )
-{
-  UINT32  LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-  UINT32  THR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_THR_REG;
-
-  while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
-  MmioWrite8(THR, Char);
-}
-
-VOID
-GdbPutString (
-  IN CHAR8  *String
-  )
-{
-  while (*String != '\0') {
-    GdbPutChar (*String);
-    String++;
-  }
-}
-
-
-
-
diff --git a/Chips/TexasInstruments/Omap35xx/Library/GdbSerialLib/GdbSerialLib.inf b/Chips/TexasInstruments/Omap35xx/Library/GdbSerialLib/GdbSerialLib.inf
deleted file mode 100644
index 2cacd0f..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/GdbSerialLib/GdbSerialLib.inf
+++ /dev/null
@@ -1,41 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = GdbSerialLib
-  FILE_GUID                      = E2423349-EF5D-439B-95F5-8B8D8E3B443F
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = GdbSerialLib
-
-  CONSTRUCTOR                    = GdbSerialLibConstructor
-
-
-[Sources.common]
-  GdbSerialLib.c
-
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  DebugLib
-  IoLib
-  OmapLib
-
-[FixedPcd]
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart
-
diff --git a/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf b/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
deleted file mode 100644
index e20b654..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
+++ /dev/null
@@ -1,45 +0,0 @@
-#/** @file
-# Timer library implementation
-#
-# A non-functional instance of the Timer Library that can be used as a template
-#  for the implementation of a functional timer library instance. This library instance can
-#  also be used to test build DXE, Runtime, DXE SAL, and DXE SMM modules that require timer
-#  services as well as EBC modules that require timer services
-# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardTimerLib
-  FILE_GUID                      = fe1d7183-9abb-42ce-9a3b-36d7c6a8959f
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = TimerLib
-
-[Sources.common]
-  TimerLib.c
-
-[Packages]
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-
-[LibraryClasses]
-  DebugLib
-  OmapLib
-  IoLib
-
-[Pcd]
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer
-
diff --git a/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/TimerLib.c b/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/TimerLib.c
deleted file mode 100644
index 652c47b..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/TimerLib.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Uefi.h>
-
-#include <Library/BaseLib.h>
-#include <Library/TimerLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/OmapLib.h>
-
-#include <Omap3530/Omap3530.h>
-
-RETURN_STATUS
-EFIAPI
-TimerConstructor (
-  VOID
-  )
-{
-  UINTN  Timer            = PcdGet32(PcdOmap35xxFreeTimer);
-  UINT32 TimerBaseAddress = TimerBase(Timer);
-
-  if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {
-    // Set source clock for GPT3 & GPT4 to SYS_CLK
-    MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
-
-    // Set count & reload registers
-    MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
-    MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
-
-    // Disable interrupts
-    MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
-
-    // Start Timer
-    MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
-
-    // Disable OMAP Watchdog timer (WDT2)
-    MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
-    DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
-    MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
-  }
-  return EFI_SUCCESS;
-}
-
-UINTN
-EFIAPI
-MicroSecondDelay (
-  IN  UINTN MicroSeconds
-  )
-{
-  UINT64  NanoSeconds;
-
-  NanoSeconds = MultU64x32(MicroSeconds, 1000);
-
-  while (NanoSeconds > (UINTN)-1) {
-    NanoSecondDelay((UINTN)-1);
-    NanoSeconds -= (UINTN)-1;
-  }
-
-  NanoSecondDelay(NanoSeconds);
-
-  return MicroSeconds;
-}
-
-UINTN
-EFIAPI
-NanoSecondDelay (
-  IN  UINTN NanoSeconds
-  )
-{
-  UINT32  Delay;
-  UINT32  StartTime;
-  UINT32  CurrentTime;
-  UINT32  ElapsedTime;
-  UINT32  TimerCountRegister;
-
-  Delay = (NanoSeconds / PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)) + 1;
-
-  TimerCountRegister = TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR;
-
-  StartTime = MmioRead32 (TimerCountRegister);
-
-  do
-  {
-    CurrentTime = MmioRead32 (TimerCountRegister);
-    ElapsedTime = CurrentTime - StartTime;
-  } while (ElapsedTime < Delay);
-
-  NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds);
-
-  return NanoSeconds;
-}
-
-UINT64
-EFIAPI
-GetPerformanceCounter (
-  VOID
-  )
-{
-  return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR);
-}
-
-UINT64
-EFIAPI
-GetPerformanceCounterProperties (
-  OUT UINT64  *StartValue,  OPTIONAL
-  OUT UINT64  *EndValue     OPTIONAL
-  )
-{
-  if (StartValue != NULL) {
-    // Timer starts with the reload value
-    *StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TLDR);
-  }
-
-  if (EndValue != NULL) {
-    // Timer counts up to 0xFFFFFFFF
-    *EndValue = 0xFFFFFFFF;
-  }
-
-  return PcdGet64(PcdEmbeddedPerformanceCounterFrequencyInHz);
-}
diff --git a/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/OmapDmaLib.c b/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/OmapDmaLib.c
deleted file mode 100755
index 41cfefb..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/OmapDmaLib.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/** @file
-  Abstractions for simple OMAP DMA channel.
-
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Base.h>
-#include <Library/DebugLib.h>
-#include <Library/OmapDmaLib.h>
-#include <Library/IoLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Omap3530/Omap3530.h>
-
-
-/**
-  Configure OMAP DMA Channel
-
-  @param  Channel               DMA Channel to configure
-  @param  Dma4                  Pointer to structure used to initialize DMA registers for the Channel
-
-  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
-  @retval EFI_INVALID_PARAMETER Channel is not valid
-  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.
-
-**/
-EFI_STATUS
-EFIAPI
-EnableDmaChannel (
-  IN  UINTN       Channel,
-  IN  OMAP_DMA4   *DMA4
-  )
-{
-  UINT32  RegVal;
-
-
-  if (Channel > DMA4_MAX_CHANNEL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  /* 1) Configure the transfer parameters in the logical DMA registers */
-  /*-------------------------------------------------------------------*/
-
-  /* a) Set the data type CSDP[1:0], the Read/Write Port access type
-        CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],
-        write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */
-
-  // Read CSDP
-  RegVal = MmioRead32 (DMA4_CSDP (Channel));
-
-  // Build reg
-  RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );
-  RegVal = ((RegVal & ~(0x3 <<  7)) | (DMA4->ReadPortAccessType << 7));
-  RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));
-  RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));
-  RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));
-  RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));
-  RegVal = ((RegVal & ~(0x1 <<  6)) | (DMA4->SourcePacked << 6));
-  RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));
-  // Write CSDP
-  MmioWrite32 (DMA4_CSDP (Channel), RegVal);
-
-  /* b) Set the number of element per frame CEN[23:0]*/
-  MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);
-
-  /* c) Set the number of frame per block CFN[15:0]*/
-  MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);
-
-  /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/
-  MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);
-  MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);
-
-  /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],
-        read/write priority CCR[6]/CCR[26]
-        I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to
-        LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber
-  */
-
-  // Read CCR
-  RegVal = MmioRead32 (DMA4_CCR (Channel));
-
-  // Build reg
-  RegVal  = ((RegVal &  ~0x1f)            | DMA4->ReadRequestNumber);
-  RegVal  = ((RegVal &  ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);
-  RegVal  = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12));
-  RegVal  = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));
-  RegVal  = ((RegVal & ~(0x1 <<  6)) | (DMA4->ReadPriority << 6));
-  RegVal  = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));
-
-  // Write CCR
-  MmioWrite32 (DMA4_CCR (Channel), RegVal);
-
-  /* f)- Set the source element index CSEI[15:0]*/
-  MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);
-
-  /* - Set the source frame index CSFI[15:0]*/
-  MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);
-
-
-  /* - Set the destination element index CDEI[15:0]*/
-  MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);
-
-  /* - Set the destination frame index CDFI[31:0]*/
-  MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
-
-  MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
-
-  // Enable all the status bits since we are polling
-  MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);
-  MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);
-
-  /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */
-  /*--------------------------------------------------------------*/
-  //write enable bit
-  MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer
-
-  return EFI_SUCCESS;
-}
-
-/**
-  Turn of DMA channel configured by EnableDma().
-
-  @param  Channel               DMA Channel to configure
-  @param  SuccesMask            Bits in DMA4_CSR register indicate EFI_SUCCESS
-  @param  ErrorMask             Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
-
-  @retval EFI_SUCCESS           DMA hardware disabled
-  @retval EFI_INVALID_PARAMETER Channel is not valid
-  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.
-
-**/
-EFI_STATUS
-EFIAPI
-DisableDmaChannel (
-  IN  UINTN       Channel,
-  IN  UINT32      SuccessMask,
-  IN  UINT32      ErrorMask
-  )
-{
-  EFI_STATUS  Status = EFI_SUCCESS;
-  UINT32      Reg;
-
-
-  if (Channel > DMA4_MAX_CHANNEL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  do {
-    Reg = MmioRead32 (DMA4_CSR(Channel));
-    if ((Reg & ErrorMask) != 0) {
-      Status = EFI_DEVICE_ERROR;
-      DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));
-      break;
-    }
-  } while ((Reg & SuccessMask) != SuccessMask);
-
-
-  // Disable all status bits and clear them
-  MmioWrite32 (DMA4_CICR (Channel), 0);
-  MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);
-
-  MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
-  return Status;
-}
-
-
-
diff --git a/Chips/TexasInstruments/Omap35xx/Library/OmapLib/OmapLib.c b/Chips/TexasInstruments/Omap35xx/Library/OmapLib/OmapLib.c
deleted file mode 100644
index 29645ee..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/OmapLib/OmapLib.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Base.h>
-#include <Library/DebugLib.h>
-#include <Library/OmapLib.h>
-#include <Omap3530/Omap3530.h>
-
-UINT32
-GpioBase (
-  IN  UINTN Port
-  )
-{
-  switch (Port) {
-  case 1:  return GPIO1_BASE;
-  case 2:  return GPIO2_BASE;
-  case 3:  return GPIO3_BASE;
-  case 4:  return GPIO4_BASE;
-  case 5:  return GPIO5_BASE;
-  case 6:  return GPIO6_BASE;
-  default: ASSERT(FALSE); return 0;
-  }
-}
-
-UINT32
-TimerBase (
-  IN  UINTN Timer
-  )
-{
-  switch (Timer) {
-  case  1: return GPTIMER1_BASE;
-  case  2: return GPTIMER2_BASE;
-  case  3: return GPTIMER3_BASE;
-  case  4: return GPTIMER4_BASE;
-  case  5: return GPTIMER5_BASE;
-  case  6: return GPTIMER6_BASE;
-  case  7: return GPTIMER7_BASE;
-  case  8: return GPTIMER8_BASE;
-  case  9: return GPTIMER9_BASE;
-  case 10: return GPTIMER10_BASE;
-  case 11: return GPTIMER11_BASE;
-  case 12: return GPTIMER12_BASE;
-  default: return 0;
-  }
-}
-
-UINTN
-InterruptVectorForTimer (
-  IN  UINTN Timer
-  )
-{
-  if ((Timer < 1) || (Timer > 12)) {
-    ASSERT(FALSE);
-    return 0xFFFFFFFF;
-  }
-
-  return 36 + Timer;
-}
-
-UINT32
-UartBase (
-  IN  UINTN Uart
-  )
-{
-  switch (Uart) {
-  case 1:  return UART1_BASE;
-  case 2:  return UART2_BASE;
-  case 3:  return UART3_BASE;
-  default: ASSERT(FALSE); return 0;
-  }
-}
-
diff --git a/Chips/TexasInstruments/Omap35xx/Library/RealTimeClockLib/RealTimeClockLib.c b/Chips/TexasInstruments/Omap35xx/Library/RealTimeClockLib/RealTimeClockLib.c
deleted file mode 100755
index 0ae452e..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/RealTimeClockLib/RealTimeClockLib.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2011, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-
-#include <Protocol/RealTimeClock.h>
-#include <Protocol/EmbeddedExternalDevice.h>
-
-#include <Omap3530/Omap3530.h>
-#include <TPS65950.h>
-
-
-EMBEDDED_EXTERNAL_DEVICE   *gTPS65950;
-INT16                      TimeZone = EFI_UNSPECIFIED_TIMEZONE;
-
-/**
-  Returns the current time and date information, and the time-keeping capabilities
-  of the hardware platform.
-
-  @param  Time                  A pointer to storage to receive a snapshot of the current time.
-  @param  Capabilities          An optional pointer to a buffer to receive the real time clock
-                                device's capabilities.
-
-  @retval EFI_SUCCESS           The operation completed successfully.
-  @retval EFI_INVALID_PARAMETER Time is NULL.
-  @retval EFI_DEVICE_ERROR      The time could not be retrieved due to hardware error.
-
-**/
-EFI_STATUS
-EFIAPI
-LibGetTime (
-  OUT EFI_TIME                *Time,
-  OUT EFI_TIME_CAPABILITIES   *Capabilities
-  )
-{
-  EFI_STATUS            Status;
-  UINT8                 Data;
-  EFI_TPL               OldTpl;
-
-  if (Time == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  OldTpl = gBS->RaiseTPL(TPL_NOTIFY);
-
-  /* Get time and date */
-  ZeroMem(Time, sizeof(EFI_TIME));
-
-  // Latch values
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-  Data |= BIT6;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-
-  // Read registers
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-  Time->Year = 2000 + ((Data >> 4) & 0xF) * 10 + (Data & 0xF);
-
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-  Time->Month = ((Data >> 4) & 0x1) * 10 + (Data & 0xF);
-
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-  Time->Day = ((Data >> 4) & 0x3) * 10 + (Data & 0xF);
-
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-  Time->Hour = ((Data >> 4) & 0x3) * 10 + (Data & 0xF);
-
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-  Time->Minute = ((Data >> 4) & 0x7) * 10 + (Data & 0xF);
-
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-  Time->Second = ((Data >> 4) & 0x7) * 10 + (Data & 0xF);
-
-  Time->TimeZone = TimeZone;
-  // TODO: check what to use here
-  Time->Daylight = EFI_TIME_ADJUST_DAYLIGHT;
-
-  // Set capabilities
-
-  // TODO: Set real capabilities
-  if (Capabilities != NULL) {
-    Capabilities->Resolution = 1;
-    Capabilities->Accuracy = 50000000;
-    Capabilities->SetsToZero = FALSE;
-  }
-
-EXIT:
-  gBS->RestoreTPL(OldTpl);
-
-  return (Status == EFI_SUCCESS) ? Status : EFI_DEVICE_ERROR;
-}
-
-/**
-  Sets the current local time and date information.
-
-  @param  Time                  A pointer to the current time.
-
-  @retval EFI_SUCCESS           The operation completed successfully.
-  @retval EFI_INVALID_PARAMETER A time field is out of range.
-  @retval EFI_DEVICE_ERROR      The time could not be set due due to hardware error.
-
-**/
-EFI_STATUS
-EFIAPI
-LibSetTime (
-  IN EFI_TIME                *Time
-  )
-{
-  EFI_STATUS Status;
-  UINT8      Data;
-  UINT8      MonthDayCount[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
-  EFI_TPL    OldTpl;
-
-  // Input validation according both to UEFI spec and hardware constraints
-  // UEFI spec says valid year range is 1900-9999 but TPS only supports 2000-2099
-  if ( (Time == NULL)
-    || (Time->Year < 2000 || Time->Year > 2099)
-    || (Time->Month < 1 || Time->Month > 12)
-    || (Time->Day < 1 || Time->Day > MonthDayCount[Time->Month])
-    || (Time->Hour > 23)
-    || (Time->Minute > 59)
-    || (Time->Second > 59)
-    || (Time->Nanosecond > 999999999)
-    || ((Time->TimeZone < -1440 || Time->TimeZone > 1440) && Time->TimeZone != 2047)
-  ) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  OldTpl = gBS->RaiseTPL(TPL_NOTIFY);
-
-  Data = Time->Year - 2000;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-
-  Data = ((Time->Month / 10) << 4) | (Time->Month % 10);
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-
-  Data = ((Time->Day / 10) << 4) | (Time->Day % 10);
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-
-  Data = ((Time->Hour / 10) << 4) | (Time->Hour % 10);
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-
-  Data = ((Time->Minute / 10) << 4) | (Time->Minute % 10);
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-
-  Data = ((Time->Second / 10) << 4) | (Time->Second % 10);
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, &Data);
-  if (Status != EFI_SUCCESS) goto EXIT;
-
-  TimeZone = Time->TimeZone;
-
-EXIT:
-  gBS->RestoreTPL(OldTpl);
-
-  return (Status == EFI_SUCCESS) ? Status : EFI_DEVICE_ERROR;
-}
-
-/**
-  Returns the current wakeup alarm clock setting.
-
-  @param  Enabled               Indicates if the alarm is currently enabled or disabled.
-  @param  Pending               Indicates if the alarm signal is pending and requires acknowledgement.
-  @param  Time                  The current alarm setting.
-
-  @retval EFI_SUCCESS           The alarm settings were returned.
-  @retval EFI_INVALID_PARAMETER Any parameter is NULL.
-  @retval EFI_DEVICE_ERROR      The wakeup time could not be retrieved due to a hardware error.
-
-**/
-EFI_STATUS
-EFIAPI
-LibGetWakeupTime (
-  OUT BOOLEAN     *Enabled,
-  OUT BOOLEAN     *Pending,
-  OUT EFI_TIME    *Time
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  Sets the system wakeup alarm clock time.
-
-  @param  Enabled               Enable or disable the wakeup alarm.
-  @param  Time                  If Enable is TRUE, the time to set the wakeup alarm for.
-
-  @retval EFI_SUCCESS           If Enable is TRUE, then the wakeup alarm was enabled. If
-                                Enable is FALSE, then the wakeup alarm was disabled.
-  @retval EFI_INVALID_PARAMETER A time field is out of range.
-  @retval EFI_DEVICE_ERROR      The wakeup time could not be set due to a hardware error.
-  @retval EFI_UNSUPPORTED       A wakeup timer is not supported on this platform.
-
-**/
-EFI_STATUS
-EFIAPI
-LibSetWakeupTime (
-  IN BOOLEAN      Enabled,
-  OUT EFI_TIME    *Time
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  This is the declaration of an EFI image entry point. This can be the entry point to an application
-  written to this specification, an EFI boot service driver, or an EFI runtime driver.
-
-  @param  ImageHandle           Handle that identifies the loaded image.
-  @param  SystemTable           System Table for this image.
-
-  @retval EFI_SUCCESS           The operation completed successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-LibRtcInitialize (
-  IN EFI_HANDLE                            ImageHandle,
-  IN EFI_SYSTEM_TABLE                      *SystemTable
-  )
-{
-  EFI_STATUS    Status;
-  EFI_HANDLE    Handle;
-  UINT8         Data;
-  EFI_TPL       OldTpl;
-
-  Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
-  ASSERT_EFI_ERROR(Status);
-
-  OldTpl = gBS->RaiseTPL(TPL_NOTIFY);
-  Data = 1;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data);
-  ASSERT_EFI_ERROR(Status);
-  gBS->RestoreTPL(OldTpl);
-
-  // Setup the setters and getters
-  gRT->GetTime       = LibGetTime;
-  gRT->SetTime       = LibSetTime;
-  gRT->GetWakeupTime = LibGetWakeupTime;
-  gRT->SetWakeupTime = LibSetWakeupTime;
-
-  // Install the protocol
-  Handle = NULL;
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &Handle,
-                  &gEfiRealTimeClockArchProtocolGuid,  NULL,
-                  NULL
-                 );
-
-  return Status;
-}
-
-/**
-  Fixup internal data so that EFI can be call in virtual mode.
-  Call the passed in Child Notify event and convert any pointers in
-  lib to virtual mode.
-
-  @param[in]    Event   The Event that is being processed
-  @param[in]    Context Event Context
-**/
-VOID
-EFIAPI
-LibRtcVirtualNotifyEvent (
-  IN EFI_EVENT        Event,
-  IN VOID             *Context
-  )
-{
-  return;
-}
diff --git a/Chips/TexasInstruments/Omap35xx/Library/RealTimeClockLib/RealTimeClockLib.inf b/Chips/TexasInstruments/Omap35xx/Library/RealTimeClockLib/RealTimeClockLib.inf
deleted file mode 100755
index 83edd86..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/RealTimeClockLib/RealTimeClockLib.inf
+++ /dev/null
@@ -1,38 +0,0 @@
-#  Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = RealTimeClockLib
-  FILE_GUID                      = EC1713DB-7DB5-4c99-8FE2-6F52F95A1132
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = RealTimeClockLib
-
-[Sources.common]
-  RealTimeClockLib.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  IoLib
-  UefiLib
-  DebugLib
-  PcdLib
-
-[Protocols]
-  gEmbeddedExternalDeviceProtocolGuid
-
-[depex]
-  gEmbeddedExternalDeviceProtocolGuid
diff --git a/Chips/TexasInstruments/Omap35xx/Library/ResetSystemLib/ResetSystemLib.inf b/Chips/TexasInstruments/Omap35xx/Library/ResetSystemLib/ResetSystemLib.inf
deleted file mode 100644
index 20496fa..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/ResetSystemLib/ResetSystemLib.inf
+++ /dev/null
@@ -1,40 +0,0 @@
-#/** @file
-# Reset System lib to make it easy to port new platforms
-#
-# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardResetSystemLib
-  FILE_GUID                      = 781371a2-3fdd-41d4-96a1-7b34cbc9e895
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = EfiResetSystemLib
-
-
-[Sources.common]
-  ResetSystemLib.c
-
-[Packages]
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-
-[Pcd.common]
-  gArmTokenSpaceGuid.PcdCpuResetAddress
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
-
-[LibraryClasses]
-  DebugLib
-  BeagleBoardSystemLib
diff --git a/Chips/TexasInstruments/Omap35xx/Library/SerialPortLib/SerialPortLib.c b/Chips/TexasInstruments/Omap35xx/Library/SerialPortLib/SerialPortLib.c
deleted file mode 100644
index 7ac12c7..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/SerialPortLib/SerialPortLib.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/** @file
-  Serial I/O Port library functions with no library constructor/destructor
-
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Base.h>
-#include <Library/DebugLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/OmapLib.h>
-#include <Omap3530/Omap3530.h>
-
-/*
-
-  Programmed hardware of Serial port.
-
-  @return    Always return EFI_UNSUPPORTED.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortInitialize (
-  VOID
-  )
-{
-  // assume assembly code at reset vector has setup UART
-  return RETURN_SUCCESS;
-}
-
-/**
-  Write data to serial device.
-
-  @param  Buffer           Point of data buffer which need to be writed.
-  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.
-
-  @retval 0                Write data failed.
-  @retval !0               Actual number of bytes writed to serial device.
-
-**/
-UINTN
-EFIAPI
-SerialPortWrite (
-  IN UINT8     *Buffer,
-  IN UINTN     NumberOfBytes
-)
-{
-  UINT32  LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-  UINT32  THR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_THR_REG;
-  UINTN   Count;
-
-  for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
-    while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
-    MmioWrite8(THR, *Buffer);
-  }
-
-  return NumberOfBytes;
-}
-
-
-/**
-  Read data from serial device and save the datas in buffer.
-
-  @param  Buffer           Point of data buffer which need to be writed.
-  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.
-
-  @retval 0                Read data failed.
-  @retval !0               Aactual number of bytes read from serial device.
-
-**/
-UINTN
-EFIAPI
-SerialPortRead (
-  OUT UINT8     *Buffer,
-  IN  UINTN     NumberOfBytes
-)
-{
-  UINT32  LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-  UINT32  RBR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_RBR_REG;
-  UINTN   Count;
-
-  for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
-    while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
-    *Buffer = MmioRead8(RBR);
-  }
-
-  return NumberOfBytes;
-}
-
-
-/**
-  Check to see if any data is avaiable to be read from the debug device.
-
-  @retval EFI_SUCCESS       At least one byte of data is avaiable to be read
-  @retval EFI_NOT_READY     No data is avaiable to be read
-  @retval EFI_DEVICE_ERROR  The serial device is not functioning properly
-
-**/
-BOOLEAN
-EFIAPI
-SerialPortPoll (
-  VOID
-  )
-{
-  UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-
-  if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-/**
-  Sets the control bits on a serial device.
-
-  @param[in] Control            Sets the bits of Control that are settable.
-
-  @retval RETURN_SUCCESS        The new control bits were set on the serial device.
-  @retval RETURN_UNSUPPORTED    The serial device does not support this operation.
-  @retval RETURN_DEVICE_ERROR   The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortSetControl (
-  IN UINT32 Control
-  )
-{
-  return RETURN_UNSUPPORTED;
-}
-
-/**
-  Retrieve the status of the control bits on a serial device.
-
-  @param[out] Control           A pointer to return the current control signals from the serial device.
-
-  @retval RETURN_SUCCESS        The control bits were read from the serial device.
-  @retval RETURN_UNSUPPORTED    The serial device does not support this operation.
-  @retval RETURN_DEVICE_ERROR   The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortGetControl (
-  OUT UINT32 *Control
-  )
-{
-  *Control = 0;
-  if (!SerialPortPoll ()) {
-    *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY;
-  }
-  return RETURN_SUCCESS;
-}
-
-/**
-  Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
-  data bits, and stop bits on a serial device.
-
-  @param BaudRate           The requested baud rate. A BaudRate value of 0 will use the
-                            device's default interface speed.
-                            On output, the value actually set.
-  @param ReveiveFifoDepth   The requested depth of the FIFO on the receive side of the
-                            serial interface. A ReceiveFifoDepth value of 0 will use
-                            the device's default FIFO depth.
-                            On output, the value actually set.
-  @param Timeout            The requested time out for a single character in microseconds.
-                            This timeout applies to both the transmit and receive side of the
-                            interface. A Timeout value of 0 will use the device's default time
-                            out value.
-                            On output, the value actually set.
-  @param Parity             The type of parity to use on this serial device. A Parity value of
-                            DefaultParity will use the device's default parity value.
-                            On output, the value actually set.
-  @param DataBits           The number of data bits to use on the serial device. A DataBits
-                            vaule of 0 will use the device's default data bit setting.
-                            On output, the value actually set.
-  @param StopBits           The number of stop bits to use on this serial device. A StopBits
-                            value of DefaultStopBits will use the device's default number of
-                            stop bits.
-                            On output, the value actually set.
-
-  @retval RETURN_SUCCESS            The new attributes were set on the serial device.
-  @retval RETURN_UNSUPPORTED        The serial device does not support this operation.
-  @retval RETURN_INVALID_PARAMETER  One or more of the attributes has an unsupported value.
-  @retval RETURN_DEVICE_ERROR       The serial device is not functioning correctly.
-
-**/
-RETURN_STATUS
-EFIAPI
-SerialPortSetAttributes (
-  IN OUT UINT64             *BaudRate,
-  IN OUT UINT32             *ReceiveFifoDepth,
-  IN OUT UINT32             *Timeout,
-  IN OUT EFI_PARITY_TYPE    *Parity,
-  IN OUT UINT8              *DataBits,
-  IN OUT EFI_STOP_BITS_TYPE *StopBits
-  )
-{
-  return RETURN_UNSUPPORTED;
-}
-
diff --git a/Chips/TexasInstruments/Omap35xx/Library/SerialPortLib/SerialPortLib.inf b/Chips/TexasInstruments/Omap35xx/Library/SerialPortLib/SerialPortLib.inf
deleted file mode 100644
index 3382ef7..0000000
--- a/Chips/TexasInstruments/Omap35xx/Library/SerialPortLib/SerialPortLib.inf
+++ /dev/null
@@ -1,44 +0,0 @@
-#/** @file
-# EDK Serial port lib
-#
-# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardSerialPortLib
-  FILE_GUID                      = 97546cbd-c0ff-4c48-ab0b-e4f58862acd3
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = SerialPortLib
-
-
-#
-#  VALID_ARCHITECTURES           = ARM IA32 X64 IPF EBC
-#
-
-[Sources.common]
-  SerialPortLib.c
-
-[LibraryClasses]
-  DebugLib
-  IoLib
-  OmapLib
-
-[Packages]
-  EmbeddedPkg/EmbeddedPkg.dec
-  MdePkg/MdePkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[FixedPcd]
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart
-
diff --git a/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.c b/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.c
deleted file mode 100644
index 9f0ebe0..0000000
--- a/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.c
+++ /dev/null
@@ -1,1494 +0,0 @@
-/** @file
-  MMC/SD Card driver for OMAP 35xx (SDIO not supported)
-
-  This driver always produces a BlockIo protocol but it starts off with no Media
-  present. A TimerCallBack detects when media is inserted or removed and after
-  a media change event a call to BlockIo ReadBlocks/WriteBlocks will cause the
-  media to be detected (or removed) and the BlockIo Media structure will get
-  updated. No MMC/SD Card harward registers are updated until the first BlockIo
-  ReadBlocks/WriteBlocks after media has been insterted (booting with a card
-  plugged in counts as an insertion event).
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "MMCHS.h"
-
-EFI_BLOCK_IO_MEDIA gMMCHSMedia = {
-  SIGNATURE_32('s','d','i','o'),            // MediaId
-  TRUE,                                     // RemovableMedia
-  FALSE,                                    // MediaPresent
-  FALSE,                                    // LogicalPartition
-  FALSE,                                    // ReadOnly
-  FALSE,                                    // WriteCaching
-  512,                                      // BlockSize
-  4,                                        // IoAlign
-  0,                                        // Pad
-  0                                         // LastBlock
-};
-
-typedef struct {
-  VENDOR_DEVICE_PATH  Mmc;
-  EFI_DEVICE_PATH     End;
-} MMCHS_DEVICE_PATH;
-
-MMCHS_DEVICE_PATH gMmcHsDevicePath = {
-  {
-    HARDWARE_DEVICE_PATH,
-    HW_VENDOR_DP,
-    (UINT8)(sizeof(VENDOR_DEVICE_PATH)),
-    (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8),
-    0xb615f1f5, 0x5088, 0x43cd, 0x80, 0x9c, 0xa1, 0x6e, 0x52, 0x48, 0x7d, 0x00
-  },
-  {
-    END_DEVICE_PATH_TYPE,
-    END_ENTIRE_DEVICE_PATH_SUBTYPE,
-    { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
-  }
-};
-
-CARD_INFO                  gCardInfo;
-EMBEDDED_EXTERNAL_DEVICE   *gTPS65950;
-EFI_EVENT                  gTimerEvent;
-BOOLEAN                    gMediaChange = FALSE;
-
-//
-// Internal Functions
-//
-
-
-VOID
-ParseCardCIDData (
-  UINT32 Response0,
-  UINT32 Response1,
-  UINT32 Response2,
-  UINT32 Response3
-  )
-{
-  gCardInfo.CIDData.MDT = ((Response0 >> 8) & 0xFFF);
-  gCardInfo.CIDData.PSN = (((Response0 >> 24) & 0xFF) | ((Response1 & 0xFFFFFF) << 8));
-  gCardInfo.CIDData.PRV = ((Response1 >> 24) & 0xFF);
-  gCardInfo.CIDData.PNM[4] = ((Response2) & 0xFF);
-  gCardInfo.CIDData.PNM[3] = ((Response2 >> 8) & 0xFF);
-  gCardInfo.CIDData.PNM[2] = ((Response2 >> 16) & 0xFF);
-  gCardInfo.CIDData.PNM[1] = ((Response2 >> 24) & 0xFF);
-  gCardInfo.CIDData.PNM[0] = ((Response3) & 0xFF);
-  gCardInfo.CIDData.OID = ((Response3 >> 8) & 0xFFFF);
-  gCardInfo.CIDData.MID = ((Response3 >> 24) & 0xFF);
-}
-
-
-VOID
-UpdateMMCHSClkFrequency (
-  UINTN NewCLKD
-  )
-{
-  //Set Clock enable to 0x0 to not provide the clock to the card
-  MmioAnd32 (MMCHS_SYSCTL, ~CEN);
-
-  //Set new clock frequency.
-  MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
-
-  //Poll till Internal Clock Stable
-  while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
-
-  //Set Clock enable to 0x1 to provide the clock to the card
-  MmioOr32 (MMCHS_SYSCTL, CEN);
-}
-
-
-EFI_STATUS
-SendCmd (
-  UINTN Cmd,
-  UINTN CmdInterruptEnableVal,
-  UINTN CmdArgument
-  )
-{
-  UINTN MmcStatus;
-  UINTN RetryCount = 0;
-
-  //Check if command line is in use or not. Poll till command line is available.
-  while ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
-
-  //Provide the block size.
-  MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);
-
-  //Setting Data timeout counter value to max value.
-  MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
-
-  //Clear Status register.
-  MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF);
-
-  //Set command argument register
-  MmioWrite32 (MMCHS_ARG, CmdArgument);
-
-  //Enable interrupt enable events to occur
-  MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal);
-
-  //Send a command
-  MmioWrite32 (MMCHS_CMD, Cmd);
-
-  //Check for the command status.
-  while (RetryCount < MAX_RETRY_COUNT) {
-    do {
-      MmcStatus = MmioRead32 (MMCHS_STAT);
-    } while (MmcStatus == 0);
-
-    //Read status of command response
-    if ((MmcStatus & ERRI) != 0) {
-
-      //Perform soft-reset for mmci_cmd line.
-      MmioOr32 (MMCHS_SYSCTL, SRC);
-      while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
-
-      DEBUG ((EFI_D_INFO, "MmcStatus: %x\n", MmcStatus));
-      return EFI_DEVICE_ERROR;
-    }
-
-    //Check if command is completed.
-    if ((MmcStatus & CC) == CC) {
-      MmioWrite32 (MMCHS_STAT, CC);
-      break;
-    }
-
-    RetryCount++;
-  }
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-
-VOID
-GetBlockInformation (
-  UINTN *BlockSize,
-  UINTN *NumBlocks
-  )
-{
-  CSD_SDV2 *CsdSDV2Data;
-  UINTN    CardSize;
-
-  if (gCardInfo.CardType == SD_CARD_2_HIGH) {
-    CsdSDV2Data = (CSD_SDV2 *)&gCardInfo.CSDData;
-
-    //Populate BlockSize.
-    *BlockSize = (0x1UL << CsdSDV2Data->READ_BL_LEN);
-
-    //Calculate Total number of blocks.
-    CardSize = CsdSDV2Data->C_SIZELow16 | (CsdSDV2Data->C_SIZEHigh6 << 2);
-    *NumBlocks = ((CardSize + 1) * 1024);
-  } else {
-    //Populate BlockSize.
-    *BlockSize = (0x1UL << gCardInfo.CSDData.READ_BL_LEN);
-
-    //Calculate Total number of blocks.
-    CardSize = gCardInfo.CSDData.C_SIZELow2 | (gCardInfo.CSDData.C_SIZEHigh10 << 2);
-    *NumBlocks = (CardSize + 1) * (1 << (gCardInfo.CSDData.C_SIZE_MULT + 2));
-  }
-
-  //For >=2G card, BlockSize may be 1K, but the transfer size is 512 bytes.
-  if (*BlockSize > 512) {
-    *NumBlocks = MultU64x32(*NumBlocks, *BlockSize/2);
-    *BlockSize = 512;
-  }
-
-  DEBUG ((EFI_D_INFO, "Card type: %x, BlockSize: %x, NumBlocks: %x\n", gCardInfo.CardType, *BlockSize, *NumBlocks));
-}
-
-
-VOID
-CalculateCardCLKD (
-  UINTN *ClockFrequencySelect
-  )
-{
-  UINT8    MaxDataTransferRate;
-  UINTN    TransferRateValue = 0;
-  UINTN    TimeValue = 0 ;
-  UINTN    Frequency = 0;
-
-  MaxDataTransferRate = gCardInfo.CSDData.TRAN_SPEED;
-
-  // For SD Cards  we would need to send CMD6 to set
-  // speeds abouve 25MHz. High Speed mode 50 MHz and up
-
-  //Calculate Transfer rate unit (Bits 2:0 of TRAN_SPEED)
-  switch (MaxDataTransferRate & 0x7) {
-    case 0:
-      TransferRateValue = 100 * 1000;
-      break;
-
-    case 1:
-      TransferRateValue = 1 * 1000 * 1000;
-      break;
-
-    case 2:
-      TransferRateValue = 10 * 1000 * 1000;
-      break;
-
-    case 3:
-      TransferRateValue = 100 * 1000 * 1000;
-      break;
-
-    default:
-      DEBUG((EFI_D_ERROR, "Invalid parameter.\n"));
-      ASSERT(FALSE);
-  }
-
-  //Calculate Time value (Bits 6:3 of TRAN_SPEED)
-  switch ((MaxDataTransferRate >> 3) & 0xF) {
-    case 1:
-      TimeValue = 10;
-      break;
-
-    case 2:
-      TimeValue = 12;
-      break;
-
-    case 3:
-      TimeValue = 13;
-      break;
-
-    case 4:
-      TimeValue = 15;
-      break;
-
-    case 5:
-      TimeValue = 20;
-      break;
-
-    case 6:
-      TimeValue = 25;
-      break;
-
-    case 7:
-      TimeValue = 30;
-      break;
-
-    case 8:
-      TimeValue = 35;
-      break;
-
-    case 9:
-      TimeValue = 40;
-      break;
-
-    case 10:
-      TimeValue = 45;
-      break;
-
-    case 11:
-      TimeValue = 50;
-      break;
-
-    case 12:
-      TimeValue = 55;
-      break;
-
-    case 13:
-      TimeValue = 60;
-      break;
-
-    case 14:
-      TimeValue = 70;
-      break;
-
-    case 15:
-      TimeValue = 80;
-      break;
-
-    default:
-      DEBUG((EFI_D_ERROR, "Invalid parameter.\n"));
-      ASSERT(FALSE);
-  }
-
-  Frequency = TransferRateValue * TimeValue/10;
-
-  //Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
-  *ClockFrequencySelect = ((MMC_REFERENCE_CLK/Frequency) + 1);
-
-  DEBUG ((EFI_D_INFO, "MaxDataTransferRate: 0x%x, Frequency: %d KHz, ClockFrequencySelect: %x\n", MaxDataTransferRate, Frequency/1000, *ClockFrequencySelect));
-}
-
-
-VOID
-GetCardConfigurationData (
-  VOID
-  )
-{
-  UINTN  BlockSize;
-  UINTN  NumBlocks;
-  UINTN  ClockFrequencySelect;
-
-  //Calculate BlockSize and Total number of blocks in the detected card.
-  GetBlockInformation(&BlockSize, &NumBlocks);
-  gCardInfo.BlockSize = BlockSize;
-  gCardInfo.NumBlocks = NumBlocks;
-
-  //Calculate Card clock divider value.
-  CalculateCardCLKD(&ClockFrequencySelect);
-  gCardInfo.ClockFrequencySelect = ClockFrequencySelect;
-}
-
-
-EFI_STATUS
-InitializeMMCHS (
-  VOID
-  )
-{
-  UINT8      Data = 0;
-  EFI_STATUS Status;
-
-  //Select Device group to belong to P1 device group in Power IC.
-  Data = DEV_GRP_P1;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VMMC1_DEV_GRP), 1, &Data);
-  ASSERT_EFI_ERROR(Status);
-
-  //Configure voltage regulator for MMC1 in Power IC to output 3.0 voltage.
-  Data = VSEL_3_00V;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VMMC1_DEDICATED_REG), 1, &Data);
-  ASSERT_EFI_ERROR(Status);
-
-  //After ramping up voltage, set VDDS stable bit to indicate that voltage level is stable.
-  MmioOr32 (CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));
-
-  // Enable WP GPIO
-  MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
-
-  // Enable Card Detect
-  Data = CARD_DETECT_ENABLE;
-  gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, TPS65950_GPIO_CTRL), 1, &Data);
-
-
-  return Status;
-}
-
-
-EFI_STATUS
-PerformCardIdenfication (
-  VOID
-  )
-{
-  EFI_STATUS Status;
-  UINTN      CmdArgument = 0;
-  UINTN      Response = 0;
-  UINTN      RetryCount = 0;
-  BOOLEAN    SDCmd8Supported = FALSE;
-
-  //Enable interrupts.
-  MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
-    CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN));
-
-  //Controller INIT procedure start.
-  MmioOr32 (MMCHS_CON, INIT);
-  MmioWrite32 (MMCHS_CMD, 0x00000000);
-  while (!(MmioRead32 (MMCHS_STAT) & CC));
-
-  //Wait for 1 ms
-  gBS->Stall(1000);
-
-  //Set CC bit to 0x1 to clear the flag
-  MmioOr32 (MMCHS_STAT, CC);
-
-  //Retry INIT procedure.
-  MmioWrite32 (MMCHS_CMD, 0x00000000);
-  while (!(MmioRead32 (MMCHS_STAT) & CC));
-
-  //End initialization sequence
-  MmioAnd32 (MMCHS_CON, ~INIT);
-
-  MmioOr32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON));
-
-  //Change clock frequency to 400KHz to fit protocol
-  UpdateMMCHSClkFrequency(CLKD_400KHZ);
-
-  MmioOr32 (MMCHS_CON, OD);
-
-  //Send CMD0 command.
-  Status = SendCmd (CMD0, CMD0_INT_EN, CmdArgument);
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "Cmd0 fails.\n"));
-    return Status;
-  }
-
-  DEBUG ((EFI_D_INFO, "CMD0 response: %x\n", MmioRead32 (MMCHS_RSP10)));
-
-  //Send CMD5 command.
-  Status = SendCmd (CMD5, CMD5_INT_EN, CmdArgument);
-  if (Status == EFI_SUCCESS) {
-    DEBUG ((EFI_D_ERROR, "CMD5 Success. SDIO card. Follow SDIO card specification.\n"));
-    DEBUG ((EFI_D_INFO, "CMD5 response: %x\n", MmioRead32 (MMCHS_RSP10)));
-    //NOTE: Returning unsupported error for now. Need to implement SDIO specification.
-    return EFI_UNSUPPORTED;
-  } else {
-    DEBUG ((EFI_D_INFO, "CMD5 fails. Not an SDIO card.\n"));
-  }
-
-  MmioOr32 (MMCHS_SYSCTL, SRC);
-  gBS->Stall(1000);
-  while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
-
-  //Send CMD8 command. (New v2.00 command for Voltage check)
-  //Only 2.7V - 3.6V is supported for SD2.0, only SD 2.0 card can pass.
-  //MMC & SD1.1 card will fail this command.
-  CmdArgument = CMD8_ARG;
-  Status = SendCmd (CMD8, CMD8_INT_EN, CmdArgument);
-  if (Status == EFI_SUCCESS) {
-    Response = MmioRead32 (MMCHS_RSP10);
-    DEBUG ((EFI_D_INFO, "CMD8 success. CMD8 response: %x\n", Response));
-    if (Response != CmdArgument) {
-      return EFI_DEVICE_ERROR;
-    }
-    DEBUG ((EFI_D_INFO, "Card is SD2.0\n"));
-    SDCmd8Supported = TRUE; //Supports high capacity.
-  } else {
-    DEBUG ((EFI_D_INFO, "CMD8 fails. Not an SD2.0 card.\n"));
-  }
-
-  MmioOr32 (MMCHS_SYSCTL, SRC);
-  gBS->Stall(1000);
-  while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
-
-  //Poll till card is busy
-  while (RetryCount < MAX_RETRY_COUNT) {
-    //Send CMD55 command.
-    CmdArgument = 0;
-    Status = SendCmd (CMD55, CMD55_INT_EN, CmdArgument);
-    if (Status == EFI_SUCCESS) {
-      DEBUG ((EFI_D_INFO, "CMD55 success. CMD55 response: %x\n", MmioRead32 (MMCHS_RSP10)));
-      gCardInfo.CardType = SD_CARD;
-    } else {
-      DEBUG ((EFI_D_INFO, "CMD55 fails.\n"));
-      gCardInfo.CardType = MMC_CARD;
-    }
-
-    //Send appropriate command for the card type which got detected.
-    if (gCardInfo.CardType == SD_CARD) {
-      CmdArgument = ((UINTN *) &(gCardInfo.OCRData))[0];
-
-      //Set HCS bit.
-      if (SDCmd8Supported) {
-        CmdArgument |= HCS;
-      }
-
-      Status = SendCmd (ACMD41, ACMD41_INT_EN, CmdArgument);
-      if (EFI_ERROR(Status)) {
-        DEBUG ((EFI_D_INFO, "ACMD41 fails.\n"));
-        return Status;
-      }
-      ((UINT32 *) &(gCardInfo.OCRData))[0] = MmioRead32 (MMCHS_RSP10);
-      DEBUG ((EFI_D_INFO, "SD card detected. ACMD41 OCR: %x\n", ((UINT32 *) &(gCardInfo.OCRData))[0]));
-    } else if (gCardInfo.CardType == MMC_CARD) {
-      CmdArgument = 0;
-      Status = SendCmd (CMD1, CMD1_INT_EN, CmdArgument);
-      if (EFI_ERROR(Status)) {
-        DEBUG ((EFI_D_INFO, "CMD1 fails.\n"));
-        return Status;
-      }
-      Response = MmioRead32 (MMCHS_RSP10);
-      DEBUG ((EFI_D_INFO, "MMC card detected.. CMD1 response: %x\n", Response));
-
-      //NOTE: For now, I am skipping this since I only have an SD card.
-      //Compare card OCR and host OCR (Section 22.6.1.3.2.4)
-      return EFI_UNSUPPORTED; //For now, MMC is not supported.
-    }
-
-    //Poll the card until it is out of its power-up sequence.
-    if (gCardInfo.OCRData.Busy == 1) {
-
-      if (SDCmd8Supported) {
-        gCardInfo.CardType = SD_CARD_2;
-      }
-
-      //Card is ready. Check CCS (Card capacity status) bit (bit#30).
-      //SD 2.0 standard card will response with CCS 0, SD high capacity card will respond with CCS 1.
-      if (gCardInfo.OCRData.AccessMode & BIT1) {
-        gCardInfo.CardType = SD_CARD_2_HIGH;
-        DEBUG ((EFI_D_INFO, "High capacity card.\n"));
-      } else {
-        DEBUG ((EFI_D_INFO, "Standard capacity card.\n"));
-      }
-
-      break;
-    }
-
-    gBS->Stall(1000);
-    RetryCount++;
-  }
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    DEBUG ((EFI_D_ERROR, "Timeout error. RetryCount: %d\n", RetryCount));
-    return EFI_TIMEOUT;
-  }
-
-  //Read CID data.
-  CmdArgument = 0;
-  Status = SendCmd (CMD2, CMD2_INT_EN, CmdArgument);
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "CMD2 fails. Status: %x\n", Status));
-    return Status;
-  }
-
-  DEBUG ((EFI_D_INFO, "CMD2 response: %x %x %x %x\n", MmioRead32 (MMCHS_RSP10), MmioRead32 (MMCHS_RSP32), MmioRead32 (MMCHS_RSP54), MmioRead32 (MMCHS_RSP76)));
-
-  //Parse CID register data.
-  ParseCardCIDData(MmioRead32 (MMCHS_RSP10), MmioRead32 (MMCHS_RSP32), MmioRead32 (MMCHS_RSP54), MmioRead32 (MMCHS_RSP76));
-
-  //Read RCA
-  CmdArgument = 0;
-  Status = SendCmd (CMD3, CMD3_INT_EN, CmdArgument);
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "CMD3 fails. Status: %x\n", Status));
-    return Status;
-  }
-
-  //Set RCA for the detected card. RCA is CMD3 response.
-  gCardInfo.RCA = (MmioRead32 (MMCHS_RSP10) >> 16);
-  DEBUG ((EFI_D_INFO, "CMD3 response: RCA %x\n", gCardInfo.RCA));
-
-  //MMC Bus setting change after card identification.
-  MmioAnd32 (MMCHS_CON, ~OD);
-  MmioOr32 (MMCHS_HCTL, SDVS_3_0_V);
-  UpdateMMCHSClkFrequency(CLKD_400KHZ); //Set the clock frequency to 400KHz.
-
-  return EFI_SUCCESS;
-}
-
-
-EFI_STATUS
-GetCardSpecificData (
-  VOID
-  )
-{
-  EFI_STATUS Status;
-  UINTN      CmdArgument;
-
-  //Send CMD9 to retrieve CSD.
-  CmdArgument = gCardInfo.RCA << 16;
-  Status = SendCmd (CMD9, CMD9_INT_EN, CmdArgument);
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "CMD9 fails. Status: %x\n", Status));
-    return Status;
-  }
-
-  //Populate 128-bit CSD register data.
-  ((UINT32 *)&(gCardInfo.CSDData))[0] = MmioRead32 (MMCHS_RSP10);
-  ((UINT32 *)&(gCardInfo.CSDData))[1] = MmioRead32 (MMCHS_RSP32);
-  ((UINT32 *)&(gCardInfo.CSDData))[2] = MmioRead32 (MMCHS_RSP54);
-  ((UINT32 *)&(gCardInfo.CSDData))[3] = MmioRead32 (MMCHS_RSP76);
-
-  DEBUG ((EFI_D_INFO, "CMD9 response: %x %x %x %x\n", MmioRead32 (MMCHS_RSP10), MmioRead32 (MMCHS_RSP32), MmioRead32 (MMCHS_RSP54), MmioRead32 (MMCHS_RSP76)));
-
-  //Calculate total number of blocks and max. data transfer rate supported by the detected card.
-  GetCardConfigurationData();
-
-  return Status;
-}
-
-
-EFI_STATUS
-PerformCardConfiguration (
-  VOID
-  )
-{
-  UINTN      CmdArgument = 0;
-  EFI_STATUS Status;
-
-  //Send CMD7
-  CmdArgument = gCardInfo.RCA << 16;
-  Status = SendCmd (CMD7, CMD7_INT_EN, CmdArgument);
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "CMD7 fails. Status: %x\n", Status));
-    return Status;
-  }
-
-  if ((gCardInfo.CardType != UNKNOWN_CARD) && (gCardInfo.CardType != MMC_CARD)) {
-    // We could read SCR register, but SD Card Phys spec stats any SD Card shall
-    // set SCR.SD_BUS_WIDTHS to support 4-bit mode, so why bother?
-
-    // Send ACMD6 (application specific commands must be prefixed with CMD55)
-    Status = SendCmd (CMD55, CMD55_INT_EN, CmdArgument);
-    if (!EFI_ERROR (Status)) {
-      // set device into 4-bit data bus mode
-      Status = SendCmd (ACMD6, ACMD6_INT_EN, 0x2);
-      if (!EFI_ERROR (Status)) {
-        // Set host controler into 4-bit mode
-        MmioOr32 (MMCHS_HCTL, DTW_4_BIT);
-        DEBUG ((EFI_D_INFO, "SD Memory Card set to 4-bit mode\n"));
-      }
-    }
-  }
-
-  //Send CMD16 to set the block length
-  CmdArgument = gCardInfo.BlockSize;
-  Status = SendCmd (CMD16, CMD16_INT_EN, CmdArgument);
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "CMD16 fails. Status: %x\n", Status));
-    return Status;
-  }
-
-  //Change MMCHS clock frequency to what detected card can support.
-  UpdateMMCHSClkFrequency(gCardInfo.ClockFrequencySelect);
-
-  return EFI_SUCCESS;
-}
-
-
-EFI_STATUS
-ReadBlockData (
-  IN  EFI_BLOCK_IO_PROTOCOL       *This,
-  OUT VOID                        *Buffer
-  )
-{
-  UINTN MmcStatus;
-  UINTN *DataBuffer = Buffer;
-  UINTN DataSize = This->Media->BlockSize/4;
-  UINTN Count;
-  UINTN RetryCount = 0;
-
-  //Check controller status to make sure there is no error.
-  while (RetryCount < MAX_RETRY_COUNT) {
-    do {
-      //Read Status.
-      MmcStatus = MmioRead32 (MMCHS_STAT);
-    } while(MmcStatus == 0);
-
-    //Check if Buffer read ready (BRR) bit is set?
-    if (MmcStatus & BRR) {
-
-      //Clear BRR bit
-      MmioOr32 (MMCHS_STAT, BRR);
-
-      //Read block worth of data.
-      for (Count = 0; Count < DataSize; Count++) {
-        *DataBuffer++ = MmioRead32 (MMCHS_DATA);
-      }
-      break;
-    }
-    RetryCount++;
-  }
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-
-EFI_STATUS
-WriteBlockData (
-  IN  EFI_BLOCK_IO_PROTOCOL       *This,
-  OUT VOID                        *Buffer
-  )
-{
-  UINTN MmcStatus;
-  UINTN *DataBuffer = Buffer;
-  UINTN DataSize = This->Media->BlockSize/4;
-  UINTN Count;
-  UINTN RetryCount = 0;
-
-  //Check controller status to make sure there is no error.
-  while (RetryCount < MAX_RETRY_COUNT) {
-    do {
-      //Read Status.
-      MmcStatus = MmioRead32 (MMCHS_STAT);
-    } while(MmcStatus == 0);
-
-    //Check if Buffer write ready (BWR) bit is set?
-    if (MmcStatus & BWR) {
-
-      //Clear BWR bit
-      MmioOr32 (MMCHS_STAT, BWR);
-
-      //Write block worth of data.
-      for (Count = 0; Count < DataSize; Count++) {
-        MmioWrite32 (MMCHS_DATA, *DataBuffer++);
-      }
-
-      break;
-    }
-    RetryCount++;
-  }
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DmaBlocks (
-  IN EFI_BLOCK_IO_PROTOCOL        *This,
-  IN  UINTN                       Lba,
-  IN OUT VOID                     *Buffer,
-  IN  UINTN                       BlockCount,
-  IN  OPERATION_TYPE              OperationType
-  )
-{
-  EFI_STATUS            Status;
-  UINTN                 DmaSize = 0;
-  UINTN                 Cmd = 0;
-  UINTN                 CmdInterruptEnable;
-  UINTN                 CmdArgument;
-  VOID                  *BufferMap;
-  EFI_PHYSICAL_ADDRESS  BufferAddress;
-  OMAP_DMA4             Dma4;
-  DMA_MAP_OPERATION     DmaOperation;
-  EFI_STATUS            MmcStatus;
-  UINTN                 RetryCount = 0;
-
-CpuDeadLoop ();
-  // Map passed in buffer for DMA xfer
-  DmaSize = BlockCount * This->Media->BlockSize;
-  Status = DmaMap (DmaOperation, Buffer, &DmaSize, &BufferAddress, &BufferMap);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  ZeroMem (&DmaOperation, sizeof (DMA_MAP_OPERATION));
-
-
-  Dma4.DataType = 2;                      // DMA4_CSDPi[1:0]   32-bit elements from MMCHS_DATA
-
-  Dma4.SourceEndiansim = 0;               // DMA4_CSDPi[21]
-
-  Dma4.DestinationEndianism = 0;          // DMA4_CSDPi[19]
-
-  Dma4.SourcePacked = 0;                  // DMA4_CSDPi[6]
-
-  Dma4.DestinationPacked = 0;             // DMA4_CSDPi[13]
-
-  Dma4.NumberOfElementPerFrame = This->Media->BlockSize/4; // DMA4_CENi  (TRM 4K is optimum value)
-
-  Dma4.NumberOfFramePerTransferBlock = BlockCount;         // DMA4_CFNi
-
-  Dma4.ReadPriority = 0;                  // DMA4_CCRi[6]      Low priority read
-
-  Dma4.WritePriority = 0;                 // DMA4_CCRi[23]     Prefetech disabled
-
-
-  //Populate the command information based on the operation type.
-  if (OperationType == READ) {
-    Cmd = CMD18; //Multiple block read
-    CmdInterruptEnable = CMD18_INT_EN;
-    DmaOperation = MapOperationBusMasterCommonBuffer;
-
-    Dma4.ReadPortAccessType =0 ;            // DMA4_CSDPi[8:7]   Can not burst MMCHS_DATA reg
-
-    Dma4.WritePortAccessType = 3;           // DMA4_CSDPi[15:14] Memory burst 16x32
-
-    Dma4.WriteMode = 1;                     // DMA4_CSDPi[17:16] Write posted
-
-
-
-    Dma4.SourceStartAddress = MMCHS_DATA;                   // DMA4_CSSAi
-
-    Dma4.DestinationStartAddress = (UINT32)BufferAddress;   // DMA4_CDSAi
-
-    Dma4.SourceElementIndex = 1;                            // DMA4_CSEi
-
-    Dma4.SourceFrameIndex = 0x200;                          // DMA4_CSFi
-
-    Dma4.DestinationElementIndex = 1;                       // DMA4_CDEi
-
-    Dma4.DestinationFrameIndex = 0;                         // DMA4_CDFi
-
-
-
-    Dma4.ReadPortAccessMode = 0;            // DMA4_CCRi[13:12]  Always read MMCHS_DATA
-
-    Dma4.WritePortAccessMode = 1;           // DMA4_CCRi[15:14]  Post increment memory address
-
-    Dma4.ReadRequestNumber = 0x1e;          // DMA4_CCRi[4:0]    Syncro with MMCA_DMA_RX (61)
-
-    Dma4.WriteRequestNumber = 1;            // DMA4_CCRi[20:19]  Syncro upper 0x3e == 62 (one based)
-
-  } else if (OperationType == WRITE) {
-    Cmd = CMD25; //Multiple block write
-    CmdInterruptEnable = CMD25_INT_EN;
-    DmaOperation = MapOperationBusMasterRead;
-
-    Dma4.ReadPortAccessType = 3;            // DMA4_CSDPi[8:7]   Memory burst 16x32
-
-    Dma4.WritePortAccessType = 0;           // DMA4_CSDPi[15:14] Can not burst MMCHS_DATA reg
-
-    Dma4.WriteMode = 1;                     // DMA4_CSDPi[17:16] Write posted ???
-
-
-
-    Dma4.SourceStartAddress = (UINT32)BufferAddress;        // DMA4_CSSAi
-
-    Dma4.DestinationStartAddress = MMCHS_DATA;              // DMA4_CDSAi
-
-    Dma4.SourceElementIndex = 1;                            // DMA4_CSEi
-
-    Dma4.SourceFrameIndex = 0x200;                          // DMA4_CSFi
-
-    Dma4.DestinationElementIndex = 1;                       // DMA4_CDEi
-
-    Dma4.DestinationFrameIndex = 0;                         // DMA4_CDFi
-
-
-
-    Dma4.ReadPortAccessMode = 1;            // DMA4_CCRi[13:12]  Post increment memory address
-
-    Dma4.WritePortAccessMode = 0;           // DMA4_CCRi[15:14]  Always write MMCHS_DATA
-
-    Dma4.ReadRequestNumber = 0x1d;          // DMA4_CCRi[4:0]    Syncro with MMCA_DMA_TX (60)
-
-    Dma4.WriteRequestNumber = 1;            // DMA4_CCRi[20:19]  Syncro upper 0x3d == 61 (one based)
-
-  } else {
-    return EFI_INVALID_PARAMETER;
-  }
-
-
-  EnableDmaChannel (2, &Dma4);
-
-
-  //Set command argument based on the card access mode (Byte mode or Block mode)
-  if (gCardInfo.OCRData.AccessMode & BIT1) {
-    CmdArgument = Lba;
-  } else {
-    CmdArgument = Lba * This->Media->BlockSize;
-  }
-
-  //Send Command.
-  Status = SendCmd (Cmd, CmdInterruptEnable, CmdArgument);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "CMD fails. Status: %x\n", Status));
-    return Status;
-  }
-
-    //Check for the Transfer completion.
-  while (RetryCount < MAX_RETRY_COUNT) {
-    //Read Status
-    do {
-      MmcStatus = MmioRead32 (MMCHS_STAT);
-    } while (MmcStatus == 0);
-
-    //Check if Transfer complete (TC) bit is set?
-    if (MmcStatus & TC) {
-      break;
-    } else {
-      DEBUG ((EFI_D_ERROR, "MmcStatus for TC: %x\n", MmcStatus));
-      //Check if DEB, DCRC or DTO interrupt occured.
-      if ((MmcStatus & DEB) | (MmcStatus & DCRC) | (MmcStatus & DTO)) {
-        //There was an error during the data transfer.
-
-        //Set SRD bit to 1 and wait until it return to 0x0.
-        MmioOr32 (MMCHS_SYSCTL, SRD);
-        while((MmioRead32 (MMCHS_SYSCTL) & SRD) != 0x0);
-
-        DisableDmaChannel (2, DMA4_CSR_BLOCK, DMA4_CSR_ERR);
-        DmaUnmap (BufferMap);
-        return EFI_DEVICE_ERROR;
-      }
-    }
-    RetryCount++;
-  }
-
-  DisableDmaChannel (2, DMA4_CSR_BLOCK, DMA4_CSR_ERR);
-  Status = DmaUnmap (BufferMap);
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    DEBUG ((EFI_D_ERROR, "TransferBlockData timed out.\n"));
-    return EFI_TIMEOUT;
-  }
-
-  return Status;
-}
-
-
-EFI_STATUS
-TransferBlock (
-  IN EFI_BLOCK_IO_PROTOCOL        *This,
-  IN  UINTN                       Lba,
-  IN OUT VOID                     *Buffer,
-  IN  OPERATION_TYPE              OperationType
-  )
-{
-  EFI_STATUS Status;
-  UINTN      MmcStatus;
-  UINTN      RetryCount = 0;
-  UINTN      Cmd = 0;
-  UINTN      CmdInterruptEnable = 0;
-  UINTN      CmdArgument = 0;
-
-
-  //Populate the command information based on the operation type.
-  if (OperationType == READ) {
-    Cmd = CMD17; //Single block read
-    CmdInterruptEnable = CMD18_INT_EN;
-  } else if (OperationType == WRITE) {
-    Cmd = CMD24; //Single block write
-    CmdInterruptEnable = CMD24_INT_EN;
-  }
-
-  //Set command argument based on the card access mode (Byte mode or Block mode)
-  if (gCardInfo.OCRData.AccessMode & BIT1) {
-    CmdArgument = Lba;
-  } else {
-    CmdArgument = Lba * This->Media->BlockSize;
-  }
-
-  //Send Command.
-  Status = SendCmd (Cmd, CmdInterruptEnable, CmdArgument);
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "CMD fails. Status: %x\n", Status));
-    return Status;
-  }
-
-  //Read or Write data.
-  if (OperationType == READ) {
-    Status = ReadBlockData (This, Buffer);
-    if (EFI_ERROR(Status)) {
-      DEBUG((EFI_D_ERROR, "ReadBlockData fails.\n"));
-      return Status;
-    }
-  } else if (OperationType == WRITE) {
-    Status = WriteBlockData (This, Buffer);
-    if (EFI_ERROR(Status)) {
-      DEBUG((EFI_D_ERROR, "WriteBlockData fails.\n"));
-      return Status;
-    }
-  }
-
-  //Check for the Transfer completion.
-  while (RetryCount < MAX_RETRY_COUNT) {
-    //Read Status
-    do {
-      MmcStatus = MmioRead32 (MMCHS_STAT);
-    } while (MmcStatus == 0);
-
-    //Check if Transfer complete (TC) bit is set?
-    if (MmcStatus & TC) {
-      break;
-    } else {
-      DEBUG ((EFI_D_ERROR, "MmcStatus for TC: %x\n", MmcStatus));
-      //Check if DEB, DCRC or DTO interrupt occured.
-      if ((MmcStatus & DEB) | (MmcStatus & DCRC) | (MmcStatus & DTO)) {
-        //There was an error during the data transfer.
-
-        //Set SRD bit to 1 and wait until it return to 0x0.
-        MmioOr32 (MMCHS_SYSCTL, SRD);
-        while((MmioRead32 (MMCHS_SYSCTL) & SRD) != 0x0);
-
-        return EFI_DEVICE_ERROR;
-      }
-    }
-    RetryCount++;
-  }
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    DEBUG ((EFI_D_ERROR, "TransferBlockData timed out.\n"));
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-BOOLEAN
-CardPresent (
-  VOID
-  )
-{
-  EFI_STATUS  Status;
-  UINT8       Data;
-
-  //
-  // Card detect is a GPIO0 on the TPS65950
-  //
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATAIN1), 1, &Data);
-  if (EFI_ERROR (Status)) {
-    return FALSE;
-  }
-
-  if ((Data & CARD_DETECT_BIT) == CARD_DETECT_BIT) {
-    // No Card present
-    return FALSE;
-  } else {
-    return TRUE;
-  }
-}
-
-EFI_STATUS
-DetectCard (
-  VOID
-  )
-{
-  EFI_STATUS    Status;
-
-  if (!CardPresent ()) {
-    return EFI_NO_MEDIA;
-  }
-
-  //Initialize MMC host controller clocks.
-  Status = InitializeMMCHS ();
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "Initialize MMC host controller fails. Status: %x\n", Status));
-    return Status;
-  }
-
-  //Software reset of the MMCHS host controller.
-  MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET);
-  gBS->Stall(1000);
-  while ((MmioRead32 (MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
-
-  //Soft reset for all.
-  MmioWrite32 (MMCHS_SYSCTL, SRA);
-  gBS->Stall(1000);
-  while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
-
-  //Voltage capabilities initialization. Activate VS18 and VS30.
-  MmioOr32 (MMCHS_CAPA, (VS30 | VS18));
-
-  //Wakeup configuration
-  MmioOr32 (MMCHS_SYSCONFIG, ENAWAKEUP);
-  MmioOr32 (MMCHS_HCTL, IWE);
-
-  //MMCHS Controller default initialization
-  MmioOr32 (MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));
-
-  MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
-
-  //Enable internal clock
-  MmioOr32 (MMCHS_SYSCTL, ICE);
-
-  //Set the clock frequency to 80KHz.
-  UpdateMMCHSClkFrequency (CLKD_80KHZ);
-
-  //Enable SD bus power.
-  MmioOr32 (MMCHS_HCTL, (SDBP_ON));
-
-  //Poll till SD bus power bit is set.
-  while ((MmioRead32 (MMCHS_HCTL) & SDBP_MASK) != SDBP_ON);
-
-  //Card idenfication
-  Status = PerformCardIdenfication ();
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "No MMC/SD card detected.\n"));
-    return Status;
-  }
-
-  //Get CSD (Card specific data) for the detected card.
-  Status = GetCardSpecificData();
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  //Configure the card in data transfer mode.
-  Status = PerformCardConfiguration();
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  //Patch the Media structure.
-  gMMCHSMedia.LastBlock    = (gCardInfo.NumBlocks - 1);
-  gMMCHSMedia.BlockSize    = gCardInfo.BlockSize;
-  gMMCHSMedia.ReadOnly     = (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23;
-  gMMCHSMedia.MediaPresent = TRUE;
-  gMMCHSMedia.MediaId++;
-
-  DEBUG ((EFI_D_INFO, "SD Card Media Change on Handle 0x%08x\n", gImageHandle));
-
-  return Status;
-}
-
-#define MAX_MMCHS_TRANSFER_SIZE  0x4000
-
-EFI_STATUS
-SdReadWrite (
-  IN EFI_BLOCK_IO_PROTOCOL    *This,
-  IN  UINTN                   Lba,
-  OUT VOID                    *Buffer,
-  IN  UINTN                   BufferSize,
-  IN  OPERATION_TYPE          OperationType
-  )
-{
-  EFI_STATUS Status = EFI_SUCCESS;
-  UINTN      RetryCount = 0;
-  UINTN      BlockCount;
-  UINTN      BytesToBeTranferedThisPass = 0;
-  UINTN      BytesRemainingToBeTransfered;
-  EFI_TPL    OldTpl;
-
-  BOOLEAN    Update;
-
-
-
-  Update               = FALSE;
-
-  if (gMediaChange) {
-    Update = TRUE;
-    Status = DetectCard  ();
-    if (EFI_ERROR (Status)) {
-      // We detected a removal
-      gMMCHSMedia.MediaPresent = FALSE;
-      gMMCHSMedia.LastBlock    = 0;
-      gMMCHSMedia.BlockSize    = 512;  // Should be zero but there is a bug in DiskIo
-      gMMCHSMedia.ReadOnly     = FALSE;
-    }
-    gMediaChange             = FALSE;
-  } else if (!gMMCHSMedia.MediaPresent) {
-    Status = EFI_NO_MEDIA;
-    goto Done;
-  }
-
-  if (Update) {
-    DEBUG ((EFI_D_INFO, "SD Card ReinstallProtocolInterface ()\n"));
-    gBS->ReinstallProtocolInterface (
-          gImageHandle,
-          &gEfiBlockIoProtocolGuid,
-          &gBlockIo,
-          &gBlockIo
-          );
-    return EFI_MEDIA_CHANGED;
-  }
-
-  if (EFI_ERROR (Status)) {
-    goto Done;
-  }
-
-  if (Buffer == NULL) {
-    Status = EFI_INVALID_PARAMETER;
-    goto Done;
-  }
-
-  if (Lba > This->Media->LastBlock) {
-    Status = EFI_INVALID_PARAMETER;
-    goto Done;
-  }
-
-  if ((BufferSize % This->Media->BlockSize) != 0) {
-    Status = EFI_BAD_BUFFER_SIZE;
-    goto Done;
-  }
-
-  //Check if the data lines are not in use.
-  while ((RetryCount++ < MAX_RETRY_COUNT) && ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) != DATI_ALLOWED));
-  if (RetryCount == MAX_RETRY_COUNT) {
-    Status = EFI_TIMEOUT;
-    goto Done;
-  }
-
-  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
-
-  BytesRemainingToBeTransfered = BufferSize;
-  while (BytesRemainingToBeTransfered > 0) {
-
-    if (gMediaChange) {
-      Status = EFI_NO_MEDIA;
-      DEBUG ((EFI_D_INFO, "SdReadWrite() EFI_NO_MEDIA due to gMediaChange\n"));
-      goto DoneRestoreTPL;
-    }
-
-    // Turn OFF DMA path until it is debugged
-    // BytesToBeTranferedThisPass = (BytesToBeTranferedThisPass >= MAX_MMCHS_TRANSFER_SIZE) ? MAX_MMCHS_TRANSFER_SIZE : BytesRemainingToBeTransfered;
-    BytesToBeTranferedThisPass   = This->Media->BlockSize;
-
-    BlockCount = BytesToBeTranferedThisPass/This->Media->BlockSize;
-
-    if (BlockCount > 1) {
-      Status = DmaBlocks (This, Lba, Buffer, BlockCount, OperationType);
-    } else {
-      //Transfer a block worth of data.
-      Status = TransferBlock (This, Lba, Buffer, OperationType);
-    }
-
-    if (EFI_ERROR(Status)) {
-      DEBUG ((EFI_D_ERROR, "TransferBlockData fails. %x\n", Status));
-      goto DoneRestoreTPL;
-    }
-
-    BytesRemainingToBeTransfered -= BytesToBeTranferedThisPass;
-    Lba    += BlockCount;
-    Buffer = (UINT8 *)Buffer + This->Media->BlockSize;
-  }
-
-DoneRestoreTPL:
-
-  gBS->RestoreTPL (OldTpl);
-
-Done:
-
-  return Status;
-
-}
-
-
-/**
-
-  Reset the Block Device.
-
-
-
-  @param  This                 Indicates a pointer to the calling context.
-
-  @param  ExtendedVerification Driver may perform diagnostics on reset.
-
-
-
-  @retval EFI_SUCCESS          The device was reset.
-
-  @retval EFI_DEVICE_ERROR     The device is not functioning properly and could
-
-                               not be reset.
-
-
-
-**/
-EFI_STATUS
-EFIAPI
-MMCHSReset (
-  IN EFI_BLOCK_IO_PROTOCOL          *This,
-  IN BOOLEAN                        ExtendedVerification
-  )
-{
-  return EFI_SUCCESS;
-}
-
-
-/**
-
-  Read BufferSize bytes from Lba into Buffer.
-
-
-
-  @param  This       Indicates a pointer to the calling context.
-
-  @param  MediaId    Id of the media, changes every time the media is replaced.
-
-  @param  Lba        The starting Logical Block Address to read from
-
-  @param  BufferSize Size of Buffer, must be a multiple of device block size.
-
-  @param  Buffer     A pointer to the destination buffer for the data. The caller is
-
-                     responsible for either having implicit or explicit ownership of the buffer.
-
-
-
-  @retval EFI_SUCCESS           The data was read correctly from the device.
-
-  @retval EFI_DEVICE_ERROR      The device reported an error while performing the read.
-
-  @retval EFI_NO_MEDIA          There is no media in the device.
-
-  @retval EFI_MEDIA_CHANGED     The MediaId does not matched the current device.
-
-  @retval EFI_BAD_BUFFER_SIZE   The Buffer was not a multiple of the block size of the device.
-
-  @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
-
-                                or the buffer is not on proper alignment.
-
-EFI_STATUS
-
-**/
-EFI_STATUS
-EFIAPI
-MMCHSReadBlocks (
-  IN EFI_BLOCK_IO_PROTOCOL          *This,
-  IN UINT32                         MediaId,
-  IN EFI_LBA                        Lba,
-  IN UINTN                          BufferSize,
-  OUT VOID                          *Buffer
-  )
-{
-  EFI_STATUS Status;
-
-  //Perform Read operation.
-  Status = SdReadWrite (This, (UINTN)Lba, Buffer, BufferSize, READ);
-
-  return Status;
-
-}
-
-
-/**
-
-  Write BufferSize bytes from Lba into Buffer.
-
-
-
-  @param  This       Indicates a pointer to the calling context.
-
-  @param  MediaId    The media ID that the write request is for.
-
-  @param  Lba        The starting logical block address to be written. The caller is
-
-                     responsible for writing to only legitimate locations.
-
-  @param  BufferSize Size of Buffer, must be a multiple of device block size.
-
-  @param  Buffer     A pointer to the source buffer for the data.
-
-
-
-  @retval EFI_SUCCESS           The data was written correctly to the device.
-
-  @retval EFI_WRITE_PROTECTED   The device can not be written to.
-
-  @retval EFI_DEVICE_ERROR      The device reported an error while performing the write.
-
-  @retval EFI_NO_MEDIA          There is no media in the device.
-
-  @retval EFI_MEDIA_CHNAGED     The MediaId does not matched the current device.
-
-  @retval EFI_BAD_BUFFER_SIZE   The Buffer was not a multiple of the block size of the device.
-
-  @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
-
-                                or the buffer is not on proper alignment.
-
-
-
-**/
-EFI_STATUS
-EFIAPI
-MMCHSWriteBlocks (
-  IN EFI_BLOCK_IO_PROTOCOL          *This,
-  IN UINT32                         MediaId,
-  IN EFI_LBA                        Lba,
-  IN UINTN                          BufferSize,
-  IN VOID                           *Buffer
-  )
-{
-  EFI_STATUS  Status;
-
-  //Perform write operation.
-  Status = SdReadWrite (This, (UINTN)Lba, Buffer, BufferSize, WRITE);
-
-
-  return Status;
-
-}
-
-
-/**
-
-  Flush the Block Device.
-
-
-
-  @param  This              Indicates a pointer to the calling context.
-
-
-
-  @retval EFI_SUCCESS       All outstanding data was written to the device
-
-  @retval EFI_DEVICE_ERROR  The device reported an error while writting back the data
-
-  @retval EFI_NO_MEDIA      There is no media in the device.
-
-
-
-**/
-EFI_STATUS
-EFIAPI
-MMCHSFlushBlocks (
-  IN EFI_BLOCK_IO_PROTOCOL  *This
-  )
-{
-  return EFI_SUCCESS;
-}
-
-
-EFI_BLOCK_IO_PROTOCOL gBlockIo = {
-  EFI_BLOCK_IO_INTERFACE_REVISION,   // Revision
-  &gMMCHSMedia,                      // *Media
-  MMCHSReset,                        // Reset
-  MMCHSReadBlocks,                   // ReadBlocks
-  MMCHSWriteBlocks,                  // WriteBlocks
-  MMCHSFlushBlocks                   // FlushBlocks
-};
-
-
-/**
-
-  Timer callback to convert card present hardware into a boolean that indicates
-
-  a media change event has happened. If you just check the GPIO you could see
-
-  card 1 and then check again after card 1 was removed and card 2 was inserted
-
-  and you would still see media present. Thus you need the timer tick to catch
-
-  the toggle event.
-
-
-
-  @param  Event                 Event whose notification function is being invoked.
-
-  @param  Context               The pointer to the notification function's context,
-
-                                which is implementation-dependent. Not used.
-
-
-
-**/
-VOID
-EFIAPI
-TimerCallback (
-  IN  EFI_EVENT   Event,
-  IN  VOID        *Context
-  )
-{
-  BOOLEAN Present;
-
-  Present = CardPresent ();
-  if (gMMCHSMedia.MediaPresent) {
-    if (!Present && !gMediaChange) {
-      gMediaChange = TRUE;
-    }
-  } else {
-    if (Present && !gMediaChange) {
-      gMediaChange = TRUE;
-    }
-  }
-}
-
-
-EFI_STATUS
-EFIAPI
-MMCHSInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS  Status;
-
-  Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
-  ASSERT_EFI_ERROR(Status);
-
-  ZeroMem (&gCardInfo, sizeof (CARD_INFO));
-
-  Status = gBS->CreateEvent (EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK, TimerCallback, NULL, &gTimerEvent);
-  ASSERT_EFI_ERROR (Status);
-
-  Status = gBS->SetTimer (gTimerEvent, TimerPeriodic, FixedPcdGet32 (PcdMmchsTimerFreq100NanoSeconds));
-  ASSERT_EFI_ERROR (Status);
-
-  //Publish BlockIO.
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &ImageHandle,
-                  &gEfiBlockIoProtocolGuid,    &gBlockIo,
-                  &gEfiDevicePathProtocolGuid, &gMmcHsDevicePath,
-                  NULL
-                  );
-  return Status;
-}
diff --git a/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.h b/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.h
deleted file mode 100644
index 06960a3..0000000
--- a/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _MMCHS_H_
-#define _MMCHS_H_
-
-#include <Uefi.h>
-
-#include <Library/BaseLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/OmapLib.h>
-#include <Library/OmapDmaLib.h>
-#include <Library/DmaLib.h>
-
-#include <Protocol/EmbeddedExternalDevice.h>
-#include <Protocol/BlockIo.h>
-#include <Protocol/DevicePath.h>
-
-#include <Omap3530/Omap3530.h>
-#include <TPS65950.h>
-
-#define MAX_RETRY_COUNT  (100*5)
-
-#define HCS               BIT30 //Host capacity support/1 = Supporting high capacity
-#define CCS               BIT30 //Card capacity status/1 = High capacity card
-typedef struct {
-  UINT32  Reserved0:   7; // 0
-  UINT32  V170_V195:   1; // 1.70V - 1.95V
-  UINT32  V200_V260:   7; // 2.00V - 2.60V
-  UINT32  V270_V360:   9; // 2.70V - 3.60V
-  UINT32  RESERVED_1:  5; // Reserved
-  UINT32  AccessMode:  2; // 00b (byte mode), 10b (sector mode)
-  UINT32  Busy:        1; // This bit is set to LOW if the card has not finished the power up routine
-}OCR;
-
-typedef struct {
-  UINT32  NOT_USED;   // 1 [0:0]
-  UINT32  CRC;        // CRC7 checksum [7:1]
-  UINT32  MDT;        // Manufacturing date [19:8]
-  UINT32  RESERVED_1; // Reserved [23:20]
-  UINT32  PSN;        // Product serial number [55:24]
-  UINT8   PRV;        // Product revision [63:56]
-  UINT8   PNM[5];     // Product name [64:103]
-  UINT16  OID;        // OEM/Application ID [119:104]
-  UINT8   MID;        // Manufacturer ID [127:120]
-}CID;
-
-typedef struct {
-  UINT8   NOT_USED:           1; // Not used, always 1 [0:0]
-  UINT8   CRC:                7; // CRC [7:1]
-
-  UINT8   RESERVED_1:         2; // Reserved [9:8]
-  UINT8   FILE_FORMAT:        2; // File format [11:10]
-  UINT8   TMP_WRITE_PROTECT:  1; // Temporary write protection [12:12]
-  UINT8   PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
-  UINT8   COPY:               1; // Copy flag (OTP) [14:14]
-  UINT8   FILE_FORMAT_GRP:    1; // File format group [15:15]
-
-  UINT16  RESERVED_2:         5; // Reserved [20:16]
-  UINT16  WRITE_BL_PARTIAL:   1; // Partial blocks for write allowed [21:21]
-  UINT16  WRITE_BL_LEN:       4; // Max. write data block length [25:22]
-  UINT16  R2W_FACTOR:         3; // Write speed factor [28:26]
-  UINT16  RESERVED_3:         2; // Reserved [30:29]
-  UINT16  WP_GRP_ENABLE:      1; // Write protect group enable [31:31]
-
-  UINT32  WP_GRP_SIZE:        7; // Write protect group size [38:32]
-  UINT32  SECTOR_SIZE:        7; // Erase sector size [45:39]
-  UINT32  ERASE_BLK_EN:       1; // Erase single block enable [46:46]
-  UINT32  C_SIZE_MULT:        3; // Device size multiplier [49:47]
-  UINT32  VDD_W_CURR_MAX:     3; // Max. write current @ VDD max [52:50]
-  UINT32  VDD_W_CURR_MIN:     3; // Max. write current @ VDD min [55:53]
-  UINT32  VDD_R_CURR_MAX:     3; // Max. read current @ VDD max [58:56]
-  UINT32  VDD_R_CURR_MIN:     3; // Max. read current @ VDD min [61:59]
-  UINT32  C_SIZELow2:         2; // Device size [63:62]
-
-  UINT32  C_SIZEHigh10:       10;// Device size [73:64]
-  UINT32  RESERVED_4:         2; // Reserved [75:74]
-  UINT32  DSR_IMP:            1; // DSR implemented [76:76]
-  UINT32  READ_BLK_MISALIGN:  1; // Read block misalignment [77:77]
-  UINT32  WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
-  UINT32  READ_BL_PARTIAL:    1; // Partial blocks for read allowed [79:79]
-  UINT32  READ_BL_LEN:        4; // Max. read data block length [83:80]
-  UINT32  CCC:                12;// Card command classes [95:84]
-
-  UINT8   TRAN_SPEED          ;  // Max. bus clock frequency [103:96]
-  UINT8   NSAC                ;  // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
-  UINT8   TAAC                ;  // Data read access-time 1 [119:112]
-
-  UINT8   RESERVED_5:         6; // Reserved [125:120]
-  UINT8   CSD_STRUCTURE:      2; // CSD structure [127:126]
-}CSD;
-
-typedef struct {
-  UINT8   NOT_USED:           1; // Not used, always 1 [0:0]
-  UINT8   CRC:                7; // CRC [7:1]
-  UINT8   RESERVED_1:         2; // Reserved [9:8]
-  UINT8   FILE_FORMAT:        2; // File format [11:10]
-  UINT8   TMP_WRITE_PROTECT:  1; // Temporary write protection [12:12]
-  UINT8   PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
-  UINT8   COPY:               1; // Copy flag (OTP) [14:14]
-  UINT8   FILE_FORMAT_GRP:    1; // File format group [15:15]
-  UINT16  RESERVED_2:         5; // Reserved [20:16]
-  UINT16  WRITE_BL_PARTIAL:   1; // Partial blocks for write allowed [21:21]
-  UINT16  WRITE_BL_LEN:       4; // Max. write data block length [25:22]
-  UINT16  R2W_FACTOR:         3; // Write speed factor [28:26]
-  UINT16  RESERVED_3:         2; // Reserved [30:29]
-  UINT16  WP_GRP_ENABLE:      1; // Write protect group enable [31:31]
-  UINT16  WP_GRP_SIZE:        7; // Write protect group size [38:32]
-  UINT16  SECTOR_SIZE:        7; // Erase sector size [45:39]
-  UINT16  ERASE_BLK_EN:       1; // Erase single block enable [46:46]
-  UINT16  RESERVED_4:         1; // Reserved [47:47]
-  UINT32  C_SIZELow16:        16;// Device size [69:48]
-  UINT32  C_SIZEHigh6:        6; // Device size [69:48]
-  UINT32  RESERVED_5:         6; // Reserved [75:70]
-  UINT32  DSR_IMP:            1; // DSR implemented [76:76]
-  UINT32  READ_BLK_MISALIGN:  1; // Read block misalignment [77:77]
-  UINT32  WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
-  UINT32  READ_BL_PARTIAL:    1; // Partial blocks for read allowed [79:79]
-  UINT16  READ_BL_LEN:        4; // Max. read data block length [83:80]
-  UINT16  CCC:                12;// Card command classes [95:84]
-  UINT8   TRAN_SPEED          ;  // Max. bus clock frequency [103:96]
-  UINT8   NSAC                ;  // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
-  UINT8   TAAC                ;  // Data read access-time 1 [119:112]
-  UINT8   RESERVED_6:         6; // 0 [125:120]
-  UINT8   CSD_STRUCTURE:      2; // CSD structure [127:126]
-}CSD_SDV2;
-
-typedef enum {
-  UNKNOWN_CARD,
-  MMC_CARD,              //MMC card
-  SD_CARD,               //SD 1.1 card
-  SD_CARD_2,             //SD 2.0 or above standard card
-  SD_CARD_2_HIGH         //SD 2.0 or above high capacity card
-} CARD_TYPE;
-
-typedef enum {
-  READ,
-  WRITE
-} OPERATION_TYPE;
-
-typedef struct  {
-  UINT16    RCA;
-  UINTN     BlockSize;
-  UINTN     NumBlocks;
-  UINTN     ClockFrequencySelect;
-  CARD_TYPE CardType;
-  OCR       OCRData;
-  CID       CIDData;
-  CSD       CSDData;
-} CARD_INFO;
-
-EFI_STATUS
-DetectCard (
-  VOID
-  );
-
-extern EFI_BLOCK_IO_PROTOCOL gBlockIo;
-
-#endif
diff --git a/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.inf b/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.inf
deleted file mode 100644
index e40abdc..0000000
--- a/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.inf
+++ /dev/null
@@ -1,54 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = MMCHS
-  FILE_GUID                      = 100c2cfa-b586-4198-9b4c-1683d195b1da
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = MMCHSInitialize
-
-
-[Sources.common]
-  MMCHS.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  PcdLib
-  UefiLib
-  UefiDriverEntryPoint
-  MemoryAllocationLib
-  IoLib
-  OmapDmaLib
-  DmaLib
-
-[Guids]
-
-[Protocols]
-  gEfiBlockIoProtocolGuid
-  gEfiCpuArchProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEmbeddedExternalDeviceProtocolGuid
-
-[Pcd]
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base
-  gOmap35xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds
-
-[depex]
-  gEmbeddedExternalDeviceProtocolGuid
diff --git a/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.c b/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.c
deleted file mode 100755
index ad922a1..0000000
--- a/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.c
+++ /dev/null
@@ -1,677 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-*  Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include "MmcHostDxe.h"
-
-EMBEDDED_EXTERNAL_DEVICE   *gTPS65950;
-UINT8                      mMaxDataTransferRate = 0;
-UINT32                     mRca = 0;
-BOOLEAN                    mBitModeSet = FALSE;
-
-
-typedef struct {
-  VENDOR_DEVICE_PATH  Mmc;
-  EFI_DEVICE_PATH     End;
-} MMCHS_DEVICE_PATH;
-
-MMCHS_DEVICE_PATH gMMCDevicePath = {
-  {
-    {
-      HARDWARE_DEVICE_PATH,
-      HW_VENDOR_DP,
-      { (UINT8)(sizeof(VENDOR_DEVICE_PATH)), (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8) },
-    },
-    { 0xb615f1f5, 0x5088, 0x43cd, { 0x80, 0x9c, 0xa1, 0x6e, 0x52, 0x48, 0x7d, 0x00 } }
-  },
-  {
-    END_DEVICE_PATH_TYPE,
-    END_ENTIRE_DEVICE_PATH_SUBTYPE,
-    { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
-  }
-};
-
-BOOLEAN
-IgnoreCommand (
-  UINT32 Command
-  )
-{
-  switch(Command) {
-    case MMC_CMD12:
-      return TRUE;
-    case MMC_CMD13:
-      return TRUE;
-    default:
-      return FALSE;
-  }
-}
-
-UINT32
-TranslateCommand (
-  UINT32 Command
-  )
-{
-  UINT32 Translation;
-
-  switch(Command) {
-    case MMC_CMD2:
-      Translation = CMD2;
-      break;
-    case MMC_CMD3:
-      Translation = CMD3;
-      break;
-    /*case MMC_CMD6:
-      Translation = CMD6;
-      break;*/
-    case MMC_CMD7:
-      Translation = CMD7;
-      break;
-    case MMC_CMD8:
-      Translation = CMD8;
-      break;
-    case MMC_CMD9:
-      Translation = CMD9;
-      break;
-    /*case MMC_CMD12:
-      Translation = CMD12;
-      break;
-    case MMC_CMD13:
-      Translation = CMD13;
-      break;*/
-    case MMC_CMD16:
-      Translation = CMD16;
-      break;
-    case MMC_CMD17:
-      Translation = 0x113A0014;//CMD17;
-      break;
-    case MMC_CMD24:
-      Translation = CMD24 | 4;
-      break;
-    case MMC_CMD55:
-      Translation = CMD55;
-      break;
-    case MMC_ACMD41:
-      Translation = ACMD41;
-      break;
-    default:
-      Translation = Command;
-  }
-
-  return Translation;
-}
-
-VOID
-CalculateCardCLKD (
-  UINTN *ClockFrequencySelect
-  )
-{
-  UINTN    TransferRateValue = 0;
-  UINTN    TimeValue = 0 ;
-  UINTN    Frequency = 0;
-
-  DEBUG ((DEBUG_BLKIO, "CalculateCardCLKD()\n"));
-
-  // For SD Cards  we would need to send CMD6 to set
-  // speeds abouve 25MHz. High Speed mode 50 MHz and up
-
-  // Calculate Transfer rate unit (Bits 2:0 of TRAN_SPEED)
-  switch (mMaxDataTransferRate & 0x7) { // 2
-    case 0:
-      TransferRateValue = 100 * 1000;
-      break;
-
-    case 1:
-      TransferRateValue = 1 * 1000 * 1000;
-      break;
-
-    case 2:
-      TransferRateValue = 10 * 1000 * 1000;
-      break;
-
-    case 3:
-      TransferRateValue = 100 * 1000 * 1000;
-      break;
-
-    default:
-      DEBUG ((DEBUG_BLKIO, "Invalid parameter.\n"));
-      ASSERT(FALSE);
-      return;
-  }
-
-  //Calculate Time value (Bits 6:3 of TRAN_SPEED)
-  switch ((mMaxDataTransferRate >> 3) & 0xF) { // 6
-    case 1:
-      TimeValue = 10;
-      break;
-
-    case 2:
-      TimeValue = 12;
-      break;
-
-    case 3:
-      TimeValue = 13;
-      break;
-
-    case 4:
-      TimeValue = 15;
-      break;
-
-    case 5:
-      TimeValue = 20;
-      break;
-
-    case 6:
-      TimeValue = 25;
-      break;
-
-    case 7:
-      TimeValue = 30;
-      break;
-
-    case 8:
-      TimeValue = 35;
-      break;
-
-    case 9:
-      TimeValue = 40;
-      break;
-
-    case 10:
-      TimeValue = 45;
-      break;
-
-    case 11:
-      TimeValue = 50;
-      break;
-
-    case 12:
-      TimeValue = 55;
-      break;
-
-    case 13:
-      TimeValue = 60;
-      break;
-
-    case 14:
-      TimeValue = 70;
-      break;
-
-    case 15:
-      TimeValue = 80;
-      break;
-
-    default:
-      DEBUG ((DEBUG_BLKIO, "Invalid parameter.\n"));
-      ASSERT(FALSE);
-      return;
-  }
-
-  Frequency = TransferRateValue * TimeValue/10;
-
-  // Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
-  *ClockFrequencySelect = ((MMC_REFERENCE_CLK/Frequency) + 1);
-
-  DEBUG ((DEBUG_BLKIO, "mMaxDataTransferRate: 0x%x, Frequency: %d KHz, ClockFrequencySelect: %x\n", mMaxDataTransferRate, Frequency/1000, *ClockFrequencySelect));
-}
-
-VOID
-UpdateMMCHSClkFrequency (
-  UINTN NewCLKD
-  )
-{
-  DEBUG ((DEBUG_BLKIO, "UpdateMMCHSClkFrequency()\n"));
-
-  // Set Clock enable to 0x0 to not provide the clock to the card
-  MmioAnd32 (MMCHS_SYSCTL, ~CEN);
-
-  // Set new clock frequency.
-  MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
-
-  // Poll till Internal Clock Stable
-  while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
-
-  // Set Clock enable to 0x1 to provide the clock to the card
-  MmioOr32 (MMCHS_SYSCTL, CEN);
-}
-
-EFI_STATUS
-InitializeMMCHS (
-  VOID
-  )
-{
-  UINT8      Data;
-  EFI_STATUS Status;
-
-  DEBUG ((DEBUG_BLKIO, "InitializeMMCHS()\n"));
-
-  // Select Device group to belong to P1 device group in Power IC.
-  Data = DEV_GRP_P1;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VMMC1_DEV_GRP), 1, &Data);
-  ASSERT_EFI_ERROR(Status);
-
-  // Configure voltage regulator for MMC1 in Power IC to output 3.0 voltage.
-  Data = VSEL_3_00V;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VMMC1_DEDICATED_REG), 1, &Data);
-  ASSERT_EFI_ERROR(Status);
-
-  // After ramping up voltage, set VDDS stable bit to indicate that voltage level is stable.
-  MmioOr32 (CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));
-
-  // Enable WP GPIO
-  MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
-
-  // Enable Card Detect
-  Data = CARD_DETECT_ENABLE;
-  gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, TPS65950_GPIO_CTRL), 1, &Data);
-
-  return Status;
-}
-
-BOOLEAN
-MMCIsCardPresent (
-  IN EFI_MMC_HOST_PROTOCOL     *This
-  )
-{
-  EFI_STATUS  Status;
-  UINT8       Data;
-
-  //
-  // Card detect is a GPIO0 on the TPS65950
-  //
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATAIN1), 1, &Data);
-  if (EFI_ERROR (Status)) {
-    return FALSE;
-  }
-
-  return !(Data & CARD_DETECT_BIT);
-}
-
-BOOLEAN
-MMCIsReadOnly (
-  IN EFI_MMC_HOST_PROTOCOL     *This
-  )
-{
-  /* Note:
-   * On our BeagleBoard the SD card WP pin is always read as TRUE.
-   * Probably something wrong with GPIO configuration.
-   * BeagleBoard-xM uses microSD cards so there is no write protect at all.
-   * Hence commenting out SD card WP pin read status.
-   */
-  //return (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23;
-  return 0;
-
-}
-
-// TODO
-EFI_GUID mPL180MciDevicePathGuid = EFI_CALLER_ID_GUID;
-
-EFI_STATUS
-MMCBuildDevicePath (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN EFI_DEVICE_PATH_PROTOCOL  **DevicePath
-  )
-{
-  EFI_DEVICE_PATH_PROTOCOL    *NewDevicePathNode;
-
-  NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH));
-  CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid);
-  *DevicePath = NewDevicePathNode;
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-MMCSendCommand (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_CMD                   MmcCmd,
-  IN UINT32                    Argument
-  )
-{
-  UINTN MmcStatus;
-  UINTN RetryCount = 0;
-
-  if (IgnoreCommand(MmcCmd))
-    return EFI_SUCCESS;
-
-  MmcCmd = TranslateCommand(MmcCmd);
-
-  //DEBUG ((EFI_D_ERROR, "MMCSendCommand(%d)\n", MmcCmd));
-
-  // Check if command line is in use or not. Poll till command line is available.
-  while ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
-
-  // Provide the block size.
-  MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);
-
-  // Setting Data timeout counter value to max value.
-  MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
-
-  // Clear Status register.
-  MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF);
-
-  // Set command argument register
-  MmioWrite32 (MMCHS_ARG, Argument);
-
-  //TODO: fix this
-  //Enable interrupt enable events to occur
-  //MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal);
-
-  // Send a command
-  MmioWrite32 (MMCHS_CMD, MmcCmd);
-
-  // Check for the command status.
-  while (RetryCount < MAX_RETRY_COUNT) {
-    do {
-      MmcStatus = MmioRead32 (MMCHS_STAT);
-    } while (MmcStatus == 0);
-
-    // Read status of command response
-    if ((MmcStatus & ERRI) != 0) {
-
-      // Perform soft-reset for mmci_cmd line.
-      MmioOr32 (MMCHS_SYSCTL, SRC);
-      while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
-
-      //DEBUG ((EFI_D_INFO, "MmcStatus: 0x%x\n", MmcStatus));
-      return EFI_DEVICE_ERROR;
-    }
-
-    // Check if command is completed.
-    if ((MmcStatus & CC) == CC) {
-      MmioWrite32 (MMCHS_STAT, CC);
-      break;
-    }
-
-    RetryCount++;
-  }
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    DEBUG ((DEBUG_BLKIO, "MMCSendCommand: Timeout\n"));
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-MMCNotifyState (
-  IN EFI_MMC_HOST_PROTOCOL    *This,
-  IN MMC_STATE                State
-  )
-{
-  EFI_STATUS              Status;
-  UINTN                   FreqSel;
-
-  switch(State) {
-    case MmcInvalidState:
-      ASSERT(0);
-      break;
-    case MmcHwInitializationState:
-      mBitModeSet = FALSE;
-
-      DEBUG ((DEBUG_BLKIO, "MMCHwInitializationState()\n"));
-      Status = InitializeMMCHS ();
-      if (EFI_ERROR(Status)) {
-        DEBUG ((DEBUG_BLKIO, "Initialize MMC host controller fails. Status: %x\n", Status));
-        return Status;
-      }
-
-      // Software reset of the MMCHS host controller.
-      MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET);
-      gBS->Stall(1000);
-      while ((MmioRead32 (MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
-
-      // Soft reset for all.
-      MmioWrite32 (MMCHS_SYSCTL, SRA);
-      gBS->Stall(1000);
-      while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
-
-      //Voltage capabilities initialization. Activate VS18 and VS30.
-      MmioOr32 (MMCHS_CAPA, (VS30 | VS18));
-
-      // Wakeup configuration
-      MmioOr32 (MMCHS_SYSCONFIG, ENAWAKEUP);
-      MmioOr32 (MMCHS_HCTL, IWE);
-
-      // MMCHS Controller default initialization
-      MmioOr32 (MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));
-
-      MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
-
-      // Enable internal clock
-      MmioOr32 (MMCHS_SYSCTL, ICE);
-
-      // Set the clock frequency to 80KHz.
-      UpdateMMCHSClkFrequency (CLKD_80KHZ);
-
-      // Enable SD bus power.
-      MmioOr32 (MMCHS_HCTL, (SDBP_ON));
-
-      // Poll till SD bus power bit is set.
-      while ((MmioRead32 (MMCHS_HCTL) & SDBP_MASK) != SDBP_ON);
-
-      // Enable interrupts.
-      MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
-        CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN));
-
-      // Controller INIT procedure start.
-      MmioOr32 (MMCHS_CON, INIT);
-      MmioWrite32 (MMCHS_CMD, 0x00000000);
-      while (!(MmioRead32 (MMCHS_STAT) & CC));
-
-      // Wait for 1 ms
-      gBS->Stall (1000);
-
-      // Set CC bit to 0x1 to clear the flag
-      MmioOr32 (MMCHS_STAT, CC);
-
-      // Retry INIT procedure.
-      MmioWrite32 (MMCHS_CMD, 0x00000000);
-      while (!(MmioRead32 (MMCHS_STAT) & CC));
-
-      // End initialization sequence
-      MmioAnd32 (MMCHS_CON, ~INIT);
-
-      MmioOr32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON));
-
-      // Change clock frequency to 400KHz to fit protocol
-      UpdateMMCHSClkFrequency(CLKD_400KHZ);
-
-      MmioOr32 (MMCHS_CON, OD);
-      break;
-    case MmcIdleState:
-      break;
-    case MmcReadyState:
-      break;
-    case MmcIdentificationState:
-      break;
-    case MmcStandByState:
-      CalculateCardCLKD (&FreqSel);
-      UpdateMMCHSClkFrequency (FreqSel);
-      break;
-    case MmcTransferState:
-      if (!mBitModeSet) {
-        Status = MMCSendCommand (This, CMD55, mRca << 16);
-        if (!EFI_ERROR (Status)) {
-          // Set device into 4-bit data bus mode
-          Status = MMCSendCommand (This, ACMD6, 0x2);
-          if (!EFI_ERROR (Status)) {
-            // Set host controler into 4-bit mode
-            MmioOr32 (MMCHS_HCTL, DTW_4_BIT);
-            DEBUG ((DEBUG_BLKIO, "SD Memory Card set to 4-bit mode\n"));
-            mBitModeSet = TRUE;
-          }
-        }
-      }
-      break;
-    case MmcSendingDataState:
-      break;
-    case MmcReceiveDataState:
-      break;
-    case MmcProgrammingState:
-      break;
-    case MmcDisconnectState:
-    default:
-      ASSERT(0);
-  }
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-MMCReceiveResponse (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_RESPONSE_TYPE         Type,
-  IN UINT32*                   Buffer
-  )
-{
-  if (Buffer == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  if (Type == MMC_RESPONSE_TYPE_R2) {
-    Buffer[0] = MmioRead32 (MMCHS_RSP10);
-    Buffer[1] = MmioRead32 (MMCHS_RSP32);
-    Buffer[2] = MmioRead32 (MMCHS_RSP54);
-    Buffer[3] = MmioRead32 (MMCHS_RSP76);
-  } else {
-    Buffer[0] = MmioRead32 (MMCHS_RSP10);
-  }
-
-  if (Type == MMC_RESPONSE_TYPE_CSD) {
-    mMaxDataTransferRate = Buffer[3] & 0xFF;
-  } else if (Type == MMC_RESPONSE_TYPE_RCA) {
-    mRca = Buffer[0] >> 16;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-MMCReadBlockData (
-  IN EFI_MMC_HOST_PROTOCOL      *This,
-  IN EFI_LBA                    Lba,
-  IN UINTN                      Length,
-  IN UINT32*                    Buffer
-  )
-{
-  UINTN MmcStatus;
-  UINTN Count;
-  UINTN RetryCount = 0;
-
-  DEBUG ((DEBUG_BLKIO, "MMCReadBlockData(LBA: 0x%x, Length: 0x%x, Buffer: 0x%x)\n", Lba, Length, Buffer));
-
-  // Check controller status to make sure there is no error.
-  while (RetryCount < MAX_RETRY_COUNT) {
-    do {
-      // Read Status.
-      MmcStatus = MmioRead32 (MMCHS_STAT);
-    } while(MmcStatus == 0);
-
-    // Check if Buffer read ready (BRR) bit is set?
-    if (MmcStatus & BRR) {
-
-      // Clear BRR bit
-      MmioOr32 (MMCHS_STAT, BRR);
-
-      for (Count = 0; Count < Length / 4; Count++) {
-        *Buffer++ = MmioRead32(MMCHS_DATA);
-      }
-      break;
-    }
-    RetryCount++;
-  }
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-MMCWriteBlockData (
-  IN EFI_MMC_HOST_PROTOCOL    *This,
-  IN EFI_LBA                  Lba,
-  IN UINTN                    Length,
-  IN UINT32*                  Buffer
-  )
-{
-  UINTN MmcStatus;
-  UINTN Count;
-  UINTN RetryCount = 0;
-
-  // Check controller status to make sure there is no error.
-  while (RetryCount < MAX_RETRY_COUNT) {
-    do {
-      // Read Status.
-      MmcStatus = MmioRead32 (MMCHS_STAT);
-    } while(MmcStatus == 0);
-
-    // Check if Buffer write ready (BWR) bit is set?
-    if (MmcStatus & BWR) {
-
-      // Clear BWR bit
-      MmioOr32 (MMCHS_STAT, BWR);
-
-      // Write block worth of data.
-      for (Count = 0; Count < Length / 4; Count++) {
-        MmioWrite32 (MMCHS_DATA, *Buffer++);
-      }
-
-      break;
-    }
-    RetryCount++;
-  }
-
-  if (RetryCount == MAX_RETRY_COUNT) {
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_MMC_HOST_PROTOCOL gMMCHost = {
-  MMC_HOST_PROTOCOL_REVISION,
-  MMCIsCardPresent,
-  MMCIsReadOnly,
-  MMCBuildDevicePath,
-  MMCNotifyState,
-  MMCSendCommand,
-  MMCReceiveResponse,
-  MMCReadBlockData,
-  MMCWriteBlockData
-};
-
-EFI_STATUS
-MMCInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS    Status;
-  EFI_HANDLE    Handle = NULL;
-
-  DEBUG ((DEBUG_BLKIO, "MMCInitialize()\n"));
-
-  Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
-  ASSERT_EFI_ERROR(Status);
-
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &Handle,
-                  &gEfiMmcHostProtocolGuid,         &gMMCHost,
-                  NULL
-                  );
-  ASSERT_EFI_ERROR (Status);
-
-  return Status;
-}
diff --git a/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.inf b/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.inf
deleted file mode 100755
index f6cca8c..0000000
--- a/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.inf
+++ /dev/null
@@ -1,53 +0,0 @@
-#  Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = MMC
-  FILE_GUID                      = 100c2cfa-b586-4198-9b4c-1683d195b1da
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = MMCInitialize
-
-
-[Sources.common]
-  MmcHostDxe.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  PcdLib
-  UefiLib
-  UefiDriverEntryPoint
-  MemoryAllocationLib
-  IoLib
-  OmapDmaLib
-  DmaLib
-
-[Guids]
-
-[Protocols]
-  gEfiBlockIoProtocolGuid
-  gEfiCpuArchProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEmbeddedExternalDeviceProtocolGuid
-  gEfiMmcHostProtocolGuid
-
-[Pcd]
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base
-  gOmap35xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds
-
-[depex]
-  gEmbeddedExternalDeviceProtocolGuid
diff --git a/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec b/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
deleted file mode 100644
index 8924e2a..0000000
--- a/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
+++ /dev/null
@@ -1,58 +0,0 @@
-#/** @file
-# Omap35xx SoC package.
-#
-# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-#
-#    This program and the accompanying materials are licensed and made available under
-#    the terms and conditions of the BSD License which accompanies this distribution.
-#    The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
-#
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = Omap35xxPkg
-  PACKAGE_GUID                   = D196A631-B7B7-4953-A3EE-0F773CBABF20
-  PACKAGE_VERSION                = 0.1
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-#                   Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-[Includes.common]
-  Include                        # Root include for the package
-
-[LibraryClasses]
-  ##  @libraryclass  Abstract location of basic OMAP components
-  ##
-  OmapLib|Include/Library/OmapLib.h
-
-  ##  @libraryclass  Abstract OMAP and ARM DMA, modeled after PCI IO protocol
-  ##
-  OmapDmaLib|Include/Library/OmapDmaLib.h
-
-
-[Guids.common]
-  gOmap35xxTokenSpaceGuid    =  { 0x24b09abe, 0x4e47, 0x481c, { 0xa9, 0xad, 0xce, 0xf1, 0x2c, 0x39, 0x23, 0x27} }
-
-[PcdsFeatureFlag.common]
-
-[PcdsFixedAtBuild.common]
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart|3|UINT32|0x00000202
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset|0x00000000|UINT32|0x00000203
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base|0x00000000|UINT32|0x00000204
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer|3|UINT32|0x00000205
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer|4|UINT32|0x00000206
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxDebugAgentTimer|5|UINT32|0x00000207
-  gOmap35xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds|77|UINT32|0x00000208
-  gOmap35xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds|1000000|UINT32|0x00000209
-
diff --git a/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc b/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc
deleted file mode 100644
index 60edc79..0000000
--- a/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc
+++ /dev/null
@@ -1,188 +0,0 @@
-#/** @file
-# Omap35xx SoC package.
-#
-# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-#
-#    This program and the accompanying materials
-#    are licensed and made available under the terms and conditions of the BSD License
-#    which accompanies this distribution. The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
-#
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
-  PLATFORM_NAME                  = Omap35xxPkg
-  PLATFORM_GUID                  = D196A631-B7B7-4953-A3EE-0F773CBABF20
-  PLATFORM_VERSION               = 0.1
-  DSC_SPECIFICATION              = 0x00010005
-  OUTPUT_DIRECTORY               = Build/Omap35xxPkg
-  SUPPORTED_ARCHITECTURES        = ARM
-  BUILD_TARGETS                  = DEBUG|RELEASE
-  SKUID_IDENTIFIER               = DEFAULT
-  DEFINE TARGET_HACK             = DEBUG
-
-
-[LibraryClasses.common]
-  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
-
-  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-
-  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
-  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-
-  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
-
-  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
-  DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
-  CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
-  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
-
-  RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
-
-  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-  OmapLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapLib/OmapLib.inf
-  OmapDmaLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/OmapDmaLib.inf
-
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
-  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
-  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
-  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
-
-  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
-  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
-  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
-
-#
-# Assume everything is fixed at build
-#
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-
-  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
-
- # UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
-  UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
-
-  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
-
-
-[LibraryClasses.common.DXE_DRIVER]
-  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
-
-
-[LibraryClasses.ARM]
-  #
-  # Note: This NULL library feature is not yet in the edk2/BaseTools, but it is checked in to
-  # the BaseTools project. So you need to build with the BaseTools project util this feature gets synced.
-  #
-  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
-
-
-[BuildOptions]
-  XCODE:*_*_ARM_ARCHCC_FLAGS     == -arch armv7 -march=armv7
-  XCODE:*_*_ARM_ARCHASM_FLAGS    == -arch armv7
-  XCODE:*_*_ARM_ARCHDLINK_FLAGS  == -arch armv7
-
-  GCC:*_*_ARM_ARCHCC_FLAGS     == -march=armv7-a -mthumb
-  GCC:*_*_ARM_ARCHASM_FLAGS    == -march=armv7-a
-
-  RVCT:*_*_ARM_ARCHCC_FLAGS     == --cpu 7-A
-  RVCT:*_*_ARM_ARCHASM_FLAGS    == --cpu 7-A
-
-
-################################################################################
-#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
-#
-################################################################################
-
-
-[PcdsFixedAtBuild.common]
-
-# DEBUG_ASSERT_ENABLED       0x01
-# DEBUG_PRINT_ENABLED        0x02
-# DEBUG_CODE_ENABLED         0x04
-# CLEAR_MEMORY_ENABLED       0x08
-# ASSERT_BREAKPOINT_ENABLED  0x10
-# ASSERT_DEADLOOP_ENABLED    0x20
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
-
-#  DEBUG_INIT      0x00000001  // Initialization
-#  DEBUG_WARN      0x00000002  // Warnings
-#  DEBUG_LOAD      0x00000004  // Load events
-#  DEBUG_FS        0x00000008  // EFI File system
-#  DEBUG_POOL      0x00000010  // Alloc & Free's
-#  DEBUG_PAGE      0x00000020  // Alloc & Free's
-#  DEBUG_INFO      0x00000040  // Verbose
-#  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
-#  DEBUG_VARIABLE  0x00000100  // Variable
-#  DEBUG_BM        0x00000400  // Boot Manager
-#  DEBUG_BLKIO     0x00001000  // BlkIo Driver
-#  DEBUG_NET       0x00004000  // SNI Driver
-#  DEBUG_UNDI      0x00010000  // UNDI Driver
-#  DEBUG_LOADFILE  0x00020000  // UNDI Driver
-#  DEBUG_EVENT     0x00080000  // Event messages
-#  DEBUG_ERROR     0x80000000  // Error
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
-
-  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
-
-  gEmbeddedTokenSpaceGuid.PcdPrePiTempMemorySize|0
-  gEmbeddedTokenSpaceGuid.PcdPrePiBfvBaseAddress|0
-  gEmbeddedTokenSpaceGuid.PcdPrePiBfvSize|0
-  gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0
-  gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0
-  gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000
-  gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory
-  gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000  # 128K stack
-  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000
-  gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
-
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset|0x6E000000
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base|0x4809C000
-
-  # Console
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart|3
-
-  # Timers
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer|3
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer|4
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds|77
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|13000000
-
-  #
-  # ARM Pcds
-  #
-  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
-
-################################################################################
-#
-# Components Section - list of all EDK II Modules needed by this Platform
-#
-################################################################################
-[Components.common]
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapLib/OmapLib.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/OmapDmaLib.inf
-
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Flash/Flash.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MMCHSDxe/MMCHS.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Gpio/Gpio.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/InterruptDxe/InterruptDxe.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/TimerDxe/TimerDxe.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.inf
-
-
-
diff --git a/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.c b/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.c
deleted file mode 100644
index 17ea03c..0000000
--- a/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "PciEmulation.h"
-
-EMBEDDED_EXTERNAL_DEVICE   *gTPS65950;
-
-#define HOST_CONTROLLER_OPERATION_REG_SIZE  0x44
-
-typedef struct {
-  ACPI_HID_DEVICE_PATH      AcpiDevicePath;
-  PCI_DEVICE_PATH           PciDevicePath;
-  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
-} EFI_PCI_IO_DEVICE_PATH;
-
-typedef struct {
-  UINT32                  Signature;
-  EFI_PCI_IO_DEVICE_PATH  DevicePath;
-  EFI_PCI_IO_PROTOCOL     PciIoProtocol;
-  PCI_TYPE00              *ConfigSpace;
-  PCI_ROOT_BRIDGE         RootBridge;
-  UINTN                   Segment;
-} EFI_PCI_IO_PRIVATE_DATA;
-
-#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE     SIGNATURE_32('p', 'c', 'i', 'o')
-#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a)  CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
-
-EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
-{
-  {
-    { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },
-    EISA_PNP_ID(0x0A03),  // HID
-    0                     // UID
-  },
-  {
-    { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },
-    0,
-    0
-  },
-  { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }
-};
-
-STATIC
-VOID
-ConfigureUSBHost (
-  VOID
-  )
-{
-  EFI_STATUS Status;
-  UINT8      Data = 0;
-
-  // Take USB host out of force-standby mode
-  MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
-                            | UHH_SYSCONFIG_CLOCKACTIVITY_ON
-                            | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
-                            | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
-                            | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
-  MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
-                             | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
-                             | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
-                             | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
-                             | UHH_HOSTCONFIG_ENA_INCR16_ENABLE
-                             | UHH_HOSTCONFIG_ENA_INCR8_ENABLE
-                             | UHH_HOSTCONFIG_ENA_INCR4_ENABLE
-                             | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
-                             | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
-
-  // USB reset (GPIO 147 - Port 5 pin 19) output high
-  MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);
-  MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
-
-  // Get the Power IC protocol
-  Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
-  ASSERT_EFI_ERROR (Status);
-
-  // Power the USB PHY
-  Data = VAUX_DEV_GRP_P1;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEV_GRP), 1, &Data);
-  ASSERT_EFI_ERROR(Status);
-
-  Data = VAUX_DEDICATED_18V;
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEDICATED), 1, &Data);
-  ASSERT_EFI_ERROR (Status);
-
-  // Enable power to the USB hub
-  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
-  ASSERT_EFI_ERROR (Status);
-
-  // LEDAON controls the power to the USB host, PWM is disabled
-  Data &= ~LEDAPWM;
-  Data |= LEDAON;
-
-  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
-  ASSERT_EFI_ERROR (Status);
-}
-
-
-EFI_STATUS
-PciIoPollMem (
-  IN EFI_PCI_IO_PROTOCOL           *This,
-  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,
-  IN  UINT8                        BarIndex,
-  IN  UINT64                       Offset,
-  IN  UINT64                       Mask,
-  IN  UINT64                       Value,
-  IN  UINT64                       Delay,
-  OUT UINT64                       *Result
-  )
-{
-  ASSERT (FALSE);
-  return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-PciIoPollIo (
-  IN EFI_PCI_IO_PROTOCOL           *This,
-  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,
-  IN  UINT8                        BarIndex,
-  IN  UINT64                       Offset,
-  IN  UINT64                       Mask,
-  IN  UINT64                       Value,
-  IN  UINT64                       Delay,
-  OUT UINT64                       *Result
-  )
-{
-  ASSERT (FALSE);
-  return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-PciIoMemRead (
-  IN EFI_PCI_IO_PROTOCOL              *This,
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
-  IN     UINT8                        BarIndex,
-  IN     UINT64                       Offset,
-  IN     UINTN                        Count,
-  IN OUT VOID                         *Buffer
-  )
-{
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
-
-  return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
-                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
-                                Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
-                                Count,
-                                Buffer
-                                );
-}
-
-EFI_STATUS
-PciIoMemWrite (
-  IN EFI_PCI_IO_PROTOCOL              *This,
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
-  IN     UINT8                        BarIndex,
-  IN     UINT64                       Offset,
-  IN     UINTN                        Count,
-  IN OUT VOID                         *Buffer
-  )
-{
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
-
-  return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
-                                 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
-                                 Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
-                                 Count,
-                                 Buffer
-                                 );
-}
-
-EFI_STATUS
-PciIoIoRead (
-  IN EFI_PCI_IO_PROTOCOL              *This,
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
-  IN     UINT8                        BarIndex,
-  IN     UINT64                       Offset,
-  IN     UINTN                        Count,
-  IN OUT VOID                         *Buffer
-  )
-{
-  ASSERT (FALSE);
-  return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-PciIoIoWrite (
-  IN EFI_PCI_IO_PROTOCOL              *This,
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
-  IN     UINT8                        BarIndex,
-  IN     UINT64                       Offset,
-  IN     UINTN                        Count,
-  IN OUT VOID                         *Buffer
-  )
-{
-  ASSERT (FALSE);
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  Enable a PCI driver to read PCI controller registers in PCI configuration space.
-
-  @param[in]      This    A pointer to the EFI_PCI_IO_PROTOCOL instance.
-  @param[in]      Width   Signifies the width of the memory operations.
-  @param[in]      Offset  The offset within the PCI configuration space for
-                          the PCI controller.
-  @param[in]      Count   The number of PCI configuration operations to
-                          perform. Bytes moved is Width size * Count,
-                          starting at Offset.
-
-  @param[in out]  Buffer  The destination buffer to store the results.
-
-  @retval  EFI_SUCCESS            The data was read from the PCI controller.
-  @retval  EFI_INVALID_PARAMETER  "Width" is invalid.
-  @retval  EFI_INVALID_PARAMETER  "Buffer" is NULL.
-
-**/
-EFI_STATUS
-PciIoPciRead (
-  IN     EFI_PCI_IO_PROTOCOL       *This,
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT32                     Offset,
-  IN     UINTN                      Count,
-  IN OUT VOID                      *Buffer
-  )
-{
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
-  EFI_STATUS Status;
-
-  if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  Status = PciRootBridgeIoMemRW (
-             (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
-             Count,
-             TRUE,
-             (PTR)(UINTN)Buffer,
-             TRUE,
-             (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)  //Fix me ConfigSpace
-             );
-
-  return Status;
-}
-
-/**
-  Enable a PCI driver to write PCI controller registers in PCI configuration space.
-
-  @param[in]      This    A pointer to the EFI_PCI_IO_PROTOCOL instance.
-  @param[in]      Width   Signifies the width of the memory operations.
-  @param[in]      Offset  The offset within the PCI configuration space for
-                          the PCI controller.
-  @param[in]      Count   The number of PCI configuration operations to
-                          perform. Bytes moved is Width size * Count,
-                          starting at Offset.
-
-  @param[in out]  Buffer  The source buffer to write data from.
-
-  @retval  EFI_SUCCESS            The data was read from the PCI controller.
-  @retval  EFI_INVALID_PARAMETER  "Width" is invalid.
-  @retval  EFI_INVALID_PARAMETER  "Buffer" is NULL.
-
-**/
-EFI_STATUS
-PciIoPciWrite (
-  IN EFI_PCI_IO_PROTOCOL              *This,
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
-  IN     UINT32                       Offset,
-  IN     UINTN                        Count,
-  IN OUT VOID                         *Buffer
-  )
-{
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
-
-  if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
-                               Count,
-                               TRUE,
-                               (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
-                               TRUE,
-                               (PTR)(UINTN)Buffer
-                               );
-}
-
-EFI_STATUS
-PciIoCopyMem (
-  IN EFI_PCI_IO_PROTOCOL              *This,
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
-  IN     UINT8                        DestBarIndex,
-  IN     UINT64                       DestOffset,
-  IN     UINT8                        SrcBarIndex,
-  IN     UINT64                       SrcOffset,
-  IN     UINTN                        Count
-  )
-{
-  ASSERT (FALSE);
-  return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-PciIoMap (
-  IN EFI_PCI_IO_PROTOCOL                *This,
-  IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,
-  IN     VOID                           *HostAddress,
-  IN OUT UINTN                          *NumberOfBytes,
-  OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,
-  OUT    VOID                           **Mapping
-  )
-{
-  DMA_MAP_OPERATION   DmaOperation;
-
-  if (Operation == EfiPciIoOperationBusMasterRead) {
-    DmaOperation = MapOperationBusMasterRead;
-  } else if (Operation == EfiPciIoOperationBusMasterWrite) {
-    DmaOperation = MapOperationBusMasterWrite;
-  } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {
-    DmaOperation = MapOperationBusMasterCommonBuffer;
-  } else {
-    return EFI_INVALID_PARAMETER;
-  }
-  return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
-}
-
-EFI_STATUS
-PciIoUnmap (
-  IN EFI_PCI_IO_PROTOCOL           *This,
-  IN  VOID                         *Mapping
-  )
-{
-  return DmaUnmap (Mapping);
-}
-
-/**
-  Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
-  mapping.
-
-  @param[in]   This         A pointer to the EFI_PCI_IO_PROTOCOL instance.
-  @param[in]   Type         This parameter is not used and must be ignored.
-  @param[in]   MemoryType   The type of memory to allocate, EfiBootServicesData or
-                            EfiRuntimeServicesData.
-  @param[in]   Pages        The number of pages to allocate.
-  @param[out]  HostAddress  A pointer to store the base system memory address of
-                            the allocated range.
-  @param[in]   Attributes   The requested bit mask of attributes for the allocated
-                            range. Only the attributes,
-                            EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE and
-                            EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be used with this
-                            function. If any other bits are set, then EFI_UNSUPPORTED
-                            is returned. This function ignores this bit mask.
-
-  @retval  EFI_SUCCESS            The requested memory pages were allocated.
-  @retval  EFI_INVALID_PARAMETER  HostAddress is NULL.
-  @retval  EFI_INVALID_PARAMETER  MemoryType is invalid.
-  @retval  EFI_UNSUPPORTED        Attributes is unsupported.
-  @retval  EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.
-
-**/
-EFI_STATUS
-PciIoAllocateBuffer (
-  IN EFI_PCI_IO_PROTOCOL  *This,
-  IN  EFI_ALLOCATE_TYPE   Type,
-  IN  EFI_MEMORY_TYPE     MemoryType,
-  IN  UINTN               Pages,
-  OUT VOID                **HostAddress,
-  IN  UINT64              Attributes
-  )
-{
-  if (Attributes &
-      (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE |
-         EFI_PCI_ATTRIBUTE_MEMORY_CACHED         ))) {
-    return EFI_UNSUPPORTED;
-  }
-
-  return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
-}
-
-
-EFI_STATUS
-PciIoFreeBuffer (
-  IN EFI_PCI_IO_PROTOCOL           *This,
-  IN  UINTN                        Pages,
-  IN  VOID                         *HostAddress
-  )
-{
-  return DmaFreeBuffer (Pages, HostAddress);
-}
-
-
-EFI_STATUS
-PciIoFlush (
-  IN EFI_PCI_IO_PROTOCOL  *This
-  )
-{
-  return EFI_SUCCESS;
-}
-
-/**
-  Retrieves this PCI controller's current PCI bus number, device number, and function number.
-
-  @param[in]   This            A pointer to the EFI_PCI_IO_PROTOCOL instance.
-  @param[out]  SegmentNumber   The PCI controller's current PCI segment number.
-  @param[out]  BusNumber       The PCI controller's current PCI bus number.
-  @param[out]  DeviceNumber    The PCI controller's current PCI device number.
-  @param[out]  FunctionNumber  The PCI controller’s current PCI function number.
-
-  @retval  EFI_SUCCESS            The PCI controller location was returned.
-  @retval  EFI_INVALID_PARAMETER  At least one out of the four output parameters is
-                                  a NULL pointer.
-**/
-EFI_STATUS
-PciIoGetLocation (
-  IN   EFI_PCI_IO_PROTOCOL  *This,
-  OUT  UINTN                *SegmentNumber,
-  OUT  UINTN                *BusNumber,
-  OUT  UINTN                *DeviceNumber,
-  OUT  UINTN                *FunctionNumber
-  )
-{
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
-
-  if ((SegmentNumber == NULL) || (BusNumber      == NULL) ||
-      (DeviceNumber  == NULL) || (FunctionNumber == NULL)    ) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  *SegmentNumber  = Private->Segment;
-  *BusNumber      = 0xff;
-  *DeviceNumber   = 0;
-  *FunctionNumber = 0;
-
-  return EFI_SUCCESS;
-}
-
-/**
-  Performs an operation on the attributes that this PCI controller supports.
-
-  The operations include getting the set of supported attributes, retrieving
-  the current attributes, setting the current attributes, enabling attributes,
-  and disabling attributes.
-
-  @param[in]   This        A pointer to the EFI_PCI_IO_PROTOCOL instance.
-  @param[in]   Operation   The operation to perform on the attributes for this
-                           PCI controller.
-  @param[in]   Attributes  The mask of attributes that are used for Set,
-                           Enable and Disable operations.
-  @param[out]  Result      A pointer to the result mask of attributes that are
-                           returned for the Get and Supported operations. This
-                           is an optional parameter that may be NULL for the
-                           Set, Enable, and Disable operations.
-
-  @retval  EFI_SUCCESS            The operation on the PCI controller's
-                                  attributes was completed. If the operation
-                                  was Get or Supported, then the attribute mask
-                                  is returned in Result.
-  @retval  EFI_INVALID_PARAMETER  Operation is greater than or equal to
-                                  EfiPciIoAttributeOperationMaximum.
-  @retval  EFI_INVALID_PARAMETER  Operation is Get and Result is NULL.
-  @retval  EFI_INVALID_PARAMETER  Operation is Supported and Result is NULL.
-
-**/
-EFI_STATUS
-PciIoAttributes (
-  IN EFI_PCI_IO_PROTOCOL                       *This,
-  IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,
-  IN  UINT64                                   Attributes,
-  OUT UINT64                                   *Result OPTIONAL
-  )
-{
-  switch (Operation) {
-  case EfiPciIoAttributeOperationGet:
-  case EfiPciIoAttributeOperationSupported:
-    if (Result == NULL) {
-      return EFI_INVALID_PARAMETER;
-    }
-    //
-    // We are not a real PCI device so just say things we kind of do
-    //
-    *Result = EFI_PCI_DEVICE_ENABLE;
-    break;
-
-  case EfiPciIoAttributeOperationSet:
-  case EfiPciIoAttributeOperationEnable:
-  case EfiPciIoAttributeOperationDisable:
-    if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) {
-      return EFI_UNSUPPORTED;
-    }
-    // Since we are not a real PCI device no enable/set or disable operations exist.
-    return EFI_SUCCESS;
-
-  default:
-    return EFI_INVALID_PARAMETER;
-  };
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-PciIoGetBarAttributes (
-  IN EFI_PCI_IO_PROTOCOL             *This,
-  IN  UINT8                          BarIndex,
-  OUT UINT64                         *Supports, OPTIONAL
-  OUT VOID                           **Resources OPTIONAL
-  )
-{
-  ASSERT (FALSE);
-  return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-PciIoSetBarAttributes (
-  IN EFI_PCI_IO_PROTOCOL              *This,
-  IN     UINT64                       Attributes,
-  IN     UINT8                        BarIndex,
-  IN OUT UINT64                       *Offset,
-  IN OUT UINT64                       *Length
-  )
-{
-  ASSERT (FALSE);
-  return EFI_UNSUPPORTED;
-}
-
-EFI_PCI_IO_PROTOCOL PciIoTemplate =
-{
-  PciIoPollMem,
-  PciIoPollIo,
-  { PciIoMemRead, PciIoMemWrite },
-  { PciIoIoRead,  PciIoIoWrite },
-  { PciIoPciRead, PciIoPciWrite },
-  PciIoCopyMem,
-  PciIoMap,
-  PciIoUnmap,
-  PciIoAllocateBuffer,
-  PciIoFreeBuffer,
-  PciIoFlush,
-  PciIoGetLocation,
-  PciIoAttributes,
-  PciIoGetBarAttributes,
-  PciIoSetBarAttributes,
-  0,
-  0
-};
-
-EFI_STATUS
-EFIAPI
-PciEmulationEntryPoint (
-  IN EFI_HANDLE       ImageHandle,
-  IN EFI_SYSTEM_TABLE *SystemTable
-  )
-{
-  EFI_STATUS              Status;
-  EFI_HANDLE              Handle;
-  EFI_PCI_IO_PRIVATE_DATA *Private;
-  UINT8                   CapabilityLength;
-  UINT8                   PhysicalPorts;
-  UINTN                   Count;
-
-
-  //Configure USB host for OMAP3530.
-  ConfigureUSBHost();
-
-  // Create a private structure
-  Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));
-  if (Private == NULL) {
-    Status = EFI_OUT_OF_RESOURCES;
-    return Status;
-  }
-
-  Private->Signature              = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE;  // Fill in signature
-  Private->RootBridge.Signature   = PCI_ROOT_BRIDGE_SIGNATURE;          // Fake Root Bridge structure needs a signature too
-  Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE;                 // Get the USB capability register base
-  Private->Segment                = 0;                                  // Default to segment zero
-
-  // Find out the capability register length and number of physical ports.
-  CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);
-  PhysicalPorts    = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
-
-  // Calculate the total size of the USB registers.
-  Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
-
-  // Enable Port Power bit in Port status and control registers in EHCI register space.
-  // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
-  // host controller implementation includes port power control.
-  for (Count = 0; Count < PhysicalPorts; Count++) {
-    MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
-  }
-
-  // Create fake PCI config space.
-  Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));
-  if (Private->ConfigSpace == NULL) {
-    Status = EFI_OUT_OF_RESOURCES;
-    FreePool(Private);
-    return Status;
-  }
-
-  // Configure PCI config space
-  Private->ConfigSpace->Hdr.VendorId = 0xFFFF; // Invalid vendor Id as it is not an actual device.
-  Private->ConfigSpace->Hdr.DeviceId = 0x0000; // Not relevant as the vendor id is not valid.
-  Private->ConfigSpace->Hdr.ClassCode[0] = 0x20;
-  Private->ConfigSpace->Hdr.ClassCode[1] = 0x03;
-  Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C;
-  Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;
-
-  Handle = NULL;
-
-  // Unique device path.
-  CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));
-  Private->DevicePath.AcpiDevicePath.UID = 0;
-
-  // Copy protocol structure
-  CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));
-
-  Status = gBS->InstallMultipleProtocolInterfaces(&Handle,
-                                                  &gEfiPciIoProtocolGuid,       &Private->PciIoProtocol,
-                                                  &gEfiDevicePathProtocolGuid,  &Private->DevicePath,
-                                                  NULL);
-  if (EFI_ERROR(Status)) {
-    DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));
-  }
-
-  return Status;
-}
-
diff --git a/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.h b/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.h
deleted file mode 100644
index d5ee043..0000000
--- a/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _PCI_ROOT_BRIDGE_H_
-#define _PCI_ROOT_BRIDGE_H_
-
-#include <PiDxe.h>
-
-#include <TPS65950.h>
-
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PciLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/OmapDmaLib.h>
-#include <Library/DmaLib.h>
-
-#include <Protocol/EmbeddedExternalDevice.h>
-#include <Protocol/DevicePath.h>
-#include <Protocol/PciIo.h>
-#include <Protocol/PciRootBridgeIo.h>
-#include <Protocol/PciHostBridgeResourceAllocation.h>
-
-#include <IndustryStandard/Pci22.h>
-#include <IndustryStandard/Acpi.h>
-
-#include <Omap3530/Omap3530.h>
-
-
-
-#define EFI_RESOURCE_NONEXISTENT  0xFFFFFFFFFFFFFFFFULL
-#define EFI_RESOURCE_LESS         0xFFFFFFFFFFFFFFFEULL
-#define EFI_RESOURCE_SATISFIED    0x0000000000000000ULL
-
-
-typedef struct {
-  ACPI_HID_DEVICE_PATH      AcpiDevicePath;
-  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;
-} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
-
-
-#define ACPI_CONFIG_IO    0
-#define ACPI_CONFIG_MMIO  1
-#define ACPI_CONFIG_BUS   2
-
-typedef struct {
-  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];
-  EFI_ACPI_END_TAG_DESCRIPTOR       EndDesc;
-} ACPI_CONFIG_INFO;
-
-
-#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')
-
-typedef struct {
-  UINT32                                            Signature;
-  EFI_HANDLE                                        Handle;
-  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL                   Io;
-  EFI_PCI_ROOT_BRIDGE_DEVICE_PATH                   DevicePath;
-
-  UINT8   StartBus;
-  UINT8   EndBus;
-  UINT16  Type;
-  UINT32  MemoryStart;
-  UINT32  MemorySize;
-  UINTN   IoOffset;
-  UINT32  IoStart;
-  UINT32  IoSize;
-  UINT64  PciAttributes;
-
-  ACPI_CONFIG_INFO  *Config;
-
-} PCI_ROOT_BRIDGE;
-
-
-#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
-
-
-typedef union {
-  UINT8   volatile  *buf;
-  UINT8   volatile  *ui8;
-  UINT16  volatile  *ui16;
-  UINT32  volatile  *ui32;
-  UINT64  volatile  *ui64;
-  UINTN   volatile  ui;
-} PTR;
-
-
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoPollMem (
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN  UINT64                                 Address,
-  IN  UINT64                                 Mask,
-  IN  UINT64                                 Value,
-  IN  UINT64                                 Delay,
-  OUT UINT64                                 *Result
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoPollIo (
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN  UINT64                                 Address,
-  IN  UINT64                                 Mask,
-  IN  UINT64                                 Value,
-  IN  UINT64                                 Delay,
-  OUT UINT64                                 *Result
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoMemRead (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 Address,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *Buffer
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoMemWrite (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 Address,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *Buffer
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoIoRead (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 UserAddress,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *UserBuffer
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoIoWrite (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 UserAddress,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *UserBuffer
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoCopyMem (
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN UINT64                                 DestAddress,
-  IN UINT64                                 SrcAddress,
-  IN UINTN                                  Count
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoPciRead (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 Address,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *Buffer
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoPciWrite (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 Address,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *Buffer
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoMap (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
-  IN     VOID                                       *HostAddress,
-  IN OUT UINTN                                      *NumberOfBytes,
-  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
-  OUT    VOID                                       **Mapping
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoUnmap (
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
-  IN VOID                             *Mapping
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoAllocateBuffer (
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
-  IN  EFI_ALLOCATE_TYPE                Type,
-  IN  EFI_MEMORY_TYPE                  MemoryType,
-  IN  UINTN                            Pages,
-  OUT VOID                             **HostAddress,
-  IN  UINT64                           Attributes
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoFreeBuffer (
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
-  IN  UINTN                            Pages,
-  OUT VOID                             *HostAddress
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoFlush (
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoGetAttributes (
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
-  OUT UINT64                           *Supported,
-  OUT UINT64                           *Attributes
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoSetAttributes (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
-  IN     UINT64                           Attributes,
-  IN OUT UINT64                           *ResourceBase,
-  IN OUT UINT64                           *ResourceLength
-  );
-
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoConfiguration (
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
-  OUT VOID                             **Resources
-  );
-
-//
-// Private Function Prototypes
-//
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoMemRW (
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN  UINTN                                  Count,
-  IN  BOOLEAN                                InStrideFlag,
-  IN  PTR                                    In,
-  IN  BOOLEAN                                OutStrideFlag,
-  OUT PTR                                    Out
-  );
-
-BOOLEAN
-PciIoMemAddressValid (
-  IN EFI_PCI_IO_PROTOCOL  *This,
-  IN UINT64               Address
-  );
-
-EFI_STATUS
-EmulatePciIoForEhci (
-  INTN    MvPciIfMaxIf
-  );
-
-#endif
-
diff --git a/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.inf b/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.inf
deleted file mode 100644
index 02e09c3..0000000
--- a/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.inf
+++ /dev/null
@@ -1,56 +0,0 @@
-/** @file
-
-  Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-[Defines]
-  INF_VERSION                     = 0x00010005
-  BASE_NAME                       = BeagleBoardPciEmulation
-  FILE_GUID                       = feaa2e2b-53ac-4d5e-ae10-1efd5da4a2ba
-  MODULE_TYPE                     = DXE_DRIVER
-  VERSION_STRING                  = 1.0
-
-  ENTRY_POINT                     = PciEmulationEntryPoint
-
-[Sources.common]
-  PciRootBridgeIo.c
-  PciEmulation.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  IntelFrameworkPkg/IntelFrameworkPkg.dec
-  ArmPkg/ArmPkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  BaseLib
-  DxeServicesTableLib
-  UefiLib
-  UefiBootServicesTableLib
-  UefiDriverEntryPoint
-  UefiRuntimeServicesTableLib
-  IoLib
-  OmapDmaLib
-  DmaLib
-
-[Protocols]
-  gEfiPciRootBridgeIoProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEfiPciHostBridgeResourceAllocationProtocolGuid
-  gEfiPciIoProtocolGuid
-  gEmbeddedExternalDeviceProtocolGuid
-
-[Depex]
-  gEfiMetronomeArchProtocolGuid AND
-  gEmbeddedExternalDeviceProtocolGuid
diff --git a/Chips/TexasInstruments/Omap35xx/PciEmulation/PciRootBridgeIo.c b/Chips/TexasInstruments/Omap35xx/PciEmulation/PciRootBridgeIo.c
deleted file mode 100644
index e8635ed..0000000
--- a/Chips/TexasInstruments/Omap35xx/PciEmulation/PciRootBridgeIo.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "PciEmulation.h"
-
-BOOLEAN
-PciRootBridgeMemAddressValid (
-  IN PCI_ROOT_BRIDGE  *Private,
-  IN UINT64           Address
-  )
-{
-  if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {
-    return TRUE;
-  }
-
-  return FALSE;
-}
-
-
-EFI_STATUS
-PciRootBridgeIoMemRW (
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN  UINTN                                  Count,
-  IN  BOOLEAN                                InStrideFlag,
-  IN  PTR                                    In,
-  IN  BOOLEAN                                OutStrideFlag,
-  OUT PTR                                    Out
-  )
-{
-  UINTN  Stride;
-  UINTN  InStride;
-  UINTN  OutStride;
-
-
-  Width     = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
-  Stride    = (UINTN)1 << Width;
-  InStride  = InStrideFlag  ? Stride : 0;
-  OutStride = OutStrideFlag ? Stride : 0;
-
-  //
-  // Loop for each iteration and move the data
-  //
-  switch (Width) {
-  case EfiPciWidthUint8:
-    for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
-      *In.ui8 = *Out.ui8;
-    }
-    break;
-  case EfiPciWidthUint16:
-    for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
-      *In.ui16 = *Out.ui16;
-    }
-    break;
-  case EfiPciWidthUint32:
-    for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
-      *In.ui32 = *Out.ui32;
-    }
-    break;
-  default:
-    return EFI_INVALID_PARAMETER;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-PciRootBridgeIoPciRW (
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN BOOLEAN                                Write,
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN UINT64                                 UserAddress,
-  IN UINTN                                  Count,
-  IN OUT VOID                               *UserBuffer
-  )
-{
-  return EFI_SUCCESS;
-}
-
-/**
-  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-
-  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-  @param  Width                 Signifies the width of the memory operations.
-  @param  Address               The base address of the memory operations.
-  @param  Count                 The number of memory operations to perform.
-  @param  Buffer                For read operations, the destination buffer to store the results. For write
-                                operations, the source buffer to write data from.
-
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-
-**/
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoMemRead (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 Address,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *Buffer
-  )
-{
-  PCI_ROOT_BRIDGE   *Private;
-  UINTN             AlignMask;
-  PTR               In;
-  PTR               Out;
-
-  if ( Buffer == NULL ) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
-
-  if (!PciRootBridgeMemAddressValid (Private, Address)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  AlignMask = (1 << (Width & 0x03)) - 1;
-  if (Address & AlignMask) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  In.buf  = Buffer;
-  Out.buf = (VOID *)(UINTN) Address;
-
-  switch (Width) {
-  case EfiPciWidthUint8:
-  case EfiPciWidthUint16:
-  case EfiPciWidthUint32:
-  case EfiPciWidthUint64:
-    return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
-
-  case EfiPciWidthFifoUint8:
-  case EfiPciWidthFifoUint16:
-  case EfiPciWidthFifoUint32:
-  case EfiPciWidthFifoUint64:
-    return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
-
-  case EfiPciWidthFillUint8:
-  case EfiPciWidthFillUint16:
-  case EfiPciWidthFillUint32:
-  case EfiPciWidthFillUint64:
-    return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
-
-  default:
-    break;
-  }
-
-  return EFI_INVALID_PARAMETER;
-}
-
-
-
-/**
-  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-
-  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-  @param  Width                 Signifies the width of the memory operations.
-  @param  Address               The base address of the memory operations.
-  @param  Count                 The number of memory operations to perform.
-  @param  Buffer                For read operations, the destination buffer to store the results. For write
-                                operations, the source buffer to write data from.
-
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-
-**/
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoMemWrite (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 Address,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *Buffer
-  )
-{
-  PCI_ROOT_BRIDGE *Private;
-  UINTN  AlignMask;
-  PTR    In;
-  PTR    Out;
-
-  if ( Buffer == NULL ) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
-
-  if (!PciRootBridgeMemAddressValid (Private, Address)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  AlignMask = (1 << (Width & 0x03)) - 1;
-  if (Address & AlignMask) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  In.buf  = (VOID *)(UINTN) Address;
-  Out.buf = Buffer;
-
-  switch (Width) {
-  case EfiPciWidthUint8:
-  case EfiPciWidthUint16:
-  case EfiPciWidthUint32:
-  case EfiPciWidthUint64:
-    return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
-
-  case EfiPciWidthFifoUint8:
-  case EfiPciWidthFifoUint16:
-  case EfiPciWidthFifoUint32:
-  case EfiPciWidthFifoUint64:
-    return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
-
-  case EfiPciWidthFillUint8:
-  case EfiPciWidthFillUint16:
-  case EfiPciWidthFillUint32:
-  case EfiPciWidthFillUint64:
-    return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
-
-  default:
-    break;
-  }
-
-  return EFI_INVALID_PARAMETER;
-}
-
-/**
-  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-
-  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-  @param  Width                 Signifies the width of the memory operations.
-  @param  Address               The base address of the memory operations.
-  @param  Count                 The number of memory operations to perform.
-  @param  Buffer                For read operations, the destination buffer to store the results. For write
-                                operations, the source buffer to write data from.
-
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-
-**/
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoPciRead (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 Address,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *Buffer
-  )
-{
-  if (Buffer == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
-}
-
-
-
-/**
-  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-
-  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-  @param  Width                 Signifies the width of the memory operations.
-  @param  Address               The base address of the memory operations.
-  @param  Count                 The number of memory operations to perform.
-  @param  Buffer                For read operations, the destination buffer to store the results. For write
-                                operations, the source buffer to write data from.
-
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-
-**/
-EFI_STATUS
-EFIAPI
-PciRootBridgeIoPciWrite (
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
-  IN     UINT64                                 Address,
-  IN     UINTN                                  Count,
-  IN OUT VOID                                   *Buffer
-  )
-{
-  if (Buffer == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
-}
-
-
diff --git a/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.c b/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.c
deleted file mode 100644
index f2f43e2..0000000
--- a/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Uefi.h>
-#include <Omap3530/Omap3530.h>
-
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Protocol/SmbusHc.h>
-
-#define MAX_RETRY  1000
-
-//
-// Internal Functions
-//
-STATIC
-EFI_STATUS
-WaitForBusBusy (
-  VOID
-  )
-{
-  UINTN Retry = 0;
-
-  while (++Retry < MAX_RETRY && (MmioRead16(I2C_STAT) & BB) == 0x1);
-
-  if (Retry == MAX_RETRY) {
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-PollForStatus(
-  UINT16 StatusBit
-  )
-{
-  UINTN Retry = 0;
-
-  while(Retry < MAX_RETRY) {
-    if (MmioRead16(I2C_STAT) & StatusBit) {
-      //Clear particular status bit from Status register.
-      MmioOr16(I2C_STAT, StatusBit);
-      break;
-    }
-    Retry++;
-  }
-
-  if (Retry == MAX_RETRY) {
-    return EFI_TIMEOUT;
-  }
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-ConfigureI2c (
-  VOID
-  )
-{
-  //Program prescaler to obtain 12-MHz clock
-  MmioWrite16(I2C_PSC, 0x0000);
-
-  //Program SCLL and SCLH
-  //NOTE: Following values are the register dump after U-Boot code executed.
-  //We need to figure out how its calculated based on the I2C functional clock and I2C_PSC.
-  MmioWrite16(I2C_SCLL, 0x0035);
-  MmioWrite16(I2C_SCLH, 0x0035);
-
-  //Take the I2C controller out of reset.
-  MmioOr16(I2C_CON, I2C_EN);
-
-  //Initialize the I2C controller.
-
-  //Set I2C controller in Master mode.
-  MmioOr16(I2C_CON, MST);
-
-  //Enable interrupts for receive/transmit mode.
-  MmioOr16(I2C_IE, (XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE));
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-I2CReadOneByte (
-  UINT8 *Data
-  )
-{
-  EFI_STATUS Status;
-
-  //I2C bus status checking
-  Status = WaitForBusBusy();
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  //Poll till Receive ready bit is set.
-  Status = PollForStatus(RRDY);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  *Data = MmioRead8(I2C_DATA);
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-I2CWriteOneByte (
-  UINT8 Data
-  )
-{
-  EFI_STATUS Status;
-
-  //I2C bus status checking
-  Status = WaitForBusBusy();
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  //Data transfer
-  //Poll till Transmit ready bit is set
-  Status = PollForStatus(XRDY);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  MmioWrite8(I2C_DATA, Data);
-
-  //Wait and check if the NACK is not set.
-  gBS->Stall(1000);
-  if (MmioRead16(I2C_STAT) & NACK) {
-    return EFI_DEVICE_ERROR;
-  }
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-SmbusBlockRead (
-  OUT UINT8       *Buffer,
-  IN  UINTN       Length
-  )
-{
-  UINTN      Index = 0;
-  EFI_STATUS Status = EFI_SUCCESS;
-
-  //Transfer configuration for receiving data.
-  MmioWrite16(I2C_CNT, Length);
-  //Need stop bit before sending data.
-  MmioWrite16(I2C_CON, (I2C_EN | MST | STP | STT));
-
-  while (Index < Length) {
-    //Read a byte
-    Status = I2CReadOneByte(&Buffer[Index++]);
-    if (EFI_ERROR(Status)) {
-      return Status;
-    }
-  }
-
-  //Transfer completion
-  Status = PollForStatus(ARDY);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-SmbusBlockWrite (
-  IN UINT8       *Buffer,
-  IN UINTN       Length
-  )
-{
-  UINTN      Index = 0;
-  EFI_STATUS Status = EFI_SUCCESS;
-
-  //Transfer configuration for transmitting data
-  MmioWrite16(I2C_CNT, Length);
-  MmioWrite16(I2C_CON, (I2C_EN | TRX | MST | STT | STP));
-
-  while (Index < Length) {
-    //Send a byte
-    Status = I2CWriteOneByte(Buffer[Index++]);
-    if (EFI_ERROR(Status)) {
-      return Status;
-    }
-  }
-
-  //Transfer completion
-  Status = PollForStatus(ARDY);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  return Status;
-}
-
-//
-// Public Functions.
-//
-EFI_STATUS
-EFIAPI
-SmbusExecute (
-  IN CONST EFI_SMBUS_HC_PROTOCOL    *This,
-  IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
-  IN CONST EFI_SMBUS_DEVICE_COMMAND Command,
-  IN CONST EFI_SMBUS_OPERATION      Operation,
-  IN CONST BOOLEAN                  PecCheck,
-  IN OUT   UINTN                    *Length,
-  IN OUT   VOID                     *Buffer
-  )
-{
-  UINT8      *ByteBuffer  = Buffer;
-  EFI_STATUS Status       = EFI_SUCCESS;
-  UINT8      SlaveAddr    = (UINT8)(SlaveAddress.SmbusDeviceAddress);
-
-  if (PecCheck) {
-    return EFI_UNSUPPORTED;
-  }
-
-  if ((Operation != EfiSmbusWriteBlock) && (Operation != EfiSmbusReadBlock)) {
-    return EFI_UNSUPPORTED;
-  }
-
-  //Set the Slave address.
-  MmioWrite16(I2C_SA, SlaveAddr);
-
-  if (Operation == EfiSmbusReadBlock) {
-    Status = SmbusBlockRead(ByteBuffer, *Length);
-  } else if (Operation == EfiSmbusWriteBlock) {
-    Status = SmbusBlockWrite(ByteBuffer, *Length);
-  }
-
-  return Status;
-}
-
-EFI_STATUS
-EFIAPI
-SmbusArpDevice (
-  IN CONST EFI_SMBUS_HC_PROTOCOL    *This,
-  IN       BOOLEAN                  ArpAll,
-  IN       EFI_SMBUS_UDID           *SmbusUdid OPTIONAL,
-  IN OUT   EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-
-EFI_STATUS
-EFIAPI
-SmbusGetArpMap (
-  IN CONST EFI_SMBUS_HC_PROTOCOL    *This,
-  IN OUT   UINTN                    *Length,
-  IN OUT   EFI_SMBUS_DEVICE_MAP     **SmbusDeviceMap
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-
-EFI_STATUS
-EFIAPI
-SmbusNotify (
-  IN CONST  EFI_SMBUS_HC_PROTOCOL     *This,
-  IN CONST  EFI_SMBUS_DEVICE_ADDRESS  SlaveAddress,
-  IN CONST  UINTN                     Data,
-  IN CONST  EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-EFI_SMBUS_HC_PROTOCOL SmbusProtocol =
-{
-  SmbusExecute,
-  SmbusArpDevice,
-  SmbusGetArpMap,
-  SmbusNotify
-};
-
-EFI_STATUS
-InitializeSmbus (
-    IN EFI_HANDLE       ImageHandle,
-    IN EFI_SYSTEM_TABLE *SystemTable
-    )
-{
-  EFI_HANDLE      Handle = NULL;
-  EFI_STATUS      Status;
-
-  //Configure I2C controller.
-  Status = ConfigureI2c();
-  if (EFI_ERROR(Status)) {
-    DEBUG ((EFI_D_ERROR, "InitializeI2c fails.\n"));
-    return Status;
-  }
-
-  // Install the SMBUS interface
-  Status = gBS->InstallMultipleProtocolInterfaces(&Handle, &gEfiSmbusHcProtocolGuid, &SmbusProtocol, NULL);
-  ASSERT_EFI_ERROR(Status);
-
-  return Status;
-}
-
diff --git a/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.inf b/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.inf
deleted file mode 100644
index a92474f..0000000
--- a/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.inf
+++ /dev/null
@@ -1,45 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = Smbus
-  FILE_GUID                      = d5125e0f-1226-444f-a218-0085996ed5da
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = InitializeSmbus
-
-[Sources.common]
-  Smbus.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  PcdLib
-  UefiLib
-  UefiDriverEntryPoint
-  MemoryAllocationLib
-  IoLib
-
-[Guids]
-
-[Protocols]
-  gEfiSmbusHcProtocolGuid
-
-[Pcd]
-
-[depex]
-  TRUE
diff --git a/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.c b/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.c
deleted file mode 100644
index 66f9d85..0000000
--- a/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Uefi.h>
-
-#include <TPS65950.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Protocol/EmbeddedExternalDevice.h>
-#include <Protocol/SmbusHc.h>
-
-EFI_SMBUS_HC_PROTOCOL *Smbus;
-
-EFI_STATUS
-Read (
-  IN  EMBEDDED_EXTERNAL_DEVICE    *This,
-  IN  UINTN                       Register,
-  IN  UINTN                       Length,
-  OUT VOID                        *Buffer
-  )
-{
-  EFI_STATUS               Status;
-  EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
-  UINT8                    DeviceRegister;
-  UINTN                    DeviceRegisterLength = 1;
-
-  SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register);
-  DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register);
-
-  //Write DeviceRegister.
-  Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceRegisterLength, &DeviceRegister);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  //Read Data
-  Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusReadBlock, FALSE, &Length, Buffer);
-  return Status;
-}
-
-EFI_STATUS
-Write (
-  IN EMBEDDED_EXTERNAL_DEVICE   *This,
-  IN UINTN                      Register,
-  IN UINTN                      Length,
-  IN VOID                       *Buffer
-  )
-{
-  EFI_STATUS               Status;
-  EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
-  UINT8                    DeviceRegister;
-  UINTN                    DeviceBufferLength = Length + 1;
-  UINT8                    *DeviceBuffer;
-
-  SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register);
-  DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register);
-
-  //Prepare buffer for writing
-  DeviceBuffer = (UINT8 *)AllocatePool(DeviceBufferLength);
-  if (DeviceBuffer == NULL) {
-    Status = EFI_OUT_OF_RESOURCES;
-    goto exit;
-  }
-
-  //Set Device register followed by data to write.
-  DeviceBuffer[0] = DeviceRegister;
-  CopyMem(&DeviceBuffer[1], Buffer, Length);
-
-  //Write Data
-  Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceBufferLength, DeviceBuffer);
-  if (EFI_ERROR(Status)) {
-    goto exit;
-  }
-
-exit:
-  if (DeviceBuffer) {
-    FreePool(DeviceBuffer);
-  }
-
-  return Status;
-}
-
-EMBEDDED_EXTERNAL_DEVICE ExternalDevice = {
-  Read,
-  Write
-};
-
-EFI_STATUS
-TPS65950Initialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS  Status;
-
-  Status = gBS->LocateProtocol(&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&Smbus);
-  ASSERT_EFI_ERROR(Status);
-
-  Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedExternalDeviceProtocolGuid, &ExternalDevice, NULL);
-  return Status;
-}
diff --git a/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.inf b/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.inf
deleted file mode 100644
index bd85155..0000000
--- a/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.inf
+++ /dev/null
@@ -1,48 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = TPS65950
-  FILE_GUID                      = 71fe861a-5450-48b6-bfb0-b93522616f99
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = TPS65950Initialize
-
-
-[Sources.common]
-  TPS65950.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  BaseMemoryLib
-  PcdLib
-  UefiLib
-  UefiDriverEntryPoint
-  MemoryAllocationLib
-
-[Guids]
-
-[Protocols]
-  gEfiSmbusHcProtocolGuid
-  gEmbeddedExternalDeviceProtocolGuid
-
-[Pcd]
-
-[depex]
-  gEfiSmbusHcProtocolGuid
diff --git a/Chips/TexasInstruments/Omap35xx/TimerDxe/Timer.c b/Chips/TexasInstruments/Omap35xx/TimerDxe/Timer.c
deleted file mode 100644
index 8b56d45..0000000
--- a/Chips/TexasInstruments/Omap35xx/TimerDxe/Timer.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/** @file
-  Template for Timer Architecture Protocol driver of the ARM flavor
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include <PiDxe.h>
-
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/OmapLib.h>
-
-#include <Protocol/Timer.h>
-#include <Protocol/HardwareInterrupt.h>
-
-#include <Omap3530/Omap3530.h>
-
-
-// The notification function to call on every timer interrupt.
-volatile EFI_TIMER_NOTIFY      mTimerNotifyFunction   = (EFI_TIMER_NOTIFY)NULL;
-
-
-// The current period of the timer interrupt
-volatile UINT64 mTimerPeriod = 0;
-
-// Cached copy of the Hardware Interrupt protocol instance
-EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
-
-// Cached registers
-volatile UINT32 TISR;
-volatile UINT32 TCLR;
-volatile UINT32 TLDR;
-volatile UINT32 TCRR;
-volatile UINT32 TIER;
-
-// Cached interrupt vector
-volatile UINTN  gVector;
-
-
-/**
-
-  C Interrupt Handler calledin the interrupt context when Source interrupt is active.
-
-
-  @param Source         Source of the interrupt. Hardware routing off a specific platform defines
-                        what source means.
-
-  @param SystemContext  Pointer to system register context. Mostly used by debuggers and will
-                        update the system context after the return from the interrupt if
-                        modified. Don't change these values unless you know what you are doing
-
-**/
-VOID
-EFIAPI
-TimerInterruptHandler (
-  IN  HARDWARE_INTERRUPT_SOURCE   Source,
-  IN  EFI_SYSTEM_CONTEXT          SystemContext
-  )
-{
-  EFI_TPL OriginalTPL;
-
-
-
-  //
-  // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
-  // that raise to TPL_HIGH and then restore back to current level. Thus we need
-  // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
-  //
-  OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
-
-  if (mTimerNotifyFunction) {
-    mTimerNotifyFunction(mTimerPeriod);
-  }
-
-  // Clear all timer interrupts
-  MmioWrite32 (TISR, TISR_CLEAR_ALL);
-
-  // Poll interrupt status bits to ensure clearing
-  while ((MmioRead32 (TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
-
-  gBS->RestoreTPL (OriginalTPL);
-}
-
-/**
-  This function registers the handler NotifyFunction so it is called every time
-  the timer interrupt fires.  It also passes the amount of time since the last
-  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
-  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
-  returned.  If the CPU does not support registering a timer interrupt handler,
-  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a handler
-  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
-  If an attempt is made to unregister a handler when a handler is not registered,
-  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
-  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
-  is returned.
-
-  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
-  @param  NotifyFunction   The function to call when a timer interrupt fires. This
-                           function executes at TPL_HIGH_LEVEL. The DXE Core will
-                           register a handler for the timer interrupt, so it can know
-                           how much time has passed. This information is used to
-                           signal timer based events. NULL will unregister the handler.
-  @retval EFI_SUCCESS           The timer handler was registered.
-  @retval EFI_UNSUPPORTED       The platform does not support timer interrupts.
-  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a handler is already
-                                registered.
-  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
-                                previously registered.
-  @retval EFI_DEVICE_ERROR      The timer handler could not be registered.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverRegisterHandler (
-  IN EFI_TIMER_ARCH_PROTOCOL  *This,
-  IN EFI_TIMER_NOTIFY         NotifyFunction
-  )
-{
-  if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
-    return EFI_ALREADY_STARTED;
-  }
-
-  mTimerNotifyFunction = NotifyFunction;
-
-  return EFI_SUCCESS;
-}
-
-/**
-
-  This function adjusts the period of timer interrupts to the value specified
-  by TimerPeriod.  If the timer period is updated, then the selected timer
-  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If
-  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
-  If an error occurs while attempting to update the timer period, then the
-  timer hardware will be put back in its state prior to this call, and
-  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt
-  is disabled.  This is not the same as disabling the CPU's interrupts.
-  Instead, it must either turn off the timer hardware, or it must adjust the
-  interrupt controller so that a CPU interrupt is not generated when the timer
-  interrupt fires.
-
-  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
-  @param  TimerPeriod      The rate to program the timer interrupt in 100 nS units. If
-                           the timer hardware is not programmable, then EFI_UNSUPPORTED is
-                           returned. If the timer is programmable, then the timer period
-                           will be rounded up to the nearest timer period that is supported
-                           by the timer hardware. If TimerPeriod is set to 0, then the
-                           timer interrupts will be disabled.
-
-
-  @retval EFI_SUCCESS           The timer period was changed.
-  @retval EFI_UNSUPPORTED       The platform cannot change the period of the timer interrupt.
-  @retval EFI_DEVICE_ERROR      The timer period could not be changed due to a device error.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverSetTimerPeriod (
-  IN EFI_TIMER_ARCH_PROTOCOL  *This,
-  IN UINT64                   TimerPeriod
-  )
-{
-  EFI_STATUS  Status;
-  UINT64      TimerCount;
-  INT32       LoadValue;
-
-  if (TimerPeriod == 0) {
-    // Turn off GPTIMER3
-    MmioWrite32 (TCLR, TCLR_ST_OFF);
-
-    Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector);
-  } else {
-    // Calculate required timer count
-    TimerCount = DivU64x32(TimerPeriod * 100, PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds));
-
-    // Set GPTIMER3 Load register
-    LoadValue = (INT32) -TimerCount;
-    MmioWrite32 (TLDR, LoadValue);
-    MmioWrite32 (TCRR, LoadValue);
-
-    // Enable Overflow interrupt
-    MmioWrite32 (TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
-
-    // Turn on GPTIMER3, it will reload at overflow
-    MmioWrite32 (TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
-
-    Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector);
-  }
-
-  //
-  // Save the new timer period
-  //
-  mTimerPeriod = TimerPeriod;
-  return Status;
-}
-
-
-/**
-  This function retrieves the period of timer interrupts in 100 ns units,
-  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod
-  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is
-  returned, then the timer is currently disabled.
-
-  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
-  @param  TimerPeriod      A pointer to the timer period to retrieve in 100 ns units. If
-                           0 is returned, then the timer is currently disabled.
-
-
-  @retval EFI_SUCCESS           The timer period was returned in TimerPeriod.
-  @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverGetTimerPeriod (
-  IN EFI_TIMER_ARCH_PROTOCOL   *This,
-  OUT UINT64                   *TimerPeriod
-  )
-{
-  if (TimerPeriod == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  *TimerPeriod = mTimerPeriod;
-  return EFI_SUCCESS;
-}
-
-/**
-  This function generates a soft timer interrupt. If the platform does not support soft
-  timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
-  If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
-  service, then a soft timer interrupt will be generated. If the timer interrupt is
-  enabled when this service is called, then the registered handler will be invoked. The
-  registered handler should not be able to distinguish a hardware-generated timer
-  interrupt from a software-generated timer interrupt.
-
-  @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
-
-  @retval EFI_SUCCESS           The soft timer interrupt was generated.
-  @retval EFI_UNSUPPORTED       The platform does not support the generation of soft timer interrupts.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverGenerateSoftInterrupt (
-  IN EFI_TIMER_ARCH_PROTOCOL  *This
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-
-/**
-  Interface stucture for the Timer Architectural Protocol.
-
-  @par Protocol Description:
-  This protocol provides the services to initialize a periodic timer
-  interrupt, and to register a handler that is called each time the timer
-  interrupt fires.  It may also provide a service to adjust the rate of the
-  periodic timer interrupt.  When a timer interrupt occurs, the handler is
-  passed the amount of time that has passed since the previous timer
-  interrupt.
-
-  @param RegisterHandler
-  Registers a handler that will be called each time the
-  timer interrupt fires.  TimerPeriod defines the minimum
-  time between timer interrupts, so TimerPeriod will also
-  be the minimum time between calls to the registered
-  handler.
-
-  @param SetTimerPeriod
-  Sets the period of the timer interrupt in 100 nS units.
-  This function is optional, and may return EFI_UNSUPPORTED.
-  If this function is supported, then the timer period will
-  be rounded up to the nearest supported timer period.
-
-
-  @param GetTimerPeriod
-  Retrieves the period of the timer interrupt in 100 nS units.
-
-  @param GenerateSoftInterrupt
-  Generates a soft timer interrupt that simulates the firing of
-  the timer interrupt. This service can be used to invoke the   registered handler if the timer interrupt has been masked for
-  a period of time.
-
-**/
-EFI_TIMER_ARCH_PROTOCOL   gTimer = {
-  TimerDriverRegisterHandler,
-  TimerDriverSetTimerPeriod,
-  TimerDriverGetTimerPeriod,
-  TimerDriverGenerateSoftInterrupt
-};
-
-
-/**
-  Initialize the state information for the Timer Architectural Protocol and
-  the Timer Debug support protocol that allows the debugger to break into a
-  running program.
-
-  @param  ImageHandle   of the loaded driver
-  @param  SystemTable   Pointer to the System Table
-
-  @retval EFI_SUCCESS           Protocol registered
-  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
-  @retval EFI_DEVICE_ERROR      Hardware problems
-
-**/
-EFI_STATUS
-EFIAPI
-TimerInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_HANDLE  Handle = NULL;
-  EFI_STATUS  Status;
-  UINT32      TimerBaseAddress;
-
-  // Find the interrupt controller protocol.  ASSERT if not found.
-  Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
-  ASSERT_EFI_ERROR (Status);
-
-  // Set up the timer registers
-  TimerBaseAddress = TimerBase (FixedPcdGet32(PcdOmap35xxArchTimer));
-  TISR = TimerBaseAddress + GPTIMER_TISR;
-  TCLR = TimerBaseAddress + GPTIMER_TCLR;
-  TLDR = TimerBaseAddress + GPTIMER_TLDR;
-  TCRR = TimerBaseAddress + GPTIMER_TCRR;
-  TIER = TimerBaseAddress + GPTIMER_TIER;
-
-  // Disable the timer
-  Status = TimerDriverSetTimerPeriod (&gTimer, 0);
-  ASSERT_EFI_ERROR (Status);
-
-  // Install interrupt handler
-  gVector = InterruptVectorForTimer (FixedPcdGet32(PcdOmap35xxArchTimer));
-  Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler);
-  ASSERT_EFI_ERROR (Status);
-
-  // Turn on the functional clock for Timer
-  MmioOr32 (CM_FCLKEN_PER, CM_FCLKEN_PER_EN_GPT3_ENABLE);
-
-  // Set up default timer
-  Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
-  ASSERT_EFI_ERROR (Status);
-
-  // Install the Timer Architectural Protocol onto a new handle
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &Handle,
-                  &gEfiTimerArchProtocolGuid,      &gTimer,
-                  NULL
-                  );
-  ASSERT_EFI_ERROR(Status);
-
-  return Status;
-}
-
diff --git a/Chips/TexasInstruments/Omap35xx/TimerDxe/TimerDxe.inf b/Chips/TexasInstruments/Omap35xx/TimerDxe/TimerDxe.inf
deleted file mode 100644
index 6344a1d..0000000
--- a/Chips/TexasInstruments/Omap35xx/TimerDxe/TimerDxe.inf
+++ /dev/null
@@ -1,57 +0,0 @@
-#/** @file
-#
-#    Component description file for Timer module
-#
-#  Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardTimerDxe
-  FILE_GUID                      = 6ddbf08b-cfc9-43cc-9e81-0784ba312ca0
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = TimerInitialize
-
-[Sources.common]
-  Timer.c
-
-[Packages]
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  ArmPkg/ArmPkg.dec
-
-[LibraryClasses]
-  BaseLib
-  UefiRuntimeServicesTableLib
-  UefiLib
-  UefiBootServicesTableLib
-  BaseMemoryLib
-  DebugLib
-  UefiDriverEntryPoint
-  IoLib
-  OmapLib
-
-[Guids]
-
-[Protocols]
-  gEfiTimerArchProtocolGuid
-  gHardwareInterruptProtocolGuid
-
-[Pcd.common]
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer
-
-[Depex]
-  gHardwareInterruptProtocolGuid
diff --git a/Documentation/Marvell/Drivers/EepromDriver.txt b/Documentation/Marvell/Drivers/EepromDriver.txt
new file mode 100644
index 0000000..e2da35f
--- /dev/null
+++ b/Documentation/Marvell/Drivers/EepromDriver.txt
@@ -0,0 +1,96 @@
+1. Introduction
+---------------
+**MvEeprom** driver creates MARVELL_EEPROM_PROTOCOL, which
++is used for managing eeprom.
+
+2. MvEeprom driver design
+-------------------------
+Every I2C device driver should implement EFI_DRIVER_BINDING_PROTOCOL and
+consume EFI_I2C_IO_PROTOCOL for transactions on I2C bus. MvEeprom driver
+additionally implements MARVELL_EEPROM_PROTOCOL.
+
+  2.1 EFI_DRIVER_BINDING_PROTOCOL
+  -------------------------------
+  Driver Binding protocol is extensively covered in UEFI documentation, as
+  it is not specific to I2C stack. The only difference is that Supported()
+  function should check if EFI_I2C_IO_PROTOCOL provides valid EFI_GUID and
+  DeviceIndex values.
+  Excerpt from MvEepromSupported():
+
+    Status = gBS->OpenProtocol (
+                    ControllerHandle,
+                    &gEfiI2cIoProtocolGuid,
+                    (VOID **) &TmpI2cIo,
+                    gImageHandle,
+                    ControllerHandle,
+                    EFI_OPEN_PROTOCOL_BY_DRIVER
+                    );
+    if (EFI_ERROR(Status)) {
+      return EFI_UNSUPPORTED;
+    }
+
+    /* get EEPROM devices' addresses from PCD */
+    EepromAddresses = PcdGetPtr (PcdEepromI2cAddresses);
+    if (EepromAddresses == 0) {
+      Status = EFI_UNSUPPORTED;
+      goto out;
+    }
+
+    Status = EFI_UNSUPPORTED;
+    for (i = 0; EepromAddresses[i] != '\0'; i++) {
+      /* I2C guid must fit and valid DeviceIndex must be provided */
+      if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) &&
+          TmpI2cIo->DeviceIndex == EepromAddresses[i]) {
+        DEBUG((DEBUG_INFO, "A8kEepromSupported: attached to EEPROM device\n"));
+        Status = EFI_SUCCESS;
+        break;
+      }
+    }
+
+  2.2 EFI_I2C_IO_PROTOCOL
+  -----------------------
+  This protocol is provided by generic I2C stack. Multiple drivers can use IO
+  protocol at once, as queueing is implemented.
+
+  QueueRequest is a routine that queues an I2C transaction to the I2C
+  controller for execution on the I2C bus.
+
+  2.3 MARVELL_EEPROM_PROTOCOL
+  -----------------------
+    typedef struct _MARVELL_EEPROM_PROTOCOL MARVELL_EEPROM_PROTOCOL;
+
+    #define EEPROM_READ   0x1
+    #define EEPROM_WRITE  0x0
+    typedef
+    EFI_STATUS
+    (EFIAPI *EFI_EEPROM_TRANSFER) (
+      IN CONST MARVELL_EEPROM_PROTOCOL  *This,
+      IN UINT16                     Address,
+      IN UINT32                     Length,
+      IN UINT8                      *Buffer,
+      IN UINT8                      Operation
+      );
+
+    struct _MARVELL_EEPROM_PROTOCOL {
+      EFI_EEPROM_TRANSFER Transfer;
+      UINT8 Identifier;
+    };
+
+3. Adding new I2C slave device drivers
+--------------------------------------
+In order to support I2C slave device other than EEPROM, new driver should
+be created. Required steps follow.
+
+  1. Create driver directory (OpenPlatformPkg/Drivers/I2c/Devices/...).
+  2. Create stubs of .inf and .c files (MvEeprom files are a reference),
+     include .inf file in platform .dsc and .fdf files.
+  3. Implement EFI_DRIVER_BINDING_PROTOCOL - Start(), Stop(), Supported()
+     functions' implementation is a must. EFI_DRIVER_BINDING_PROTOCOL
+     should be installed at driver's entry point.
+  4. Add I2C address of device to PcdI2cSlaveAddresses in .dsc file.
+  5. Test available EFI_I2C_IO_PROTOCOLs in Supported() - find instance
+     with valid GUID and DeviceIndex (I2C slave address).
+  6. Open EFI_I2C_IO_PROTOCOL for usage in Start(). After that, QueueRequest
+     function should be available.
+  7. Implement core functionality of driver (using QueueRequest to access I2C).
+  8. (not mandatory) Produce/consume additional protocols.
diff --git a/Documentation/Marvell/Drivers/I2cDriver.txt b/Documentation/Marvell/Drivers/I2cDriver.txt
new file mode 100644
index 0000000..2f890de
--- /dev/null
+++ b/Documentation/Marvell/Drivers/I2cDriver.txt
@@ -0,0 +1,64 @@
+1. Introduction
+---------------
+**MvI2cDxe** is a driver supporting I2C controller on Marvell SOCs boards.
+It is connected through protocols to generic UEFI I2C stack, which exposes
+IO functionality to drivers of specific devices on I2C bus.
+
+2. MvI2cDxe driver design
+--------------------------
+MvI2cDxe produces several protocols from generic I2C stack:
+ - EFI_I2C_MASTER_PROTOCOL,
+ - EFI_I2C_ENUMERATE_PROTOCOL,
+ - EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
+ - general-purpose EFI_DRIVER_BINDING_PROTOCOL.
+
+  2.1 EFI_I2C_MASTER_PROTOCOL
+  ---------------------------
+  This is the most important protocol produced by MvI2cDxe. Following functions
+  are implemented:
+
+      ///
+      /// Reset the I2C host controller.
+      ///
+      EFI_I2C_MASTER_PROTOCOL_RESET             Reset;
+
+      ///
+      /// Start an I2C transaction in master mode on the host controller.
+      ///
+      EFI_I2C_MASTER_PROTOCOL_START_REQUEST     StartRequest;
+
+    StartRequest and Reset functions are used by I2cHost.
+    These should **not** be used by I2C device drivers - required
+    synchronization is not provided. Instead, members of EFI_I2C_IO_PROTOCOL
+    should be used.
+
+  2.2 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
+  -------------------------------------------------
+  The only function exposed via this protocol is MvI2cEnableConf. It is
+  required by I2C stack in order to allow changing I2C bus configuration from
+  device drivers.
+
+  2.3 EFI_I2C_ENUMERATE_PROTOCOL
+  ------------------------------
+  Provides Enumerate function, which is used by I2cBus code as an iterator over
+  devices on I2C bus.
+
+    typedef
+    EFI_STATUS
+    (EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE) (
+      IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This,
+      IN OUT CONST EFI_I2C_DEVICE         **Device
+    );
+
+    ///
+    /// Traverse the set of I2C devices on an I2C bus.  This routine
+    /// returns the next I2C device on an I2C bus.
+    ///
+    EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE         Enumerate;
+
+  MvI2cDevice creates EFI_I2C_DEVICE structure for every device on the bus.
+  Due to the fact that hardware-based I2C enumeration isn't safe, information
+  about attached devices should be provided through PCDs. After EFI_I2C_DEVICE
+  structure is created and filled properly, it is returned to I2cBus. It is
+  followed by attachment of I2C device driver.
+
diff --git a/Documentation/Marvell/Drivers/SpiDriver.txt b/Documentation/Marvell/Drivers/SpiDriver.txt
new file mode 100644
index 0000000..42b5e3c
--- /dev/null
+++ b/Documentation/Marvell/Drivers/SpiDriver.txt
@@ -0,0 +1,116 @@
+1. Introduction
+---------------
+**SpiDxe** driver implements MARVELL_SPI_MASTER_PROTOCOL in order to manage SPI
+controller on Marvell A8k boards. It exposes below functionalities:
+ - create and setup SPI slaves
+ - raw transfer over SPI bus
+
+2. SpiDxe driver design
+-----------------------
+
+  2.1 MARVELL_SPI_MASTER_PROTOCOL
+  -----------------------
+  First member of SPI_MASTER protocol is Init function, implemented for SPI
+  master controller initialization.
+
+  ->Init()
+
+    //
+    //Initializes the host controller to execute SPI commands.
+    //
+
+    param[IN]   This Pointer to the MARVELL_SPI_MASTER_PROTOCOL instance
+
+    return      EFI_SUCCESS             Opcode initialization on the SPI host
+                                        controller completed.
+    return      EFI_ACCESS_DENIED       The SPI configuration interface is
+                                        locked.
+    return      EFI_OUT_OF_RESOURCES    Not enough resource available to
+                                        initialize the device.
+    return      EFI_DEVICE_ERROR        Device error, operation failed.
+
+  ********
+
+  SPI devices (slaves) do not support any kind of automatic discovery or
+  enumaration, so every device needs manual configuration, which may be done
+  with SetupDevice function.
+
+    ->SetupDevice()
+
+    //
+    //Allocate and zero all fields in the SPI_DEVICE struct. Set the chip
+    //select, max frequency and transfer mode supported by slave device.
+    //
+
+    param[IN]   Cs Chip select ID of the slave chip.
+    param[IN]   MaxFreq Maximum SCK rate in Hz.
+    param[IN]   Mode Clock polarity and clock phase.
+
+    return      *SPI_DEVICE   Pointer to new allocated struct SPI_DEVICE.
+    return      NULL          NULL pointer if any eroor occured.
+
+    ********
+
+  Developers have to destroy all created SPI device structs (with FreeDevice
+  function) in order to prevent from memory leak.
+
+    ->FreeDevice()
+
+    //
+    //Free any memory associated with a SPI device.
+    //
+
+    param[in]   SpiDev                  Pointer to the SPI_DEVICE struct.
+
+    return      EFI_SUCCESS             Memory fried succesfully.
+    return      EFI_DEVICE_ERROR        Device error, operation failed.
+
+    ********
+
+  Transfer function allows write/read raw bytes over SPI bus.
+
+    ->Transfer()
+
+    //
+    //Perform transfer over SPI bus
+    //
+    param[in]     This                  Pointer to the MARVELL_SPI_MASTER_PROTOCOL
+                                        instance.
+    param[in]     Slave                 Pointer to the SPI_DEVICE struct.
+    param[in]     DataByteCount         Number of bytes in the data portion of
+                                        the SPI cycle.
+    param[in]     DataOut               Pointer to caller-allocated buffer
+                                        containing the data to send.
+    param[out]    DataIn                Pointer to caller-allocated buffer
+                                        where received data will be placed.
+    param[in]     Flag                  Flags which indicate state of CS line
+                                        during/after transfer (see file
+                                        Drivers/Spi/Devices/A8kSpiFlash.h)
+
+    return        EFI_SUCCESS           Memory fried succesfully.
+    return        EFI_DEVICE_ERROR      Device error, operation failed.
+
+    *********
+
+  When working with SPI devices it is often necessary to perform "command and
+  address" transactions. It may be done via ReadWrite function.
+
+    ->ReadWrite()
+
+    //
+    //Perform two steps transactions. First write Command, then read/write
+    //buffer
+    //
+
+    param[in]     This                  Pointer to the MARVELL_SPI_MASTER_PROTOCOL
+                                        instance.
+    param[in]     Slave                 Pointer to the SPI_DEVICE struct.
+    param[in]     Cmd                   Pointer to caller-allocated buffer
+                                        containing the command to send.
+    param[in]     CmdSize               Size of command (in bytes).
+    param[in]     DataOut               Pointer to caller-allocated buffer
+                                        containing the data to send.
+    param[out]    DataIn                Pointer to caller-allocated buffer
+                                        where received data will be placed.
+    param[in]     DataSize              Number of bytes in the data portion of
+                                        the SPI cycle.
diff --git a/Documentation/Marvell/PortingGuide/ComPhy.txt b/Documentation/Marvell/PortingGuide/ComPhy.txt
new file mode 100644
index 0000000..b5c4727
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/ComPhy.txt
@@ -0,0 +1,85 @@
+COMPHY configuration
+---------------------------
+In order to configure ComPhy library, following PCDs are available:
+
+  gMarvellTokenSpaceGuid.PcdComPhyChipCount
+
+Indicates how many different chips are placed on board. So far, up to 4 chips
+are supported.
+
+Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
+important, but configuration will be set for first PcdComPhyChipCount chips).
+
+Every chip has 8 ComPhy PCDs and three of them concern lanes settings for this
+chip. Below is example for the first chip (Chip0).
+
+General PCDs:
+
+  gMarvellTokenSpaceGuid.PcdChip0Compatible
+
+Unicode string indicating type of chip - currently supported is
+{ L"Cp110" }
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress
+
+Indicates COMPHY unit base address.
+
+  gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress
+
+Indicates Hpipe3 unit base address.
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount
+
+Indicates number of bits that are allocated for every MUX in the
+COMPHY-selector register.
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes
+
+Indicates maximum ComPhy lanes number.
+
+Next three PCDs are in unicode string format containing settings for up to 10
+lanes. Setting for each one is separated with semicolon. These PCDs form
+structure describing outputs of PHY integrated in simple cihp.
+Below is example for the first chip (Chip0).
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
+
+Unicode string indicating PHY types. Currently supported are:
+
+{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3",
+L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0",
+L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII",
+L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE",
+L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0",
+L"RXAUI1", L"KR" }
+
+Below documents describes some of above interfaces' types:
+
+SGMII, QSGMII, XAUI - IEEE 802.3
+KR - IEEE 802.3a
+RXAUI - RXAUI Interface and RXAUI Adapter Specification, Marvell
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
+
+Indicates PHY speeds in MHz. Currently supported are:
+
+{ 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 10310 }
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
+
+Indicates lane polarity invert.
+
+Example
+-------
+  #ComPhy
+  gMarvellTokenSpaceGuid.PcdComPhyChipCount|1
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000
+  gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4
+  gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110"
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;1250;5000;5000;5000"
+
diff --git a/Documentation/Marvell/PortingGuide/I2c.txt b/Documentation/Marvell/PortingGuide/I2c.txt
new file mode 100644
index 0000000..28ae1ef
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/I2c.txt
@@ -0,0 +1,20 @@
+1. Porting I2C driver to a new SOC
+----------------------------------
+In order to enable driver on a new platform, following steps need to be taken:
+ - add following line to .dsc file:
+   OpenPlatformPkg/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+ - add following line to .fdf file:
+   INF OpenPlatformPkg/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+ - add PCDs with relevant values to .dsc file:
+     gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
+   (addresses of I2C slave devices on bus)
+     gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+   (buses to which accoring slaves are attached)
+     gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+   (number of SoC's I2C buses)
+     gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100"
+   (base addresses of I2C controller buses)
+     gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000
+   (I2C host controller clock frequency)
+     gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+   (baud rate used in I2C transmission)
diff --git a/Documentation/Marvell/PortingGuide/Mdio.txt b/Documentation/Marvell/PortingGuide/Mdio.txt
new file mode 100644
index 0000000..c341d9e
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/Mdio.txt
@@ -0,0 +1,7 @@
+MDIO driver configuration
+-------------------------
+MDIO driver provides access to network PHYs' registers via MARVELL_MDIO_READ and
+MARVELL_MDIO_WRITE functions (MARVELL_MDIO_PROTOCOL). Following PCD is required:
+
+  gMarvellTokenSpaceGuid.PcdMdioBaseAddress
+  (base address of SMI management register)
diff --git a/Documentation/Marvell/PortingGuide/Mpp.txt b/Documentation/Marvell/PortingGuide/Mpp.txt
new file mode 100644
index 0000000..3e36b5f
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/Mpp.txt
@@ -0,0 +1,48 @@
+MPP configuration
+-----------------
+Multi-Purpose Ports (MPP) are configurable through platform PCDs.
+In order to set desired pin multiplexing, .dsc file needs to be modified.
+(OpenPlatformPkg/Platforms/Marvell/Armada/{platform_name}.dsc - please refer to
+Documentation/Build.txt for currently supported {platftorm_name} )
+Following PCDs are available:
+
+ gMarvellTokenSpaceGuid.PcdMppChipCount
+
+Indicates how many different chips are placed on board. So far up to 4 chips
+are supported.
+
+Every MPP PCD has <Num> part where
+ <Num> stands for chip ID (order is not important, but configuration will be
+ set for first PcdMppChipCount chips).
+
+Below is example for the first chip (Chip0).
+
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
+
+Indicates that register order is reversed. (Needs to be used only for AP806-Z1)
+
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
+
+This is base address for MPP configuration register.
+
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount
+
+Defines how many MPP pins are available.
+
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1
+ gMarvellTokenSpaceGuid.PcdChip0MppSel2
+
+This registers defines functions of 10 pins in ascending order.
+
+Examples
+--------
+#APN806-A0 MPP SET
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+Set pin 6 and 7 to 0xa function:
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
diff --git a/Documentation/Marvell/PortingGuide/PciEmulation.txt b/Documentation/Marvell/PortingGuide/PciEmulation.txt
new file mode 100644
index 0000000..ec1afbc
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/PciEmulation.txt
@@ -0,0 +1,31 @@
+PciEmulation configuration
+--------------------------
+Installation of various NonDiscoverable devices via PciEmulation driver is performed
+via set of PCDs. Following are available:
+
+ gMarvellTokenSpaceGuid.PcdPciEXhci
+
+Indicates, which Xhci devices are used.
+
+ gMarvellTokenSpaceGuid.PcdPciEAhci
+
+Indicates, which Ahci devices are used.
+
+ gMarvellTokenSpaceGuid.PcdPciESdhci
+
+Indicates, which Sdhci devices are used.
+
+All above PCD's correspond to hardware description in a dedicated structure:
+
+STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate
+
+in Platforms/Marvell/PciEmulation/PciEmulation.c file. It comprises device
+count, base addresses, register region size and DMA-coherency type.
+
+Examples
+--------
+Assuming we want to enable second XHCI port and one SDHCI port on Armada
+70x0 board, following needs to be declared:
+
+  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
+  gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
diff --git a/Documentation/Marvell/PortingGuide/Phy.txt b/Documentation/Marvell/PortingGuide/Phy.txt
new file mode 100644
index 0000000..69dae02
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/Phy.txt
@@ -0,0 +1,45 @@
+PHY driver configuration
+------------------------
+MvPhyDxe provides basic initialization and status routines for Marvell PHYs.
+Currently only 1512 series PHYs are supported. Following PCDs are required:
+
+  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
+  (list of values corresponding to PHY_CONNECTION enum)
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
+  (boolean - if true, driver waits for autonegotiation on startup)
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds
+  (list of values corresponding to MV_PHY_DEVICE_ID enum)
+
+PHY_CONNECTION enum type is defined as follows:
+
+  typedef enum {
+0    PHY_CONNECTION_RGMII,
+1    PHY_CONNECTION_RGMII_ID,
+2    PHY_CONNECTION_RGMII_TXID,
+3    PHY_CONNECTION_RGMII_RXID,
+4    PHY_CONNECTION_SGMII,
+5    PHY_CONNECTION_RTBI,
+6    PHY_CONNECTION_XAUI,
+7    PHY_CONNECTION_RXAUI
+  } PHY_CONNECTION;
+
+MV_PHY_DEVICE_ID:
+
+  typedef enum {
+0    MV_PHY_DEVICE_1512,
+  } MV_PHY_DEVICE_ID;
+
+It should be extended when adding support for other PHY
+models.
+
+Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be:
+
+  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 }
+
+with disabled autonegotiation:
+
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+assuming, that PHY models are 1512:
+
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
diff --git a/Documentation/Marvell/PortingGuide/Pp2.txt b/Documentation/Marvell/PortingGuide/Pp2.txt
new file mode 100644
index 0000000..c1554a6
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/Pp2.txt
@@ -0,0 +1,59 @@
+Pp2Dxe porting guide
+--------------------
+Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
+are required to operate:
+
+Number of ports/network interfaces:
+  gMarvellTokenSpaceGuid.PcdPp2NumPorts
+
+Addresses of PHY devices:
+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses
+
+Identificators of PP2 ports:
+  gMarvellTokenSpaceGuid.PcdPp2PortIds
+
+Indexes used in GOP operation:
+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes
+
+Set to 0x1 for always-up interface, 0x0 otherwise:
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
+
+Values corresponding to PHY_SPEED enum:
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
+
+PHY_SPEED (in Mbps) is defined as follows:
+  typedef enum {
+  0  NO_SPEED,
+  1  SPEED_10,
+  2  SPEED_100,
+  3  SPEED_1000,
+  4  SPEED_2500,
+  5  SPEED_10000
+  } PHY_SPEED;
+
+Base address of shared register space of PP2:
+  gMarvellTokenSpaceGuid.PcdPp2SharedAddress
+
+Spacing between consecutive GMAC register spaces:
+  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
+
+Base address of GMAC:
+  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
+
+Spacing between consecutive XLG register spaces:
+  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
+
+Base address of XLG:
+  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
+
+Base address of RFU1:
+  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
+
+Base address of SMI:
+  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
+
+TCLK frequency in Hz:
+  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
+
+GMAC and XLG addresses are computed as follows:
+  address = base_address + dev_size * gop_index
diff --git a/Documentation/Marvell/PortingGuide/Reset.txt b/Documentation/Marvell/PortingGuide/Reset.txt
new file mode 100644
index 0000000..30dec86
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/Reset.txt
@@ -0,0 +1,7 @@
+MarvellResetSystemLib configuration
+-----------------------------------
+This simple library allows to mask given bits in given reg at UEFI 'reset'
+command call. These variables are configurable through PCDs:
+
+  gMarvellTokenSpaceGuid.PcdResetRegAddress
+  gMarvellTokenSpaceGuid.PcdResetRegMask
diff --git a/Documentation/Marvell/PortingGuide/Spi.txt b/Documentation/Marvell/PortingGuide/Spi.txt
new file mode 100644
index 0000000..f1f36ad
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/Spi.txt
@@ -0,0 +1,15 @@
+Spi driver configuration
+------------------------
+Following PCDs are available for configuration of spi driver:
+
+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency
+
+Frequency (in Hz) of SPI clock
+
+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
+
+Max SCLK line frequency (in Hz) (max transfer frequency)
+
+ gMarvellTokenSpaceGuid.PcdSpiDefaultMode
+
+default SCLK mode (see SPI_MODE enum in file OpenPlatformPkg/Drivers/Spi/MvSpi.h)
diff --git a/Documentation/Marvell/PortingGuide/SpiFlash.txt b/Documentation/Marvell/PortingGuide/SpiFlash.txt
new file mode 100644
index 0000000..226db40
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/SpiFlash.txt
@@ -0,0 +1,23 @@
+SpiFlash driver configuration
+-----------------------------
+Folowing PCDs for spi flash driver configuration must be set properly:
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles
+
+Size of SPI flash address in bytes (3 or 4)
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize
+
+Size of minimal erase block in bytes
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashPageSize
+
+Size of SPI flash page
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashId
+
+Id of SPI flash
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd
+
+Spi flash polling flag
diff --git a/Documentation/Marvell/PortingGuide/Utmi.txt b/Documentation/Marvell/PortingGuide/Utmi.txt
new file mode 100644
index 0000000..cff4843
--- /dev/null
+++ b/Documentation/Marvell/PortingGuide/Utmi.txt
@@ -0,0 +1,35 @@
+UTMI PHY configuration
+----------------------
+In order to configure UTMI, following PCDs are available:
+
+  gMarvellTokenSpaceGuid.PcdUtmiPhyCount
+
+Indicates how many UTMI PHYs are available on platform.
+
+Next four PCDs are in unicode string format containing settings for all devices
+separated with semicolon.
+
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit
+
+Indicates base address of the UTMI unit.
+
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg
+
+Indicates address of USB Configuration register.
+
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg
+
+Indicates address of external UTMI configuration.
+
+  gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort
+
+Indicates type of the connected USB port.
+
+Example
+-------
+#UtmiPhy
+  gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000"
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420"
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444"
+  gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1"
diff --git a/Drivers/Block/DwUfsHcDxe/ComponentName.c b/Drivers/Block/DwUfsHcDxe/ComponentName.c
new file mode 100644
index 0000000..03c690c
--- /dev/null
+++ b/Drivers/Block/DwUfsHcDxe/ComponentName.c
@@ -0,0 +1,227 @@
+/** @file
+  UfsHcDxe driver produces EFI_UFS_HOST_CONTROLLER_PROTOCOL. The upper layer module
+  uses it to query the MMIO base address of the UFS host controller.
+
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DwUfsHcDxe.h"
+
+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gUfsHcComponentName = {
+  UfsHcComponentNameGetDriverName,
+  UfsHcComponentNameGetControllerName,
+  "eng"
+};
+
+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gUfsHcComponentName2 = {
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) UfsHcComponentNameGetDriverName,
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) UfsHcComponentNameGetControllerName,
+  "en"
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUfsHcDriverNameTable[] = {
+  {
+    "eng;en",
+    L"Universal Flash Storage (UFS) Mmio Host Controller Driver"
+  },
+  {
+    NULL,
+    NULL
+  }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mUfsHcControllerNameTable[] = {
+  {
+    "eng;en",
+    L"Universal Flash Storage (UFS) Mmio Host Controller"
+  },
+  {
+    NULL,
+    NULL
+  }
+};
+
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL       *This,
+  IN  CHAR8                             *Language,
+  OUT CHAR16                            **DriverName
+  )
+{
+  return LookupUnicodeString2 (
+           Language,
+           This->SupportedLanguages,
+           mUfsHcDriverNameTable,
+           DriverName,
+           (BOOLEAN)(This == &gUfsHcComponentName)
+           );
+}
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
+  IN  EFI_HANDLE                                      ControllerHandle,
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
+  IN  CHAR8                                           *Language,
+  OUT CHAR16                                          **ControllerName
+  )
+{
+  EFI_STATUS                    Status;
+
+  if (Language == NULL || ControllerName == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // This is a device driver, so ChildHandle must be NULL.
+  //
+  if (ChildHandle != NULL) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Make sure this driver is currently managing Controller Handle
+  //
+  Status = EfiTestManagedDevice (
+             ControllerHandle,
+             gUfsHcDriverBinding.DriverBindingHandle,
+             &gEfiPciIoProtocolGuid
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return LookupUnicodeString2 (
+           Language,
+           This->SupportedLanguages,
+           mUfsHcControllerNameTable,
+           ControllerName,
+           (BOOLEAN)(This == &gUfsHcComponentName)
+           );
+
+}
diff --git a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c
new file mode 100644
index 0000000..562218e
--- /dev/null
+++ b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c
@@ -0,0 +1,1034 @@
+/** @file
+  UfsHcDxe driver is used to provide platform-dependent info, mainly UFS host controller
+  MMIO base, to upper layer UFS drivers.
+
+  Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DwUfsHcDxe.h"
+
+#include <IndustryStandard/Pci.h>
+
+#include <Protocol/PciIo.h>
+
+//
+// Ufs Host Controller Driver Binding Protocol Instance
+//
+EFI_DRIVER_BINDING_PROTOCOL gUfsHcDriverBinding = {
+  UfsHcDriverBindingSupported,
+  UfsHcDriverBindingStart,
+  UfsHcDriverBindingStop,
+  0x10,
+  NULL,
+  NULL
+};
+
+//
+// Template for Ufs host controller private data.
+//
+UFS_HOST_CONTROLLER_PRIVATE_DATA gUfsHcTemplate = {
+  UFS_HC_PRIVATE_DATA_SIGNATURE,  // Signature
+  NULL,                           // Handle
+  {                               // UfsHcProtocol
+    UfsHcGetMmioBar,
+    UfsHcAllocateBuffer,
+    UfsHcFreeBuffer,
+    UfsHcMap,
+    UfsHcUnmap,
+    UfsHcFlush,
+    UfsHcMmioRead,
+    UfsHcMmioWrite,
+    UfsHcPhyInit,
+    UfsHcPhySetPowerMode,
+  },
+  0                               // RegBase
+};
+
+STATIC
+EFI_STATUS
+DwUfsDmeSet (
+  IN  UINTN         RegBase,
+  IN  UINT16        Attr,
+  IN  UINT16        Index,
+  IN  UINT32        Value
+  )
+{
+  UINT32            Data;
+
+  Data = MmioRead32 (RegBase + UFS_HC_STATUS_OFFSET);
+  if ((Data & UFS_HC_HCS_UCRDY) == 0) {
+    return EFI_NOT_READY;
+  }
+  MmioWrite32 (RegBase + UFS_HC_IS_OFFSET, ~0);
+  MmioWrite32 (RegBase + UFS_HC_UCMD_ARG1_OFFSET, (Attr << 16) | Index);
+  MmioWrite32 (RegBase + UFS_HC_UCMD_ARG2_OFFSET, 0);
+  MmioWrite32 (RegBase + UFS_HC_UCMD_ARG3_OFFSET, Value);
+  MmioWrite32 (RegBase + UFS_HC_UIC_CMD_OFFSET, UFS_UIC_DME_SET);
+  do {
+    Data = MmioRead32 (RegBase + UFS_HC_IS_OFFSET);
+    if (Data & UFS_HC_IS_UE) {
+      return EFI_DEVICE_ERROR;
+    }
+  } while ((Data & UFS_HC_IS_UCCS) == 0);
+  MmioWrite32 (RegBase + UFS_HC_IS_OFFSET, UFS_HC_IS_UCCS);
+  Data = MmioRead32 (RegBase + UFS_HC_UCMD_ARG2_OFFSET);
+  if (Data) {
+    return EFI_DEVICE_ERROR;
+  }
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+DwUfsDmeGet (
+  IN  UINTN         RegBase,
+  IN  UINT16        Attr,
+  IN  UINT16        Index,
+  OUT UINT32        *Value
+  )
+{
+  UINT32            Data;
+
+  Data = MmioRead32 (RegBase + UFS_HC_STATUS_OFFSET);
+  if ((Data & UFS_HC_HCS_UCRDY) == 0) {
+    return EFI_NOT_READY;
+  }
+  MmioWrite32 (RegBase + UFS_HC_IS_OFFSET, ~0);
+  MmioWrite32 (RegBase + UFS_HC_UCMD_ARG1_OFFSET, (Attr << 16) | Index);
+  MmioWrite32 (RegBase + UFS_HC_UCMD_ARG2_OFFSET, 0);
+  MmioWrite32 (RegBase + UFS_HC_UCMD_ARG3_OFFSET, 0);
+  MmioWrite32 (RegBase + UFS_HC_UIC_CMD_OFFSET, UFS_UIC_DME_GET);
+  do {
+    Data = MmioRead32 (RegBase + UFS_HC_IS_OFFSET);
+    if (Data & UFS_HC_IS_UE) {
+      return EFI_DEVICE_ERROR;
+    }
+  } while ((Data & UFS_HC_IS_UCCS) == 0);
+  MmioWrite32 (RegBase + UFS_HC_IS_OFFSET, UFS_HC_IS_UCCS);
+  Data = MmioRead32 (RegBase + UFS_HC_UCMD_ARG2_OFFSET);
+  if (Data) {
+    return EFI_DEVICE_ERROR;
+  }
+  *Value = MmioRead32 (RegBase + UFS_HC_UCMD_ARG3_OFFSET);
+  return EFI_SUCCESS;
+}
+
+/**
+  Get the MMIO base of the UFS host controller.
+
+  @param[in]   This             A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param[out]  MmioBar          The MMIO base address of UFS host controller.
+
+  @retval EFI_SUCCESS           The operation succeeds.
+  @retval others                The operation fails.
+**/
+EFI_STATUS
+EFIAPI
+UfsHcGetMmioBar (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+     OUT UINTN                              *MmioBar
+  )
+{
+  UFS_HOST_CONTROLLER_PRIVATE_DATA  *Private;
+
+  if ((This == NULL) || (MmioBar == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private  = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
+  *MmioBar = Private->RegBase;
+  return EFI_SUCCESS;
+}
+
+/**
+  Provides the UFS controller-specific addresses needed to access system memory.
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Operation             Indicates if the bus master is going to read or write to system memory.
+  @param  HostAddress           The system memory address to map to the UFS controller.
+  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
+                                that were mapped.
+  @param  DeviceAddress         The resulting map address for the bus master UFS controller to use to
+                                access the hosts HostAddress.
+  @param  Mapping               A resulting value to pass to Unmap().
+
+  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
+  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
+  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcMap (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL   *This,
+  IN     EDKII_UFS_HOST_CONTROLLER_OPERATION  Operation,
+  IN     VOID                                 *HostAddress,
+  IN OUT UINTN                                *NumberOfBytes,
+     OUT EFI_PHYSICAL_ADDRESS                 *DeviceAddress,
+     OUT VOID                                 **Mapping
+  )
+{
+  DMA_MAP_OPERATION   DmaOperation;
+
+  if ((This == NULL) || (HostAddress == NULL) || (NumberOfBytes == NULL) || (DeviceAddress == NULL) || (Mapping == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Operation == EdkiiUfsHcOperationBusMasterRead) {
+    DmaOperation = MapOperationBusMasterRead;
+  } else if (Operation == EdkiiUfsHcOperationBusMasterWrite) {
+    DmaOperation = MapOperationBusMasterWrite;
+  } else if (Operation == EdkiiUfsHcOperationBusMasterCommonBuffer) {
+    DmaOperation = MapOperationBusMasterCommonBuffer;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((*NumberOfBytes & (BIT0 | BIT1)) != 0) {
+    *NumberOfBytes += BIT0 | BIT1;
+    *NumberOfBytes &= ~(BIT0 | BIT1);
+  }
+
+  return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
+}
+
+/**
+  Completes the Map() operation and releases any corresponding resources.
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Mapping               The mapping value returned from Map().
+
+  @retval EFI_SUCCESS           The range was unmapped.
+  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcUnmap (
+  IN  EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+  IN  VOID                               *Mapping
+  )
+{
+  if ((This == NULL) || (Mapping == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return DmaUnmap (Mapping);
+}
+
+/**
+  Allocates pages that are suitable for an EfiUfsHcOperationBusMasterCommonBuffer
+  mapping.
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Type                  This parameter is not used and must be ignored.
+  @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
+                                EfiRuntimeServicesData.
+  @param  Pages                 The number of pages to allocate.
+  @param  HostAddress           A pointer to store the base system memory address of the
+                                allocated range.
+  @param  Attributes            The requested bit mask of attributes for the allocated range.
+
+  @retval EFI_SUCCESS           The requested memory pages were allocated.
+  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
+                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcAllocateBuffer (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+  IN     EFI_ALLOCATE_TYPE                  Type,
+  IN     EFI_MEMORY_TYPE                    MemoryType,
+  IN     UINTN                              Pages,
+     OUT VOID                               **HostAddress,
+  IN     UINT64                             Attributes
+  )
+{
+  if ((This == NULL) || (HostAddress == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
+}
+
+/**
+  Frees memory that was allocated with AllocateBuffer().
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Pages                 The number of pages to free.
+  @param  HostAddress           The base system memory address of the allocated range.
+
+  @retval EFI_SUCCESS           The requested memory pages were freed.
+  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
+                                was not allocated with AllocateBuffer().
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcFreeBuffer (
+  IN  EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+  IN  UINTN                              Pages,
+  IN  VOID                               *HostAddress
+  )
+{
+  if ((This == NULL) || (HostAddress == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return DmaFreeBuffer (Pages, HostAddress);
+}
+
+/**
+  Flushes all posted write transactions from the UFS bus to attached UFS device.
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+
+  @retval EFI_SUCCESS           The posted write transactions were flushed from the UFS bus
+                                to attached UFS device.
+  @retval EFI_DEVICE_ERROR      The posted write transactions were not flushed from the UFS
+                                bus to attached UFS device due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcFlush (
+  IN  EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
+
+  @param  This                  A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Width                 Signifies the width of the memory operations.
+  @param  Offset                The offset within the UFS Host Controller MMIO space to start the
+                                memory operation.
+  @param  Count                 The number of memory operations to perform.
+  @param  Buffer                For read operations, the destination buffer to store the results.
+                                For write operations, the source buffer to write data from.
+
+  @retval EFI_SUCCESS           The data was read from or written to the UFS host controller.
+  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
+                                valid for the UFS Host Controller memory space.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcMmioRead (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL        *This,
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                    Offset,
+  IN     UINTN                                     Count,
+  IN OUT VOID                                      *Buffer
+  )
+{
+  UFS_HOST_CONTROLLER_PRIVATE_DATA  *Private;
+  UINTN                             Index;
+
+  Private  = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
+
+  switch (Width) {
+  case EfiUfsHcWidthUint8:
+    for (Index = 0; Index < Count; Index++) {
+      *((UINT8 *)Buffer + Index) = MmioRead8 (Private->RegBase + Offset);
+    }
+    break;
+  case EfiUfsHcWidthUint16:
+    for (Index = 0; Index < Count; Index++) {
+      *((UINT16 *)Buffer + Index) = MmioRead16 (Private->RegBase + Offset);
+    }
+    break;
+  case EfiUfsHcWidthUint32:
+    for (Index = 0; Index < Count; Index++) {
+      *((UINT32 *)Buffer + Index) = MmioRead32 (Private->RegBase + Offset);
+    }
+    break;
+  case EfiUfsHcWidthUint64:
+    for (Index = 0; Index < Count; Index++) {
+      *((UINT64 *)Buffer + Index) = MmioRead64 (Private->RegBase + Offset);
+    }
+    break;
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
+
+  @param  This                  A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Width                 Signifies the width of the memory operations.
+  @param  Offset                The offset within the UFS Host Controller MMIO space to start the
+                                memory operation.
+  @param  Count                 The number of memory operations to perform.
+  @param  Buffer                For read operations, the destination buffer to store the results.
+                                For write operations, the source buffer to write data from.
+
+  @retval EFI_SUCCESS           The data was read from or written to the UFS host controller.
+  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
+                                valid for the UFS Host Controller memory space.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcMmioWrite (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL        *This,
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                    Offset,
+  IN     UINTN                                     Count,
+  IN OUT VOID                                      *Buffer
+  )
+{
+  UFS_HOST_CONTROLLER_PRIVATE_DATA  *Private;
+  EFI_STATUS                        Status = EFI_SUCCESS;
+  UINTN                             Index;
+
+  Private  = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
+
+  switch (Width) {
+  case EfiUfsHcWidthUint8:
+    for (Index = 0; Index < Count; Index++) {
+      Status = MmioWrite8 (Private->RegBase + Offset, *((UINT8 *)Buffer + Index));
+    }
+    break;
+  case EfiUfsHcWidthUint16:
+    for (Index = 0; Index < Count; Index++) {
+      Status = MmioWrite16 (Private->RegBase + Offset, *((UINT16 *)Buffer + Index));
+    }
+    break;
+  case EfiUfsHcWidthUint32:
+    for (Index = 0; Index < Count; Index++) {
+      Status = MmioWrite32 (Private->RegBase + Offset, *((UINT32 *)Buffer + Index));
+    }
+    break;
+  case EfiUfsHcWidthUint64:
+    for (Index = 0; Index < Count; Index++) {
+      Status = MmioWrite64 (Private->RegBase + Offset, *((UINT64 *)Buffer + Index));
+    }
+    break;
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+UfsHcPhyInit (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL        *This
+  )
+{
+  UFS_HOST_CONTROLLER_PRIVATE_DATA  *Private;
+  EFI_STATUS                        Status;
+  UINT32                            Data, Fsm0, Fsm1;
+
+  Private  = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
+  DwUfsDmeSet (Private->RegBase, 0xd0c1, 0, 1);
+  DwUfsDmeSet (Private->RegBase, 0xd0c1, 0, 1);
+  DwUfsDmeSet (Private->RegBase, 0x156a, 0, 2);
+  DwUfsDmeSet (Private->RegBase, 0x8114, 0, 1);
+  DwUfsDmeSet (Private->RegBase, 0x8121, 0, 0x2d);
+  DwUfsDmeSet (Private->RegBase, 0x8122, 0, 1);
+  DwUfsDmeSet (Private->RegBase, 0xd085, 0, 1);
+  DwUfsDmeSet (Private->RegBase, 0x800d, 4, 0x58);
+  DwUfsDmeSet (Private->RegBase, 0x800d, 5, 0x58);
+  DwUfsDmeSet (Private->RegBase, 0x800e, 4, 0xb);
+  DwUfsDmeSet (Private->RegBase, 0x800e, 5, 0xb);
+  DwUfsDmeSet (Private->RegBase, 0x8009, 4, 0x1);
+  DwUfsDmeSet (Private->RegBase, 0x8009, 5, 0x1);
+  DwUfsDmeSet (Private->RegBase, 0xd085, 0, 1);
+  DwUfsDmeSet (Private->RegBase, 0x8113, 0, 1);
+  DwUfsDmeSet (Private->RegBase, 0xd085, 0, 1);
+  DwUfsDmeSet (Private->RegBase, 0x0095, 4, 0x4a);
+  DwUfsDmeSet (Private->RegBase, 0x0095, 5, 0x4a);
+  DwUfsDmeSet (Private->RegBase, 0x0094, 4, 0x4a);
+  DwUfsDmeSet (Private->RegBase, 0x0094, 5, 0x4a);
+  DwUfsDmeSet (Private->RegBase, 0x008f, 4, 0x7);
+  DwUfsDmeSet (Private->RegBase, 0x008f, 5, 0x7);
+  DwUfsDmeSet (Private->RegBase, 0x000f, 0, 0x5);
+  DwUfsDmeSet (Private->RegBase, 0x000f, 1, 0x5);
+  DwUfsDmeSet (Private->RegBase, 0xd085, 0, 1);
+
+  Status = DwUfsDmeGet (Private->RegBase, 0xd0c1, 0, &Data);
+  ASSERT_EFI_ERROR (Status);
+  ASSERT (Data == 1);
+
+  DwUfsDmeSet (Private->RegBase, 0xd0c1, 0, 0);
+  for (;;) {
+    Status = DwUfsDmeGet (Private->RegBase, 0x0041, 0, &Fsm0);
+    ASSERT_EFI_ERROR (Status);
+    Status = DwUfsDmeGet (Private->RegBase, 0x0041, 1, &Fsm1);
+    ASSERT_EFI_ERROR (Status);
+    if ((Fsm0 == 1) && (Fsm1 == 1)) {
+      break;
+    }
+  }
+
+  MmioWrite32 (Private->RegBase + UFS_HC_HCLKDIV_OFFSET, 0xE4);
+  Data = MmioRead32 (Private->RegBase + UFS_HC_AHIT_OFFSET);
+  Data &= ~0x3FF;
+  MmioWrite32 (Private->RegBase + UFS_HC_AHIT_OFFSET, Data);
+
+  DwUfsDmeSet (Private->RegBase, 0x155e, 0, 0);
+  DwUfsDmeSet (Private->RegBase, 0xd0ab, 0, 0);
+
+  Status = DwUfsDmeGet (Private->RegBase, 0xd0ab, 0, &Data);
+  ASSERT_EFI_ERROR ((Status) && (Data == 0));
+
+  DwUfsDmeSet (Private->RegBase, 0x2044, 0, 0);
+  DwUfsDmeSet (Private->RegBase, 0x2045, 0, 0);
+  DwUfsDmeSet (Private->RegBase, 0x2040, 0, 9);
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+UfsHcPhySetPowerMode (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL        *This
+  )
+{
+  UFS_HOST_CONTROLLER_PRIVATE_DATA  *Private;
+  UINT32                            Data, TxLanes, RxLanes;
+
+  Private  = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This);
+  // PA_Tactive
+  DwUfsDmeGet (Private->RegBase, 0x15A8, 0, &Data);
+  if (Data < 7) {
+    DwUfsDmeSet (Private->RegBase, 0x15A8, 4, 7);
+  }
+  DwUfsDmeGet (Private->RegBase, 0x1561, 0, &TxLanes);
+  DwUfsDmeGet (Private->RegBase, 0x1581, 0, &RxLanes);
+
+  // PA TxSkip
+  DwUfsDmeSet (Private->RegBase, 0x155C, 0, 0);
+  // PA TxGear
+  DwUfsDmeSet (Private->RegBase, 0x1568, 0, 3);
+  // PA RxGear
+  DwUfsDmeSet (Private->RegBase, 0x1583, 0, 3);
+  // PA HSSeries
+  DwUfsDmeSet (Private->RegBase, 0x156A, 0, 2);
+  // PA TxTermination
+  DwUfsDmeSet (Private->RegBase, 0x1569, 0, 1);
+  // PA RxTermination
+  DwUfsDmeSet (Private->RegBase, 0x1584, 0, 1);
+  // PA Scrambling
+  DwUfsDmeSet (Private->RegBase, 0x1585, 0, 0);
+  // PA ActiveTxDataLines
+  DwUfsDmeSet (Private->RegBase, 0x1560, 0, TxLanes);
+  // PA ActiveRxDataLines
+  DwUfsDmeSet (Private->RegBase, 0x1580, 0, RxLanes);
+  // PA_PWRModeUserData0 = 8191
+  DwUfsDmeSet (Private->RegBase, 0x15B0, 0, 8191);
+  // PA_PWRModeUserData1 = 65535
+  DwUfsDmeSet (Private->RegBase, 0x15B1, 0, 65535);
+  // PA_PWRModeUserData2 = 32767
+  DwUfsDmeSet (Private->RegBase, 0x15B2, 0, 32767);
+  // DME_FC0ProtectionTimeOutVal = 8191
+  DwUfsDmeSet (Private->RegBase, 0xD041, 0, 8191);
+  // DME_TC0ReplayTimeOutVal = 65535
+  DwUfsDmeSet (Private->RegBase, 0xD042, 0, 65535);
+  // DME_AFC0ReqTimeOutVal = 32767
+  DwUfsDmeSet (Private->RegBase, 0xD043, 0, 32767);
+  // PA_PWRModeUserData3 = 8191
+  DwUfsDmeSet (Private->RegBase, 0x15B3, 0, 8191);
+  // PA_PWRModeUserData4 = 65535
+  DwUfsDmeSet (Private->RegBase, 0x15B4, 0, 65535);
+  // PA_PWRModeUserData5 = 32767
+  DwUfsDmeSet (Private->RegBase, 0x15B5, 0, 32767);
+  // DME_FC1ProtectionTimeOutVal = 8191
+  DwUfsDmeSet (Private->RegBase, 0xD044, 0, 8191);
+  // DME_TC1ReplayTimeOutVal = 65535
+  DwUfsDmeSet (Private->RegBase, 0xD045, 0, 65535);
+  // DME_AFC1ReqTimeOutVal = 32767
+  DwUfsDmeSet (Private->RegBase, 0xD046, 0, 32767);
+
+  DwUfsDmeSet (Private->RegBase, 0x1571, 0, 0x11);
+  do {
+    Data = MmioRead32(Private->RegBase + UFS_HC_IS_OFFSET);
+  } while ((Data & UFS_INT_UPMS) == 0);
+  MmioWrite32(Private->RegBase + UFS_HC_IS_OFFSET, UFS_INT_UPMS);
+  Data = MmioRead32(Private->RegBase + UFS_HC_STATUS_OFFSET);
+  if ((Data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL) {
+    DEBUG ((DEBUG_INFO, "ufs: change power mode success\n"));
+  } else {
+    DEBUG ((DEBUG_ERROR, "ufs: HCS.UPMCRS error, HCS:0x%x\n", Data));
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Tests to see if this driver supports a given controller. If a child device is provided,
+  it further tests to see if this driver supports creating a handle for the specified child device.
+
+  This function checks to see if the driver specified by This supports the device specified by
+  ControllerHandle. Drivers will typically use the device path attached to
+  ControllerHandle and/or the services from the bus I/O abstraction attached to
+  ControllerHandle to determine if the driver supports ControllerHandle. This function
+  may be called many times during platform initialization. In order to reduce boot times, the tests
+  performed by this function must be very small, and take as little time as possible to execute. This
+  function must not change the state of any hardware devices, and this function must be aware that the
+  device specified by ControllerHandle may already be managed by the same driver or a
+  different driver. This function must match its calls to AllocatePages() with FreePages(),
+  AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+  Since ControllerHandle may have been previously started by the same driver, if a protocol is
+  already in the opened state, then it must not be closed with CloseProtocol(). This is required
+  to guarantee the state of ControllerHandle is not modified by this function.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to test. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For bus drivers, if this parameter is not NULL, then
+                                   the bus driver must determine if the bus controller specified
+                                   by ControllerHandle and the child controller specified
+                                   by RemainingDevicePath are both supported by this
+                                   bus driver.
+
+  @retval EFI_SUCCESS              The device specified by ControllerHandle and
+                                   RemainingDevicePath is supported by the driver specified by This.
+  @retval EFI_ALREADY_STARTED      The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by the driver
+                                   specified by This.
+  @retval EFI_ACCESS_DENIED        The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by a different
+                                   driver or an application that requires exclusive access.
+                                   Currently not implemented.
+  @retval EFI_UNSUPPORTED          The device specified by ControllerHandle and
+                                   RemainingDevicePath is not supported by the driver specified by This.
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  )
+{
+  EFI_STATUS                Status;
+  BOOLEAN                   UfsHcFound;
+  EFI_DEVICE_PATH_PROTOCOL  *ParentDevicePath = NULL;
+  EFI_PCI_IO_PROTOCOL       *PciIo = NULL;
+  PCI_TYPE00                PciData;
+
+  ParentDevicePath = NULL;
+  UfsHcFound       = FALSE;
+
+  //
+  // UfsHcDxe is a device driver, and should ingore the
+  // "RemainingDevicePath" according to EFI spec
+  //
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiDevicePathProtocolGuid,
+                  (VOID *) &ParentDevicePath,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    //
+    // EFI_ALREADY_STARTED is also an error
+    //
+    return Status;
+  }
+  //
+  // Close the protocol because we don't use it here
+  //
+  gBS->CloseProtocol (
+        Controller,
+        &gEfiDevicePathProtocolGuid,
+        This->DriverBindingHandle,
+        Controller
+        );
+
+  //
+  // Now test the EfiPciIoProtocol
+  //
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiPciIoProtocolGuid,
+                  (VOID **) &PciIo,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Now further check the PCI header: Base class (offset 0x0B) and
+  // Sub Class (offset 0x0A). This controller should be an UFS controller
+  //
+  Status = PciIo->Pci.Read (
+                        PciIo,
+                        EfiPciIoWidthUint8,
+                        0,
+                        sizeof (PciData),
+                        &PciData
+                        );
+  if (EFI_ERROR (Status)) {
+    gBS->CloseProtocol (
+          Controller,
+          &gEfiPciIoProtocolGuid,
+          This->DriverBindingHandle,
+          Controller
+          );
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Since we already got the PciData, we can close protocol to avoid to carry it on for multiple exit points.
+  //
+  gBS->CloseProtocol (
+        Controller,
+        &gEfiPciIoProtocolGuid,
+        This->DriverBindingHandle,
+        Controller
+        );
+
+  //
+  // Examine UFS Host Controller PCI Configuration table fields
+  //
+  if (PciData.Hdr.ClassCode[2] == PCI_CLASS_MASS_STORAGE) {
+    if (PciData.Hdr.ClassCode[1] == 0x09 ) { //UFS Controller Subclass
+      UfsHcFound = TRUE;
+    }
+  }
+
+  if (!UfsHcFound) {
+    return EFI_UNSUPPORTED;
+  }
+
+  return Status;
+}
+
+/**
+  Starts a device controller or a bus controller.
+
+  The Start() function is designed to be invoked from the EFI boot service ConnectController().
+  As a result, much of the error checking on the parameters to Start() has been moved into this
+  common boot service. It is legal to call Start() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE.
+  2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
+     EFI_DEVICE_PATH_PROTOCOL.
+  3. Prior to calling Start(), the Supported() function for the driver specified by This must
+     have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to start. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For a bus driver, if this parameter is NULL, then handles
+                                   for all the children of Controller are created by this driver.
+                                   If this parameter is not NULL and the first Device Path Node is
+                                   not the End of Device Path Node, then only the handle for the
+                                   child device specified by the first Device Path Node of
+                                   RemainingDevicePath is created by this driver.
+                                   If the first Device Path Node of RemainingDevicePath is
+                                   the End of Device Path Node, no child handle is created by this
+                                   driver.
+
+  @retval EFI_SUCCESS              The device was started.
+  @retval EFI_DEVICE_ERROR         The device could not be started due to a device error.Currently not implemented.
+  @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+  @retval Others                   The driver failded to start the device.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  )
+{
+  EFI_STATUS                        Status;
+  EFI_PCI_IO_PROTOCOL               *PciIo;
+  UFS_HOST_CONTROLLER_PRIVATE_DATA  *Private;
+  UINT64                            Supports;
+  UINT8                             BarIndex;
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BarDesc;
+  UINT32                            BaseAddress;
+
+  PciIo    = NULL;
+  Private  = NULL;
+  Supports = 0;
+  BarDesc  = NULL;
+  BaseAddress = PcdGet32 (PcdDwUfsHcDxeBaseAddress);
+
+  //
+  // Now test and open the EfiPciIoProtocol
+  //
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiPciIoProtocolGuid,
+                  (VOID **) &PciIo,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  //
+  // Status == 0 - A normal execution flow, SUCCESS and the program proceeds.
+  // Status == ALREADY_STARTED - A non-zero Status code returned. It indicates
+  //           that the protocol has been opened and should be treated as a
+  //           normal condition and the program proceeds. The Protocol will not
+  //           opened 'again' by this call.
+  // Status != ALREADY_STARTED - Error status, terminate program execution
+  //
+  if (EFI_ERROR (Status)) {
+    //
+    // EFI_ALREADY_STARTED is also an error
+    //
+    return Status;
+  }
+
+  //BaseAddress = PcdGet32 (PcdDwUfsHcDxeBaseAddress);
+  Private = AllocateCopyPool (sizeof (UFS_HOST_CONTROLLER_PRIVATE_DATA), &gUfsHcTemplate);
+  if (Private == NULL) {
+    Status = EFI_OUT_OF_RESOURCES;
+    goto Done;
+  }
+
+  Private->RegBase = (UINTN)BaseAddress;
+  Private->PciIo = PciIo;
+
+  for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex++) {
+    Status = PciIo->GetBarAttributes (
+                      PciIo,
+                      BarIndex,
+                      NULL,
+                      (VOID**) &BarDesc
+                      );
+    if (Status == EFI_UNSUPPORTED) {
+      continue;
+    } else if (EFI_ERROR (Status)) {
+      goto Done;
+    }
+
+    if (BarDesc->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+      Private->BarIndex = BarIndex;
+      FreePool (BarDesc);
+      break;
+    }
+
+    FreePool (BarDesc);
+  }
+
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationGet,
+                    0,
+                    &Private->PciAttributes
+                    );
+
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationSupported,
+                    0,
+                    &Supports
+                    );
+
+  if (!EFI_ERROR (Status)) {
+    Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
+    Status    = PciIo->Attributes (
+                         PciIo,
+                         EfiPciIoAttributeOperationEnable,
+                         Supports,
+                         NULL
+                         );
+  } else {
+    goto Done;
+  }
+
+  ///
+  /// Install UFS_HOST_CONTROLLER protocol
+  ///
+  Status = gBS->InstallProtocolInterface (
+                  &Controller,
+                  &gEdkiiUfsHostControllerProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  (VOID*)&(Private->UfsHc)
+                  );
+
+Done:
+  if (EFI_ERROR (Status)) {
+    if ((Private != NULL) && (Private->PciAttributes != 0)) {
+      //
+      // Restore original PCI attributes
+      //
+      Status = PciIo->Attributes (
+                        PciIo,
+                        EfiPciIoAttributeOperationSet,
+                        Private->PciAttributes,
+                        NULL
+                        );
+      ASSERT_EFI_ERROR (Status);
+    }
+    gBS->CloseProtocol (
+          Controller,
+          &gEfiPciIoProtocolGuid,
+          This->DriverBindingHandle,
+          Controller
+          );
+    if (Private != NULL) {
+      FreePool (Private);
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Stops a device controller or a bus controller.
+
+  The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+  As a result, much of the error checking on the parameters to Stop() has been moved
+  into this common boot service. It is legal to call Stop() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
+     same driver's Start() function.
+  2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
+     EFI_HANDLE. In addition, all of these handles must have been created in this driver's
+     Start() function, and the Start() function must have called OpenProtocol() on
+     ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+  @param[in]  This              A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle  A handle to the device being stopped. The handle must
+                                support a bus specific I/O protocol for the driver
+                                to use to stop the device.
+  @param[in]  NumberOfChildren  The number of child device handles in ChildHandleBuffer.
+  @param[in]  ChildHandleBuffer An array of child handles to be freed. May be NULL
+                                if NumberOfChildren is 0.
+
+  @retval EFI_SUCCESS           The device was stopped.
+  @retval EFI_DEVICE_ERROR      The device could not be stopped due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN  EFI_HANDLE                      Controller,
+  IN  UINTN                           NumberOfChildren,
+  IN  EFI_HANDLE                      *ChildHandleBuffer
+  )
+{
+  EFI_STATUS                          Status;
+  UFS_HOST_CONTROLLER_PRIVATE_DATA    *Private;
+  EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHc;
+
+  ///
+  /// Get private data
+  ///
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEdkiiUfsHostControllerProtocolGuid,
+                  (VOID **) &UfsHc,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+
+  if (EFI_ERROR (Status)) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (UfsHc);
+
+  Status = gBS->UninstallProtocolInterface (
+                  Controller,
+                  &gEdkiiUfsHostControllerProtocolGuid,
+                  &(Private->UfsHc)
+                  );
+  if (!EFI_ERROR (Status)) {
+    //
+    // Restore original PCI attributes
+    //
+    Status = Private->PciIo->Attributes (
+                               Private->PciIo,
+                               EfiPciIoAttributeOperationSet,
+                               Private->PciAttributes,
+                               NULL
+                               );
+    ASSERT_EFI_ERROR (Status);
+
+    //
+    // Close protocols opened by UFS host controller driver
+    //
+    gBS->CloseProtocol (
+           Controller,
+           &gEfiPciIoProtocolGuid,
+           This->DriverBindingHandle,
+           Controller
+           );
+
+    FreePool (Private);
+  }
+
+  return Status;
+}
+
+/**
+  The entry point for UFS host controller driver, used to install this driver on the ImageHandle.
+
+  @param[in]  ImageHandle   The firmware allocated handle for this driver image.
+  @param[in]  SystemTable   Pointer to the EFI system table.
+
+  @retval EFI_SUCCESS   Driver loaded.
+  @retval other         Driver not loaded.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverEntry (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS           Status;
+
+  Status = EfiLibInstallDriverBindingComponentName2 (
+             ImageHandle,
+             SystemTable,
+             &gUfsHcDriverBinding,
+             ImageHandle,
+             &gUfsHcComponentName,
+             &gUfsHcComponentName2
+             );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/Drivers/Mmc/DwSdDxe/DwSdDxe.dec b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.dec
index 871966d..946c286 100644
--- a/Drivers/Mmc/DwSdDxe/DwSdDxe.dec
+++ b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.dec
@@ -1,42 +1,40 @@
-#/** @file
-# Framework Module Development Environment Industry Standards
-#
-# This Package provides headers and libraries that conform to EFI/PI Industry standards.
-# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
-# Copyright (c) 2015-2016, Linaro. All rights reserved.<BR>
-#
-#    This program and the accompanying materials are licensed and made available under
-#    the terms and conditions of the BSD License which accompanies this distribution.
-#    The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
-#
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = OpenPlatformDriversMmcDwSdDxePkg
-  PACKAGE_GUID                   = d1658c47-db3c-4a10-a878-5ea3a4d28d37
-  PACKAGE_VERSION                = 0.1
-
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-#                   Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-
-[Guids.common]
-  gDwSdDxeTokenSpaceGuid	 = { 0xd5399aaf, 0xacaf, 0x488c, {0xb2, 0x33, 0x7a, 0x16, 0x0f, 0xc6, 0x00, 0xed }}
-
-[PcdsFixedAtBuild.common]
-  # DwSd Driver PCDs
-  gDwSdDxeTokenSpaceGuid.PcdDwSdDxeBaseAddress|0x0|UINT32|0x00000001
-  gDwSdDxeTokenSpaceGuid.PcdDwSdDxeClockFrequencyInHz|0x0|UINT32|0x00000002
+#/** @file
+# Framework Module Development Environment Industry Standards
+#
+# This Package provides headers and libraries that conform to EFI/PI Industry standards.
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2016-2017, Linaro. All rights reserved.<BR>
+#
+#    This program and the accompanying materials are licensed and made available under
+#    the terms and conditions of the BSD License which accompanies this distribution.
+#    The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = OpenPlatformDriversBlockDwUfsHcDxePkg
+  PACKAGE_GUID                   = 0f2b8c0a-461a-4c2c-8bfc-0570208cc5e8
+  PACKAGE_VERSION                = 0.1
+
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+  gDwUfsHcDxeTokenSpaceGuid      = { 0x0138a049, 0x3062, 0x4d2c,  { 0x8b, 0xbe, 0x1b, 0x23, 0x69, 0xab, 0xd4, 0x8e }}
+
+[PcdsFixedAtBuild.common]
+  gDwUfsHcDxeTokenSpaceGuid.PcdDwUfsHcDxeBaseAddress|0x0|UINT32|0x00000001
diff --git a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.h b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.h
new file mode 100644
index 0000000..8c8476c
--- /dev/null
+++ b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.h
@@ -0,0 +1,596 @@
+/** @file
+  UfsHcDxe driver is used to provide platform-dependent info, mainly UFS host controller
+  MMIO base, to upper layer UFS drivers.
+
+  Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DW_UFS_HOST_CONTROLLER_H_
+#define _DW_UFS_HOST_CONTROLLER_H_
+
+#include <Uefi.h>
+
+#include <Protocol/ComponentName.h>
+#include <Protocol/ComponentName2.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/DriverBinding.h>
+#include <Protocol/LoadedImage.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/UfsHostController.h>
+
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/DmaLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+
+//
+// Host Capabilities Register Offsets
+//
+#define UFS_HC_CAP_OFFSET          0x0000  // Controller Capabilities
+#define UFS_HC_VER_OFFSET          0x0008  // Version
+#define UFS_HC_DDID_OFFSET         0x0010  // Device ID and Device Class
+#define UFS_HC_PMID_OFFSET         0x0014  // Product ID and Manufacturer ID
+#define UFS_HC_AHIT_OFFSET         0x0018  // Auto-Hibernate Idle Timer
+//
+// Operation and Runtime Register Offsets
+//
+#define UFS_HC_IS_OFFSET           0x0020  // Interrupt Status
+#define UFS_HC_IE_OFFSET           0x0024  // Interrupt Enable
+#define UFS_HC_STATUS_OFFSET       0x0030  // Host Controller Status
+#define UFS_HC_ENABLE_OFFSET       0x0034  // Host Controller Enable
+#define UFS_HC_UECPA_OFFSET        0x0038  // Host UIC Error Code PHY Adapter Layer
+#define UFS_HC_UECDL_OFFSET        0x003c  // Host UIC Error Code Data Link Layer
+#define UFS_HC_UECN_OFFSET         0x0040  // Host UIC Error Code Network Layer
+#define UFS_HC_UECT_OFFSET         0x0044  // Host UIC Error Code Transport Layer
+#define UFS_HC_UECDME_OFFSET       0x0048  // Host UIC Error Code DME
+#define UFS_HC_UTRIACR_OFFSET      0x004c  // UTP Transfer Request Interrupt Aggregation Control Register
+//
+// UTP Transfer Register Offsets
+//
+#define UFS_HC_UTRLBA_OFFSET       0x0050  // UTP Transfer Request List Base Address
+#define UFS_HC_UTRLBAU_OFFSET      0x0054  // UTP Transfer Request List Base Address Upper 32-Bits
+#define UFS_HC_UTRLDBR_OFFSET      0x0058  // UTP Transfer Request List Door Bell Register
+#define UFS_HC_UTRLCLR_OFFSET      0x005c  // UTP Transfer Request List CLear Register
+#define UFS_HC_UTRLRSR_OFFSET      0x0060  // UTP Transfer Request Run-Stop Register
+//
+// UTP Task Management Register Offsets
+//
+#define UFS_HC_UTMRLBA_OFFSET      0x0070  // UTP Task Management Request List Base Address
+#define UFS_HC_UTMRLBAU_OFFSET     0x0074  // UTP Task Management Request List Base Address Upper 32-Bits
+#define UFS_HC_UTMRLDBR_OFFSET     0x0078  // UTP Task Management Request List Door Bell Register
+#define UFS_HC_UTMRLCLR_OFFSET     0x007c  // UTP Task Management Request List CLear Register
+#define UFS_HC_UTMRLRSR_OFFSET     0x0080  // UTP Task Management Run-Stop Register
+//
+// UIC Command Register Offsets
+//
+#define UFS_HC_UIC_CMD_OFFSET      0x0090  // UIC Command Register
+#define UFS_HC_UCMD_ARG1_OFFSET    0x0094  // UIC Command Argument 1
+#define UFS_HC_UCMD_ARG2_OFFSET    0x0098  // UIC Command Argument 2
+#define UFS_HC_UCMD_ARG3_OFFSET    0x009c  // UIC Command Argument 3
+//
+// UMA Register Offsets
+//
+#define UFS_HC_UMA_OFFSET          0x00b0  // Reserved for Unified Memory Extension
+
+#define UFS_HC_HCLKDIV_OFFSET      0x00fc
+
+#define UFS_HC_HCE_EN              BIT0
+#define UFS_HC_HCS_DP              BIT0
+#define UFS_HC_HCS_UCRDY           BIT3
+#define UFS_HC_IS_UE               BIT2
+#define UFS_HC_IS_ULSS             BIT8
+#define UFS_HC_IS_UCCS             BIT10
+#define UFS_HC_CAP_64ADDR          BIT24
+#define UFS_HC_CAP_NUTMRS          (BIT16 | BIT17 | BIT18)
+#define UFS_HC_CAP_NUTRS           (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)
+#define UFS_HC_UTMRLRSR            BIT0
+#define UFS_HC_UTRLRSR             BIT0
+
+#define UFS_UIC_DME_GET            1
+#define UFS_UIC_DME_SET            2
+
+#define UFS_INT_UPMS               BIT4
+
+#define HCS_UPMCRS_MASK            (BIT10 | BIT9 | BIT8)
+#define HCS_PWR_LOCAL              BIT8
+
+extern EFI_DRIVER_BINDING_PROTOCOL                gUfsHcDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL                gUfsHcComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL               gUfsHcComponentName2;
+
+//
+// Unique signature for private data structure.
+//
+#define UFS_HC_PRIVATE_DATA_SIGNATURE             SIGNATURE_32 ('U','F','S','H')
+
+typedef struct _UFS_HOST_CONTROLLER_PRIVATE_DATA  UFS_HOST_CONTROLLER_PRIVATE_DATA;
+
+//
+// Nvme private data structure.
+//
+struct _UFS_HOST_CONTROLLER_PRIVATE_DATA {
+  UINT32                             Signature;
+  EFI_HANDLE                         Handle;
+
+  EDKII_UFS_HOST_CONTROLLER_PROTOCOL UfsHc;
+  EFI_PCI_IO_PROTOCOL                *PciIo;
+  UINT8                              BarIndex;
+  UINT64                             PciAttributes;
+
+  UINTN                              RegBase;
+};
+
+#define UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC(a) \
+  CR (a, \
+      UFS_HOST_CONTROLLER_PRIVATE_DATA, \
+      UfsHc, \
+      UFS_HC_PRIVATE_DATA_SIGNATURE \
+      )
+
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
+  IN  CHAR8                        *Language,
+  OUT CHAR16                       **DriverName
+  );
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
+  IN  EFI_HANDLE                                      ControllerHandle,
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
+  IN  CHAR8                                           *Language,
+  OUT CHAR16                                          **ControllerName
+  );
+
+/**
+  Tests to see if this driver supports a given controller. If a child device is provided,
+  it further tests to see if this driver supports creating a handle for the specified child device.
+
+  This function checks to see if the driver specified by This supports the device specified by
+  ControllerHandle. Drivers will typically use the device path attached to
+  ControllerHandle and/or the services from the bus I/O abstraction attached to
+  ControllerHandle to determine if the driver supports ControllerHandle. This function
+  may be called many times during platform initialization. In order to reduce boot times, the tests
+  performed by this function must be very small, and take as little time as possible to execute. This
+  function must not change the state of any hardware devices, and this function must be aware that the
+  device specified by ControllerHandle may already be managed by the same driver or a
+  different driver. This function must match its calls to AllocatePages() with FreePages(),
+  AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+  Since ControllerHandle may have been previously started by the same driver, if a protocol is
+  already in the opened state, then it must not be closed with CloseProtocol(). This is required
+  to guarantee the state of ControllerHandle is not modified by this function.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to test. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For bus drivers, if this parameter is not NULL, then
+                                   the bus driver must determine if the bus controller specified
+                                   by ControllerHandle and the child controller specified
+                                   by RemainingDevicePath are both supported by this
+                                   bus driver.
+
+  @retval EFI_SUCCESS              The device specified by ControllerHandle and
+                                   RemainingDevicePath is supported by the driver specified by This.
+  @retval EFI_ALREADY_STARTED      The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by the driver
+                                   specified by This.
+  @retval EFI_ACCESS_DENIED        The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by a different
+                                   driver or an application that requires exclusive access.
+                                   Currently not implemented.
+  @retval EFI_UNSUPPORTED          The device specified by ControllerHandle and
+                                   RemainingDevicePath is not supported by the driver specified by This.
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  );
+
+/**
+  Starts a device controller or a bus controller.
+
+  The Start() function is designed to be invoked from the EFI boot service ConnectController().
+  As a result, much of the error checking on the parameters to Start() has been moved into this
+  common boot service. It is legal to call Start() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE.
+  2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
+     EFI_DEVICE_PATH_PROTOCOL.
+  3. Prior to calling Start(), the Supported() function for the driver specified by This must
+     have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to start. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For a bus driver, if this parameter is NULL, then handles
+                                   for all the children of Controller are created by this driver.
+                                   If this parameter is not NULL and the first Device Path Node is
+                                   not the End of Device Path Node, then only the handle for the
+                                   child device specified by the first Device Path Node of
+                                   RemainingDevicePath is created by this driver.
+                                   If the first Device Path Node of RemainingDevicePath is
+                                   the End of Device Path Node, no child handle is created by this
+                                   driver.
+
+  @retval EFI_SUCCESS              The device was started.
+  @retval EFI_DEVICE_ERROR         The device could not be started due to a device error.Currently not implemented.
+  @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+  @retval Others                   The driver failded to start the device.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  );
+
+/**
+  Stops a device controller or a bus controller.
+
+  The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+  As a result, much of the error checking on the parameters to Stop() has been moved
+  into this common boot service. It is legal to call Stop() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
+     same driver's Start() function.
+  2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
+     EFI_HANDLE. In addition, all of these handles must have been created in this driver's
+     Start() function, and the Start() function must have called OpenProtocol() on
+     ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+  @param[in]  This              A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle  A handle to the device being stopped. The handle must
+                                support a bus specific I/O protocol for the driver
+                                to use to stop the device.
+  @param[in]  NumberOfChildren  The number of child device handles in ChildHandleBuffer.
+  @param[in]  ChildHandleBuffer An array of child handles to be freed. May be NULL
+                                if NumberOfChildren is 0.
+
+  @retval EFI_SUCCESS           The device was stopped.
+  @retval EFI_DEVICE_ERROR      The device could not be stopped due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN  EFI_HANDLE                      Controller,
+  IN  UINTN                           NumberOfChildren,
+  IN  EFI_HANDLE                      *ChildHandleBuffer
+  );
+
+/**
+  Get the MMIO base of the UFS host controller.
+
+  @param[in]   This             A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param[out]  MmioBar          The MMIO base address of UFS host controller.
+
+  @retval EFI_SUCCESS           The operation succeeds.
+  @retval others                The operation fails.
+**/
+EFI_STATUS
+EFIAPI
+UfsHcGetMmioBar (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+     OUT UINTN                              *MmioBar
+  );
+
+/**
+  Provides the UFS controller-specific addresses needed to access system memory.
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Operation             Indicates if the bus master is going to read or write to system memory.
+  @param  HostAddress           The system memory address to map to the UFS controller.
+  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
+                                that were mapped.
+  @param  DeviceAddress         The resulting map address for the bus master UFS controller to use to
+                                access the hosts HostAddress.
+  @param  Mapping               A resulting value to pass to Unmap().
+
+  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
+  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
+  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcMap (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL   *This,
+  IN     EDKII_UFS_HOST_CONTROLLER_OPERATION  Operation,
+  IN     VOID                                 *HostAddress,
+  IN OUT UINTN                                *NumberOfBytes,
+     OUT EFI_PHYSICAL_ADDRESS                 *DeviceAddress,
+     OUT VOID                                 **Mapping
+  );
+
+/**
+  Completes the Map() operation and releases any corresponding resources.
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Mapping               The mapping value returned from Map().
+
+  @retval EFI_SUCCESS           The range was unmapped.
+  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcUnmap (
+  IN  EDKII_UFS_HOST_CONTROLLER_PROTOCOL   *This,
+  IN  VOID                                 *Mapping
+  );
+
+/**
+  Allocates pages that are suitable for an EfiUfsHcOperationBusMasterCommonBuffer
+  mapping.
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Type                  This parameter is not used and must be ignored.
+  @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
+                                EfiRuntimeServicesData.
+  @param  Pages                 The number of pages to allocate.
+  @param  HostAddress           A pointer to store the base system memory address of the
+                                allocated range.
+  @param  Attributes            The requested bit mask of attributes for the allocated range.
+
+  @retval EFI_SUCCESS           The requested memory pages were allocated.
+  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
+                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcAllocateBuffer (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This,
+  IN     EFI_ALLOCATE_TYPE                  Type,
+  IN     EFI_MEMORY_TYPE                    MemoryType,
+  IN     UINTN                              Pages,
+     OUT VOID                               **HostAddress,
+  IN     UINT64                             Attributes
+  );
+
+/**
+  Frees memory that was allocated with AllocateBuffer().
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Pages                 The number of pages to free.
+  @param  HostAddress           The base system memory address of the allocated range.
+
+  @retval EFI_SUCCESS           The requested memory pages were freed.
+  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
+                                was not allocated with AllocateBuffer().
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcFreeBuffer (
+  IN  EDKII_UFS_HOST_CONTROLLER_PROTOCOL    *This,
+  IN  UINTN                                 Pages,
+  IN  VOID                                  *HostAddress
+  );
+
+/**
+  Flushes all posted write transactions from the UFS bus to attached UFS device.
+
+  @param  This                  A pointer to the EFI_UFS_HOST_CONTROLLER_PROTOCOL instance.
+
+  @retval EFI_SUCCESS           The posted write transactions were flushed from the UFS bus
+                                to attached UFS device.
+  @retval EFI_DEVICE_ERROR      The posted write transactions were not flushed from the UFS
+                                bus to attached UFS device due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcFlush (
+  IN  EDKII_UFS_HOST_CONTROLLER_PROTOCOL   *This
+  );
+
+/**
+  Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
+
+  @param  This                  A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Width                 Signifies the width of the memory operations.
+  @param  Offset                The offset within the UFS Host Controller MMIO space to start the
+                                memory operation.
+  @param  Count                 The number of memory operations to perform.
+  @param  Buffer                For read operations, the destination buffer to store the results.
+                                For write operations, the source buffer to write data from.
+
+  @retval EFI_SUCCESS           The data was read from or written to the UFS host controller.
+  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
+                                valid for the UFS Host Controller memory space.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcMmioRead (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL        *This,
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                    Offset,
+  IN     UINTN                                     Count,
+  IN OUT VOID                                      *Buffer
+  );
+
+/**
+  Enable a UFS bus driver to access UFS MMIO registers in the UFS Host Controller memory space.
+
+  @param  This                  A pointer to the EDKII_UFS_HOST_CONTROLLER_PROTOCOL instance.
+  @param  Width                 Signifies the width of the memory operations.
+  @param  Offset                The offset within the UFS Host Controller MMIO space to start the
+                                memory operation.
+  @param  Count                 The number of memory operations to perform.
+  @param  Buffer                For read operations, the destination buffer to store the results.
+                                For write operations, the source buffer to write data from.
+
+  @retval EFI_SUCCESS           The data was read from or written to the UFS host controller.
+  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
+                                valid for the UFS Host Controller memory space.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+UfsHcMmioWrite (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL        *This,
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL_WIDTH  Width,
+  IN     UINT64                                    Offset,
+  IN     UINTN                                     Count,
+  IN OUT VOID                                      *Buffer
+  );
+
+EFI_STATUS
+EFIAPI
+UfsHcPhyInit (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL        *This
+  );
+
+EFI_STATUS
+EFIAPI
+UfsHcPhySetPowerMode (
+  IN     EDKII_UFS_HOST_CONTROLLER_PROTOCOL        *This
+  );
+#endif /* _DW_UFS_HOST_CONTROLLER_H_ */
diff --git a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.inf b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.inf
new file mode 100644
index 0000000..10c2d26
--- /dev/null
+++ b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.inf
@@ -0,0 +1,60 @@
+#
+#  Copyright (c) 2016 - 2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = DwUfsHcDxe
+  FILE_GUID                      = a7bc7d5f-d719-42d0-8ab3-5b5c3917e6ad
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = UfsHcDriverEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = ARM
+#
+#  DRIVER_BINDING                =  gUfsHcDriverBinding
+#  COMPONENT_NAME                =  gUfsHcComponentName
+#  COMPONENT_NAME2               =  gUfsHcComponentName2
+
+[Sources]
+  ComponentName.c
+  DwUfsHcDxe.c
+  DwUfsHcDxe.h
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.dec
+
+[LibraryClasses]
+  ArmLib
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  DevicePathLib
+  DmaLib
+  MemoryAllocationLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  UefiLib
+
+[Protocols]
+  gEdkiiUfsHostControllerProtocolGuid         ## BY_START
+  gEfiDevicePathProtocolGuid                  ## TO_START
+  gEfiPciIoProtocolGuid
+
+[Pcd]
+  gDwUfsHcDxeTokenSpaceGuid.PcdDwUfsHcDxeBaseAddress
diff --git a/Drivers/Block/ramdisk/ramdisk.c b/Drivers/Block/ramdisk/ramdisk.c
new file mode 100644
index 0000000..21e090b
--- /dev/null
+++ b/Drivers/Block/ramdisk/ramdisk.c
@@ -0,0 +1,526 @@
+
+/*
+ * Copyright (c) 1999, 2000
+ * Intel Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. All advertising materials mentioning features or use of this software must
+ *    display the following acknowledgement:
+ *
+ *    This product includes software developed by Intel Corporation and its
+ *    contributors.
+ *
+ * 4. Neither the name of Intel Corporation or its contributors may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <Uefi.h>
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/LoadedImage.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DevicePathLib.h>
+
+#include <Guid/RamDiskGuid.h>
+#include "ramdisk.h"
+
+
+UINT32    GetDiskSize( EFI_HANDLE ImageHandle );
+
+/* Embedded version string for VERS utility */
+//static char v[] = "version_number=1.00 ";
+
+/* EFI device path definition */
+static RAM_DISK_DEVICE_PATH RamDiskDevicePath =
+{
+  {MESSAGING_DEVICE_PATH,
+  MSG_VENDOR_DP,
+  {sizeof(RAM_DISK_DEVICE_PATH) - END_DEVICE_PATH_LENGTH,
+  0}},
+  RAM_DISK_GUID,
+  {0,0,0,0,0,0,0,0},  // ID assigned below
+  {END_DEVICE_PATH_TYPE,
+  END_ENTIRE_DEVICE_PATH_SUBTYPE,
+  {END_DEVICE_PATH_LENGTH}}
+};
+
+/* Lookup table of total sectors vs. cluster size.
+ * Ramdisk sizes between 0x20D0 (4.1MB) and 0x100000 (512MB) sectors are valid FAT16 drive sizes.
+ */
+#define MIN_DISK_SIZE  1
+#define  MAX_DISK_SIZE  512
+static FAT16TABLE fat16tbl[] =
+{
+  {0x00000800, 1},  /* 800 sectors * 1 sec/cluster * 512 bytes = 1 M */
+  {0x00001000, 1},  /* 1000 sectors * 1 sec/cluster * 512 bytes = 2 M */
+  {0x00001800, 1},  /* 1800 sectors * 1 sec/cluster * 512 bytes = 3 M */
+  {0x00007FA8, 2},
+  {0x00040000, 4},
+  {0x00080000, 8},
+  {0x00100000,16},
+  {0xFFFFFFFF, 0}
+};
+
+VOID CopyBOOTSEC(VOID* Start,BOOTSEC* bsc)
+{
+UINT32 index=0;
+UINT8* pStart=(UINT8*)Start;
+
+CopyMem(&(pStart[index]), &(bsc->BS_jmpBoot[0]), sizeof(bsc->BS_jmpBoot));
+index+=sizeof(bsc->BS_jmpBoot);
+
+CopyMem(&(pStart[index]), &(bsc->BS_OEMName[0]), sizeof(bsc->BS_OEMName));
+index+=sizeof(bsc->BS_OEMName);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_BytsPerSec), sizeof(bsc->BPB_BytsPerSec));
+index+=sizeof(bsc->BPB_BytsPerSec);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_SecPerClus), sizeof(bsc->BPB_SecPerClus));
+index+=sizeof(bsc->BPB_SecPerClus);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_RsvdSecCnt), sizeof(bsc->BPB_RsvdSecCnt));
+index+=sizeof(bsc->BPB_RsvdSecCnt);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_NumFATs), sizeof(bsc->BPB_NumFATs));
+index+=sizeof(bsc->BPB_NumFATs);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_NumFATs), sizeof(bsc->BPB_NumFATs));
+index+=sizeof(bsc->BPB_NumFATs);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_RootEntCnt), sizeof(bsc->BPB_RootEntCnt));
+index+=sizeof(bsc->BPB_RootEntCnt);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_TotSec16), sizeof(bsc->BPB_TotSec16));
+index+=sizeof(bsc->BPB_TotSec16);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_Media), sizeof(bsc->BPB_Media));
+index+=sizeof(bsc->BPB_Media);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_FATSz16), sizeof(bsc->BPB_FATSz16));
+index+=sizeof(bsc->BPB_FATSz16);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_SecPerTrk), sizeof(bsc->BPB_SecPerTrk));
+index+=sizeof(bsc->BPB_SecPerTrk);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_NumHeads), sizeof(bsc->BPB_NumHeads));
+index+=sizeof(bsc->BPB_NumHeads);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_HiddSec), sizeof(bsc->BPB_HiddSec));
+index+=sizeof(bsc->BPB_HiddSec);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_TotSec32), sizeof(bsc->BPB_TotSec32));
+index+=sizeof(bsc->BPB_TotSec32);
+
+CopyMem(&(pStart[index]), &(bsc->BS_DrvNum), sizeof(bsc->BS_DrvNum));
+index+=sizeof(bsc->BS_DrvNum);
+
+CopyMem(&(pStart[index]), &(bsc->BS_Reserved1), sizeof(bsc->BS_Reserved1));
+index+=sizeof(bsc->BS_Reserved1);
+
+CopyMem(&(pStart[index]), &(bsc->BS_BootSig), sizeof(bsc->BS_BootSig));
+index+=sizeof(bsc->BS_BootSig);
+
+CopyMem(&(pStart[index]), &(bsc->BS_VolID), sizeof(bsc->BS_VolID));
+index+=sizeof(bsc->BS_VolID);
+
+CopyMem(&(pStart[index]), &(bsc->BS_VolLab[0]), sizeof(bsc->BS_VolLab));
+index+=sizeof(bsc->BS_VolLab);
+
+CopyMem(&(pStart[index]), &(bsc->BS_FilSysType[0]), sizeof(bsc->BS_FilSysType));
+index+=sizeof(bsc->BS_FilSysType);
+
+CopyMem(&(pStart[index]), &(bsc->BS_Code[0]), sizeof(bsc->BS_Code));
+index+=sizeof(bsc->BS_Code);
+
+CopyMem(&(pStart[index]), &(bsc->BS_Sig), sizeof(bsc->BS_Sig));
+
+}
+
+
+
+/* Helper function to compute cluster size
+ * vs. total sectors on drive.
+ */
+STATIC UINT8 size2spc(UINT32 ts)
+{
+  int i = 0;
+
+  while(fat16tbl[i].size != 0xFFFFFFFF)
+  {
+    if(ts <= fat16tbl[i].size)
+      return fat16tbl[i].spc;
+    ++i;
+  }
+
+  return 0;
+}
+
+UINT8 TestSize(UINT32 ts)
+{
+  int i = 0;
+
+  while(fat16tbl[i].size != 0xFFFFFFFF)
+  {
+    if(ts <= fat16tbl[i].size)
+      return fat16tbl[i].spc;
+    ++i;
+  }
+
+  return 0;
+}
+
+EFI_SYSTEM_TABLE  BackupSystemTable;
+
+/*
+ * Entry point for RamDisk driver.
+ */
+
+EFI_STATUS InitializeRamDiskDriver(
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable)
+{
+  EFI_STATUS           Status;
+  RAM_DISK_DEV         *RamDiskDev;
+  UINT32               RamDiskSize;
+  UINT32               NumPages;
+  UINT32               BlockSize;
+  UINT64               DiskId;
+
+  /*
+   * Make a copy of the system table to workaround load command bug
+   */
+  CopyMem(&BackupSystemTable,SystemTable,sizeof(BackupSystemTable));
+
+  /*
+   * Initialize EFI library
+   */
+  //InitializeLib(ImageHandle,&BackupSystemTable);
+
+  /* IA64 compiler is removing version string (unused?) so I use it */
+  //v[0] = 'v';
+
+  /*
+   *  Set the disk size
+   */
+  RamDiskSize = GetDiskSize(ImageHandle);
+  BlockSize   = 512;
+
+  /* Allocate storage for ramdisk device info on the heap.
+   */
+  RamDiskDev = AllocateZeroPool(sizeof(RAM_DISK_DEV));
+  if(RamDiskDev == NULL)
+    return EFI_OUT_OF_RESOURCES;
+
+  /*
+   * Compute the number of 4KB pages needed by the ramdisk and allocate the memory.
+   */
+  NumPages = RamDiskSize / EFI_PAGE_SIZE;
+  if(NumPages % RamDiskSize)
+    NumPages++;
+
+  Status = gBS->AllocatePages(AllocateAnyPages,EfiBootServicesData,NumPages,&RamDiskDev->Start);
+  if(EFI_ERROR(Status)) {
+    FreePool(RamDiskDev);
+    return Status;
+  }
+
+  /*
+   * Initialize the ramdisk's device info.
+   */
+  (void)gBS->GetNextMonotonicCount(&DiskId);
+  CopyMem(&RamDiskDevicePath.DiskId, &DiskId, sizeof(DiskId));
+
+  RamDiskDev->Signature            = PBLOCK_DEVICE_SIGNATURE;
+  RamDiskDev->BlkIo.Revision       = EFI_BLOCK_IO_INTERFACE_REVISION;
+  RamDiskDev->BlkIo.Media          = &RamDiskDev->Media;
+  RamDiskDev->Media.RemovableMedia = FALSE;
+  RamDiskDev->Media.MediaPresent   = TRUE;
+
+  RamDiskDev->Media.LastBlock        = RamDiskSize/BlockSize - 1;
+  RamDiskDev->Media.BlockSize        = BlockSize;
+  RamDiskDev->Media.LogicalPartition = TRUE;
+  RamDiskDev->Media.ReadOnly         = FALSE;
+  RamDiskDev->Media.WriteCaching     = TRUE;
+
+  RamDiskDev->BlkIo.ReadBlocks  = RamDiskReadBlocks;
+  RamDiskDev->BlkIo.WriteBlocks = RamDiskWriteBlocks;
+  RamDiskDev->BlkIo.FlushBlocks = RamDiskFlushBlocks;
+
+  RamDiskDev->DevicePath = DuplicateDevicePath((EFI_DEVICE_PATH*)&RamDiskDevicePath);
+
+  /*
+   * Build a FAT16 file system on the ramdisk.
+   */
+  FormatRamdisk((VOID*)(UINTN)RamDiskDev->Start,RamDiskSize);
+
+  /*
+   * Install the device.
+   */
+
+  Status = gBS->InstallMultipleProtocolInterfaces(
+  &ImageHandle,
+  &gEfiBlockIoProtocolGuid,
+  &RamDiskDev->BlkIo,
+  &gEfiDevicePathProtocolGuid,
+  RamDiskDev->DevicePath,
+  NULL);
+
+DEBUG((EFI_D_ERROR,"ramdisk:blckio install. Status=%r\n",Status));
+  return Status;
+}
+
+UINT32
+GetDiskSize( EFI_HANDLE ImageHandle )
+{
+  EFI_STATUS      Status;
+  EFI_LOADED_IMAGE  *Image;
+  UINT32        DiskSize = PcdGet32(PcdRamDiskMaxSize);
+
+  /*
+   * Check load options to see if they want to specify disk size in MBs
+   */
+  Status = gBS->HandleProtocol(ImageHandle, &gEfiLoadedImageProtocolGuid, (void**)&Image);
+  if (!EFI_ERROR(Status)) {
+    if (Image->LoadOptions && Image->LoadOptionsSize) {
+#define MAX_ARG_SIZE    32
+      CHAR16  Size[ MAX_ARG_SIZE ];
+      CHAR16  *CmdLine = Image->LoadOptions;
+      INT32  CmdLen   = (INT32)Image->LoadOptionsSize;
+
+      /*
+       * Get past program name
+       */
+      while( CmdLen > 0 && *CmdLine != L' ' ) {
+        CmdLen -= sizeof(CHAR16);
+        CmdLine++;
+      }
+
+      if ( CmdLen > 0 ) {
+        /*
+         * Make sure we're null terminated
+         */
+        CopyMem( Size, CmdLine, MIN(CmdLen, (INT32)sizeof(Size)));
+        Size[MAX_ARG_SIZE - 1] = 0;
+
+        /*
+         *  Atoi() will skip any leading white space
+         */
+        DiskSize = (UINT32)StrDecimalToUintn(Size);
+        if (DiskSize == 0)
+          DiskSize = PcdGet32(PcdRamDiskMaxSize);
+        DiskSize = MAX(DiskSize, MIN_DISK_SIZE);
+        DiskSize = MIN(DiskSize, MAX_DISK_SIZE);
+      }
+    }
+  }
+
+  return (DiskSize * 1024 * 1024);
+}
+
+/* Given a block of memory representing a ramdisk, build a pseudo-boot sector
+ * and initialize the drive.
+ *
+ * Assumes the global boot sector structure g_bs has been filled out with the
+ * static information the boot sector requires.  Also assumes the ramdisk size
+ * is between 4.1MB and 512MB as appropriate for FAT16 file system.
+ */
+STATIC VOID FormatRamdisk(
+  IN VOID*  pStart,
+  IN UINT32 Size)
+{
+  UINT32 TotalSectors,RootDirSectors,FatSz,tmp1,tmp2;
+  UINT8 *Fat1,*Fat2;
+    BOOTSEC g_bs;
+
+    g_bs.BS_jmpBoot[0] = 0xeb;
+    g_bs.BS_jmpBoot[1] = 0x0;
+    g_bs.BS_jmpBoot[2] = 0x90;
+    g_bs.BS_OEMName[0] = 'E';
+    g_bs.BS_OEMName[1] = 'F';
+    g_bs.BS_OEMName[2] = 'I';
+    g_bs.BS_OEMName[3] = 'R';
+    g_bs.BS_OEMName[4] = 'D';
+    g_bs.BS_OEMName[5] = 'I';
+    g_bs.BS_OEMName[6] = 'S';
+    g_bs.BS_OEMName[7] = 'K';
+    g_bs.BPB_BytsPerSec = 512;
+    g_bs.BPB_SecPerClus = 0;
+    g_bs.BPB_RsvdSecCnt = 1;
+    g_bs.BPB_NumFATs = 2;
+    g_bs.BPB_RootEntCnt = 512;
+    g_bs.BPB_TotSec16 = 0;
+    g_bs.BPB_Media = 0xF8;
+    g_bs.BPB_FATSz16 = 0;
+    g_bs.BPB_SecPerTrk = 0;
+    g_bs.BPB_NumHeads = 0;
+    g_bs.BPB_HiddSec = 0;
+    g_bs.BPB_TotSec32 = 0;
+    g_bs.BS_DrvNum = 0;
+    g_bs.BS_Reserved1 = 0;
+    g_bs.BS_BootSig = 0x29;
+    g_bs.BS_VolID = 0;
+    g_bs.BS_VolLab[0] = 'N';
+    g_bs.BS_VolLab[1] = 'O';
+    g_bs.BS_VolLab[2] = ' ';
+    g_bs.BS_VolLab[3] = 'N';
+    g_bs.BS_VolLab[4] = 'A';
+    g_bs.BS_VolLab[5] = 'M';
+    g_bs.BS_VolLab[6] = 'E';
+    g_bs.BS_VolLab[7] = ' ';
+    g_bs.BS_VolLab[8] = ' ';
+    g_bs.BS_FilSysType[0] = 'F';
+    g_bs.BS_FilSysType[1] = 'A';
+    g_bs.BS_FilSysType[2] = 'T';
+    g_bs.BS_FilSysType[3] = '1';
+    g_bs.BS_FilSysType[4] = '6';
+    g_bs.BS_FilSysType[5] = ' ';
+    g_bs.BS_FilSysType[6] = ' ';
+    g_bs.BS_FilSysType[7] = ' ';
+  /* The boot signature needs to be filled out */
+  g_bs.BS_Sig = 0xAA55;
+
+  /* Compute the total sectors and appropriate cluster size */
+  TotalSectors = Size / g_bs.BPB_BytsPerSec;
+  g_bs.BPB_SecPerClus = size2spc(TotalSectors);
+  ASSERT(g_bs.BPB_SecPerClus != 0);
+
+  /* Compute how many root directory sectors are needed */
+  RootDirSectors = (g_bs.BPB_RootEntCnt * 32 + g_bs.BPB_BytsPerSec - 1) / g_bs.BPB_BytsPerSec;
+
+  /* Compute how many sectors are required per FAT */
+  tmp1 = TotalSectors - (g_bs.BPB_RsvdSecCnt + RootDirSectors);
+  tmp2 = 256 * g_bs.BPB_SecPerClus + g_bs.BPB_NumFATs;
+  FatSz = (tmp1 + tmp2 - 1) / tmp2;
+  ASSERT(FatSz <= 0xFFFF);
+
+  /* Store the total sectors and fat size values */
+  if(TotalSectors > 0xFFFF)
+    g_bs.BPB_TotSec32 = TotalSectors;
+  else
+    g_bs.BPB_TotSec16 = (UINT16)TotalSectors;
+
+  g_bs.BPB_FATSz16 = (UINT16)FatSz;
+
+  /* The FAT table and root directory need to be all zeroes.
+   * We'll zero the whole drive.
+   */
+  ZeroMem(pStart,Size);
+
+  /* Write the completed boot sector to the ramdisk */
+  CopyMem(pStart,&g_bs,512);
+
+  /* Compute the starting offsets of the two FATs */
+  Fat1 = (UINT8*)pStart + g_bs.BPB_RsvdSecCnt * 512;
+  Fat2 = (UINT8*)pStart + (UINTN)(g_bs.BPB_RsvdSecCnt + FatSz) * 512;
+
+  /* Initialize FAT1 */
+  Fat1[0] = g_bs.BPB_Media;
+  Fat1[1] = 0xFF;
+  Fat1[2] = 0xFF;
+  Fat1[3] = 0xFF;
+
+  /* Initialize FAT2 */
+  Fat2[0] = g_bs.BPB_Media;
+  Fat2[1] = 0xFF;
+  Fat2[2] = 0xFF;
+  Fat2[3] = 0xFF;
+}
+
+/* Implementation of block I/O read */
+STATIC EFI_STATUS RamDiskReadBlocks(
+  IN EFI_BLOCK_IO *This,
+  IN UINT32       MediaId,
+  IN EFI_LBA      LBA,
+  IN UINTN        BufferSize,
+  OUT VOID        *Buffer)
+{
+  EFI_BLOCK_IO_MEDIA   *Media;
+  RAM_DISK_DEV         *RamDiskDev;
+  EFI_PHYSICAL_ADDRESS RamDiskLBA;
+
+  Media = This->Media;
+
+  if(BufferSize % Media->BlockSize != 0)
+    return EFI_BAD_BUFFER_SIZE;
+
+  if(LBA > Media->LastBlock)
+    return EFI_DEVICE_ERROR;
+
+  if(LBA + BufferSize / Media->BlockSize - 1 > Media->LastBlock)
+    return EFI_DEVICE_ERROR;
+
+  RamDiskDev = RAM_DISK_FROM_THIS(This);
+  RamDiskLBA = RamDiskDev->Start + MultU64x32(LBA,Media->BlockSize);
+  CopyMem(Buffer,(VOID*)(UINTN)RamDiskLBA,BufferSize);
+
+  return EFI_SUCCESS;
+}
+
+
+/* Implementation of block I/O write */
+STATIC EFI_STATUS RamDiskWriteBlocks(
+  IN EFI_BLOCK_IO *This,
+  IN UINT32       MediaId,
+  IN EFI_LBA      LBA,
+  IN UINTN        BufferSize,
+  IN VOID         *Buffer)
+{
+  EFI_BLOCK_IO_MEDIA   *Media;
+  RAM_DISK_DEV         *RamDiskDev;
+  EFI_PHYSICAL_ADDRESS RamDiskLBA;
+
+  Media = This->Media;
+  if(Media->ReadOnly)
+    return EFI_WRITE_PROTECTED;
+
+  if(BufferSize % Media->BlockSize != 0)
+    return EFI_BAD_BUFFER_SIZE;
+
+  if(LBA > Media->LastBlock)
+    return EFI_DEVICE_ERROR;
+
+  if(LBA + BufferSize / Media->BlockSize - 1 > Media->LastBlock)
+    return EFI_DEVICE_ERROR;
+
+  RamDiskDev = RAM_DISK_FROM_THIS(This);
+  RamDiskLBA = RamDiskDev->Start + MultU64x32(LBA,Media->BlockSize);
+  CopyMem((VOID*)(UINTN)RamDiskLBA,Buffer,BufferSize);
+
+  return EFI_SUCCESS;
+}
+
+/* Implementation of block I/O flush */
+STATIC EFI_STATUS RamDiskFlushBlocks(
+  IN EFI_BLOCK_IO *This)
+{
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/Block/ramdisk/ramdisk.h b/Drivers/Block/ramdisk/ramdisk.h
new file mode 100644
index 0000000..398c916
--- /dev/null
+++ b/Drivers/Block/ramdisk/ramdisk.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 1999, 2000
+ * Intel Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. All advertising materials mentioning features or use of this software must
+ *    display the following acknowledgement:
+ *
+ *    This product includes software developed by Intel Corporation and its
+ *    contributors.
+ *
+ * 4. Neither the name of Intel Corporation or its contributors may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _RAMDISK_H_
+#define _RAMDISK_H_
+
+#pragma pack(1)
+/* RAM disk device path structure.
+ * Will use Vendor Messaging Device Path.
+ */
+typedef struct sRAM_DISK_DEVICE_PATH
+{
+  EFI_DEVICE_PATH Header;
+  EFI_GUID        Guid;
+  UINT8           DiskId[8];
+  EFI_DEVICE_PATH EndDevicePath;
+} RAM_DISK_DEVICE_PATH;
+
+/* FAT16 boot sector definition */
+typedef struct sBOOTSEC
+{
+  UINT8  BS_jmpBoot[3];
+  UINT8  BS_OEMName[8];
+  UINT16 BPB_BytsPerSec;
+  UINT8  BPB_SecPerClus;
+  UINT16 BPB_RsvdSecCnt;
+  UINT8  BPB_NumFATs;
+  UINT16 BPB_RootEntCnt;
+  UINT16 BPB_TotSec16;
+  UINT8  BPB_Media;
+  UINT16 BPB_FATSz16;
+  UINT16 BPB_SecPerTrk;
+  UINT16 BPB_NumHeads;
+  UINT32 BPB_HiddSec;
+  UINT32 BPB_TotSec32;
+  UINT8  BS_DrvNum;
+  UINT8  BS_Reserved1;
+  UINT8  BS_BootSig;
+  UINT32 BS_VolID;
+  UINT8  BS_VolLab[11];
+  UINT8  BS_FilSysType[8];
+  UINT8  BS_Code[448];
+  UINT16 BS_Sig;
+} BOOTSEC;
+
+#pragma pack()
+
+/* structure for total sectors to cluster size lookup */
+typedef struct sFAT16TABLE
+{
+  UINTN size;
+  UINT8  spc;
+} FAT16TABLE;
+
+#define PBLOCK_DEVICE_SIGNATURE SIGNATURE_32('r', 'd', 's', 'k')
+
+/* Ramdisk device info structure */
+typedef struct sRAM_DISKDEV
+{
+  UINTN                Signature;
+  EFI_HANDLE           Handle;
+  EFI_PHYSICAL_ADDRESS Start;
+  EFI_BLOCK_IO         BlkIo;
+  EFI_BLOCK_IO_MEDIA   Media;
+  EFI_DEVICE_PATH      *DevicePath;
+} RAM_DISK_DEV;
+
+/* Macro finds the device info structure given a ramdisk BlkIo interface */
+#define RAM_DISK_FROM_THIS(a) CR(a,RAM_DISK_DEV,BlkIo,PBLOCK_DEVICE_SIGNATURE)
+
+/* Prototypes */
+EFI_STATUS InitializeRamDiskDriver(
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable);
+
+STATIC VOID FormatRamdisk(
+  IN VOID*  pStart,
+  IN UINT32 Size);
+
+STATIC EFI_STATUS RamDiskReadBlocks(
+  IN EFI_BLOCK_IO *This,
+  IN UINT32       MediaId,
+  IN EFI_LBA      LBA,
+  IN UINTN        BufferSize,
+  OUT VOID        *Buffer);
+
+STATIC EFI_STATUS RamDiskWriteBlocks(
+  IN EFI_BLOCK_IO *This,
+  IN UINT32       MediaId,
+  IN EFI_LBA      LBA,
+  IN UINTN        BufferSize,
+  IN VOID         *Buffer);
+
+STATIC EFI_STATUS RamDiskFlushBlocks(
+  IN EFI_BLOCK_IO *This);
+
+#endif
+
diff --git a/Drivers/Block/ramdisk/ramdisk.inf b/Drivers/Block/ramdisk/ramdisk.inf
new file mode 100644
index 0000000..de80e32
--- /dev/null
+++ b/Drivers/Block/ramdisk/ramdisk.inf
@@ -0,0 +1,54 @@
+#/*++
+#
+# Copyright (c) 2004, Intel Corporation
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Module Name:
+#
+#
+#Mem.c
+#
+#  Abstract:
+#
+#    Component description file for set cmd reg module.
+#
+#--*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ramdisk
+  FILE_GUID                      = A8D2D6E6-D256-4c7a-B835-D6D1422212DB
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeRamDiskDriver
+
+[Sources]
+  ramdisk.c
+  ramdisk.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/OpenPlatformPkg.dec
+
+[LibraryClasses]
+  MemoryAllocationLib
+  BaseLib
+  UefiLib
+  UefiDriverEntryPoint
+  BaseMemoryLib
+  DebugLib
+  PcdLib
+  UefiBootServicesTableLib
+
+[Protocols]
+  gEfiBlockIoProtocolGuid
+  gEfiLoadedImageProtocolGuid
+[PCD]
+  gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize
diff --git a/Drivers/I2c/Devices/MvEeprom/MvEeprom.c b/Drivers/I2c/Devices/MvEeprom/MvEeprom.c
new file mode 100644
index 0000000..d8fd1bf
--- /dev/null
+++ b/Drivers/I2c/Devices/MvEeprom/MvEeprom.c
@@ -0,0 +1,292 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <Protocol/DriverBinding.h>
+#include <Protocol/I2cIo.h>
+#include <Protocol/Eeprom.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Pi/PiI2c.h>
+
+#include "MvEeprom.h"
+
+#define I2C_DEVICE_INDEX(bus, address) (((address) & 0xffff) | (bus) << 16)
+
+STATIC CONST EFI_GUID I2cGuid = I2C_GUID;
+
+EFI_DRIVER_BINDING_PROTOCOL gDriverBindingProtocol = {
+  MvEepromSupported,
+  MvEepromStart,
+  MvEepromStop
+};
+
+EFI_STATUS
+EFIAPI
+MvEepromSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL            *This,
+  IN EFI_HANDLE                             ControllerHandle,
+  IN EFI_DEVICE_PATH_PROTOCOL               *RemainingDevicePath OPTIONAL
+  )
+{
+  EFI_STATUS Status = EFI_UNSUPPORTED;
+  EFI_I2C_IO_PROTOCOL *TmpI2cIo;
+  UINT8 *EepromAddresses;
+  UINT8 *EepromBuses;
+  UINTN i;
+
+  Status = gBS->OpenProtocol (
+      ControllerHandle,
+      &gEfiI2cIoProtocolGuid,
+      (VOID **) &TmpI2cIo,
+      gImageHandle,
+      ControllerHandle,
+      EFI_OPEN_PROTOCOL_BY_DRIVER
+      );
+  if (EFI_ERROR(Status)) {
+    return EFI_UNSUPPORTED;
+  }
+
+  /* get EEPROM devices' addresses from PCD */
+  EepromAddresses = PcdGetPtr (PcdEepromI2cAddresses);
+  EepromBuses = PcdGetPtr (PcdEepromI2cBuses);
+  if (EepromAddresses == 0) {
+    Status = EFI_UNSUPPORTED;
+    DEBUG((DEBUG_INFO, "MvEepromSupported: I2C device found, but it's not EEPROM\n"));
+    goto out;
+  }
+
+  Status = EFI_UNSUPPORTED;
+  for (i = 0; EepromAddresses[i] != '\0'; i++) {
+    /* I2C guid must fit and valid DeviceIndex must be provided */
+    if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) &&
+        TmpI2cIo->DeviceIndex == I2C_DEVICE_INDEX(EepromBuses[i],
+          EepromAddresses[i])) {
+      DEBUG((DEBUG_INFO, "MvEepromSupported: attached to EEPROM device\n"));
+      Status = EFI_SUCCESS;
+      break;
+    }
+  }
+
+out:
+  gBS->CloseProtocol (
+      ControllerHandle,
+      &gEfiI2cIoProtocolGuid,
+      gImageHandle,
+      ControllerHandle
+      );
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+MvEepromTransfer (
+  IN CONST MARVELL_EEPROM_PROTOCOL *This,
+  IN UINT16 Address,
+  IN UINT32 Length,
+  IN UINT8 *Buffer,
+  IN UINT8 Operation
+  )
+{
+  EFI_I2C_REQUEST_PACKET *RequestPacket;
+  UINTN RequestPacketSize;
+  EFI_STATUS Status = EFI_SUCCESS;
+  EEPROM_CONTEXT *EepromContext = EEPROM_SC_FROM_EEPROM(This);
+  UINT32 BufferLength;
+  UINT32 Transmitted = 0;
+  UINT32 CurrentAddress = Address;
+
+  ASSERT(EepromContext != NULL);
+  ASSERT(EepromContext->I2cIo != NULL);
+
+  RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION) * 2;
+  RequestPacket = AllocateZeroPool (RequestPacketSize);
+  if (RequestPacket == NULL)
+    return EFI_OUT_OF_RESOURCES;
+  /* First operation contains address, the second is buffer */
+  RequestPacket->OperationCount = 2;
+  RequestPacket->Operation[0].LengthInBytes = 2;
+  RequestPacket->Operation[0].Buffer = AllocateZeroPool ( RequestPacket->Operation[0].LengthInBytes );
+  if (RequestPacket->Operation[0].Buffer == NULL) {
+    FreePool(RequestPacket);
+    return EFI_OUT_OF_RESOURCES;
+  }
+  RequestPacket->Operation[1].Flags = (Operation == EEPROM_READ ? I2C_FLAG_READ : I2C_FLAG_NORESTART);
+
+  while (Length > 0) {
+    CurrentAddress = Address + Transmitted;
+    BufferLength = (Length <= MAX_BUFFER_LENGTH ? Length : MAX_BUFFER_LENGTH);
+    RequestPacket->Operation[0].Buffer[0] = (CurrentAddress >> 8) & 0xff;
+    RequestPacket->Operation[0].Buffer[1] = CurrentAddress & 0xff;
+    RequestPacket->Operation[1].LengthInBytes = BufferLength;
+    RequestPacket->Operation[1].Buffer = Buffer + Transmitted;
+    Status = EepromContext->I2cIo->QueueRequest(EepromContext->I2cIo, 0, NULL, RequestPacket, NULL);
+    if (EFI_ERROR(Status)) {
+      DEBUG((DEBUG_ERROR, "MvEepromTransfer: error %d during transmission\n", Status));
+      break;
+    }
+    Length -= BufferLength;
+    Transmitted += BufferLength;
+  }
+
+  FreePool(RequestPacket->Operation[0].Buffer);
+  FreePool(RequestPacket);
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+MvEepromStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL            *This,
+  IN EFI_HANDLE                             ControllerHandle,
+  IN EFI_DEVICE_PATH_PROTOCOL               *RemainingDevicePath OPTIONAL
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  EEPROM_CONTEXT *EepromContext;
+
+  EepromContext = AllocateZeroPool (sizeof(EEPROM_CONTEXT));
+  if (EepromContext == NULL) {
+    DEBUG((DEBUG_ERROR, "MvEeprom: allocation fail\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  EepromContext->ControllerHandle = ControllerHandle;
+  EepromContext->Signature = EEPROM_SIGNATURE;
+  EepromContext->EepromProtocol.Transfer = MvEepromTransfer;
+
+  Status = gBS->OpenProtocol (
+      ControllerHandle,
+      &gEfiI2cIoProtocolGuid,
+      (VOID **) &EepromContext->I2cIo,
+      gImageHandle,
+      ControllerHandle,
+      EFI_OPEN_PROTOCOL_BY_DRIVER
+      );
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "MvEeprom: failed to open I2cIo\n"));
+    FreePool(EepromContext);
+    return EFI_UNSUPPORTED;
+  }
+
+  EepromContext->EepromProtocol.Identifier = EepromContext->I2cIo->DeviceIndex;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+      &ControllerHandle,
+      &gMarvellEepromProtocolGuid, &EepromContext->EepromProtocol,
+      NULL
+      );
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "MvEeprom: failed to install EEPROM protocol\n"));
+    goto fail;
+  }
+
+  return Status;
+
+fail:
+  FreePool(EepromContext);
+  gBS->CloseProtocol (
+      ControllerHandle,
+      &gEfiI2cIoProtocolGuid,
+      gImageHandle,
+      ControllerHandle
+      );
+
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+MvEepromStop (
+  IN EFI_DRIVER_BINDING_PROTOCOL            *This,
+  IN  EFI_HANDLE                            ControllerHandle,
+  IN  UINTN                                 NumberOfChildren,
+  IN  EFI_HANDLE                            *ChildHandleBuffer OPTIONAL
+  )
+{
+  MARVELL_EEPROM_PROTOCOL *EepromProtocol;
+  EFI_STATUS Status;
+  EEPROM_CONTEXT *EepromContext;
+
+  Status = gBS->OpenProtocol (
+                  ControllerHandle,
+                  &gMarvellEepromProtocolGuid,
+                  (VOID **) &EepromProtocol,
+                  This->DriverBindingHandle,
+                  ControllerHandle,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+
+  if (EFI_ERROR (Status)) {
+    return EFI_DEVICE_ERROR;
+  }
+  EepromContext = EEPROM_SC_FROM_EEPROM(EepromProtocol);
+
+  gBS->UninstallMultipleProtocolInterfaces (
+      &ControllerHandle,
+      &gMarvellEepromProtocolGuid, &EepromContext->EepromProtocol,
+      &gEfiDriverBindingProtocolGuid, &gDriverBindingProtocol,
+      NULL
+      );
+  gBS->CloseProtocol (
+      ControllerHandle,
+      &gEfiI2cIoProtocolGuid,
+      gImageHandle,
+      ControllerHandle
+      );
+  FreePool(EepromContext);
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvEepromInitialise (
+  IN EFI_HANDLE  ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS Status;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+      &ImageHandle,
+      &gEfiDriverBindingProtocolGuid, &gDriverBindingProtocol,
+      NULL
+      );
+  return Status;
+}
diff --git a/Drivers/I2c/Devices/MvEeprom/MvEeprom.h b/Drivers/I2c/Devices/MvEeprom/MvEeprom.h
new file mode 100644
index 0000000..b1af645
--- /dev/null
+++ b/Drivers/I2c/Devices/MvEeprom/MvEeprom.h
@@ -0,0 +1,103 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MV_EEPROM_H__
+#define __MV_EEPROM_H__
+
+#include <Uefi.h>
+
+#define EEPROM_SIGNATURE          SIGNATURE_32 ('E', 'E', 'P', 'R')
+
+#define MAX_BUFFER_LENGTH 64
+
+/*
+ * I2C_FLAG_NORESTART is not part of PI spec, it allows to continue
+ * transmission without repeated start operation.
+ * FIXME: This flag is also defined in Drivers/I2c/MvI2cDxe/MvI2cDxe.h
+ * and it's important to have both version synced. This solution is
+ * temporary and shared flag should be used by both files.
+ * Situation is analogous with I2C_GUID, which also should be common, but is
+ * for now defined same way in two header files.
+ */
+#define I2C_FLAG_NORESTART 0x00000002
+#define I2C_GUID \
+  { \
+  0xadc1901b, 0xb83c, 0x4831, { 0x8f, 0x59, 0x70, 0x89, 0x8f, 0x26, 0x57, 0x1e } \
+  }
+
+typedef struct {
+  UINT32  Signature;
+  EFI_HANDLE ControllerHandle;
+  EFI_I2C_IO_PROTOCOL *I2cIo;
+  MARVELL_EEPROM_PROTOCOL EepromProtocol;
+} EEPROM_CONTEXT;
+
+#define EEPROM_SC_FROM_IO(a) CR (a, EEPROM_CONTEXT, I2cIo, EEPROM_SIGNATURE)
+#define EEPROM_SC_FROM_EEPROM(a) CR (a, EEPROM_CONTEXT, EepromProtocol, EEPROM_SIGNATURE)
+
+EFI_STATUS
+EFIAPI
+MvEepromSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL            *This,
+  IN EFI_HANDLE                             ControllerHandle,
+  IN EFI_DEVICE_PATH_PROTOCOL               *RemainingDevicePath OPTIONAL
+  );
+
+EFI_STATUS
+EFIAPI
+MvEepromStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL            *This,
+  IN EFI_HANDLE                             ControllerHandle,
+  IN EFI_DEVICE_PATH_PROTOCOL               *RemainingDevicePath OPTIONAL
+  );
+
+EFI_STATUS
+EFIAPI
+MvEepromStop (
+  IN EFI_DRIVER_BINDING_PROTOCOL            *This,
+  IN  EFI_HANDLE                            ControllerHandle,
+  IN  UINTN                                 NumberOfChildren,
+  IN  EFI_HANDLE                            *ChildHandleBuffer OPTIONAL
+  );
+
+EFI_STATUS
+EFIAPI
+MvEepromTransfer (
+  IN CONST MARVELL_EEPROM_PROTOCOL *This,
+  IN UINT16 Address,
+  IN UINT32 Length,
+  IN UINT8 *Buffer,
+  IN UINT8 Operation
+  );
+#endif // __MV_EEPROM_H__
diff --git a/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf b/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
new file mode 100644
index 0000000..219041b
--- /dev/null
+++ b/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
@@ -0,0 +1,70 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MvEeprom
+  FILE_GUID                      = 59fc3843-d8d4-40aa-ae07-38967138509c
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = MvEepromInitialise
+
+[Sources.common]
+  MvEeprom.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  IoLib
+  PcdLib
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  UefiLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+
+[Protocols]
+  gEfiI2cIoProtocolGuid
+  gEfiDriverBindingProtocolGuid
+  gMarvellEepromProtocolGuid
+
+[Pcd]
+  gMarvellTokenSpaceGuid.PcdEepromI2cAddresses
+  gMarvellTokenSpaceGuid.PcdEepromI2cBuses
+
+[Depex]
+  TRUE
diff --git a/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Drivers/I2c/MvI2cDxe/MvI2cDxe.c
new file mode 100755
index 0000000..fa79ebc
--- /dev/null
+++ b/Drivers/I2c/MvI2cDxe/MvI2cDxe.c
@@ -0,0 +1,740 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <Protocol/I2cMaster.h>
+#include <Protocol/I2cEnumerate.h>
+#include <Protocol/I2cBusConfigurationManagement.h>
+#include <Protocol/DevicePath.h>
+
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/ParsePcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "MvI2cDxe.h"
+
+STATIC MV_I2C_BAUD_RATE baud_rate;
+
+STATIC MV_I2C_DEVICE_PATH MvI2cDevicePathProtocol = {
+  {
+    {
+      HARDWARE_DEVICE_PATH,
+      HW_VENDOR_DP,
+      {
+  (UINT8) (sizeof(VENDOR_DEVICE_PATH)),
+  (UINT8) (sizeof(VENDOR_DEVICE_PATH) >> 8),
+      },
+    },
+    EFI_CALLER_ID_GUID
+  },
+  {
+    END_DEVICE_PATH_TYPE,
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    {
+      sizeof(EFI_DEVICE_PATH_PROTOCOL),
+      0
+    }
+  }
+};
+
+STATIC
+UINT32
+I2C_READ(
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINTN off)
+{
+  ASSERT (I2cMasterContext != NULL);
+  return MmioRead32 (I2cMasterContext->BaseAddress + off);
+}
+
+STATIC
+EFI_STATUS
+I2C_WRITE (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINTN off,
+  IN UINT32 Value)
+{
+  ASSERT (I2cMasterContext != NULL);
+  return MmioWrite32 (I2cMasterContext->BaseAddress + off, Value);
+}
+
+EFI_STATUS
+EFIAPI
+MvI2cInitialiseController (
+  IN EFI_HANDLE  ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable,
+  IN EFI_PHYSICAL_ADDRESS BaseAddress
+  )
+{
+  EFI_STATUS Status;
+  I2C_MASTER_CONTEXT *I2cMasterContext;
+  STATIC INTN Bus = 0;
+  MV_I2C_DEVICE_PATH *DevicePath;
+
+  DevicePath = AllocateCopyPool (sizeof(MvI2cDevicePathProtocol),
+                                 &MvI2cDevicePathProtocol);
+  if (DevicePath == NULL) {
+    DEBUG((DEBUG_ERROR, "MvI2cDxe: I2C device path allocation failed\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+  DevicePath->Guid.Guid.Data4[0] = Bus;
+
+  /* if attachment succeeds, this gets freed at ExitBootServices */
+  I2cMasterContext = AllocateZeroPool (sizeof (I2C_MASTER_CONTEXT));
+  if (I2cMasterContext == NULL) {
+    DEBUG((DEBUG_ERROR, "MvI2cDxe: I2C master context allocation failed\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+  I2cMasterContext->Signature = I2C_MASTER_SIGNATURE;
+  I2cMasterContext->I2cMaster.Reset = MvI2cReset;
+  I2cMasterContext->I2cMaster.StartRequest = MvI2cStartRequest;
+  I2cMasterContext->I2cEnumerate.Enumerate = MvI2cEnumerate;
+  I2cMasterContext->I2cBusConf.EnableI2cBusConfiguration = MvI2cEnableConf;
+  I2cMasterContext->TclkFrequency = PcdGet32 (PcdI2cClockFrequency);
+  I2cMasterContext->BaseAddress = BaseAddress;
+  I2cMasterContext->Bus = Bus;
+  /* I2cMasterContext->Lock is responsible for serializing I2C operations */
+  EfiInitializeLock(&I2cMasterContext->Lock, TPL_NOTIFY);
+
+  MvI2cCalBaudRate( I2cMasterContext,
+                    PcdGet32 (PcdI2cBaudRate),
+                    &baud_rate,
+                    I2cMasterContext->TclkFrequency
+                  );
+
+  Status = gBS->InstallMultipleProtocolInterfaces(
+      &I2cMasterContext->Controller,
+      &gEfiI2cMasterProtocolGuid,
+      &I2cMasterContext->I2cMaster,
+      &gEfiI2cEnumerateProtocolGuid,
+      &I2cMasterContext->I2cEnumerate,
+      &gEfiI2cBusConfigurationManagementProtocolGuid,
+      &I2cMasterContext->I2cBusConf,
+      &gEfiDevicePathProtocolGuid,
+      (EFI_DEVICE_PATH_PROTOCOL *) DevicePath,
+      NULL);
+
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "MvI2cDxe: Installing protocol interfaces failed!\n"));
+    goto fail;
+  }
+  DEBUG((DEBUG_ERROR, "Succesfully installed controller %d at 0x%llx\n", Bus,
+        I2cMasterContext->BaseAddress));
+
+  Bus++;
+
+  return EFI_SUCCESS;
+
+fail:
+  FreePool(I2cMasterContext);
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+MvI2cInitialise (
+  IN EFI_HANDLE  ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS Status;
+  UINT32 BusCount;
+  EFI_PHYSICAL_ADDRESS I2cBaseAddresses[PcdGet32 (PcdI2cBusCount)];
+  INTN i;
+
+  BusCount = PcdGet32 (PcdI2cBusCount);
+  if (BusCount == 0)
+    return EFI_SUCCESS;
+
+  Status = ParsePcdString (
+      (CHAR16 *) PcdGetPtr (PcdI2cBaseAddresses),
+      BusCount,
+      I2cBaseAddresses,
+      NULL
+      );
+  if (EFI_ERROR(Status))
+    return Status;
+
+  for (i = 0; i < BusCount; i++) {
+    Status = MvI2cInitialiseController(
+        ImageHandle,
+        SystemTable,
+        I2cBaseAddresses[i]
+        );
+    if (EFI_ERROR(Status))
+      return Status;
+  }
+
+  return Status;
+}
+
+STATIC
+VOID
+MvI2cControlClear (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINT32 Mask)
+{
+  UINT32 Value;
+
+  /* clears given bits in I2C_CONTROL register */
+  Value = I2C_READ(I2cMasterContext, I2C_CONTROL);
+  Value &= ~Mask;
+  I2C_WRITE(I2cMasterContext, I2C_CONTROL, Value);
+}
+
+STATIC
+VOID
+MvI2cControlSet (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINT32 Mask)
+{
+  UINT32 Value;
+
+  /* sets given bits in I2C_CONTROL register */
+  Value = I2C_READ(I2cMasterContext, I2C_CONTROL);
+  Value |= Mask;
+  I2C_WRITE(I2cMasterContext, I2C_CONTROL, Value);
+}
+
+STATIC
+VOID
+MvI2cClearIflg (
+ IN I2C_MASTER_CONTEXT *I2cMasterContext
+ )
+{
+  gBS->Stall(I2C_OPERATION_TIMEOUT);
+  MvI2cControlClear(I2cMasterContext, I2C_CONTROL_IFLG);
+  gBS->Stall(I2C_OPERATION_TIMEOUT);
+}
+
+/* Timeout is given in us */
+STATIC
+UINTN
+MvI2cPollCtrl (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINTN Timeout,
+  IN UINT32 Mask)
+{
+  Timeout /= 10;
+  while (!(I2C_READ(I2cMasterContext, I2C_CONTROL) & Mask)) {
+    gBS->Stall(10);
+    if (--Timeout == 0)
+      return (Timeout);
+  }
+  return (0);
+}
+
+/*
+ * 'Timeout' is given in us. Note also that Timeout handling is not exact --
+ * MvI2cLockedStart() total wait can be more than 2 x Timeout
+ * (MvI2cPollCtrl() is called twice). 'Mask' can be either I2C_STATUS_START
+ * or I2C_STATUS_RPTD_START
+ */
+STATIC
+EFI_STATUS
+MvI2cLockedStart (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN INT32 Mask,
+  IN UINT8 Slave,
+  IN UINTN Timeout
+  )
+{
+  UINTN ReadAccess, IflgSet = 0;
+  UINT32 I2cStatus;
+
+  if (Mask == I2C_STATUS_RPTD_START) {
+    /* read IFLG to know if it should be cleared later */
+    IflgSet = I2C_READ(I2cMasterContext, I2C_CONTROL) & I2C_CONTROL_IFLG;
+  }
+
+  MvI2cControlSet(I2cMasterContext, I2C_CONTROL_START);
+
+  if (Mask == I2C_STATUS_RPTD_START && IflgSet) {
+    DEBUG((DEBUG_INFO, "MvI2cDxe: IFLG set, clearing\n"));
+    MvI2cClearIflg(I2cMasterContext);
+  }
+
+  /* Without this delay we Timeout checking IFLG if the Timeout is 0 */
+  gBS->Stall(I2C_OPERATION_TIMEOUT);
+
+  if (MvI2cPollCtrl(I2cMasterContext, Timeout, I2C_CONTROL_IFLG)) {
+    DEBUG((DEBUG_ERROR, "MvI2cDxe: Timeout sending %sSTART condition\n",
+        Mask == I2C_STATUS_START ? "" : "repeated "));
+    return EFI_NO_RESPONSE;
+  }
+
+  I2cStatus = I2C_READ(I2cMasterContext, I2C_STATUS);
+  if (I2cStatus != Mask) {
+    DEBUG((DEBUG_ERROR, "MvI2cDxe: wrong I2cStatus (%02x) after sending %sSTART condition\n",
+        I2cStatus, Mask == I2C_STATUS_START ? "" : "repeated "));
+    return EFI_DEVICE_ERROR;
+  }
+
+  I2C_WRITE(I2cMasterContext, I2C_DATA, Slave);
+  gBS->Stall(I2C_OPERATION_TIMEOUT);
+  MvI2cClearIflg(I2cMasterContext);
+
+  if (MvI2cPollCtrl(I2cMasterContext, Timeout, I2C_CONTROL_IFLG)) {
+    DEBUG((DEBUG_ERROR, "MvI2cDxe: Timeout sending Slave address\n"));
+    return EFI_NO_RESPONSE;
+  }
+
+  ReadAccess = (Slave & 0x1) ? 1 : 0;
+  I2cStatus = I2C_READ(I2cMasterContext, I2C_STATUS);
+  if (I2cStatus != (ReadAccess ?
+      I2C_STATUS_ADDR_R_ACK : I2C_STATUS_ADDR_W_ACK)) {
+    DEBUG((DEBUG_ERROR, "MvI2cDxe: no ACK (I2cStatus: %02x) after sending Slave address\n",
+        I2cStatus));
+    return EFI_NO_RESPONSE;
+  }
+
+  return EFI_SUCCESS;
+}
+
+#define  ABSSUB(a,b)  (((a) > (b)) ? (a) - (b) : (b) - (a))
+STATIC
+VOID
+MvI2cCalBaudRate (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN CONST UINT32 target,
+  IN OUT MV_I2C_BAUD_RATE *rate,
+  UINT32 clk
+  )
+{
+  UINT32 cur, diff, diff0, baud;
+  UINTN m, n, m0, n0;
+
+  /* Read initial m0, n0 values from register */
+  baud = I2C_READ(I2cMasterContext, I2C_BAUD_RATE);
+  m0 = I2C_M_FROM_BAUD(baud);
+  n0 = I2C_N_FROM_BAUD(baud);
+  /* Calculate baud rate. */
+  diff0 = 0xffffffff;
+
+  for (n = 0; n < 8; n++) {
+    for (m = 0; m < 16; m++) {
+      cur = I2C_BAUD_RATE_RAW(clk,m,n);
+      diff = ABSSUB(target, cur);
+      if (diff < diff0) {
+        m0 = m;
+        n0 = n;
+        diff0 = diff;
+      }
+    }
+  }
+  rate->raw = I2C_BAUD_RATE_RAW(clk, m0, n0);
+  rate->param = I2C_BAUD_RATE_PARAM(m0, n0);
+  rate->m = m0;
+  rate->n = n0;
+}
+
+EFI_STATUS
+EFIAPI
+MvI2cReset (
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This
+  )
+{
+  UINT32 param;
+  I2C_MASTER_CONTEXT *I2cMasterContext = I2C_SC_FROM_MASTER(This);
+
+  param = baud_rate.param;
+
+  EfiAcquireLock (&I2cMasterContext->Lock);
+  I2C_WRITE(I2cMasterContext, I2C_SOFT_RESET, 0x0);
+  gBS->Stall(2 * I2C_OPERATION_TIMEOUT);
+  I2C_WRITE(I2cMasterContext, I2C_BAUD_RATE, param);
+  I2C_WRITE(I2cMasterContext, I2C_CONTROL, I2C_CONTROL_I2CEN | I2C_CONTROL_ACK);
+  gBS->Stall(I2C_OPERATION_TIMEOUT);
+  EfiReleaseLock (&I2cMasterContext->Lock);
+
+  return EFI_SUCCESS;
+}
+
+/*
+ * Timeout is given in us
+ */
+STATIC
+EFI_STATUS
+MvI2cRepeatedStart (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINT8 Slave,
+  IN UINTN Timeout
+  )
+{
+  EFI_STATUS Status;
+
+  EfiAcquireLock (&I2cMasterContext->Lock);
+  Status = MvI2cLockedStart(I2cMasterContext, I2C_STATUS_RPTD_START, Slave,
+      Timeout);
+  EfiReleaseLock (&I2cMasterContext->Lock);
+
+  if (EFI_ERROR(Status)) {
+    MvI2cStop(I2cMasterContext);
+  }
+  return Status;
+}
+
+/*
+ * Timeout is given in us
+ */
+STATIC
+EFI_STATUS
+MvI2cStart (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINT8 Slave,
+  IN UINTN Timeout
+  )
+{
+  EFI_STATUS Status;
+
+  EfiAcquireLock (&I2cMasterContext->Lock);
+  Status = MvI2cLockedStart(I2cMasterContext, I2C_STATUS_START, Slave, Timeout);
+  EfiReleaseLock (&I2cMasterContext->Lock);
+
+  if (EFI_ERROR(Status)) {
+    MvI2cStop(I2cMasterContext);
+  }
+  return Status;
+}
+
+STATIC
+EFI_STATUS
+MvI2cStop (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext
+  )
+{
+  EfiAcquireLock (&I2cMasterContext->Lock);
+  MvI2cControlSet(I2cMasterContext, I2C_CONTROL_STOP);
+  gBS->Stall(I2C_OPERATION_TIMEOUT);
+  MvI2cClearIflg(I2cMasterContext);
+  EfiReleaseLock (&I2cMasterContext->Lock);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+MvI2cRead (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN OUT UINT8 *Buf,
+  IN UINTN Length,
+  IN OUT UINTN *read,
+  IN UINTN last,
+  IN UINTN delay
+  )
+{
+  UINT32 I2cStatus;
+  UINTN LastByte;
+  EFI_STATUS Status;
+
+  EfiAcquireLock (&I2cMasterContext->Lock);
+  *read = 0;
+  while (*read < Length) {
+    /*
+     * Check if we are reading last byte of the last Buffer,
+     * do not send ACK then, per I2C specs
+     */
+    LastByte = ((*read == Length - 1) && last) ? 1 : 0;
+    if (LastByte)
+      MvI2cControlClear(I2cMasterContext, I2C_CONTROL_ACK);
+    else
+      MvI2cControlSet(I2cMasterContext, I2C_CONTROL_ACK);
+
+    gBS->Stall (I2C_OPERATION_TIMEOUT);
+    MvI2cClearIflg(I2cMasterContext);
+
+    if (MvI2cPollCtrl(I2cMasterContext, delay, I2C_CONTROL_IFLG)) {
+      DEBUG((DEBUG_ERROR, "MvI2cDxe: Timeout reading data\n"));
+      Status = EFI_NO_RESPONSE;
+      goto out;
+    }
+
+    I2cStatus = I2C_READ(I2cMasterContext, I2C_STATUS);
+    if (I2cStatus != (LastByte ?
+        I2C_STATUS_DATA_RD_NOACK : I2C_STATUS_DATA_RD_ACK)) {
+      DEBUG((DEBUG_ERROR, "MvI2cDxe: wrong I2cStatus (%02x) while reading\n", I2cStatus));
+      Status = EFI_DEVICE_ERROR;
+      goto out;
+    }
+
+    *Buf++ = I2C_READ(I2cMasterContext, I2C_DATA);
+    (*read)++;
+  }
+  Status = EFI_SUCCESS;
+out:
+  EfiReleaseLock (&I2cMasterContext->Lock);
+  return (Status);
+}
+
+STATIC
+EFI_STATUS
+MvI2cWrite (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN OUT CONST UINT8 *Buf,
+  IN UINTN Length,
+  IN OUT UINTN *Sent,
+  IN UINTN Timeout
+  )
+{
+  UINT32 status;
+  EFI_STATUS Status;
+
+  EfiAcquireLock (&I2cMasterContext->Lock);
+  *Sent = 0;
+  while (*Sent < Length) {
+    I2C_WRITE(I2cMasterContext, I2C_DATA, *Buf++);
+
+    MvI2cClearIflg(I2cMasterContext);
+    if (MvI2cPollCtrl(I2cMasterContext, Timeout, I2C_CONTROL_IFLG)) {
+      DEBUG((DEBUG_ERROR, "MvI2cDxe: Timeout writing data\n"));
+      Status = EFI_NO_RESPONSE;
+      goto out;
+    }
+
+    status = I2C_READ(I2cMasterContext, I2C_STATUS);
+    if (status != I2C_STATUS_DATA_WR_ACK) {
+      DEBUG((DEBUG_ERROR, "MvI2cDxe: wrong status (%02x) while writing\n", status));
+      Status = EFI_DEVICE_ERROR;
+      goto out;
+    }
+    (*Sent)++;
+  }
+  Status = EFI_SUCCESS;
+out:
+  EfiReleaseLock (&I2cMasterContext->Lock);
+  return (Status);
+}
+
+/*
+ * MvI2cStartRequest should be called only by I2cHost.
+ * I2C device drivers ought to use EFI_I2C_IO_PROTOCOL instead.
+ */
+STATIC
+EFI_STATUS
+MvI2cStartRequest (
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+  IN UINTN                         SlaveAddress,
+  IN EFI_I2C_REQUEST_PACKET        *RequestPacket,
+  IN EFI_EVENT                     Event      OPTIONAL,
+  OUT EFI_STATUS                   *I2cStatus OPTIONAL
+  )
+{
+  UINTN Count;
+  UINTN ReadMode;
+  UINTN Transmitted;
+  I2C_MASTER_CONTEXT *I2cMasterContext = I2C_SC_FROM_MASTER(This);
+  EFI_I2C_OPERATION *Operation;
+
+  ASSERT (RequestPacket != NULL);
+  ASSERT (I2cMasterContext != NULL);
+
+  for (Count = 0; Count < RequestPacket->OperationCount; Count++) {
+    Operation = &RequestPacket->Operation[Count];
+    ReadMode = Operation->Flags & I2C_FLAG_READ;
+
+    if (Count == 0) {
+      MvI2cStart ( I2cMasterContext,
+                   (SlaveAddress << 1) | ReadMode,
+                   I2C_TRANSFER_TIMEOUT
+                 );
+    } else if (!(Operation->Flags & I2C_FLAG_NORESTART)) {
+      MvI2cRepeatedStart ( I2cMasterContext,
+                           (SlaveAddress << 1) | ReadMode,
+                           I2C_TRANSFER_TIMEOUT
+                         );
+    }
+
+    if (ReadMode) {
+      MvI2cRead ( I2cMasterContext,
+                  Operation->Buffer,
+                  Operation->LengthInBytes,
+                  &Transmitted,
+                  Count == 1,
+                  I2C_TRANSFER_TIMEOUT
+                 );
+    } else {
+      MvI2cWrite ( I2cMasterContext,
+                   Operation->Buffer,
+                   Operation->LengthInBytes,
+                   &Transmitted,
+                   I2C_TRANSFER_TIMEOUT
+                  );
+    }
+    if (Count == RequestPacket->OperationCount - 1) {
+      MvI2cStop ( I2cMasterContext );
+    }
+  }
+
+  if (I2cStatus != NULL)
+    I2cStatus = EFI_SUCCESS;
+  if (Event != NULL)
+    gBS->SignalEvent(Event);
+  return EFI_SUCCESS;
+}
+
+STATIC CONST EFI_GUID DevGuid = I2C_GUID;
+
+#define I2C_DEVICE_INDEX(bus, address) (((address) & 0xffff) | (bus) << 16)
+#define I2C_DEVICE_ADDRESS(index) ((index) & 0xffff)
+
+STATIC
+EFI_STATUS
+MvI2cAllocDevice (
+  IN UINT8 SlaveAddress,
+  IN UINT8 Bus,
+  IN OUT CONST EFI_I2C_DEVICE **Device
+  )
+{
+  EFI_STATUS Status;
+  EFI_I2C_DEVICE *Dev;
+  UINT32 *TmpSlaveArray;
+  EFI_GUID *TmpGuidP;
+
+  Status = gBS->AllocatePool ( EfiBootServicesData,
+             sizeof(EFI_I2C_DEVICE),
+             (VOID **) &Dev );
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "MvI2cDxe: I2C device memory allocation failed\n"));
+    return Status;
+  }
+  *Device = Dev;
+  Dev->DeviceIndex = SlaveAddress;
+  Dev->DeviceIndex = I2C_DEVICE_INDEX(Bus, SlaveAddress);
+  Dev->SlaveAddressCount = 1;
+  Dev->I2cBusConfiguration = 0;
+  Status = gBS->AllocatePool ( EfiBootServicesData,
+             sizeof(UINT32),
+             (VOID **) &TmpSlaveArray);
+  if (EFI_ERROR(Status)) {
+    goto fail1;
+  }
+  TmpSlaveArray[0] = SlaveAddress;
+  Dev->SlaveAddressArray = TmpSlaveArray;
+
+  Status = gBS->AllocatePool ( EfiBootServicesData,
+             sizeof(EFI_GUID),
+             (VOID **) &TmpGuidP);
+  if (EFI_ERROR(Status)) {
+    goto fail2;
+  }
+  *TmpGuidP = DevGuid;
+  Dev->DeviceGuid = TmpGuidP;
+
+  DEBUG((DEBUG_INFO, "MvI2c: allocated device with address %x\n", (UINTN)SlaveAddress));
+  return EFI_SUCCESS;
+
+fail2:
+  FreePool(TmpSlaveArray);
+fail1:
+  FreePool(Dev);
+
+  return Status;
+}
+
+/*
+ * It is called by I2cBus to enumerate devices on I2C bus. In this case,
+ * enumeration is based on PCD configuration - all Slave addresses specified
+ * in PCD get their corresponding EFI_I2C_DEVICE structures here.
+ *
+ * After enumeration succeeds, Supported() function of drivers that installed
+ * DriverBinding protocol is called.
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+MvI2cEnumerate (
+  IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This,
+  IN OUT CONST EFI_I2C_DEVICE         **Device
+  )
+{
+  UINT8 *DevicesPcd;
+  UINT8 *DeviceBusPcd;
+  UINTN Index, NextIndex, DevCount;
+  UINT8 NextDeviceAddress;
+  I2C_MASTER_CONTEXT *I2cMasterContext = I2C_SC_FROM_ENUMERATE(This);
+
+  DevCount = PcdGetSize (PcdI2cSlaveAddresses);
+  DevicesPcd = PcdGetPtr (PcdI2cSlaveAddresses);
+  DeviceBusPcd = PcdGetPtr (PcdI2cSlaveBuses);
+  if (*Device == NULL) {
+    for (Index = 0; Index < DevCount ; Index++) {
+      if (DeviceBusPcd[Index] != I2cMasterContext->Bus)
+        continue;
+      if (Index < DevCount)
+        MvI2cAllocDevice (DevicesPcd[Index], I2cMasterContext->Bus, Device);
+      return EFI_SUCCESS;
+    }
+  } else {
+    /* Device is not NULL, so something was already allocated */
+    for (Index = 0; Index < DevCount; Index++) {
+      if (DeviceBusPcd[Index] != I2cMasterContext->Bus)
+        continue;
+      if (DevicesPcd[Index] == I2C_DEVICE_ADDRESS((*Device)->DeviceIndex)) {
+        for (NextIndex = Index + 1; NextIndex < DevCount; NextIndex++) {
+          if (DeviceBusPcd[NextIndex] != I2cMasterContext->Bus)
+            continue;
+          NextDeviceAddress = DevicesPcd[NextIndex];
+          if (NextIndex < DevCount)
+            MvI2cAllocDevice(NextDeviceAddress, I2cMasterContext->Bus, Device);
+          return EFI_SUCCESS;
+        }
+      }
+    }
+    *Device = NULL;
+    return EFI_SUCCESS;
+  }
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+MvI2cEnableConf (
+  IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This,
+  IN UINTN                                               I2cBusConfiguration,
+  IN EFI_EVENT                                           Event      OPTIONAL,
+  IN EFI_STATUS                                          *I2cStatus OPTIONAL
+  )
+{
+  /* do nothing */
+  if (I2cStatus != NULL)
+    I2cStatus = EFI_SUCCESS;
+  if (Event != NULL)
+    gBS->SignalEvent(Event);
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/I2c/MvI2cDxe/MvI2cDxe.h b/Drivers/I2c/MvI2cDxe/MvI2cDxe.h
new file mode 100644
index 0000000..028fd54
--- /dev/null
+++ b/Drivers/I2c/MvI2cDxe/MvI2cDxe.h
@@ -0,0 +1,269 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MV_I2C_H__
+#define __MV_I2C_H__
+
+#include <Uefi.h>
+
+#define I2C_BASE_ADDRESS    0xf0511000
+
+#define I2C_SLAVE_ADDR    0x00
+#define I2C_EXT_SLAVE_ADDR  0x10
+#define I2C_DATA    0x04
+
+#define I2C_CONTROL    0x08
+#define I2C_CONTROL_ACK  (1 << 2)
+#define I2C_CONTROL_IFLG  (1 << 3)
+#define I2C_CONTROL_STOP  (1 << 4)
+#define I2C_CONTROL_START  (1 << 5)
+#define I2C_CONTROL_I2CEN  (1 << 6)
+#define I2C_CONTROL_INTEN  (1 << 7)
+
+#define I2C_STATUS      0x0c
+#define I2C_STATUS_START    0x08
+#define I2C_STATUS_RPTD_START    0x10
+#define I2C_STATUS_ADDR_W_ACK    0x18
+#define I2C_STATUS_DATA_WR_ACK    0x28
+#define I2C_STATUS_ADDR_R_ACK    0x40
+#define I2C_STATUS_DATA_RD_ACK    0x50
+#define I2C_STATUS_DATA_RD_NOACK  0x58
+
+#define I2C_BAUD_RATE    0x0c
+#define I2C_BAUD_RATE_PARAM(M,N)  ((((M) << 3) | ((N) & 0x7)) & 0x7f)
+#define I2C_BAUD_RATE_RAW(C,M,N)  ((C)/((10*(M+1))<<(N+1)))
+#define I2C_M_FROM_BAUD(baud)     (((baud) >> 3) & 0xf)
+#define I2C_N_FROM_BAUD(baud)     ((baud) & 0x7)
+
+#define I2C_SOFT_RESET    0x1c
+#define I2C_TRANSFER_TIMEOUT 10000
+#define I2C_OPERATION_TIMEOUT 1000
+
+#define I2C_UNKNOWN        0x0
+#define I2C_SLOW           0x1
+#define I2C_FAST           0x2
+#define I2C_FASTEST        0x3
+
+/*
+ * I2C_FLAG_NORESTART is not part of PI spec, it allows to continue
+ * transmission without repeated start operation.
+ * FIXME: This flag is also defined in
+ * Platforms/Marvell/Include/Protocol/Eeprom.h and it's important to have both
+ * version synced. This solution is temporary and shared flag should be used by
+ * both files.
+ * Situation is analogous with I2C_GUID, which also should be common, but is
+ * for now defined same way in two header files.
+ */
+#define I2C_FLAG_NORESTART 0x00000002
+#define I2C_GUID \
+  { \
+  0xadc1901b, 0xb83c, 0x4831, { 0x8f, 0x59, 0x70, 0x89, 0x8f, 0x26, 0x57, 0x1e } \
+  }
+
+#define I2C_MASTER_SIGNATURE          SIGNATURE_32 ('I', '2', 'C', 'M')
+
+typedef struct {
+  UINT32      Signature;
+  EFI_HANDLE  Controller;
+  EFI_LOCK    Lock;
+  UINTN       TclkFrequency;
+  UINTN       BaseAddress;
+  INTN        Bus;
+  EFI_I2C_MASTER_PROTOCOL I2cMaster;
+  EFI_I2C_ENUMERATE_PROTOCOL I2cEnumerate;
+  EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL I2cBusConf;
+} I2C_MASTER_CONTEXT;
+
+#define I2C_SC_FROM_MASTER(a) CR (a, I2C_MASTER_CONTEXT, I2cMaster, I2C_MASTER_SIGNATURE)
+#define I2C_SC_FROM_ENUMERATE(a) CR (a, I2C_MASTER_CONTEXT, I2cEnumerate, I2C_MASTER_SIGNATURE)
+#define I2C_SC_FROM_BUSCONF(a) CR (a, I2C_MASTER_CONTEXT, I2cBusConf, I2C_MASTER_SIGNATURE)
+
+typedef struct {
+  UINT32  raw;
+  UINTN    param;
+  UINTN    m;
+  UINTN    n;
+} MV_I2C_BAUD_RATE;
+
+typedef struct {
+  VENDOR_DEVICE_PATH            Guid;
+  EFI_DEVICE_PATH_PROTOCOL      End;
+} MV_I2C_DEVICE_PATH;
+
+STATIC
+UINT32
+I2C_READ(
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINTN off
+  );
+
+STATIC
+EFI_STATUS
+I2C_WRITE (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINTN off,
+  IN UINT32 val
+  );
+
+EFI_STATUS
+EFIAPI
+MvI2cInitialise (
+  IN EFI_HANDLE ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  );
+
+STATIC
+VOID
+MvI2cControlClear (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINT32 mask
+  );
+
+STATIC
+VOID
+MvI2cControlSet (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINT32 mask
+  );
+
+STATIC
+VOID
+MvI2cClearIflg (
+ IN I2C_MASTER_CONTEXT *I2cMasterContext
+ );
+STATIC
+UINTN
+MvI2cPollCtrl (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINTN timeout,
+  IN UINT32 mask
+  );
+
+STATIC
+EFI_STATUS
+MvI2cLockedStart (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN INT32 mask,
+  IN UINT8 slave,
+  IN UINTN timeout
+  );
+
+STATIC
+VOID
+MvI2cCalBaudRate (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN CONST UINT32 target,
+  IN OUT MV_I2C_BAUD_RATE *rate,
+  UINT32 clk
+  );
+
+EFI_STATUS
+EFIAPI
+MvI2cReset (
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This
+  );
+
+STATIC
+EFI_STATUS
+MvI2cRepeatedStart (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINT8 slave,
+  IN UINTN timeout
+  );
+
+STATIC
+EFI_STATUS
+MvI2cStart (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN UINT8 slave,
+  IN UINTN timeout
+  );
+
+STATIC
+EFI_STATUS
+MvI2cStop (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext
+  );
+
+STATIC
+EFI_STATUS
+MvI2cRead (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN OUT UINT8 *buf,
+  IN UINTN len,
+  IN OUT UINTN *read,
+  IN UINTN last,
+  IN UINTN delay
+  );
+
+STATIC
+EFI_STATUS
+MvI2cWrite (
+  IN I2C_MASTER_CONTEXT *I2cMasterContext,
+  IN OUT CONST UINT8 *buf,
+  IN UINTN len,
+  IN OUT UINTN *sent,
+  IN UINTN timeout
+  );
+
+STATIC
+EFI_STATUS
+EFIAPI
+MvI2cStartRequest (
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+  IN UINTN                         SlaveAddress,
+  IN EFI_I2C_REQUEST_PACKET        *RequestPacket,
+  IN EFI_EVENT                     Event      OPTIONAL,
+  OUT EFI_STATUS                   *I2cStatus OPTIONAL
+  );
+
+STATIC
+EFI_STATUS
+EFIAPI
+MvI2cEnumerate (
+  IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This,
+  IN OUT CONST EFI_I2C_DEVICE         **Device
+  );
+
+STATIC
+EFI_STATUS
+EFIAPI
+MvI2cEnableConf (
+  IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This,
+  IN UINTN                                               I2cBusConfiguration,
+  IN EFI_EVENT                                           Event      OPTIONAL,
+  IN EFI_STATUS                                          *I2cStatus OPTIONAL
+  );
+
+#endif // __MV_I2C_H__
diff --git a/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
new file mode 100755
index 0000000..c7c084c
--- /dev/null
+++ b/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
@@ -0,0 +1,75 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MvI2cDxe
+  FILE_GUID                      = 59fc3843-d8d4-40aa-ae07-38967138509b
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = MvI2cInitialise
+
+[Sources.common]
+  MvI2cDxe.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  IoLib
+  PcdLib
+  BaseLib
+  DebugLib
+  UefiLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  ParsePcdLib
+
+[Protocols]
+  gEfiI2cMasterProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiI2cEnumerateProtocolGuid
+  gEfiI2cBusConfigurationManagementProtocolGuid
+
+[Pcd]
+  gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses
+  gMarvellTokenSpaceGuid.PcdI2cSlaveBuses
+  gMarvellTokenSpaceGuid.PcdI2cBaseAddresses
+  gMarvellTokenSpaceGuid.PcdI2cClockFrequency
+  gMarvellTokenSpaceGuid.PcdI2cBaudRate
+  gMarvellTokenSpaceGuid.PcdI2cBusCount
+
+[Depex]
+  TRUE
diff --git a/Drivers/Keyboard/VirtualKeyboardDxe/ComponentName.c b/Drivers/Keyboard/VirtualKeyboardDxe/ComponentName.c
new file mode 100644
index 0000000..c000e29
--- /dev/null
+++ b/Drivers/Keyboard/VirtualKeyboardDxe/ComponentName.c
@@ -0,0 +1,184 @@
+/** @file
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions
+of the BSD License which accompanies this distribution.  The
+full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "VirtualKeyboard.h"
+
+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL  gVirtualKeyboardComponentName = {
+  VirtualKeyboardComponentNameGetDriverName,
+  VirtualKeyboardComponentNameGetControllerName,
+  "eng"
+};
+
+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gVirtualKeyboardComponentName2 = {
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) VirtualKeyboardComponentNameGetDriverName,
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) VirtualKeyboardComponentNameGetControllerName,
+  "en"
+};
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mVirtualKeyboardDriverNameTable[] = {
+  {
+    "eng;en",
+    L"RAM Keyboard Driver"
+  },
+  {
+    NULL,
+    NULL
+  }
+};
+
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
+  IN  CHAR8                        *Language,
+  OUT CHAR16                       **DriverName
+  )
+{
+  return LookupUnicodeString2 (
+           Language,
+           This->SupportedLanguages,
+           mVirtualKeyboardDriverNameTable,
+           DriverName,
+           (BOOLEAN)(This == &gVirtualKeyboardComponentName)
+           );
+}
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
+  IN  EFI_HANDLE                                      ControllerHandle,
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
+  IN  CHAR8                                           *Language,
+  OUT CHAR16                                          **ControllerName
+  )
+{
+  return EFI_UNSUPPORTED;
+}
diff --git a/Drivers/Keyboard/VirtualKeyboardDxe/ComponentName.h b/Drivers/Keyboard/VirtualKeyboardDxe/ComponentName.h
new file mode 100644
index 0000000..bb1facf
--- /dev/null
+++ b/Drivers/Keyboard/VirtualKeyboardDxe/ComponentName.h
@@ -0,0 +1,154 @@
+/** @file
+
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions
+of the BSD License which accompanies this distribution.  The
+full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VIRTUAL_KEYBOARD_COMPONENT_NAME_H_
+#define _VIRTUAL_KEYBOARD_COMPONENT_NAME_H_
+
+
+extern EFI_COMPONENT_NAME_PROTOCOL   gVirtualKeyboardComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL  gVirtualKeyboardComponentName2;
+
+//
+// EFI Component Name Functions
+//
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
+  IN  CHAR8                        *Language,
+  OUT CHAR16                       **DriverName
+  );
+
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
+  IN  EFI_HANDLE                                      ControllerHandle,
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
+  IN  CHAR8                                           *Language,
+  OUT CHAR16                                          **ControllerName
+  );
+
+
+#endif
diff --git a/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboard.c b/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboard.c
new file mode 100644
index 0000000..2aff805
--- /dev/null
+++ b/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboard.c
@@ -0,0 +1,1117 @@
+/** @file
+  VirtualKeyboard driver
+
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions
+of the BSD License which accompanies this distribution.  The
+full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "VirtualKeyboard.h"
+
+//
+// RAM Keyboard Driver Binding Protocol Instance
+//
+EFI_DRIVER_BINDING_PROTOCOL gVirtualKeyboardDriverBinding = {
+  VirtualKeyboardDriverBindingSupported,
+  VirtualKeyboardDriverBindingStart,
+  VirtualKeyboardDriverBindingStop,
+  0x10,
+  NULL,
+  NULL
+};
+
+//
+// EFI Driver Binding Protocol Functions
+//
+
+/**
+  Check whether the driver supports this device.
+
+  @param  This                   The Udriver binding protocol.
+  @param  Controller             The controller handle to check.
+  @param  RemainingDevicePath    The remaining device path.
+
+  @retval EFI_SUCCESS            The driver supports this controller.
+  @retval other                  This device isn't supported.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  )
+{
+  EFI_STATUS                     Status;
+  PLATFORM_VIRTUAL_KBD_PROTOCOL  *PlatformVirtual;
+
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gPlatformVirtualKeyboardProtocolGuid,
+                  (VOID **) &PlatformVirtual,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  gBS->CloseProtocol (
+         Controller,
+         &gPlatformVirtualKeyboardProtocolGuid,
+         This->DriverBindingHandle,
+         Controller
+         );
+  return Status;
+}
+
+/**
+  Starts the device with this driver.
+
+  @param  This                   The driver binding instance.
+  @param  Controller             Handle of device to bind driver to.
+  @param  RemainingDevicePath    Optional parameter use to pick a specific child
+                                 device to start.
+
+  @retval EFI_SUCCESS            The controller is controlled by the driver.
+  @retval Other                  This controller cannot be started.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  )
+{
+  EFI_STATUS                                Status;
+  VIRTUAL_KEYBOARD_DEV                      *VirtualKeyboardPrivate;
+  PLATFORM_VIRTUAL_KBD_PROTOCOL             *PlatformVirtual;
+
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gPlatformVirtualKeyboardProtocolGuid,
+                  (VOID **) &PlatformVirtual,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Allocate the private device structure
+  //
+  VirtualKeyboardPrivate = (VIRTUAL_KEYBOARD_DEV *) AllocateZeroPool (sizeof (VIRTUAL_KEYBOARD_DEV));
+  if (NULL == VirtualKeyboardPrivate) {
+    Status = EFI_OUT_OF_RESOURCES;
+    goto Done;
+  }
+
+  //
+  // Initialize the private device structure
+  //
+  VirtualKeyboardPrivate->Signature                  = VIRTUAL_KEYBOARD_DEV_SIGNATURE;
+  VirtualKeyboardPrivate->Handle                     = Controller;
+  VirtualKeyboardPrivate->PlatformVirtual            = PlatformVirtual;
+  VirtualKeyboardPrivate->Queue.Front                = 0;
+  VirtualKeyboardPrivate->Queue.Rear                 = 0;
+  VirtualKeyboardPrivate->QueueForNotify.Front       = 0;
+  VirtualKeyboardPrivate->QueueForNotify.Rear        = 0;
+
+  VirtualKeyboardPrivate->SimpleTextIn.Reset         = VirtualKeyboardReset;
+  VirtualKeyboardPrivate->SimpleTextIn.ReadKeyStroke = VirtualKeyboardReadKeyStroke;
+
+  VirtualKeyboardPrivate->SimpleTextInputEx.Reset               = VirtualKeyboardResetEx;
+  VirtualKeyboardPrivate->SimpleTextInputEx.ReadKeyStrokeEx     = VirtualKeyboardReadKeyStrokeEx;
+  VirtualKeyboardPrivate->SimpleTextInputEx.SetState            = VirtualKeyboardSetState;
+
+  VirtualKeyboardPrivate->SimpleTextInputEx.RegisterKeyNotify   = VirtualKeyboardRegisterKeyNotify;
+  VirtualKeyboardPrivate->SimpleTextInputEx.UnregisterKeyNotify = VirtualKeyboardUnregisterKeyNotify;
+  InitializeListHead (&VirtualKeyboardPrivate->NotifyList);
+
+  Status = PlatformVirtual->Register ();
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  //
+  // Report that the keyboard is being enabled
+  //
+  REPORT_STATUS_CODE (
+    EFI_PROGRESS_CODE,
+    EFI_PERIPHERAL_KEYBOARD | EFI_P_PC_ENABLE
+    );
+
+  //
+  // Setup the WaitForKey event
+  //
+  Status = gBS->CreateEvent (
+                  EVT_NOTIFY_WAIT,
+                  TPL_NOTIFY,
+                  VirtualKeyboardWaitForKey,
+                  &(VirtualKeyboardPrivate->SimpleTextIn),
+                  &((VirtualKeyboardPrivate->SimpleTextIn).WaitForKey)
+                  );
+  if (EFI_ERROR (Status)) {
+    (VirtualKeyboardPrivate->SimpleTextIn).WaitForKey = NULL;
+    goto Done;
+  }
+  Status = gBS->CreateEvent (
+                  EVT_NOTIFY_WAIT,
+                  TPL_NOTIFY,
+                  VirtualKeyboardWaitForKeyEx,
+                  &(VirtualKeyboardPrivate->SimpleTextInputEx),
+                  &(VirtualKeyboardPrivate->SimpleTextInputEx.WaitForKeyEx)
+                  );
+  if (EFI_ERROR (Status)) {
+    VirtualKeyboardPrivate->SimpleTextInputEx.WaitForKeyEx = NULL;
+    goto Done;
+  }
+
+  //
+  // Setup a periodic timer, used for reading keystrokes at a fixed interval
+  //
+  Status = gBS->CreateEvent (
+                  EVT_TIMER | EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  VirtualKeyboardTimerHandler,
+                  VirtualKeyboardPrivate,
+                  &VirtualKeyboardPrivate->TimerEvent
+                  );
+  if (EFI_ERROR (Status)) {
+    Status      = EFI_OUT_OF_RESOURCES;
+    goto Done;
+  }
+
+  Status = gBS->SetTimer (
+                  VirtualKeyboardPrivate->TimerEvent,
+                  TimerPeriodic,
+                  KEYBOARD_TIMER_INTERVAL
+                  );
+  if (EFI_ERROR (Status)) {
+    Status      = EFI_OUT_OF_RESOURCES;
+    goto Done;
+  }
+
+  Status = gBS->CreateEvent (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_CALLBACK,
+                  KeyNotifyProcessHandler,
+                  VirtualKeyboardPrivate,
+                  &VirtualKeyboardPrivate->KeyNotifyProcessEvent
+                  );
+  if (EFI_ERROR (Status)) {
+    Status      = EFI_OUT_OF_RESOURCES;
+    goto Done;
+  }
+
+  //
+  // Reset the keyboard device
+  //
+  Status = VirtualKeyboardPrivate->SimpleTextInputEx.Reset (
+                                                    &VirtualKeyboardPrivate->SimpleTextInputEx,
+                                                    FALSE
+                                                    );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "[KBD]Reset Failed. Status - %r\n", Status));
+    goto Done;
+  }
+  //
+  // Install protocol interfaces for the keyboard device.
+  //
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Controller,
+                  &gEfiSimpleTextInProtocolGuid,
+                  &VirtualKeyboardPrivate->SimpleTextIn,
+                  &gEfiSimpleTextInputExProtocolGuid,
+                  &VirtualKeyboardPrivate->SimpleTextInputEx,
+                  NULL
+                  );
+
+Done:
+  if (EFI_ERROR (Status)) {
+    if (VirtualKeyboardPrivate != NULL) {
+      if ((VirtualKeyboardPrivate->SimpleTextIn).WaitForKey != NULL) {
+        gBS->CloseEvent ((VirtualKeyboardPrivate->SimpleTextIn).WaitForKey);
+      }
+
+      if ((VirtualKeyboardPrivate->SimpleTextInputEx).WaitForKeyEx != NULL) {
+        gBS->CloseEvent ((VirtualKeyboardPrivate->SimpleTextInputEx).WaitForKeyEx);
+      }
+
+      if (VirtualKeyboardPrivate->KeyNotifyProcessEvent != NULL) {
+        gBS->CloseEvent (VirtualKeyboardPrivate->KeyNotifyProcessEvent);
+      }
+
+      VirtualKeyboardFreeNotifyList (&VirtualKeyboardPrivate->NotifyList);
+
+      if (VirtualKeyboardPrivate->TimerEvent != NULL) {
+        gBS->CloseEvent (VirtualKeyboardPrivate->TimerEvent);
+      }
+      FreePool (VirtualKeyboardPrivate);
+    }
+  }
+
+  gBS->CloseProtocol (
+         Controller,
+         &gPlatformVirtualKeyboardProtocolGuid,
+         This->DriverBindingHandle,
+         Controller
+         );
+
+  return Status;
+}
+
+/**
+  Stop the device handled by this driver.
+
+  @param  This                   The driver binding protocol.
+  @param  Controller             The controller to release.
+  @param  NumberOfChildren       The number of handles in ChildHandleBuffer.
+  @param  ChildHandleBuffer      The array of child handle.
+
+  @retval EFI_SUCCESS            The device was stopped.
+  @retval EFI_DEVICE_ERROR       The device could not be stopped due to a device error.
+  @retval Others                 Fail to uninstall protocols attached on the device.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN  EFI_HANDLE                   Controller,
+  IN  UINTN                        NumberOfChildren,
+  IN  EFI_HANDLE                   *ChildHandleBuffer
+  )
+{
+  return EFI_SUCCESS;
+}
+
+
+/**
+  Enqueue the key.
+
+  @param  Queue                 The queue to be enqueued.
+  @param  KeyData               The key data to be enqueued.
+
+  @retval EFI_NOT_READY         The queue is full.
+  @retval EFI_SUCCESS           Successfully enqueued the key data.
+
+**/
+EFI_STATUS
+Enqueue (
+  IN SIMPLE_QUEUE         *Queue,
+  IN EFI_KEY_DATA         *KeyData
+  )
+{
+  if ((Queue->Rear + 1) % QUEUE_MAX_COUNT == Queue->Front) {
+    return EFI_NOT_READY;
+  }
+
+  CopyMem (&Queue->Buffer[Queue->Rear], KeyData, sizeof (EFI_KEY_DATA));
+  Queue->Rear = (Queue->Rear + 1) % QUEUE_MAX_COUNT;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Dequeue the key.
+
+  @param  Queue                 The queue to be dequeued.
+  @param  KeyData               The key data to be dequeued.
+
+  @retval EFI_NOT_READY         The queue is empty.
+  @retval EFI_SUCCESS           Successfully dequeued the key data.
+
+**/
+EFI_STATUS
+Dequeue (
+  IN SIMPLE_QUEUE         *Queue,
+  IN EFI_KEY_DATA         *KeyData
+  )
+{
+  if (Queue->Front == Queue->Rear) {
+    return EFI_NOT_READY;
+  }
+
+  CopyMem (KeyData, &Queue->Buffer[Queue->Front], sizeof (EFI_KEY_DATA));
+  Queue->Front  = (Queue->Front + 1) % QUEUE_MAX_COUNT;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Check whether the queue is empty.
+
+  @param  Queue                 The queue to be checked.
+
+  @retval EFI_NOT_READY         The queue is empty.
+  @retval EFI_SUCCESS           The queue is not empty.
+
+**/
+EFI_STATUS
+CheckQueue (
+  IN SIMPLE_QUEUE         *Queue
+  )
+{
+  if (Queue->Front == Queue->Rear) {
+    return EFI_NOT_READY;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Check key buffer to get the key stroke status.
+
+  @param  This         Pointer of the protocol EFI_SIMPLE_TEXT_IN_PROTOCOL.
+
+  @retval EFI_SUCCESS  A key is being pressed now.
+  @retval Other        No key is now pressed.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardCheckForKey (
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This
+  )
+{
+  VIRTUAL_KEYBOARD_DEV     *VirtualKeyboardPrivate;
+
+  VirtualKeyboardPrivate = VIRTUAL_KEYBOARD_DEV_FROM_THIS (This);
+
+  return CheckQueue (&VirtualKeyboardPrivate->Queue);
+}
+
+/**
+  Free keyboard notify list.
+
+  @param  ListHead   The list head
+
+  @retval EFI_SUCCESS           Free the notify list successfully
+  @retval EFI_INVALID_PARAMETER ListHead is invalid.
+
+**/
+EFI_STATUS
+VirtualKeyboardFreeNotifyList (
+  IN OUT LIST_ENTRY           *ListHead
+  )
+{
+  VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY *NotifyNode;
+
+  if (ListHead == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  while (!IsListEmpty (ListHead)) {
+    NotifyNode = CR (
+                   ListHead->ForwardLink,
+                   VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY,
+                   NotifyEntry,
+                   VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY_SIGNATURE
+                   );
+    RemoveEntryList (ListHead->ForwardLink);
+    gBS->FreePool (NotifyNode);
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Judge whether is a registed key
+
+  @param RegsiteredData       A pointer to a buffer that is filled in with the keystroke
+                              state data for the key that was registered.
+  @param InputData            A pointer to a buffer that is filled in with the keystroke
+                              state data for the key that was pressed.
+
+  @retval TRUE                Key be pressed matches a registered key.
+  @retval FLASE               Match failed.
+
+**/
+BOOLEAN
+IsKeyRegistered (
+  IN EFI_KEY_DATA  *RegsiteredData,
+  IN EFI_KEY_DATA  *InputData
+  )
+
+{
+  ASSERT (RegsiteredData != NULL && InputData != NULL);
+
+  if ((RegsiteredData->Key.ScanCode    != InputData->Key.ScanCode) ||
+      (RegsiteredData->Key.UnicodeChar != InputData->Key.UnicodeChar)) {
+    return FALSE;
+  }
+
+  //
+  // Assume KeyShiftState/KeyToggleState = 0 in Registered key data means these state could be ignored.
+  //
+  if (RegsiteredData->KeyState.KeyShiftState != 0 &&
+      RegsiteredData->KeyState.KeyShiftState != InputData->KeyState.KeyShiftState) {
+    return FALSE;
+  }
+  if (RegsiteredData->KeyState.KeyToggleState != 0 &&
+      RegsiteredData->KeyState.KeyToggleState != InputData->KeyState.KeyToggleState) {
+    return FALSE;
+  }
+
+  return TRUE;
+
+}
+
+/**
+  Event notification function for SIMPLE_TEXT_IN.WaitForKey event
+  Signal the event if there is key available
+
+  @param Event    the event object
+  @param Context  waitting context
+
+**/
+VOID
+EFIAPI
+VirtualKeyboardWaitForKey (
+  IN  EFI_EVENT               Event,
+  IN  VOID                    *Context
+  )
+{
+  //
+  // Stall 1ms to give a chance to let other driver interrupt this routine for their timer event.
+  // Csm will be used to check whether there is a key pending, but the csm will disable all
+  // interrupt before switch to compatibility16, which mean all the efiCompatibility timer
+  // event will stop work during the compatibility16. And If a caller recursivly invoke this function,
+  // e.g. UI setup or Shell, other drivers which are driven by timer event will have a bad performance during this period,
+  // e.g. usb keyboard driver.
+  // Add a stall period can greatly increate other driver performance during the WaitForKey is recursivly invoked.
+  // 1ms delay will make little impact to the thunk keyboard driver, and user can not feel the delay at all when input.
+  //
+  gBS->Stall (1000);
+  //
+  // Use TimerEvent callback function to check whether there's any key pressed
+  //
+  VirtualKeyboardTimerHandler (NULL, VIRTUAL_KEYBOARD_DEV_FROM_THIS (Context));
+
+  if (!EFI_ERROR (VirtualKeyboardCheckForKey (Context))) {
+    gBS->SignalEvent (Event);
+  }
+}
+
+/**
+  Event notification function for SIMPLE_TEXT_INPUT_EX_PROTOCOL.WaitForKeyEx event
+  Signal the event if there is key available
+
+  @param Event    event object
+  @param Context  waiting context
+
+**/
+VOID
+EFIAPI
+VirtualKeyboardWaitForKeyEx (
+  IN  EFI_EVENT               Event,
+  IN  VOID                    *Context
+  )
+
+{
+  VIRTUAL_KEYBOARD_DEV                     *VirtualKeyboardPrivate;
+
+  VirtualKeyboardPrivate = TEXT_INPUT_EX_VIRTUAL_KEYBOARD_DEV_FROM_THIS (Context);
+  VirtualKeyboardWaitForKey (Event, &VirtualKeyboardPrivate->SimpleTextIn);
+
+}
+
+//
+// EFI Simple Text In Protocol Functions
+//
+/**
+  Reset the Keyboard and do BAT test for it, if (ExtendedVerification == TRUE) then do some extra keyboard validations.
+
+  @param  This                  Pointer of simple text Protocol.
+  @param  ExtendedVerification  Whether perform the extra validation of keyboard. True: perform; FALSE: skip.
+
+  @retval EFI_SUCCESS           The command byte is written successfully.
+  @retval EFI_DEVICE_ERROR      Errors occurred during resetting keyboard.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardReset (
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This,
+  IN  BOOLEAN                         ExtendedVerification
+  )
+{
+  VIRTUAL_KEYBOARD_DEV *VirtualKeyboardPrivate;
+  EFI_STATUS           Status;
+  EFI_TPL              OldTpl;
+
+  VirtualKeyboardPrivate = VIRTUAL_KEYBOARD_DEV_FROM_THIS (This);
+
+  //
+  // Raise TPL to avoid mouse operation impact
+  //
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  if (VirtualKeyboardPrivate->PlatformVirtual && VirtualKeyboardPrivate->PlatformVirtual->Reset) {
+    Status = VirtualKeyboardPrivate->PlatformVirtual->Reset ();
+  } else {
+    Status = EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // resume priority of task level
+  //
+  gBS->RestoreTPL (OldTpl);
+
+  return Status;
+}
+
+/**
+  Reset the input device and optionaly run diagnostics
+
+  @param  This                  Protocol instance pointer.
+  @param  ExtendedVerification  Driver may perform diagnostics on reset.
+
+  @retval EFI_SUCCESS           The device was reset.
+  @retval EFI_DEVICE_ERROR      The device is not functioning properly and could-
+                                not be reset.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardResetEx (
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,
+  IN BOOLEAN                            ExtendedVerification
+  )
+{
+  VIRTUAL_KEYBOARD_DEV                     *VirtualKeyboardPrivate;
+  EFI_STATUS                            Status;
+  EFI_TPL                               OldTpl;
+
+  VirtualKeyboardPrivate = TEXT_INPUT_EX_VIRTUAL_KEYBOARD_DEV_FROM_THIS (This);
+
+  Status = VirtualKeyboardPrivate->SimpleTextIn.Reset (
+                                               &VirtualKeyboardPrivate->SimpleTextIn,
+                                               ExtendedVerification
+                                               );
+  if (EFI_ERROR (Status)) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  gBS->RestoreTPL (OldTpl);
+
+  return EFI_SUCCESS;
+
+}
+
+/**
+  Reads the next keystroke from the input device. The WaitForKey Event can
+  be used to test for existance of a keystroke via WaitForEvent () call.
+
+  @param  VirtualKeyboardPrivate   Virtualkeyboard driver private structure.
+  @param  KeyData               A pointer to a buffer that is filled in with the keystroke
+                                state data for the key that was pressed.
+
+  @retval EFI_SUCCESS           The keystroke information was returned.
+  @retval EFI_NOT_READY         There was no keystroke data availiable.
+  @retval EFI_DEVICE_ERROR      The keystroke information was not returned due to
+                                hardware errors.
+  @retval EFI_INVALID_PARAMETER KeyData is NULL.
+
+**/
+EFI_STATUS
+KeyboardReadKeyStrokeWorker (
+  IN VIRTUAL_KEYBOARD_DEV  *VirtualKeyboardPrivate,
+  OUT EFI_KEY_DATA      *KeyData
+  )
+{
+  EFI_STATUS                            Status;
+  EFI_TPL                               OldTpl;
+  if (KeyData == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Use TimerEvent callback function to check whether there's any key pressed
+  //
+
+  //
+  // Stall 1ms to give a chance to let other driver interrupt this routine for their timer event.
+  // Csm will be used to check whether there is a key pending, but the csm will disable all
+  // interrupt before switch to compatibility16, which mean all the efiCompatibility timer
+  // event will stop work during the compatibility16. And If a caller recursivly invoke this function,
+  // e.g. OS loader, other drivers which are driven by timer event will have a bad performance during this period,
+  // e.g. usb keyboard driver.
+  // Add a stall period can greatly increate other driver performance during the WaitForKey is recursivly invoked.
+  // 1ms delay will make little impact to the thunk keyboard driver, and user can not feel the delay at all when input.
+  //
+  gBS->Stall (1000);
+
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  VirtualKeyboardTimerHandler (NULL, VirtualKeyboardPrivate);
+  //
+  // If there's no key, just return
+  //
+  Status = CheckQueue (&VirtualKeyboardPrivate->Queue);
+  if (EFI_ERROR (Status)) {
+    gBS->RestoreTPL (OldTpl);
+    return EFI_NOT_READY;
+  }
+
+  Status = Dequeue (&VirtualKeyboardPrivate->Queue, KeyData);
+
+  gBS->RestoreTPL (OldTpl);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Read out the scan code of the key that has just been stroked.
+
+  @param  This        Pointer of simple text Protocol.
+  @param  Key         Pointer for store the key that read out.
+
+  @retval EFI_SUCCESS The key is read out successfully.
+  @retval other       The key reading failed.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardReadKeyStroke (
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This,
+  OUT EFI_INPUT_KEY                   *Key
+  )
+{
+  VIRTUAL_KEYBOARD_DEV     *VirtualKeyboardPrivate;
+  EFI_STATUS            Status;
+  EFI_KEY_DATA          KeyData;
+
+  VirtualKeyboardPrivate = VIRTUAL_KEYBOARD_DEV_FROM_THIS (This);
+
+  Status = KeyboardReadKeyStrokeWorker (VirtualKeyboardPrivate, &KeyData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Convert the Ctrl+[a-z] to Ctrl+[1-26]
+  //
+  if ((KeyData.KeyState.KeyShiftState & (EFI_LEFT_CONTROL_PRESSED | EFI_RIGHT_CONTROL_PRESSED)) != 0) {
+    if (KeyData.Key.UnicodeChar >= L'a' && KeyData.Key.UnicodeChar <= L'z') {
+      KeyData.Key.UnicodeChar = (CHAR16) (KeyData.Key.UnicodeChar - L'a' + 1);
+    } else if (KeyData.Key.UnicodeChar >= L'A' && KeyData.Key.UnicodeChar <= L'Z') {
+      KeyData.Key.UnicodeChar = (CHAR16) (KeyData.Key.UnicodeChar - L'A' + 1);
+    }
+  }
+
+  CopyMem (Key, &KeyData.Key, sizeof (EFI_INPUT_KEY));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Reads the next keystroke from the input device. The WaitForKey Event can
+  be used to test for existance of a keystroke via WaitForEvent () call.
+
+  @param  This         Protocol instance pointer.
+  @param  KeyData      A pointer to a buffer that is filled in with the keystroke
+                       state data for the key that was pressed.
+
+  @retval  EFI_SUCCESS           The keystroke information was returned.
+  @retval  EFI_NOT_READY         There was no keystroke data availiable.
+  @retval  EFI_DEVICE_ERROR      The keystroke information was not returned due to
+                                 hardware errors.
+  @retval  EFI_INVALID_PARAMETER KeyData is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardReadKeyStrokeEx (
+  IN  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,
+  OUT EFI_KEY_DATA                      *KeyData
+  )
+{
+  VIRTUAL_KEYBOARD_DEV                     *VirtualKeyboardPrivate;
+
+  if (KeyData == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  VirtualKeyboardPrivate = TEXT_INPUT_EX_VIRTUAL_KEYBOARD_DEV_FROM_THIS (This);
+
+  return KeyboardReadKeyStrokeWorker (VirtualKeyboardPrivate, KeyData);
+
+}
+
+/**
+  Set certain state for the input device.
+
+  @param  This              Protocol instance pointer.
+  @param  KeyToggleState    A pointer to the EFI_KEY_TOGGLE_STATE to set the-
+                            state for the input device.
+
+  @retval EFI_SUCCESS           The device state was set successfully.
+  @retval EFI_DEVICE_ERROR      The device is not functioning correctly and could-
+                                not have the setting adjusted.
+  @retval EFI_UNSUPPORTED       The device does not have the ability to set its state.
+  @retval EFI_INVALID_PARAMETER KeyToggleState is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardSetState (
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,
+  IN EFI_KEY_TOGGLE_STATE               *KeyToggleState
+  )
+{
+  if (KeyToggleState == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Thunk keyboard driver doesn't support partial keystroke.
+  //
+  if ((*KeyToggleState & EFI_TOGGLE_STATE_VALID) != EFI_TOGGLE_STATE_VALID ||
+      (*KeyToggleState & EFI_KEY_STATE_EXPOSED) == EFI_KEY_STATE_EXPOSED
+      ) {
+    return EFI_UNSUPPORTED;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Register a notification function for a particular keystroke for the input device.
+
+  @param  This                    Protocol instance pointer.
+  @param  KeyData                 A pointer to a buffer that is filled in with the keystroke
+                                  information data for the key that was pressed.
+  @param  KeyNotificationFunction Points to the function to be called when the key
+                                  sequence is typed specified by KeyData.
+  @param  NotifyHandle            Points to the unique handle assigned to the registered notification.
+
+
+  @retval EFI_SUCCESS             The notification function was registered successfully.
+  @retval EFI_OUT_OF_RESOURCES    Unable to allocate resources for necesssary data structures.
+  @retval EFI_INVALID_PARAMETER   KeyData or NotifyHandle is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardRegisterKeyNotify (
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,
+  IN EFI_KEY_DATA                       *KeyData,
+  IN EFI_KEY_NOTIFY_FUNCTION            KeyNotificationFunction,
+  OUT VOID                              **NotifyHandle
+  )
+{
+  EFI_STATUS                            Status;
+  VIRTUAL_KEYBOARD_DEV                     *VirtualKeyboardPrivate;
+  EFI_TPL                               OldTpl;
+  VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY    *NewNotify;
+  LIST_ENTRY                            *Link;
+  VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY    *CurrentNotify;
+
+  if (KeyData == NULL || NotifyHandle == NULL || KeyNotificationFunction == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  VirtualKeyboardPrivate = TEXT_INPUT_EX_VIRTUAL_KEYBOARD_DEV_FROM_THIS (This);
+
+  //
+  // Enter critical section
+  //
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  //
+  // Return EFI_SUCCESS if the (KeyData, NotificationFunction) is already registered.
+  //
+  for (Link = VirtualKeyboardPrivate->NotifyList.ForwardLink; Link != &VirtualKeyboardPrivate->NotifyList; Link = Link->ForwardLink) {
+    CurrentNotify = CR (
+                      Link,
+                      VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY,
+                      NotifyEntry,
+                      VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY_SIGNATURE
+                      );
+    if (IsKeyRegistered (&CurrentNotify->KeyData, KeyData)) {
+      if (CurrentNotify->KeyNotificationFn == KeyNotificationFunction) {
+        *NotifyHandle = CurrentNotify;
+        Status = EFI_SUCCESS;
+        goto Exit;
+      }
+    }
+  }
+
+  //
+  // Allocate resource to save the notification function
+  //
+
+  NewNotify = (VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY *) AllocateZeroPool (sizeof (VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY));
+  if (NewNotify == NULL) {
+    Status = EFI_OUT_OF_RESOURCES;
+    goto Exit;
+  }
+
+  NewNotify->Signature         = VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY_SIGNATURE;
+  NewNotify->KeyNotificationFn = KeyNotificationFunction;
+  CopyMem (&NewNotify->KeyData, KeyData, sizeof (EFI_KEY_DATA));
+  InsertTailList (&VirtualKeyboardPrivate->NotifyList, &NewNotify->NotifyEntry);
+
+  *NotifyHandle                = NewNotify;
+  Status                       = EFI_SUCCESS;
+
+Exit:
+  //
+  // Leave critical section and return
+  //
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+
+}
+
+/**
+  Remove a registered notification function from a particular keystroke.
+
+  @param  This                 Protocol instance pointer.
+  @param  NotificationHandle   The handle of the notification function being unregistered.
+
+  @retval EFI_SUCCESS             The notification function was unregistered successfully.
+  @retval EFI_INVALID_PARAMETER   The NotificationHandle is invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardUnregisterKeyNotify (
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,
+  IN VOID                               *NotificationHandle
+  )
+{
+  EFI_STATUS                            Status;
+  VIRTUAL_KEYBOARD_DEV                     *VirtualKeyboardPrivate;
+  EFI_TPL                               OldTpl;
+  LIST_ENTRY                            *Link;
+  VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY    *CurrentNotify;
+
+  //
+  // Check incoming notification handle
+  //
+  if (NotificationHandle == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (((VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY *) NotificationHandle)->Signature != VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY_SIGNATURE) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  VirtualKeyboardPrivate = TEXT_INPUT_EX_VIRTUAL_KEYBOARD_DEV_FROM_THIS (This);
+
+  //
+  // Enter critical section
+  //
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  for (Link = VirtualKeyboardPrivate->NotifyList.ForwardLink; Link != &VirtualKeyboardPrivate->NotifyList; Link = Link->ForwardLink) {
+    CurrentNotify = CR (
+                      Link,
+                      VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY,
+                      NotifyEntry,
+                      VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY_SIGNATURE
+                      );
+    if (CurrentNotify == NotificationHandle) {
+      //
+      // Remove the notification function from NotifyList and free resources
+      //
+      RemoveEntryList (&CurrentNotify->NotifyEntry);
+
+      Status = EFI_SUCCESS;
+      goto Exit;
+    }
+  }
+
+  //
+  // Can not find the specified Notification Handle
+  //
+  Status = EFI_INVALID_PARAMETER;
+
+Exit:
+  //
+  // Leave critical section and return
+  //
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+}
+
+/**
+  Timer event handler: read a series of scancodes from 8042
+  and put them into memory scancode buffer.
+  it read as much scancodes to either fill
+  the memory buffer or empty the keyboard buffer.
+  It is registered as running under TPL_NOTIFY
+
+  @param Event       The timer event
+  @param Context     A KEYBOARD_CONSOLE_IN_DEV pointer
+
+**/
+VOID
+EFIAPI
+VirtualKeyboardTimerHandler (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  )
+{
+  EFI_TPL                            OldTpl;
+  LIST_ENTRY                         *Link;
+  EFI_KEY_DATA                       KeyData;
+  VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY  *CurrentNotify;
+  VIRTUAL_KEYBOARD_DEV                   *VirtualKeyboardPrivate;
+  VIRTUAL_KBD_KEY                        VirtualKey;
+
+  VirtualKeyboardPrivate = Context;
+
+  //
+  // Enter critical section
+  //
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  if (VirtualKeyboardPrivate->PlatformVirtual &&
+      VirtualKeyboardPrivate->PlatformVirtual->Query) {
+    if (VirtualKeyboardPrivate->PlatformVirtual->Query (&VirtualKey) == FALSE) {
+      goto Exit;
+    }
+    // Found key
+    KeyData.Key.ScanCode = VirtualKey.Key.ScanCode;
+    KeyData.Key.UnicodeChar = VirtualKey.Key.UnicodeChar;
+    KeyData.KeyState.KeyShiftState  = EFI_SHIFT_STATE_VALID;
+    KeyData.KeyState.KeyToggleState = EFI_TOGGLE_STATE_VALID;
+    if (VirtualKeyboardPrivate->PlatformVirtual->Clear) {
+      VirtualKeyboardPrivate->PlatformVirtual->Clear (&VirtualKey);
+    }
+  } else {
+    goto Exit;
+  }
+
+  //
+  // Signal KeyNotify process event if this key pressed matches any key registered.
+  //
+  for (Link = VirtualKeyboardPrivate->NotifyList.ForwardLink; Link != &VirtualKeyboardPrivate->NotifyList; Link = Link->ForwardLink) {
+    CurrentNotify = CR (
+                      Link,
+                      VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY,
+                      NotifyEntry,
+                      VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY_SIGNATURE
+                      );
+    if (IsKeyRegistered (&CurrentNotify->KeyData, &KeyData)) {
+      //
+      // The key notification function needs to run at TPL_CALLBACK
+      // while current TPL is TPL_NOTIFY. It will be invoked in
+      // KeyNotifyProcessHandler() which runs at TPL_CALLBACK.
+      //
+      Enqueue (&VirtualKeyboardPrivate->QueueForNotify, &KeyData);
+      gBS->SignalEvent (VirtualKeyboardPrivate->KeyNotifyProcessEvent);
+    }
+  }
+
+  Enqueue (&VirtualKeyboardPrivate->Queue, &KeyData);
+
+Exit:
+  //
+  // Leave critical section and return
+  //
+  gBS->RestoreTPL (OldTpl);
+}
+
+/**
+  Process key notify.
+
+  @param  Event                 Indicates the event that invoke this function.
+  @param  Context               Indicates the calling context.
+**/
+VOID
+EFIAPI
+KeyNotifyProcessHandler (
+  IN  EFI_EVENT                 Event,
+  IN  VOID                      *Context
+  )
+{
+  EFI_STATUS                            Status;
+  VIRTUAL_KEYBOARD_DEV                     *VirtualKeyboardPrivate;
+  EFI_KEY_DATA                          KeyData;
+  LIST_ENTRY                            *Link;
+  LIST_ENTRY                            *NotifyList;
+  VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY    *CurrentNotify;
+  EFI_TPL                               OldTpl;
+
+  VirtualKeyboardPrivate = (VIRTUAL_KEYBOARD_DEV *) Context;
+
+  //
+  // Invoke notification functions.
+  //
+  NotifyList = &VirtualKeyboardPrivate->NotifyList;
+  while (TRUE) {
+    //
+    // Enter critical section
+    //
+    OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+    Status = Dequeue (&VirtualKeyboardPrivate->QueueForNotify, &KeyData);
+    //
+    // Leave critical section
+    //
+    gBS->RestoreTPL (OldTpl);
+    if (EFI_ERROR (Status)) {
+      break;
+    }
+    for (Link = GetFirstNode (NotifyList); !IsNull (NotifyList, Link); Link = GetNextNode (NotifyList, Link)) {
+      CurrentNotify = CR (Link, VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY, NotifyEntry, VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY_SIGNATURE);
+      if (IsKeyRegistered (&CurrentNotify->KeyData, &KeyData)) {
+        CurrentNotify->KeyNotificationFn (&KeyData);
+      }
+    }
+  }
+}
+
+/**
+  The user Entry Point for module VirtualKeyboard. The user code starts with this function.
+
+  @param[in] ImageHandle    The firmware allocated handle for the EFI image.
+  @param[in] SystemTable    A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+  @retval other             Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeVirtualKeyboard(
+  IN EFI_HANDLE           ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+{
+  EFI_STATUS              Status;
+
+  //
+  // Install driver model protocol(s).
+  //
+  Status = EfiLibInstallDriverBindingComponentName2 (
+             ImageHandle,
+             SystemTable,
+             &gVirtualKeyboardDriverBinding,
+             ImageHandle,
+             &gVirtualKeyboardComponentName,
+             &gVirtualKeyboardComponentName2
+             );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboard.h b/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboard.h
new file mode 100644
index 0000000..faef24d
--- /dev/null
+++ b/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboard.h
@@ -0,0 +1,544 @@
+/** @file
+
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions
+of the BSD License which accompanies this distribution.  The
+full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _VIRTUAL_KEYBOARD_H_
+#define _VIRTUAL_KEYBOARD_H_
+
+
+#include <Guid/StatusCodeDataTypeId.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/PlatformVirtualKeyboard.h>
+#include <Protocol/SimpleTextIn.h>
+#include <Protocol/SimpleTextInEx.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+
+//
+// Driver Binding Externs
+//
+extern EFI_DRIVER_BINDING_PROTOCOL  gVirtualKeyboardDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL  gVirtualKeyboardComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gVirtualKeyboardComponentName2;
+
+
+//
+// VIRTUAL Keyboard Defines
+//
+#define CHAR_SCANCODE                   0xe0
+#define CHAR_ESC                        0x1b
+
+#define KEYBOARD_TIMEOUT                65536   // 0.07s
+#define KEYBOARD_WAITFORVALUE_TIMEOUT   1000000 // 1s
+#define KEYBOARD_BAT_TIMEOUT            4000000 // 4s
+#define KEYBOARD_TIMER_INTERVAL         500000  // 0.5s
+
+#define QUEUE_MAX_COUNT                 32
+
+//
+// VIRTUAL Keyboard Device Structure
+//
+#define VIRTUAL_KEYBOARD_DEV_SIGNATURE SIGNATURE_32 ('V', 'K', 'B', 'D')
+#define VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY_SIGNATURE SIGNATURE_32 ('v', 'k', 'c', 'n')
+
+typedef struct _VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY {
+  UINTN                                      Signature;
+  EFI_KEY_DATA                               KeyData;
+  EFI_KEY_NOTIFY_FUNCTION                    KeyNotificationFn;
+  LIST_ENTRY                                 NotifyEntry;
+} VIRTUAL_KEYBOARD_CONSOLE_IN_EX_NOTIFY;
+
+typedef struct {
+  UINTN             Front;
+  UINTN             Rear;
+  EFI_KEY_DATA      Buffer[QUEUE_MAX_COUNT];
+} SIMPLE_QUEUE;
+
+#define KEYBOARD_SCAN_CODE_MAX_COUNT  32
+typedef struct {
+  UINT8                               Buffer[KEYBOARD_SCAN_CODE_MAX_COUNT];
+  UINTN                               Head;
+  UINTN                               Tail;
+} SCAN_CODE_QUEUE;
+
+typedef struct {
+  UINTN                                       Signature;
+  EFI_HANDLE                                  Handle;
+  PLATFORM_VIRTUAL_KBD_PROTOCOL               *PlatformVirtual;
+  EFI_SIMPLE_TEXT_INPUT_PROTOCOL              SimpleTextIn;
+  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL           SimpleTextInputEx;
+
+  //
+  // Buffer storing EFI_KEY_DATA
+  //
+  SIMPLE_QUEUE                                Queue;
+  SIMPLE_QUEUE                                QueueForNotify;
+
+  //
+  // Notification Function List
+  //
+  LIST_ENTRY                                  NotifyList;
+  EFI_EVENT                                   KeyNotifyProcessEvent;
+  EFI_EVENT                                   TimerEvent;
+
+} VIRTUAL_KEYBOARD_DEV;
+
+#define VIRTUAL_KEYBOARD_DEV_FROM_THIS(a)  CR (a, VIRTUAL_KEYBOARD_DEV, SimpleTextIn, VIRTUAL_KEYBOARD_DEV_SIGNATURE)
+#define TEXT_INPUT_EX_VIRTUAL_KEYBOARD_DEV_FROM_THIS(a) \
+  CR (a, \
+      VIRTUAL_KEYBOARD_DEV, \
+      SimpleTextInputEx, \
+      VIRTUAL_KEYBOARD_DEV_SIGNATURE \
+      )
+
+//
+// Global Variables
+//
+extern EFI_DRIVER_BINDING_PROTOCOL   gVirtualKeyboardDriverBinding;
+
+//
+// Driver Binding Protocol functions
+//
+
+/**
+  Check whether the driver supports this device.
+
+  @param  This                   The Udriver binding protocol.
+  @param  Controller             The controller handle to check.
+  @param  RemainingDevicePath    The remaining device path.
+
+  @retval EFI_SUCCESS            The driver supports this controller.
+  @retval other                  This device isn't supported.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  );
+
+/**
+  Starts the device with this driver.
+
+  @param  This                   The driver binding instance.
+  @param  Controller             Handle of device to bind driver to.
+  @param  RemainingDevicePath    Optional parameter use to pick a specific child
+                                 device to start.
+
+  @retval EFI_SUCCESS            The controller is controlled by the driver.
+  @retval Other                  This controller cannot be started.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN EFI_HANDLE                   Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+  );
+
+/**
+  Stop the device handled by this driver.
+
+  @param  This                   The driver binding protocol.
+  @param  Controller             The controller to release.
+  @param  NumberOfChildren       The number of handles in ChildHandleBuffer.
+  @param  ChildHandleBuffer      The array of child handle.
+
+  @retval EFI_SUCCESS            The device was stopped.
+  @retval EFI_DEVICE_ERROR       The device could not be stopped due to a device error.
+  @retval Others                 Fail to uninstall protocols attached on the device.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL  *This,
+  IN  EFI_HANDLE                   Controller,
+  IN  UINTN                        NumberOfChildren,
+  IN  EFI_HANDLE                   *ChildHandleBuffer
+  );
+
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PAVIRTUALETER Language is NULL.
+
+  @retval EFI_INVALID_PAVIRTUALETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
+  IN  CHAR8                        *Language,
+  OUT CHAR16                       **DriverName
+  );
+
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PAVIRTUALETER ControllerHandle is NULL.
+
+  @retval EFI_INVALID_PAVIRTUALETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PAVIRTUALETER Language is NULL.
+
+  @retval EFI_INVALID_PAVIRTUALETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
+  IN  EFI_HANDLE                                      ControllerHandle,
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
+  IN  CHAR8                                           *Language,
+  OUT CHAR16                                          **ControllerName
+  );
+
+
+//
+// Simple Text Input Protocol functions
+//
+/**
+  Reset the Keyboard and do BAT test for it, if (ExtendedVerification == TRUE) then do some extra keyboard validations.
+
+  @param  This                  Pointer of simple text Protocol.
+  @param  ExtendedVerification  Whether perform the extra validation of keyboard. True: perform; FALSE: skip.
+
+  @retval EFI_SUCCESS           The command byte is written successfully.
+  @retval EFI_DEVICE_ERROR      Errors occurred during resetting keyboard.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardReset (
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This,
+  IN  BOOLEAN                         ExtendedVerification
+  );
+
+/**
+  Reset the input device and optionaly run diagnostics
+
+  @param  This                  Protocol instance pointer.
+  @param  ExtendedVerification  Driver may perform diagnostics on reset.
+
+  @retval EFI_SUCCESS           The device was reset.
+  @retval EFI_DEVICE_ERROR      The device is not functioning properly and could 
+                                not be reset.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardResetEx (
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,
+  IN BOOLEAN                            ExtendedVerification
+  );
+
+/**
+  Set certain state for the input device.
+
+  @param  This              Protocol instance pointer.
+  @param  KeyToggleState    A pointer to the EFI_KEY_TOGGLE_STATE to set the
+                            state for the input device.
+
+  @retval EFI_SUCCESS           The device state was set successfully.
+  @retval EFI_DEVICE_ERROR      The device is not functioning correctly and could
+                                not have the setting adjusted.
+  @retval EFI_UNSUPPORTED       The device does not have the ability to set its state.
+  @retval EFI_INVALID_PAVIRTUALETER KeyToggleState is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardSetState (
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,
+  IN EFI_KEY_TOGGLE_STATE               *KeyToggleState
+  );
+
+/**
+  Register a notification function for a particular keystroke for the input device.
+
+  @param  This                    Protocol instance pointer.
+  @param  KeyData                 A pointer to a buffer that is filled in with the keystroke
+                                  information data for the key that was pressed.
+  @param  KeyNotificationFunction Points to the function to be called when the key
+                                  sequence is typed specified by KeyData.
+  @param  NotifyHandle            Points to the unique handle assigned to the registered notification.
+
+
+  @retval EFI_SUCCESS             The notification function was registered successfully.
+  @retval EFI_OUT_OF_RESOURCES    Unable to allocate resources for necesssary data structures.
+  @retval EFI_INVALID_PAVIRTUALETER   KeyData or NotifyHandle is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardRegisterKeyNotify (
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,
+  IN EFI_KEY_DATA                       *KeyData,
+  IN EFI_KEY_NOTIFY_FUNCTION            KeyNotificationFunction,
+  OUT VOID                              **NotifyHandle
+  );
+
+/**
+  Remove a registered notification function from a particular keystroke.
+
+  @param  This                 Protocol instance pointer.
+  @param  NotificationHandle   The handle of the notification function being unregistered.
+
+  @retval EFI_SUCCESS             The notification function was unregistered successfully.
+  @retval EFI_INVALID_PAVIRTUALETER   The NotificationHandle is invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardUnregisterKeyNotify (
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,
+  IN VOID                               *NotificationHandle
+  );
+
+//
+// Private worker functions
+//
+/**
+  Free keyboard notify list.
+
+  @param  ListHead   The list head
+
+  @retval EFI_SUCCESS           Free the notify list successfully
+  @retval EFI_INVALID_PAVIRTUALETER ListHead is invalid.
+
+**/
+EFI_STATUS
+VirtualKeyboardFreeNotifyList (
+  IN OUT LIST_ENTRY           *ListHead
+  );
+
+/**
+  Check if key is registered.
+
+  @param  RegsiteredData    A pointer to a buffer that is filled in with the keystroke
+                            state data for the key that was registered.
+  @param  InputData         A pointer to a buffer that is filled in with the keystroke
+                            state data for the key that was pressed.
+
+  @retval TRUE              Key be pressed matches a registered key.
+  @retval FLASE             Match failed.
+
+**/
+BOOLEAN
+IsKeyRegistered (
+  IN EFI_KEY_DATA  *RegsiteredData,
+  IN EFI_KEY_DATA  *InputData
+  );
+
+/**
+  Waiting on the keyboard event, if there's any key pressed by the user, signal the event
+
+  @param  Event       The event that be siganlled when any key has been stroked.
+  @param  Context     Pointer of the protocol EFI_SIMPLE_TEXT_INPUT_PROTOCOL.
+
+**/
+VOID
+EFIAPI
+VirtualKeyboardWaitForKey (
+  IN  EFI_EVENT  Event,
+  IN  VOID       *Context
+  );
+
+/**
+  Waiting on the keyboard event, if there's any key pressed by the user, signal the event
+
+  @param  Event    The event that be siganlled when any key has been stroked.
+  @param  Context  Pointer of the protocol EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.
+
+**/
+VOID
+EFIAPI
+VirtualKeyboardWaitForKeyEx (
+  IN  EFI_EVENT  Event,
+  IN  VOID       *Context
+  );
+
+/**
+  Timer event handler: read a series of key stroke from 8042
+  and put them into memory key buffer.
+  It is registered as running under TPL_NOTIFY
+
+  @param  Event   The timer event
+  @param  Context A VIRTUAL_KEYBOARD_DEV pointer
+
+**/
+VOID
+EFIAPI
+VirtualKeyboardTimerHandler (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  );
+
+/**
+  Process key notify.
+
+  @param  Event                 Indicates the event that invoke this function.
+  @param  Context               Indicates the calling context.
+**/
+VOID
+EFIAPI
+KeyNotifyProcessHandler (
+  IN  EFI_EVENT                 Event,
+  IN  VOID                      *Context
+  );
+
+/**
+  Read out the scan code of the key that has just been stroked.
+
+  @param  This        Pointer of simple text Protocol.
+  @param  Key         Pointer for store the key that read out.
+
+  @retval EFI_SUCCESS The key is read out successfully.
+  @retval other       The key reading failed.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardReadKeyStroke (
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This,
+  OUT EFI_INPUT_KEY                   *Key
+  );
+
+/**
+  Reads the next keystroke from the input device. The WaitForKey Event can
+  be used to test for existance of a keystroke via WaitForEvent () call.
+
+  @param  This         Protocol instance pointer.
+  @param  KeyData      A pointer to a buffer that is filled in with the keystroke
+                       state data for the key that was pressed.
+
+  @retval  EFI_SUCCESS           The keystroke information was returned.
+  @retval  EFI_NOT_READY         There was no keystroke data availiable.
+  @retval  EFI_DEVICE_ERROR      The keystroke information was not returned due to
+                                 hardware errors.
+  @retval  EFI_INVALID_PAVIRTUALETER KeyData is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+VirtualKeyboardReadKeyStrokeEx (
+  IN  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,
+  OUT EFI_KEY_DATA                      *KeyData
+  );
+
+#endif /* _VIRTUAL_KEYBOARD_H_ */
diff --git a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dec b/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.dec
index 496442a..0f10e47 100644
--- a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dec
+++ b/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.dec
@@ -1,36 +1,39 @@
-#/** @file
-# Beagle board package.
-#
-# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
-#
-#    This program and the accompanying materials are licensed and made available under
-#    the terms and conditions of the BSD License which accompanies this distribution.
-#    The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
-#
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = BeagleBoardPkg
-  PACKAGE_GUID                   = 6eba6648-d853-4eb3-9761-528b82d5ab04
-  PACKAGE_VERSION                = 0.1
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-#                   Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-[Includes.common]
-  Include                        # Root include for the package
-
-[Guids.common]
-  gBeagleBoardTokenSpaceGuid    =  { 0x6834fe45, 0x4aee, 0x4fc6, { 0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xe2 } }
-
+#/** @file
+# Framework Module Development Environment Industry Standards
+#
+# This Package provides headers and libraries that conform to EFI/PI Industry standards.
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro. All rights reserved.<BR>
+#
+#    This program and the accompanying materials are licensed and made available under
+#    the terms and conditions of the BSD License which accompanies this distribution.
+#    The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = VirtualKeyboardDxePkg
+  PACKAGE_GUID                   = 774326bc-20d0-4203-97e4-10dc17f7dc1a
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+  gVirtualKeyboardDxeTokenSpaceGuid    = { 0x80caf901, 0x0cf6, 0x4c09, { 0x89, 0x84, 0x61, 0xd1, 0xf3, 0xd2, 0x54, 0x39 }}
+
+[Protocols.common]
+  gPlatformVirtualKeyboardProtocolGuid = { 0x0e3606d2, 0x1dc3, 0x4e6f, { 0xbe, 0x65, 0x39, 0x49, 0x82, 0xa2, 0x65, 0x47 }}
diff --git a/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.inf b/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
new file mode 100644
index 0000000..9cfc82f
--- /dev/null
+++ b/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
@@ -0,0 +1,61 @@
+## @file
+# Virtual Keyboard driver.
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions
+# of the BSD License which accompanies this distribution.  The
+# full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = VirtualKeyboardDxe
+  FILE_GUID                      = 88079b18-b42b-44aa-a6f2-b83911075e89
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeVirtualKeyboard
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+#  DRIVER_BINDING                = gVirtualKeyboardDriverBinding
+#  COMPONENT_NAME                = gVirtualKeyboardComponentName
+#
+
+[Sources.common]
+  ComponentName.c
+  VirtualKeyboard.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  IoLib
+  ReportStatusCodeLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  UefiLib
+
+[Protocols]
+  gEfiDriverBindingProtocolGuid
+  gEfiSimpleTextInProtocolGuid
+  gEfiSimpleTextInputExProtocolGuid
+  gPlatformVirtualKeyboardProtocolGuid
+
+[Depex]
+  TRUE
diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmc.h b/Drivers/Mmc/DwEmmcDxe/DwEmmc.h
index 999b584..055f1e0 100644
--- a/Drivers/Mmc/DwEmmcDxe/DwEmmc.h
+++ b/Drivers/Mmc/DwEmmcDxe/DwEmmc.h
@@ -1,128 +1,127 @@
-/** @file
-*
-*  Copyright (c) 2014, Linaro Limited. All rights reserved.
-*  Copyright (c) 2014, Hisilicon Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-
-#ifndef __DWEMMC_H__
-#define __DWEMMC_H__
-
-#include <Protocol/EmbeddedGpio.h>
-
-// DW MMC Registers
-#define DWEMMC_CTRL		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)
-#define DWEMMC_PWREN		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)
-#define DWEMMC_CLKDIV		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)
-#define DWEMMC_CLKSRC		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)
-#define DWEMMC_CLKENA		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)
-#define DWEMMC_TMOUT		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)
-#define DWEMMC_CTYPE		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)
-#define DWEMMC_BLKSIZ		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)
-#define DWEMMC_BYTCNT		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)
-#define DWEMMC_INTMASK		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)
-#define DWEMMC_CMDARG		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)
-#define DWEMMC_CMD		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)
-#define DWEMMC_RESP0		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)
-#define DWEMMC_RESP1		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)
-#define DWEMMC_RESP2		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)
-#define DWEMMC_RESP3		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)
-#define DWEMMC_RINTSTS		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)
-#define DWEMMC_STATUS		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)
-#define DWEMMC_FIFOTH		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)
-#define DWEMMC_DEBNCE		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)
-#define DWEMMC_UHSREG		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)
-#define DWEMMC_BMOD		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)
-#define DWEMMC_DBADDR		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)
-#define DWEMMC_IDSTS		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)
-#define DWEMMC_IDINTEN		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)
-#define DWEMMC_DSCADDR		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)
-#define DWEMMC_BUFADDR		((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)
-#define DWEMMC_CARDTHRCTL	((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)
-
-#define CMD_UPDATE_CLK				0x80202000
-#define CMD_START_BIT				(1 << 31)
-
-#define MMC_8BIT_MODE				(1 << 16)
-
-#define BIT_CMD_RESPONSE_EXPECT			(1 << 6)
-#define BIT_CMD_LONG_RESPONSE			(1 << 7)
-#define BIT_CMD_CHECK_RESPONSE_CRC		(1 << 8)
-#define BIT_CMD_DATA_EXPECTED			(1 << 9)
-#define BIT_CMD_READ				(0 << 10)
-#define BIT_CMD_WRITE				(1 << 10)
-#define BIT_CMD_BLOCK_TRANSFER			(0 << 11)
-#define BIT_CMD_STREAM_TRANSFER			(1 << 11)
-#define BIT_CMD_SEND_AUTO_STOP			(1 << 12)
-#define BIT_CMD_WAIT_PRVDATA_COMPLETE		(1 << 13)
-#define BIT_CMD_STOP_ABORT_CMD			(1 << 14)
-#define BIT_CMD_SEND_INIT			(1 << 15)
-#define BIT_CMD_UPDATE_CLOCK_ONLY		(1 << 21)
-#define BIT_CMD_READ_CEATA_DEVICE		(1 << 22)
-#define BIT_CMD_CCS_EXPECTED			(1 << 23)
-#define BIT_CMD_ENABLE_BOOT			(1 << 24)
-#define BIT_CMD_EXPECT_BOOT_ACK			(1 << 25)
-#define BIT_CMD_DISABLE_BOOT			(1 << 26)
-#define BIT_CMD_MANDATORY_BOOT			(0 << 27)
-#define BIT_CMD_ALTERNATE_BOOT			(1 << 27)
-#define BIT_CMD_VOLT_SWITCH			(1 << 28)
-#define BIT_CMD_USE_HOLD_REG			(1 << 29)
-#define BIT_CMD_START				(1 << 31)
-
-#define DWEMMC_INT_EBE				(1 << 15)	/* End-bit Err */
-#define DWEMMC_INT_SBE				(1 << 13)	/* Start-bit  Err */
-#define DWEMMC_INT_HLE				(1 << 12)	/* Hardware-lock Err */
-#define DWEMMC_INT_FRUN				(1 << 11)	/* FIFO UN/OV RUN */
-#define DWEMMC_INT_DRT				(1 << 9)	/* Data timeout */
-#define DWEMMC_INT_RTO				(1 << 8)	/* Response timeout */
-#define DWEMMC_INT_DCRC				(1 << 7)	/* Data CRC err */
-#define DWEMMC_INT_RCRC				(1 << 6)	/* Response CRC err */
-#define DWEMMC_INT_RXDR				(1 << 5)
-#define DWEMMC_INT_TXDR				(1 << 4)
-#define DWEMMC_INT_DTO				(1 << 3)	/* Data trans over */
-#define DWEMMC_INT_CMD_DONE			(1 << 2)
-#define DWEMMC_INT_RE				(1 << 1)
-
-#define DWEMMC_IDMAC_DES0_DIC			(1 << 1)
-#define DWEMMC_IDMAC_DES0_LD			(1 << 2)
-#define DWEMMC_IDMAC_DES0_FS			(1 << 3)
-#define DWEMMC_IDMAC_DES0_CH			(1 << 4)
-#define DWEMMC_IDMAC_DES0_ER			(1 << 5)
-#define DWEMMC_IDMAC_DES0_CES			(1 << 30)
-#define DWEMMC_IDMAC_DES0_OWN			(1 << 31)
-#define DWEMMC_IDMAC_DES1_BS1(x)		((x) & 0x1fff)
-#define DWEMMC_IDMAC_DES2_BS2(x)		(((x) & 0x1fff) << 13)
-#define DWEMMC_IDMAC_SWRESET			(1 << 0)
-#define DWEMMC_IDMAC_FB				(1 << 1)
-#define DWEMMC_IDMAC_ENABLE			(1 << 7)
-
-#define EMMC_FIX_RCA				6
-
-/* bits in MMC0_CTRL */
-#define DWEMMC_CTRL_RESET			(1 << 0)
-#define DWEMMC_CTRL_FIFO_RESET			(1 << 1)
-#define DWEMMC_CTRL_DMA_RESET			(1 << 2)
-#define DWEMMC_CTRL_INT_EN			(1 << 4)
-#define DWEMMC_CTRL_DMA_EN			(1 << 5)
-#define DWEMMC_CTRL_IDMAC_EN			(1 << 25)
-#define DWEMMC_CTRL_RESET_ALL			(DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)
-
-#define DWEMMC_STS_DATA_BUSY			(1 << 9)
-
-#define DWEMMC_FIFO_TWMARK(x)			(x & 0xfff)
-#define DWEMMC_FIFO_RWMARK(x)			((x & 0x1ff) << 16)
-#define DWEMMC_DMA_BURST_SIZE(x)		((x & 0x7) << 28)
-
-#define DWEMMC_CARD_RD_THR(x)			((x & 0xfff) << 16)
-#define DWEMMC_CARD_RD_THR_EN			(1 << 0)
-
-#endif  // __DWEMMC_H__
+/** @file
+*
+*  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef __DWEMMC_H__
+#define __DWEMMC_H__
+
+#include <Protocol/EmbeddedGpio.h>
+
+// DW MMC Registers
+#define DWEMMC_CTRL             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)
+#define DWEMMC_PWREN            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)
+#define DWEMMC_CLKDIV           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)
+#define DWEMMC_CLKSRC           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)
+#define DWEMMC_CLKENA           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)
+#define DWEMMC_TMOUT            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)
+#define DWEMMC_CTYPE            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)
+#define DWEMMC_BLKSIZ           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)
+#define DWEMMC_BYTCNT           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)
+#define DWEMMC_INTMASK          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)
+#define DWEMMC_CMDARG           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)
+#define DWEMMC_CMD              ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)
+#define DWEMMC_RESP0            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)
+#define DWEMMC_RESP1            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)
+#define DWEMMC_RESP2            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)
+#define DWEMMC_RESP3            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)
+#define DWEMMC_RINTSTS          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)
+#define DWEMMC_STATUS           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)
+#define DWEMMC_FIFOTH           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)
+#define DWEMMC_DEBNCE           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)
+#define DWEMMC_UHSREG           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)
+#define DWEMMC_BMOD             ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)
+#define DWEMMC_DBADDR           ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)
+#define DWEMMC_IDSTS            ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)
+#define DWEMMC_IDINTEN          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)
+#define DWEMMC_DSCADDR          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)
+#define DWEMMC_BUFADDR          ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)
+#define DWEMMC_CARDTHRCTL       ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)
+
+#define CMD_UPDATE_CLK                          0x80202000
+#define CMD_START_BIT                           (1 << 31)
+
+#define MMC_8BIT_MODE                           (1 << 16)
+
+#define BIT_CMD_RESPONSE_EXPECT                 (1 << 6)
+#define BIT_CMD_LONG_RESPONSE                   (1 << 7)
+#define BIT_CMD_CHECK_RESPONSE_CRC              (1 << 8)
+#define BIT_CMD_DATA_EXPECTED                   (1 << 9)
+#define BIT_CMD_READ                            (0 << 10)
+#define BIT_CMD_WRITE                           (1 << 10)
+#define BIT_CMD_BLOCK_TRANSFER                  (0 << 11)
+#define BIT_CMD_STREAM_TRANSFER                 (1 << 11)
+#define BIT_CMD_SEND_AUTO_STOP                  (1 << 12)
+#define BIT_CMD_WAIT_PRVDATA_COMPLETE           (1 << 13)
+#define BIT_CMD_STOP_ABORT_CMD                  (1 << 14)
+#define BIT_CMD_SEND_INIT                       (1 << 15)
+#define BIT_CMD_UPDATE_CLOCK_ONLY               (1 << 21)
+#define BIT_CMD_READ_CEATA_DEVICE               (1 << 22)
+#define BIT_CMD_CCS_EXPECTED                    (1 << 23)
+#define BIT_CMD_ENABLE_BOOT                     (1 << 24)
+#define BIT_CMD_EXPECT_BOOT_ACK                 (1 << 25)
+#define BIT_CMD_DISABLE_BOOT                    (1 << 26)
+#define BIT_CMD_MANDATORY_BOOT                  (0 << 27)
+#define BIT_CMD_ALTERNATE_BOOT                  (1 << 27)
+#define BIT_CMD_VOLT_SWITCH                     (1 << 28)
+#define BIT_CMD_USE_HOLD_REG                    (1 << 29)
+#define BIT_CMD_START                           (1 << 31)
+
+#define DWEMMC_INT_EBE                          (1 << 15)       /* End-bit Err */
+#define DWEMMC_INT_SBE                          (1 << 13)       /* Start-bit  Err */
+#define DWEMMC_INT_HLE                          (1 << 12)       /* Hardware-lock Err */
+#define DWEMMC_INT_FRUN                         (1 << 11)       /* FIFO UN/OV RUN */
+#define DWEMMC_INT_DRT                          (1 << 9)        /* Data timeout */
+#define DWEMMC_INT_RTO                          (1 << 8)        /* Response timeout */
+#define DWEMMC_INT_DCRC                         (1 << 7)        /* Data CRC err */
+#define DWEMMC_INT_RCRC                         (1 << 6)        /* Response CRC err */
+#define DWEMMC_INT_RXDR                         (1 << 5)
+#define DWEMMC_INT_TXDR                         (1 << 4)
+#define DWEMMC_INT_DTO                          (1 << 3)        /* Data trans over */
+#define DWEMMC_INT_CMD_DONE                     (1 << 2)
+#define DWEMMC_INT_RE                           (1 << 1)
+
+#define DWEMMC_IDMAC_DES0_DIC                   (1 << 1)
+#define DWEMMC_IDMAC_DES0_LD                    (1 << 2)
+#define DWEMMC_IDMAC_DES0_FS                    (1 << 3)
+#define DWEMMC_IDMAC_DES0_CH                    (1 << 4)
+#define DWEMMC_IDMAC_DES0_ER                    (1 << 5)
+#define DWEMMC_IDMAC_DES0_CES                   (1 << 30)
+#define DWEMMC_IDMAC_DES0_OWN                   (1 << 31)
+#define DWEMMC_IDMAC_DES1_BS1(x)                ((x) & 0x1fff)
+#define DWEMMC_IDMAC_DES2_BS2(x)                (((x) & 0x1fff) << 13)
+#define DWEMMC_IDMAC_SWRESET                    (1 << 0)
+#define DWEMMC_IDMAC_FB                         (1 << 1)
+#define DWEMMC_IDMAC_ENABLE                     (1 << 7)
+
+#define EMMC_FIX_RCA                            6
+
+/* bits in MMC0_CTRL */
+#define DWEMMC_CTRL_RESET                       (1 << 0)
+#define DWEMMC_CTRL_FIFO_RESET                  (1 << 1)
+#define DWEMMC_CTRL_DMA_RESET                   (1 << 2)
+#define DWEMMC_CTRL_INT_EN                      (1 << 4)
+#define DWEMMC_CTRL_DMA_EN                      (1 << 5)
+#define DWEMMC_CTRL_IDMAC_EN                    (1 << 25)
+#define DWEMMC_CTRL_RESET_ALL                   (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)
+
+#define DWEMMC_STS_DATA_BUSY                    (1 << 9)
+
+#define DWEMMC_FIFO_TWMARK(x)                   (x & 0xfff)
+#define DWEMMC_FIFO_RWMARK(x)                   ((x & 0x1ff) << 16)
+#define DWEMMC_DMA_BURST_SIZE(x)                ((x & 0x7) << 28)
+
+#define DWEMMC_CARD_RD_THR(x)                   ((x & 0xfff) << 16)
+#define DWEMMC_CARD_RD_THR_EN                   (1 << 0)
+
+#endif  // __DWEMMC_H__
diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c
index 6f43677..fe23d11 100644
--- a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c
+++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c
@@ -1,643 +1,648 @@
-/** @file
-  This file implement the MMC Host Protocol for the DesignWare eMMC.
-
-  Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
-  Copyright (c) 2014-2016, Hisilicon Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Library/TimerLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Protocol/MmcHost.h>
-
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
-
-#include "DwEmmc.h"
-
-#define DWEMMC_DESC_PAGE		1
-#define DWEMMC_BLOCK_SIZE		512
-#define DWEMMC_DMA_BUF_SIZE		(512 * 8)
-#define DWEMMC_MAX_DESC_PAGES   	512
-
-typedef struct {
-  UINT32		Des0;
-  UINT32		Des1;
-  UINT32		Des2;
-  UINT32		Des3;
-} DWEMMC_IDMAC_DESCRIPTOR;
-
-EFI_MMC_HOST_PROTOCOL     *gpMmcHost;
-DWEMMC_IDMAC_DESCRIPTOR   *gpIdmacDesc;
-EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID;
-STATIC UINT32 mDwEmmcCommand;
-STATIC UINT32 mDwEmmcArgument;
-
-EFI_STATUS
-DwEmmcReadBlockData (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN EFI_LBA                    Lba,
-  IN UINTN                      Length,
-  IN UINT32*                    Buffer
-  );
-
-BOOLEAN
-DwEmmcIsPowerOn (
-  VOID
-  )
-{
-    return TRUE;
-}
-
-EFI_STATUS
-DwEmmcInitialize (
-  VOID
-  )
-{
-    DEBUG ((EFI_D_BLKIO, "DwEmmcInitialize()"));
-    return EFI_SUCCESS;
-}
-
-BOOLEAN
-DwEmmcIsCardPresent (
-  IN EFI_MMC_HOST_PROTOCOL     *This
-  )
-{
-  return TRUE;
-}
-
-BOOLEAN
-DwEmmcIsReadOnly (
-  IN EFI_MMC_HOST_PROTOCOL     *This
-  )
-{
-  return FALSE;
-}
-
-BOOLEAN
-DwEmmcIsDmaSupported (
-  IN EFI_MMC_HOST_PROTOCOL     *This
-  )
-{
-  return TRUE;
-}
-
-EFI_STATUS
-DwEmmcBuildDevicePath (
-  IN EFI_MMC_HOST_PROTOCOL      *This,
-  IN EFI_DEVICE_PATH_PROTOCOL   **DevicePath
-  )
-{
-  EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
-
-  NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
-  CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwEmmcDevicePathGuid);
-
-  *DevicePath = NewDevicePathNode;
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DwEmmcUpdateClock (
-  VOID
-  )
-{
-  UINT32 Data;
-
-  /* CMD_UPDATE_CLK */
-  Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
-	 BIT_CMD_START;
-  MmioWrite32 (DWEMMC_CMD, Data);
-  while (1) {
-    Data = MmioRead32 (DWEMMC_CMD);
-    if (!(Data & CMD_START_BIT))
-      break;
-    Data = MmioRead32 (DWEMMC_RINTSTS);
-    if (Data & DWEMMC_INT_HLE)
-    {
-      Print (L"failed to update mmc clock frequency\n");
-      return EFI_DEVICE_ERROR;
-    }
-  }
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DwEmmcSetClock (
-  IN UINTN                     ClockFreq
-  )
-{
-  UINT32 Divider, Rate, Data;
-  EFI_STATUS Status;
-  BOOLEAN Found = FALSE;
-
-  for (Divider = 1; Divider < 256; Divider++) {
-    Rate = PcdGet32 (PcdDwEmmcDxeClockFrequencyInHz);
-    if ((Rate / (2 * Divider)) <= ClockFreq) {
-      Found = TRUE;
-      break;
-    }
-  }
-  if (Found == FALSE)
-    return EFI_NOT_FOUND;
-
-  // Wait until MMC is idle
-  do {
-    Data = MmioRead32 (DWEMMC_STATUS);
-  } while (Data & DWEMMC_STS_DATA_BUSY);
-
-  // Disable MMC clock first
-  MmioWrite32 (DWEMMC_CLKENA, 0);
-  Status = DwEmmcUpdateClock ();
-  ASSERT (!EFI_ERROR (Status));
-
-  MmioWrite32 (DWEMMC_CLKDIV, Divider);
-  Status = DwEmmcUpdateClock ();
-  ASSERT (!EFI_ERROR (Status));
-
-  // Enable MMC clock
-  MmioWrite32 (DWEMMC_CLKENA, 1);
-  MmioWrite32 (DWEMMC_CLKSRC, 0);
-  Status = DwEmmcUpdateClock ();
-  ASSERT (!EFI_ERROR (Status));
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DwEmmcNotifyState (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_STATE                 State
-  )
-{
-  UINT32      Data;
-  EFI_STATUS  Status;
-
-  switch (State) {
-  case MmcInvalidState:
-    ASSERT (0);
-    break;
-  case MmcHwInitializationState:
-    MmioWrite32 (DWEMMC_PWREN, 1);
-
-    // If device already turn on then restart it
-    Data = DWEMMC_CTRL_RESET_ALL;
-    MmioWrite32 (DWEMMC_CTRL, Data);
-    do {
-      // Wait until reset operation finished
-      Data = MmioRead32 (DWEMMC_CTRL);
-    } while (Data & DWEMMC_CTRL_RESET_ALL);
-
-    // Setup clock that could not be higher than 400KHz.
-    Status = DwEmmcSetClock (400000);
-    ASSERT (!EFI_ERROR (Status));
-    MicroSecondDelay (100);
-
-    MmioWrite32 (DWEMMC_RINTSTS, ~0);
-    MmioWrite32 (DWEMMC_INTMASK, 0);
-    MmioWrite32 (DWEMMC_TMOUT, ~0);
-    MmioWrite32 (DWEMMC_IDINTEN, 0);
-    MmioWrite32 (DWEMMC_BMOD, DWEMMC_IDMAC_SWRESET);
-
-    MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
-    do {
-      Data = MmioRead32 (DWEMMC_BMOD);
-    } while (Data & DWEMMC_IDMAC_SWRESET);
-    break;
-  case MmcIdleState:
-    break;
-  case MmcReadyState:
-    break;
-  case MmcIdentificationState:
-    break;
-  case MmcStandByState:
-    break;
-  case MmcTransferState:
-    break;
-  case MmcSendingDataState:
-    break;
-  case MmcReceiveDataState:
-    break;
-  case MmcProgrammingState:
-    break;
-  case MmcDisconnectState:
-    break;
-  default:
-    ASSERT (0);
-  }
-  return EFI_SUCCESS;
-}
-
-// Need to prepare DMA buffer first before sending commands to MMC card
-BOOLEAN
-IsPendingReadCommand (
-  IN MMC_CMD                    MmcCmd
-  )
-{
-  UINTN  Mask;
-
-  Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
-  if ((MmcCmd & Mask) == Mask)
-    return TRUE;
-  return FALSE;
-}
-
-BOOLEAN
-IsPendingWriteCommand (
-  IN MMC_CMD                    MmcCmd
-  )
-{
-  UINTN  Mask;
-
-  Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
-  if ((MmcCmd & Mask) == Mask)
-    return TRUE;
-  return FALSE;
-}
-
-EFI_STATUS
-SendCommand (
-  IN MMC_CMD                    MmcCmd,
-  IN UINT32                     Argument
-  )
-{
-  UINT32      Data, ErrMask;
-
-  // Wait until MMC is idle
-  do {
-    Data = MmioRead32 (DWEMMC_STATUS);
-  } while (Data & DWEMMC_STS_DATA_BUSY);
-
-  MmioWrite32 (DWEMMC_RINTSTS, ~0);
-  MmioWrite32 (DWEMMC_CMDARG, Argument);
-  MmioWrite32 (DWEMMC_CMD, MmcCmd);
-
-  ErrMask = DWEMMC_INT_EBE | DWEMMC_INT_HLE | DWEMMC_INT_RTO |
-            DWEMMC_INT_RCRC | DWEMMC_INT_RE;
-  ErrMask |= DWEMMC_INT_DCRC | DWEMMC_INT_DRT | DWEMMC_INT_SBE;
-  do {
-    MicroSecondDelay(500);
-    Data = MmioRead32 (DWEMMC_RINTSTS);
-
-    if (Data & ErrMask)
-      return EFI_DEVICE_ERROR;
-    if (Data & DWEMMC_INT_DTO)	// Transfer Done
-      break;
-  } while (!(Data & DWEMMC_INT_CMD_DONE));
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DwEmmcSendCommand (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_CMD                    MmcCmd,
-  IN UINT32                     Argument
-  )
-{
-  UINT32       Cmd = 0;
-  EFI_STATUS   Status = EFI_SUCCESS;
-
-  switch (MMC_GET_INDX(MmcCmd)) {
-  case MMC_INDX(0):
-    Cmd = BIT_CMD_SEND_INIT;
-    break;
-  case MMC_INDX(1):
-    Cmd = BIT_CMD_RESPONSE_EXPECT;
-    break;
-  case MMC_INDX(2):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
-           BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
-    break;
-  case MMC_INDX(3):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_SEND_INIT;
-    break;
-  case MMC_INDX(7):
-    if (Argument)
-        Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
-    else
-        Cmd = 0;
-    break;
-  case MMC_INDX(8):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(9):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_LONG_RESPONSE;
-    break;
-  case MMC_INDX(12):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_STOP_ABORT_CMD;
-    break;
-  case MMC_INDX(13):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(16):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(17):
-  case MMC_INDX(18):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(24):
-  case MMC_INDX(25):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(30):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED;
-    break;
-  default:
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
-    break;
-  }
-
-  Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
-  if (IsPendingReadCommand (Cmd) || IsPendingWriteCommand (Cmd)) {
-    mDwEmmcCommand = Cmd;
-    mDwEmmcArgument = Argument;
-  } else {
-    Status = SendCommand (Cmd, Argument);
-  }
-  return Status;
-}
-
-EFI_STATUS
-DwEmmcReceiveResponse (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_RESPONSE_TYPE          Type,
-  IN UINT32*                    Buffer
-  )
-{
-  if (Buffer == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  if (   (Type == MMC_RESPONSE_TYPE_R1)
-      || (Type == MMC_RESPONSE_TYPE_R1b)
-      || (Type == MMC_RESPONSE_TYPE_R3)
-      || (Type == MMC_RESPONSE_TYPE_R6)
-      || (Type == MMC_RESPONSE_TYPE_R7))
-  {
-    Buffer[0] = MmioRead32 (DWEMMC_RESP0);
-  } else if (Type == MMC_RESPONSE_TYPE_R2) {
-    Buffer[0] = MmioRead32 (DWEMMC_RESP0);
-    Buffer[1] = MmioRead32 (DWEMMC_RESP1);
-    Buffer[2] = MmioRead32 (DWEMMC_RESP2);
-    Buffer[3] = MmioRead32 (DWEMMC_RESP3);
-  }
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-PrepareDmaData (
-  IN DWEMMC_IDMAC_DESCRIPTOR*    IdmacDesc,
-  IN UINTN                      Length,
-  IN UINT32*                    Buffer
-  )
-{
-  UINTN  Cnt, Blks, Idx, LastIdx;
-
-  Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
-  Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
-  Length = DWEMMC_BLOCK_SIZE * Blks;
-
-  for (Idx = 0; Idx < Cnt; Idx++) {
-    (IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |
-	    		      DWEMMC_IDMAC_DES0_DIC;
-    (IdmacDesc + Idx)->Des1 = DWEMMC_IDMAC_DES1_BS1(DWEMMC_DMA_BUF_SIZE);
-    /* Buffer Address */
-    (IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWEMMC_DMA_BUF_SIZE * Idx);
-    /* Next Descriptor Address */
-    (IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +
-   	                               (sizeof(DWEMMC_IDMAC_DESCRIPTOR) * (Idx + 1)));
-  }
-  /* First Descriptor */
-  IdmacDesc->Des0 |= DWEMMC_IDMAC_DES0_FS;
-  /* Last Descriptor */
-  LastIdx = Cnt - 1;
-  (IdmacDesc + LastIdx)->Des0 |= DWEMMC_IDMAC_DES0_LD;
-  (IdmacDesc + LastIdx)->Des0 &= ~(DWEMMC_IDMAC_DES0_DIC | DWEMMC_IDMAC_DES0_CH);
-  (IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -
-   		                (LastIdx * DWEMMC_DMA_BUF_SIZE));
-  /* Set the Next field of Last Descriptor */
-  (IdmacDesc + LastIdx)->Des3 = 0;
-  MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
-
-  return EFI_SUCCESS;
-}
-
-VOID
-StartDma (
-  UINTN    Length
-  )
-{
-  UINT32 Data;
-
-  Data = MmioRead32 (DWEMMC_CTRL);
-  Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
-  MmioWrite32 (DWEMMC_CTRL, Data);
-  Data = MmioRead32 (DWEMMC_BMOD);
-  Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
-  MmioWrite32 (DWEMMC_BMOD, Data);
-
-  MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
-  MmioWrite32 (DWEMMC_BYTCNT, Length);
-}
-
-EFI_STATUS
-DwEmmcReadBlockData (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN EFI_LBA                    Lba,
-  IN UINTN                      Length,
-  IN UINT32*                   Buffer
-  )
-{
-  EFI_STATUS  Status;
-  UINT32      DescPages, CountPerPage, Count;
-  EFI_TPL     Tpl;
-
-  Tpl = gBS->RaiseTPL (TPL_NOTIFY);
-
-  CountPerPage = EFI_PAGE_SIZE / 16;
-  Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
-  DescPages = (Count + CountPerPage - 1) / CountPerPage;
-
-  InvalidateDataCacheRange (Buffer, Length);
-
-  Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
-  if (EFI_ERROR (Status))
-    goto out;
-
-  WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
-  StartDma (Length);
-
-  Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
-    goto out;
-  }
-out:
-  // Restore Tpl
-  gBS->RestoreTPL (Tpl);
-  return Status;
-}
-
-EFI_STATUS
-DwEmmcWriteBlockData (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN EFI_LBA                    Lba,
-  IN UINTN                      Length,
-  IN UINT32*                    Buffer
-  )
-{
-  EFI_STATUS  Status;
-  UINT32      DescPages, CountPerPage, Count;
-  EFI_TPL     Tpl;
-
-  Tpl = gBS->RaiseTPL (TPL_NOTIFY);
-
-  CountPerPage = EFI_PAGE_SIZE / 16;
-  Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
-  DescPages = (Count + CountPerPage - 1) / CountPerPage;
-
-  WriteBackDataCacheRange (Buffer, Length);
-
-  Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
-  if (EFI_ERROR (Status))
-    goto out;
-
-  WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
-  StartDma (Length);
-
-  Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
-    goto out;
-  }
-out:
-  // Restore Tpl
-  gBS->RestoreTPL (Tpl);
-  return Status;
-}
-
-EFI_STATUS
-DwEmmcSetIos (
-  IN EFI_MMC_HOST_PROTOCOL      *This,
-  IN  UINT32                    BusClockFreq,
-  IN  UINT32                    BusWidth,
-  IN  UINT32                    TimingMode
-  )
-{
-  EFI_STATUS Status = EFI_SUCCESS;
-  UINT32    Data;
-
-  if (TimingMode != EMMCBACKWARD) {
-    Data = MmioRead32 (DWEMMC_UHSREG);
-    switch (TimingMode) {
-    case EMMCHS52DDR1V2:
-    case EMMCHS52DDR1V8:
-      Data |= 1 << 16;
-      break;
-    case EMMCHS52:
-    case EMMCHS26:
-      Data &= ~(1 << 16);
-      break;
-    default:
-      return EFI_UNSUPPORTED;
-    }
-    MmioWrite32 (DWEMMC_UHSREG, Data);
-  }
-
-  switch (BusWidth) {
-  case 1:
-    MmioWrite32 (DWEMMC_CTYPE, 0);
-    break;
-  case 4:
-    MmioWrite32 (DWEMMC_CTYPE, 1);
-    break;
-  case 8:
-    MmioWrite32 (DWEMMC_CTYPE, 1 << 16);
-    break;
-  default:
-    return EFI_UNSUPPORTED;
-  }
-  if (BusClockFreq) {
-    Status = DwEmmcSetClock (BusClockFreq);
-  }
-  return Status;
-}
-
-BOOLEAN
-DwEmmcIsMultiBlock (
-  IN EFI_MMC_HOST_PROTOCOL      *This
-  )
-{
-  return TRUE;
-}
-
-EFI_MMC_HOST_PROTOCOL gMciHost = {
-  MMC_HOST_PROTOCOL_REVISION,
-  DwEmmcIsCardPresent,
-  DwEmmcIsReadOnly,
-  DwEmmcBuildDevicePath,
-  DwEmmcNotifyState,
-  DwEmmcSendCommand,
-  DwEmmcReceiveResponse,
-  DwEmmcReadBlockData,
-  DwEmmcWriteBlockData,
-  DwEmmcSetIos,
-  DwEmmcIsMultiBlock
-};
-
-EFI_STATUS
-DwEmmcDxeInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS    Status;
-  EFI_HANDLE    Handle;
-
-  Handle = NULL;
-
-  gpIdmacDesc = (DWEMMC_IDMAC_DESCRIPTOR *)AllocatePages (DWEMMC_MAX_DESC_PAGES);
-  if (gpIdmacDesc == NULL)
-    return EFI_BUFFER_TOO_SMALL;
-
-  DEBUG ((EFI_D_BLKIO, "DwEmmcDxeInitialize()\n"));
-
-  //Publish Component Name, BlockIO protocol interfaces
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &Handle,
-                  &gEfiMmcHostProtocolGuid,         &gMciHost,
-                  NULL
-                  );
-  ASSERT_EFI_ERROR (Status);
-
-  return EFI_SUCCESS;
-}
+/** @file
+  This file implement the MMC Host Protocol for the DesignWare eMMC.
+
+  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/MmcHost.h>
+
+#include "DwEmmc.h"
+
+#define DWEMMC_DESC_PAGE                1
+#define DWEMMC_BLOCK_SIZE               512
+#define DWEMMC_DMA_BUF_SIZE             (512 * 8)
+#define DWEMMC_MAX_DESC_PAGES           512
+
+typedef struct {
+  UINT32                        Des0;
+  UINT32                        Des1;
+  UINT32                        Des2;
+  UINT32                        Des3;
+} DWEMMC_IDMAC_DESCRIPTOR;
+
+EFI_MMC_HOST_PROTOCOL     *gpMmcHost;
+DWEMMC_IDMAC_DESCRIPTOR   *gpIdmacDesc;
+EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID;
+STATIC UINT32 mDwEmmcCommand;
+STATIC UINT32 mDwEmmcArgument;
+
+EFI_STATUS
+DwEmmcReadBlockData (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN EFI_LBA                    Lba,
+  IN UINTN                      Length,
+  IN UINT32*                    Buffer
+  );
+
+BOOLEAN
+DwEmmcIsPowerOn (
+  VOID
+  )
+{
+    return TRUE;
+}
+
+EFI_STATUS
+DwEmmcInitialize (
+  VOID
+  )
+{
+    DEBUG ((DEBUG_BLKIO, "DwEmmcInitialize()"));
+    return EFI_SUCCESS;
+}
+
+BOOLEAN
+DwEmmcIsCardPresent (
+  IN EFI_MMC_HOST_PROTOCOL     *This
+  )
+{
+  return TRUE;
+}
+
+BOOLEAN
+DwEmmcIsReadOnly (
+  IN EFI_MMC_HOST_PROTOCOL     *This
+  )
+{
+  return FALSE;
+}
+
+BOOLEAN
+DwEmmcIsDmaSupported (
+  IN EFI_MMC_HOST_PROTOCOL     *This
+  )
+{
+  return TRUE;
+}
+
+EFI_STATUS
+DwEmmcBuildDevicePath (
+  IN EFI_MMC_HOST_PROTOCOL      *This,
+  IN EFI_DEVICE_PATH_PROTOCOL   **DevicePath
+  )
+{
+  EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
+
+  NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
+  CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwEmmcDevicePathGuid);
+
+  *DevicePath = NewDevicePathNode;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcUpdateClock (
+  VOID
+  )
+{
+  UINT32 Data;
+
+  /* CMD_UPDATE_CLK */
+  Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
+         BIT_CMD_START;
+  MmioWrite32 (DWEMMC_CMD, Data);
+  while (1) {
+    Data = MmioRead32 (DWEMMC_CMD);
+    if (!(Data & CMD_START_BIT)) {
+      break;
+    }
+    Data = MmioRead32 (DWEMMC_RINTSTS);
+    if (Data & DWEMMC_INT_HLE) {
+      Print (L"failed to update mmc clock frequency\n");
+      return EFI_DEVICE_ERROR;
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcSetClock (
+  IN UINTN                     ClockFreq
+  )
+{
+  UINT32 Divider, Rate, Data;
+  EFI_STATUS Status;
+  BOOLEAN Found = FALSE;
+
+  for (Divider = 1; Divider < 256; Divider++) {
+    Rate = PcdGet32 (PcdDwEmmcDxeClockFrequencyInHz);
+    if ((Rate / (2 * Divider)) <= ClockFreq) {
+      Found = TRUE;
+      break;
+    }
+  }
+  if (Found == FALSE) {
+    return EFI_NOT_FOUND;
+  }
+
+  // Wait until MMC is idle
+  do {
+    Data = MmioRead32 (DWEMMC_STATUS);
+  } while (Data & DWEMMC_STS_DATA_BUSY);
+
+  // Disable MMC clock first
+  MmioWrite32 (DWEMMC_CLKENA, 0);
+  Status = DwEmmcUpdateClock ();
+  ASSERT (!EFI_ERROR (Status));
+
+  MmioWrite32 (DWEMMC_CLKDIV, Divider);
+  Status = DwEmmcUpdateClock ();
+  ASSERT (!EFI_ERROR (Status));
+
+  // Enable MMC clock
+  MmioWrite32 (DWEMMC_CLKENA, 1);
+  MmioWrite32 (DWEMMC_CLKSRC, 0);
+  Status = DwEmmcUpdateClock ();
+  ASSERT (!EFI_ERROR (Status));
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcNotifyState (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN MMC_STATE                 State
+  )
+{
+  UINT32      Data;
+  EFI_STATUS  Status;
+
+  switch (State) {
+  case MmcInvalidState:
+    return EFI_INVALID_PARAMETER;
+  case MmcHwInitializationState:
+    MmioWrite32 (DWEMMC_PWREN, 1);
+
+    // If device already turn on then restart it
+    Data = DWEMMC_CTRL_RESET_ALL;
+    MmioWrite32 (DWEMMC_CTRL, Data);
+    do {
+      // Wait until reset operation finished
+      Data = MmioRead32 (DWEMMC_CTRL);
+    } while (Data & DWEMMC_CTRL_RESET_ALL);
+
+    // Setup clock that could not be higher than 400KHz.
+    Status = DwEmmcSetClock (400000);
+    ASSERT (!EFI_ERROR (Status));
+    // Wait clock stable
+    MicroSecondDelay (100);
+
+    MmioWrite32 (DWEMMC_RINTSTS, ~0);
+    MmioWrite32 (DWEMMC_INTMASK, 0);
+    MmioWrite32 (DWEMMC_TMOUT, ~0);
+    MmioWrite32 (DWEMMC_IDINTEN, 0);
+    MmioWrite32 (DWEMMC_BMOD, DWEMMC_IDMAC_SWRESET);
+
+    MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
+    do {
+      Data = MmioRead32 (DWEMMC_BMOD);
+    } while (Data & DWEMMC_IDMAC_SWRESET);
+    break;
+  case MmcIdleState:
+    break;
+  case MmcReadyState:
+    break;
+  case MmcIdentificationState:
+    break;
+  case MmcStandByState:
+    break;
+  case MmcTransferState:
+    break;
+  case MmcSendingDataState:
+    break;
+  case MmcReceiveDataState:
+    break;
+  case MmcProgrammingState:
+    break;
+  case MmcDisconnectState:
+    break;
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+  return EFI_SUCCESS;
+}
+
+// Need to prepare DMA buffer first before sending commands to MMC card
+BOOLEAN
+IsPendingReadCommand (
+  IN MMC_CMD                    MmcCmd
+  )
+{
+  UINTN  Mask;
+
+  Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
+  if ((MmcCmd & Mask) == Mask) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+BOOLEAN
+IsPendingWriteCommand (
+  IN MMC_CMD                    MmcCmd
+  )
+{
+  UINTN  Mask;
+
+  Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
+  if ((MmcCmd & Mask) == Mask) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+EFI_STATUS
+SendCommand (
+  IN MMC_CMD                    MmcCmd,
+  IN UINT32                     Argument
+  )
+{
+  UINT32      Data, ErrMask;
+
+  // Wait until MMC is idle
+  do {
+    Data = MmioRead32 (DWEMMC_STATUS);
+  } while (Data & DWEMMC_STS_DATA_BUSY);
+
+  MmioWrite32 (DWEMMC_RINTSTS, ~0);
+  MmioWrite32 (DWEMMC_CMDARG, Argument);
+  MmioWrite32 (DWEMMC_CMD, MmcCmd);
+
+  ErrMask = DWEMMC_INT_EBE | DWEMMC_INT_HLE | DWEMMC_INT_RTO |
+            DWEMMC_INT_RCRC | DWEMMC_INT_RE;
+  ErrMask |= DWEMMC_INT_DCRC | DWEMMC_INT_DRT | DWEMMC_INT_SBE;
+  do {
+    MicroSecondDelay(500);
+    Data = MmioRead32 (DWEMMC_RINTSTS);
+
+    if (Data & ErrMask) {
+      return EFI_DEVICE_ERROR;
+    }
+    if (Data & DWEMMC_INT_DTO) {     // Transfer Done
+      break;
+    }
+  } while (!(Data & DWEMMC_INT_CMD_DONE));
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwEmmcSendCommand (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN MMC_CMD                    MmcCmd,
+  IN UINT32                     Argument
+  )
+{
+  UINT32       Cmd = 0;
+  EFI_STATUS   Status = EFI_SUCCESS;
+
+  switch (MMC_GET_INDX(MmcCmd)) {
+  case MMC_INDX(0):
+    Cmd = BIT_CMD_SEND_INIT;
+    break;
+  case MMC_INDX(1):
+    Cmd = BIT_CMD_RESPONSE_EXPECT;
+    break;
+  case MMC_INDX(2):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
+           BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
+    break;
+  case MMC_INDX(3):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_SEND_INIT;
+    break;
+  case MMC_INDX(7):
+    if (Argument)
+        Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+    else
+        Cmd = 0;
+    break;
+  case MMC_INDX(8):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+           BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(9):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_LONG_RESPONSE;
+    break;
+  case MMC_INDX(12):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_STOP_ABORT_CMD;
+    break;
+  case MMC_INDX(13):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(16):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+           BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(17):
+  case MMC_INDX(18):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+           BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(24):
+  case MMC_INDX(25):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
+           BIT_CMD_WAIT_PRVDATA_COMPLETE;
+    break;
+  case MMC_INDX(30):
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+           BIT_CMD_DATA_EXPECTED;
+    break;
+  default:
+    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+    break;
+  }
+
+  Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
+  if (IsPendingReadCommand (Cmd) || IsPendingWriteCommand (Cmd)) {
+    mDwEmmcCommand = Cmd;
+    mDwEmmcArgument = Argument;
+  } else {
+    Status = SendCommand (Cmd, Argument);
+  }
+  return Status;
+}
+
+EFI_STATUS
+DwEmmcReceiveResponse (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN MMC_RESPONSE_TYPE          Type,
+  IN UINT32*                    Buffer
+  )
+{
+  if (Buffer == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (   (Type == MMC_RESPONSE_TYPE_R1)
+      || (Type == MMC_RESPONSE_TYPE_R1b)
+      || (Type == MMC_RESPONSE_TYPE_R3)
+      || (Type == MMC_RESPONSE_TYPE_R6)
+      || (Type == MMC_RESPONSE_TYPE_R7))
+  {
+    Buffer[0] = MmioRead32 (DWEMMC_RESP0);
+  } else if (Type == MMC_RESPONSE_TYPE_R2) {
+    Buffer[0] = MmioRead32 (DWEMMC_RESP0);
+    Buffer[1] = MmioRead32 (DWEMMC_RESP1);
+    Buffer[2] = MmioRead32 (DWEMMC_RESP2);
+    Buffer[3] = MmioRead32 (DWEMMC_RESP3);
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrepareDmaData (
+  IN DWEMMC_IDMAC_DESCRIPTOR*    IdmacDesc,
+  IN UINTN                      Length,
+  IN UINT32*                    Buffer
+  )
+{
+  UINTN  Cnt, Blks, Idx, LastIdx;
+
+  Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
+  Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
+  Length = DWEMMC_BLOCK_SIZE * Blks;
+
+  for (Idx = 0; Idx < Cnt; Idx++) {
+    (IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |
+                              DWEMMC_IDMAC_DES0_DIC;
+    (IdmacDesc + Idx)->Des1 = DWEMMC_IDMAC_DES1_BS1(DWEMMC_DMA_BUF_SIZE);
+    /* Buffer Address */
+    (IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWEMMC_DMA_BUF_SIZE * Idx);
+    /* Next Descriptor Address */
+    (IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +
+                                       (sizeof(DWEMMC_IDMAC_DESCRIPTOR) * (Idx + 1)));
+  }
+  /* First Descriptor */
+  IdmacDesc->Des0 |= DWEMMC_IDMAC_DES0_FS;
+  /* Last Descriptor */
+  LastIdx = Cnt - 1;
+  (IdmacDesc + LastIdx)->Des0 |= DWEMMC_IDMAC_DES0_LD;
+  (IdmacDesc + LastIdx)->Des0 &= ~(DWEMMC_IDMAC_DES0_DIC | DWEMMC_IDMAC_DES0_CH);
+  (IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -
+                                                      (LastIdx * DWEMMC_DMA_BUF_SIZE));
+  /* Set the Next field of Last Descriptor */
+  (IdmacDesc + LastIdx)->Des3 = 0;
+  MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
+
+  return EFI_SUCCESS;
+}
+
+VOID
+StartDma (
+  UINTN    Length
+  )
+{
+  UINT32 Data;
+
+  Data = MmioRead32 (DWEMMC_CTRL);
+  Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
+  MmioWrite32 (DWEMMC_CTRL, Data);
+  Data = MmioRead32 (DWEMMC_BMOD);
+  Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
+  MmioWrite32 (DWEMMC_BMOD, Data);
+
+  MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
+  MmioWrite32 (DWEMMC_BYTCNT, Length);
+}
+
+EFI_STATUS
+DwEmmcReadBlockData (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN EFI_LBA                    Lba,
+  IN UINTN                      Length,
+  IN UINT32*                   Buffer
+  )
+{
+  EFI_STATUS  Status;
+  UINT32      DescPages, CountPerPage, Count;
+  EFI_TPL     Tpl;
+
+  Tpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  CountPerPage = EFI_PAGE_SIZE / 16;
+  Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
+  DescPages = (Count + CountPerPage - 1) / CountPerPage;
+
+  InvalidateDataCacheRange (Buffer, Length);
+
+  Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
+  if (EFI_ERROR (Status)) {
+    goto out;
+  }
+
+  WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
+  StartDma (Length);
+
+  Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
+    goto out;
+  }
+out:
+  // Restore Tpl
+  gBS->RestoreTPL (Tpl);
+  return Status;
+}
+
+EFI_STATUS
+DwEmmcWriteBlockData (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN EFI_LBA                    Lba,
+  IN UINTN                      Length,
+  IN UINT32*                    Buffer
+  )
+{
+  EFI_STATUS  Status;
+  UINT32      DescPages, CountPerPage, Count;
+  EFI_TPL     Tpl;
+
+  Tpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  CountPerPage = EFI_PAGE_SIZE / 16;
+  Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
+  DescPages = (Count + CountPerPage - 1) / CountPerPage;
+
+  WriteBackDataCacheRange (Buffer, Length);
+
+  Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
+  if (EFI_ERROR (Status)) {
+    goto out;
+  }
+
+  WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
+  StartDma (Length);
+
+  Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
+    goto out;
+  }
+out:
+  // Restore Tpl
+  gBS->RestoreTPL (Tpl);
+  return Status;
+}
+
+EFI_STATUS
+DwEmmcSetIos (
+  IN EFI_MMC_HOST_PROTOCOL      *This,
+  IN  UINT32                    BusClockFreq,
+  IN  UINT32                    BusWidth,
+  IN  UINT32                    TimingMode
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  UINT32    Data;
+
+  if (TimingMode != EMMCBACKWARD) {
+    Data = MmioRead32 (DWEMMC_UHSREG);
+    switch (TimingMode) {
+    case EMMCHS52DDR1V2:
+    case EMMCHS52DDR1V8:
+      Data |= 1 << 16;
+      break;
+    case EMMCHS52:
+    case EMMCHS26:
+      Data &= ~(1 << 16);
+      break;
+    default:
+      return EFI_UNSUPPORTED;
+    }
+    MmioWrite32 (DWEMMC_UHSREG, Data);
+  }
+
+  switch (BusWidth) {
+  case 1:
+    MmioWrite32 (DWEMMC_CTYPE, 0);
+    break;
+  case 4:
+    MmioWrite32 (DWEMMC_CTYPE, 1);
+    break;
+  case 8:
+    MmioWrite32 (DWEMMC_CTYPE, 1 << 16);
+    break;
+  default:
+    return EFI_UNSUPPORTED;
+  }
+  if (BusClockFreq) {
+    Status = DwEmmcSetClock (BusClockFreq);
+  }
+  return Status;
+}
+
+BOOLEAN
+DwEmmcIsMultiBlock (
+  IN EFI_MMC_HOST_PROTOCOL      *This
+  )
+{
+  return TRUE;
+}
+
+EFI_MMC_HOST_PROTOCOL gMciHost = {
+  MMC_HOST_PROTOCOL_REVISION,
+  DwEmmcIsCardPresent,
+  DwEmmcIsReadOnly,
+  DwEmmcBuildDevicePath,
+  DwEmmcNotifyState,
+  DwEmmcSendCommand,
+  DwEmmcReceiveResponse,
+  DwEmmcReadBlockData,
+  DwEmmcWriteBlockData,
+  DwEmmcSetIos,
+  DwEmmcIsMultiBlock
+};
+
+EFI_STATUS
+DwEmmcDxeInitialize (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS    Status;
+  EFI_HANDLE    Handle;
+
+  Handle = NULL;
+
+  gpIdmacDesc = (DWEMMC_IDMAC_DESCRIPTOR *)AllocatePages (DWEMMC_MAX_DESC_PAGES);
+  if (gpIdmacDesc == NULL) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+
+  DEBUG ((DEBUG_BLKIO, "DwEmmcDxeInitialize()\n"));
+
+  //Publish Component Name, BlockIO protocol interfaces
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gEfiMmcHostProtocolGuid,         &gMciHost,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec
index b281b93..c4bf7ed 100644
--- a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec
+++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec
@@ -1,42 +1,42 @@
-#/** @file
-# Framework Module Development Environment Industry Standards
-#
-# This Package provides headers and libraries that conform to EFI/PI Industry standards.
-# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
-# Copyright (c) 2015-2016, Linaro. All rights reserved.<BR>
-#
-#    This program and the accompanying materials are licensed and made available under
-#    the terms and conditions of the BSD License which accompanies this distribution.
-#    The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
-#
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = OpenPlatformDriversMmcDwEmmcDxePkg
-  PACKAGE_GUID                   = 3869905e-c96c-4d20-9bfb-3b9d71bb900c
-  PACKAGE_VERSION                = 0.1
-
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-#                   Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-
-[Guids.common]
-  gDwEmmcDxeTokenSpaceGuid	= { 0x6fdd76a9, 0xf220, 0x4f1d,  { 0x9c, 0xcf, 0xbc, 0x2d, 0x68, 0x29, 0xab, 0x9c }}
-
-[PcdsFixedAtBuild.common]
-  # DwEmmc Driver PCDs
-  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x0|UINT32|0x00000001
-  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000002
+#/** @file
+# Framework Module Development Environment Industry Standards
+#
+# This Package provides headers and libraries that conform to EFI/PI Industry standards.
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2015-2017, Linaro. All rights reserved.<BR>
+#
+#    This program and the accompanying materials are licensed and made available under
+#    the terms and conditions of the BSD License which accompanies this distribution.
+#    The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = MmcDwEmmcDxePkg
+  PACKAGE_GUID                   = 3869905e-c96c-4d20-9bfb-3b9d71bb900c
+  PACKAGE_VERSION                = 0.1
+
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+  gDwEmmcDxeTokenSpaceGuid       = { 0x6fdd76a9, 0xf220, 0x4f1d,  { 0x9c, 0xcf, 0xbc, 0x2d, 0x68, 0x29, 0xab, 0x9c }}
+
+[PcdsFixedAtBuild.common]
+  # DwEmmc Driver PCDs
+  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x0|UINT32|0x00000001
+  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000002
diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf
index f23494c..c0cbba7 100644
--- a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf
+++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf
@@ -1,55 +1,54 @@
-#/** @file
-#  INF file for the eMMC Host Protocol implementation for the DesignWare MMC.
-#
-#  Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
-#  Copyright (c) 2014-2016, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = DwEmmcDxe
-  FILE_GUID                      = b549f005-4bd4-4020-a0cb-06f42bda68c3
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = DwEmmcDxeInitialize
-
-[Sources.common]
-  DwEmmcDxe.c
-
-[Packages]
-  EmbeddedPkg/EmbeddedPkg.dec
-  MdePkg/MdePkg.dec
-  OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec
-
-[LibraryClasses]
-  ArmLib
-  BaseLib
-  BaseMemoryLib
-  CacheMaintenanceLib
-  IoLib
-  MemoryAllocationLib
-  TimerLib
-  UefiDriverEntryPoint
-  UefiLib
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEfiMmcHostProtocolGuid
-
-[Pcd]
-  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress
-  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz
-
-[Depex]
-  TRUE
+#/** @file
+#  INF file for the eMMC Host Protocol implementation for the DesignWare MMC.
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = DwEmmcDxe
+  FILE_GUID                      = b549f005-4bd4-4020-a0cb-06f42bda68c3
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = DwEmmcDxeInitialize
+
+[Sources.common]
+  DwEmmcDxe.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec
+
+[LibraryClasses]
+  ArmLib
+  BaseLib
+  BaseMemoryLib
+  CacheMaintenanceLib
+  IoLib
+  MemoryAllocationLib
+  TimerLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Protocols]
+  gEfiCpuArchProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiMmcHostProtocolGuid
+
+[Pcd]
+  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress
+  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz
+
+[Depex]
+  TRUE
diff --git a/Drivers/Mmc/DwSdDxe/DwSd.h b/Drivers/Mmc/DwSdDxe/DwSd.h
deleted file mode 100644
index 3f86cea..0000000
--- a/Drivers/Mmc/DwSdDxe/DwSd.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2014, Linaro Limited. All rights reserved.
-*  Copyright (c) 2014, Hisilicon Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-
-#ifndef __DWSD_H__
-#define __DWSD_H__
-
-#include <Protocol/EmbeddedGpio.h>
-
-// DW MMC Registers
-#define DWSD_CTRL		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x000)
-#define DWSD_PWREN		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x004)
-#define DWSD_CLKDIV		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x008)
-#define DWSD_CLKSRC		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x00c)
-#define DWSD_CLKENA		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x010)
-#define DWSD_TMOUT		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x014)
-#define DWSD_CTYPE		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x018)
-#define DWSD_BLKSIZ		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x01c)
-#define DWSD_BYTCNT		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x020)
-#define DWSD_INTMASK		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x024)
-#define DWSD_CMDARG		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x028)
-#define DWSD_CMD		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x02c)
-#define DWSD_RESP0		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x030)
-#define DWSD_RESP1		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x034)
-#define DWSD_RESP2		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x038)
-#define DWSD_RESP3		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x03c)
-#define DWSD_RINTSTS		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x044)
-#define DWSD_STATUS		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x048)
-#define DWSD_FIFOTH		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x04c)
-#define DWSD_TCBCNT		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x05c)
-#define DWSD_TBBCNT		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x060)
-#define DWSD_DEBNCE		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x064)
-#define DWSD_UHSREG		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x074)
-#define DWSD_BMOD		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x080)
-#define DWSD_DBADDR		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x088)
-#define DWSD_IDSTS		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x08c)
-#define DWSD_IDINTEN		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x090)
-#define DWSD_DSCADDR		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x094)
-#define DWSD_BUFADDR		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x098)
-#define DWSD_CARDTHRCTL		((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x100)
-#define DWSD_FIFO_START         ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x200)
-
-#define CMD_UPDATE_CLK				0x80202000
-#define CMD_START_BIT				(1 << 31)
-
-#define MMC_8BIT_MODE				(1 << 16)
-
-#define BIT_CMD_RESPONSE_EXPECT			(1 << 6)
-#define BIT_CMD_LONG_RESPONSE			(1 << 7)
-#define BIT_CMD_CHECK_RESPONSE_CRC		(1 << 8)
-#define BIT_CMD_DATA_EXPECTED			(1 << 9)
-#define BIT_CMD_READ				(0 << 10)
-#define BIT_CMD_WRITE				(1 << 10)
-#define BIT_CMD_BLOCK_TRANSFER			(0 << 11)
-#define BIT_CMD_STREAM_TRANSFER			(1 << 11)
-#define BIT_CMD_SEND_AUTO_STOP			(1 << 12)
-#define BIT_CMD_WAIT_PRVDATA_COMPLETE		(1 << 13)
-#define BIT_CMD_STOP_ABORT_CMD			(1 << 14)
-#define BIT_CMD_SEND_INIT			(1 << 15)
-#define BIT_CMD_UPDATE_CLOCK_ONLY		(1 << 21)
-#define BIT_CMD_READ_CEATA_DEVICE		(1 << 22)
-#define BIT_CMD_CCS_EXPECTED			(1 << 23)
-#define BIT_CMD_ENABLE_BOOT			(1 << 24)
-#define BIT_CMD_EXPECT_BOOT_ACK			(1 << 25)
-#define BIT_CMD_DISABLE_BOOT			(1 << 26)
-#define BIT_CMD_MANDATORY_BOOT			(0 << 27)
-#define BIT_CMD_ALTERNATE_BOOT			(1 << 27)
-#define BIT_CMD_VOLT_SWITCH			(1 << 28)
-#define BIT_CMD_USE_HOLD_REG			(1 << 29)
-#define BIT_CMD_START				(1 << 31)
-
-#define DWSD_INT_EBE			(1 << 15)	/* End-bit Err */
-#define DWSD_INT_SBE			(1 << 13)	/* Start-bit  Err */
-#define DWSD_INT_HLE			(1 << 12)	/* Hardware-lock Err */
-#define DWSD_INT_FRUN			(1 << 11)	/* FIFO UN/OV RUN */
-#define DWSD_INT_DRT			(1 << 9)	/* Data timeout */
-#define DWSD_INT_RTO			(1 << 8)	/* Response timeout */
-#define DWSD_INT_DCRC			(1 << 7)	/* Data CRC err */
-#define DWSD_INT_RCRC			(1 << 6)	/* Response CRC err */
-#define DWSD_INT_RXDR			(1 << 5)
-#define DWSD_INT_TXDR			(1 << 4)
-#define DWSD_INT_DTO			(1 << 3)	/* Data trans over */
-#define DWSD_INT_CMD_DONE		(1 << 2)
-#define DWSD_INT_RE			(1 << 1)
-
-#define DWSD_IDMAC_DES0_DIC		(1 << 1)
-#define DWSD_IDMAC_DES0_LD		(1 << 2)
-#define DWSD_IDMAC_DES0_FS		(1 << 3)
-#define DWSD_IDMAC_DES0_CH		(1 << 4)
-#define DWSD_IDMAC_DES0_ER		(1 << 5)
-#define DWSD_IDMAC_DES0_CES		(1 << 30)
-#define DWSD_IDMAC_DES0_OWN		(1 << 31)
-#define DWSD_IDMAC_DES1_BS1(x)		((x) & 0x1fff)
-#define DWSD_IDMAC_DES2_BS2(x)		(((x) & 0x1fff) << 13)
-#define DWSD_IDMAC_SWRESET		(1 << 0)
-#define DWSD_IDMAC_FB			(1 << 1)
-#define DWSD_IDMAC_ENABLE		(1 << 7)
-
-#define EMMC_FIX_RCA				6
-
-/* bits in MMC0_CTRL */
-#define DWSD_CTRL_RESET		(1 << 0)
-#define DWSD_CTRL_FIFO_RESET		(1 << 1)
-#define DWSD_CTRL_DMA_RESET		(1 << 2)
-#define DWSD_CTRL_INT_EN		(1 << 4)
-#define DWSD_CTRL_DMA_EN		(1 << 5)
-#define DWSD_CTRL_IDMAC_EN		(1 << 25)
-#define DWSD_CTRL_RESET_ALL		(DWSD_CTRL_RESET | DWSD_CTRL_FIFO_RESET | DWSD_CTRL_DMA_RESET)
-
-#define DWSD_STS_DATA_BUSY		(1 << 9)
-
-#define DWSD_FIFO_TWMARK(x)		(x & 0xfff)
-#define DWSD_FIFO_RWMARK(x)		((x & 0x1ff) << 16)
-#define DWSD_DMA_BURST_SIZE(x)		((x & 0x7) << 28)
-
-#define DWSD_CARD_RD_THR(x)		((x & 0xfff) << 16)
-#define DWSD_CARD_RD_THR_EN		(1 << 0)
-
-#endif  // __DWSD_H__
diff --git a/Drivers/Mmc/DwSdDxe/DwSdDxe.c b/Drivers/Mmc/DwSdDxe/DwSdDxe.c
deleted file mode 100644
index cbe6b77..0000000
--- a/Drivers/Mmc/DwSdDxe/DwSdDxe.c
+++ /dev/null
@@ -1,756 +0,0 @@
-/** @file
-  This file implement the MMC Host Protocol for the DesignWare SD.
-
-  Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
-  Copyright (c) 2014-2016, Hisilicon Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Library/TimerLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Protocol/MmcHost.h>
-
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
-
-#include "DwSd.h"
-
-#define DWSD_DESC_PAGE		1
-#define DWSD_BLOCK_SIZE	        512
-#define DWSD_DMA_BUF_SIZE	(512 * 8)
-
-#define DWSD_DMA_THRESHOLD	16
-
-#define MAX_IDLE_LOOPS		1000000
-
-typedef struct {
-  UINT32		Des0;
-  UINT32		Des1;
-  UINT32		Des2;
-  UINT32		Des3;
-} DWSD_IDMAC_DESCRIPTOR;
-
-EFI_MMC_HOST_PROTOCOL     *gpMmcHost;
-DWSD_IDMAC_DESCRIPTOR     *gpIdmacDesc;
-EFI_GUID mDwSdDevicePathGuid = EFI_CALLER_ID_GUID;
-STATIC UINT32 mDwSdCommand;
-STATIC UINT32 mDwSdArgument;
-
-EFI_STATUS
-DwSdSendCommand (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_CMD                    MmcCmd,
-  IN UINT32                     Argument
-  );
-EFI_STATUS
-DwSdReceiveResponse (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_RESPONSE_TYPE          Type,
-  IN UINT32*                    Buffer
-  );
-
-EFI_STATUS
-DwSdReadBlockData (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN EFI_LBA                    Lba,
-  IN UINTN                      Length,
-  IN UINT32*                    Buffer
-  );
-
-BOOLEAN
-DwSdIsPowerOn (
-  VOID
-  )
-{
-    return TRUE;
-}
-
-EFI_STATUS
-DwSdInitialize (
-  VOID
-  )
-{
-    DEBUG ((EFI_D_BLKIO, "DwSdInitialize()"));
-    return EFI_SUCCESS;
-}
-
-BOOLEAN
-DwSdIsCardPresent (
-  IN EFI_MMC_HOST_PROTOCOL     *This
-  )
-{
-  UINT32    Value;
-
-  /*
-   * FIXME
-   * At first, reading GPIO pin shouldn't exist in SD driver. We need to
-   * add some callbacks to handle settings for hardware platform.
-   * In the second, reading GPIO pin should be based on GPIO driver. Now
-   * GPIO driver could only be used for one PL061 gpio controller. And it's
-   * used to detect jumper setting. As a workaround, we have to read the gpio
-   * register instead at here.
-   *
-   */
-  Value = MmioRead32 (0xf8012000 + (1 << 2));
-  if (Value)
-    return FALSE;
-  return TRUE;
-}
-
-BOOLEAN
-DwSdIsReadOnly (
-  IN EFI_MMC_HOST_PROTOCOL     *This
-  )
-{
-  /* FIXME */
-  return FALSE;
-}
-
-EFI_STATUS
-DwSdBuildDevicePath (
-  IN EFI_MMC_HOST_PROTOCOL      *This,
-  IN EFI_DEVICE_PATH_PROTOCOL   **DevicePath
-  )
-{
-  EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
-
-  NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
-  CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwSdDevicePathGuid);
-
-  *DevicePath = NewDevicePathNode;
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DwSdUpdateClock (
-  VOID
-  )
-{
-  UINT32 Data;
-
-  /* CMD_UPDATE_CLK */
-  Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
-	 BIT_CMD_START;
-  MmioWrite32 (DWSD_CMD, Data);
-  while (1) {
-    Data = MmioRead32 (DWSD_CMD);
-    if (!(Data & CMD_START_BIT))
-      break;
-    Data = MmioRead32 (DWSD_RINTSTS);
-    if (Data & DWSD_INT_HLE)
-    {
-      Print (L"failed to update mmc clock frequency\n");
-      return EFI_DEVICE_ERROR;
-    }
-  }
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DwSdSetClock (
-  IN UINTN                     ClockFreq
-  )
-{
-  UINT32 Divider, Rate, Data, Count;
-  EFI_STATUS Status;
-  BOOLEAN Found = FALSE;
-
-  for (Divider = 1; Divider < 256; Divider++) {
-    Rate = PcdGet32 (PcdDwSdDxeClockFrequencyInHz);
-    if ((Rate / (2 * Divider)) <= ClockFreq) {
-      Found = TRUE;
-      break;
-    }
-  }
-  if (Found == FALSE)
-    return EFI_NOT_FOUND;
-
-  // Wait until MMC is idle
-  Count = 0;
-  do {
-    Data = MmioRead32 (DWSD_STATUS);
-    if (Count++ > MAX_IDLE_LOOPS)
-      break;
-  } while (Data & DWSD_STS_DATA_BUSY);
-
-  // Disable MMC clock first
-  MmioWrite32 (DWSD_CLKENA, 0);
-  Status = DwSdUpdateClock ();
-  ASSERT (!EFI_ERROR (Status));
-
-  MmioWrite32 (DWSD_CLKDIV, Divider);
-  Status = DwSdUpdateClock ();
-  ASSERT (!EFI_ERROR (Status));
-
-  // Enable MMC clock
-  MmioWrite32 (DWSD_CLKENA, 1);
-  MmioWrite32 (DWSD_CLKSRC, 0);
-  Status = DwSdUpdateClock ();
-  ASSERT (!EFI_ERROR (Status));
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DwSdNotifyState (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_STATE                 State
-  )
-{
-  UINT32      Data;
-  EFI_STATUS  Status;
-
-  switch (State) {
-  case MmcInvalidState:
-    ASSERT (0);
-    break;
-  case MmcHwInitializationState:
-    MmioWrite32 (DWSD_PWREN, 1);
-
-    // If device already turn on then restart it
-    Data = DWSD_CTRL_RESET_ALL;
-    MmioWrite32 (DWSD_CTRL, Data);
-    do {
-      // Wait until reset operation finished
-      Data = MmioRead32 (DWSD_CTRL);
-    } while (Data & DWSD_CTRL_RESET_ALL);
-
-    MmioWrite32 (DWSD_RINTSTS, ~0);
-    MmioWrite32 (DWSD_INTMASK, 0);
-    MmioWrite32 (DWSD_TMOUT, ~0);
-    MmioWrite32 (DWSD_IDINTEN, 0);
-    MmioWrite32 (DWSD_BMOD, DWSD_IDMAC_SWRESET);
-
-    MmioWrite32 (DWSD_BLKSIZ, DWSD_BLOCK_SIZE);
-    do {
-      Data = MmioRead32 (DWSD_BMOD);
-    } while (Data & DWSD_IDMAC_SWRESET);
-
-
-    Data = DWSD_DMA_BURST_SIZE(2) | DWSD_FIFO_TWMARK(8) | DWSD_FIFO_RWMARK(7) | (2 << 28);
-    MmioWrite32 (DWSD_FIFOTH, Data);
-    Data = DWSD_CARD_RD_THR(512) | DWSD_CARD_RD_THR_EN;
-    MmioWrite32 (DWSD_CARDTHRCTL, Data);
-
-    // Set Data Length & Data Timer
-    MmioWrite32 (DWSD_CTYPE, 0);
-    MmioWrite32 (DWSD_DEBNCE, 0x00ffffff);
-
-    // Setup clock that could not be higher than 400KHz.
-    Status = DwSdSetClock (400000);
-    ASSERT (!EFI_ERROR (Status));
-    MicroSecondDelay (100);
-
-    break;
-  case MmcIdleState:
-    break;
-  case MmcReadyState:
-    break;
-  case MmcIdentificationState:
-    break;
-  case MmcStandByState:
-    break;
-  case MmcTransferState:
-    break;
-  case MmcSendingDataState:
-    break;
-  case MmcReceiveDataState:
-    break;
-  case MmcProgrammingState:
-    break;
-  case MmcDisconnectState:
-    break;
-  default:
-    ASSERT (0);
-  }
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-SendCommand (
-  IN MMC_CMD                    MmcCmd,
-  IN UINT32                     Argument
-  )
-{
-  UINT32      Data, ErrMask, Count;
-
-  MmioWrite32 (DWSD_RINTSTS, ~0);
-  MmioWrite32 (DWSD_CMDARG, Argument);
-  MicroSecondDelay(500);
-  // Wait until MMC is idle
-  Count = 0;
-  do {
-    Data = MmioRead32 (DWSD_STATUS);
-    if (Count++ > MAX_IDLE_LOOPS)
-      break;
-  } while (Data & DWSD_STS_DATA_BUSY);
-
-  MmioWrite32 (DWSD_CMD, MmcCmd);
-
-  ErrMask = DWSD_INT_EBE | DWSD_INT_HLE | DWSD_INT_RTO |
-            DWSD_INT_RCRC | DWSD_INT_RE;
-  ErrMask |= DWSD_INT_DCRC | DWSD_INT_DRT | DWSD_INT_SBE;
-  do {
-    MicroSecondDelay(500);
-    Data = MmioRead32 (DWSD_RINTSTS);
-
-    if (Data & ErrMask) {
-      DEBUG ((EFI_D_ERROR, "Data:%x, ErrMask:%x, TBBCNT:%x, TCBCNT:%x, BYTCNT:%x, BLKSIZ:%x\n", Data, ErrMask, MmioRead32 (DWSD_TBBCNT), MmioRead32 (DWSD_TCBCNT), MmioRead32 (DWSD_BYTCNT), MmioRead32 (DWSD_BLKSIZ)));
-      return EFI_DEVICE_ERROR;
-    }
-    if (Data & DWSD_INT_DTO)	// Transfer Done
-      break;
-  } while (!(Data & DWSD_INT_CMD_DONE));
-  MmcCmd &= 0x3f;
-  if (MmcCmd == 17)
-    MicroSecondDelay(100);
-  else if (MmcCmd != 13)
-    MicroSecondDelay(5000);
-
-  return EFI_SUCCESS;
-}
-
-UINTN ACmd = 0;
-
-EFI_STATUS
-DwSdSendCommand (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_CMD                    MmcCmd,
-  IN UINT32                     Argument
-  )
-{
-  UINT32       Cmd = 0;
-  EFI_STATUS   Status = EFI_SUCCESS;
-  BOOLEAN      Pending = FALSE;
-  UINT32       Data;
-
-  switch (MMC_GET_INDX(MmcCmd)) {
-  case MMC_INDX(0):
-    //Cmd = BIT_CMD_SEND_INIT;
-    Cmd = BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(1):
-    Cmd = BIT_CMD_RESPONSE_EXPECT;
-    break;
-  case MMC_INDX(2):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
-           BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(3):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(6):
-    if (!ACmd) {
-      Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-	    BIT_CMD_DATA_EXPECTED | BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    } else {
-      Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-	    BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    }
-    if (!ACmd)
-      Pending = TRUE;
-    break;
-  case MMC_INDX(7):
-    if (Argument)
-        Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-	       BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    else
-        Cmd = 0;
-    break;
-  case MMC_INDX(8):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_READ |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(9):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_LONG_RESPONSE | BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(12):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_STOP_ABORT_CMD;
-    break;
-  case MMC_INDX(13):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
-    break;
-  case MMC_INDX(17):
-  case MMC_INDX(18):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    Pending = TRUE;
-    Data = MmioRead32 (DWSD_CTRL);
-    Data |= DWSD_CTRL_FIFO_RESET;
-    MmioWrite32 (DWSD_CTRL, Data);
-    while (MmioRead32 (DWSD_CTRL) & DWSD_CTRL_FIFO_RESET) {
-    };
-    break;
-  case MMC_INDX(24):
-  case MMC_INDX(25):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    Pending = TRUE;
-    break;
-  case MMC_INDX(30):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED;
-    break;
-  case MMC_INDX(41):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    break;
-  case MMC_INDX(51):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
-           BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
-           BIT_CMD_WAIT_PRVDATA_COMPLETE;
-    Pending = TRUE;
-    break;
-  case MMC_INDX(55):
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
-    ACmd = 1;
-    break;
-  default:
-    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
-    break;
-  }
-
-  Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
-  if (Pending) {
-    mDwSdCommand = Cmd;
-    mDwSdArgument = Argument;
-  } else {
-    mDwSdCommand = 0;
-    mDwSdArgument = 0;
-    Status = SendCommand (Cmd, Argument);
-  }
-  /* Clear ACMD */
-  if (MMC_GET_INDX(MmcCmd) != MMC_INDX(55))
-    ACmd = 0;
-  return Status;
-}
-
-EFI_STATUS
-DwSdReceiveResponse (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN MMC_RESPONSE_TYPE          Type,
-  IN UINT32*                    Buffer
-  )
-{
-  if (Buffer == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  if (   (Type == MMC_RESPONSE_TYPE_R1)
-      || (Type == MMC_RESPONSE_TYPE_R1b)
-      || (Type == MMC_RESPONSE_TYPE_R3)
-      || (Type == MMC_RESPONSE_TYPE_R6)
-      || (Type == MMC_RESPONSE_TYPE_R7))
-  {
-    Buffer[0] = MmioRead32 (DWSD_RESP0);
-  } else if (Type == MMC_RESPONSE_TYPE_R2) {
-    Buffer[0] = MmioRead32 (DWSD_RESP0);
-    Buffer[1] = MmioRead32 (DWSD_RESP1);
-    Buffer[2] = MmioRead32 (DWSD_RESP2);
-    Buffer[3] = MmioRead32 (DWSD_RESP3);
-  }
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-PrepareDmaData (
-  IN DWSD_IDMAC_DESCRIPTOR*    IdmacDesc,
-  IN UINTN                      Length,
-  IN UINT32*                    Buffer
-  )
-{
-  UINTN  Cnt, Idx, LastIdx, Blks;
-
-  if (Length % 4) {
-    DEBUG ((EFI_D_ERROR, "Length isn't aligned with 4\n"));
-    return EFI_BAD_BUFFER_SIZE;
-  }
-  if (Length < DWSD_DMA_THRESHOLD) {
-    return EFI_BUFFER_TOO_SMALL;
-  }
-  Cnt = (Length + DWSD_DMA_BUF_SIZE - 1) / DWSD_DMA_BUF_SIZE;
-  Blks = (Length + DWSD_BLOCK_SIZE - 1 ) / DWSD_BLOCK_SIZE;
-  Length = DWSD_BLOCK_SIZE * Blks;
-
-  for (Idx = 0; Idx < Cnt; Idx++) {
-    (IdmacDesc + Idx)->Des0 = DWSD_IDMAC_DES0_OWN | DWSD_IDMAC_DES0_CH |
-	    		      DWSD_IDMAC_DES0_DIC;
-    (IdmacDesc + Idx)->Des1 = DWSD_IDMAC_DES1_BS1(DWSD_DMA_BUF_SIZE);
-    /* Buffer Address */
-    (IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWSD_DMA_BUF_SIZE * Idx);
-    /* Next Descriptor Address */
-    (IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +
-   	                               (sizeof(DWSD_IDMAC_DESCRIPTOR) * (Idx + 1)));
-  }
-  /* First Descriptor */
-  IdmacDesc->Des0 |= DWSD_IDMAC_DES0_FS;
-  /* Last Descriptor */
-  LastIdx = Cnt - 1;
-  (IdmacDesc + LastIdx)->Des0 |= DWSD_IDMAC_DES0_LD;
-  (IdmacDesc + LastIdx)->Des0 &= ~(DWSD_IDMAC_DES0_DIC | DWSD_IDMAC_DES0_CH);
-  (IdmacDesc + LastIdx)->Des1 = DWSD_IDMAC_DES1_BS1(Length -
-   		                (LastIdx * DWSD_DMA_BUF_SIZE));
-  /* Set the Next field of Last Descriptor */
-  (IdmacDesc + LastIdx)->Des3 = 0;
-  MmioWrite32 (DWSD_DBADDR, (UINT32)((UINTN)IdmacDesc));
-
-  return EFI_SUCCESS;
-}
-
-VOID
-StartDma (
-  UINTN    Length
-  )
-{
-  UINT32 Data;
-
-  Data = MmioRead32 (DWSD_CTRL);
-  Data |= DWSD_CTRL_INT_EN | DWSD_CTRL_DMA_EN | DWSD_CTRL_IDMAC_EN;
-  MmioWrite32 (DWSD_CTRL, Data);
-  Data = MmioRead32 (DWSD_BMOD);
-  Data |= DWSD_IDMAC_ENABLE | DWSD_IDMAC_FB;
-  MmioWrite32 (DWSD_BMOD, Data);
-
-  MmioWrite32 (DWSD_BLKSIZ, DWSD_BLOCK_SIZE);
-  MmioWrite32 (DWSD_BYTCNT, Length);
-}
-
-STATIC
-EFI_STATUS
-ReadFifo (
-  IN UINTN                      Length,
-  IN UINT32*                    Buffer
-  )
-{
-  UINT32      Data, Received, Count;
-
-  Received = 0;
-  Count = (Length + 3) / 4;
-  while (Received < Count) {
-    Data = MmioRead32 (DWSD_RINTSTS);
-    if (Data & DWSD_INT_CMD_DONE) {
-      *(Buffer + Received) = MmioRead32 (DWSD_FIFO_START);
-      Received++;
-    } else {
-      DEBUG ((EFI_D_ERROR, "Received:%d, RINTSTS:%x\n", Received, Data));
-    }
-  }
-  while (1) {
-    Data = MmioRead32 (DWSD_RINTSTS);
-    if (Data & DWSD_INT_DTO)
-      break;
-  }
-  /* FIXME */
-  MicroSecondDelay (1000);
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-DwSdReadBlockData (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN EFI_LBA                    Lba,
-  IN UINTN                      Length,
-  IN UINT32*                   Buffer
-  )
-{
-  EFI_STATUS  Status;
-  UINT32      DescPages, CountPerPage, Count, Data;
-  EFI_TPL     Tpl;
-
-  Tpl = gBS->RaiseTPL (TPL_NOTIFY);
-
-  CountPerPage = EFI_PAGE_SIZE / 16;
-  Count = (Length + DWSD_DMA_BUF_SIZE - 1) / DWSD_DMA_BUF_SIZE;
-  DescPages = (Count + CountPerPage - 1) / CountPerPage;
-
-  InvalidateDataCacheRange (Buffer, Length);
-
-  Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
-  if (EFI_ERROR (Status)) {
-    if (Status == EFI_BUFFER_TOO_SMALL) {
-      Data = MmioRead32 (DWSD_CTRL);
-      Data |= DWSD_CTRL_FIFO_RESET;
-      MmioWrite32 (DWSD_CTRL, Data);
-      while (MmioRead32 (DWSD_CTRL) & DWSD_CTRL_FIFO_RESET) {
-      };
-
-      Status = SendCommand (mDwSdCommand, mDwSdArgument);
-      if (EFI_ERROR (Status)) {
-	DEBUG ((EFI_D_ERROR, "Failed to read data from FIFO, mDwSdCommand:%x, mDwSdArgument:%x, Status:%r\n", mDwSdCommand, mDwSdArgument, Status));
-	goto out;
-      }
-      Status = ReadFifo (Length, Buffer);
-    }
-    goto out;
-  } else {
-
-    WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
-    StartDma (Length);
-
-    Status = SendCommand (mDwSdCommand, mDwSdArgument);
-    if (EFI_ERROR (Status)) {
-      DEBUG ((EFI_D_ERROR, "Failed to read data, mDwSdCommand:%x, mDwSdArgument:%x, Status:%r\n", mDwSdCommand, mDwSdArgument, Status));
-      goto out;
-    }
-
-    /* Wait until data transfer finished */
-    while (MmioRead32 (DWSD_TCBCNT) < MmioRead32 (DWSD_BYTCNT)) {
-    }
-
-  }
-out:
-  // Restore Tpl
-  gBS->RestoreTPL (Tpl);
-  return Status;
-}
-
-EFI_STATUS
-DwSdWriteBlockData (
-  IN EFI_MMC_HOST_PROTOCOL     *This,
-  IN EFI_LBA                    Lba,
-  IN UINTN                      Length,
-  IN UINT32*                    Buffer
-  )
-{
-  EFI_STATUS  Status;
-  UINT32      DescPages, CountPerPage, Count;
-  EFI_TPL     Tpl;
-
-  Tpl = gBS->RaiseTPL (TPL_NOTIFY);
-
-  CountPerPage = EFI_PAGE_SIZE / 16;
-  Count = (Length + DWSD_DMA_BUF_SIZE - 1) / DWSD_DMA_BUF_SIZE;
-  DescPages = (Count + CountPerPage - 1) / CountPerPage;
-
-  WriteBackDataCacheRange (Buffer, Length);
-
-  Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
-  if (EFI_ERROR (Status))
-    goto out;
-
-  WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
-  StartDma (Length);
-
-  Status = SendCommand (mDwSdCommand, mDwSdArgument);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Failed to write data, mDwSdCommand:%x, mDwSdArgument:%x, Status:%r\n", mDwSdCommand, mDwSdArgument, Status));
-    goto out;
-  }
-out:
-  // Restore Tpl
-  gBS->RestoreTPL (Tpl);
-  return Status;
-}
-
-EFI_STATUS
-DwSdSetIos (
-  IN EFI_MMC_HOST_PROTOCOL      *This,
-  IN  UINT32                    BusClockFreq,
-  IN  UINT32                    BusWidth,
-  IN  UINT32                    TimingMode
-  )
-{
-  EFI_STATUS Status = EFI_SUCCESS;
-  UINT32    Data;
-
-  if (TimingMode != EMMCBACKWARD) {
-    Data = MmioRead32 (DWSD_UHSREG);
-    switch (TimingMode) {
-    case EMMCHS52DDR1V2:
-    case EMMCHS52DDR1V8:
-      Data |= 1 << 16;
-      break;
-    case EMMCHS52:
-    case EMMCHS26:
-      Data &= ~(1 << 16);
-      break;
-    default:
-      return EFI_UNSUPPORTED;
-    }
-    MmioWrite32 (DWSD_UHSREG, Data);
-  }
-
-  switch (BusWidth) {
-  case 1:
-    MmioWrite32 (DWSD_CTYPE, 0);
-    break;
-  case 4:
-    MmioWrite32 (DWSD_CTYPE, 1);
-    break;
-  case 8:
-    MmioWrite32 (DWSD_CTYPE, 1 << 16);
-    break;
-  default:
-    return EFI_UNSUPPORTED;
-  }
-  if (BusClockFreq) {
-    Status = DwSdSetClock (BusClockFreq);
-  }
-  return Status;
-}
-
-BOOLEAN
-DwSdIsMultiBlock (
-  IN EFI_MMC_HOST_PROTOCOL      *This
-  )
-{
-  return TRUE;
-}
-
-EFI_MMC_HOST_PROTOCOL gMciHost = {
-  MMC_HOST_PROTOCOL_REVISION,
-  DwSdIsCardPresent,
-  DwSdIsReadOnly,
-  DwSdBuildDevicePath,
-  DwSdNotifyState,
-  DwSdSendCommand,
-  DwSdReceiveResponse,
-  DwSdReadBlockData,
-  DwSdWriteBlockData,
-  DwSdSetIos,
-  DwSdIsMultiBlock
-};
-
-EFI_STATUS
-DwSdDxeInitialize (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS    Status;
-  EFI_HANDLE    Handle;
-
-  Handle = NULL;
-
-  DEBUG ((EFI_D_BLKIO, "DwSdDxeInitialize()\n"));
-
-  //Publish Component Name, BlockIO protocol interfaces
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &Handle,
-                  &gEfiMmcHostProtocolGuid,         &gMciHost,
-                  NULL
-                  );
-  ASSERT_EFI_ERROR (Status);
-
-  return EFI_SUCCESS;
-}
diff --git a/Drivers/Mmc/DwSdDxe/DwSdDxe.inf b/Drivers/Mmc/DwSdDxe/DwSdDxe.inf
deleted file mode 100644
index ad042a7..0000000
--- a/Drivers/Mmc/DwSdDxe/DwSdDxe.inf
+++ /dev/null
@@ -1,55 +0,0 @@
-#/** @file
-#  INF file for the MMC Host Protocol implementation for the DesignWare MMC.
-#
-#  Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
-#  Copyright (c) 2014-2016, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = DwSdDxe
-  FILE_GUID                      = 594bfe73-5e18-4f12-8119-19db8c5fc849
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = DwSdDxeInitialize
-
-[Sources.common]
-  DwSdDxe.c
-
-[Packages]
-  EmbeddedPkg/EmbeddedPkg.dec
-  MdePkg/MdePkg.dec
-  OpenPlatformPkg/Drivers/Mmc/DwSdDxe/DwSdDxe.dec
-
-[LibraryClasses]
-  ArmLib
-  BaseLib
-  BaseMemoryLib
-  CacheMaintenanceLib
-  IoLib
-  MemoryAllocationLib
-  TimerLib
-  UefiDriverEntryPoint
-  UefiLib
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEfiMmcHostProtocolGuid
-
-[Pcd]
-  gDwSdDxeTokenSpaceGuid.PcdDwSdDxeBaseAddress
-  gDwSdDxeTokenSpaceGuid.PcdDwSdDxeClockFrequencyInHz
-
-[Depex]
-  TRUE
diff --git a/Drivers/Net/Lan91xDxe/Lan91xDxe.c b/Drivers/Net/Lan91xDxe/Lan91xDxe.c
index 3f857a5..8895f58 100644
--- a/Drivers/Net/Lan91xDxe/Lan91xDxe.c
+++ b/Drivers/Net/Lan91xDxe/Lan91xDxe.c
@@ -1,2233 +1,2235 @@
-/** @file
-*  SMSC LAN91x series Network Controller Driver.
-*
-*  Copyright (c) 2013 Linaro.org
-*
-*  Derived from the LAN9118 driver. Original sources
-*  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials are licensed and
-*  made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license
-*  may be found at: http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Uefi/UefiSpec.h>
-#include <Base.h>
-
-// Protocols used by this driver
-#include <Protocol/SimpleNetwork.h>
-#include <Protocol/ComponentName2.h>
-#include <Protocol/PxeBaseCode.h>
-#include <Protocol/DevicePath.h>
-
-// Libraries used by this driver
-#include <Library/UefiLib.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/NetLib.h>
-#include <Library/DevicePathLib.h>
-
-// Hardware register definitions
-#include "Lan91xDxeHw.h"
-
-// Debugging output options
-//#define LAN91X_PRINT_REGISTERS 1
-//#define LAN91X_PRINT_PACKET_HEADERS 1
-//#define LAN91X_PRINT_RECEIVE_FILTERS 1
-
-// Chip power-down option -- UNTESTED
-//#define LAN91X_POWER_DOWN 1
-
-/*---------------------------------------------------------------------------------------------------------------------
-
-  LAN91x Information Structure
-
----------------------------------------------------------------------------------------------------------------------*/
-typedef struct _LAN91X_DRIVER {
-  // Driver signature
-  UINT32            Signature;
-  EFI_HANDLE        ControllerHandle;
-
-  // EFI SNP protocol instances
-  EFI_SIMPLE_NETWORK_PROTOCOL Snp;
-  EFI_SIMPLE_NETWORK_MODE SnpMode;
-
-  // EFI Snp statistics instance
-  EFI_NETWORK_STATISTICS Stats;
-
-  // Transmit Buffer recycle queue
-#define TX_QUEUE_DEPTH 16
-  VOID              *TxQueue[TX_QUEUE_DEPTH];
-  UINTN             TxQueHead;
-  UINTN             TxQueTail;
-
-  // Register access variables
-  UINTN             IoBase;             // I/O Base Address
-  UINT8             Revision;           // Chip Revision Number
-  INT8              PhyAd;              // Phy Address
-  UINT8             BankSel;            // Currently selected register bank
-
-} LAN91X_DRIVER;
-
-#define LAN91X_NO_PHY (-1)              // PhyAd value if PHY not detected
-
-#define LAN91X_SIGNATURE                        SIGNATURE_32('S', 'M', '9', '1')
-#define INSTANCE_FROM_SNP_THIS(a)               CR(a, LAN91X_DRIVER, Snp, LAN91X_SIGNATURE)
-
-#define LAN91X_STALL              2
-#define LAN91X_MEMORY_ALLOC_POLLS 100   // Max times to poll for memory allocation
-#define LAN91X_PKT_OVERHEAD       6     // Overhead bytes in packet buffer
-
-// Synchronization TPLs
-#define LAN91X_TPL  TPL_CALLBACK
-
-// Most common CRC32 Polynomial for little endian machines
-#define CRC_POLYNOMIAL               0xEDB88320
-
-
-typedef struct {
-  MAC_ADDR_DEVICE_PATH      Lan91x;
-  EFI_DEVICE_PATH_PROTOCOL  End;
-} LAN91X_DEVICE_PATH;
-
-LAN91X_DEVICE_PATH Lan91xPathTemplate =  {
-  {
-    {
-      MESSAGING_DEVICE_PATH, MSG_MAC_ADDR_DP,
-      { (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)), (UINT8) ((sizeof(MAC_ADDR_DEVICE_PATH)) >> 8) }
-    },
-    { { 0 } },
-    0
-  },
-  {
-    END_DEVICE_PATH_TYPE,
-    END_ENTIRE_DEVICE_PATH_SUBTYPE,
-    { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0 }
-  }
-};
-
-// Chip ID numbers and name strings
-#define CHIP_9192       3
-#define CHIP_9194       4
-#define CHIP_9195       5
-#define CHIP_9196       6
-#define CHIP_91100      7
-#define CHIP_91100FD    8
-#define CHIP_91111FD    9
-
-STATIC CHAR16 CONST * CONST ChipIds[ 16 ] =  {
-  NULL, NULL, NULL,
-  /* 3 */ L"SMC91C90/91C92",
-  /* 4 */ L"SMC91C94",
-  /* 5 */ L"SMC91C95",
-  /* 6 */ L"SMC91C96",
-  /* 7 */ L"SMC91C100",
-  /* 8 */ L"SMC91C100FD",
-  /* 9 */ L"SMC91C11xFD",
-  NULL, NULL, NULL,
-  NULL, NULL, NULL
-};
-
-
-/* ------------------ TxBuffer Queue functions ------------------- */
-
-#define TxQueNext(off)  ((((off) + 1) >= TX_QUEUE_DEPTH) ? 0 : ((off) + 1))
-
-STATIC
-BOOLEAN
-TxQueInsert (
-    IN    LAN91X_DRIVER *LanDriver,
-    IN    VOID          *Buffer
-    )
-{
-
-  if (TxQueNext (LanDriver->TxQueTail) == LanDriver->TxQueHead) {
-    return FALSE;
-  }
-
-  LanDriver->TxQueue[LanDriver->TxQueTail] = Buffer;
-  LanDriver->TxQueTail = TxQueNext (LanDriver->TxQueTail);
-
-  return TRUE;
-}
-
-STATIC
-VOID
-*TxQueRemove (
-    IN    LAN91X_DRIVER *LanDriver
-    )
-{
-  VOID *Buffer;
-
-  if (LanDriver->TxQueTail == LanDriver->TxQueHead) {
-    return NULL;
-  }
-
-  Buffer = LanDriver->TxQueue[LanDriver->TxQueHead];
-  LanDriver->TxQueue[LanDriver->TxQueHead] = NULL;
-  LanDriver->TxQueHead = TxQueNext (LanDriver->TxQueHead);
-
-  return Buffer;
-}
-
-/* ------------------ MAC Address Hash Calculations ------------------- */
-
-/*
-**  Generate a hash value from a multicast address
-**
-**  This uses the Ethernet standard CRC32 algorithm
-**
-**  INFO USED:
-**    1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check
-**
-**    2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html
-**
-**    3: http://en.wikipedia.org/wiki/Computation_of_CRC
-*/
-STATIC
-UINT32
-MulticastHash (
-  IN    EFI_MAC_ADDRESS *Mac,
-  IN    UINT32 AddrLen
-  )
-{
-  UINT32 Iter;
-  UINT32 Remainder;
-  UINT32 Crc32;
-  UINT8 *Addr;
-
-  // 0xFFFFFFFF is standard seed for Ethernet
-  Remainder = 0xFFFFFFFF;
-
-  // Generate the remainder byte-by-byte (LSB first)
-  Addr = &Mac->Addr[0];
-  while (AddrLen-- > 0) {
-    Remainder ^= *Addr++;
-    for (Iter = 0; Iter < 8; ++Iter) {
-      // Check if exponent is set
-      if ((Remainder & 1) != 0) {
-        Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;
-      } else {
-        Remainder = (Remainder >> 1) ^ 0;
-      }
-    }
-  }
-
-  // Reverse the bits of the remainder
-  Crc32 = 0;
-  for (Iter = 0; Iter < 32; ++Iter) {
-    Crc32 <<= 1;
-    Crc32 |= Remainder & 1;
-    Remainder >>= 1;
-  }
-  return Crc32;
-}
-
-
-/* ---------------- Banked Register Operations ------------------ */
-
-// Select the proper I/O bank
-STATIC
-VOID
-SelectIoBank (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            Register
-  )
-{
-  UINT8   Bank;
-
-  Bank = RegisterToBank (Register);
-
-  // Select the proper I/O bank
-  if (LanDriver->BankSel != Bank) {
-    MmioWrite16 (LanDriver->IoBase + LAN91X_BANK_OFFSET, Bank);
-    LanDriver->BankSel = Bank;
-  }
-}
-
-// Read a 16-bit I/O-space register
-STATIC
-UINT16
-ReadIoReg16 (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            Register
-  )
-{
-  UINT8   Offset;
-
-  // Select the proper I/O bank
-  SelectIoBank (LanDriver, Register);
-
-  // Read the requested register
-  Offset = RegisterToOffset (Register);
-  return MmioRead16 (LanDriver->IoBase + Offset);
-}
-
-// Write a 16-bit I/O-space register
-STATIC
-UINT16
-WriteIoReg16 (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            Register,
-  UINT16           Value
-  )
-{
-  UINT8   Offset;
-
-  // Select the proper I/O bank
-  SelectIoBank (LanDriver, Register);
-
-  // Write the requested register
-  Offset = RegisterToOffset (Register);
-  return MmioWrite16 (LanDriver->IoBase + Offset, Value);
-}
-
-// Read an 8-bit I/O-space register
-STATIC
-UINT8
-ReadIoReg8 (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            Register
-  )
-{
-  UINT8   Offset;
-
-  // Select the proper I/O bank
-  SelectIoBank (LanDriver, Register);
-
-  // Read the requested register
-  Offset = RegisterToOffset (Register);
-  return MmioRead8 (LanDriver->IoBase + Offset);
-}
-
-// Write an 8-bit I/O-space register
-STATIC
-UINT8
-WriteIoReg8 (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            Register,
-  UINT8            Value
-  )
-{
-  UINT8   Offset;
-
-  // Select the proper I/O bank
-  SelectIoBank (LanDriver, Register);
-
-  // Write the requested register
-  Offset = RegisterToOffset (Register);
-  return MmioWrite8 (LanDriver->IoBase + Offset, Value);
-}
-
-
-/* ---------------- MII/PHY Access Operations ------------------ */
-
-#define LAN91X_MDIO_STALL   1
-
-STATIC
-VOID
-MdioOutput (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            Bits,
-  UINT32           Value
-  )
-{
-  UINT16          MgmtReg;
-  UINT32          Mask;
-
-  MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT);
-  MgmtReg &= ~MGMT_MCLK;
-  MgmtReg |= MGMT_MDOE;
-
-  for (Mask = (1 << (Bits - 1)); Mask != 0; Mask >>= 1) {
-    if ((Value & Mask) != 0) {
-      MgmtReg |= MGMT_MDO;
-    } else {
-      MgmtReg &= ~MGMT_MDO;
-    }
-
-    WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg);
-    gBS->Stall (LAN91X_MDIO_STALL);
-    WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg | MGMT_MCLK);
-    gBS->Stall (LAN91X_MDIO_STALL);
-  }
-}
-#define PHY_OUTPUT_TIME (2 * LAN91X_MDIO_STALL)
-
-STATIC
-UINT32
-MdioInput (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            Bits
-  )
-{
-  UINT16          MgmtReg;
-  UINT32          Mask;
-  UINT32          Value;
-
-  MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT);
-  MgmtReg &= ~(MGMT_MDOE | MGMT_MCLK | MGMT_MDO);
-  WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg);
-
-  Value = 0;
-  for (Mask = (1 << (Bits - 1)); Mask != 0; Mask >>= 1) {
-    if ((ReadIoReg16 (LanDriver, LAN91X_MGMT) & MGMT_MDI) != 0) {
-       Value |= Mask;
-    }
-
-    WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg);
-    gBS->Stall (LAN91X_MDIO_STALL);
-    WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg | MGMT_MCLK);
-    gBS->Stall (LAN91X_MDIO_STALL);
-  }
-
-  return Value;
-}
-#define PHY_INPUT_TIME (2 * LAN91X_MDIO_STALL)
-
-STATIC
-VOID
-MdioIdle (
-  LAN91X_DRIVER   *LanDriver
-  )
-{
-  UINT16          MgmtReg;
-
-  MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT);
-  MgmtReg &= ~(MGMT_MDOE | MGMT_MCLK | MGMT_MDO);
-  WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg);
-}
-
-// Write to a PHY register
-STATIC
-VOID
-WritePhyReg16 (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            RegAd,
-  UINT16           Value
-  )
-{
-  // Bit-bang the MII Serial Frame write operation
-  MdioOutput (LanDriver, 32, 0xffffffff);       // Send 32 Ones as a preamble
-  MdioOutput (LanDriver,  2, 0x01);             // Send Start (01)
-  MdioOutput (LanDriver,  2, 0x01);             // Send Write (01)
-  MdioOutput (LanDriver,  5, LanDriver->PhyAd); // Send PHYAD[4:0]
-  MdioOutput (LanDriver,  5, RegAd);            // Send REGAD[4:0]
-  MdioOutput (LanDriver,  2, 0x02);             // Send TurnAround (10)
-  MdioOutput (LanDriver, 16, Value);            // Write 16 data bits
-
-  // Idle the MDIO bus
-  MdioIdle (LanDriver);
-}
-// Calculate approximate time to write a PHY register in microseconds
-#define PHY_WRITE_TIME  ((32 + 2 + 2 + 5 + 5 + 2 + 16) * PHY_OUTPUT_TIME)
-
-// Read from a PHY register
-STATIC
-UINT16
-ReadPhyReg16 (
-  LAN91X_DRIVER   *LanDriver,
-  UINTN            RegAd
-  )
-{
-  UINT32 Value;
-
-  // Bit-bang the MII Serial Frame read operation
-  MdioOutput (LanDriver, 32, 0xffffffff);       // Send 32 Ones as a preamble
-  MdioOutput (LanDriver,  2, 0x01);             // Send Start (01)
-  MdioOutput (LanDriver,  2, 0x02);             // Send Read (10)
-  MdioOutput (LanDriver,  5, LanDriver->PhyAd); // Send PHYAD[4:0]
-  MdioOutput (LanDriver,  5, RegAd);            // Send REGAD[4:0]
-
-  (VOID)  MdioInput (LanDriver, 2);             // Discard TurnAround bits
-  Value = MdioInput (LanDriver, 16);            // Read 16 data bits
-
-  // Idle the MDIO bus
-  MdioIdle (LanDriver);
-
-  return (Value & 0xffff);
-}
-// Calculate approximate time to read a PHY register in microseconds
-#define PHY_READ_TIME  (((32 + 2 + 2 + 5 + 5) * PHY_OUTPUT_TIME) + \
-                        ((2 + 16) * PHY_INPUT_TIME))
-
-
-/* ---------------- Debug Functions ------------------ */
-
-#ifdef LAN91X_PRINT_REGISTERS
-STATIC
-VOID
-PrintIoRegisters (
-  IN  LAN91X_DRIVER   *LanDriver
-  )
-{
-  UINTN   Bank;
-  UINTN   Offset;
-  UINT16  Value;
-
-  DEBUG((EFI_D_ERROR, "\nLAN91x I/O Register Dump:\n"));
-
-  // Print currrent bank select register
-  Value = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
-  DEBUG((EFI_D_ERROR, "  BankSel: %d  Bank Register %04x (%d)\n",
-      LanDriver->BankSel, Value, Value & 0x0007));
-
-  // Print all I/O registers
-  for (Offset = 0; Offset < 0x0e; Offset += 2) {
-    DEBUG((EFI_D_ERROR, "  %02x:", Offset));
-    for (Bank = 0; Bank <= 3; ++Bank) {
-      DEBUG((EFI_D_ERROR, "  %04x", ReadIoReg16 (LanDriver, MakeRegister (Bank, Offset))));
-    }
-    DEBUG((EFI_D_ERROR, "\n"));
-  }
-}
-
-STATIC
-VOID
-PrintPhyRegisters (
-  IN  LAN91X_DRIVER   *LanDriver
-  )
-{
-  UINTN   RegNum;
-
-  DEBUG((EFI_D_ERROR, "\nLAN91x Phy %d Register Dump:\n", LanDriver->PhyAd));
-
-  // Print all Phy registers
-  for (RegNum = 0; RegNum <= 5; ++RegNum) {
-    DEBUG((EFI_D_ERROR, "  %2d:  %04x\n",
-           RegNum,
-           ReadPhyReg16 (LanDriver, RegNum)
-    ));
-  }
-  for (RegNum = 16; RegNum <= 20; ++RegNum) {
-    DEBUG((EFI_D_ERROR, "  %2d:  %04x\n",
-           RegNum,
-           ReadPhyReg16 (LanDriver, RegNum)
-    ));
-  }
-}
-#endif
-
-#if LAN91X_PRINT_PACKET_HEADERS
-STATIC
-VOID
-PrintIpDgram (
-  IN  CONST VOID  *DstMac,
-  IN  CONST VOID  *SrcMac,
-  IN  CONST VOID  *Proto,
-  IN  CONST VOID  *IpDgram
-  )
-{
-  CONST UINT8   *Ptr;
-  UINT16         SrcPort;
-  UINT16         DstPort;
-
-  Ptr = DstMac;
-  DEBUG((EFI_D_ERROR, "  Dst: %02x-%02x-%02x",
-         Ptr[0], Ptr[1], Ptr[2]));
-  DEBUG((EFI_D_ERROR, "-%02x-%02x-%02x",
-         Ptr[3], Ptr[4], Ptr[5]));
-
-  Ptr = SrcMac;
-  DEBUG((EFI_D_ERROR, "  Src: %02x-%02x-%02x",
-         Ptr[0], Ptr[1], Ptr[2]));
-  DEBUG((EFI_D_ERROR, "-%02x-%02x-%02x",
-         Ptr[3], Ptr[4], Ptr[5]));
-
-  Ptr = Proto;
-  DEBUG((EFI_D_ERROR, "  Proto: %02x%02x\n",
-         Ptr[0], Ptr[1]));
-
-  Ptr = IpDgram;
-  switch (Ptr[9]) {
-  case EFI_IP_PROTO_ICMP:
-    DEBUG((EFI_D_ERROR, "  ICMP"));
-    break;
-  case EFI_IP_PROTO_TCP:
-    DEBUG((EFI_D_ERROR, "  TCP"));
-    break;
-  case EFI_IP_PROTO_UDP:
-    DEBUG((EFI_D_ERROR, "  UDP"));
-    break;
-  default:
-    DEBUG((EFI_D_ERROR, "  IpProto %d\n", Ptr[9]));
-    return;
-  }
-
-  DEBUG((EFI_D_ERROR, "  SrcIp: %d.%d.%d.%d",
-         Ptr[12], Ptr[13], Ptr[14], Ptr[15]));
-  DEBUG((EFI_D_ERROR, "  DstIp: %d.%d.%d.%d",
-         Ptr[16], Ptr[17], Ptr[18], Ptr[19]));
-
-  SrcPort = (Ptr[20] << 8) | Ptr[21];
-  DstPort = (Ptr[22] << 8) | Ptr[23];
-  DEBUG((EFI_D_ERROR, "  SrcPort: %d  DstPort: %d\n", SrcPort, DstPort));
-}
-#endif
-
-
-/* ---------------- PHY Management Operations ----------------- */
-
-STATIC
-EFI_STATUS
-PhyDetect (
-  IN  LAN91X_DRIVER *LanDriver
-  )
-{
-  UINT16  PhyId1;
-  UINT16  PhyId2;
-
-  for (LanDriver->PhyAd = 0x1f; LanDriver->PhyAd >= 0 ; --LanDriver->PhyAd) {
-    PhyId1 = ReadPhyReg16 (LanDriver, PHY_INDEX_ID1);
-    PhyId2 = ReadPhyReg16 (LanDriver, PHY_INDEX_ID2);
-
-    if ((PhyId1 != 0x0000) && (PhyId1 != 0xffff) &&
-        (PhyId2 != 0x0000) && (PhyId2 != 0xffff)) {
-      if ((PhyId1 == 0x0016) && ((PhyId2 & 0xfff0) == 0xf840)) {
-        DEBUG((EFI_D_ERROR, "LAN91x: PHY type LAN83C183 (LAN91C111 Internal)\n"));
-      } else if ((PhyId1 == 0x0282) && ((PhyId2 & 0xfff0) == 0x1c50)) {
-        DEBUG((EFI_D_ERROR, "LAN91x: PHY type LAN83C180\n"));
-      } else {
-        DEBUG((EFI_D_ERROR, "LAN91x: PHY id %04x:%04x\n", PhyId1, PhyId2));
-      }
-      return EFI_SUCCESS;
-    }
-  }
-
-  DEBUG((EFI_D_ERROR, "LAN91x: PHY detection failed\n"));
-  return EFI_NO_MEDIA;
-}
-
-
-// Check the Link Status and take appropriate action
-STATIC
-BOOLEAN
-CheckLinkStatus (
-  IN  LAN91X_DRIVER *LanDriver
-  )
-{
-  UINT16  PhyStatus;
-
-  // Get the PHY Status
-  PhyStatus = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS);
-
-  return (PhyStatus & PHYSTS_LINK_STS) != 0;
-}
-
-
-// Do auto-negotiation
-STATIC
-EFI_STATUS
-PhyAutoNegotiate (
-  IN  LAN91X_DRIVER *LanDriver
-  )
-{
-  UINTN  Retries;
-  UINT16 PhyControl;
-  UINT16 PhyStatus;
-  UINT16 PhyAdvert;
-
-  // If there isn't a PHY, don't try to reset it
-  if (LanDriver->PhyAd == LAN91X_NO_PHY) {
-    return EFI_SUCCESS;
-  }
-
-  // Next check that auto-negotiation is supported
-  PhyStatus = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS);
-  if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {
-    return EFI_SUCCESS;
-  }
-
-  // Translate capabilities to advertise
-  PhyAdvert = PHYANA_CSMA;
-
-  if ((PhyStatus & PHYSTS_10BASET_HDPLX) != 0) {
-    PhyAdvert |= PHYANA_10BASET;
-  }
-  if ((PhyStatus & PHYSTS_10BASET_FDPLX) != 0) {
-    PhyAdvert |= PHYANA_10BASETFD;
-  }
-  if ((PhyStatus & PHYSTS_100BASETX_HDPLX) != 0) {
-    PhyAdvert |= PHYANA_100BASETX;
-  }
-  if ((PhyStatus & PHYSTS_100BASETX_FDPLX) != 0) {
-    PhyAdvert |= PHYANA_100BASETXFD;
-  }
-  if ((PhyStatus & PHYSTS_100BASE_T4) != 0) {
-    PhyAdvert |= PHYANA_100BASET4;
-  }
-
-  // Set the capabilities to advertise
-  WritePhyReg16 (LanDriver, PHY_INDEX_AUTO_NEG_ADVERT, PhyAdvert);
-  (VOID) ReadPhyReg16 (LanDriver, PHY_INDEX_AUTO_NEG_ADVERT);
-
-  // Restart Auto-Negotiation
-  PhyControl = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL);
-  PhyControl &= ~(PHYCR_SPEED_SEL | PHYCR_DUPLEX_MODE);
-  PhyControl |= PHYCR_AUTO_EN | PHYCR_RST_AUTO;
-  WritePhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL, PhyControl);
-
-  // Wait up to 2 seconds for the process to complete
-  Retries = 2000000 / (PHY_READ_TIME + 100);
-  while ((ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0) {
-    if (--Retries == 0) {
-      DEBUG((EFI_D_ERROR, "LAN91x: PHY auto-negotiation timed-out\n"));
-      return EFI_TIMEOUT;
-    }
-    gBS->Stall (100);
-  }
-
-  return EFI_SUCCESS;
-}
-
-
-// Perform PHY software reset
-STATIC
-EFI_STATUS
-PhySoftReset (
-  IN  LAN91X_DRIVER *LanDriver
-  )
-{
-  UINTN     Retries;
-
-  // If there isn't a PHY, don't try to reset it
-  if (LanDriver->PhyAd == LAN91X_NO_PHY) {
-    return EFI_SUCCESS;
-  }
-
-  // Request a PHY reset
-  WritePhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL, PHYCR_RESET);
-
-  // The internal PHY will reset within 50ms. Allow 100ms.
-  Retries = 100000 / (PHY_READ_TIME + 100);
-  while (ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {
-    if (--Retries == 0) {
-      DEBUG((EFI_D_ERROR, "LAN91x: PHY reset timed-out\n"));
-      return EFI_TIMEOUT;
-    }
-    gBS->Stall (100);
-  }
-
-  return EFI_SUCCESS;
-}
-
-
-/* ---------------- General Operations ----------------- */
-
-STATIC
-EFI_MAC_ADDRESS
-GetCurrentMacAddress (
-  IN  LAN91X_DRIVER *LanDriver
-  )
-{
-  UINTN            RegNum;
-  UINT8           *Addr;
-  EFI_MAC_ADDRESS  MacAddress;
-
-  SetMem (&MacAddress, sizeof(MacAddress), 0);
-
-  Addr = &MacAddress.Addr[0];
-  for (RegNum = LAN91X_IAR0; RegNum <= LAN91X_IAR5; ++RegNum) {
-    *Addr = ReadIoReg8 (LanDriver, RegNum);
-    ++Addr;
-  }
-
-  return MacAddress;
-}
-
-STATIC
-EFI_STATUS
-SetCurrentMacAddress (
-  IN  LAN91X_DRIVER   *LanDriver,
-  IN  EFI_MAC_ADDRESS *MacAddress
-  )
-{
-  UINTN            RegNum;
-  UINT8           *Addr;
-
-  Addr = &MacAddress->Addr[0];
-  for (RegNum = LAN91X_IAR0; RegNum <= LAN91X_IAR5; ++RegNum) {
-    WriteIoReg8 (LanDriver, RegNum, *Addr);
-    ++Addr;
-  }
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-MmuOperation (
-  IN  LAN91X_DRIVER *LanDriver,
-  IN  UINTN          MmuOp
-  )
-{
-  UINTN   Polls;
-
-  WriteIoReg16 (LanDriver, LAN91X_MMUCR, MmuOp);
-  Polls = 100;
-  while ((ReadIoReg16 (LanDriver, LAN91X_MMUCR) & MMUCR_BUSY) != 0) {
-    if (--Polls == 0) {
-      DEBUG((EFI_D_ERROR, "LAN91x: MMU operation %04x timed-out\n", MmuOp));
-      return EFI_TIMEOUT;
-    }
-    gBS->Stall (LAN91X_STALL);
-  }
-
-  return EFI_SUCCESS;
-}
-
-// Read bytes from the DATA register
-STATIC
-EFI_STATUS
-ReadIoData (
-  IN  LAN91X_DRIVER *LanDriver,
-  IN  VOID          *Buffer,
-  IN  UINTN          BufLen
-  )
-{
-  UINT8     *Ptr;
-
-  Ptr = Buffer;
-  for (; BufLen > 0; --BufLen) {
-    *Ptr = ReadIoReg8 (LanDriver, LAN91X_DATA0);
-    ++Ptr;
-  }
-
-  return EFI_SUCCESS;
-}
-
-// Write bytes to the DATA register
-STATIC
-EFI_STATUS
-WriteIoData (
-  IN  LAN91X_DRIVER *LanDriver,
-  IN  VOID          *Buffer,
-  IN  UINTN          BufLen
-  )
-{
-  UINT8     *Ptr;
-
-  Ptr = Buffer;
-  for (; BufLen > 0; --BufLen) {
-    WriteIoReg8 (LanDriver, LAN91X_DATA0, *Ptr);
-    ++Ptr;
-  }
-
-  return EFI_SUCCESS;
-}
-
-// Disable the interface
-STATIC
-EFI_STATUS
-ChipDisable (
-  IN  LAN91X_DRIVER *LanDriver
-  )
-{
-#ifdef LAN91X_POWER_DOWN
-  UINT16  Val16;
-#endif
-
-  // Stop Rx and Tx operations
-  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR);
-  WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_CLEAR);
-
-#ifdef LAN91X_POWER_DOWN
-  // Power-down the chip
-  Val16 = ReadIoReg16 (LanDriver, LAN91X_CR);
-  Val16 &= ~CR_EPH_POWER_EN;
-  WriteIoReg16 (LanDriver, LAN91X_CR, Val16);
-#endif
-
-  return EFI_SUCCESS;
-}
-
-// Enable the interface
-STATIC
-EFI_STATUS
-ChipEnable (
-  IN  LAN91X_DRIVER *LanDriver
-  )
-{
-#ifdef LAN91X_POWER_DOWN
-  UINT16  Val16;
-
-  // Power-up the chip
-  Val16 = ReadIoReg16 (LanDriver, LAN91X_CR);
-  Val16 |= CR_EPH_POWER_EN;
-  WriteIoReg16 (LanDriver, LAN91X_CR, Val16);
-  gBS->Stall (LAN91X_STALL);
-#endif
-
-  // Start Rx and Tx operations
-  WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_DEFAULT);
-  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_DEFAULT);
-
-  return EFI_SUCCESS;
-}
-
-
-// Perform software reset on the LAN91x
-STATIC
-EFI_STATUS
-SoftReset (
-  IN  LAN91X_DRIVER   *LanDriver
-  )
-{
-  UINT16  Val16;
-
-  // Issue the reset
-  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_SOFT_RST);
-  gBS->Stall (LAN91X_STALL);
-  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR);
-
-  // Set the configuration register
-  WriteIoReg16 (LanDriver, LAN91X_CR, CR_DEFAULT);
-  gBS->Stall (LAN91X_STALL);
-
-  // Stop Rx and Tx
-  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR);
-  WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_CLEAR);
-
-  // Initialize the Control Register
-  Val16 = ReadIoReg16 (LanDriver, LAN91X_CTR);
-  Val16 |= CTR_AUTO_REL;
-  WriteIoReg16 (LanDriver, LAN91X_CTR, Val16);
-
-  // Reset the MMU
-  MmuOperation (LanDriver, MMUCR_OP_RESET_MMU);
-
-  return EFI_SUCCESS;
-}
-
-/*
-**  Probe()
-**
-**  Validate that there is a LAN91x device.
-**
-*/
-STATIC
-EFI_STATUS
-Probe (
-  IN  LAN91X_DRIVER   *LanDriver
-  )
-{
-  UINT16        Bank;
-  UINT16        Val16;
-  CHAR16 CONST *ChipId;
-  UINTN         ResetTime;
-
-  // First check that the Bank Select register is valid
-  Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
-  if ((Bank & 0xff00) != 0x3300) {
-    DEBUG((EFI_D_ERROR, "LAN91x: signature error: expecting 33xx, read %04x\n", Bank));
-    return EFI_DEVICE_ERROR;
-  }
-
-  // Try reading the revision register next
-  LanDriver->BankSel = 0xff;
-  Val16 = ReadIoReg16 (LanDriver, LAN91X_REV);
-
-  Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
-  if ((Bank & 0xff03) != 0x3303) {
-    DEBUG((EFI_D_ERROR, "LAN91x: signature error: expecting 33x3, read %04x\n", Bank));
-    return EFI_DEVICE_ERROR;
-  }
-
-  // Validate the revision register
-  if ((Val16 & 0xff00) != 0x3300) {
-    DEBUG((EFI_D_ERROR, "LAN91x: revision error: expecting 33xx, read %04x\n", Val16));
-    return EFI_DEVICE_ERROR;
-  }
-
-  ChipId = ChipIds[(Val16 >> 4) & 0x0f];
-  if (ChipId == NULL) {
-    DEBUG((EFI_D_ERROR, "LAN91x: unrecognized revision: %04x\n", Val16));
-    return EFI_DEVICE_ERROR;
-  }
-  DEBUG((EFI_D_ERROR, "LAN91x: detected chip %s rev %d\n", ChipId, Val16 & 0xf));
-  LanDriver->Revision = Val16 & 0xff;
-
-  // Reload from EEPROM to get the hardware MAC address
-  WriteIoReg16 (LanDriver, LAN91X_CTR, CTR_RESERVED | CTR_RELOAD);
-  ResetTime = 1000;
-  while ((ReadIoReg16 (LanDriver, LAN91X_CTR) & CTR_RELOAD) != 0) {
-    if (--ResetTime == 0) {
-      DEBUG((EFI_D_ERROR, "LAN91x: reload from EEPROM timed-out\n"));
-      WriteIoReg16 (LanDriver, LAN91X_CTR, CTR_RESERVED);
-      return EFI_DEVICE_ERROR;
-    }
-    gBS->Stall (LAN91X_STALL);
-  }
-
-  // Read and save the Permanent MAC Address
-  LanDriver->SnpMode.PermanentAddress = GetCurrentMacAddress (LanDriver);
-  LanDriver->SnpMode.CurrentAddress = LanDriver->SnpMode.PermanentAddress;
-  DEBUG((EFI_D_ERROR, //EFI_D_NET | EFI_D_INFO,
-         "LAN91x: HW MAC Address: %02x-%02x-%02x-%02x-%02x-%02x\n",
-         LanDriver->SnpMode.PermanentAddress.Addr[0],
-         LanDriver->SnpMode.PermanentAddress.Addr[1],
-         LanDriver->SnpMode.PermanentAddress.Addr[2],
-         LanDriver->SnpMode.PermanentAddress.Addr[3],
-         LanDriver->SnpMode.PermanentAddress.Addr[4],
-         LanDriver->SnpMode.PermanentAddress.Addr[5]
-         ));
-
-  // Reset the device
-  SoftReset (LanDriver);
-
-  // Try to detect a PHY
-  if (LanDriver->Revision > (CHIP_91100 << 4)) {
-    PhyDetect (LanDriver);
-  } else {
-    LanDriver->PhyAd = LAN91X_NO_PHY;
-  }
-
-  return EFI_SUCCESS;
-}
-
-
-
-
-/*------------------ Simple Network Driver entry point functions ------------------*/
-
-// Refer to the Simple Network Protocol section (21.1)
-// in the UEFI 2.3.1 Specification for documentation.
-
-#define ReturnUnlock(s) do { Status = (s); goto exit_unlock; } while(0)
-
-
-/*
-**  UEFI Start() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpStart (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp
- )
-{
-  EFI_SIMPLE_NETWORK_MODE *Mode;
-  EFI_TPL                  SavedTpl;
-  EFI_STATUS               Status;
-
-  // Check Snp instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-  Mode = Snp->Mode;
-
-  // Check state of the driver
-  switch (Mode->State) {
-  case EfiSimpleNetworkStopped:
-    break;
-  case EfiSimpleNetworkStarted:
-  case EfiSimpleNetworkInitialized:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver already started\n"));
-    ReturnUnlock (EFI_ALREADY_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-
-  // Change state
-  Mode->State = EfiSimpleNetworkStarted;
-  Status = EFI_SUCCESS;
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-/*
-**  UEFI Stop() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpStop (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp
-  )
-{
-  LAN91X_DRIVER *LanDriver;
-  EFI_TPL        SavedTpl;
-  EFI_STATUS     Status;
-
-  // Check Snp Instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // Check state of the driver
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkStarted:
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  // Stop the Tx and Rx
-  ChipDisable (LanDriver);
-
-  // Change the state
-  Snp->Mode->State = EfiSimpleNetworkStopped;
-  Status = EFI_SUCCESS;
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-/*
-**  UEFI Initialize() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpInitialize (
-  IN  EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
-  IN  UINTN                        RxBufferSize    OPTIONAL,
-  IN  UINTN                        TxBufferSize    OPTIONAL
-  )
-{
-  LAN91X_DRIVER *LanDriver;
-  EFI_TPL        SavedTpl;
-  EFI_STATUS     Status;
-
-  // Check Snp Instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // Check that driver was started but not initialised
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkStarted:
-    break;
-  case EfiSimpleNetworkInitialized:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver already initialized\n"));
-    ReturnUnlock (EFI_SUCCESS);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  // Initiate a software reset
-  Status = SoftReset (LanDriver);
-  if (EFI_ERROR(Status)) {
-    DEBUG((EFI_D_WARN, "LAN91x: Soft reset failed\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Initiate a PHY reset
-  if (PhySoftReset (LanDriver) < 0) {
-    Snp->Mode->State = EfiSimpleNetworkStopped;
-    DEBUG((EFI_D_WARN, "LAN91x: PHY soft reset timeout\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  }
-
-  // Do auto-negotiation
-  Status = PhyAutoNegotiate (LanDriver);
-  if (EFI_ERROR(Status)) {
-    DEBUG((EFI_D_WARN, "LAN91x: PHY auto-negotiation failed\n"));
-  }
-
-  // Enable the receiver and transmitter
-  ChipEnable (LanDriver);
-
-  // Now acknowledge all interrupts
-  WriteIoReg8 (LanDriver, LAN91X_IST, 0xFF);
-
-  // Declare the driver as initialized
-  Snp->Mode->State = EfiSimpleNetworkInitialized;
-  Status = EFI_SUCCESS;
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-/*
-**  UEFI Reset () function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpReset (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
-  IN        BOOLEAN Verification
-  )
-{
-  LAN91X_DRIVER *LanDriver;
-  EFI_TPL        SavedTpl;
-  EFI_STATUS     Status;
-
-  // Check Snp Instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // Check that driver was started and initialised
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStarted:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  // Initiate a software reset
-  if (EFI_ERROR (SoftReset (LanDriver))) {
-    DEBUG((EFI_D_WARN, "LAN91x: Soft reset failed\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Initiate a PHY reset
-  if (EFI_ERROR (PhySoftReset (LanDriver))) {
-    DEBUG((EFI_D_WARN, "LAN91x: PHY soft reset failed\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Enable the receiver and transmitter
-  Status = ChipEnable (LanDriver);
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-/*
-**  UEFI Shutdown () function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpShutdown (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp
-  )
-{
-  LAN91X_DRIVER *LanDriver;
-  EFI_TPL        SavedTpl;
-  EFI_STATUS     Status;
-
-  // Check Snp Instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // First check that driver has already been initialized
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStarted:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver in stopped state\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  // Disable the interface
-  Status = ChipDisable (LanDriver);
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-
-/*
-**  UEFI ReceiveFilters() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpReceiveFilters (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
-  IN        UINT32 Enable,
-  IN        UINT32 Disable,
-  IN        BOOLEAN Reset,
-  IN        UINTN NumMfilter          OPTIONAL,
-  IN        EFI_MAC_ADDRESS *Mfilter  OPTIONAL
-  )
-{
-#define MCAST_HASH_BYTES  8
-
-  LAN91X_DRIVER           *LanDriver;
-  EFI_SIMPLE_NETWORK_MODE *SnpMode;
-  EFI_TPL        SavedTpl;
-  EFI_STATUS     Status;
-  UINTN          i;
-  UINT32         Crc;
-  UINT16         RcvCtrl;
-  UINT8          McastHash[MCAST_HASH_BYTES];
-
-  // Check Snp Instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // First check that driver has already been initialized
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStarted:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-  SnpMode = Snp->Mode;
-
-#ifdef LAN91X_PRINT_RECEIVE_FILTERS
-  DEBUG((EFI_D_ERROR, "LAN91x:SnpReceiveFilters()\n"));
-  DEBUG((EFI_D_ERROR, "  Enable     = %08x\n", Enable));
-  DEBUG((EFI_D_ERROR, "  Disable    = %08x\n", Disable));
-  DEBUG((EFI_D_ERROR, "  Reset      = %d\n",  Reset));
-  DEBUG((EFI_D_ERROR, "  NumMfilter = %d\n",  NumMfilter));
-  for (i = 0; i < NumMfilter; ++i) {
-    DEBUG((EFI_D_ERROR,
-           "    [%2d] = %02x-%02x-%02x-%02x-%02x-%02x\n",
-           i,
-           Mfilter[i].Addr[0],
-           Mfilter[i].Addr[1],
-           Mfilter[i].Addr[2],
-           Mfilter[i].Addr[3],
-           Mfilter[i].Addr[4],
-           Mfilter[i].Addr[5]));
-  }
-#endif
-
-  // Update the Multicast Hash registers
-  if (Reset) {
-    // Clear the hash table
-    SetMem (McastHash, MCAST_HASH_BYTES, 0);
-    SnpMode->MCastFilterCount = 0;
-  } else {
-    // Read the current hash table
-    for (i = 0; i < MCAST_HASH_BYTES; ++i) {
-      McastHash[i] = ReadIoReg8 (LanDriver, LAN91X_MT0 + i);
-    }
-    // Set the new additions
-    for (i = 0; i < NumMfilter; ++i) {
-      Crc = MulticastHash (&Mfilter[i], NET_ETHER_ADDR_LEN);
-      McastHash[(Crc >> 29) & 0x3] |= 1 << ((Crc >> 26) & 0x3);
-    }
-    SnpMode->MCastFilterCount = NumMfilter;
-  }
-  // If the hash registers need updating, write them
-  if (Reset || NumMfilter > 0) {
-    for (i = 0; i < MCAST_HASH_BYTES; ++i) {
-      WriteIoReg8 (LanDriver, LAN91X_MT0 + i, McastHash[i]);
-    }
-  }
-
-  RcvCtrl = ReadIoReg16 (LanDriver, LAN91X_RCR);
-  if ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) {
-    RcvCtrl |= RCR_PRMS;
-    SnpMode->ReceiveFilterSetting |= EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS;
-  }
-  if ((Disable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) {
-    RcvCtrl &= ~RCR_PRMS;
-    SnpMode->ReceiveFilterSetting &= ~EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS;
-  }
-
-  if ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) != 0) {
-    RcvCtrl |= RCR_ALMUL;
-    SnpMode->ReceiveFilterSetting |= EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
-  }
-  if ((Disable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) != 0) {
-    RcvCtrl &= ~RCR_ALMUL;
-    SnpMode->ReceiveFilterSetting &= ~EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
-  }
-  WriteIoReg16 (LanDriver, LAN91X_RCR, RcvCtrl);
-
-  Status = SetCurrentMacAddress (LanDriver, &SnpMode->CurrentAddress);
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-/*
-**  UEFI StationAddress() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpStationAddress (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
-  IN        BOOLEAN Reset,
-  IN        EFI_MAC_ADDRESS *NewMac
-)
-{
-  LAN91X_DRIVER *LanDriver;
-  EFI_TPL        SavedTpl;
-  EFI_STATUS     Status;
-
-  // Check Snp instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // Check that driver was started and initialised
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStarted:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  if (Reset) {
-    Snp->Mode->CurrentAddress = Snp->Mode->PermanentAddress;
-  } else {
-    if (NewMac == NULL) {
-      ReturnUnlock (EFI_INVALID_PARAMETER);
-    }
-    Snp->Mode->CurrentAddress = *NewMac;
-  }
-
-  Status = SetCurrentMacAddress (LanDriver, &Snp->Mode->CurrentAddress);
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-/*
-**  UEFI Statistics() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpStatistics (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
-  IN        BOOLEAN Reset,
-  IN  OUT   UINTN *StatSize,
-      OUT   EFI_NETWORK_STATISTICS *Statistics
-  )
-{
-  LAN91X_DRIVER *LanDriver;
-  EFI_TPL        SavedTpl;
-  EFI_STATUS     Status;
-
-  // Check Snp instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Check pointless condition
-  if ((!Reset) && (StatSize == NULL) && (Statistics == NULL)) {
-    return EFI_SUCCESS;
-  }
-
-  // Check the parameters
-  if ((StatSize == NULL) && (Statistics != NULL)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // Check that driver was started and initialised
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStarted:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  // Do a reset if required
-  if (Reset) {
-    ZeroMem (&LanDriver->Stats, sizeof(EFI_NETWORK_STATISTICS));
-  }
-
-  // Check buffer size
-  if (*StatSize < sizeof(EFI_NETWORK_STATISTICS)) {
-    *StatSize = sizeof(EFI_NETWORK_STATISTICS);
-    ReturnUnlock (EFI_BUFFER_TOO_SMALL);
-    goto exit_unlock;
-  }
-
-  // Fill in the statistics
-  CopyMem(&Statistics, &LanDriver->Stats, sizeof(EFI_NETWORK_STATISTICS));
-  Status = EFI_SUCCESS;
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-/*
-**  UEFI MCastIPtoMAC() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpMcastIptoMac (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
-  IN        BOOLEAN IsIpv6,
-  IN        EFI_IP_ADDRESS *Ip,
-      OUT   EFI_MAC_ADDRESS *McastMac
-  )
-{
-  // Check Snp instance
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Check parameters
-  if ((McastMac == NULL) || (Ip == NULL)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Make sure MAC address is empty
-  ZeroMem (McastMac, sizeof(EFI_MAC_ADDRESS));
-
-  // If we need ipv4 address
-  if (!IsIpv6) {
-    // Most significant 25 bits of a multicast HW address are set
-    McastMac->Addr[0] = 0x01;
-    McastMac->Addr[1] = 0x00;
-    McastMac->Addr[2] = 0x5E;
-
-    // Lower 23 bits from ipv4 address
-    McastMac->Addr[3] = (Ip->v4.Addr[1] & 0x7F); // Clear the ms bit (25th bit of MAC must be 0)
-    McastMac->Addr[4] = Ip->v4.Addr[2];
-    McastMac->Addr[5] = Ip->v4.Addr[3];
-  } else {
-    // Most significant 16 bits of multicast v6 HW address are set
-    McastMac->Addr[0] = 0x33;
-    McastMac->Addr[1] = 0x33;
-
-    // lower four octets are taken from ipv6 address
-    McastMac->Addr[2] = Ip->v6.Addr[8];
-    McastMac->Addr[3] = Ip->v6.Addr[9];
-    McastMac->Addr[4] = Ip->v6.Addr[10];
-    McastMac->Addr[5] = Ip->v6.Addr[11];
-  }
-
-  return EFI_SUCCESS;
-}
-
-/*
-**  UEFI NvData() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpNvData (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL* pobj,
-  IN        BOOLEAN read_write,
-  IN        UINTN offset,
-  IN        UINTN buff_size,
-  IN  OUT   VOID *data
-  )
-{
-  DEBUG((EFI_D_ERROR, "LAN91x: Non-volatile storage not supported\n"));
-
-  return EFI_UNSUPPORTED;
-}
-
-
-/*
-**  UEFI GetStatus () function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpGetStatus (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
-      OUT   UINT32   *IrqStat   OPTIONAL,
-      OUT   VOID    **TxBuff    OPTIONAL
-  )
-{
-  LAN91X_DRIVER   *LanDriver;
-  EFI_TPL          SavedTpl;
-  EFI_STATUS       Status;
-  BOOLEAN          MediaPresent;
-  UINT8            IstReg;
-
-  // Check preliminaries
-  if (Snp == NULL) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // Check that driver was started and initialised
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStarted:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  // Arbitrarily set the interrupt status to 0
-  if (IrqStat != NULL) {
-    *IrqStat = 0;
-    IstReg = ReadIoReg8 (LanDriver, LAN91X_IST);
-    if ((IstReg & IST_RCV) != 0) {
-      *IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
-    }
-    if ((IstReg & IST_TX) != 0) {
-      *IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
-    }
-  }
-
-  // Pass back the completed buffer address
-  if (TxBuff != NULL) {
-    *TxBuff = TxQueRemove (LanDriver);
-  }
-
-  // Update the media status
-  MediaPresent = CheckLinkStatus (LanDriver);
-  if (MediaPresent != Snp->Mode->MediaPresent) {
-    DEBUG((EFI_D_WARN, "LAN91x: Link %s\n", MediaPresent ? L"up" : L"down"));
-  }
-  Snp->Mode->MediaPresent = MediaPresent;
-  Status = EFI_SUCCESS;
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-
-/*
-**  UEFI Transmit() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpTransmit (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
-  IN        UINTN            HdrSize,
-  IN        UINTN            BufSize,
-  IN        VOID            *BufAddr,
-  IN        EFI_MAC_ADDRESS *SrcAddr    OPTIONAL,
-  IN        EFI_MAC_ADDRESS *DstAddr    OPTIONAL,
-  IN        UINT16          *Protocol   OPTIONAL
-  )
-{
-  LAN91X_DRIVER   *LanDriver;
-  EFI_TPL          SavedTpl;
-  EFI_STATUS       Status;
-  UINT8           *Ptr;
-  UINTN            Len;
-  UINTN            MmuPages;
-  UINTN            Retries;
-  UINT16           Proto;
-  UINT8            PktNum;
-
-  // Check preliminaries
-  if ((Snp == NULL) || (BufAddr == NULL)) {
-    DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): NULL Snp (%p) or BufAddr (%p)\n",
-        Snp, BufAddr));
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // Check that driver was started and initialised
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStarted:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  // Ensure header is correct size if non-zero
-  if (HdrSize != 0) {
-    if (HdrSize != Snp->Mode->MediaHeaderSize) {
-      DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): Invalid HdrSize %d\n", HdrSize));
-      ReturnUnlock (EFI_INVALID_PARAMETER);
-    }
-
-    if ((DstAddr == NULL) || (Protocol == NULL)) {
-      DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): NULL DstAddr %p or Protocol %p\n",
-          DstAddr, Protocol));
-      ReturnUnlock (EFI_INVALID_PARAMETER);
-    }
-  }
-
-  // Before transmitting check the link status
-  if (!Snp->Mode->MediaPresent) {
-    DEBUG((EFI_D_WARN, "LAN91x: SnpTransmit(): Link not ready\n"));
-    ReturnUnlock (EFI_NOT_READY);
-  }
-
-  // Calculate the request size in 256-byte "pages" minus 1
-  // The 91C111 ignores this, but some older devices need it.
-  MmuPages = ((BufSize & ~1) + LAN91X_PKT_OVERHEAD - 1) >> 8;
-  if (MmuPages > 7) {
-    DEBUG((EFI_D_WARN, "LAN91x: Tx buffer too large (%d bytes)\n", BufSize));
-    LanDriver->Stats.TxOversizeFrames += 1;
-    LanDriver->Stats.TxDroppedFrames += 1;
-    ReturnUnlock (EFI_BAD_BUFFER_SIZE);
-  }
-
-  // Request allocation of a transmit buffer
-  Status = MmuOperation (LanDriver, MMUCR_OP_TX_ALLOC | MmuPages);
-  if (EFI_ERROR (Status)) {
-    DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer request failure: %d\n", Status));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Wait for allocation request completion
-  Retries = LAN91X_MEMORY_ALLOC_POLLS;
-  while ((ReadIoReg8 (LanDriver, LAN91X_IST) & IST_ALLOC) == 0) {
-    if (--Retries == 0) {
-      DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer allocation timeout\n"));
-      ReturnUnlock (EFI_TIMEOUT);
-    }
-  }
-
-  // Check for successful allocation
-  PktNum = ReadIoReg8 (LanDriver, LAN91X_ARR);
-  if ((PktNum & ARR_FAILED) != 0) {
-    DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer allocation failure: %02x\n", PktNum));
-    ReturnUnlock (EFI_NOT_READY);
-  }
-  PktNum &= ARR_PACKET;
-
-  // Check for the nature of the frame
-  if (DstAddr->Addr[0] == 0xFF) {
-    LanDriver->Stats.TxBroadcastFrames += 1;
-  } else if ((DstAddr->Addr[0] & 0x1) == 1) {
-    LanDriver->Stats.TxMulticastFrames += 1;
-  } else {
-    LanDriver->Stats.TxUnicastFrames += 1;
-  }
-
-  // Set the Packet Number and Pointer registers
-  WriteIoReg8 (LanDriver, LAN91X_PNR, PktNum);
-  WriteIoReg16 (LanDriver, LAN91X_PTR, PTR_AUTO_INCR);
-
-  // Set up mutable buffer information variables
-  Ptr = BufAddr;
-  Len = BufSize;
-
-  // Write Status and Byte Count first
-  WriteIoReg16 (LanDriver, LAN91X_DATA0, 0);
-  WriteIoReg16 (LanDriver, LAN91X_DATA0, (Len + LAN91X_PKT_OVERHEAD) & BCW_COUNT);
-
-  // This packet may come with a preconfigured Ethernet header.
-  // If not, we need to construct one from optional parameters.
-  if (HdrSize) {
-
-    // Write the destination address
-    WriteIoData (LanDriver, DstAddr, NET_ETHER_ADDR_LEN);
-
-    // Write the Source Address
-    if (SrcAddr != NULL) {
-      WriteIoData (LanDriver, SrcAddr, NET_ETHER_ADDR_LEN);
-    } else {
-      WriteIoData (LanDriver, &LanDriver->SnpMode.CurrentAddress, NET_ETHER_ADDR_LEN);
-    }
-
-    // Write the Protocol word
-    Proto = HTONS (*Protocol);
-    WriteIoReg16 (LanDriver, LAN91X_DATA0, Proto);
-
-    // Adjust the data start and length
-    Ptr += sizeof(ETHER_HEAD);
-    Len -= sizeof(ETHER_HEAD);
-  }
-
-  // Copy the remainder data buffer, except the odd byte
-  WriteIoData (LanDriver, Ptr, Len & ~1);
-  Ptr += Len & ~1;
-  Len &= 1;
-
-  // Write the Packet Control Word and odd byte
-  WriteIoReg16 (LanDriver, LAN91X_DATA0,
-      (Len != 0) ? (PCW_ODD | PCW_CRC | *Ptr) : PCW_CRC);
-
-  // Release the packet for transmission
-  Status = MmuOperation (LanDriver, MMUCR_OP_TX_PUSH);
-  if (EFI_ERROR (Status)) {
-    DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer release failure: %d\n", Status));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Update the Rx statistics
-  LanDriver->Stats.TxTotalBytes += BufSize;
-  LanDriver->Stats.TxGoodFrames += 1;
-
-  // Update the Tx Buffer cache
-  if (!TxQueInsert (LanDriver, BufAddr)) {
-    DEBUG((EFI_D_WARN, "LAN91x: SnpTransmit(): TxQueue insert failure.\n"));
-  }
-  Status = EFI_SUCCESS;
-
-  // Dump the packet header
-#if LAN91X_PRINT_PACKET_HEADERS
-  Ptr = BufAddr;
-  DEBUG((EFI_D_ERROR, "LAN91X:SnpTransmit()\n"));
-  DEBUG((EFI_D_ERROR, "  HdrSize: %d, SrcAddr: %p, Length: %d, Last byte: %02x\n",
-         HdrSize, SrcAddr, BufSize, Ptr[BufSize - 1]));
-  PrintIpDgram (
-      (HdrSize == 0) ? (EFI_MAC_ADDRESS *)&Ptr[0] : DstAddr,
-      (HdrSize == 0) ? (EFI_MAC_ADDRESS *)&Ptr[6] : (SrcAddr != NULL) ? SrcAddr : &LanDriver->SnpMode.CurrentAddress,
-      (HdrSize == 0) ? (UINT16 *)&Ptr[12] : &Proto,
-      &Ptr[14]
-      );
-#endif
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-
-/*
-**  UEFI Receive() function
-**
-*/
-EFI_STATUS
-EFIAPI
-SnpReceive (
-  IN        EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
-      OUT   UINTN           *HdrSize      OPTIONAL,
-  IN  OUT   UINTN           *BuffSize,
-      OUT   VOID            *Data,
-      OUT   EFI_MAC_ADDRESS *SrcAddr      OPTIONAL,
-      OUT   EFI_MAC_ADDRESS *DstAddr      OPTIONAL,
-      OUT   UINT16 *Protocol              OPTIONAL
-  )
-{
-  EFI_TPL        SavedTpl;
-  EFI_STATUS     Status;
-  LAN91X_DRIVER *LanDriver;
-  UINT8         *DataPtr;
-  UINT16         PktStatus;
-  UINT16         PktLength;
-  UINT16         PktControl;
-  UINT8          IstReg;
-
-  // Check preliminaries
-  if ((Snp == NULL) || (Data == NULL)) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  // Serialize access to data and registers
-  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
-
-  // Check that driver was started and initialised
-  switch (Snp->Mode->State) {
-  case EfiSimpleNetworkInitialized:
-    break;
-  case EfiSimpleNetworkStarted:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  case EfiSimpleNetworkStopped:
-    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
-    ReturnUnlock (EFI_NOT_STARTED);
-  default:
-    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
-          (UINTN)Snp->Mode->State));
-    ReturnUnlock (EFI_DEVICE_ERROR);
-  }
-
-  // Find the LanDriver structure
-  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
-
-  // Check for Rx Overrun
-  IstReg = ReadIoReg8 (LanDriver, LAN91X_IST);
-  if ((IstReg & IST_RX_OVRN) != 0) {
-    LanDriver->Stats.RxTotalFrames += 1;
-    LanDriver->Stats.RxDroppedFrames += 1;
-    WriteIoReg8 (LanDriver, LAN91X_IST, IST_RX_OVRN);
-    DEBUG((EFI_D_WARN, "LAN91x: Receiver overrun\n"));
-  }
-
-  // Check for Rx data available
-  if ((IstReg & IST_RCV) == 0) {
-    ReturnUnlock (EFI_NOT_READY);
-  }
-
-  // Configure the PTR register for reading
-  WriteIoReg16 (LanDriver, LAN91X_PTR, PTR_RCV | PTR_AUTO_INCR | PTR_READ);
-
-  // Read the Packet Status and Packet Length words
-  PktStatus = ReadIoReg16 (LanDriver, LAN91X_DATA0);
-  PktLength = ReadIoReg16 (LanDriver, LAN91X_DATA0) & BCW_COUNT;
-
-  // Check for valid received packet
-  if ((PktStatus == 0) && (PktLength == 0)) {
-    DEBUG((EFI_D_WARN, "LAN91x: Received zero-length packet. IST=%04x\n", IstReg));
-    ReturnUnlock (EFI_NOT_READY);
-  }
-  LanDriver->Stats.RxTotalFrames += 1;
-
-  // Check if we got a CRC error
-  if ((PktStatus & RX_BAD_CRC) != 0) {
-    DEBUG((EFI_D_WARN, "LAN91x: Received frame CRC error\n"));
-    LanDriver->Stats.RxCrcErrorFrames += 1;
-    LanDriver->Stats.RxDroppedFrames += 1;
-    Status = EFI_DEVICE_ERROR;
-    goto exit_release;
-  }
-
-  // Check if we got a too-short frame
-  if ((PktStatus & RX_TOO_SHORT) != 0) {
-    DEBUG((EFI_D_WARN, "LAN91x: Received frame too short (%d bytes)\n", PktLength));
-    LanDriver->Stats.RxUndersizeFrames += 1;
-    LanDriver->Stats.RxDroppedFrames += 1;
-    Status = EFI_DEVICE_ERROR;
-    goto exit_release;
-  }
-
-   // Check if we got a too-long frame
-  if ((PktStatus & RX_TOO_LONG) != 0) {
-    DEBUG((EFI_D_WARN, "LAN91x: Received frame too long (%d bytes)\n", PktLength));
-    LanDriver->Stats.RxOversizeFrames += 1;
-    LanDriver->Stats.RxDroppedFrames += 1;
-    Status = EFI_DEVICE_ERROR;
-    goto exit_release;
-  }
-
-   // Check if we got an alignment error
-  if ((PktStatus & RX_ALGN_ERR) != 0) {
-    DEBUG((EFI_D_WARN, "LAN91x: Received frame alignment error\n"));
-    // Don't seem to keep track of these specifically
-    LanDriver->Stats.RxDroppedFrames += 1;
-    Status = EFI_DEVICE_ERROR;
-    goto exit_release;
-  }
-
-  // Classify the received fram
-  if ((PktStatus & RX_MULTICAST) != 0) {
-    LanDriver->Stats.RxMulticastFrames += 1;
-  } else if ((PktStatus & RX_BROADCAST) != 0) {
-    LanDriver->Stats.RxBroadcastFrames += 1;
-  } else {
-    LanDriver->Stats.RxUnicastFrames += 1;
-  }
-
-  // Calculate the received packet data length
-  PktLength -= LAN91X_PKT_OVERHEAD;
-  if ((PktStatus & RX_ODD_FRAME) != 0) {
-    PktLength += 1;
-  }
-
-  // Check buffer size
-  if (*BuffSize < PktLength) {
-    DEBUG((EFI_D_WARN, "LAN91x: Receive buffer too small for packet (%d < %d)\n",
-        *BuffSize, PktLength));
-    *BuffSize = PktLength;
-    Status = EFI_BUFFER_TOO_SMALL;
-    goto exit_release;
-  }
-
-  // Transfer the data bytes
-  DataPtr = Data;
-  ReadIoData (LanDriver, DataPtr, PktLength & ~0x0001);
-
-  // Read the PktControl and Odd Byte from the FIFO
-  PktControl = ReadIoReg16 (LanDriver, LAN91X_DATA0);
-  if ((PktControl & PCW_ODD) != 0) {
-    DataPtr[PktLength - 1] = PktControl & PCW_ODD_BYTE;
-  }
-
-  // Update buffer size
-  *BuffSize = PktLength;
-
-  if (HdrSize != NULL) {
-    *HdrSize = LanDriver->SnpMode.MediaHeaderSize;
-  }
-
-  // Extract the destination address
-  if (DstAddr != NULL) {
-    CopyMem (DstAddr, &DataPtr[0], NET_ETHER_ADDR_LEN);
-  }
-
-  // Get the source address
-  if (SrcAddr != NULL) {
-    CopyMem (SrcAddr, &DataPtr[6], NET_ETHER_ADDR_LEN);
-  }
-
-  // Get the protocol
-  if (Protocol != NULL) {
-    *Protocol = NTOHS (*(UINT16*)(&DataPtr[12]));
-  }
-
-  // Update the Rx statistics
-  LanDriver->Stats.RxTotalBytes += PktLength;
-  LanDriver->Stats.RxGoodFrames += 1;
-  Status = EFI_SUCCESS;
-
-#if LAN91X_PRINT_PACKET_HEADERS
-  // Dump the packet header
-  DEBUG((EFI_D_ERROR, "LAN91X:SnpReceive()\n"));
-  DEBUG((EFI_D_ERROR, "  HdrSize: %p, SrcAddr: %p, DstAddr: %p, Protocol: %p\n",
-         HdrSize, SrcAddr, DstAddr, Protocol));
-  DEBUG((EFI_D_ERROR, "  Length: %d, Last byte: %02x\n", PktLength, DataPtr[PktLength - 1]));
-  PrintIpDgram (&DataPtr[0], &DataPtr[6], &DataPtr[12], &DataPtr[14]);
-#endif
-
-  // Release the FIFO buffer
-exit_release:
-  MmuOperation (LanDriver, MMUCR_OP_RX_POP_REL);
-
-  // Restore TPL and return
-exit_unlock:
-  gBS->RestoreTPL (SavedTpl);
-  return Status;
-}
-
-
-/*------------------ Driver Execution Environment main entry point ------------------*/
-
-/*
-**  Entry point for the LAN91x driver
-**
-*/
-EFI_STATUS
-Lan91xDxeEntry (
-  IN EFI_HANDLE Handle,
-  IN EFI_SYSTEM_TABLE *SystemTable
-  )
-{
-  EFI_STATUS Status;
-  LAN91X_DRIVER *LanDriver;
-  EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
-  EFI_SIMPLE_NETWORK_MODE *SnpMode;
-  LAN91X_DEVICE_PATH *Lan91xPath;
-
-  // The PcdLan91xDxeBaseAddress PCD must be defined
-  ASSERT(PcdGet32 (PcdLan91xDxeBaseAddress) != 0);
-
-  // Allocate Resources
-  LanDriver = AllocateZeroPool (sizeof(LAN91X_DRIVER));
-  Lan91xPath = AllocateCopyPool (sizeof(LAN91X_DEVICE_PATH), &Lan91xPathTemplate);
-
-  // Initialize I/O Space access info
-  LanDriver->IoBase = PcdGet32 (PcdLan91xDxeBaseAddress);
-  LanDriver->PhyAd = LAN91X_NO_PHY;
-  LanDriver->BankSel = 0xff;
-
-  // Initialize pointers
-  Snp = &(LanDriver->Snp);
-  SnpMode = &(LanDriver->SnpMode);
-  Snp->Mode = SnpMode;
-
-  // Set the signature of the LAN Driver structure
-  LanDriver->Signature = LAN91X_SIGNATURE;
-
-  // Probe the device
-  Status = Probe (LanDriver);
-  if (EFI_ERROR(Status)) {
-    DEBUG((EFI_D_ERROR, "LAN91x:Lan91xDxeEntry(): Probe failed with status %d\n", Status));
-    return Status;
-  }
-
-#ifdef LAN91X_PRINT_REGISTERS
-  PrintIoRegisters (LanDriver);
-  PrintPhyRegisters (LanDriver);
-#endif
-
-  // Assign fields and func pointers
-  Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
-  Snp->WaitForPacket = NULL;
-  Snp->Initialize = SnpInitialize;
-  Snp->Start = SnpStart;
-  Snp->Stop = SnpStop;
-  Snp->Reset = SnpReset;
-  Snp->Shutdown = SnpShutdown;
-  Snp->ReceiveFilters = SnpReceiveFilters;
-  Snp->StationAddress = SnpStationAddress;
-  Snp->Statistics = SnpStatistics;
-  Snp->MCastIpToMac = SnpMcastIptoMac;
-  Snp->NvData = SnpNvData;
-  Snp->GetStatus = SnpGetStatus;
-  Snp->Transmit = SnpTransmit;
-  Snp->Receive = SnpReceive;
-
-  // Fill in simple network mode structure
-  SnpMode->State = EfiSimpleNetworkStopped;
-  SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN;    // HW address is 6 bytes
-  SnpMode->MediaHeaderSize = sizeof(ETHER_HEAD);  // Size of an Ethernet header
-  SnpMode->MaxPacketSize = EFI_PAGE_SIZE;         // Ethernet Frame (with VLAN tag +4 bytes)
-
-  // Supported receive filters
-  SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
-                               EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
-                               EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |
-                               EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |
-                               EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
-
-  // Initially-enabled receive filters
-  SnpMode->ReceiveFilterSetting = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
-                                  EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
-                                  EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST;
-
-  // LAN91x has 64bit hash table. We can filter an infinite MACs, but
-  // higher-level software must filter out any hash collisions.
-  SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
-  SnpMode->MCastFilterCount = 0;
-  ZeroMem (&SnpMode->MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));
-
-  // Set the interface type (1: Ethernet or 6: IEEE 802 Networks)
-  SnpMode->IfType = NET_IFTYPE_ETHERNET;
-
-  // Mac address is changeable
-  SnpMode->MacAddressChangeable = TRUE;
-
-  // We can only transmit one packet at a time
-  SnpMode->MultipleTxSupported = FALSE;
-
-  // MediaPresent checks for cable connection and partner link
-  SnpMode->MediaPresentSupported = TRUE;
-  SnpMode->MediaPresent = FALSE;
-
-  //  Set broadcast address
-  SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
-
-  // Assign fields for device path
-  Lan91xPath->Lan91x.MacAddress = SnpMode->PermanentAddress;
-  Lan91xPath->Lan91x.IfType = SnpMode->IfType;
-
-  // Initialise the protocol
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &LanDriver->ControllerHandle,
-                  &gEfiSimpleNetworkProtocolGuid, Snp,
-                  &gEfiDevicePathProtocolGuid, Lan91xPath,
-                  NULL
-                  );
-
-  // Say what the status of loading the protocol structure is
-  if (EFI_ERROR(Status)) {
-    FreePool (LanDriver);
-  }
-
-  return Status;
-}
+/** @file
+*  SMSC LAN91x series Network Controller Driver.
+*
+*  Copyright (c) 2013 Linaro.org
+*
+*  Derived from the LAN9118 driver. Original sources
+*  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials are licensed and
+*  made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license
+*  may be found at: http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Uefi/UefiSpec.h>
+#include <Base.h>
+
+// Protocols used by this driver
+#include <Protocol/SimpleNetwork.h>
+#include <Protocol/ComponentName2.h>
+#include <Protocol/PxeBaseCode.h>
+#include <Protocol/DevicePath.h>
+
+// Libraries used by this driver
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/NetLib.h>
+#include <Library/DevicePathLib.h>
+
+// Hardware register definitions
+#include "Lan91xDxeHw.h"
+
+// Debugging output options
+//#define LAN91X_PRINT_REGISTERS 1
+//#define LAN91X_PRINT_PACKET_HEADERS 1
+//#define LAN91X_PRINT_RECEIVE_FILTERS 1
+
+// Chip power-down option -- UNTESTED
+//#define LAN91X_POWER_DOWN 1
+
+/*---------------------------------------------------------------------------------------------------------------------
+
+  LAN91x Information Structure
+
+---------------------------------------------------------------------------------------------------------------------*/
+typedef struct _LAN91X_DRIVER {
+  // Driver signature
+  UINT32            Signature;
+  EFI_HANDLE        ControllerHandle;
+
+  // EFI SNP protocol instances
+  EFI_SIMPLE_NETWORK_PROTOCOL Snp;
+  EFI_SIMPLE_NETWORK_MODE SnpMode;
+
+  // EFI Snp statistics instance
+  EFI_NETWORK_STATISTICS Stats;
+
+  // Transmit Buffer recycle queue
+
+  LIST_ENTRY TransmitQueueHead;
+
+  // Register access variables
+  UINTN             IoBase;             // I/O Base Address
+  UINT8             Revision;           // Chip Revision Number
+  INT8              PhyAd;              // Phy Address
+  UINT8             BankSel;            // Currently selected register bank
+
+} LAN91X_DRIVER;
+
+#define LAN91X_NO_PHY (-1)              // PhyAd value if PHY not detected
+
+#define LAN91X_SIGNATURE                        SIGNATURE_32('S', 'M', '9', '1')
+#define INSTANCE_FROM_SNP_THIS(a)               CR(a, LAN91X_DRIVER, Snp, LAN91X_SIGNATURE)
+
+#define LAN91X_STALL              2
+#define LAN91X_MEMORY_ALLOC_POLLS 100   // Max times to poll for memory allocation
+#define LAN91X_PKT_OVERHEAD       6     // Overhead bytes in packet buffer
+
+// Synchronization TPLs
+#define LAN91X_TPL  TPL_CALLBACK
+
+// Most common CRC32 Polynomial for little endian machines
+#define CRC_POLYNOMIAL               0xEDB88320
+
+
+typedef struct {
+  MAC_ADDR_DEVICE_PATH      Lan91x;
+  EFI_DEVICE_PATH_PROTOCOL  End;
+} LAN91X_DEVICE_PATH;
+
+LAN91X_DEVICE_PATH Lan91xPathTemplate =  {
+  {
+    {
+      MESSAGING_DEVICE_PATH, MSG_MAC_ADDR_DP,
+      { (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)), (UINT8) ((sizeof(MAC_ADDR_DEVICE_PATH)) >> 8) }
+    },
+    { { 0 } },
+    0
+  },
+  {
+    END_DEVICE_PATH_TYPE,
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0 }
+  }
+};
+
+// Chip ID numbers and name strings
+#define CHIP_9192       3
+#define CHIP_9194       4
+#define CHIP_9195       5
+#define CHIP_9196       6
+#define CHIP_91100      7
+#define CHIP_91100FD    8
+#define CHIP_91111FD    9
+
+STATIC CHAR16 CONST * CONST ChipIds[ 16 ] =  {
+  NULL, NULL, NULL,
+  /* 3 */ L"SMC91C90/91C92",
+  /* 4 */ L"SMC91C94",
+  /* 5 */ L"SMC91C95",
+  /* 6 */ L"SMC91C96",
+  /* 7 */ L"SMC91C100",
+  /* 8 */ L"SMC91C100FD",
+  /* 9 */ L"SMC91C11xFD",
+  NULL, NULL, NULL,
+  NULL, NULL, NULL
+};
+
+/* ------------------ TxBuffer Queue structures ------------------- */
+
+typedef struct {
+  VOID            *Buf;
+  UINTN           Length;
+} MSK_SYSTEM_BUF;
+
+typedef struct {
+  UINTN           Signature;
+  LIST_ENTRY      Link;
+  MSK_SYSTEM_BUF  SystemBuf;
+} MSK_LINKED_SYSTEM_BUF;
+
+#define TX_MBUF_SIGNATURE  SIGNATURE_32 ('t','x','m','b')
+
+/* ------------------ MAC Address Hash Calculations ------------------- */
+
+/*
+**  Generate a hash value from a multicast address
+**
+**  This uses the Ethernet standard CRC32 algorithm
+**
+**  INFO USED:
+**    1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check
+**
+**    2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html
+**
+**    3: http://en.wikipedia.org/wiki/Computation_of_CRC
+*/
+STATIC
+UINT32
+MulticastHash (
+  IN    EFI_MAC_ADDRESS *Mac,
+  IN    UINT32 AddrLen
+  )
+{
+  UINT32 Iter;
+  UINT32 Remainder;
+  UINT32 Crc32;
+  UINT8 *Addr;
+
+  // 0xFFFFFFFF is standard seed for Ethernet
+  Remainder = 0xFFFFFFFF;
+
+  // Generate the remainder byte-by-byte (LSB first)
+  Addr = &Mac->Addr[0];
+  while (AddrLen-- > 0) {
+    Remainder ^= *Addr++;
+    for (Iter = 0; Iter < 8; ++Iter) {
+      // Check if exponent is set
+      if ((Remainder & 1) != 0) {
+        Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;
+      } else {
+        Remainder = (Remainder >> 1) ^ 0;
+      }
+    }
+  }
+
+  // Reverse the bits of the remainder
+  Crc32 = 0;
+  for (Iter = 0; Iter < 32; ++Iter) {
+    Crc32 <<= 1;
+    Crc32 |= Remainder & 1;
+    Remainder >>= 1;
+  }
+  return Crc32;
+}
+
+
+/* ---------------- Banked Register Operations ------------------ */
+
+// Select the proper I/O bank
+STATIC
+VOID
+SelectIoBank (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            Register
+  )
+{
+  UINT8   Bank;
+
+  Bank = RegisterToBank (Register);
+
+  // Select the proper I/O bank
+  if (LanDriver->BankSel != Bank) {
+    MmioWrite16 (LanDriver->IoBase + LAN91X_BANK_OFFSET, Bank);
+    LanDriver->BankSel = Bank;
+  }
+}
+
+// Read a 16-bit I/O-space register
+STATIC
+UINT16
+ReadIoReg16 (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            Register
+  )
+{
+  UINT8   Offset;
+
+  // Select the proper I/O bank
+  SelectIoBank (LanDriver, Register);
+
+  // Read the requested register
+  Offset = RegisterToOffset (Register);
+  return MmioRead16 (LanDriver->IoBase + Offset);
+}
+
+// Write a 16-bit I/O-space register
+STATIC
+UINT16
+WriteIoReg16 (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            Register,
+  UINT16           Value
+  )
+{
+  UINT8   Offset;
+
+  // Select the proper I/O bank
+  SelectIoBank (LanDriver, Register);
+
+  // Write the requested register
+  Offset = RegisterToOffset (Register);
+  return MmioWrite16 (LanDriver->IoBase + Offset, Value);
+}
+
+// Read an 8-bit I/O-space register
+STATIC
+UINT8
+ReadIoReg8 (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            Register
+  )
+{
+  UINT8   Offset;
+
+  // Select the proper I/O bank
+  SelectIoBank (LanDriver, Register);
+
+  // Read the requested register
+  Offset = RegisterToOffset (Register);
+  return MmioRead8 (LanDriver->IoBase + Offset);
+}
+
+// Write an 8-bit I/O-space register
+STATIC
+UINT8
+WriteIoReg8 (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            Register,
+  UINT8            Value
+  )
+{
+  UINT8   Offset;
+
+  // Select the proper I/O bank
+  SelectIoBank (LanDriver, Register);
+
+  // Write the requested register
+  Offset = RegisterToOffset (Register);
+  return MmioWrite8 (LanDriver->IoBase + Offset, Value);
+}
+
+
+/* ---------------- MII/PHY Access Operations ------------------ */
+
+#define LAN91X_MDIO_STALL   1
+
+STATIC
+VOID
+MdioOutput (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            Bits,
+  UINT32           Value
+  )
+{
+  UINT16          MgmtReg;
+  UINT32          Mask;
+
+  MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT);
+  MgmtReg &= ~MGMT_MCLK;
+  MgmtReg |= MGMT_MDOE;
+
+  for (Mask = (1 << (Bits - 1)); Mask != 0; Mask >>= 1) {
+    if ((Value & Mask) != 0) {
+      MgmtReg |= MGMT_MDO;
+    } else {
+      MgmtReg &= ~MGMT_MDO;
+    }
+
+    WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg);
+    gBS->Stall (LAN91X_MDIO_STALL);
+    WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg | MGMT_MCLK);
+    gBS->Stall (LAN91X_MDIO_STALL);
+  }
+}
+#define PHY_OUTPUT_TIME (2 * LAN91X_MDIO_STALL)
+
+STATIC
+UINT32
+MdioInput (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            Bits
+  )
+{
+  UINT16          MgmtReg;
+  UINT32          Mask;
+  UINT32          Value;
+
+  MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT);
+  MgmtReg &= ~(MGMT_MDOE | MGMT_MCLK | MGMT_MDO);
+  WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg);
+
+  Value = 0;
+  for (Mask = (1 << (Bits - 1)); Mask != 0; Mask >>= 1) {
+    if ((ReadIoReg16 (LanDriver, LAN91X_MGMT) & MGMT_MDI) != 0) {
+       Value |= Mask;
+    }
+
+    WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg);
+    gBS->Stall (LAN91X_MDIO_STALL);
+    WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg | MGMT_MCLK);
+    gBS->Stall (LAN91X_MDIO_STALL);
+  }
+
+  return Value;
+}
+#define PHY_INPUT_TIME (2 * LAN91X_MDIO_STALL)
+
+STATIC
+VOID
+MdioIdle (
+  LAN91X_DRIVER   *LanDriver
+  )
+{
+  UINT16          MgmtReg;
+
+  MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT);
+  MgmtReg &= ~(MGMT_MDOE | MGMT_MCLK | MGMT_MDO);
+  WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg);
+}
+
+// Write to a PHY register
+STATIC
+VOID
+WritePhyReg16 (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            RegAd,
+  UINT16           Value
+  )
+{
+  // Bit-bang the MII Serial Frame write operation
+  MdioOutput (LanDriver, 32, 0xffffffff);       // Send 32 Ones as a preamble
+  MdioOutput (LanDriver,  2, 0x01);             // Send Start (01)
+  MdioOutput (LanDriver,  2, 0x01);             // Send Write (01)
+  MdioOutput (LanDriver,  5, LanDriver->PhyAd); // Send PHYAD[4:0]
+  MdioOutput (LanDriver,  5, RegAd);            // Send REGAD[4:0]
+  MdioOutput (LanDriver,  2, 0x02);             // Send TurnAround (10)
+  MdioOutput (LanDriver, 16, Value);            // Write 16 data bits
+
+  // Idle the MDIO bus
+  MdioIdle (LanDriver);
+}
+// Calculate approximate time to write a PHY register in microseconds
+#define PHY_WRITE_TIME  ((32 + 2 + 2 + 5 + 5 + 2 + 16) * PHY_OUTPUT_TIME)
+
+// Read from a PHY register
+STATIC
+UINT16
+ReadPhyReg16 (
+  LAN91X_DRIVER   *LanDriver,
+  UINTN            RegAd
+  )
+{
+  UINT32 Value;
+
+  // Bit-bang the MII Serial Frame read operation
+  MdioOutput (LanDriver, 32, 0xffffffff);       // Send 32 Ones as a preamble
+  MdioOutput (LanDriver,  2, 0x01);             // Send Start (01)
+  MdioOutput (LanDriver,  2, 0x02);             // Send Read (10)
+  MdioOutput (LanDriver,  5, LanDriver->PhyAd); // Send PHYAD[4:0]
+  MdioOutput (LanDriver,  5, RegAd);            // Send REGAD[4:0]
+
+  (VOID)  MdioInput (LanDriver, 2);             // Discard TurnAround bits
+  Value = MdioInput (LanDriver, 16);            // Read 16 data bits
+
+  // Idle the MDIO bus
+  MdioIdle (LanDriver);
+
+  return (Value & 0xffff);
+}
+// Calculate approximate time to read a PHY register in microseconds
+#define PHY_READ_TIME  (((32 + 2 + 2 + 5 + 5) * PHY_OUTPUT_TIME) + \
+                        ((2 + 16) * PHY_INPUT_TIME))
+
+
+/* ---------------- Debug Functions ------------------ */
+
+#ifdef LAN91X_PRINT_REGISTERS
+STATIC
+VOID
+PrintIoRegisters (
+  IN  LAN91X_DRIVER   *LanDriver
+  )
+{
+  UINTN   Bank;
+  UINTN   Offset;
+  UINT16  Value;
+
+  DEBUG((EFI_D_ERROR, "\nLAN91x I/O Register Dump:\n"));
+
+  // Print currrent bank select register
+  Value = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
+  DEBUG((EFI_D_ERROR, "  BankSel: %d  Bank Register %04x (%d)\n",
+      LanDriver->BankSel, Value, Value & 0x0007));
+
+  // Print all I/O registers
+  for (Offset = 0; Offset < 0x0e; Offset += 2) {
+    DEBUG((EFI_D_ERROR, "  %02x:", Offset));
+    for (Bank = 0; Bank <= 3; ++Bank) {
+      DEBUG((EFI_D_ERROR, "  %04x", ReadIoReg16 (LanDriver, MakeRegister (Bank, Offset))));
+    }
+    DEBUG((EFI_D_ERROR, "\n"));
+  }
+}
+
+STATIC
+VOID
+PrintPhyRegisters (
+  IN  LAN91X_DRIVER   *LanDriver
+  )
+{
+  UINTN   RegNum;
+
+  DEBUG((EFI_D_ERROR, "\nLAN91x Phy %d Register Dump:\n", LanDriver->PhyAd));
+
+  // Print all Phy registers
+  for (RegNum = 0; RegNum <= 5; ++RegNum) {
+    DEBUG((EFI_D_ERROR, "  %2d:  %04x\n",
+           RegNum,
+           ReadPhyReg16 (LanDriver, RegNum)
+    ));
+  }
+  for (RegNum = 16; RegNum <= 20; ++RegNum) {
+    DEBUG((EFI_D_ERROR, "  %2d:  %04x\n",
+           RegNum,
+           ReadPhyReg16 (LanDriver, RegNum)
+    ));
+  }
+}
+#endif
+
+#if LAN91X_PRINT_PACKET_HEADERS
+STATIC
+VOID
+PrintIpDgram (
+  IN  CONST VOID  *DstMac,
+  IN  CONST VOID  *SrcMac,
+  IN  CONST VOID  *Proto,
+  IN  CONST VOID  *IpDgram
+  )
+{
+  CONST UINT8   *Ptr;
+  UINT16         SrcPort;
+  UINT16         DstPort;
+
+  Ptr = DstMac;
+  DEBUG((EFI_D_ERROR, "  Dst: %02x-%02x-%02x",
+         Ptr[0], Ptr[1], Ptr[2]));
+  DEBUG((EFI_D_ERROR, "-%02x-%02x-%02x",
+         Ptr[3], Ptr[4], Ptr[5]));
+
+  Ptr = SrcMac;
+  DEBUG((EFI_D_ERROR, "  Src: %02x-%02x-%02x",
+         Ptr[0], Ptr[1], Ptr[2]));
+  DEBUG((EFI_D_ERROR, "-%02x-%02x-%02x",
+         Ptr[3], Ptr[4], Ptr[5]));
+
+  Ptr = Proto;
+  DEBUG((EFI_D_ERROR, "  Proto: %02x%02x\n",
+         Ptr[0], Ptr[1]));
+
+  Ptr = IpDgram;
+  switch (Ptr[9]) {
+  case EFI_IP_PROTO_ICMP:
+    DEBUG((EFI_D_ERROR, "  ICMP"));
+    break;
+  case EFI_IP_PROTO_TCP:
+    DEBUG((EFI_D_ERROR, "  TCP"));
+    break;
+  case EFI_IP_PROTO_UDP:
+    DEBUG((EFI_D_ERROR, "  UDP"));
+    break;
+  default:
+    DEBUG((EFI_D_ERROR, "  IpProto %d\n", Ptr[9]));
+    return;
+  }
+
+  DEBUG((EFI_D_ERROR, "  SrcIp: %d.%d.%d.%d",
+         Ptr[12], Ptr[13], Ptr[14], Ptr[15]));
+  DEBUG((EFI_D_ERROR, "  DstIp: %d.%d.%d.%d",
+         Ptr[16], Ptr[17], Ptr[18], Ptr[19]));
+
+  SrcPort = (Ptr[20] << 8) | Ptr[21];
+  DstPort = (Ptr[22] << 8) | Ptr[23];
+  DEBUG((EFI_D_ERROR, "  SrcPort: %d  DstPort: %d\n", SrcPort, DstPort));
+}
+#endif
+
+
+/* ---------------- PHY Management Operations ----------------- */
+
+STATIC
+EFI_STATUS
+PhyDetect (
+  IN  LAN91X_DRIVER *LanDriver
+  )
+{
+  UINT16  PhyId1;
+  UINT16  PhyId2;
+
+  for (LanDriver->PhyAd = 0x1f; LanDriver->PhyAd >= 0 ; --LanDriver->PhyAd) {
+    PhyId1 = ReadPhyReg16 (LanDriver, PHY_INDEX_ID1);
+    PhyId2 = ReadPhyReg16 (LanDriver, PHY_INDEX_ID2);
+
+    if ((PhyId1 != 0x0000) && (PhyId1 != 0xffff) &&
+        (PhyId2 != 0x0000) && (PhyId2 != 0xffff)) {
+      if ((PhyId1 == 0x0016) && ((PhyId2 & 0xfff0) == 0xf840)) {
+        DEBUG((EFI_D_ERROR, "LAN91x: PHY type LAN83C183 (LAN91C111 Internal)\n"));
+      } else if ((PhyId1 == 0x0282) && ((PhyId2 & 0xfff0) == 0x1c50)) {
+        DEBUG((EFI_D_ERROR, "LAN91x: PHY type LAN83C180\n"));
+      } else {
+        DEBUG((EFI_D_ERROR, "LAN91x: PHY id %04x:%04x\n", PhyId1, PhyId2));
+      }
+      return EFI_SUCCESS;
+    }
+  }
+
+  DEBUG((EFI_D_ERROR, "LAN91x: PHY detection failed\n"));
+  return EFI_NO_MEDIA;
+}
+
+
+// Check the Link Status and take appropriate action
+STATIC
+BOOLEAN
+CheckLinkStatus (
+  IN  LAN91X_DRIVER *LanDriver
+  )
+{
+  UINT16  PhyStatus;
+
+  // Get the PHY Status
+  PhyStatus = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS);
+
+  return (PhyStatus & PHYSTS_LINK_STS) != 0;
+}
+
+
+// Do auto-negotiation
+STATIC
+EFI_STATUS
+PhyAutoNegotiate (
+  IN  LAN91X_DRIVER *LanDriver
+  )
+{
+  UINTN  Retries;
+  UINT16 PhyControl;
+  UINT16 PhyStatus;
+  UINT16 PhyAdvert;
+
+  // If there isn't a PHY, don't try to reset it
+  if (LanDriver->PhyAd == LAN91X_NO_PHY) {
+    return EFI_SUCCESS;
+  }
+
+  // Next check that auto-negotiation is supported
+  PhyStatus = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS);
+  if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {
+    return EFI_SUCCESS;
+  }
+
+  // Translate capabilities to advertise
+  PhyAdvert = PHYANA_CSMA;
+
+  if ((PhyStatus & PHYSTS_10BASET_HDPLX) != 0) {
+    PhyAdvert |= PHYANA_10BASET;
+  }
+  if ((PhyStatus & PHYSTS_10BASET_FDPLX) != 0) {
+    PhyAdvert |= PHYANA_10BASETFD;
+  }
+  if ((PhyStatus & PHYSTS_100BASETX_HDPLX) != 0) {
+    PhyAdvert |= PHYANA_100BASETX;
+  }
+  if ((PhyStatus & PHYSTS_100BASETX_FDPLX) != 0) {
+    PhyAdvert |= PHYANA_100BASETXFD;
+  }
+  if ((PhyStatus & PHYSTS_100BASE_T4) != 0) {
+    PhyAdvert |= PHYANA_100BASET4;
+  }
+
+  // Set the capabilities to advertise
+  WritePhyReg16 (LanDriver, PHY_INDEX_AUTO_NEG_ADVERT, PhyAdvert);
+  (VOID) ReadPhyReg16 (LanDriver, PHY_INDEX_AUTO_NEG_ADVERT);
+
+  // Restart Auto-Negotiation
+  PhyControl = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL);
+  PhyControl &= ~(PHYCR_SPEED_SEL | PHYCR_DUPLEX_MODE);
+  PhyControl |= PHYCR_AUTO_EN | PHYCR_RST_AUTO;
+  WritePhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL, PhyControl);
+
+  // Wait up to 2 seconds for the process to complete
+  Retries = 2000000 / (PHY_READ_TIME + 100);
+  while ((ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0) {
+    if (--Retries == 0) {
+      DEBUG((EFI_D_ERROR, "LAN91x: PHY auto-negotiation timed-out\n"));
+      return EFI_TIMEOUT;
+    }
+    gBS->Stall (100);
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+// Perform PHY software reset
+STATIC
+EFI_STATUS
+PhySoftReset (
+  IN  LAN91X_DRIVER *LanDriver
+  )
+{
+  UINTN     Retries;
+
+  // If there isn't a PHY, don't try to reset it
+  if (LanDriver->PhyAd == LAN91X_NO_PHY) {
+    return EFI_SUCCESS;
+  }
+
+  // Request a PHY reset
+  WritePhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL, PHYCR_RESET);
+
+  // The internal PHY will reset within 50ms. Allow 100ms.
+  Retries = 100000 / (PHY_READ_TIME + 100);
+  while (ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {
+    if (--Retries == 0) {
+      DEBUG((EFI_D_ERROR, "LAN91x: PHY reset timed-out\n"));
+      return EFI_TIMEOUT;
+    }
+    gBS->Stall (100);
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+/* ---------------- General Operations ----------------- */
+
+STATIC
+EFI_MAC_ADDRESS
+GetCurrentMacAddress (
+  IN  LAN91X_DRIVER *LanDriver
+  )
+{
+  UINTN            RegNum;
+  UINT8           *Addr;
+  EFI_MAC_ADDRESS  MacAddress;
+
+  SetMem (&MacAddress, sizeof(MacAddress), 0);
+
+  Addr = &MacAddress.Addr[0];
+  for (RegNum = LAN91X_IAR0; RegNum <= LAN91X_IAR5; ++RegNum) {
+    *Addr = ReadIoReg8 (LanDriver, RegNum);
+    ++Addr;
+  }
+
+  return MacAddress;
+}
+
+STATIC
+EFI_STATUS
+SetCurrentMacAddress (
+  IN  LAN91X_DRIVER   *LanDriver,
+  IN  EFI_MAC_ADDRESS *MacAddress
+  )
+{
+  UINTN            RegNum;
+  UINT8           *Addr;
+
+  Addr = &MacAddress->Addr[0];
+  for (RegNum = LAN91X_IAR0; RegNum <= LAN91X_IAR5; ++RegNum) {
+    WriteIoReg8 (LanDriver, RegNum, *Addr);
+    ++Addr;
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+MmuOperation (
+  IN  LAN91X_DRIVER *LanDriver,
+  IN  UINTN          MmuOp
+  )
+{
+  UINTN   Polls;
+
+  WriteIoReg16 (LanDriver, LAN91X_MMUCR, MmuOp);
+  Polls = 100;
+  while ((ReadIoReg16 (LanDriver, LAN91X_MMUCR) & MMUCR_BUSY) != 0) {
+    if (--Polls == 0) {
+      DEBUG((EFI_D_ERROR, "LAN91x: MMU operation %04x timed-out\n", MmuOp));
+      return EFI_TIMEOUT;
+    }
+    gBS->Stall (LAN91X_STALL);
+  }
+
+  return EFI_SUCCESS;
+}
+
+// Read bytes from the DATA register
+STATIC
+EFI_STATUS
+ReadIoData (
+  IN  LAN91X_DRIVER *LanDriver,
+  IN  VOID          *Buffer,
+  IN  UINTN          BufLen
+  )
+{
+  UINT8     *Ptr;
+
+  Ptr = Buffer;
+  for (; BufLen > 0; --BufLen) {
+    *Ptr = ReadIoReg8 (LanDriver, LAN91X_DATA0);
+    ++Ptr;
+  }
+
+  return EFI_SUCCESS;
+}
+
+// Write bytes to the DATA register
+STATIC
+EFI_STATUS
+WriteIoData (
+  IN  LAN91X_DRIVER *LanDriver,
+  IN  VOID          *Buffer,
+  IN  UINTN          BufLen
+  )
+{
+  UINT8     *Ptr;
+
+  Ptr = Buffer;
+  for (; BufLen > 0; --BufLen) {
+    WriteIoReg8 (LanDriver, LAN91X_DATA0, *Ptr);
+    ++Ptr;
+  }
+
+  return EFI_SUCCESS;
+}
+
+// Disable the interface
+STATIC
+EFI_STATUS
+ChipDisable (
+  IN  LAN91X_DRIVER *LanDriver
+  )
+{
+#ifdef LAN91X_POWER_DOWN
+  UINT16  Val16;
+#endif
+
+  // Stop Rx and Tx operations
+  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR);
+  WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_CLEAR);
+
+#ifdef LAN91X_POWER_DOWN
+  // Power-down the chip
+  Val16 = ReadIoReg16 (LanDriver, LAN91X_CR);
+  Val16 &= ~CR_EPH_POWER_EN;
+  WriteIoReg16 (LanDriver, LAN91X_CR, Val16);
+#endif
+
+  return EFI_SUCCESS;
+}
+
+// Enable the interface
+STATIC
+EFI_STATUS
+ChipEnable (
+  IN  LAN91X_DRIVER *LanDriver
+  )
+{
+#ifdef LAN91X_POWER_DOWN
+  UINT16  Val16;
+
+  // Power-up the chip
+  Val16 = ReadIoReg16 (LanDriver, LAN91X_CR);
+  Val16 |= CR_EPH_POWER_EN;
+  WriteIoReg16 (LanDriver, LAN91X_CR, Val16);
+  gBS->Stall (LAN91X_STALL);
+#endif
+
+  // Start Rx and Tx operations
+  WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_DEFAULT);
+  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_DEFAULT);
+
+  return EFI_SUCCESS;
+}
+
+
+// Perform software reset on the LAN91x
+STATIC
+EFI_STATUS
+SoftReset (
+  IN  LAN91X_DRIVER   *LanDriver
+  )
+{
+  UINT16  Val16;
+
+  // Issue the reset
+  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_SOFT_RST);
+  gBS->Stall (LAN91X_STALL);
+  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR);
+
+  // Set the configuration register
+  WriteIoReg16 (LanDriver, LAN91X_CR, CR_DEFAULT);
+  gBS->Stall (LAN91X_STALL);
+
+  // Stop Rx and Tx
+  WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR);
+  WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_CLEAR);
+
+  // Initialize the Control Register
+  Val16 = ReadIoReg16 (LanDriver, LAN91X_CTR);
+  Val16 |= CTR_AUTO_REL;
+  WriteIoReg16 (LanDriver, LAN91X_CTR, Val16);
+
+  // Reset the MMU
+  MmuOperation (LanDriver, MMUCR_OP_RESET_MMU);
+
+  return EFI_SUCCESS;
+}
+
+/*
+**  Probe()
+**
+**  Validate that there is a LAN91x device.
+**
+*/
+STATIC
+EFI_STATUS
+Probe (
+  IN  LAN91X_DRIVER   *LanDriver
+  )
+{
+  UINT16        Bank;
+  UINT16        Val16;
+  CHAR16 CONST *ChipId;
+  UINTN         ResetTime;
+
+  // First check that the Bank Select register is valid
+  Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
+  if ((Bank & 0xff00) != 0x3300) {
+    DEBUG((EFI_D_ERROR, "LAN91x: signature error: expecting 33xx, read %04x\n", Bank));
+    return EFI_DEVICE_ERROR;
+  }
+
+  // Try reading the revision register next
+  LanDriver->BankSel = 0xff;
+  Val16 = ReadIoReg16 (LanDriver, LAN91X_REV);
+
+  Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET);
+  if ((Bank & 0xff03) != 0x3303) {
+    DEBUG((EFI_D_ERROR, "LAN91x: signature error: expecting 33x3, read %04x\n", Bank));
+    return EFI_DEVICE_ERROR;
+  }
+
+  // Validate the revision register
+  if ((Val16 & 0xff00) != 0x3300) {
+    DEBUG((EFI_D_ERROR, "LAN91x: revision error: expecting 33xx, read %04x\n", Val16));
+    return EFI_DEVICE_ERROR;
+  }
+
+  ChipId = ChipIds[(Val16 >> 4) & 0x0f];
+  if (ChipId == NULL) {
+    DEBUG((EFI_D_ERROR, "LAN91x: unrecognized revision: %04x\n", Val16));
+    return EFI_DEVICE_ERROR;
+  }
+  DEBUG((EFI_D_ERROR, "LAN91x: detected chip %s rev %d\n", ChipId, Val16 & 0xf));
+  LanDriver->Revision = Val16 & 0xff;
+
+  // Reload from EEPROM to get the hardware MAC address
+  WriteIoReg16 (LanDriver, LAN91X_CTR, CTR_RESERVED | CTR_RELOAD);
+  ResetTime = 1000;
+  while ((ReadIoReg16 (LanDriver, LAN91X_CTR) & CTR_RELOAD) != 0) {
+    if (--ResetTime == 0) {
+      DEBUG((EFI_D_ERROR, "LAN91x: reload from EEPROM timed-out\n"));
+      WriteIoReg16 (LanDriver, LAN91X_CTR, CTR_RESERVED);
+      return EFI_DEVICE_ERROR;
+    }
+    gBS->Stall (LAN91X_STALL);
+  }
+
+  // Read and save the Permanent MAC Address
+  LanDriver->SnpMode.PermanentAddress = GetCurrentMacAddress (LanDriver);
+  LanDriver->SnpMode.CurrentAddress = LanDriver->SnpMode.PermanentAddress;
+  DEBUG((EFI_D_ERROR, //EFI_D_NET | EFI_D_INFO,
+         "LAN91x: HW MAC Address: %02x-%02x-%02x-%02x-%02x-%02x\n",
+         LanDriver->SnpMode.PermanentAddress.Addr[0],
+         LanDriver->SnpMode.PermanentAddress.Addr[1],
+         LanDriver->SnpMode.PermanentAddress.Addr[2],
+         LanDriver->SnpMode.PermanentAddress.Addr[3],
+         LanDriver->SnpMode.PermanentAddress.Addr[4],
+         LanDriver->SnpMode.PermanentAddress.Addr[5]
+         ));
+
+  // Reset the device
+  SoftReset (LanDriver);
+
+  // Try to detect a PHY
+  if (LanDriver->Revision > (CHIP_91100 << 4)) {
+    PhyDetect (LanDriver);
+  } else {
+    LanDriver->PhyAd = LAN91X_NO_PHY;
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+
+
+/*------------------ Simple Network Driver entry point functions ------------------*/
+
+// Refer to the Simple Network Protocol section (21.1)
+// in the UEFI 2.3.1 Specification for documentation.
+
+#define ReturnUnlock(s) do { Status = (s); goto exit_unlock; } while(0)
+
+
+/*
+**  UEFI Start() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpStart (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp
+ )
+{
+  EFI_SIMPLE_NETWORK_MODE *Mode;
+  EFI_TPL                  SavedTpl;
+  EFI_STATUS               Status;
+
+  // Check Snp instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+  Mode = Snp->Mode;
+
+  // Check state of the driver
+  switch (Mode->State) {
+  case EfiSimpleNetworkStopped:
+    break;
+  case EfiSimpleNetworkStarted:
+  case EfiSimpleNetworkInitialized:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver already started\n"));
+    ReturnUnlock (EFI_ALREADY_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+
+  // Change state
+  Mode->State = EfiSimpleNetworkStarted;
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+**  UEFI Stop() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpStop (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp
+  )
+{
+  LAN91X_DRIVER *LanDriver;
+  EFI_TPL        SavedTpl;
+  EFI_STATUS     Status;
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // Check state of the driver
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkStarted:
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Stop the Tx and Rx
+  ChipDisable (LanDriver);
+
+  // Change the state
+  Snp->Mode->State = EfiSimpleNetworkStopped;
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+**  UEFI Initialize() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpInitialize (
+  IN  EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
+  IN  UINTN                        RxBufferSize    OPTIONAL,
+  IN  UINTN                        TxBufferSize    OPTIONAL
+  )
+{
+  LAN91X_DRIVER *LanDriver;
+  EFI_TPL        SavedTpl;
+  EFI_STATUS     Status;
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // Check that driver was started but not initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkStarted:
+    break;
+  case EfiSimpleNetworkInitialized:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver already initialized\n"));
+    ReturnUnlock (EFI_SUCCESS);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Initiate a software reset
+  Status = SoftReset (LanDriver);
+  if (EFI_ERROR(Status)) {
+    DEBUG((EFI_D_WARN, "LAN91x: Soft reset failed\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Initiate a PHY reset
+  if (PhySoftReset (LanDriver) < 0) {
+    Snp->Mode->State = EfiSimpleNetworkStopped;
+    DEBUG((EFI_D_WARN, "LAN91x: PHY soft reset timeout\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  }
+
+  // Do auto-negotiation
+  Status = PhyAutoNegotiate (LanDriver);
+  if (EFI_ERROR(Status)) {
+    DEBUG((EFI_D_WARN, "LAN91x: PHY auto-negotiation failed\n"));
+  }
+
+  // Enable the receiver and transmitter
+  ChipEnable (LanDriver);
+
+  // Now acknowledge all interrupts
+  WriteIoReg8 (LanDriver, LAN91X_IST, 0xFF);
+
+  // Declare the driver as initialized
+  Snp->Mode->State = EfiSimpleNetworkInitialized;
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+**  UEFI Reset () function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpReset (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
+  IN        BOOLEAN Verification
+  )
+{
+  LAN91X_DRIVER *LanDriver;
+  EFI_TPL        SavedTpl;
+  EFI_STATUS     Status;
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Initiate a software reset
+  if (EFI_ERROR (SoftReset (LanDriver))) {
+    DEBUG((EFI_D_WARN, "LAN91x: Soft reset failed\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Initiate a PHY reset
+  if (EFI_ERROR (PhySoftReset (LanDriver))) {
+    DEBUG((EFI_D_WARN, "LAN91x: PHY soft reset failed\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Enable the receiver and transmitter
+  Status = ChipEnable (LanDriver);
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+**  UEFI Shutdown () function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpShutdown (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp
+  )
+{
+  LAN91X_DRIVER *LanDriver;
+  EFI_TPL        SavedTpl;
+  EFI_STATUS     Status;
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // First check that driver has already been initialized
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver in stopped state\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Disable the interface
+  Status = ChipDisable (LanDriver);
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+
+/*
+**  UEFI ReceiveFilters() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpReceiveFilters (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
+  IN        UINT32 Enable,
+  IN        UINT32 Disable,
+  IN        BOOLEAN Reset,
+  IN        UINTN NumMfilter          OPTIONAL,
+  IN        EFI_MAC_ADDRESS *Mfilter  OPTIONAL
+  )
+{
+#define MCAST_HASH_BYTES  8
+
+  LAN91X_DRIVER           *LanDriver;
+  EFI_SIMPLE_NETWORK_MODE *SnpMode;
+  EFI_TPL        SavedTpl;
+  EFI_STATUS     Status;
+  UINTN          i;
+  UINT32         Crc;
+  UINT16         RcvCtrl;
+  UINT8          McastHash[MCAST_HASH_BYTES];
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // First check that driver has already been initialized
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+  SnpMode = Snp->Mode;
+
+#ifdef LAN91X_PRINT_RECEIVE_FILTERS
+  DEBUG((EFI_D_ERROR, "LAN91x:SnpReceiveFilters()\n"));
+  DEBUG((EFI_D_ERROR, "  Enable     = %08x\n", Enable));
+  DEBUG((EFI_D_ERROR, "  Disable    = %08x\n", Disable));
+  DEBUG((EFI_D_ERROR, "  Reset      = %d\n",  Reset));
+  DEBUG((EFI_D_ERROR, "  NumMfilter = %d\n",  NumMfilter));
+  for (i = 0; i < NumMfilter; ++i) {
+    DEBUG((EFI_D_ERROR,
+           "    [%2d] = %02x-%02x-%02x-%02x-%02x-%02x\n",
+           i,
+           Mfilter[i].Addr[0],
+           Mfilter[i].Addr[1],
+           Mfilter[i].Addr[2],
+           Mfilter[i].Addr[3],
+           Mfilter[i].Addr[4],
+           Mfilter[i].Addr[5]));
+  }
+#endif
+
+  // Update the Multicast Hash registers
+  if (Reset) {
+    // Clear the hash table
+    SetMem (McastHash, MCAST_HASH_BYTES, 0);
+    SnpMode->MCastFilterCount = 0;
+  } else {
+    // Read the current hash table
+    for (i = 0; i < MCAST_HASH_BYTES; ++i) {
+      McastHash[i] = ReadIoReg8 (LanDriver, LAN91X_MT0 + i);
+    }
+    // Set the new additions
+    for (i = 0; i < NumMfilter; ++i) {
+      Crc = MulticastHash (&Mfilter[i], NET_ETHER_ADDR_LEN);
+      McastHash[(Crc >> 29) & 0x3] |= 1 << ((Crc >> 26) & 0x3);
+    }
+    SnpMode->MCastFilterCount = NumMfilter;
+  }
+  // If the hash registers need updating, write them
+  if (Reset || NumMfilter > 0) {
+    for (i = 0; i < MCAST_HASH_BYTES; ++i) {
+      WriteIoReg8 (LanDriver, LAN91X_MT0 + i, McastHash[i]);
+    }
+  }
+
+  RcvCtrl = ReadIoReg16 (LanDriver, LAN91X_RCR);
+  if ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) {
+    RcvCtrl |= RCR_PRMS;
+    SnpMode->ReceiveFilterSetting |= EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS;
+  }
+  if ((Disable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) {
+    RcvCtrl &= ~RCR_PRMS;
+    SnpMode->ReceiveFilterSetting &= ~EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS;
+  }
+
+  if ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) != 0) {
+    RcvCtrl |= RCR_ALMUL;
+    SnpMode->ReceiveFilterSetting |= EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
+  }
+  if ((Disable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) != 0) {
+    RcvCtrl &= ~RCR_ALMUL;
+    SnpMode->ReceiveFilterSetting &= ~EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
+  }
+  WriteIoReg16 (LanDriver, LAN91X_RCR, RcvCtrl);
+
+  Status = SetCurrentMacAddress (LanDriver, &SnpMode->CurrentAddress);
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+**  UEFI StationAddress() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpStationAddress (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+  IN        BOOLEAN Reset,
+  IN        EFI_MAC_ADDRESS *NewMac
+)
+{
+  LAN91X_DRIVER *LanDriver;
+  EFI_TPL        SavedTpl;
+  EFI_STATUS     Status;
+
+  // Check Snp instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  if (Reset) {
+    Snp->Mode->CurrentAddress = Snp->Mode->PermanentAddress;
+  } else {
+    if (NewMac == NULL) {
+      ReturnUnlock (EFI_INVALID_PARAMETER);
+    }
+    Snp->Mode->CurrentAddress = *NewMac;
+  }
+
+  Status = SetCurrentMacAddress (LanDriver, &Snp->Mode->CurrentAddress);
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+**  UEFI Statistics() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpStatistics (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
+  IN        BOOLEAN Reset,
+  IN  OUT   UINTN *StatSize,
+      OUT   EFI_NETWORK_STATISTICS *Statistics
+  )
+{
+  LAN91X_DRIVER *LanDriver;
+  EFI_TPL        SavedTpl;
+  EFI_STATUS     Status;
+
+  // Check Snp instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Check pointless condition
+  if ((!Reset) && (StatSize == NULL) && (Statistics == NULL)) {
+    return EFI_SUCCESS;
+  }
+
+  // Check the parameters
+  if ((StatSize == NULL) && (Statistics != NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Do a reset if required
+  if (Reset) {
+    ZeroMem (&LanDriver->Stats, sizeof(EFI_NETWORK_STATISTICS));
+  }
+
+  // Check buffer size
+  if (*StatSize < sizeof(EFI_NETWORK_STATISTICS)) {
+    *StatSize = sizeof(EFI_NETWORK_STATISTICS);
+    ReturnUnlock (EFI_BUFFER_TOO_SMALL);
+    goto exit_unlock;
+  }
+
+  // Fill in the statistics
+  CopyMem(&Statistics, &LanDriver->Stats, sizeof(EFI_NETWORK_STATISTICS));
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+**  UEFI MCastIPtoMAC() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpMcastIptoMac (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL* Snp,
+  IN        BOOLEAN IsIpv6,
+  IN        EFI_IP_ADDRESS *Ip,
+      OUT   EFI_MAC_ADDRESS *McastMac
+  )
+{
+  // Check Snp instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Check parameters
+  if ((McastMac == NULL) || (Ip == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Make sure MAC address is empty
+  ZeroMem (McastMac, sizeof(EFI_MAC_ADDRESS));
+
+  // If we need ipv4 address
+  if (!IsIpv6) {
+    // Most significant 25 bits of a multicast HW address are set
+    McastMac->Addr[0] = 0x01;
+    McastMac->Addr[1] = 0x00;
+    McastMac->Addr[2] = 0x5E;
+
+    // Lower 23 bits from ipv4 address
+    McastMac->Addr[3] = (Ip->v4.Addr[1] & 0x7F); // Clear the ms bit (25th bit of MAC must be 0)
+    McastMac->Addr[4] = Ip->v4.Addr[2];
+    McastMac->Addr[5] = Ip->v4.Addr[3];
+  } else {
+    // Most significant 16 bits of multicast v6 HW address are set
+    McastMac->Addr[0] = 0x33;
+    McastMac->Addr[1] = 0x33;
+
+    // lower four octets are taken from ipv6 address
+    McastMac->Addr[2] = Ip->v6.Addr[8];
+    McastMac->Addr[3] = Ip->v6.Addr[9];
+    McastMac->Addr[4] = Ip->v6.Addr[10];
+    McastMac->Addr[5] = Ip->v6.Addr[11];
+  }
+
+  return EFI_SUCCESS;
+}
+
+/*
+**  UEFI NvData() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpNvData (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL* pobj,
+  IN        BOOLEAN read_write,
+  IN        UINTN offset,
+  IN        UINTN buff_size,
+  IN  OUT   VOID *data
+  )
+{
+  DEBUG((EFI_D_ERROR, "LAN91x: Non-volatile storage not supported\n"));
+
+  return EFI_UNSUPPORTED;
+}
+
+
+/*
+**  UEFI GetStatus () function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpGetStatus (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+      OUT   UINT32   *IrqStat   OPTIONAL,
+      OUT   VOID    **TxBuff    OPTIONAL
+  )
+{
+  LAN91X_DRIVER         *LanDriver;
+  EFI_TPL               SavedTpl;
+  EFI_STATUS            Status;
+  BOOLEAN               MediaPresent;
+  UINT8                 IstReg;
+  MSK_LINKED_SYSTEM_BUF *LinkedTXRecycleBuff;
+
+  // Check preliminaries
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Arbitrarily set the interrupt status to 0
+  if (IrqStat != NULL) {
+    *IrqStat = 0;
+    IstReg = ReadIoReg8 (LanDriver, LAN91X_IST);
+    if ((IstReg & IST_RCV) != 0) {
+      *IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
+    }
+    if ((IstReg & IST_TX) != 0) {
+      *IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
+    }
+  }
+
+  // Pass back the completed buffer address
+  // The transmit buffer status is not read when TxBuf is NULL
+  if (TxBuff != NULL) {
+    *((UINT8 **) TxBuff) = (UINT8 *) 0;
+    if( !IsListEmpty (&LanDriver->TransmitQueueHead))
+    {
+      LinkedTXRecycleBuff = CR (GetFirstNode (&LanDriver->TransmitQueueHead), MSK_LINKED_SYSTEM_BUF, Link, TX_MBUF_SIGNATURE);
+      if(LinkedTXRecycleBuff != NULL) {
+        *TxBuff = LinkedTXRecycleBuff->SystemBuf.Buf;
+        RemoveEntryList (&LinkedTXRecycleBuff->Link);
+        FreePool (LinkedTXRecycleBuff);
+      }
+    }
+  }
+
+  // Update the media status
+  MediaPresent = CheckLinkStatus (LanDriver);
+  if (MediaPresent != Snp->Mode->MediaPresent) {
+    DEBUG((EFI_D_WARN, "LAN91x: Link %s\n", MediaPresent ? L"up" : L"down"));
+  }
+  Snp->Mode->MediaPresent = MediaPresent;
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+
+/*
+**  UEFI Transmit() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpTransmit (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+  IN        UINTN            HdrSize,
+  IN        UINTN            BufSize,
+  IN        VOID            *BufAddr,
+  IN        EFI_MAC_ADDRESS *SrcAddr    OPTIONAL,
+  IN        EFI_MAC_ADDRESS *DstAddr    OPTIONAL,
+  IN        UINT16          *Protocol   OPTIONAL
+  )
+{
+  LAN91X_DRIVER   *LanDriver;
+  EFI_TPL          SavedTpl;
+  EFI_STATUS       Status;
+  UINT8           *Ptr;
+  UINTN            Len;
+  UINTN            MmuPages;
+  UINTN            Retries;
+  UINT16           Proto;
+  UINT8            PktNum;
+  MSK_LINKED_SYSTEM_BUF   *LinkedTXRecycleBuff;
+
+
+  // Check preliminaries
+  if ((Snp == NULL) || (BufAddr == NULL)) {
+    DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): NULL Snp (%p) or BufAddr (%p)\n",
+        Snp, BufAddr));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Ensure header is correct size if non-zero
+  if (HdrSize != 0) {
+    if (HdrSize != Snp->Mode->MediaHeaderSize) {
+      DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): Invalid HdrSize %d\n", HdrSize));
+      ReturnUnlock (EFI_INVALID_PARAMETER);
+    }
+
+    if ((DstAddr == NULL) || (Protocol == NULL)) {
+      DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): NULL DstAddr %p or Protocol %p\n",
+          DstAddr, Protocol));
+      ReturnUnlock (EFI_INVALID_PARAMETER);
+    }
+  }
+
+  // Before transmitting check the link status
+  if (!Snp->Mode->MediaPresent) {
+    DEBUG((EFI_D_WARN, "LAN91x: SnpTransmit(): Link not ready\n"));
+    ReturnUnlock (EFI_NOT_READY);
+  }
+
+  // Calculate the request size in 256-byte "pages" minus 1
+  // The 91C111 ignores this, but some older devices need it.
+  MmuPages = ((BufSize & ~1) + LAN91X_PKT_OVERHEAD - 1) >> 8;
+  if (MmuPages > 7) {
+    DEBUG((EFI_D_WARN, "LAN91x: Tx buffer too large (%d bytes)\n", BufSize));
+    LanDriver->Stats.TxOversizeFrames += 1;
+    LanDriver->Stats.TxDroppedFrames += 1;
+    ReturnUnlock (EFI_BAD_BUFFER_SIZE);
+  }
+
+  // Request allocation of a transmit buffer
+  Status = MmuOperation (LanDriver, MMUCR_OP_TX_ALLOC | MmuPages);
+  if (EFI_ERROR (Status)) {
+    DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer request failure: %d\n", Status));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Wait for allocation request completion
+  Retries = LAN91X_MEMORY_ALLOC_POLLS;
+  while ((ReadIoReg8 (LanDriver, LAN91X_IST) & IST_ALLOC) == 0) {
+    if (--Retries == 0) {
+      DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer allocation timeout\n"));
+      ReturnUnlock (EFI_TIMEOUT);
+    }
+  }
+
+  // Check for successful allocation
+  PktNum = ReadIoReg8 (LanDriver, LAN91X_ARR);
+  if ((PktNum & ARR_FAILED) != 0) {
+    DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer allocation failure: %02x\n", PktNum));
+    ReturnUnlock (EFI_NOT_READY);
+  }
+  PktNum &= ARR_PACKET;
+
+  // Check for the nature of the frame
+  // If no destination address, it's ARP broadcast
+  if(DstAddr != NULL)
+  {
+    if (DstAddr->Addr[0] == 0xFF) {
+      LanDriver->Stats.TxBroadcastFrames += 1;
+    } else if ((DstAddr->Addr[0] & 0x1) == 1) {
+      LanDriver->Stats.TxMulticastFrames += 1;
+    } else {
+      LanDriver->Stats.TxUnicastFrames += 1;
+    }
+  } else {
+    LanDriver->Stats.TxBroadcastFrames += 1;
+  }
+
+  // Set the Packet Number and Pointer registers
+  WriteIoReg8 (LanDriver, LAN91X_PNR, PktNum);
+  WriteIoReg16 (LanDriver, LAN91X_PTR, PTR_AUTO_INCR);
+
+  // Set up mutable buffer information variables
+  Ptr = BufAddr;
+  Len = BufSize;
+
+  // Write Status and Byte Count first
+  WriteIoReg16 (LanDriver, LAN91X_DATA0, 0);
+  WriteIoReg16 (LanDriver, LAN91X_DATA0, (Len + LAN91X_PKT_OVERHEAD) & BCW_COUNT);
+
+  // This packet may come with a preconfigured Ethernet header.
+  // If not, we need to construct one from optional parameters.
+  if (HdrSize) {
+
+    // Write the destination address
+    WriteIoData (LanDriver, DstAddr, NET_ETHER_ADDR_LEN);
+
+    // Write the Source Address
+    if (SrcAddr != NULL) {
+      WriteIoData (LanDriver, SrcAddr, NET_ETHER_ADDR_LEN);
+    } else {
+      WriteIoData (LanDriver, &LanDriver->SnpMode.CurrentAddress, NET_ETHER_ADDR_LEN);
+    }
+
+    // Write the Protocol word
+    Proto = HTONS (*Protocol);
+    WriteIoReg16 (LanDriver, LAN91X_DATA0, Proto);
+
+    // Adjust the data start and length
+    Ptr += sizeof(ETHER_HEAD);
+    Len -= sizeof(ETHER_HEAD);
+  }
+
+  // Copy the remainder data buffer, except the odd byte
+  WriteIoData (LanDriver, Ptr, Len & ~1);
+  Ptr += Len & ~1;
+  Len &= 1;
+
+  // Write the Packet Control Word and odd byte
+  WriteIoReg16 (LanDriver, LAN91X_DATA0,
+      (Len != 0) ? (PCW_ODD | PCW_CRC | *Ptr) : PCW_CRC);
+
+  // Release the packet for transmission
+  Status = MmuOperation (LanDriver, MMUCR_OP_TX_PUSH);
+  if (EFI_ERROR (Status)) {
+    DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer release failure: %d\n", Status));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Update the Tx statistics
+  LanDriver->Stats.TxTotalBytes += BufSize;
+  LanDriver->Stats.TxGoodFrames += 1;
+
+  // Update the Tx Buffer cache
+  LinkedTXRecycleBuff = AllocateZeroPool (sizeof (MSK_LINKED_SYSTEM_BUF));
+  if (LinkedTXRecycleBuff == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  LinkedTXRecycleBuff->Signature = TX_MBUF_SIGNATURE;
+  //
+  // Add the passed Buffer to the transmit queue. Don't copy.
+  //
+  LinkedTXRecycleBuff->SystemBuf.Buf = BufAddr;
+  LinkedTXRecycleBuff->SystemBuf.Length = BufSize;
+  InsertTailList (&LanDriver->TransmitQueueHead, &LinkedTXRecycleBuff->Link);
+
+  Status = EFI_SUCCESS;
+
+  // Dump the packet header
+#if LAN91X_PRINT_PACKET_HEADERS
+  Ptr = BufAddr;
+  DEBUG((EFI_D_ERROR, "LAN91X:SnpTransmit()\n"));
+  DEBUG((EFI_D_ERROR, "  HdrSize: %d, SrcAddr: %p, Length: %d, Last byte: %02x\n",
+         HdrSize, SrcAddr, BufSize, Ptr[BufSize - 1]));
+  PrintIpDgram (
+      (HdrSize == 0) ? (EFI_MAC_ADDRESS *)&Ptr[0] : DstAddr,
+      (HdrSize == 0) ? (EFI_MAC_ADDRESS *)&Ptr[6] : (SrcAddr != NULL) ? SrcAddr : &LanDriver->SnpMode.CurrentAddress,
+      (HdrSize == 0) ? (UINT16 *)&Ptr[12] : &Proto,
+      &Ptr[14]
+      );
+#endif
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+
+/*
+**  UEFI Receive() function
+**
+*/
+EFI_STATUS
+EFIAPI
+SnpReceive (
+  IN        EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+      OUT   UINTN           *HdrSize      OPTIONAL,
+  IN  OUT   UINTN           *BuffSize,
+      OUT   VOID            *Data,
+      OUT   EFI_MAC_ADDRESS *SrcAddr      OPTIONAL,
+      OUT   EFI_MAC_ADDRESS *DstAddr      OPTIONAL,
+      OUT   UINT16 *Protocol              OPTIONAL
+  )
+{
+  EFI_TPL        SavedTpl;
+  EFI_STATUS     Status;
+  LAN91X_DRIVER *LanDriver;
+  UINT8         *DataPtr;
+  UINT16         PktStatus;
+  UINT16         PktLength;
+  UINT16         PktControl;
+  UINT8          IstReg;
+
+  // Check preliminaries
+  if ((Snp == NULL) || (Data == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (LAN91X_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n",
+          (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Check for Rx Overrun
+  IstReg = ReadIoReg8 (LanDriver, LAN91X_IST);
+  if ((IstReg & IST_RX_OVRN) != 0) {
+    LanDriver->Stats.RxTotalFrames += 1;
+    LanDriver->Stats.RxDroppedFrames += 1;
+    WriteIoReg8 (LanDriver, LAN91X_IST, IST_RX_OVRN);
+    DEBUG((EFI_D_WARN, "LAN91x: Receiver overrun\n"));
+  }
+
+  // Check for Rx data available
+  if ((IstReg & IST_RCV) == 0) {
+    ReturnUnlock (EFI_NOT_READY);
+  }
+
+  // Configure the PTR register for reading
+  WriteIoReg16 (LanDriver, LAN91X_PTR, PTR_RCV | PTR_AUTO_INCR | PTR_READ);
+
+  // Read the Packet Status and Packet Length words
+  PktStatus = ReadIoReg16 (LanDriver, LAN91X_DATA0);
+  PktLength = ReadIoReg16 (LanDriver, LAN91X_DATA0) & BCW_COUNT;
+
+  // Check for valid received packet
+  if ((PktStatus == 0) && (PktLength == 0)) {
+    DEBUG((EFI_D_WARN, "LAN91x: Received zero-length packet. IST=%04x\n", IstReg));
+    ReturnUnlock (EFI_NOT_READY);
+  }
+  LanDriver->Stats.RxTotalFrames += 1;
+
+  // Check if we got a CRC error
+  if ((PktStatus & RX_BAD_CRC) != 0) {
+    DEBUG((EFI_D_WARN, "LAN91x: Received frame CRC error\n"));
+    LanDriver->Stats.RxCrcErrorFrames += 1;
+    LanDriver->Stats.RxDroppedFrames += 1;
+    Status = EFI_DEVICE_ERROR;
+    goto exit_release;
+  }
+
+  // Check if we got a too-short frame
+  if ((PktStatus & RX_TOO_SHORT) != 0) {
+    DEBUG((EFI_D_WARN, "LAN91x: Received frame too short (%d bytes)\n", PktLength));
+    LanDriver->Stats.RxUndersizeFrames += 1;
+    LanDriver->Stats.RxDroppedFrames += 1;
+    Status = EFI_DEVICE_ERROR;
+    goto exit_release;
+  }
+
+   // Check if we got a too-long frame
+  if ((PktStatus & RX_TOO_LONG) != 0) {
+    DEBUG((EFI_D_WARN, "LAN91x: Received frame too long (%d bytes)\n", PktLength));
+    LanDriver->Stats.RxOversizeFrames += 1;
+    LanDriver->Stats.RxDroppedFrames += 1;
+    Status = EFI_DEVICE_ERROR;
+    goto exit_release;
+  }
+
+   // Check if we got an alignment error
+  if ((PktStatus & RX_ALGN_ERR) != 0) {
+    DEBUG((EFI_D_WARN, "LAN91x: Received frame alignment error\n"));
+    // Don't seem to keep track of these specifically
+    LanDriver->Stats.RxDroppedFrames += 1;
+    Status = EFI_DEVICE_ERROR;
+    goto exit_release;
+  }
+
+  // Classify the received fram
+  if ((PktStatus & RX_MULTICAST) != 0) {
+    LanDriver->Stats.RxMulticastFrames += 1;
+  } else if ((PktStatus & RX_BROADCAST) != 0) {
+    LanDriver->Stats.RxBroadcastFrames += 1;
+  } else {
+    LanDriver->Stats.RxUnicastFrames += 1;
+  }
+
+  // Calculate the received packet data length
+  PktLength -= LAN91X_PKT_OVERHEAD;
+  if ((PktStatus & RX_ODD_FRAME) != 0) {
+    PktLength += 1;
+  }
+
+  // Check buffer size
+  if (*BuffSize < PktLength) {
+    DEBUG((EFI_D_WARN, "LAN91x: Receive buffer too small for packet (%d < %d)\n",
+        *BuffSize, PktLength));
+    *BuffSize = PktLength;
+    Status = EFI_BUFFER_TOO_SMALL;
+    goto exit_release;
+  }
+
+  // Transfer the data bytes
+  DataPtr = Data;
+  ReadIoData (LanDriver, DataPtr, PktLength & ~0x0001);
+
+  // Read the PktControl and Odd Byte from the FIFO
+  PktControl = ReadIoReg16 (LanDriver, LAN91X_DATA0);
+  if ((PktControl & PCW_ODD) != 0) {
+    DataPtr[PktLength - 1] = PktControl & PCW_ODD_BYTE;
+  }
+
+  // Update buffer size
+  *BuffSize = PktLength;
+
+  if (HdrSize != NULL) {
+    *HdrSize = LanDriver->SnpMode.MediaHeaderSize;
+  }
+
+  // Extract the destination address
+  if (DstAddr != NULL) {
+    CopyMem (DstAddr, &DataPtr[0], NET_ETHER_ADDR_LEN);
+  }
+
+  // Get the source address
+  if (SrcAddr != NULL) {
+    CopyMem (SrcAddr, &DataPtr[6], NET_ETHER_ADDR_LEN);
+  }
+
+  // Get the protocol
+  if (Protocol != NULL) {
+    *Protocol = NTOHS (*(UINT16*)(&DataPtr[12]));
+  }
+
+  // Update the Rx statistics
+  LanDriver->Stats.RxTotalBytes += PktLength;
+  LanDriver->Stats.RxGoodFrames += 1;
+  Status = EFI_SUCCESS;
+
+#if LAN91X_PRINT_PACKET_HEADERS
+  // Dump the packet header
+  DEBUG((EFI_D_ERROR, "LAN91X:SnpReceive()\n"));
+  DEBUG((EFI_D_ERROR, "  HdrSize: %p, SrcAddr: %p, DstAddr: %p, Protocol: %p\n",
+         HdrSize, SrcAddr, DstAddr, Protocol));
+  DEBUG((EFI_D_ERROR, "  Length: %d, Last byte: %02x\n", PktLength, DataPtr[PktLength - 1]));
+  PrintIpDgram (&DataPtr[0], &DataPtr[6], &DataPtr[12], &DataPtr[14]);
+#endif
+
+  // Release the FIFO buffer
+exit_release:
+  MmuOperation (LanDriver, MMUCR_OP_RX_POP_REL);
+
+  // Restore TPL and return
+exit_unlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+
+/*------------------ Driver Execution Environment main entry point ------------------*/
+
+/*
+**  Entry point for the LAN91x driver
+**
+*/
+EFI_STATUS
+Lan91xDxeEntry (
+  IN EFI_HANDLE Handle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS Status;
+  LAN91X_DRIVER *LanDriver;
+  EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
+  EFI_SIMPLE_NETWORK_MODE *SnpMode;
+  LAN91X_DEVICE_PATH *Lan91xPath;
+
+  // The PcdLan91xDxeBaseAddress PCD must be defined
+  ASSERT(PcdGet32 (PcdLan91xDxeBaseAddress) != 0);
+
+  // Allocate Resources
+  LanDriver = AllocateZeroPool (sizeof(LAN91X_DRIVER));
+  Lan91xPath = AllocateCopyPool (sizeof(LAN91X_DEVICE_PATH), &Lan91xPathTemplate);
+
+  // Initialize I/O Space access info
+  LanDriver->IoBase = PcdGet32 (PcdLan91xDxeBaseAddress);
+  LanDriver->PhyAd = LAN91X_NO_PHY;
+  LanDriver->BankSel = 0xff;
+
+  // Initialize pointers
+  Snp = &(LanDriver->Snp);
+  SnpMode = &(LanDriver->SnpMode);
+  Snp->Mode = SnpMode;
+
+  // Set the signature of the LAN Driver structure
+  LanDriver->Signature = LAN91X_SIGNATURE;
+
+  // Probe the device
+  Status = Probe (LanDriver);
+  if (EFI_ERROR(Status)) {
+    DEBUG((EFI_D_ERROR, "LAN91x:Lan91xDxeEntry(): Probe failed with status %d\n", Status));
+    return Status;
+  }
+
+#ifdef LAN91X_PRINT_REGISTERS
+  PrintIoRegisters (LanDriver);
+  PrintPhyRegisters (LanDriver);
+#endif
+
+  // Initialize transmit queue
+  InitializeListHead (&LanDriver->TransmitQueueHead);
+
+  // Assign fields and func pointers
+  Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
+  Snp->WaitForPacket = NULL;
+  Snp->Initialize = SnpInitialize;
+  Snp->Start = SnpStart;
+  Snp->Stop = SnpStop;
+  Snp->Reset = SnpReset;
+  Snp->Shutdown = SnpShutdown;
+  Snp->ReceiveFilters = SnpReceiveFilters;
+  Snp->StationAddress = SnpStationAddress;
+  Snp->Statistics = SnpStatistics;
+  Snp->MCastIpToMac = SnpMcastIptoMac;
+  Snp->NvData = SnpNvData;
+  Snp->GetStatus = SnpGetStatus;
+  Snp->Transmit = SnpTransmit;
+  Snp->Receive = SnpReceive;
+
+  // Fill in simple network mode structure
+  SnpMode->State = EfiSimpleNetworkStopped;
+  SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN;    // HW address is 6 bytes
+  SnpMode->MediaHeaderSize = sizeof(ETHER_HEAD);  // Size of an Ethernet header
+  SnpMode->MaxPacketSize = EFI_PAGE_SIZE;         // Ethernet Frame (with VLAN tag +4 bytes)
+
+  // Supported receive filters
+  SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+                               EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+                               EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |
+                               EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |
+                               EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
+
+  // Initially-enabled receive filters
+  SnpMode->ReceiveFilterSetting = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+                                  EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+                                  EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST;
+
+  // LAN91x has 64bit hash table. We can filter an infinite MACs, but
+  // higher-level software must filter out any hash collisions.
+  SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
+  SnpMode->MCastFilterCount = 0;
+  ZeroMem (&SnpMode->MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));
+
+  // Set the interface type (1: Ethernet or 6: IEEE 802 Networks)
+  SnpMode->IfType = NET_IFTYPE_ETHERNET;
+
+  // Mac address is changeable
+  SnpMode->MacAddressChangeable = TRUE;
+
+  // We can only transmit one packet at a time
+  SnpMode->MultipleTxSupported = FALSE;
+
+  // MediaPresent checks for cable connection and partner link
+  SnpMode->MediaPresentSupported = TRUE;
+  SnpMode->MediaPresent = FALSE;
+
+  //  Set broadcast address
+  SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
+
+  // Assign fields for device path
+  Lan91xPath->Lan91x.MacAddress = SnpMode->PermanentAddress;
+  Lan91xPath->Lan91x.IfType = SnpMode->IfType;
+
+  // Initialise the protocol
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &LanDriver->ControllerHandle,
+                  &gEfiSimpleNetworkProtocolGuid, Snp,
+                  &gEfiDevicePathProtocolGuid, Lan91xPath,
+                  NULL
+                  );
+
+  // Say what the status of loading the protocol structure is
+  if (EFI_ERROR(Status)) {
+    FreePool (LanDriver);
+  }
+
+  return Status;
+}
diff --git a/Drivers/Net/Lan91xDxe/Lan91xDxe.inf b/Drivers/Net/Lan91xDxe/Lan91xDxe.inf
index 0838a3d..f62a7d1 100644
--- a/Drivers/Net/Lan91xDxe/Lan91xDxe.inf
+++ b/Drivers/Net/Lan91xDxe/Lan91xDxe.inf
@@ -1,58 +1,58 @@
-#/** @file
-#  INF file for the SMSC LAN91x series Network Controller Driver.
-#
-#  Copyright (c) 2013 Linaro.org
-#
-#  Derived from the LAN9118 driver. Original sources
-#  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials are licensed and
-#  made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license
-#  may be found at: http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010006
-  BASE_NAME                      = Lan91xDxe
-  FILE_GUID                      = 5c12ea2f-9897-48af-8138-25f4ce6ff8d6
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 0.1
-  ENTRY_POINT                    = Lan91xDxeEntry
-
-[Sources.common]
-  Lan91xDxe.c
-  Lan91xDxeHw.h
-
-[Packages]
-  OpenPlatformPkg/Drivers/Net/Lan91xDxe/Lan91xDxe.dec
-  NetworkPkg/NetworkPkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  MdePkg/MdePkg.dec
-
-[LibraryClasses]
-  BaseLib
-  UefiLib
-  NetLib
-  UefiDriverEntryPoint
-  BaseMemoryLib
-  ArmLib
-  IoLib
-  TimerLib
-  DevicePathLib
-
-[Protocols]
-  gEfiSimpleNetworkProtocolGuid
-  gEfiMetronomeArchProtocolGuid
-  gEfiPxeBaseCodeProtocolGuid
-  gEfiDevicePathProtocolGuid
-
-[FixedPcd]
-  gLan91xDxeTokenSpaceGuid.PcdLan91xDxeBaseAddress
-
-[Depex]
-  TRUE
+#/** @file
+#  INF file for the SMSC LAN91x series Network Controller Driver.
+#
+#  Copyright (c) 2013 Linaro.org
+#
+#  Derived from the LAN9118 driver. Original sources
+#  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and
+#  made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license
+#  may be found at: http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010006
+  BASE_NAME                      = Lan91xDxe
+  FILE_GUID                      = 5c12ea2f-9897-48af-8138-25f4ce6ff8d6
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 0.1
+  ENTRY_POINT                    = Lan91xDxeEntry
+
+[Sources.common]
+  Lan91xDxe.c
+  Lan91xDxeHw.h
+
+[Packages]
+  OpenPlatformPkg/Drivers/Net/Lan91xDxe/Lan91xDxe.dec
+  NetworkPkg/NetworkPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
+  UefiLib
+  NetLib
+  UefiDriverEntryPoint
+  BaseMemoryLib
+  ArmLib
+  IoLib
+  TimerLib
+  DevicePathLib
+
+[Protocols]
+  gEfiSimpleNetworkProtocolGuid
+  gEfiMetronomeArchProtocolGuid
+  gEfiPxeBaseCodeProtocolGuid
+  gEfiDevicePathProtocolGuid
+
+[FixedPcd]
+  gLan91xDxeTokenSpaceGuid.PcdLan91xDxeBaseAddress
+
+[Depex]
+  TRUE
diff --git a/Drivers/Net/Lan91xDxe/Lan91xDxeHw.h b/Drivers/Net/Lan91xDxe/Lan91xDxeHw.h
index 9274ba0..1b05c54 100644
--- a/Drivers/Net/Lan91xDxe/Lan91xDxeHw.h
+++ b/Drivers/Net/Lan91xDxe/Lan91xDxeHw.h
@@ -1,278 +1,278 @@
-/** @file
-*  SMSC LAN91x series Network Controller Driver.
-*
-*  Copyright (c) 2013 Linaro.org
-*
-*  This program and the accompanying materials are licensed and
-*  made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license
-*  may be found at: http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __LAN91XDXEHW_H__
-#define __LAN91XDXEHW_H__
-
-#include <Base.h>
-
-#define MakeRegister(Bank, Offset)  (((Bank) << 8) | (Offset))
-#define RegisterToBank(Register)    (((Register) >> 8) & 0x07)
-#define RegisterToOffset(Register)  ((Register) & 0x0f)
-
-/*---------------------------------------------------------------------------------------------------------------------
-
-	SMSC LAN91x Registers
-
----------------------------------------------------------------------------------------------------------------------*/
-#define LAN91X_BANK_OFFSET      0xe                     // Bank Select Register (all banks)
-
-#define LAN91X_TCR      MakeRegister (0, 0x0)           // Transmit Control Register
-#define LAN91X_EPHSR    MakeRegister (0, 0x2)           // EPH Status Register
-#define LAN91X_RCR      MakeRegister (0, 0x4)           // Receive Control Register
-#define LAN91X_ECR      MakeRegister (0, 0x6)           // Counter Register
-#define LAN91X_MIR      MakeRegister (0, 0x8)           // Memory Information Register
-#define LAN91X_RPCR     MakeRegister (0, 0xa)           // Receive/Phy Control Register
-
-#define LAN91X_CR       MakeRegister (1, 0x0)           // Configuration Register
-#define LAN91X_BAR      MakeRegister (1, 0x2)           // Base Address Register
-#define LAN91X_IAR0     MakeRegister (1, 0x4)           // Individual Address Register 0
-#define LAN91X_IAR1     MakeRegister (1, 0x5)           // Individual Address Register 1
-#define LAN91X_IAR2     MakeRegister (1, 0x6)           // Individual Address Register 2
-#define LAN91X_IAR3     MakeRegister (1, 0x7)           // Individual Address Register 3
-#define LAN91X_IAR4     MakeRegister (1, 0x8)           // Individual Address Register 4
-#define LAN91X_IAR5     MakeRegister (1, 0x9)           // Individual Address Register 5
-#define LAN91X_GPR      MakeRegister (1, 0xa)           // General Purpose Register
-#define LAN91X_CTR      MakeRegister (1, 0xc)           // Control Register
-
-#define LAN91X_MMUCR    MakeRegister (2, 0x0)           // MMU Command Register
-#define LAN91X_PNR      MakeRegister (2, 0x2)           // Packet Number Register
-#define LAN91X_ARR      MakeRegister (2, 0x3)           // Allocation Result Register
-#define LAN91X_FIFO     MakeRegister (2, 0x4)           // FIFO Ports Register
-#define LAN91X_PTR      MakeRegister (2, 0x6)           // Pointer Register
-#define LAN91X_DATA0    MakeRegister (2, 0x8)           // Data Register 0
-#define LAN91X_DATA1    MakeRegister (2, 0x9)           // Data Register 1
-#define LAN91X_DATA2    MakeRegister (2, 0xa)           // Data Register 2
-#define LAN91X_DATA3    MakeRegister (2, 0xb)           // Data Register 3
-#define LAN91X_IST      MakeRegister (2, 0xc)           // Interrupt Status Register
-#define LAN91X_MSK      MakeRegister (2, 0xd)           // Interrupt Mask Register
-
-#define LAN91X_MT0      MakeRegister (3, 0x0)           // Multicast Table Register 0
-#define LAN91X_MT1      MakeRegister (3, 0x1)           // Multicast Table Register 1
-#define LAN91X_MT2      MakeRegister (3, 0x2)           // Multicast Table Register 2
-#define LAN91X_MT3      MakeRegister (3, 0x3)           // Multicast Table Register 3
-#define LAN91X_MT4      MakeRegister (3, 0x4)           // Multicast Table Register 4
-#define LAN91X_MT5      MakeRegister (3, 0x5)           // Multicast Table Register 5
-#define LAN91X_MT6      MakeRegister (3, 0x6)           // Multicast Table Register 6
-#define LAN91X_MT7      MakeRegister (3, 0x7)           // Multicast Table Register 7
-#define LAN91X_MGMT     MakeRegister (3, 0x8)           // Management Interface Register
-#define LAN91X_REV      MakeRegister (3, 0xa)           // Revision Register
-#define LAN91X_RCV      MakeRegister (3, 0xc)           // RCV Register
-
-// Transmit Control Register Bits
-#define TCR_TXENA       BIT0
-#define TCR_LOOP        BIT1
-#define TCR_FORCOL      BIT2
-#define TCR_PAD_EN      BIT7
-#define TCR_NOCRC       BIT8
-#define TCR_MON_CSN     BIT10
-#define TCR_FDUPLX      BIT11
-#define TCR_STP_SQET    BIT12
-#define TCR_EPH_LOOP    BIT13
-#define TCR_SWFDUP      BIT15
-
-#define TCR_DEFAULT     (TCR_TXENA | TCR_PAD_EN)
-#define TCR_CLEAR       0x0
-
-// EPH Status Register Bits
-#define EPHSR_TX_SUC    BIT0
-#define EPHSR_SNGLCOL   BIT1
-#define EPHSR_MULCOL    BIT2
-#define EPHSR_LTX_MULT  BIT3
-#define EPHSR_16COL     BIT4
-#define EPHSR_SQET      BIT5
-#define EPHSR_LTX_BRD   BIT6
-#define EPHSR_TX_DEFR   BIT7
-#define EPHSR_LATCOL    BIT9
-#define EPHSR_LOST_CARR BIT10
-#define EPHSR_EXC_DEF   BIT11
-#define EPHSR_CTR_ROL   BIT12
-#define EPHSR_LINK_OK   BIT14
-
-// Receive Control Register Bits
-#define RCR_RX_ABORT    BIT0
-#define RCR_PRMS        BIT1
-#define RCR_ALMUL       BIT2
-#define RCR_RXEN        BIT8
-#define RCR_STRIP_CRC   BIT9
-#define RCR_ABORT_ENB   BIT13
-#define RCR_FILT_CAR    BIT14
-#define RCR_SOFT_RST    BIT15
-
-#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
-#define RCR_CLEAR       0x0
-
-// Receive/Phy Control Register Bits
-#define RPCR_LS0B       BIT2
-#define RPCR_LS1B       BIT3
-#define RPCR_LS2B       BIT4
-#define RPCR_LS0A       BIT5
-#define RPCR_LS1A       BIT6
-#define RPCR_LS2A       BIT7
-#define RPCR_ANEG       BIT11
-#define RPCR_DPLX       BIT12
-#define RPCR_SPEED      BIT13
-
-// Configuration Register Bits
-#define CR_EXT_PHY      BIT9
-#define CR_GPCNTRL      BIT10
-#define CR_NO_WAIT      BIT12
-#define CR_EPH_POWER_EN BIT15
-
-#define CR_DEFAULT      (CR_EPH_POWER_EN | CR_NO_WAIT)
-
-// Control Register Bits
-#define CTR_STORE       BIT0
-#define CTR_RELOAD      BIT1
-#define CTR_EEPROM_SEL  BIT2
-#define CTR_TE_ENABLE   BIT5
-#define CTR_CR_ENABLE   BIT6
-#define CTR_LE_ENABLE   BIT7
-#define CTR_AUTO_REL    BIT11
-#define CTR_RCV_BAD     BIT14
-
-#define	CTR_RESERVED	(BIT12 | BIT9 | BIT4)
-#define CTR_DEFAULT     (CTR_RESERVED | CTR_AUTO_REL)
-
-// MMU Command Register Bits
-#define MMUCR_BUSY      BIT0
-
-// MMU Command Register Operaction Codes
-#define MMUCR_OP_NOOP           (0 << 5)        // No operation
-#define MMUCR_OP_TX_ALLOC       (1 << 5)        // Allocate memory for TX
-#define MMUCR_OP_RESET_MMU      (2 << 5)        // Reset MMU to initial state
-#define MMUCR_OP_RX_POP         (3 << 5)        // Remove frame from top of RX FIFO
-#define MMUCR_OP_RX_POP_REL     (4 << 5)        // Remove and release frame from top of RX FIFO
-#define MMUCR_OP_RX_REL         (5 << 5)        // Release specific RX frame
-#define MMUCR_OP_TX_PUSH        (6 << 5)        // Enqueue packet number into TX FIFO
-#define MMUCR_OP_TX_RESET       (7 << 5)        // Reset TX FIFOs
-
-// Packet Number Register Bits
-#define PNR_PACKET      (0x3f)
-
-// Allocation Result Register Bits
-#define ARR_PACKET      (0x3f)
-#define ARR_FAILED      BIT7
-
-// FIFO Ports Register Bits
-#define FIFO_TX_PACKET  (0x003f)
-#define FIFO_TEMPTY     BIT7
-#define FIFO_RX_PACKET  (0x3f00)
-#define FIFO_REMPTY     BIT15
-
-// Pointer Register Bits
-#define PTR_POINTER     (0x07ff)
-#define PTR_NOT_EMPTY   BIT11
-#define PTR_READ        BIT13
-#define PTR_AUTO_INCR   BIT14
-#define PTR_RCV         BIT15
-
-// Interupt Status and Mask Register Bits
-#define IST_RCV         BIT0
-#define IST_TX          BIT1
-#define IST_TX_EMPTY    BIT2
-#define IST_ALLOC       BIT3
-#define IST_RX_OVRN     BIT4
-#define IST_EPH         BIT5
-#define IST_MD          BIT7
-
-// Management Interface
-#define MGMT_MDO        BIT0
-#define MGMT_MDI        BIT1
-#define MGMT_MCLK       BIT2
-#define MGMT_MDOE       BIT3
-#define MGMT_MSK_CRS100 BIT14
-
-// RCV Register
-#define RCV_MBO         (0x1f)
-#define RCV_RCV_DISCRD  BIT7
-
-// Packet RX Status word bits
-#define RX_MULTICAST    BIT0
-#define RX_HASH         (0x7e)
-#define RX_TOO_SHORT    BIT10
-#define RX_TOO_LONG     BIT11
-#define RX_ODD_FRAME    BIT12
-#define RX_BAD_CRC      BIT13
-#define RX_BROADCAST    BIT14
-#define RX_ALGN_ERR     BIT15
-
-// Packet Byte Count word bits
-#define	BCW_COUNT	(0x7fe)
-
-// Packet Control Word bits
-#define PCW_ODD_BYTE    (0x00ff)
-#define PCW_CRC         BIT12
-#define PCW_ODD         BIT13
-
-/*---------------------------------------------------------------------------------------------------------------------
-
-	SMSC PHY Registers
-
-	Most of these should be common, as there is
-	documented STANDARD for PHY registers!
-
----------------------------------------------------------------------------------------------------------------------*/
-//
-// PHY Register Numbers
-//
-#define PHY_INDEX_BASIC_CTRL              0
-#define PHY_INDEX_BASIC_STATUS            1
-#define PHY_INDEX_ID1                     2
-#define PHY_INDEX_ID2                     3
-#define PHY_INDEX_AUTO_NEG_ADVERT         4
-#define PHY_INDEX_AUTO_NEG_LINK_ABILITY   5
-
-#define PHY_INDEX_CONFIG1                 16
-#define PHY_INDEX_CONFIG2                 17
-#define PHY_INDEX_STATUS_OUTPUT           18
-#define PHY_INDEX_MASK                    19
-
-
-// PHY control register bits
-#define PHYCR_COLL_TEST                       BIT7                  // Collision test enable
-#define PHYCR_DUPLEX_MODE                     BIT8                  // Set Duplex Mode
-#define PHYCR_RST_AUTO                        BIT9                  // Restart Auto-Negotiation of Link abilities
-#define PHYCR_PD                              BIT11                 // Power-Down switch
-#define PHYCR_AUTO_EN                         BIT12                 // Auto-Negotiation Enable
-#define PHYCR_SPEED_SEL                       BIT13                 // Link Speed Selection
-#define PHYCR_LOOPBK                          BIT14                 // Set loopback mode
-#define PHYCR_RESET                           BIT15                 // Do a PHY reset
-
-// PHY status register bits
-#define PHYSTS_EXT_CAP                        BIT0                  // Extended Capabilities Register capability
-#define PHYSTS_JABBER                         BIT1                  // Jabber condition detected
-#define PHYSTS_LINK_STS                       BIT2                  // Link Status
-#define PHYSTS_AUTO_CAP                       BIT3                  // Auto-Negotiation Capability
-#define PHYSTS_REMOTE_FAULT                   BIT4                  // Remote fault detected
-#define PHYSTS_AUTO_COMP                      BIT5                  // Auto-Negotiation Completed
-#define PHYSTS_10BASET_HDPLX                  BIT11                 // 10Mbps Half-Duplex ability
-#define PHYSTS_10BASET_FDPLX                  BIT12                 // 10Mbps Full-Duplex ability
-#define PHYSTS_100BASETX_HDPLX                BIT13                 // 100Mbps Half-Duplex ability
-#define PHYSTS_100BASETX_FDPLX                BIT14                 // 100Mbps Full-Duplex ability
-#define PHYSTS_100BASE_T4                     BIT15                 // Base T4 ability
-
-// PHY Auto-Negotiation advertisement
-#define PHYANA_SEL_MASK                       ((UINT32)0x1F)        // Link type selector
-#define PHYANA_CSMA                           BIT0                  // Advertise CSMA capability
-#define PHYANA_10BASET                        BIT5                  // Advertise 10BASET capability
-#define PHYANA_10BASETFD                      BIT6                  // Advertise 10BASET Full duplex capability
-#define PHYANA_100BASETX                      BIT7                  // Advertise 100BASETX capability
-#define PHYANA_100BASETXFD                    BIT8                  // Advertise 100 BASETX Full duplex capability
-#define PHYANA_100BASET4                      BIT9                  // Advertise 100 BASETX Full duplex capability
-#define PHYANA_PAUSE_OP_MASK                  (3 << 10)             // Advertise PAUSE frame capability
-#define PHYANA_REMOTE_FAULT                   BIT13                 // Remote fault detected
-
-#endif /* __LAN91XDXEHW_H__ */
+/** @file
+*  SMSC LAN91x series Network Controller Driver.
+*
+*  Copyright (c) 2013 Linaro.org
+*
+*  This program and the accompanying materials are licensed and
+*  made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license
+*  may be found at: http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __LAN91XDXEHW_H__
+#define __LAN91XDXEHW_H__
+
+#include <Base.h>
+
+#define MakeRegister(Bank, Offset)  (((Bank) << 8) | (Offset))
+#define RegisterToBank(Register)    (((Register) >> 8) & 0x07)
+#define RegisterToOffset(Register)  ((Register) & 0x0f)
+
+/*---------------------------------------------------------------------------------------------------------------------
+
+	SMSC LAN91x Registers
+
+---------------------------------------------------------------------------------------------------------------------*/
+#define LAN91X_BANK_OFFSET      0xe                     // Bank Select Register (all banks)
+
+#define LAN91X_TCR      MakeRegister (0, 0x0)           // Transmit Control Register
+#define LAN91X_EPHSR    MakeRegister (0, 0x2)           // EPH Status Register
+#define LAN91X_RCR      MakeRegister (0, 0x4)           // Receive Control Register
+#define LAN91X_ECR      MakeRegister (0, 0x6)           // Counter Register
+#define LAN91X_MIR      MakeRegister (0, 0x8)           // Memory Information Register
+#define LAN91X_RPCR     MakeRegister (0, 0xa)           // Receive/Phy Control Register
+
+#define LAN91X_CR       MakeRegister (1, 0x0)           // Configuration Register
+#define LAN91X_BAR      MakeRegister (1, 0x2)           // Base Address Register
+#define LAN91X_IAR0     MakeRegister (1, 0x4)           // Individual Address Register 0
+#define LAN91X_IAR1     MakeRegister (1, 0x5)           // Individual Address Register 1
+#define LAN91X_IAR2     MakeRegister (1, 0x6)           // Individual Address Register 2
+#define LAN91X_IAR3     MakeRegister (1, 0x7)           // Individual Address Register 3
+#define LAN91X_IAR4     MakeRegister (1, 0x8)           // Individual Address Register 4
+#define LAN91X_IAR5     MakeRegister (1, 0x9)           // Individual Address Register 5
+#define LAN91X_GPR      MakeRegister (1, 0xa)           // General Purpose Register
+#define LAN91X_CTR      MakeRegister (1, 0xc)           // Control Register
+
+#define LAN91X_MMUCR    MakeRegister (2, 0x0)           // MMU Command Register
+#define LAN91X_PNR      MakeRegister (2, 0x2)           // Packet Number Register
+#define LAN91X_ARR      MakeRegister (2, 0x3)           // Allocation Result Register
+#define LAN91X_FIFO     MakeRegister (2, 0x4)           // FIFO Ports Register
+#define LAN91X_PTR      MakeRegister (2, 0x6)           // Pointer Register
+#define LAN91X_DATA0    MakeRegister (2, 0x8)           // Data Register 0
+#define LAN91X_DATA1    MakeRegister (2, 0x9)           // Data Register 1
+#define LAN91X_DATA2    MakeRegister (2, 0xa)           // Data Register 2
+#define LAN91X_DATA3    MakeRegister (2, 0xb)           // Data Register 3
+#define LAN91X_IST      MakeRegister (2, 0xc)           // Interrupt Status Register
+#define LAN91X_MSK      MakeRegister (2, 0xd)           // Interrupt Mask Register
+
+#define LAN91X_MT0      MakeRegister (3, 0x0)           // Multicast Table Register 0
+#define LAN91X_MT1      MakeRegister (3, 0x1)           // Multicast Table Register 1
+#define LAN91X_MT2      MakeRegister (3, 0x2)           // Multicast Table Register 2
+#define LAN91X_MT3      MakeRegister (3, 0x3)           // Multicast Table Register 3
+#define LAN91X_MT4      MakeRegister (3, 0x4)           // Multicast Table Register 4
+#define LAN91X_MT5      MakeRegister (3, 0x5)           // Multicast Table Register 5
+#define LAN91X_MT6      MakeRegister (3, 0x6)           // Multicast Table Register 6
+#define LAN91X_MT7      MakeRegister (3, 0x7)           // Multicast Table Register 7
+#define LAN91X_MGMT     MakeRegister (3, 0x8)           // Management Interface Register
+#define LAN91X_REV      MakeRegister (3, 0xa)           // Revision Register
+#define LAN91X_RCV      MakeRegister (3, 0xc)           // RCV Register
+
+// Transmit Control Register Bits
+#define TCR_TXENA       BIT0
+#define TCR_LOOP        BIT1
+#define TCR_FORCOL      BIT2
+#define TCR_PAD_EN      BIT7
+#define TCR_NOCRC       BIT8
+#define TCR_MON_CSN     BIT10
+#define TCR_FDUPLX      BIT11
+#define TCR_STP_SQET    BIT12
+#define TCR_EPH_LOOP    BIT13
+#define TCR_SWFDUP      BIT15
+
+#define TCR_DEFAULT     (TCR_TXENA | TCR_PAD_EN)
+#define TCR_CLEAR       0x0
+
+// EPH Status Register Bits
+#define EPHSR_TX_SUC    BIT0
+#define EPHSR_SNGLCOL   BIT1
+#define EPHSR_MULCOL    BIT2
+#define EPHSR_LTX_MULT  BIT3
+#define EPHSR_16COL     BIT4
+#define EPHSR_SQET      BIT5
+#define EPHSR_LTX_BRD   BIT6
+#define EPHSR_TX_DEFR   BIT7
+#define EPHSR_LATCOL    BIT9
+#define EPHSR_LOST_CARR BIT10
+#define EPHSR_EXC_DEF   BIT11
+#define EPHSR_CTR_ROL   BIT12
+#define EPHSR_LINK_OK   BIT14
+
+// Receive Control Register Bits
+#define RCR_RX_ABORT    BIT0
+#define RCR_PRMS        BIT1
+#define RCR_ALMUL       BIT2
+#define RCR_RXEN        BIT8
+#define RCR_STRIP_CRC   BIT9
+#define RCR_ABORT_ENB   BIT13
+#define RCR_FILT_CAR    BIT14
+#define RCR_SOFT_RST    BIT15
+
+#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
+#define RCR_CLEAR       0x0
+
+// Receive/Phy Control Register Bits
+#define RPCR_LS0B       BIT2
+#define RPCR_LS1B       BIT3
+#define RPCR_LS2B       BIT4
+#define RPCR_LS0A       BIT5
+#define RPCR_LS1A       BIT6
+#define RPCR_LS2A       BIT7
+#define RPCR_ANEG       BIT11
+#define RPCR_DPLX       BIT12
+#define RPCR_SPEED      BIT13
+
+// Configuration Register Bits
+#define CR_EXT_PHY      BIT9
+#define CR_GPCNTRL      BIT10
+#define CR_NO_WAIT      BIT12
+#define CR_EPH_POWER_EN BIT15
+
+#define CR_DEFAULT      (CR_EPH_POWER_EN | CR_NO_WAIT)
+
+// Control Register Bits
+#define CTR_STORE       BIT0
+#define CTR_RELOAD      BIT1
+#define CTR_EEPROM_SEL  BIT2
+#define CTR_TE_ENABLE   BIT5
+#define CTR_CR_ENABLE   BIT6
+#define CTR_LE_ENABLE   BIT7
+#define CTR_AUTO_REL    BIT11
+#define CTR_RCV_BAD     BIT14
+
+#define	CTR_RESERVED	(BIT12 | BIT9 | BIT4)
+#define CTR_DEFAULT     (CTR_RESERVED | CTR_AUTO_REL)
+
+// MMU Command Register Bits
+#define MMUCR_BUSY      BIT0
+
+// MMU Command Register Operaction Codes
+#define MMUCR_OP_NOOP           (0 << 5)        // No operation
+#define MMUCR_OP_TX_ALLOC       (1 << 5)        // Allocate memory for TX
+#define MMUCR_OP_RESET_MMU      (2 << 5)        // Reset MMU to initial state
+#define MMUCR_OP_RX_POP         (3 << 5)        // Remove frame from top of RX FIFO
+#define MMUCR_OP_RX_POP_REL     (4 << 5)        // Remove and release frame from top of RX FIFO
+#define MMUCR_OP_RX_REL         (5 << 5)        // Release specific RX frame
+#define MMUCR_OP_TX_PUSH        (6 << 5)        // Enqueue packet number into TX FIFO
+#define MMUCR_OP_TX_RESET       (7 << 5)        // Reset TX FIFOs
+
+// Packet Number Register Bits
+#define PNR_PACKET      (0x3f)
+
+// Allocation Result Register Bits
+#define ARR_PACKET      (0x3f)
+#define ARR_FAILED      BIT7
+
+// FIFO Ports Register Bits
+#define FIFO_TX_PACKET  (0x003f)
+#define FIFO_TEMPTY     BIT7
+#define FIFO_RX_PACKET  (0x3f00)
+#define FIFO_REMPTY     BIT15
+
+// Pointer Register Bits
+#define PTR_POINTER     (0x07ff)
+#define PTR_NOT_EMPTY   BIT11
+#define PTR_READ        BIT13
+#define PTR_AUTO_INCR   BIT14
+#define PTR_RCV         BIT15
+
+// Interupt Status and Mask Register Bits
+#define IST_RCV         BIT0
+#define IST_TX          BIT1
+#define IST_TX_EMPTY    BIT2
+#define IST_ALLOC       BIT3
+#define IST_RX_OVRN     BIT4
+#define IST_EPH         BIT5
+#define IST_MD          BIT7
+
+// Management Interface
+#define MGMT_MDO        BIT0
+#define MGMT_MDI        BIT1
+#define MGMT_MCLK       BIT2
+#define MGMT_MDOE       BIT3
+#define MGMT_MSK_CRS100 BIT14
+
+// RCV Register
+#define RCV_MBO         (0x1f)
+#define RCV_RCV_DISCRD  BIT7
+
+// Packet RX Status word bits
+#define RX_MULTICAST    BIT0
+#define RX_HASH         (0x7e)
+#define RX_TOO_SHORT    BIT10
+#define RX_TOO_LONG     BIT11
+#define RX_ODD_FRAME    BIT12
+#define RX_BAD_CRC      BIT13
+#define RX_BROADCAST    BIT14
+#define RX_ALGN_ERR     BIT15
+
+// Packet Byte Count word bits
+#define	BCW_COUNT	(0x7fe)
+
+// Packet Control Word bits
+#define PCW_ODD_BYTE    (0x00ff)
+#define PCW_CRC         BIT12
+#define PCW_ODD         BIT13
+
+/*---------------------------------------------------------------------------------------------------------------------
+
+	SMSC PHY Registers
+
+	Most of these should be common, as there is
+	documented STANDARD for PHY registers!
+
+---------------------------------------------------------------------------------------------------------------------*/
+//
+// PHY Register Numbers
+//
+#define PHY_INDEX_BASIC_CTRL              0
+#define PHY_INDEX_BASIC_STATUS            1
+#define PHY_INDEX_ID1                     2
+#define PHY_INDEX_ID2                     3
+#define PHY_INDEX_AUTO_NEG_ADVERT         4
+#define PHY_INDEX_AUTO_NEG_LINK_ABILITY   5
+
+#define PHY_INDEX_CONFIG1                 16
+#define PHY_INDEX_CONFIG2                 17
+#define PHY_INDEX_STATUS_OUTPUT           18
+#define PHY_INDEX_MASK                    19
+
+
+// PHY control register bits
+#define PHYCR_COLL_TEST                       BIT7                  // Collision test enable
+#define PHYCR_DUPLEX_MODE                     BIT8                  // Set Duplex Mode
+#define PHYCR_RST_AUTO                        BIT9                  // Restart Auto-Negotiation of Link abilities
+#define PHYCR_PD                              BIT11                 // Power-Down switch
+#define PHYCR_AUTO_EN                         BIT12                 // Auto-Negotiation Enable
+#define PHYCR_SPEED_SEL                       BIT13                 // Link Speed Selection
+#define PHYCR_LOOPBK                          BIT14                 // Set loopback mode
+#define PHYCR_RESET                           BIT15                 // Do a PHY reset
+
+// PHY status register bits
+#define PHYSTS_EXT_CAP                        BIT0                  // Extended Capabilities Register capability
+#define PHYSTS_JABBER                         BIT1                  // Jabber condition detected
+#define PHYSTS_LINK_STS                       BIT2                  // Link Status
+#define PHYSTS_AUTO_CAP                       BIT3                  // Auto-Negotiation Capability
+#define PHYSTS_REMOTE_FAULT                   BIT4                  // Remote fault detected
+#define PHYSTS_AUTO_COMP                      BIT5                  // Auto-Negotiation Completed
+#define PHYSTS_10BASET_HDPLX                  BIT11                 // 10Mbps Half-Duplex ability
+#define PHYSTS_10BASET_FDPLX                  BIT12                 // 10Mbps Full-Duplex ability
+#define PHYSTS_100BASETX_HDPLX                BIT13                 // 100Mbps Half-Duplex ability
+#define PHYSTS_100BASETX_FDPLX                BIT14                 // 100Mbps Full-Duplex ability
+#define PHYSTS_100BASE_T4                     BIT15                 // Base T4 ability
+
+// PHY Auto-Negotiation advertisement
+#define PHYANA_SEL_MASK                       ((UINT32)0x1F)        // Link type selector
+#define PHYANA_CSMA                           BIT0                  // Advertise CSMA capability
+#define PHYANA_10BASET                        BIT5                  // Advertise 10BASET capability
+#define PHYANA_10BASETFD                      BIT6                  // Advertise 10BASET Full duplex capability
+#define PHYANA_100BASETX                      BIT7                  // Advertise 100BASETX capability
+#define PHYANA_100BASETXFD                    BIT8                  // Advertise 100 BASETX Full duplex capability
+#define PHYANA_100BASET4                      BIT9                  // Advertise 100 BASETX Full duplex capability
+#define PHYANA_PAUSE_OP_MASK                  (3 << 10)             // Advertise PAUSE frame capability
+#define PHYANA_REMOTE_FAULT                   BIT13                 // Remote fault detected
+
+#endif /* __LAN91XDXEHW_H__ */
diff --git a/Drivers/Net/MarvellYukonDxe/ComponentName.c b/Drivers/Net/MarvellYukonDxe/ComponentName.c
new file mode 100644
index 0000000..c3523a2
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/ComponentName.c
@@ -0,0 +1,313 @@
+/**
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "MarvellYukon.h"
+
+//
+// EFI Component Name Functions
+//
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+   <at> param  This[in]               A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                      EFI_COMPONENT_NAME_PROTOCOL instance.
+
+   <at> param  Language[in]           A pointer to a Null-terminated ASCII string
+                                      array indicating the language. This is the
+                                      language of the driver name that the caller is
+                                      requesting, and it must match one of the
+                                      languages specified in SupportedLanguages. The
+                                      number of languages supported by a driver is up
+                                      to the driver writer. Language is specified
+                                      in RFC 4646 or ISO 639-2 language code format.
+
+   <at> param  DriverName[out]        A pointer to the Unicode string to return.
+                                      This Unicode string is the name of the
+                                      driver specified by This in the language
+                                      specified by Language.
+
+   <at> retval EFI_SUCCESS            The Unicode string for the Driver specified by
+                                      This and the language specified by Language was
+                                      returned in DriverName.
+
+   <at> retval EFI_INVALID_PARAMETER  Language is NULL.
+
+   <at> retval EFI_INVALID_PARAMETER  DriverName is NULL.
+
+   <at> retval EFI_UNSUPPORTED        The driver specified by This does not support
+                                      the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SimpleNetworkComponentNameGetDriverName (
+    IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
+    IN  CHAR8                        *Language,
+    OUT CHAR16                       **DriverName
+    );
+
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+   <at> param  This[in]               A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                      EFI_COMPONENT_NAME_PROTOCOL instance.
+
+   <at> param  ControllerHandle[in]   The handle of a controller that the driver
+                                      specified by This is managing.  This handle
+                                      specifies the controller whose name is to be
+                                      returned.
+
+   <at> param  ChildHandle[in]        The handle of the child controller to retrieve
+                                      the name of.  This is an optional parameter that
+                                      may be NULL.  It will be NULL for device
+                                      drivers.  It will also be NULL for a bus drivers
+                                      that wish to retrieve the name of the bus
+                                      controller.  It will not be NULL for a bus
+                                      driver that wishes to retrieve the name of a
+                                      child controller.
+
+   <at> param  Language[in]           A pointer to a Null-terminated ASCII string
+                                      array indicating the language.  This is the
+                                      language of the driver name that the caller is
+                                      requesting, and it must match one of the
+                                      languages specified in SupportedLanguages. The
+                                      number of languages supported by a driver is up
+                                      to the driver writer. Language is specified in
+                                      RFC 4646 or ISO 639-2 language code format.
+
+   <at> param  ControllerName[out]    A pointer to the Unicode string to return.
+                                      This Unicode string is the name of the
+                                      controller specified by ControllerHandle and
+                                      ChildHandle in the language specified by
+                                      Language from the point of view of the driver
+                                      specified by This.
+
+   <at> retval EFI_SUCCESS            The Unicode string for the user readable name in
+                                      the language specified by Language for the
+                                      driver specified by This was returned in
+                                      DriverName.
+
+   <at> retval EFI_INVALID_PARAMETER  ControllerHandle is not a valid EFI_HANDLE.
+
+   <at> retval EFI_INVALID_PARAMETER  ChildHandle is not NULL and it is not a valid
+                                      EFI_HANDLE.
+
+   <at> retval EFI_INVALID_PARAMETER  Language is NULL.
+
+   <at> retval EFI_INVALID_PARAMETER  ControllerName is NULL.
+
+   <at> retval EFI_UNSUPPORTED        The driver specified by This is not currently
+                                      managing the controller specified by
+                                      ControllerHandle and ChildHandle.
+
+   <at> retval EFI_UNSUPPORTED        The driver specified by This does not support
+                                      the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SimpleNetworkComponentNameGetControllerName (
+    IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
+    IN  EFI_HANDLE                                      ControllerHandle,
+    IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
+    IN  CHAR8                                           *Language,
+    OUT CHAR16                                          **ControllerName
+    );
+
+
+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL  gSimpleNetworkComponentName = {
+  SimpleNetworkComponentNameGetDriverName,
+  SimpleNetworkComponentNameGetControllerName,
+  "eng"
+};
+
+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSimpleNetworkComponentName2 = {
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SimpleNetworkComponentNameGetDriverName,
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SimpleNetworkComponentNameGetControllerName,
+  "en"
+};
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSimpleNetworkDriverNameTable[] = {
+  {
+    "eng;en",
+    L"Marvell Yukon Simple Network Protocol Driver"
+  },
+  {
+    NULL,
+    NULL
+  }
+};
+
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+   <at> param  This[in]               A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                      EFI_COMPONENT_NAME_PROTOCOL instance.
+
+   <at> param  Language[in]           A pointer to a Null-terminated ASCII string
+                                      array indicating the language. This is the
+                                      language of the driver name that the caller is
+                                      requesting, and it must match one of the
+                                      languages specified in SupportedLanguages. The
+                                      number of languages supported by a driver is up
+                                      to the driver writer. Language is specified
+                                      in RFC 4646 or ISO 639-2 language code format.
+
+   <at> param  DriverName[out]        A pointer to the Unicode string to return.
+                                      This Unicode string is the name of the
+                                      driver specified by This in the language
+                                      specified by Language.
+
+   <at> retval EFI_SUCCESS            The Unicode string for the Driver specified by
+                                      This and the language specified by Language was
+                                      returned in DriverName.
+
+   <at> retval EFI_INVALID_PARAMETER  Language is NULL.
+
+   <at> retval EFI_INVALID_PARAMETER  DriverName is NULL.
+
+   <at> retval EFI_UNSUPPORTED        The driver specified by This does not support
+                                      the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SimpleNetworkComponentNameGetDriverName (
+    IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
+    IN  CHAR8                        *Language,
+    OUT CHAR16                       **DriverName
+    )
+{
+  return LookupUnicodeString2 (
+        Language,
+        This->SupportedLanguages,
+        mSimpleNetworkDriverNameTable,
+        DriverName,
+        (BOOLEAN)(This == &gSimpleNetworkComponentName)
+        );
+}
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+  Currently not implemented.
+
+   <at> param  This[in]               A pointer to the EFI_COMPONENT_NAME2_PROTOCOL
+                                      or EFI_COMPONENT_NAME_PROTOCOL instance.
+
+   <at> param  ControllerHandle[in]   The handle of a controller that the driver
+                                      specified by This is managing.  This handle
+                                      specifies the controller whose name is to be
+                                      returned.
+
+   <at> param  ChildHandle[in]        The handle of the child controller to retrieve
+                                      the name of.  This is an optional parameter that
+                                      may be NULL.  It will be NULL for device
+                                      drivers.  It will also be NULL for a bus drivers
+                                      that wish to retrieve the name of the bus
+                                      controller.  It will not be NULL for a bus
+                                      driver that wishes to retrieve the name of a
+                                      child controller.
+
+   <at> param  Language[in]           A pointer to a Null-terminated ASCII string
+                                      array indicating the language.  This is the
+                                      language of the driver name that the caller is
+                                      requesting, and it must match one of the
+                                      languages specified in SupportedLanguages. The
+                                      number of languages supported by a driver is up
+                                      to the driver writer. Language is specified in
+                                      RFC 4646 or ISO 639-2 language code format.
+
+   <at> param  ControllerName[out]    A pointer to the Unicode string to return.
+                                      This Unicode string is the name of the
+                                      controller specified by ControllerHandle and
+                                      ChildHandle in the language specified by
+                                      Language from the point of view of the driver
+                                      specified by This.
+
+   <at> retval EFI_SUCCESS            The Unicode string for the user readable name in
+                                      the language specified by Language for the
+                                      driver specified by This was returned in
+                                      DriverName.
+
+   <at> retval EFI_INVALID_PARAMETER  ControllerHandle is not a valid EFI_HANDLE.
+
+   <at> retval EFI_INVALID_PARAMETER  ChildHandle is not NULL and it is not a valid
+                                      EFI_HANDLE.
+
+   <at> retval EFI_INVALID_PARAMETER  Language is NULL.
+
+   <at> retval EFI_INVALID_PARAMETER  ControllerName is NULL.
+
+   <at> retval EFI_UNSUPPORTED        The driver specified by This is not currently
+                                      managing the controller specified by
+                                      ControllerHandle and ChildHandle.
+
+   <at> retval EFI_UNSUPPORTED        The driver specified by This does not support
+                                      the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SimpleNetworkComponentNameGetControllerName (
+    IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
+    IN  EFI_HANDLE                                      ControllerHandle,
+    IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
+    IN  CHAR8                                           *Language,
+    OUT CHAR16                                          **ControllerName
+    )
+{
+  return EFI_UNSUPPORTED;
+}
diff --git a/Drivers/Net/MarvellYukonDxe/DriverBinding.c b/Drivers/Net/MarvellYukonDxe/DriverBinding.c
new file mode 100644
index 0000000..947d738
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/DriverBinding.c
@@ -0,0 +1,672 @@
+/**  <at> file
+  Implementation of driver entry point and driver binding protocol.
+
+Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
+
+This program and the accompanying materials are licensed
+and made available under the terms and conditions of the BSD License which
+accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/NetLib.h>
+#include <Library/DevicePathLib.h>
+#include "MarvellYukon.h"
+#include "if_msk.h"
+
+STATIC LIST_ENTRY MarvellYukonDrvDataHead;
+
+/**
+  Test to see if this driver supports ControllerHandle. This service
+  is called by the EFI boot service ConnectController(). In
+  order to make drivers as small as possible, there are a few calling
+  restrictions for this service. ConnectController() must
+  follow these calling restrictions. If any other agent wishes to call
+  Supported() it must also follow these calling restrictions.
+
+   <at> param  This                   Protocol instance pointer.
+   <at> param  ControllerHandle       Handle of device to test.
+   <at> param  RemainingDevicePath    Optional parameter use to pick a specific child
+                                                             device to start.
+
+   <at> retval EFI_SUCCESS            This driver supports this device.
+   <at> retval EFI_ALREADY_STARTED    This driver is already running on this device.
+   <at> retval other                  This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonDriverSupported (
+    IN EFI_DRIVER_BINDING_PROTOCOL    *This,
+    IN EFI_HANDLE                     Controller,
+    IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
+    )
+{
+  EFI_STATUS              Status;
+  EFI_PCI_IO_PROTOCOL     *PciIo;
+
+  //
+  // Test that the PCI IO Protocol is attached to the controller handle and no other driver is consuming it
+  //
+  Status = gBS->OpenProtocol (
+        Controller,
+        &gEfiPciIoProtocolGuid,
+        (VOID **) &PciIo,
+        This->DriverBindingHandle,
+        Controller,
+        EFI_OPEN_PROTOCOL_BY_DRIVER
+        );
+
+  if (!EFI_ERROR (Status)) {
+    //
+    // Test whether the controller is on a supported NIC
+    //
+    Status = mskc_probe (PciIo);
+    if (EFI_ERROR (Status)) {
+      Status = EFI_UNSUPPORTED;
+    } else {
+      DEBUG ((EFI_D_NET, "Marvell Yukon: MarvellYukonDriverSupported: Supported Controller = %p\n", Controller));
+    }
+
+    gBS->CloseProtocol (
+          Controller,
+          &gEfiPciIoProtocolGuid,
+          This->DriverBindingHandle,
+          Controller
+          );
+  }
+
+  return Status;
+}
+
+/**
+  Start this driver on Controller by opening PciIo and DevicePath protocols.
+  Initialize PXE structures, create a copy of the Controller Device Path with the
+  NIC's MAC address appended to it, install the NetworkInterfaceIdentifier protocol
+  on the newly created Device Path.
+
+  @param [in] pThis                   Protocol instance pointer.
+  @param [in] Controller              Handle of device to work with.
+  @param [in] pRemainingDevicePath    Not used, always produce all possible children.
+
+  @retval EFI_SUCCESS                 This driver is added to Controller.
+  @retval other                       This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonDriverStart (
+    IN EFI_DRIVER_BINDING_PROTOCOL * pThis,
+    IN EFI_HANDLE Controller,
+    IN EFI_DEVICE_PATH_PROTOCOL * pRemainingDevicePath
+    )
+{
+
+  EFI_STATUS                       Status;
+  EFI_DEVICE_PATH_PROTOCOL         *ParentDevicePath;
+  MAC_ADDR_DEVICE_PATH             MacDeviceNode;
+  VOID                            *ChildPciIo;
+  YUKON_DRIVER                    *YukonDriver;
+  struct msk_softc                *ScData;
+  EFI_PCI_IO_PROTOCOL             *PciIo;
+  UINTN                            Port;
+
+  Status = gBS->OpenProtocol (
+        Controller,
+        &gEfiPciIoProtocolGuid,
+        (VOID **) &PciIo,
+        pThis->DriverBindingHandle,
+        Controller,
+        EFI_OPEN_PROTOCOL_BY_DRIVER
+        );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: OpenProtocol: EFI_PCI_IO_PROTOCOL ERROR Status = %r\n", Status));
+    gBS->FreePool (YukonDriver);
+    return Status;
+  }
+
+  //
+  // Initialize Marvell Yukon controller
+  // Get number of ports and MAC address for each port
+  //
+  Status = mskc_attach (PciIo, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = MarvellYukonAddControllerData (Controller, ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  for (Port = 0; Port < ScData->msk_num_port; Port++) {
+
+    Status = gBS->AllocatePool (EfiBootServicesData,
+                                sizeof (YUKON_DRIVER),
+                                (VOID**) &YukonDriver);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Marvell Yukon: AllocatePool() failed with Status = %r\n", Status));
+      return Status;
+    }
+
+    if (ScData->msk_if[Port] == NULL) {
+      DEBUG ((DEBUG_ERROR, "Marvell Yukon: AllocatePool() failed with Status = %r\n", EFI_BAD_BUFFER_SIZE));
+      return EFI_BAD_BUFFER_SIZE;
+    }
+
+    gBS->SetMem (YukonDriver, sizeof (YUKON_DRIVER), 0);
+    EfiInitializeLock (&YukonDriver->Lock, TPL_NOTIFY);
+
+    //
+    //  Set the structure signature
+    //
+    YukonDriver->Signature = YUKON_DRIVER_SIGNATURE;
+
+    //
+    // Set MAC address
+    //
+    gBS->CopyMem (&YukonDriver->SnpMode.PermanentAddress, &(ScData->msk_if[Port])->MacAddress,
+                  sizeof (EFI_MAC_ADDRESS));
+
+    //
+    // Set Port number
+    //
+    YukonDriver->Port = Port;
+
+    //
+    //  Initialize the simple network protocol
+    //
+    Status = InitializeSNPProtocol (YukonDriver);
+
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Marvell Yukon: InitializeSNPProtocol: ERROR Status = %r\n", Status));
+      gBS->CloseProtocol (
+            Controller,
+            &gEfiPciIoProtocolGuid,
+            pThis->DriverBindingHandle,
+            Controller
+            );
+    }
+
+    //
+    // Set Device Path
+    //
+    Status = gBS->OpenProtocol (
+          Controller,
+          &gEfiDevicePathProtocolGuid,
+          (VOID **) &ParentDevicePath,
+          pThis->DriverBindingHandle,
+          Controller,
+          EFI_OPEN_PROTOCOL_GET_PROTOCOL
+          );
+
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Marvell Yukon: OpenProtocol:EFI_DEVICE_PATH_PROTOCOL error. Status = %r\n", Status));
+
+      gBS->CloseProtocol (
+            Controller,
+            &gEfiPciIoProtocolGuid,
+            pThis->DriverBindingHandle,
+            Controller
+            );
+
+      gBS->FreePool (YukonDriver);
+      return Status;
+    }
+
+    gBS->SetMem (&MacDeviceNode, sizeof (MAC_ADDR_DEVICE_PATH), 0);
+    MacDeviceNode.Header.Type = MESSAGING_DEVICE_PATH;
+    MacDeviceNode.Header.SubType = MSG_MAC_ADDR_DP;
+
+    SetDevicePathNodeLength (&MacDeviceNode, sizeof (MacDeviceNode));
+
+    //
+    // Assign fields for device path
+    //
+    gBS->CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress,
+                  sizeof (EFI_MAC_ADDRESS));
+    gBS->CopyMem (&MacDeviceNode.MacAddress, &YukonDriver->SnpMode.CurrentAddress, sizeof (EFI_MAC_ADDRESS));
+
+    MacDeviceNode.IfType = YukonDriver->SnpMode.IfType;
+    YukonDriver->DevicePath = AppendDevicePathNode (ParentDevicePath, &MacDeviceNode.Header);
+    if (YukonDriver->DevicePath == NULL) {
+      DEBUG ((DEBUG_ERROR, "Marvell Yukon: AppendDevicePathNode: ERROR Status = %r\n", EFI_OUT_OF_RESOURCES));
+      gBS->CloseProtocol (
+            Controller,
+            &gEfiPciIoProtocolGuid,
+            pThis->DriverBindingHandle,
+            Controller
+            );
+      gBS->FreePool (YukonDriver);
+      return EFI_OUT_OF_RESOURCES;
+    }
+
+    //
+    //  Install both the simple network and device path protocols.
+    //
+    Status = gBS->InstallMultipleProtocolInterfaces (
+          &YukonDriver->Controller,
+          &gEfiSimpleNetworkProtocolGuid,
+          &YukonDriver->Snp,
+          &gEfiDevicePathProtocolGuid,
+          YukonDriver->DevicePath,
+          NULL
+          );
+
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Marvell Yukon: InstallMultipleProtocolInterfaces error. Status = %r\n", Status));
+
+      gBS->CloseProtocol (
+            Controller,
+            &gEfiPciIoProtocolGuid,
+            pThis->DriverBindingHandle,
+            Controller
+            );
+
+      gBS->FreePool (YukonDriver->DevicePath);
+      gBS->FreePool (YukonDriver);
+      return Status;
+    } else {
+
+      //
+      // Hook as a child device
+      //
+      Status = gBS->OpenProtocol (Controller,
+                                  &gEfiPciIoProtocolGuid,
+                                  &ChildPciIo,
+                                  pThis->DriverBindingHandle,
+                                  YukonDriver->Controller,
+                                  EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER);
+      if (EFI_ERROR (Status)) {
+        DEBUG ((DEBUG_ERROR, "Marvell Yukon: OpenProtocol: child controller error. Status = %r\n", Status));
+
+        gBS->UninstallMultipleProtocolInterfaces (
+              Controller,
+              &gEfiSimpleNetworkProtocolGuid,
+              &YukonDriver->Snp,
+              &gEfiDevicePathProtocolGuid,
+              YukonDriver->DevicePath,
+              NULL
+              );
+
+        gBS->CloseProtocol (
+              Controller,
+              &gEfiPciIoProtocolGuid,
+              pThis->DriverBindingHandle,
+              Controller
+              );
+
+        gBS->FreePool (YukonDriver->DevicePath);
+        gBS->FreePool (YukonDriver);
+        return Status;
+      } else {
+        DEBUG ((DEBUG_NET, "Marvell Yukon: MarvellYukonDriverSupported: New Controller Handle = %p\n",
+               YukonDriver->Controller));
+      }
+
+      Status = MarvellYukonAddControllerData (YukonDriver->Controller, ScData);
+      if (EFI_ERROR (Status)) {
+        DEBUG ((DEBUG_ERROR, "Marvell Yukon: Failed to register port %d with controller handle %p\n", Port,
+               YukonDriver->Controller));
+      }
+
+    }
+
+    if (!EFI_ERROR (Status)) {
+      Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_CALLBACK,
+                      &MarvellYukonNotifyExitBoot, YukonDriver, &YukonDriver->ExitBootEvent);
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Stop this driver on Controller by removing NetworkInterfaceIdentifier protocol and
+  closing the DevicePath and PciIo protocols on Controller.
+
+  @param [in] pThis                   Protocol instance pointer.
+  @param [in] Controller              Handle of device to stop driver on.
+  @param [in] NumberOfChildren        How many children need to be stopped.
+  @param [in] pChildHandleBuffer      Not used.
+
+  @retval EFI_SUCCESS                 This driver is removed Controller.
+  @retval EFI_DEVICE_ERROR            The device could not be stopped due to a device error.
+  @retval other                       This driver was not removed from this device.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonDriverStop (
+    IN  EFI_DRIVER_BINDING_PROTOCOL * pThis,
+    IN  EFI_HANDLE Controller,
+    IN  UINTN NumberOfChildren,
+    IN  EFI_HANDLE * ChildHandleBuffer
+    )
+{
+  EFI_SIMPLE_NETWORK_PROTOCOL  *SimpleNetwork;
+  EFI_STATUS                   Status;
+  YUKON_DRIVER                 *YukonDriver;
+  EFI_TPL                      OldTpl;
+  UINTN                        ChildController;
+  struct msk_softc             *ScData;
+
+  if (pThis == NULL) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: MarvellYukonDriverStop() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (NumberOfChildren > 0 && ChildHandleBuffer == NULL) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: MarvellYukonDriverStop() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  for (ChildController = 0; ChildController < NumberOfChildren; ChildController ++) {
+
+    Status = gBS->OpenProtocol (
+          ChildHandleBuffer[ChildController],
+          &gEfiSimpleNetworkProtocolGuid,
+          (VOID **) &SimpleNetwork,
+          pThis->DriverBindingHandle,
+          Controller,
+          EFI_OPEN_PROTOCOL_GET_PROTOCOL
+          );
+
+    if (!EFI_ERROR(Status)) {
+
+      YukonDriver = YUKON_DEV_FROM_THIS_SNP (SimpleNetwork);
+
+      Status = MarvellYukonGetControllerData (YukonDriver->Controller, &ScData);
+      if (EFI_ERROR (Status)) {
+        continue;
+      }
+
+      OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+      ASSERT (YukonDriver->Controller == ChildHandleBuffer[ChildController]);
+      if (YukonDriver->SnpMode.State != EfiSimpleNetworkStopped) {
+
+         //
+         // Device in use, cannot stop driver instance
+         //
+         Status = EFI_DEVICE_ERROR;
+         DEBUG ((DEBUG_ERROR,
+                "Marvell Yukon: MarvellYukonDriverStop: Error: SNP is not stopped. Status %r\n", Status));
+       } else {
+
+         //
+         // Unhook the child controller
+         //
+         Status = gBS->CloseProtocol (Controller,
+                             &gEfiPciIoProtocolGuid,
+                             pThis->DriverBindingHandle,
+                             YukonDriver->Controller);
+
+         if (EFI_ERROR (Status)) {
+           DEBUG ((DEBUG_ERROR,
+                  "Marvell Yukon: MarvellYukonDriverStop:Close Child EfiPciIoProtocol error. Status %r\n", Status));
+         }
+
+         Status = gBS->UninstallMultipleProtocolInterfaces (
+              YukonDriver->Controller,
+              &gEfiSimpleNetworkProtocolGuid,
+              &YukonDriver->Snp,
+              &gEfiDevicePathProtocolGuid,
+              YukonDriver->DevicePath,
+              NULL
+              );
+
+         if (EFI_ERROR(Status)){
+           DEBUG ((DEBUG_ERROR,
+                  "Marvell Yukon: MarvellYukonDriverStop:UninstallMultipleProtocolInterfaces error. Status %r\n",
+                  Status));
+         }
+
+         MarvellYukonDelControllerData (YukonDriver->Controller);
+
+         gBS->CloseEvent (YukonDriver->ExitBootEvent);
+         gBS->FreePool (YukonDriver->DevicePath);
+         gBS->FreePool (YukonDriver);
+       }
+       gBS->RestoreTPL (OldTpl);
+    }
+  }
+
+  Status = gBS->CloseProtocol (
+        Controller,
+        &gEfiPciIoProtocolGuid,
+        pThis->DriverBindingHandle,
+        Controller
+        );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Marvell Yukon: MarvellYukonDriverStop:Close EfiPciIoProtocol error. Status %r\n", Status));
+  }
+
+  Status = MarvellYukonGetControllerData (Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  mskc_detach (ScData);
+  gBS->FreePool (ScData);
+  Status = MarvellYukonDelControllerData (Controller);
+
+  return Status;
+}
+
+/**
+  Process exit boot event.
+
+  @param [in] Event                   Event id.
+  @param [in] Context                 Driver context.
+
+**/
+VOID
+EFIAPI
+MarvellYukonNotifyExitBoot (
+  IN EFI_EVENT Event,
+  IN VOID *Context
+  )
+{
+  YUKON_DRIVER    *YukonDriver;
+  EFI_STATUS      Status;
+
+  if (Context == NULL) {
+    DEBUG ((DEBUG_ERROR,
+           "Marvell Yukon: MarvellYukonNotifyExitBoot() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+  } else {
+
+    YukonDriver = Context;
+
+    if (YukonDriver->SnpMode.State != EfiSimpleNetworkStopped) {
+      Status  = YukonDriver->Snp.Shutdown(&YukonDriver->Snp);
+      if (!EFI_ERROR (Status)) {
+        YukonDriver->Snp.Stop(&YukonDriver->Snp);
+      }
+    }
+  }
+}
+
+/**
+  Get driver's data structure associated with controller
+
+  @param [in] Controller           Controller Id.
+  @param [out] Data                Driver's data.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonGetControllerData (
+  IN EFI_HANDLE Controller,
+  OUT struct msk_softc **Data
+  )
+{
+  MSK_LINKED_DRV_BUF *DrvNode;
+  EFI_STATUS         Status;
+
+  Status = MarvellYukonFindControllerNode (Controller, &DrvNode);
+  if (!EFI_ERROR (Status)) {
+    *Data = DrvNode->Data;
+  }
+  return Status;
+}
+
+/**
+  Add driver's data structure associated with controller
+
+  @param [in] Controller           Controller Id.
+  @param [in] Data                 Driver's data.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonAddControllerData (
+  IN EFI_HANDLE Controller,
+  IN struct msk_softc *Data
+  )
+{
+  MSK_LINKED_DRV_BUF *DrvNode;
+  EFI_STATUS         Status;
+
+  Status = MarvellYukonFindControllerNode (Controller, &DrvNode);
+  if (EFI_ERROR (Status)) {
+    Status = gBS->AllocatePool (EfiBootServicesData,
+                                sizeof (MSK_LINKED_DRV_BUF),
+                                (VOID**) &DrvNode);
+    if (!EFI_ERROR (Status)) {
+      DrvNode->Signature = MSK_DRV_SIGNATURE;
+      DrvNode->Controller = Controller;
+      DrvNode->Data = Data;
+      InsertTailList (&MarvellYukonDrvDataHead, &DrvNode->Link);
+    }
+  } else {
+    Status = EFI_ALREADY_STARTED;
+  }
+
+  return Status;
+}
+
+/**
+  Delete driver's data structure associated with controller
+
+  @param [in] Controller           Controller Id.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonDelControllerData (
+  IN EFI_HANDLE Controller
+  )
+{
+  MSK_LINKED_DRV_BUF *DrvNode;
+  EFI_STATUS         Status;
+
+  Status = MarvellYukonFindControllerNode (Controller, &DrvNode);
+  if (!EFI_ERROR (Status)) {
+    RemoveEntryList (&DrvNode->Link);
+    gBS->FreePool (DrvNode);
+  }
+
+  return Status;
+}
+
+/**
+  Find node associated with controller
+
+  @param [in] Controller           Controller Id.
+  @param [out] DrvLinkedBuff       Controller's node.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonFindControllerNode (
+  IN EFI_HANDLE Controller,
+  OUT MSK_LINKED_DRV_BUF **DrvLinkedBuff
+  )
+{
+  MSK_LINKED_DRV_BUF *DrvBuffNode;
+  EFI_STATUS         Status;
+  LIST_ENTRY         *Node;
+
+  Status = EFI_NOT_FOUND;
+
+  Node = GetFirstNode (&MarvellYukonDrvDataHead);
+  while (!IsNull (&MarvellYukonDrvDataHead, Node)) {
+    DrvBuffNode = MSK_DRV_INFO_FROM_THIS (Node);
+    if (DrvBuffNode->Controller == Controller) {
+      *DrvLinkedBuff = DrvBuffNode;
+      Status = EFI_SUCCESS;
+      break;
+    }
+    Node = GetNextNode (&MarvellYukonDrvDataHead, Node);
+  }
+
+  return Status;
+}
+
+//
+// Simple Network Protocol Driver Global Variables
+//
+EFI_DRIVER_BINDING_PROTOCOL gMarvellYukonDriverBinding = {
+  MarvellYukonDriverSupported,
+  MarvellYukonDriverStart,
+  MarvellYukonDriverStop,
+  0xa,
+  NULL,
+  NULL
+};
+
+/**
+  The Marvell Yukon driver entry point.
+
+   <at> param ImageHandle             The driver image handle.
+   <at> param SystemTable             The system table.
+
+   <at> retval EFI_SUCCESS            Initialization routine has found and initialized
+                                      hardware successfully.
+   <at> retval Other                  Return value from HandleProtocol for
+                                      DeviceIoProtocol or LoadedImageProtocol
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeMarvellYukonDriver (
+    IN EFI_HANDLE       ImageHandle,
+    IN EFI_SYSTEM_TABLE *SystemTable
+    )
+{
+  EFI_STATUS                           Status;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: InitializeMarvellYukonDriver()\n"));
+
+  if (SystemTable == NULL) {
+    DEBUG ((DEBUG_ERROR,
+           "Marvell Yukon: InitializeMarvellYukonDriver() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = EfiLibInstallDriverBindingComponentName2 (
+        ImageHandle,
+        SystemTable,
+        &gMarvellYukonDriverBinding,
+        NULL,
+        &gSimpleNetworkComponentName,
+        &gSimpleNetworkComponentName2
+        );
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: InitializeMarvellYukonDriver(): Driver binding failed\n"));
+    return Status;
+  }
+
+  InitializeListHead (&MarvellYukonDrvDataHead);
+
+  return Status;
+}
diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukon.h b/Drivers/Net/MarvellYukonDxe/MarvellYukon.h
new file mode 100644
index 0000000..a419234
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/MarvellYukon.h
@@ -0,0 +1,782 @@
+/**
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _SNP_H_
+#define _SNP_H_
+
+
+#include <Uefi.h>
+
+#include <Protocol/SimpleNetwork.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/DevicePath.h>
+
+#include <Guid/EventGroup.h>
+
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/NetLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <IndustryStandard/Pci.h>
+
+#define YUKON_DRIVER_SIGNATURE  SIGNATURE_32 ('m', 'y', 'u', 'k')
+
+typedef struct {
+  UINT32                      Signature;
+  EFI_LOCK                    Lock;
+
+  EFI_HANDLE                  Controller;
+  UINTN                       Port;
+  EFI_EVENT                   ExitBootEvent;
+
+  EFI_SIMPLE_NETWORK_PROTOCOL Snp;
+  EFI_SIMPLE_NETWORK_MODE     SnpMode;
+
+  EFI_HANDLE                  DeviceHandle;
+  EFI_DEVICE_PATH_PROTOCOL*   DevicePath;
+  EFI_PCI_IO_PROTOCOL*        PciIo;
+
+} YUKON_DRIVER;
+
+#define YUKON_DEV_FROM_THIS_SNP(a) CR (a, YUKON_DRIVER, Snp, YUKON_DRIVER_SIGNATURE)
+
+#define SNP_MEM_PAGES(x)  (((x) - 1) / 4096 + 1)
+
+typedef struct {
+  UINT32                      Signature;
+  LIST_ENTRY                  Link;
+  EFI_HANDLE                  Controller;
+  struct msk_softc            *Data;
+} MSK_LINKED_DRV_BUF;
+
+#define MSK_DRV_SIGNATURE  SIGNATURE_32 ('m', 's', 'k', 'c')
+
+#define MSK_DRV_INFO_FROM_THIS(a) \
+  CR (a, \
+      MSK_LINKED_DRV_BUF, \
+      Link, \
+      MSK_DRV_SIGNATURE \
+      );
+
+//
+// Global Variables
+//
+extern EFI_COMPONENT_NAME_PROTOCOL    gSimpleNetworkComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL   gSimpleNetworkComponentName2;
+
+//
+// The SNP driver control functions
+//
+
+EFI_STATUS
+InitializeSNPProtocol (
+    IN OUT  YUKON_DRIVER *YukonDriver
+    );
+
+/**
+  Changes the state of a network interface from "stopped" to "started".
+
+  This function starts a network interface. If the network interface successfully
+  starts, then EFI_SUCCESS will be returned.
+
+   <at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+
+   <at> retval EFI_SUCCESS            The network interface was started.
+   <at> retval EFI_ALREADY_STARTED    The network interface is already in the started state.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                      EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpStart (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+    );
+
+/**
+  Changes the state of a network interface from "started" to "stopped".
+
+  This function stops a network interface. This call is only valid if the network
+  interface is in the started state. If the network interface was successfully
+  stopped, then EFI_SUCCESS will be returned.
+
+   <at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+
+
+   <at> retval EFI_SUCCESS            The network interface was stopped.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                      EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpStop (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+    );
+
+//
+// The SNP protocol functions
+//
+
+
+/**
+  Resets a network adapter and allocates the transmit and receive buffers
+  required by the network interface; optionally, also requests allocation of
+  additional transmit and receive buffers.
+
+  This function allocates the transmit and receive buffers required by the network
+  interface. If this allocation fails, then EFI_OUT_OF_RESOURCES is returned.
+  If the allocation succeeds and the network interface is successfully initialized,
+  then EFI_SUCCESS will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+
+   <at> param ExtraRxBufferSize       The size, in bytes, of the extra receive buffer space
+                                      that the driver should allocate for the network interface.
+                                      Some network interfaces will not be able to use the
+                                      extra buffer, and the caller will not know if it is
+                                      actually being used.
+   <at> param ExtraTxBufferSize       The size, in bytes, of the extra transmit buffer space
+                                      that the driver should allocate for the network interface.
+                                      Some network interfaces will not be able to use the
+                                      extra buffer, and the caller will not know if it is
+                                      actually being used.
+
+   <at> retval EFI_SUCCESS            The network interface was initialized.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_OUT_OF_RESOURCES   There was not enough memory for the transmit and
+                                      receive buffers.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                      EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        The increased buffer size feature is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpInitialize (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN UINTN                       ExtraRxBufferSize OPTIONAL,
+    IN UINTN                       ExtraTxBufferSize OPTIONAL
+    );
+
+/**
+  Resets a network adapter and reinitializes it with the parameters that were
+  provided in the previous call to Initialize().
+
+  This function resets a network adapter and reinitializes it with the parameters
+  that were provided in the previous call to Initialize(). The transmit and
+  receive queues are emptied and all pending interrupts are cleared.
+  Receive filters, the station address, the statistics, and the multicast-IP-to-HW
+  MAC addresses are not reset by this call. If the network interface was
+  successfully reset, then EFI_SUCCESS will be returned. If the driver has not
+  been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param ExtendedVerification    Indicates that the driver may perform a more
+                                      exhaustive verification operation of the device
+                                      during reset.
+
+   <at> retval EFI_SUCCESS            The network interface was reset.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the parameters has an unsupported value.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpReset (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL  *This,
+    IN BOOLEAN                      ExtendedVerification
+    );
+
+/**
+  Resets a network adapter and leaves it in a state that is safe for another
+  driver to initialize.
+
+  This function releases the memory buffers assigned in the Initialize() call.
+  Pending transmits and receives are lost, and interrupts are cleared and disabled.
+  After this call, only the Initialize() and Stop() calls may be used. If the
+  network interface was successfully shutdown, then EFI_SUCCESS will be returned.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param                         This  A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+
+   <at> retval EFI_SUCCESS            The network interface was shutdown.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                      EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpShutdown (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+    );
+
+/**
+  Manages the multicast receive filters of a network interface.
+
+  This function is used enable and disable the hardware and software receive
+  filters for the underlying network device.
+  The receive filter change is broken down into three steps:
+  * The filter mask bits that are set (ON) in the Enable parameter are added to
+    the current receive filter settings.
+  * The filter mask bits that are set (ON) in the Disable parameter are subtracted
+    from the updated receive filter settings.
+  * If the resulting receive filter setting is not supported by the hardware a
+    more liberal setting is selected.
+  If the same bits are set in the Enable and Disable parameters, then the bits
+  in the Disable parameter takes precedence.
+  If the ResetMCastFilter parameter is TRUE, then the multicast address list
+  filter is disabled (irregardless of what other multicast bits are set in the
+  Enable and Disable parameters). The SNP->SnpMode->MCastFilterCount field is set
+  to zero. The Snp->SnpMode->MCastFilter contents are undefined.
+  After enabling or disabling receive filter settings, software should verify
+  the new settings by checking the Snp->SnpMode->ReceiveFilterSettings,
+  Snp->SnpMode->MCastFilterCount and Snp->SnpMode->MCastFilter fields.
+  Note: Some network drivers and/or devices will automatically promote receive
+    filter settings if the requested setting can not be honored. For example, if
+    a request for four multicast addresses is made and the underlying hardware
+    only supports two multicast addresses the driver might set the promiscuous
+    or promiscuous multicast receive filters instead. The receiving software is
+    responsible for discarding any extra packets that get through the hardware
+    receive filters.
+    Note: Note: To disable all receive filter hardware, the network driver must
+      be Shutdown() and Stopped(). Calling ReceiveFilters() with Disable set to
+      Snp->SnpMode->ReceiveFilterSettings will make it so no more packets are
+      returned by the Receive() function, but the receive hardware may still be
+      moving packets into system memory before inspecting and discarding them.
+      Unexpected system errors, reboots and hangs can occur if an OS is loaded
+      and the network devices are not Shutdown() and Stopped().
+  If ResetMCastFilter is TRUE, then the multicast receive filter list on the
+  network interface will be reset to the default multicast receive filter list.
+  If ResetMCastFilter is FALSE, and this network interface allows the multicast
+  receive filter list to be modified, then the MCastFilterCnt and MCastFilter
+  are used to update the current multicast receive filter list. The modified
+  receive filter list settings can be found in the MCastFilter field of
+  EFI_SIMPLE_NETWORK_MODE. If the network interface does not allow the multicast
+  receive filter list to be modified, then EFI_INVALID_PARAMETER will be returned.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+  If the receive filter mask and multicast receive filter list have been
+  successfully updated on the network interface, EFI_SUCCESS will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param Enable                  A bit mask of receive filters to enable on the network
+                                      interface.
+   <at> param Disable                 A bit mask of receive filters to disable on the network
+                                      interface. For backward compatibility with EFI 1.1
+                                      platforms, the EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit
+                                      must be set when the ResetMCastFilter parameter is TRUE.
+   <at> param ResetMCastFilter        Set to TRUE to reset the contents of the multicast
+                                      receive filters on the network interface to their
+                                      default values.
+   <at> param MCastFilterCnt          Number of multicast HW MAC addresses in the new MCastFilter
+                                      list. This value must be less than or equal to the
+                                      MCastFilterCnt field of EFI_SIMPLE_NETWORK_MODE.
+                                      This field is optional if ResetMCastFilter is TRUE.
+   <at> param MCastFilter             A pointer to a list of new multicast receive filter HW
+                                      MAC addresses. This list will replace any existing
+                                      multicast HW MAC address list. This field is optional
+                                      if ResetMCastFilter is TRUE.
+
+   <at> retval EFI_SUCCESS            The multicast receive filter list was updated.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
+                                      * This is NULL
+                                      * There are bits set in Enable that are not set
+                                        in Snp->SnpMode->ReceiveFilterMask
+                                      * There are bits set in Disable that are not set
+                                        in Snp->SnpMode->ReceiveFilterMask
+                                      * Multicast is being enabled (the
+                                        EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit is
+                                        set in Enable, it is not set in Disable, and
+                                        ResetMCastFilter is FALSE) and MCastFilterCount
+                                        is zero
+                                      * Multicast is being enabled and MCastFilterCount
+                                        is greater than Snp->SnpMode->MaxMCastFilterCount
+                                      * Multicast is being enabled and MCastFilter is NULL
+                                      * Multicast is being enabled and one or more of
+                                        the addresses in the MCastFilter list are not
+                                        valid multicast MAC addresses
+   <at> retval EFI_DEVICE_ERROR       One or more of the following conditions is TRUE:
+                                      * The network interface has been started but has
+                                        not been initialized
+                                      * An unexpected error was returned by the
+                                        underlying network driver or device
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network
+                                      interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpReceiveFilters (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN UINT32                      Enable,
+    IN UINT32                      Disable,
+    IN BOOLEAN                     ResetMCastFilter,
+    IN UINTN                       MCastFilterCnt,  OPTIONAL
+    IN EFI_MAC_ADDRESS             *MCastFilter     OPTIONAL
+    );
+
+/**
+  Modifies or resets the current station address, if supported.
+
+  This function modifies or resets the current station address of a network
+  interface, if supported. If Reset is TRUE, then the current station address is
+  set to the network interface's permanent address. If Reset is FALSE, and the
+  network interface allows its station address to be modified, then the current
+  station address is changed to the address specified by New. If the network
+  interface does not allow its station address to be modified, then
+  EFI_INVALID_PARAMETER will be returned. If the station address is successfully
+  updated on the network interface, EFI_SUCCESS will be returned. If the driver
+  has not been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param This  A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param Reset Flag used to reset the station address to the network interface's
+               permanent address.
+   <at> param New   New station address to be used for the network interface.
+
+
+   <at> retval EFI_SUCCESS            The network interface's station address was updated.
+   <at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not been
+                                      started by calling Start().
+   <at> retval EFI_INVALID_PARAMETER  The New station address was not accepted by the NIC.
+   <at> retval EFI_INVALID_PARAMETER  Reset is FALSE and New is NULL.
+   <at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
+                                      been initialized by calling Initialize().
+   <at> retval EFI_DEVICE_ERROR       An error occurred attempting to set the new
+                                      station address.
+   <at> retval EFI_UNSUPPORTED        The NIC does not support changing the network
+                                      interface's station address.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpStationAddress (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     Reset,
+    IN EFI_MAC_ADDRESS             *New  OPTIONAL
+    );
+
+/**
+  Resets or collects the statistics on a network interface.
+
+  This function resets or collects the statistics on a network interface. If the
+  size of the statistics table specified by StatisticsSize is not big enough for
+  all the statistics that are collected by the network interface, then a partial
+  buffer of statistics is returned in StatisticsTable, StatisticsSize is set to
+  the size required to collect all the available statistics, and
+  EFI_BUFFER_TOO_SMALL is returned.
+  If StatisticsSize is big enough for all the statistics, then StatisticsTable
+  will be filled, StatisticsSize will be set to the size of the returned
+  StatisticsTable structure, and EFI_SUCCESS is returned.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+  If Reset is FALSE, and both StatisticsSize and StatisticsTable are NULL, then
+  no operations will be performed, and EFI_SUCCESS will be returned.
+  If Reset is TRUE, then all of the supported statistics counters on this network
+  interface will be reset to zero.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param Reset                   Set to TRUE to reset the statistics for the network interface.
+   <at> param StatisticsSize          On input the size, in bytes, of StatisticsTable. On output
+                                      the size, in bytes, of the resulting table of statistics.
+   <at> param StatisticsTable         A pointer to the EFI_NETWORK_STATISTICS structure that
+                                      contains the statistics. Type EFI_NETWORK_STATISTICS is
+                                      defined in "Related Definitions" below.
+
+   <at> retval EFI_SUCCESS            The requested operation succeeded.
+   <at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not been
+                                      started by calling Start().
+   <at> retval EFI_BUFFER_TOO_SMALL   StatisticsSize is not NULL and StatisticsTable is
+                                      NULL. The current buffer size that is needed to
+                                      hold all the statistics is returned in StatisticsSize.
+   <at> retval EFI_BUFFER_TOO_SMALL   StatisticsSize is not NULL and StatisticsTable is
+                                      not NULL. The current buffer size that is needed
+                                      to hold all the statistics is returned in
+                                      StatisticsSize. A partial set of statistics is
+                                      returned in StatisticsTable.
+   <at> retval EFI_INVALID_PARAMETER  StatisticsSize is NULL and StatisticsTable is not
+                                      NULL.
+   <at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
+                                      been initialized by calling Initialize().
+   <at> retval EFI_DEVICE_ERROR       An error was encountered collecting statistics
+                                      from the NIC.
+   <at> retval EFI_UNSUPPORTED        The NIC does not support collecting statistics
+                                      from the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpStatistics (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     Reset,
+    IN OUT UINTN                   *StatisticsSize,  OPTIONAL
+    IN OUT EFI_NETWORK_STATISTICS  *StatisticsTable  OPTIONAL
+    );
+
+/**
+  Converts a multicast IP address to a multicast HW MAC address.
+
+  This function converts a multicast IP address to a multicast HW MAC address
+  for all packet transactions. If the mapping is accepted, then EFI_SUCCESS will
+  be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param IPv6                    Set to TRUE if the multicast IP address is IPv6 [RFC 2460].
+                                      Set to FALSE if the multicast IP address is IPv4 [RFC 791].
+   <at> param IP                      The multicast IP address that is to be converted to a multicast
+                                      HW MAC address.
+   <at> param MAC                     The multicast HW MAC address that is to be generated from IP.
+
+   <at> retval EFI_SUCCESS            The multicast IP address was mapped to the
+                                      multicast HW MAC address.
+   <at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not
+                                      been started by calling Start().
+   <at> retval EFI_INVALID_PARAMETER  IP is NULL.
+   <at> retval EFI_INVALID_PARAMETER  MAC is NULL.
+   <at> retval EFI_INVALID_PARAMETER  IP does not point to a valid IPv4 or IPv6
+                                      multicast address.
+   <at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
+                                      been initialized by calling Initialize().
+   <at> retval EFI_UNSUPPORTED        IPv6 is TRUE and the implementation does not
+                                      support IPv6 multicast to MAC address conversion.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpMcastIpToMac (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     IPv6,
+    IN EFI_IP_ADDRESS              *IP,
+    OUT EFI_MAC_ADDRESS            *MAC
+    );
+
+/**
+  Performs read and write operations on the NVRAM device attached to a network
+  interface.
+
+  This function performs read and write operations on the NVRAM device attached
+  to a network interface. If ReadWrite is TRUE, a read operation is performed.
+  If ReadWrite is FALSE, a write operation is performed. Offset specifies the
+  byte offset at which to start either operation. Offset must be a multiple of
+  NvRamAccessSize , and it must have a value between zero and NvRamSize.
+  BufferSize specifies the length of the read or write operation. BufferSize must
+  also be a multiple of NvRamAccessSize, and Offset + BufferSize must not exceed
+  NvRamSize.
+  If any of the above conditions is not met, then EFI_INVALID_PARAMETER will be
+  returned.
+  If all the conditions are met and the operation is "read," the NVRAM device
+  attached to the network interface will be read into Buffer and EFI_SUCCESS
+  will be returned. If this is a write operation, the contents of Buffer will be
+  used to update the contents of the NVRAM device attached to the network
+  interface and EFI_SUCCESS will be returned.
+
+  It does the basic checking on the input parameters and retrieves snp structure
+  and then calls the read_nvdata() call which does the actual reading
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param ReadWrite               TRUE for read operations, FALSE for write operations.
+   <at> param Offset                  Byte offset in the NVRAM device at which to start the read or
+                                      write operation. This must be a multiple of NvRamAccessSize
+                                      and less than NvRamSize. (See EFI_SIMPLE_NETWORK_MODE)
+   <at> param BufferSize              The number of bytes to read or write from the NVRAM device.
+                                      This must also be a multiple of NvramAccessSize.
+   <at> param Buffer                  A pointer to the data buffer.
+
+   <at> retval EFI_SUCCESS            The NVRAM access was performed.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
+                                      * The This parameter is NULL
+                                      * The This parameter does not point to a valid
+                                        EFI_SIMPLE_NETWORK_PROTOCOL  structure
+                                      * The Offset parameter is not a multiple of
+                                        EFI_SIMPLE_NETWORK_MODE.NvRamAccessSize
+                                      * The Offset parameter is not less than
+                                        EFI_SIMPLE_NETWORK_MODE.NvRamSize
+                                      * The BufferSize parameter is not a multiple of
+                                        EFI_SIMPLE_NETWORK_MODE.NvRamAccessSize
+                                      * The Buffer parameter is NULL
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
+                                      interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network
+                                      interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpNvData (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     ReadWrite,
+    IN UINTN                       Offset,
+    IN UINTN                       BufferSize,
+    IN OUT VOID                    *Buffer
+    );
+
+/**
+  Reads the current interrupt status and recycled transmit buffer status from a
+  network interface.
+
+  This function gets the current interrupt and recycled transmit buffer status
+  from the network interface. The interrupt status is returned as a bit mask in
+  InterruptStatus. If InterruptStatus is NULL, the interrupt status will not be
+  read. If TxBuf is not NULL, a recycled transmit buffer address will be retrieved.
+  If a recycled transmit buffer address is returned in TxBuf, then the buffer has
+  been successfully transmitted, and the status for that buffer is cleared. If
+  the status of the network interface is successfully collected, EFI_SUCCESS
+  will be returned. If the driver has not been initialized, EFI_DEVICE_ERROR will
+  be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param InterruptStatus         A pointer to the bit mask of the currently active
+                                      interrupts (see "Related Definitions"). If this is NULL,
+                                      the interrupt status will not be read from the device.
+                                      If this is not NULL, the interrupt status will be read
+                                      from the device. When the interrupt status is read, it
+                                      will also be cleared. Clearing the transmit interrupt does
+                                      not empty the recycled transmit buffer array.
+   <at> param TxBuf                   Recycled transmit buffer address. The network interface
+                                      will not transmit if its internal recycled transmit
+                                      buffer array is full. Reading the transmit buffer does
+                                      not clear the transmit interrupt. If this is NULL, then
+                                      the transmit buffer status will not be read. If there
+                                      are no transmit buffers to recycle and TxBuf is not NULL,
+                                      TxBuf will be set to NULL.
+
+   <at> retval EFI_SUCCESS            The status of the network interface was retrieved.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                      EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
+                                      interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpGetStatus (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    OUT UINT32                     *InterruptStatus, OPTIONAL
+    OUT VOID                       **TxBuf           OPTIONAL
+    );
+
+/**
+  Places a packet in the transmit queue of a network interface.
+
+  This function places the packet specified by Header and Buffer on the transmit
+  queue. If HeaderSize is nonzero and HeaderSize is not equal to
+  This->SnpMode->MediaHeaderSize, then EFI_INVALID_PARAMETER will be returned. If
+  BufferSize is less than This->SnpMode->MediaHeaderSize, then EFI_BUFFER_TOO_SMALL
+  will be returned. If Buffer is NULL, then EFI_INVALID_PARAMETER will be
+  returned. If HeaderSize is nonzero and DestAddr or Protocol is NULL, then
+  EFI_INVALID_PARAMETER will be returned. If the transmit engine of the network
+  interface is busy, then EFI_NOT_READY will be returned. If this packet can be
+  accepted by the transmit engine of the network interface, the packet contents
+  specified by Buffer will be placed on the transmit queue of the network
+  interface, and EFI_SUCCESS will be returned. GetStatus() can be used to
+  determine when the packet has actually been transmitted. The contents of the
+  Buffer must not be modified until the packet has actually been transmitted.
+  The Transmit() function performs nonblocking I/O. A caller who wants to perform
+  blocking I/O, should call Transmit(), and then GetStatus() until the
+  transmitted buffer shows up in the recycled transmit buffer.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param HeaderSize              The size, in bytes, of the media header to be filled in by the
+                                      Transmit() function. If HeaderSize is nonzero, then it must
+                                      be equal to This->SnpMode->MediaHeaderSize and the DestAddr and
+                                      Protocol parameters must not be NULL.
+   <at> param BufferSize              The size, in bytes, of the entire packet (media header and
+                                      data) to be transmitted through the network interface.
+   <at> param Buffer                  A pointer to the packet (media header followed by data) to be
+                                      transmitted. This parameter cannot be NULL. If HeaderSize is
+                                      zero, then the media header in Buffer must already be filled
+                                      in by the caller. If HeaderSize is nonzero, then the media
+                                      header will be filled in by the Transmit() function.
+   <at> param SrcAddr                 The source HW MAC address. If HeaderSize is zero, then this
+                                      parameter is ignored. If HeaderSize is nonzero and SrcAddr
+                                      is NULL, then This->SnpMode->CurrentAddress is used for the
+                                      source HW MAC address.
+   <at> param DestAddr                The destination HW MAC address. If HeaderSize is zero, then
+                                      this parameter is ignored.
+   <at> param Protocol                The type of header to build. If HeaderSize is zero, then this
+                                      parameter is ignored. See RFC 1700, section "Ether Types,"
+                                      for examples.
+
+   <at> retval EFI_SUCCESS            The packet was placed on the transmit queue.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_NOT_READY          The network interface is too busy to accept this
+                                      transmit request.
+   <at> retval EFI_BUFFER_TOO_SMALL   The BufferSize parameter is too small.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the parameters has an unsupported
+                                      value.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpTransmit (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN UINTN                       HeaderSize,
+    IN UINTN                       BufferSize,
+    IN VOID                        *Buffer,
+    IN EFI_MAC_ADDRESS             *SrcAddr,  OPTIONAL
+    IN EFI_MAC_ADDRESS             *DestAddr, OPTIONAL
+    IN UINT16                      *Protocol  OPTIONAL
+    );
+
+/**
+  Receives a packet from a network interface.
+
+  This function retrieves one packet from the receive queue of a network interface.
+  If there are no packets on the receive queue, then EFI_NOT_READY will be
+  returned. If there is a packet on the receive queue, and the size of the packet
+  is smaller than BufferSize, then the contents of the packet will be placed in
+  Buffer, and BufferSize will be updated with the actual size of the packet.
+  In addition, if SrcAddr, DestAddr, and Protocol are not NULL, then these values
+  will be extracted from the media header and returned. EFI_SUCCESS will be
+  returned if a packet was successfully received.
+  If BufferSize is smaller than the received packet, then the size of the receive
+  packet will be placed in BufferSize and EFI_BUFFER_TOO_SMALL will be returned.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param HeaderSize              The size, in bytes, of the media header received on the network
+                                      interface. If this parameter is NULL, then the media header size
+                                      will not be returned.
+   <at> param BufferSize              On entry, the size, in bytes, of Buffer. On exit, the size, in
+                                      bytes, of the packet that was received on the network interface.
+   <at> param Buffer                  A pointer to the data buffer to receive both the media
+                                      header and the data.
+   <at> param SrcAddr                 The source HW MAC address. If this parameter is NULL, the HW
+                                      MAC source address will not be extracted from the media header.
+   <at> param DestAddr                The destination HW MAC address. If this parameter is NULL,
+                                      the HW MAC destination address will not be extracted from
+                                      the media header.
+   <at> param Protocol                The media header type. If this parameter is NULL, then the
+                                      protocol will not be extracted from the media header. See
+                                      RFC 1700 section "Ether Types" for examples.
+
+   <at> retval EFI_SUCCESS            The received data was stored in Buffer, and
+                                      BufferSize has been updated to the number of
+                                      bytes received.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_NOT_READY          No packets have been received on the network interface.
+   <at> retval EFI_BUFFER_TOO_SMALL   BufferSize is too small for the received packets.
+                                      BufferSize has been updated to the required size.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
+                                      * The This parameter is NULL
+                                      * The This parameter does not point to a valid
+                                        EFI_SIMPLE_NETWORK_PROTOCOL structure.
+                                      * The BufferSize parameter is NULL
+                                      * The Buffer parameter is NULL
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpReceive (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    OUT UINTN                      *HeaderSize OPTIONAL,
+    IN OUT UINTN                   *BufferSize,
+    OUT VOID                       *Buffer,
+    OUT EFI_MAC_ADDRESS            *SrcAddr OPTIONAL,
+    OUT EFI_MAC_ADDRESS            *DestAddr OPTIONAL,
+    OUT UINT16                     *Protocol OPTIONAL
+    );
+
+#endif
+
+/**
+  Process exit boot event.
+
+  @param [in] Event                   Event id.
+  @param [in] Context                 Driver context.
+
+**/
+VOID
+EFIAPI
+MarvellYukonNotifyExitBoot (
+  IN EFI_EVENT Event,
+  IN VOID *Context
+  );
+
+/**
+  Get driver's data structure associated with controller
+
+  @param [in] Controller           Controller Id.
+  @param [out] Data                Driver's data.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonGetControllerData (
+  IN EFI_HANDLE Controller,
+  OUT struct msk_softc **Data
+  );
+
+/**
+  Add driver's data structure associated with controller
+
+  @param [in] Controller           Controller Id.
+  @param [in] Data                 Driver's data.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonAddControllerData (
+  IN EFI_HANDLE Controller,
+  IN struct msk_softc *
+  );
+
+/**
+  Delete driver's data structure associated with controller
+
+  @param [in] Controller           Controller Id.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonDelControllerData (
+  IN EFI_HANDLE Controller
+  );
+
+/**
+  Find node associated with controller
+
+  @param [in] Controller           Controller Id.
+  @param [out] DrvLinkedBuff       Controller's node.
+
+**/
+EFI_STATUS
+EFIAPI
+MarvellYukonFindControllerNode (
+  IN EFI_HANDLE Controller,
+  OUT MSK_LINKED_DRV_BUF **DrvLinkedBuff
+  );
+
+/*  _SNP_H_  */
diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc
new file mode 100644
index 0000000..2411041
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc
@@ -0,0 +1,88 @@
+#
+#  Copyright (c) 2013-2016, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = MarvellYukonDxe
+  PLATFORM_GUID                  = 8391d2d4-63fc-11e6-82d5-7b6c1a2ff410
+  PLATFORM_VERSION               = 0.96
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/OpenPlatformPkg
+  SUPPORTED_ARCHITECTURES        = IA32|IPF|X64|EBC|ARM|AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
+  SKUID_IDENTIFIER               = DEFAULT
+
+[LibraryClasses]
+  #
+  # Entry point
+  #
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  #
+  # Basic
+  #
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  #
+  # UEFI & PI
+  #
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  #
+  # Generic Modules
+  #
+  TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  #
+  # Misc
+  #
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+
+[LibraryClasses.common.UEFI_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
+
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
+  #
+  # It is not possible to prevent ARM compiler calls to generic intrinsic functions.
+  # This library provides the instrinsic functions generated by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.EBC]
+  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+[PcdsFeatureFlag]
+
+[PcdsFixedAtBuild]
+
+[PcdsFixedAtBuild.IPF]
+
+###################################################################################################
+#
+# Components Section - list of all EDK II Modules included in the build
+#
+###################################################################################################
+
+[Components]
+  OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
new file mode 100644
index 0000000..54ef18b
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
@@ -0,0 +1,65 @@
+##  <at> file
+# Component description file for Marvell Yukon II SNP module.
+#
+# Copyright (c) 2011-2016, ARM Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed
+# and made available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MarvellYukonDxe
+  FILE_GUID                      = d7de5d0c-99f8-4970-b85c-c19df8997d7d
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeMarvellYukonDriver
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  DRIVER_BINDING                =  gMarvellYukonDriverBinding
+#  COMPONENT_NAME                =  gSimpleNetworkComponentName
+#  COMPONENT_NAME2               =  gSimpleNetworkComponentName2
+#
+
+[Sources]
+  Snp.c
+  DriverBinding.c
+  ComponentName.c
+  e1000phy.c
+  if_msk.c
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  NetworkPkg/NetworkPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  DevicePathLib
+  IoLib
+  MemoryAllocationLib
+  NetLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Protocols]
+  gEfiDevicePathProtocolGuid
+  gEfiMetronomeArchProtocolGuid
+  gEfiPciIoProtocolGuid
+  gEfiPxeBaseCodeProtocolGuid
+  gEfiSimpleNetworkProtocolGuid
+
+[Depex]
+  TRUE
diff --git a/Drivers/Net/MarvellYukonDxe/Snp.c b/Drivers/Net/MarvellYukonDxe/Snp.c
new file mode 100644
index 0000000..f2f173f
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/Snp.c
@@ -0,0 +1,1468 @@
+/**  <at> file
+Provides the Simple Network functions.
+
+Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
+
+This program and the accompanying materials are licensed
+and made available under the terms and conditions of the BSD License which
+accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "MarvellYukon.h"
+#include "if_msk.h"
+
+EFI_STATUS
+InitializeSNPProtocol (
+    IN OUT  YUKON_DRIVER *YukonDriver
+    )
+{
+  EFI_STATUS    Status;
+
+  Status = RETURN_SUCCESS;
+
+  YukonDriver->Snp.Revision       = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
+  YukonDriver->Snp.Start          = SnpStart;
+  YukonDriver->Snp.Stop           = SnpStop;
+  YukonDriver->Snp.Initialize     = SnpInitialize;
+  YukonDriver->Snp.Reset          = SnpReset;
+  YukonDriver->Snp.Shutdown       = SnpShutdown;
+  YukonDriver->Snp.ReceiveFilters = SnpReceiveFilters;
+  YukonDriver->Snp.StationAddress = SnpStationAddress;
+  YukonDriver->Snp.Statistics     = SnpStatistics;
+  YukonDriver->Snp.MCastIpToMac   = SnpMcastIpToMac;
+  YukonDriver->Snp.NvData         = SnpNvData;
+  YukonDriver->Snp.GetStatus      = SnpGetStatus;
+  YukonDriver->Snp.Transmit       = SnpTransmit;
+  YukonDriver->Snp.Receive        = SnpReceive;
+  YukonDriver->Snp.WaitForPacket  = NULL;
+
+  YukonDriver->Snp.Mode           = &YukonDriver->SnpMode;
+
+  //
+  //  Initialize simple network protocol mode structure
+  //
+  YukonDriver->SnpMode.State               = EfiSimpleNetworkStopped;
+  YukonDriver->SnpMode.HwAddressSize       = NET_ETHER_ADDR_LEN;
+  YukonDriver->SnpMode.MediaHeaderSize     = sizeof (ETHER_HEAD);
+  YukonDriver->SnpMode.MaxPacketSize       = MAX_SUPPORTED_PACKET_SIZE;
+  YukonDriver->SnpMode.NvRamAccessSize     = 0;
+  YukonDriver->SnpMode.NvRamSize           = 0;
+  YukonDriver->SnpMode.IfType              = NET_IFTYPE_ETHERNET;
+  YukonDriver->SnpMode.MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
+  YukonDriver->SnpMode.MCastFilterCount    = 0;
+  gBS->SetMem (&YukonDriver->SnpMode.MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS), 0);
+
+  //
+  //  Set broadcast address
+  //
+  gBS->SetMem (&YukonDriver->SnpMode.BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
+
+  YukonDriver->SnpMode.MediaPresentSupported = FALSE;
+  YukonDriver->SnpMode.MacAddressChangeable = FALSE;
+  YukonDriver->SnpMode.MultipleTxSupported = FALSE;
+  YukonDriver->SnpMode.ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST;
+  YukonDriver->SnpMode.ReceiveFilterSetting = 0;
+
+  YukonDriver->SnpMode.MediaPresent = TRUE;
+
+  return Status;
+}
+
+/**
+  Reads the current interrupt status and recycled transmit buffer status from a
+  network interface.
+
+  This function gets the current interrupt and recycled transmit buffer status
+  from the network interface. The interrupt status is returned as a bit mask in
+  InterruptStatus. If InterruptStatus is NULL, the interrupt status will not be
+  read. If TxBuf is not NULL, a recycled transmit buffer address will be retrieved.
+  If a recycled transmit buffer address is returned in TxBuf, then the buffer has
+  been successfully transmitted, and the status for that buffer is cleared. If
+  the status of the network interface is successfully collected, EFI_SUCCESS
+  will be returned. If the driver has not been initialized, EFI_DEVICE_ERROR will
+  be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param InterruptStatus         A pointer to the bit mask of the currently active
+                                      interrupts (see "Related Definitions"). If this is NULL,
+                                      the interrupt status will not be read from the device.
+                                      If this is not NULL, the interrupt status will be read
+                                      from the device. When the interrupt status is read, it
+                                      will also be cleared. Clearing the transmit interrupt does
+                                      not empty the recycled transmit buffer array.
+   <at> param TxBuf                   Recycled transmit buffer address. The network interface
+                                      will not transmit if its internal recycled transmit
+                                      buffer array is full. Reading the transmit buffer does
+                                      not clear the transmit interrupt. If this is NULL, then
+                                      the transmit buffer status will not be read. If there
+                                      are no transmit buffers to recycle and TxBuf is not NULL,
+                                      TxBuf will be set to NULL.
+
+   <at> retval EFI_SUCCESS            The status of the network interface was retrieved.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                      EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
+                                      interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpGetStatus (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    OUT UINT32                     *InterruptStatus, OPTIONAL
+    OUT VOID                       **TxBuf           OPTIONAL
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *Snp;
+  EFI_TPL       OldTpl;
+  struct msk_softc *ScData;
+
+  if (This == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Snp = YUKON_DEV_FROM_THIS_SNP (This);
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = MarvellYukonGetControllerData (Snp->Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (Snp->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_EXIT;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_EXIT;
+  }
+
+  mskc_getstatus (ScData->msk_if[Snp->Port], InterruptStatus, TxBuf);
+  Status = EFI_SUCCESS;
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+
+  return Status;
+}
+
+/**
+  Resets a network adapter and allocates the transmit and receive buffers
+  required by the network interface; optionally, also requests allocation of
+  additional transmit and receive buffers.
+
+  This function allocates the transmit and receive buffers required by the network
+  interface. If this allocation fails, then EFI_OUT_OF_RESOURCES is returned.
+  If the allocation succeeds and the network interface is successfully initialized,
+  then EFI_SUCCESS will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+
+   <at> param ExtraRxBufferSize       The size, in bytes, of the extra receive buffer space
+                                      that the driver should allocate for the network interface.
+                                      Some network interfaces will not be able to use the
+                                      extra buffer, and the caller will not know if it is
+                                      actually being used.
+   <at> param ExtraTxBufferSize       The size, in bytes, of the extra transmit buffer space
+                                      that the driver should allocate for the network interface.
+                                      Some network interfaces will not be able to use the
+                                      extra buffer, and the caller will not know if it is
+                                      actually being used.
+
+   <at> retval EFI_SUCCESS            The network interface was initialized.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_OUT_OF_RESOURCES   There was not enough memory for the transmit and
+                                      receive buffers.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                                                   EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        The increased buffer size feature is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpInitialize (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN UINTN                       ExtraRxBufferSize OPTIONAL,
+    IN UINTN                       ExtraTxBufferSize OPTIONAL
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+  struct msk_softc *ScData;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpInitialize()\n"));
+  if (This == NULL) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpInitialize() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  Status = MarvellYukonGetControllerData (YukonDriver->Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkStarted:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_ERROR_RESTORE_TPL;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_ERROR_RESTORE_TPL;
+  }
+
+  YukonDriver->SnpMode.MCastFilterCount      = 0;
+  YukonDriver->SnpMode.ReceiveFilterSetting  = 0;
+  gBS->SetMem (YukonDriver->SnpMode.MCastFilter, sizeof YukonDriver->SnpMode.MCastFilter, 0);
+  gBS->CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS));
+
+  Status = mskc_init (ScData->msk_if[YukonDriver->Port]);
+
+  if (EFI_ERROR (Status)) {
+     goto ON_ERROR_RESTORE_TPL;
+  }
+
+  YukonDriver->SnpMode.State = EfiSimpleNetworkInitialized;
+  goto ON_EXIT;
+
+ON_ERROR_RESTORE_TPL:
+  DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpInitialize() failed with Status = %r\n", Status));
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+}
+
+/**
+  Converts a multicast IP address to a multicast HW MAC address.
+
+  This function converts a multicast IP address to a multicast HW MAC address
+  for all packet transactions. If the mapping is accepted, then EFI_SUCCESS will
+  be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param IPv6                    Set to TRUE if the multicast IP address is IPv6 [RFC 2460].
+                                      Set to FALSE if the multicast IP address is IPv4 [RFC 791].
+   <at> param IP                      The multicast IP address that is to be converted to a multicast
+                                      HW MAC address.
+   <at> param MAC                     The multicast HW MAC address that is to be generated from IP.
+
+   <at> retval EFI_SUCCESS            The multicast IP address was mapped to the
+                                      multicast HW MAC address.
+   <at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not
+                                      been started by calling Start().
+   <at> retval EFI_INVALID_PARAMETER  IP is NULL.
+   <at> retval EFI_INVALID_PARAMETER  MAC is NULL.
+   <at> retval EFI_INVALID_PARAMETER  IP does not point to a valid IPv4 or IPv6
+                                      multicast address.
+   <at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
+                                      been initialized by calling Initialize().
+   <at> retval EFI_UNSUPPORTED        IPv6 is TRUE and the implementation does not
+                                      support IPv6 multicast to MAC address conversion.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpMcastIpToMac (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     IPv6,
+    IN EFI_IP_ADDRESS              *IP,
+    OUT EFI_MAC_ADDRESS            *MAC
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpMcastIpToMac()\n"));
+
+  //
+  // Get pointer to SNP driver instance for *this.
+  //
+  if (This == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (IP == NULL || MAC == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_EXIT;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_EXIT;
+  }
+
+  Status = EFI_UNSUPPORTED;
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+
+  return Status;
+}
+
+/**
+  Performs read and write operations on the NVRAM device attached to a network
+  interface.
+
+  This function performs read and write operations on the NVRAM device attached
+  to a network interface. If ReadWrite is TRUE, a read operation is performed.
+  If ReadWrite is FALSE, a write operation is performed. Offset specifies the
+  byte offset at which to start either operation. Offset must be a multiple of
+  NvRamAccessSize , and it must have a value between zero and NvRamSize.
+  BufferSize specifies the length of the read or write operation. BufferSize must
+  also be a multiple of NvRamAccessSize, and Offset + BufferSize must not exceed
+  NvRamSize.
+  If any of the above conditions is not met, then EFI_INVALID_PARAMETER will be
+  returned.
+  If all the conditions are met and the operation is "read," the NVRAM device
+  attached to the network interface will be read into Buffer and EFI_SUCCESS
+  will be returned. If this is a write operation, the contents of Buffer will be
+  used to update the contents of the NVRAM device attached to the network
+  interface and EFI_SUCCESS will be returned.
+
+  It does the basic checking on the input parameters and retrieves snp structure
+  and then calls the read_nvdata() call which does the actual reading
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param ReadWrite               TRUE for read operations, FALSE for write operations.
+   <at> param Offset                  Byte offset in the NVRAM device at which to start the read or
+                                      write operation. This must be a multiple of NvRamAccessSize
+                                      and less than NvRamSize. (See EFI_SIMPLE_NETWORK_MODE)
+   <at> param BufferSize              The number of bytes to read or write from the NVRAM device.
+                                      This must also be a multiple of NvramAccessSize.
+   <at> param Buffer                  A pointer to the data buffer.
+
+   <at> retval EFI_SUCCESS            The NVRAM access was performed.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
+                                      * The This parameter is NULL
+                                      * The This parameter does not point to a valid
+                                        EFI_SIMPLE_NETWORK_PROTOCOL  structure
+                                      * The Offset parameter is not a multiple of
+                                        EFI_SIMPLE_NETWORK_MODE.NvRamAccessSize
+                                      * The Offset parameter is not less than
+                                        EFI_SIMPLE_NETWORK_MODE.NvRamSize
+                                      * The BufferSize parameter is not a multiple of
+                                        EFI_SIMPLE_NETWORK_MODE.NvRamAccessSize
+                                      * The Buffer parameter is NULL
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
+                                      interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network
+                                      interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpNvData (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     ReadWrite,
+    IN UINTN                       Offset,
+    IN UINTN                       BufferSize,
+    IN OUT VOID                    *Buffer
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpNvData()\n"));
+  //
+  // Get pointer to SNP driver instance for *this.
+  //
+  if (This == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  //
+  // Return error if the SNP is not initialized.
+  //
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_EXIT;
+
+    case EfiSimpleNetworkStarted:
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_EXIT;
+  }
+  //
+  // Return error if non-volatile memory variables are not valid.
+  //
+  if (YukonDriver->SnpMode.NvRamSize == 0 || YukonDriver->SnpMode.NvRamAccessSize == 0) {
+    Status = EFI_UNSUPPORTED;
+    goto ON_EXIT;
+  }
+  //
+  // Check for invalid parameter combinations.
+  //
+  if ((BufferSize == 0) ||
+      (Buffer == NULL) ||
+      (Offset >= YukonDriver->SnpMode.NvRamSize) ||
+      (Offset + BufferSize > YukonDriver->SnpMode.NvRamSize) ||
+      (BufferSize % YukonDriver->SnpMode.NvRamAccessSize != 0) ||
+      (Offset % YukonDriver->SnpMode.NvRamAccessSize != 0)
+      ) {
+    Status = EFI_INVALID_PARAMETER;
+    goto ON_EXIT;
+  }
+
+  Status = EFI_UNSUPPORTED;
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+
+  return Status;
+}
+
+/**
+  Receives a packet from a network interface.
+
+  This function retrieves one packet from the receive queue of a network interface.
+  If there are no packets on the receive queue, then EFI_NOT_READY will be
+  returned. If there is a packet on the receive queue, and the size of the packet
+  is smaller than BufferSize, then the contents of the packet will be placed in
+  Buffer, and BufferSize will be updated with the actual size of the packet.
+  In addition, if SrcAddr, DestAddr, and Protocol are not NULL, then these values
+  will be extracted from the media header and returned. EFI_SUCCESS will be
+  returned if a packet was successfully received.
+  If BufferSize is smaller than the received packet, then the size of the receive
+  packet will be placed in BufferSize and EFI_BUFFER_TOO_SMALL will be returned.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param HeaderSize              The size, in bytes, of the media header received on the network
+                                      interface. If this parameter is NULL, then the media header size
+                                      will not be returned.
+   <at> param BufferSize              On entry, the size, in bytes, of Buffer. On exit, the size, in
+                                      bytes, of the packet that was received on the network interface.
+   <at> param Buffer                  A pointer to the data buffer to receive both the media
+                                      header and the data.
+   <at> param SrcAddr                 The source HW MAC address. If this parameter is NULL, the HW
+                                      MAC source address will not be extracted from the media header.
+   <at> param DestAddr                The destination HW MAC address. If this parameter is NULL,
+                                      the HW MAC destination address will not be extracted from
+                                      the media header.
+   <at> param Protocol                The media header type. If this parameter is NULL, then the
+                                      protocol will not be extracted from the media header. See
+                                      RFC 1700 section "Ether Types" for examples.
+
+   <at> retval EFI_SUCCESS            The received data was stored in Buffer, and
+                                      BufferSize has been updated to the number of
+                                      bytes received.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_NOT_READY          No packets have been received on the network interface.
+   <at> retval EFI_BUFFER_TOO_SMALL   BufferSize is too small for the received packets.
+                                      BufferSize has been updated to the required size.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
+                                      * The This parameter is NULL
+                                      * The This parameter does not point to a valid
+                                        EFI_SIMPLE_NETWORK_PROTOCOL structure.
+                                      * The BufferSize parameter is NULL
+                                      * The Buffer parameter is NULL
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpReceive (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    OUT UINTN                      *HeaderSize OPTIONAL,
+    IN OUT UINTN                   *BufferSize,
+    OUT VOID                       *Buffer,
+    OUT EFI_MAC_ADDRESS            *SrcAddr OPTIONAL,
+    OUT EFI_MAC_ADDRESS            *DestAddr OPTIONAL,
+    OUT UINT16                     *Protocol OPTIONAL
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *Snp;
+  EFI_TPL       OldTpl;
+  struct msk_softc *ScData;
+
+  if (This == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Snp = YUKON_DEV_FROM_THIS_SNP (This);
+
+  Status = MarvellYukonGetControllerData (Snp->Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (Snp->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_EXIT;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_EXIT;
+  }
+
+  if ((BufferSize == NULL) || (Buffer == NULL)) {
+    Status = EFI_INVALID_PARAMETER;
+    goto ON_EXIT;
+  }
+
+  Status = mskc_receive (ScData->msk_if[Snp->Port], BufferSize, Buffer);
+  if (EFI_ERROR (Status)) {
+    if (Status == EFI_NOT_READY) {
+      goto ON_EXIT_NO_DEBUG;
+    }
+  } else {
+    // Extract header info
+    if (HeaderSize != NULL) {
+      *HeaderSize = sizeof (ETHER_HEAD);
+    }
+
+    if (SrcAddr != NULL) {
+      gBS->SetMem (SrcAddr, NET_ETHER_ADDR_LEN, 0);
+      gBS->CopyMem (SrcAddr, ((UINT8 *) Buffer) + NET_ETHER_ADDR_LEN, NET_ETHER_ADDR_LEN);
+    }
+
+    if (DestAddr != NULL) {
+      gBS->SetMem (DestAddr, NET_ETHER_ADDR_LEN, 0);
+      gBS->CopyMem (DestAddr, ((UINT8 *) Buffer), NET_ETHER_ADDR_LEN);
+    }
+
+    if (Protocol != NULL) {
+      *Protocol = NTOHS (*((UINT16 *) (((UINT8 *) Buffer) + (2 * NET_ETHER_ADDR_LEN))));
+    }
+  }
+
+ON_EXIT:
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReceive() Status = %r\n", Status));
+
+ON_EXIT_NO_DEBUG:
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+}
+
+/**
+  Manages the multicast receive filters of a network interface.
+
+  This function is used enable and disable the hardware and software receive
+  filters for the underlying network device.
+  The receive filter change is broken down into three steps:
+  * The filter mask bits that are set (ON) in the Enable parameter are added to
+    the current receive filter settings.
+  * The filter mask bits that are set (ON) in the Disable parameter are subtracted
+    from the updated receive filter settings.
+  * If the resulting receive filter setting is not supported by the hardware a
+    more liberal setting is selected.
+  If the same bits are set in the Enable and Disable parameters, then the bits
+  in the Disable parameter takes precedence.
+  If the ResetMCastFilter parameter is TRUE, then the multicast address list
+  filter is disabled (irregardless of what other multicast bits are set in the
+  Enable and Disable parameters). The SNP->Mode->MCastFilterCount field is set
+  to zero. The Snp->Mode->MCastFilter contents are undefined.
+  After enabling or disabling receive filter settings, software should verify
+  the new settings by checking the Snp->Mode->ReceiveFilterSettings,
+  Snp->Mode->MCastFilterCount and Snp->Mode->MCastFilter fields.
+  Note: Some network drivers and/or devices will automatically promote receive
+    filter settings if the requested setting can not be honored. For example, if
+    a request for four multicast addresses is made and the underlying hardware
+    only supports two multicast addresses the driver might set the promiscuous
+    or promiscuous multicast receive filters instead. The receiving software is
+    responsible for discarding any extra packets that get through the hardware
+    receive filters.
+    Note: Note: To disable all receive filter hardware, the network driver must
+      be Shutdown() and Stopped(). Calling ReceiveFilters() with Disable set to
+      Snp->Mode->ReceiveFilterSettings will make it so no more packets are
+      returned by the Receive() function, but the receive hardware may still be
+      moving packets into system memory before inspecting and discarding them.
+      Unexpected system errors, reboots and hangs can occur if an OS is loaded
+      and the network devices are not Shutdown() and Stopped().
+  If ResetMCastFilter is TRUE, then the multicast receive filter list on the
+  network interface will be reset to the default multicast receive filter list.
+  If ResetMCastFilter is FALSE, and this network interface allows the multicast
+  receive filter list to be modified, then the MCastFilterCnt and MCastFilter
+  are used to update the current multicast receive filter list. The modified
+  receive filter list settings can be found in the MCastFilter field of
+  EFI_SIMPLE_NETWORK_MODE. If the network interface does not allow the multicast
+  receive filter list to be modified, then EFI_INVALID_PARAMETER will be returned.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+  If the receive filter mask and multicast receive filter list have been
+  successfully updated on the network interface, EFI_SUCCESS will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param Enable                  A bit mask of receive filters to enable on the network
+                                      interface.
+   <at> param Disable                 A bit mask of receive filters to disable on the network
+                                      interface. For backward compatibility with EFI 1.1
+                                      platforms, the EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit
+                                      must be set when the ResetMCastFilter parameter is TRUE.
+   <at> param ResetMCastFilter        Set to TRUE to reset the contents of the multicast
+                                      receive filters on the network interface to their
+                                      default values.
+   <at> param MCastFilterCnt          Number of multicast HW MAC addresses in the new MCastFilter
+                                      list. This value must be less than or equal to the
+                                      MCastFilterCnt field of EFI_SIMPLE_NETWORK_MODE.
+                                      This field is optional if ResetMCastFilter is TRUE.
+   <at> param MCastFilter             A pointer to a list of new multicast receive filter HW
+                                      MAC addresses. This list will replace any existing
+                                      multicast HW MAC address list. This field is optional
+                                      if ResetMCastFilter is TRUE.
+
+   <at> retval EFI_SUCCESS            The multicast receive filter list was updated.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
+                                      * This is NULL
+                                      * There are bits set in Enable that are not set
+                                        in Snp->Mode->ReceiveFilterMask
+                                      * There are bits set in Disable that are not set
+                                        in Snp->Mode->ReceiveFilterMask
+                                      * Multicast is being enabled (the
+                                        EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit is
+                                        set in Enable, it is not set in Disable, and
+                                        ResetMCastFilter is FALSE) and MCastFilterCount
+                                        is zero
+                                      * Multicast is being enabled and MCastFilterCount
+                                        is greater than Snp->Mode->MaxMCastFilterCount
+                                      * Multicast is being enabled and MCastFilter is NULL
+                                      * Multicast is being enabled and one or more of
+                                        the addresses in the MCastFilter list are not
+                                        valid multicast MAC addresses
+   <at> retval EFI_DEVICE_ERROR       One or more of the following conditions is TRUE:
+                                      * The network interface has been started but has
+                                        not been initialized
+                                      * An unexpected error was returned by the
+                                        underlying network driver or device
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network
+                                      interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpReceiveFilters (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN UINT32                      Enable,
+    IN UINT32                      Disable,
+    IN BOOLEAN                     ResetMCastFilter,
+    IN UINTN                       MCastFilterCnt,  OPTIONAL
+    IN EFI_MAC_ADDRESS             *MCastFilter     OPTIONAL
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+  UINT32        newReceiveFilter;
+  struct msk_softc *ScData;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReceiveFilters()\n"));
+  if (This == NULL) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpReceiveFilters() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  Status = MarvellYukonGetControllerData (YukonDriver->Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_ERROR_RESTORE_TPL;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_ERROR_RESTORE_TPL;
+  }
+  //
+  // check if we are asked to enable or disable something that the NIC
+  // does not even support!
+  //
+  newReceiveFilter = (YukonDriver->SnpMode.ReceiveFilterSetting | Enable) & ~Disable;
+  if ((newReceiveFilter & ~YukonDriver->SnpMode.ReceiveFilterMask) != 0) {
+    DEBUG ((DEBUG_NET,
+           "Marvell Yukon: SnpReceiveFilters() NIC does not support Enable = 0x%x, Disable = 0x%x\n", Enable, Disable));
+    Status = EFI_INVALID_PARAMETER;
+    goto ON_ERROR_RESTORE_TPL;
+  }
+
+  if (ResetMCastFilter) {
+    newReceiveFilter &= ~(EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST & YukonDriver->SnpMode.ReceiveFilterMask);
+    MCastFilterCnt = 0;
+    MCastFilter    = NULL;
+  } else {
+    if (MCastFilterCnt != 0) {
+      if ((MCastFilterCnt > YukonDriver->SnpMode.MaxMCastFilterCount) ||
+          (MCastFilter == NULL)) {
+
+        DEBUG ((DEBUG_NET,
+               "Marvell Yukon: SnpReceiveFilters() NIC does not support MCastFilterCnt = %d (Max = %d)\n",
+               MCastFilterCnt, YukonDriver->SnpMode.MaxMCastFilterCount));
+        Status = EFI_INVALID_PARAMETER;
+        goto ON_ERROR_RESTORE_TPL;
+      }
+    }
+  }
+
+  if (newReceiveFilter == YukonDriver->SnpMode.ReceiveFilterSetting && !ResetMCastFilter && MCastFilterCnt == 0) {
+    Status = EFI_SUCCESS;
+    goto ON_EXIT;
+  }
+
+  if ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST) != 0 && MCastFilterCnt == 0) {
+    Status = EFI_INVALID_PARAMETER;
+    goto ON_ERROR_RESTORE_TPL;
+  }
+
+  YukonDriver->SnpMode.ReceiveFilterSetting = newReceiveFilter;
+  mskc_rxfilter (ScData->msk_if[YukonDriver->Port], YukonDriver->SnpMode.ReceiveFilterSetting,
+                 MCastFilterCnt, MCastFilter);
+
+  Status = EFI_SUCCESS;
+  goto ON_EXIT;
+
+ON_ERROR_RESTORE_TPL:
+  DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpReceiveFilters() failed with Status = %r\n", Status));
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+}
+
+/**
+  Resets a network adapter and reinitializes it with the parameters that were
+  provided in the previous call to Initialize().
+
+  This function resets a network adapter and reinitializes it with the parameters
+  that were provided in the previous call to Initialize(). The transmit and
+  receive queues are emptied and all pending interrupts are cleared.
+  Receive filters, the station address, the statistics, and the multicast-IP-to-HW
+  MAC addresses are not reset by this call. If the network interface was
+  successfully reset, then EFI_SUCCESS will be returned. If the driver has not
+  been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param ExtendedVerification    Indicates that the driver may perform a more
+                                      exhaustive verification operation of the device
+                                      during reset.
+
+   <at> retval EFI_SUCCESS            The network interface was reset.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the parameters has an unsupported value.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpReset (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     ExtendedVerification
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpReset()\n"));
+  //
+  // Resolve Warning 4 unreferenced parameter problem
+  //
+  ExtendedVerification = 0;
+  DEBUG ((EFI_D_WARN, "Marvell Yukon: ExtendedVerification = %d is not implemented!\n", ExtendedVerification));
+
+  if (This == NULL) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpReset() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_ERROR_RESTORE_TPL;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_ERROR_RESTORE_TPL;
+  }
+
+  // Always succeeds
+  Status = EFI_SUCCESS;
+  goto ON_EXIT;
+
+ON_ERROR_RESTORE_TPL:
+  DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpReset() failed with Status = %r\n", Status));
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+}
+
+/**
+  Resets a network adapter and leaves it in a state that is safe for another
+  driver to initialize.
+
+  This function releases the memory buffers assigned in the Initialize() call.
+  Pending transmits and receives are lost, and interrupts are cleared and disabled.
+  After this call, only the Initialize() and Stop() calls may be used. If the
+  network interface was successfully shutdown, then EFI_SUCCESS will be returned.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+
+   <at> retval EFI_SUCCESS            The network interface was shutdown.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                      EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpShutdown (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+  struct msk_softc *ScData;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpShutdown()\n"));
+  //
+  // Get pointer to SNP driver instance for *This.
+  //
+  if (This == NULL) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpShutdown() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  Status = MarvellYukonGetControllerData (YukonDriver->Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  //
+  // Return error if the SNP is not initialized.
+  //
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_ERROR_RESTORE_TPL;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_ERROR_RESTORE_TPL;
+  }
+
+  mskc_stop_if (ScData->msk_if[YukonDriver->Port]);
+  YukonDriver->SnpMode.State = EfiSimpleNetworkStarted;
+  Status = EFI_SUCCESS;
+
+  YukonDriver->SnpMode.State                 = EfiSimpleNetworkStarted;
+  YukonDriver->SnpMode.ReceiveFilterSetting  = 0;
+
+  YukonDriver->SnpMode.MCastFilterCount      = 0;
+  YukonDriver->SnpMode.ReceiveFilterSetting  = 0;
+  gBS->SetMem (YukonDriver->SnpMode.MCastFilter, sizeof YukonDriver->SnpMode.MCastFilter, 0);
+  gBS->CopyMem (
+        &YukonDriver->SnpMode.CurrentAddress,
+        &YukonDriver->SnpMode.PermanentAddress,
+        sizeof (EFI_MAC_ADDRESS)
+        );
+
+  goto ON_EXIT;
+
+ON_ERROR_RESTORE_TPL:
+  DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpShutdown() failed with Status = %r\n", Status));
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+}
+
+/**
+  Change the state of a network interface from "stopped" to "started."
+
+  This function starts a network interface. If the network interface successfully
+  starts, then EFI_SUCCESS will be returned.
+
+   <at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+
+   <at> retval EFI_SUCCESS            The network interface was started.
+   <at> retval EFI_ALREADY_STARTED    The network interface is already in the started state.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a valid
+                                      EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpStart (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+    )
+{
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+  EFI_STATUS    Status;
+  struct msk_softc  *ScData;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStart()\n"));
+  if (This == NULL) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpStart() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  Status = MarvellYukonGetControllerData (YukonDriver->Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkStopped:
+      break;
+
+    case EfiSimpleNetworkStarted:
+    case EfiSimpleNetworkInitialized:
+      Status = EFI_ALREADY_STARTED;
+      goto ON_EXIT;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_ERROR_RESTORE_TPL;
+  }
+
+  Status = mskc_attach_if (ScData->msk_if[YukonDriver->Port], YukonDriver->Port);
+
+  if (EFI_ERROR (Status)) {
+    goto ON_ERROR_RESTORE_TPL;
+  }
+
+  YukonDriver->SnpMode.State = EfiSimpleNetworkStarted;
+  gBS->CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS));
+  YukonDriver->SnpMode.MCastFilterCount = 0;
+  goto ON_EXIT;
+
+ON_ERROR_RESTORE_TPL:
+  DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpStart() failed with Status = %r\n", Status));
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+}
+
+/**
+  Modifies or resets the current station address, if supported.
+
+  This function modifies or resets the current station address of a network
+  interface, if supported. If Reset is TRUE, then the current station address is
+  set to the network interface's permanent address. If Reset is FALSE, and the
+  network interface allows its station address to be modified, then the current
+  station address is changed to the address specified by New. If the network
+  interface does not allow its station address to be modified, then
+  EFI_INVALID_PARAMETER will be returned. If the station address is successfully
+  updated on the network interface, EFI_SUCCESS will be returned. If the driver
+  has not been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param Reset                   Flag used to reset the station address to the network interface's
+                                      permanent address.
+   <at> param New                     New station address to be used for the network interface.
+
+
+   <at> retval EFI_SUCCESS            The network interface's station address was updated.
+   <at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not been
+                                                                 started by calling Start().
+   <at> retval EFI_INVALID_PARAMETER  The New station address was not accepted by the NIC.
+   <at> retval EFI_INVALID_PARAMETER  Reset is FALSE and New is NULL.
+   <at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
+                                      been initialized by calling Initialize().
+   <at> retval EFI_DEVICE_ERROR       An error occurred attempting to set the new
+                                      station address.
+   <at> retval EFI_UNSUPPORTED        The NIC does not support changing the network
+                                      interface's station address.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpStationAddress (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     Reset,
+    IN EFI_MAC_ADDRESS             *New OPTIONAL
+    )
+{
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+  EFI_STATUS    Status;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStationAddress()\n"));
+  //
+  // Check for invalid parameter combinations.
+  //
+  if ((This == NULL) || (!Reset && (New == NULL))) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  //
+  // Return error if the SNP is not initialized.
+  //
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_EXIT;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_EXIT;
+  }
+
+  Status = EFI_UNSUPPORTED;
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+
+  return Status;
+}
+
+/**
+  Resets or collects the statistics on a network interface.
+
+  This function resets or collects the statistics on a network interface. If the
+  size of the statistics table specified by StatisticsSize is not big enough for
+  all the statistics that are collected by the network interface, then a partial
+  buffer of statistics is returned in StatisticsTable, StatisticsSize is set to
+  the size required to collect all the available statistics, and
+  EFI_BUFFER_TOO_SMALL is returned.
+  If StatisticsSize is big enough for all the statistics, then StatisticsTable
+  will be filled, StatisticsSize will be set to the size of the returned
+  StatisticsTable structure, and EFI_SUCCESS is returned.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+  If Reset is FALSE, and both StatisticsSize and StatisticsTable are NULL, then
+  no operations will be performed, and EFI_SUCCESS will be returned.
+  If Reset is TRUE, then all of the supported statistics counters on this network
+  interface will be reset to zero.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param Reset                   Set to TRUE to reset the statistics for the network interface.
+   <at> param StatisticsSize          On input the size, in bytes, of StatisticsTable. On output
+                                      the size, in bytes, of the resulting table of statistics.
+   <at> param StatisticsTable         A pointer to the EFI_NETWORK_STATISTICS structure that
+                                      contains the statistics. Type EFI_NETWORK_STATISTICS is
+                                      defined in "Related Definitions" below.
+
+   <at> retval EFI_SUCCESS            The requested operation succeeded.
+   <at> retval EFI_NOT_STARTED        The Simple Network Protocol interface has not been
+                                      started by calling Start().
+   <at> retval EFI_BUFFER_TOO_SMALL   StatisticsSize is not NULL and StatisticsTable is
+                                      NULL. The current buffer size that is needed to
+                                      hold all the statistics is returned in StatisticsSize.
+   <at> retval EFI_BUFFER_TOO_SMALL   StatisticsSize is not NULL and StatisticsTable is
+                                      not NULL. The current buffer size that is needed
+                                      to hold all the statistics is returned in
+                                      StatisticsSize. A partial set of statistics is
+                                      returned in StatisticsTable.
+   <at> retval EFI_INVALID_PARAMETER  StatisticsSize is NULL and StatisticsTable is not
+                                      NULL.
+   <at> retval EFI_DEVICE_ERROR       The Simple Network Protocol interface has not
+                                      been initialized by calling Initialize().
+   <at> retval EFI_DEVICE_ERROR       An error was encountered collecting statistics
+                                      from the NIC.
+   <at> retval EFI_UNSUPPORTED        The NIC does not support collecting statistics
+                                      from the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpStatistics (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN BOOLEAN                     Reset,
+    IN OUT UINTN                   *StatisticsSize, OPTIONAL
+    IN OUT EFI_NETWORK_STATISTICS  *StatisticsTable OPTIONAL
+    )
+{
+  EFI_STATUS        Status;
+  YUKON_DRIVER        *YukonDriver;
+  EFI_TPL           OldTpl;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStatistics()\n"));
+  //
+  // Get pointer to SNP driver instance for *This.
+  //
+  if (This == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = EFI_SUCCESS;
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  //
+  // Return error if the SNP is not initialized.
+  //
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_EXIT;
+
+    case EfiSimpleNetworkStarted:
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_EXIT;
+  }
+
+  //
+  // Error Checking
+  //
+
+  if (!Reset && (StatisticsSize == NULL) && (StatisticsTable == NULL)) {
+    Status = EFI_SUCCESS;
+    goto ON_EXIT;
+  }
+
+  if ((StatisticsSize == NULL) && (StatisticsTable != NULL)) {
+    Status = EFI_INVALID_PARAMETER;
+    goto ON_EXIT;
+  }
+
+  if ((StatisticsSize != NULL) && (StatisticsTable == NULL)) {
+    *StatisticsSize = sizeof (EFI_NETWORK_STATISTICS);
+    Status = EFI_BUFFER_TOO_SMALL;
+    goto ON_EXIT;
+  }
+
+  if ((StatisticsSize != NULL) && (StatisticsTable != NULL)) {
+    if (*StatisticsSize < sizeof (EFI_NETWORK_STATISTICS)) {
+      if (*StatisticsSize == 0) {
+        Status = EFI_BUFFER_TOO_SMALL;
+        // Note: From here on, the Status value must be preserved.
+      } else {
+        // FixMe: Return partial statistics for the available size and also set
+        //        Status = EFI_BUFFER_TOO_SMALL;
+        //        but for now it is unsupported.
+        Status = EFI_UNSUPPORTED;
+        // Note: From here on, the Status value must be preserved.
+      }
+      *StatisticsSize = sizeof (EFI_NETWORK_STATISTICS);
+    } else {
+      // FixMe: Return full statistics and also set
+      //        Status = EFI_SUCCESS;
+      //        but for now it is unsupported.
+      Status = EFI_UNSUPPORTED;
+    }
+  }
+
+  if (Reset == TRUE) {
+    // FixMe: Reset all statistics;
+
+    // Preserve any previous errors else return success.
+    if (!EFI_ERROR (Status)) {
+      // FixMe: Should return success
+      //        Status = EFI_SUCCESS;
+      //        but for now it is unsupported.
+      Status = EFI_UNSUPPORTED;
+    }
+  }
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+
+  return Status;
+}
+
+/**
+  Changes the state of a network interface from "started" to "stopped."
+
+  This function stops a network interface. This call is only valid if the network
+  interface is in the started state. If the network interface was successfully
+  stopped, then EFI_SUCCESS will be returned.
+
+   <at> param  This                   A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL
+                                                                  instance.
+
+
+   <at> retval EFI_SUCCESS            The network interface was stopped.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_INVALID_PARAMETER  This parameter was NULL or did not point to a
+                                      valid EFI_SIMPLE_NETWORK_PROTOCOL structure.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network
+                                      interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network
+                                      interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpStop (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+  struct msk_softc *ScData;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpStop()\n"));
+  if (This == NULL) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpStop() failed with Status = %r\n", EFI_INVALID_PARAMETER));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  Status = MarvellYukonGetControllerData (YukonDriver->Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkStarted:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_ERROR_RESTORE_TPL;
+
+    case EfiSimpleNetworkInitialized:
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_ERROR_RESTORE_TPL;
+  }
+
+  mskc_detach_if (ScData->msk_if[YukonDriver->Port]);
+  YukonDriver->SnpMode.State = EfiSimpleNetworkStopped;
+  gBS->SetMem (&YukonDriver->SnpMode.CurrentAddress, sizeof (EFI_MAC_ADDRESS), 0);
+  Status = EFI_SUCCESS;
+  goto ON_EXIT;
+
+ON_ERROR_RESTORE_TPL:
+  DEBUG ((EFI_D_ERROR, "Marvell Yukon: SnpStop() failed with Status = %r\n", Status));
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+  return Status;
+}
+
+/**
+  Places a packet in the transmit queue of a network interface.
+
+  This function places the packet specified by Header and Buffer on the transmit
+  queue. If HeaderSize is nonzero and HeaderSize is not equal to
+  This->SnpMode->MediaHeaderSize, then EFI_INVALID_PARAMETER will be returned. If
+  BufferSize is less than This->SnpMode->MediaHeaderSize, then EFI_BUFFER_TOO_SMALL
+  will be returned. If Buffer is NULL, then EFI_INVALID_PARAMETER will be
+  returned. If HeaderSize is nonzero and DestAddr or Protocol is NULL, then
+  EFI_INVALID_PARAMETER will be returned. If the transmit engine of the network
+  interface is busy, then EFI_NOT_READY will be returned. If this packet can be
+  accepted by the transmit engine of the network interface, the packet contents
+  specified by Buffer will be placed on the transmit queue of the network
+  interface, and EFI_SUCCESS will be returned. GetStatus() can be used to
+  determine when the packet has actually been transmitted. The contents of the
+  Buffer must not be modified until the packet has actually been transmitted.
+  The Transmit() function performs nonblocking I/O. A caller who wants to perform
+  blocking I/O, should call Transmit(), and then GetStatus() until the
+  transmitted buffer shows up in the recycled transmit buffer.
+  If the driver has not been initialized, EFI_DEVICE_ERROR will be returned.
+
+   <at> param This                    A pointer to the EFI_SIMPLE_NETWORK_PROTOCOL instance.
+   <at> param HeaderSize              The size, in bytes, of the media header to be filled in by the
+                                      Transmit() function. If HeaderSize is nonzero, then it must
+                                      be equal to This->SnpMode->MediaHeaderSize and the DestAddr and
+                                      Protocol parameters must not be NULL.
+   <at> param BufferSize              The size, in bytes, of the entire packet (media header and
+                                      data) to be transmitted through the network interface.
+   <at> param Buffer                  A pointer to the packet (media header followed by data) to be
+                                      transmitted. This parameter cannot be NULL. If HeaderSize is
+                                      zero, then the media header in Buffer must already be filled
+                                      in by the caller. If HeaderSize is nonzero, then the media
+                                      header will be filled in by the Transmit() function.
+   <at> param SrcAddr                 The source HW MAC address. If HeaderSize is zero, then this
+                                      parameter is ignored. If HeaderSize is nonzero and SrcAddr
+                                      is NULL, then This->SnpMode->CurrentAddress is used for the
+                                      source HW MAC address.
+   <at> param DestAddr                The destination HW MAC address. If HeaderSize is zero, then
+                                      this parameter is ignored.
+   <at> param Protocol                The type of header to build. If HeaderSize is zero, then this
+                                      parameter is ignored. See RFC 1700, section "Ether Types,"
+                                      for examples.
+
+   <at> retval EFI_SUCCESS            The packet was placed on the transmit queue.
+   <at> retval EFI_NOT_STARTED        The network interface has not been started.
+   <at> retval EFI_NOT_READY          The network interface is too busy to accept this
+                                      transmit request.
+   <at> retval EFI_BUFFER_TOO_SMALL   The BufferSize parameter is too small.
+   <at> retval EFI_INVALID_PARAMETER  One or more of the parameters has an unsupported
+                                      value.
+   <at> retval EFI_DEVICE_ERROR       The command could not be sent to the network interface.
+   <at> retval EFI_UNSUPPORTED        This function is not supported by the network interface.
+
+**/
+EFI_STATUS
+EFIAPI
+SnpTransmit (
+    IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+    IN UINTN                       HeaderSize,
+    IN UINTN                       BufferSize,
+    IN VOID                        *Buffer,
+    IN EFI_MAC_ADDRESS             *SrcAddr,  OPTIONAL
+    IN EFI_MAC_ADDRESS             *DestAddr, OPTIONAL
+    IN UINT16                      *Protocol  OPTIONAL
+    )
+{
+  EFI_STATUS    Status;
+  YUKON_DRIVER    *YukonDriver;
+  EFI_TPL       OldTpl;
+  ETHER_HEAD    *Frame;
+  UINT16        ProtocolNet;
+  struct msk_softc  *ScData;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: SnpTransmit()\n"));
+  if (This == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  YukonDriver = YUKON_DEV_FROM_THIS_SNP (This);
+
+  if (YukonDriver == NULL) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = MarvellYukonGetControllerData (YukonDriver->Controller, &ScData);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  switch (YukonDriver->SnpMode.State) {
+    case EfiSimpleNetworkInitialized:
+      break;
+
+    case EfiSimpleNetworkStopped:
+      Status = EFI_NOT_STARTED;
+      goto ON_EXIT;
+
+    default:
+      Status = EFI_DEVICE_ERROR;
+      goto ON_EXIT;
+  }
+
+  if (Buffer == NULL) {
+    Status = EFI_INVALID_PARAMETER;
+    goto ON_EXIT;
+  }
+
+  if (BufferSize < YukonDriver->SnpMode.MediaHeaderSize) {
+    Status = EFI_BUFFER_TOO_SMALL;
+    goto ON_EXIT;
+  }
+
+  //
+  // Construct the frame header if not already presented
+  //
+  if (HeaderSize != 0) {
+    if (HeaderSize != YukonDriver->SnpMode.MediaHeaderSize || DestAddr == 0 || Protocol == 0) {
+      Status = EFI_INVALID_PARAMETER;
+      goto ON_EXIT;
+    }
+    Frame       = (ETHER_HEAD*)Buffer;
+    ProtocolNet = NTOHS (*Protocol);
+
+    gBS->CopyMem (Frame->SrcMac,     SrcAddr,      NET_ETHER_ADDR_LEN);
+    gBS->CopyMem (Frame->DstMac,     DestAddr,     NET_ETHER_ADDR_LEN);
+    gBS->CopyMem (&Frame->EtherType, &ProtocolNet, sizeof (UINT16));
+  }
+
+  Status = mskc_transmit (ScData->msk_if[YukonDriver->Port], BufferSize, Buffer);
+
+ON_EXIT:
+  gBS->RestoreTPL (OldTpl);
+
+  return Status;
+}
+
diff --git a/Drivers/Net/MarvellYukonDxe/e1000phy.c b/Drivers/Net/MarvellYukonDxe/e1000phy.c
new file mode 100644
index 0000000..c71ef3d
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/e1000phy.c
@@ -0,0 +1,621 @@
+/**  <at> file
+*  Support for Marvell 88E1000 Series PHYs
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/*-
+ * Principal Author: Parag Patel
+ * Copyright (c) 2001
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Additonal Copyright (c) 2001 by Traakan Software under same licence.
+ * Secondary Author: Matthew Jacob
+ */
+
+/*
+ * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
+ */
+
+/*
+ * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
+ * 1000baseSX PHY.
+ * Nathan Binkert <nate <at> openbsd.org>
+ * Jung-uk Kim <jkim <at> niksun.com>
+ */
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "if_media.h"
+
+#include "miivar.h"
+
+#include "e1000phyreg.h"
+
+static EFI_STATUS e1000phy_probe (const struct mii_attach_args *ma);
+STATIC VOID  e1000phy_attach (struct e1000phy_softc *, const struct mii_attach_args *ma);
+STATIC VOID  e1000phy_service (struct e1000phy_softc *, INTN);
+STATIC VOID  e1000phy_status (struct e1000phy_softc *);
+STATIC VOID  e1000phy_reset (struct e1000phy_softc *);
+STATIC VOID  e1000phy_mii_phy_auto (struct e1000phy_softc *);
+
+INTN msk_phy_readreg (VOID *, INTN);
+INTN msk_phy_writereg (VOID *, INTN, INTN);
+VOID msk_miibus_statchg (VOID *);
+
+static const struct mii_phydesc * mii_phy_match (const struct mii_attach_args *ma,
+                                                 const struct mii_phydesc *mpd);
+static const struct mii_phydesc * mii_phy_match_gen (const struct mii_attach_args *ma,
+                                                     const struct mii_phydesc *mpd, UINTN endlen);
+static EFI_STATUS mii_phy_dev_probe (const struct mii_attach_args *ma, const struct mii_phydesc *mpd);
+STATIC VOID mii_phy_update (struct e1000phy_softc *, INTN);
+
+static const struct mii_phydesc e1000phys[] = {
+  MII_PHY_DESC (MARVELL, E1000),
+  MII_PHY_DESC (MARVELL, E1011),
+  MII_PHY_DESC (MARVELL, E1000_3),
+  MII_PHY_DESC (MARVELL, E1000S),
+  MII_PHY_DESC (MARVELL, E1000_5),
+  MII_PHY_DESC (MARVELL, E1000_6),
+  MII_PHY_DESC (MARVELL, E3082),
+  MII_PHY_DESC (MARVELL, E1112),
+  MII_PHY_DESC (MARVELL, E1149),
+  MII_PHY_DESC (MARVELL, E1111),
+  MII_PHY_DESC (MARVELL, E1116),
+  MII_PHY_DESC (MARVELL, E1116R),
+  MII_PHY_DESC (MARVELL, E1118),
+  MII_PHY_DESC (MARVELL, E3016),
+  MII_PHY_DESC (MARVELL, PHYG65G),
+  MII_PHY_DESC (xxMARVELL, E1000),
+  MII_PHY_DESC (xxMARVELL, E1011),
+  MII_PHY_DESC (xxMARVELL, E1000_3),
+  MII_PHY_DESC (xxMARVELL, E1000_5),
+  MII_PHY_DESC (xxMARVELL, E1111),
+  MII_PHY_END
+};
+
+EFI_STATUS
+e1000_probe_and_attach (
+    struct mii_data             *mii,
+    const struct msk_mii_data   *mmd,
+    VOID                        *sc_if,
+    VOID                        **rsc_phy
+    )
+{
+  struct mii_attach_args    ma;
+  INTN                      bmsr;
+  EFI_STATUS                Status;
+  struct e1000phy_softc        *sc_phy;
+
+  Status = gBS->AllocatePool (EfiBootServicesData,
+                              sizeof (struct e1000phy_softc),
+                              (VOID**) &sc_phy);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  gBS->SetMem (sc_phy, sizeof (struct e1000phy_softc), 0);
+  sc_phy->mmd = mmd;
+
+  sc_phy->sc_if = sc_if;
+
+  /*
+   * Check to see if there is a PHY at this address.  Note,
+   * many braindead PHYs report 0/0 in their ID registers,
+   * so we test for media in the BMSR.
+   */
+  bmsr = PHY_READ (sc_phy, E1000_SR);
+  if (bmsr == 0 || bmsr == 0xffff || (bmsr & (E1000_SR_EXTENDED_STATUS|E1000_SR_MEDIAMASK)) == 0) {
+    /* Assume no PHY at this address. */
+    gBS->FreePool (sc_phy);
+    return EFI_DEVICE_ERROR;
+  }
+
+  /*
+   * Extract the IDs.
+   */
+  ma.mii_id1 = PHY_READ (sc_phy, E1000_ID1);
+  ma.mii_id2 = PHY_READ (sc_phy, E1000_ID2);
+
+  ma.mii_data = mii;
+
+  Status = e1000phy_probe (&ma);
+  if (EFI_ERROR (Status)) {
+    gBS->FreePool (sc_phy);
+    return Status;
+  }
+
+  e1000phy_attach (sc_phy, &ma);
+
+  *rsc_phy = sc_phy;
+
+  return EFI_SUCCESS;
+}
+
+VOID
+e1000phy_detach (
+    struct e1000phy_softc *sc_phy
+    )
+{
+  if (sc_phy != NULL) {
+    gBS->FreePool (sc_phy);
+  }
+}
+
+EFI_STATUS
+e1000phy_probe (
+    const struct mii_attach_args    *ma
+    )
+{
+  return (mii_phy_dev_probe (ma, e1000phys));
+}
+
+static void
+e1000phy_attach (
+    struct e1000phy_softc        *sc_phy,
+    const struct mii_attach_args *ma
+    )
+{
+  struct mii_softc    *sc;
+
+  sc = &sc_phy->mii_sc;
+  sc->mii_pdata = ma->mii_data;
+  sc->mii_anegticks = MII_ANEGTICKS_GIGE;
+
+  sc_phy->mii_model = MII_MODEL (ma->mii_id2);
+
+  if (sc_phy->mmd != NULL && (sc_phy->mmd->mii_flags & MIIF_HAVEFIBER) != 0) {
+    sc->mii_flags |= MIIF_HAVEFIBER;
+  }
+
+  switch (sc_phy->mii_model) {
+    case MII_MODEL_MARVELL_E1011:
+    case MII_MODEL_MARVELL_E1112:
+      if (PHY_READ (sc_phy, E1000_ESSR) & E1000_ESSR_FIBER_LINK) {
+        sc->mii_flags |= MIIF_HAVEFIBER;
+      }
+      break;
+    case MII_MODEL_MARVELL_E1149:
+      /*
+     * Some 88E1149 PHY's page select is initialized to
+     * point to other bank instead of copper/fiber bank
+     * which in turn resulted in wrong registers were
+     * accessed during PHY operation. It is believed that
+     * page 0 should be used for copper PHY so reinitialize
+     * E1000_EADR to select default copper PHY. If parent
+     * device know the type of PHY(either copper or fiber),
+     * that information should be used to select default
+     * type of PHY.
+     */
+      PHY_WRITE (sc_phy, E1000_EADR, 0);
+      break;
+  }
+
+  e1000phy_reset (sc_phy);
+
+  sc->mii_capabilities = PHY_READ (sc_phy, E1000_SR) & 0xFFFFFFFF;
+  if (sc->mii_capabilities & E1000_SR_EXTENDED_STATUS) {
+    sc->mii_extcapabilities = PHY_READ (sc_phy, E1000_ESR);
+  }
+}
+
+static void
+e1000phy_reset (
+    struct e1000phy_softc  *sc_phy
+    )
+{
+  UINT16  reg;
+  UINT16  page;
+  struct mii_softc *sc;
+
+  sc = &sc_phy->mii_sc;
+
+  reg = PHY_READ (sc_phy, E1000_SCR);
+  if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
+    reg &= ~E1000_SCR_AUTO_X_MODE;
+    PHY_WRITE (sc_phy, E1000_SCR, reg);
+    if (sc_phy->mii_model == MII_MODEL_MARVELL_E1112) {
+      // Select 1000BASE-X only mode.
+      page = PHY_READ (sc_phy, E1000_EADR);
+      PHY_WRITE (sc_phy, E1000_EADR, 2);
+      reg = PHY_READ (sc_phy, E1000_SCR);
+      reg &= ~E1000_SCR_MODE_MASK;
+      reg |= E1000_SCR_MODE_1000BX;
+      PHY_WRITE (sc_phy, E1000_SCR, reg);
+      if (sc_phy->mmd != NULL && sc_phy->mmd->pmd == 'P') {
+        // Set SIGDET polarity low for SFP module
+        PHY_WRITE (sc_phy, E1000_EADR, 1);
+        reg = PHY_READ (sc_phy, E1000_SCR);
+        reg |= E1000_SCR_FIB_SIGDET_POLARITY;
+        PHY_WRITE (sc_phy, E1000_SCR, reg);
+      }
+      PHY_WRITE (sc_phy, E1000_EADR, page);
+    }
+  } else {
+    switch (sc_phy->mii_model) {
+      case MII_MODEL_MARVELL_E1111:
+      case MII_MODEL_MARVELL_E1112:
+      case MII_MODEL_MARVELL_E1116:
+      case MII_MODEL_MARVELL_E1118:
+      case MII_MODEL_MARVELL_E1149:
+      case MII_MODEL_MARVELL_PHYG65G:
+        // Disable energy detect mode
+        reg &= ~E1000_SCR_EN_DETECT_MASK;
+        reg |= E1000_SCR_AUTO_X_MODE;
+        if (sc_phy->mii_model == MII_MODEL_MARVELL_E1116)
+          reg &= ~E1000_SCR_POWER_DOWN;
+        reg |= E1000_SCR_ASSERT_CRS_ON_TX;
+        break;
+      case MII_MODEL_MARVELL_E3082:
+        reg |= (E1000_SCR_AUTO_X_MODE >> 1);
+        reg |= E1000_SCR_ASSERT_CRS_ON_TX;
+        break;
+      case MII_MODEL_MARVELL_E3016:
+        reg |= E1000_SCR_AUTO_MDIX;
+        reg &= ~(E1000_SCR_EN_DETECT |
+                 E1000_SCR_SCRAMBLER_DISABLE);
+        reg |= E1000_SCR_LPNP;
+        // XXX Enable class A driver for Yukon FE+ A0
+        PHY_WRITE (sc_phy, 0x1C, PHY_READ (sc_phy, 0x1C) | 0x0001);
+        break;
+      default:
+        reg &= ~E1000_SCR_AUTO_X_MODE;
+        reg |= E1000_SCR_ASSERT_CRS_ON_TX;
+        break;
+    }
+    if (sc_phy->mii_model != MII_MODEL_MARVELL_E3016) {
+      /* Auto correction for reversed cable polarity. */
+      reg &= ~E1000_SCR_POLARITY_REVERSAL;
+    }
+    PHY_WRITE (sc_phy, E1000_SCR, reg);
+
+    if (sc_phy->mii_model == MII_MODEL_MARVELL_E1116 ||
+        sc_phy->mii_model == MII_MODEL_MARVELL_E1149) {
+      PHY_WRITE (sc_phy, E1000_EADR, 2);
+      reg = PHY_READ (sc_phy, E1000_SCR);
+      reg |= E1000_SCR_RGMII_POWER_UP;
+      PHY_WRITE (sc_phy, E1000_SCR, reg);
+      PHY_WRITE (sc_phy, E1000_EADR, 0);
+    }
+  }
+
+  switch (sc_phy->mii_model) {
+    case MII_MODEL_MARVELL_E3082:
+    case MII_MODEL_MARVELL_E1112:
+    case MII_MODEL_MARVELL_E1118:
+      break;
+    case MII_MODEL_MARVELL_E1116:
+      page = PHY_READ (sc_phy, E1000_EADR);
+      /* Select page 3, LED control register. */
+      PHY_WRITE (sc_phy, E1000_EADR, 3);
+      PHY_WRITE (sc_phy, E1000_SCR,
+                 E1000_SCR_LED_LOS (1) |  /* Link/Act */
+                 E1000_SCR_LED_INIT (8) |  /* 10Mbps */
+                 E1000_SCR_LED_STAT1 (7) |  /* 100Mbps */
+                 E1000_SCR_LED_STAT0 (7));  /* 1000Mbps */
+      /* Set blink rate. */
+      PHY_WRITE (sc_phy, E1000_IER, E1000_PULSE_DUR (E1000_PULSE_170MS) | E1000_BLINK_RATE (E1000_BLINK_84MS));
+      PHY_WRITE (sc_phy, E1000_EADR, page);
+      break;
+    case MII_MODEL_MARVELL_E3016:
+      /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
+      PHY_WRITE (sc_phy, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
+      /* Integrated register calibration workaround. */
+      PHY_WRITE (sc_phy, 0x1D, 17);
+      PHY_WRITE (sc_phy, 0x1E, 0x3F60);
+      break;
+    default:
+      /* Force TX_CLK to 25MHz clock. */
+      reg = PHY_READ (sc_phy, E1000_ESCR);
+      reg |= E1000_ESCR_TX_CLK_25;
+      PHY_WRITE (sc_phy, E1000_ESCR, reg);
+      break;
+  }
+
+  /* Reset the PHY so all changes take effect. */
+  reg = PHY_READ (sc_phy, E1000_CR);
+  reg |= E1000_CR_RESET;
+  PHY_WRITE (sc_phy, E1000_CR, reg);
+}
+
+static void
+mii_phy_update (
+    struct e1000phy_softc  *sc_phy,
+    INTN                   cmd
+    )
+{
+  struct mii_softc      *sc = &sc_phy->mii_sc;
+  struct mii_data       *mii = sc->mii_pdata;
+
+  if (sc->mii_media_active != mii->mii_media_active ||
+      sc->mii_media_status != mii->mii_media_status ||
+      cmd == MII_MEDIACHG)
+  {
+    msk_miibus_statchg (sc_phy->sc_if);
+    sc->mii_media_active = mii->mii_media_active;
+    sc->mii_media_status = mii->mii_media_status;
+  }
+}
+
+void
+e1000phy_tick (
+    struct e1000phy_softc  *sc_phy
+    )
+{
+  e1000phy_service (sc_phy, MII_TICK);
+}
+
+void
+e1000phy_mediachg (
+    struct e1000phy_softc  *sc_phy
+    )
+{
+  struct mii_data *mii;
+
+  mii = sc_phy->mii_sc.mii_pdata;
+
+  mii->mii_media_status = 0;
+  mii->mii_media_active = IFM_NONE;
+  e1000phy_service (sc_phy, MII_MEDIACHG);
+}
+
+static void
+e1000phy_service (
+    struct e1000phy_softc  *sc_phy,
+    INTN                   cmd
+    )
+{
+  struct mii_softc    *sc;
+  INTN                reg;
+
+  sc = &sc_phy->mii_sc;
+
+  switch (cmd) {
+    case MII_POLLSTAT:
+      break;
+
+    case MII_MEDIACHG:
+      //
+      // Always try to auto-negotiate
+      //
+      e1000phy_mii_phy_auto (sc_phy);
+      break;
+
+    case MII_TICK:
+      /*
+     * check for link.
+     * Read the status register twice; Link Status is latch-low.
+     */
+      reg = PHY_READ (sc_phy, E1000_SR) | PHY_READ (sc_phy, E1000_SR);
+      if (reg & E1000_SR_LINK_STATUS) {
+        sc->mii_ticks = 0;
+        break;
+      }
+
+      /* Announce link loss right after it happens. */
+      if (sc->mii_ticks++ == 0) {
+        break;
+      }
+      if (sc->mii_ticks <= sc->mii_anegticks) {
+        break;
+      }
+
+      //
+      // Restart the auto-negotiation
+      //
+      sc->mii_ticks = 0;
+      e1000phy_reset (sc_phy);
+      e1000phy_mii_phy_auto (sc_phy);
+      break;
+  }
+
+  /* Update the media status. */
+  e1000phy_status (sc_phy);
+
+  /* Callback if something changed. */
+  mii_phy_update (sc_phy, cmd);
+}
+
+static void
+e1000phy_status (
+    struct e1000phy_softc  *sc_phy
+    )
+{
+  struct mii_softc    *sc;
+  struct mii_data     *mii;
+  INTN                bmcr;
+  INTN                bmsr;
+  INTN                gsr;
+  INTN                ssr;
+  INTN                ar;
+  INTN                lpar;
+
+  sc = &sc_phy->mii_sc;
+  mii = sc->mii_pdata;
+
+  mii->mii_media_status = IFM_AVALID;
+  mii->mii_media_active = IFM_ETHER;
+
+  bmsr = PHY_READ (sc_phy, E1000_SR) | PHY_READ (sc_phy, E1000_SR);
+  bmcr = PHY_READ (sc_phy, E1000_CR);
+  ssr = PHY_READ (sc_phy, E1000_SSR);
+
+  if (bmsr & E1000_SR_LINK_STATUS) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: e1000phy_status, link up\n"));
+    mii->mii_media_status |= IFM_ACTIVE;
+  }
+
+  if (bmcr & E1000_CR_LOOPBACK) {
+    mii->mii_media_active |= IFM_LOOP;
+  }
+
+  if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
+    /* Erg, still trying, I guess... */
+    DEBUG ((EFI_D_NET, "Marvell Yukon: e1000phy_status, auto negotiation not complete\n"));
+    mii->mii_media_active |= IFM_NONE;
+    return;
+  }
+
+  if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
+    switch (ssr & E1000_SSR_SPEED) {
+      case E1000_SSR_1000MBS:
+        mii->mii_media_active |= IFM_1000_T;
+        break;
+      case E1000_SSR_100MBS:
+        mii->mii_media_active |= IFM_100_TX;
+        break;
+      case E1000_SSR_10MBS:
+        mii->mii_media_active |= IFM_10_T;
+        break;
+      default:
+        mii->mii_media_active |= IFM_NONE;
+        return;
+    }
+  } else {
+    /*
+     * Some fiber PHY(88E1112) does not seem to set resolved
+     * speed so always assume we've got IFM_1000_SX.
+     */
+    mii->mii_media_active |= IFM_1000_SX;
+  }
+
+  if (ssr & E1000_SSR_DUPLEX) {
+    mii->mii_media_active |= IFM_FDX;
+  } else {
+    mii->mii_media_active |= IFM_HDX;
+  }
+
+  if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
+    ar = PHY_READ (sc_phy, E1000_AR);
+    lpar = PHY_READ (sc_phy, E1000_LPAR);
+    /* FLAG0==rx-flow-control FLAG1==tx-flow-control */
+    if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
+      mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
+    } else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
+               (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
+      mii->mii_media_active |= IFM_FLAG1;
+    } else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
+               !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
+      mii->mii_media_active |= IFM_FLAG0;
+    }
+  }
+
+  /* FLAG2 : local PHY resolved to MASTER */
+  if ((IFM_SUBTYPE (mii->mii_media_active) == IFM_1000_T) ||
+      (IFM_SUBTYPE (mii->mii_media_active) == IFM_1000_SX)) {
+    PHY_READ (sc_phy, E1000_1GSR);
+    gsr = PHY_READ (sc_phy, E1000_1GSR);
+    if ((gsr & E1000_1GSR_MS_CONFIG_RES) != 0) {
+      mii->mii_media_active |= IFM_FLAG2;
+    }
+  }
+}
+
+static void
+e1000phy_mii_phy_auto (
+    struct e1000phy_softc  *sc_phy
+    )
+{
+  struct mii_softc    *sc;
+  UINT16              reg;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: e1000phy_mii_phy_auto negotiation started\n"));
+  sc = &sc_phy->mii_sc;
+  if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
+    reg = PHY_READ (sc_phy, E1000_AR);
+    reg |= E1000_AR_10T | E1000_AR_10T_FD |
+        E1000_AR_100TX | E1000_AR_100TX_FD |
+        E1000_AR_PAUSE | E1000_AR_ASM_DIR;
+    PHY_WRITE (sc_phy, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
+  } else {
+    PHY_WRITE (sc_phy, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X | E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE);
+  }
+
+  if ((sc->mii_extcapabilities & (E1000_ESR_1000T_FD | E1000_ESR_1000T)) != 0) {
+    PHY_WRITE (sc_phy, E1000_1GCR, E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
+  }
+
+  PHY_WRITE (sc_phy, E1000_CR, E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
+}
+
+//
+// Generic helper functions
+//
+
+const struct mii_phydesc *
+    mii_phy_match_gen (
+    const struct mii_attach_args    *ma,
+    const struct mii_phydesc        *mpd,
+    UINTN                           len
+    )
+{
+
+  for (; mpd->mpd_name != NULL;
+       mpd = (const struct mii_phydesc *) ((const CHAR8 *) mpd + len)) {
+    if (MII_OUI (ma->mii_id1, ma->mii_id2) == mpd->mpd_oui &&
+        MII_MODEL (ma->mii_id2) == mpd->mpd_model) {
+      return (mpd);
+    }
+  }
+  return (NULL);
+}
+
+const struct mii_phydesc *
+    mii_phy_match (
+    const struct mii_attach_args    *ma,
+    const struct mii_phydesc        *mpd
+    )
+{
+
+  return (mii_phy_match_gen (ma, mpd, sizeof (struct mii_phydesc)));
+}
+
+EFI_STATUS
+mii_phy_dev_probe (
+    const struct mii_attach_args    *ma,
+    const struct mii_phydesc        *mpd
+    )
+{
+
+  mpd = mii_phy_match (ma, mpd);
+  if (mpd != NULL) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Found PHY (%a)\n", mpd->mpd_name));
+    return EFI_SUCCESS;
+  }
+
+  DEBUG ((DEBUG_NET, "Marvell Yukon: PHY not found (OUI=0x%x, MODEL=0x%x)\n",
+         MII_OUI (ma->mii_id1, ma->mii_id2), MII_MODEL (ma->mii_id2)));
+  return EFI_NOT_FOUND;
+}
diff --git a/Drivers/Net/MarvellYukonDxe/e1000phyreg.h b/Drivers/Net/MarvellYukonDxe/e1000phyreg.h
new file mode 100644
index 0000000..fb21a20
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/e1000phyreg.h
@@ -0,0 +1,410 @@
+/**  <at> file
+*  Registers and Macros for Marvell 88E1000 Series PHYs. Ported from FreeBSD.
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/* $FreeBSD: src/sys/dev/mii/e1000phyreg.h,v 1.7.2.2.2.1 2010/06/14 02:09:06 kensmith Exp $ */
+/*-
+ * Principal Author: Parag Patel
+ * Copyright (c) 2001
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Additonal Copyright (c) 2001 by Traakan Software under same licence.
+ * Secondary Author: Matthew Jacob
+ */
+
+/*-
+ * Derived by information released by Intel under the following license:
+ *
+ * Copyright (c) 1999 - 2001, Intel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  1. Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *  2. Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *  3. Neither the name of Intel Corporation nor the names of its contributors
+ *     may be used to endorse or promote products derived from this software
+ *     without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Marvell E1000 PHY registers
+ */
+
+#ifndef _E1000_PHYREG_H_
+#define _E1000_PHYREG_H_
+
+#define E1000_MAX_REG_ADDRESS        0x1F
+
+#define E1000_CR            0x00    /* control register */
+#define E1000_CR_SPEED_SELECT_MSB   0x0040
+#define E1000_CR_COLL_TEST_ENABLE   0x0080
+#define E1000_CR_FULL_DUPLEX        0x0100
+#define E1000_CR_RESTART_AUTO_NEG   0x0200
+#define E1000_CR_ISOLATE            0x0400
+#define E1000_CR_POWER_DOWN         0x0800
+#define E1000_CR_AUTO_NEG_ENABLE    0x1000
+#define E1000_CR_SPEED_SELECT_LSB   0x2000
+#define E1000_CR_LOOPBACK           0x4000
+#define E1000_CR_RESET              0x8000
+
+#define E1000_CR_SPEED_1000         0x0040
+#define E1000_CR_SPEED_100          0x2000
+#define E1000_CR_SPEED_10           0x0000
+
+#define E1000_SR                    0x01    /* status register */
+#define E1000_SR_EXTENDED           0x0001
+#define E1000_SR_JABBER_DETECT      0x0002
+#define E1000_SR_LINK_STATUS        0x0004
+#define E1000_SR_AUTO_NEG           0x0008
+#define E1000_SR_REMOTE_FAULT       0x0010
+#define E1000_SR_AUTO_NEG_COMPLETE  0x0020
+#define E1000_SR_PREAMBLE_SUPPRESS  0x0040
+#define E1000_SR_EXTENDED_STATUS    0x0100
+#define E1000_SR_100T2              0x0200
+#define E1000_SR_100T2_FD           0x0400
+#define E1000_SR_10T                0x0800
+#define E1000_SR_10T_FD             0x1000
+#define E1000_SR_100TX              0x2000
+#define E1000_SR_100TX_FD           0x4000
+#define E1000_SR_100T4              0x8000
+#define E1000_SR_MEDIAMASK  (E1000_SR_100T4|E1000_SR_100TX_FD|E1000_SR_100TX| \
+  E1000_SR_10T_FD|E1000_SR_10T|E1000_SR_100T2_FD|E1000_SR_100T2)
+
+#define E1000_ID1            0x02    /* ID register 1 */
+#define E1000_ID2            0x03    /* ID register 2 */
+#define E1000_ID_88E1000     0x01410C50
+#define E1000_ID_88E1000S    0x01410C40
+#define E1000_ID_88E1011     0x01410C20
+#define E1000_ID_MASK        0xFFFFFFF0
+
+#define IDR2_OUILSB 0xfc00  /* OUI LSB */
+#define IDR2_MODEL  0x03f0  /* vendor model */
+#define IDR2_REV  0x000f    /* vendor revision */
+#define MII_OUI(id1, id2)   (((id1) << 6) | ((id2) >> 10))
+#define MII_MODEL(id2)      (((id2) & IDR2_MODEL) >> 4)
+#define MII_REV(id2)        ((id2) & IDR2_REV)
+
+
+#define E1000_AR                0x04    /* autonegotiation advertise reg */
+#define E1000_AR_SELECTOR_FIELD 0x0001
+#define E1000_AR_10T            0x0020
+#define E1000_AR_10T_FD         0x0040
+#define E1000_AR_100TX          0x0080
+#define E1000_AR_100TX_FD       0x0100
+#define E1000_AR_100T4          0x0200
+#define E1000_AR_PAUSE          0x0400
+#define E1000_AR_ASM_DIR        0x0800
+#define E1000_AR_REMOTE_FAULT   0x2000
+#define E1000_AR_NEXT_PAGE      0x8000
+#define E1000_AR_SPEED_MASK     0x01E0
+
+/* Autonegotiation register bits for fiber cards (Alaska Only!) */
+#define E1000_FA_1000X_FD       0x0020
+#define E1000_FA_1000X          0x0040
+#define E1000_FA_SYM_PAUSE      0x0080
+#define E1000_FA_ASYM_PAUSE     0x0100
+#define E1000_FA_FAULT1         0x1000
+#define E1000_FA_FAULT2         0x2000
+#define E1000_FA_NEXT_PAGE      0x8000
+
+#define E1000_LPAR                0x05    /* autoneg link partner abilities reg */
+#define E1000_LPAR_SELECTOR_FIELD 0x0001
+#define E1000_LPAR_10T            0x0020
+#define E1000_LPAR_10T_FD         0x0040
+#define E1000_LPAR_100TX          0x0080
+#define E1000_LPAR_100TX_FD       0x0100
+#define E1000_LPAR_100T4          0x0200
+#define E1000_LPAR_PAUSE          0x0400
+#define E1000_LPAR_ASM_DIR        0x0800
+#define E1000_LPAR_REMOTE_FAULT   0x2000
+#define E1000_LPAR_ACKNOWLEDGE    0x4000
+#define E1000_LPAR_NEXT_PAGE      0x8000
+
+/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */
+#define E1000_FPAR_1000X_FD       0x0020
+#define E1000_FPAR_1000X          0x0040
+#define E1000_FPAR_SYM_PAUSE      0x0080
+#define E1000_FPAR_ASYM_PAUSE     0x0100
+#define E1000_FPAR_FAULT1         0x1000
+#define E1000_FPAR_FAULT2         0x2000
+#define E1000_FPAR_ACK            0x4000
+#define E1000_FPAR_NEXT_PAGE      0x8000
+
+#define E1000_ER                     0x06    /* autoneg expansion reg */
+#define E1000_ER_LP_NWAY             0x0001
+#define E1000_ER_PAGE_RXD            0x0002
+#define E1000_ER_NEXT_PAGE           0x0004
+#define E1000_ER_LP_NEXT_PAGE        0x0008
+#define E1000_ER_PAR_DETECT_FAULT    0x0100
+
+#define E1000_NPTX                0x07    /* autoneg next page TX */
+#define E1000_NPTX_MSG_CODE_FIELD 0x0001
+#define E1000_NPTX_TOGGLE         0x0800
+#define E1000_NPTX_ACKNOWLDGE2    0x1000
+#define E1000_NPTX_MSG_PAGE       0x2000
+#define E1000_NPTX_NEXT_PAGE      0x8000
+
+#define E1000_RNPR                0x08    /* autoneg link-partner (?) next page */
+#define E1000_RNPR_MSG_CODE_FIELD 0x0001
+#define E1000_RNPR_TOGGLE         0x0800
+#define E1000_RNPR_ACKNOWLDGE2    0x1000
+#define E1000_RNPR_MSG_PAGE       0x2000
+#define E1000_RNPR_ACKNOWLDGE     0x4000
+#define E1000_RNPR_NEXT_PAGE      0x8000
+
+#define E1000_1GCR                  0x09    /* 1000T (1G) control reg */
+#define E1000_1GCR_ASYM_PAUSE       0x0080
+#define E1000_1GCR_1000T            0x0100
+#define E1000_1GCR_1000T_FD         0x0200
+#define E1000_1GCR_REPEATER_DTE     0x0400
+#define E1000_1GCR_MS_VALUE         0x0800
+#define E1000_1GCR_MS_ENABLE        0x1000
+#define E1000_1GCR_TEST_MODE_NORMAL 0x0000
+#define E1000_1GCR_TEST_MODE_1      0x2000
+#define E1000_1GCR_TEST_MODE_2      0x4000
+#define E1000_1GCR_TEST_MODE_3      0x6000
+#define E1000_1GCR_TEST_MODE_4      0x8000
+#define E1000_1GCR_SPEED_MASK       0x0300
+
+#define E1000_1GSR                  0x0A    /* 1000T (1G) status reg */
+#define E1000_1GSR_IDLE_ERROR_CNT   0x0000
+#define E1000_1GSR_ASYM_PAUSE_DIR   0x0100
+#define E1000_1GSR_LP               0x0400
+#define E1000_1GSR_LP_FD            0x0800
+#define E1000_1GSR_REMOTE_RX_STATUS 0x1000
+#define E1000_1GSR_LOCAL_RX_STATUS  0x2000
+#define E1000_1GSR_MS_CONFIG_RES    0x4000
+#define E1000_1GSR_MS_CONFIG_FAULT  0x8000
+
+#define E1000_ESR                   0x0F    /* IEEE extended status reg */
+#define E1000_ESR_1000T             0x1000
+#define E1000_ESR_1000T_FD          0x2000
+#define E1000_ESR_1000X             0x4000
+#define E1000_ESR_1000X_FD          0x8000
+
+#define E1000_TX_POLARITY_MASK      0x0100
+#define E1000_TX_NORMAL_POLARITY    0
+
+#define E1000_AUTO_POLARITY_DISABLE 0x0010
+
+#define E1000_SCR                   0x10    /* special control register */
+#define E1000_SCR_JABBER_DISABLE    0x0001
+#define E1000_SCR_POLARITY_REVERSAL 0x0002
+#define E1000_SCR_SQE_TEST          0x0004
+#define E1000_SCR_INT_FIFO_DISABLE  0x0008
+#define E1000_SCR_CLK125_DISABLE    0x0010
+#define E1000_SCR_MDI_MANUAL_MODE   0x0000
+#define E1000_SCR_MDIX_MANUAL_MODE  0x0020
+#define E1000_SCR_AUTO_X_1000T      0x0040
+#define E1000_SCR_AUTO_X_MODE       0x0060
+#define E1000_SCR_10BT_EXT_ENABLE   0x0080
+#define E1000_SCR_MII_5BIT_ENABLE   0x0100
+#define E1000_SCR_SCRAMBLER_DISABLE 0x0200
+#define E1000_SCR_FORCE_LINK_GOOD   0x0400
+#define E1000_SCR_ASSERT_CRS_ON_TX  0x0800
+#define E1000_SCR_RX_FIFO_DEPTH_6   0x0000
+#define E1000_SCR_RX_FIFO_DEPTH_8   0x1000
+#define E1000_SCR_RX_FIFO_DEPTH_10  0x2000
+#define E1000_SCR_RX_FIFO_DEPTH_12  0x3000
+#define E1000_SCR_TX_FIFO_DEPTH_6   0x0000
+#define E1000_SCR_TX_FIFO_DEPTH_8   0x4000
+#define E1000_SCR_TX_FIFO_DEPTH_10  0x8000
+#define E1000_SCR_TX_FIFO_DEPTH_12  0xC000
+
+/* 88E3016 only */
+#define    E1000_SCR_AUTO_MDIX        0x0030
+#define    E1000_SCR_SIGDET_POLARITY  0x0040
+#define    E1000_SCR_EXT_DISTANCE     0x0080
+#define    E1000_SCR_FEFI_DISABLE     0x0100
+#define    E1000_SCR_NLP_GEN_DISABLE  0x0800
+#define    E1000_SCR_LPNP             0x1000
+#define    E1000_SCR_NLP_CHK_DISABLE  0x2000
+#define    E1000_SCR_EN_DETECT        0x4000
+
+#define E1000_SCR_EN_DETECT_MASK      0x0300
+
+/* 88E1112 page 1 fiber specific control */
+#define E1000_SCR_FIB_TX_DIS          0x0008
+#define E1000_SCR_FIB_SIGDET_POLARITY 0x0200
+#define E1000_SCR_FIB_FORCE_LINK      0x0400
+
+/* 88E1112 page 2 */
+#define E1000_SCR_MODE_MASK           0x0380
+#define E1000_SCR_MODE_AUTO           0x0180
+#define E1000_SCR_MODE_COPPER         0x0280
+#define E1000_SCR_MODE_1000BX         0x0380
+
+/* 88E1116 page 0 */
+#define    E1000_SCR_POWER_DOWN       0x0004
+/* 88E1116, 88E1149 page 2 */
+#define    E1000_SCR_RGMII_POWER_UP   0x0008
+
+/* 88E1116, 88E1149 page 3 */
+#define E1000_SCR_LED_STAT0_MASK      0x000F
+#define E1000_SCR_LED_STAT1_MASK      0x00F0
+#define E1000_SCR_LED_INIT_MASK       0x0F00
+#define E1000_SCR_LED_LOS_MASK        0xF000
+#define E1000_SCR_LED_STAT0(x)        ((x) & E1000_SCR_LED_STAT0_MASK)
+#define E1000_SCR_LED_STAT1(x)        ((x) & E1000_SCR_LED_STAT1_MASK)
+#define E1000_SCR_LED_INIT(x)         ((x) & E1000_SCR_LED_INIT_MASK)
+#define E1000_SCR_LED_LOS(x)          ((x) & E1000_SCR_LED_LOS_MASK)
+
+#define E1000_SSR                   0x11    /* special status register */
+#define E1000_SSR_JABBER            0x0001
+#define E1000_SSR_REV_POLARITY      0x0002
+#define E1000_SSR_MDIX              0x0020
+#define E1000_SSR_LINK              0x0400
+#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
+#define E1000_SSR_PAGE_RCVD         0x1000
+#define E1000_SSR_DUPLEX            0x2000
+#define E1000_SSR_SPEED             0xC000
+#define E1000_SSR_10MBS             0x0000
+#define E1000_SSR_100MBS            0x4000
+#define E1000_SSR_1000MBS           0x8000
+
+#define E1000_IER                   0x12    /* interrupt enable reg */
+#define E1000_IER_JABBER            0x0001
+#define E1000_IER_POLARITY_CHANGE   0x0002
+#define E1000_IER_MDIX_CHANGE       0x0040
+#define E1000_IER_FIFO_OVER_UNDERUN 0x0080
+#define E1000_IER_FALSE_CARRIER     0x0100
+#define E1000_IER_SYMBOL_ERROR      0x0200
+#define E1000_IER_LINK_STAT_CHANGE  0x0400
+#define E1000_IER_AUTO_NEG_COMPLETE 0x0800
+#define E1000_IER_PAGE_RECEIVED     0x1000
+#define E1000_IER_DUPLEX_CHANGED    0x2000
+#define E1000_IER_SPEED_CHANGED     0x4000
+#define E1000_IER_AUTO_NEG_ERR      0x8000
+
+/* 88E1116, 88E1149 page 3, LED timer control. */
+#define    E1000_PULSE_MASK       0x7000
+#define    E1000_PULSE_NO_STR     0    /* no pulse stretching */
+#define    E1000_PULSE_21MS       1    /* 21 ms to 42 ms */
+#define    E1000_PULSE_42MS       2    /* 42 ms to 84 ms */
+#define    E1000_PULSE_84MS       3    /* 84 ms to 170 ms */
+#define    E1000_PULSE_170MS      4    /* 170 ms to 340 ms */
+#define    E1000_PULSE_340MS      5    /* 340 ms to 670 ms */
+#define    E1000_PULSE_670MS      6    /* 670 ms to 1300 ms */
+#define    E1000_PULSE_1300MS     7    /* 1300 ms to 2700 ms */
+#define    E1000_PULSE_DUR(x)     ((x) &    E1000_PULSE_MASK)
+
+#define    E1000_BLINK_MASK       0x0700
+#define    E1000_BLINK_42MS       0    /* 42 ms */
+#define    E1000_BLINK_84MS       1    /* 84 ms */
+#define    E1000_BLINK_170MS      2    /* 170 ms */
+#define    E1000_BLINK_340MS      3    /* 340 ms */
+#define    E1000_BLINK_670MS      4    /* 670 ms */
+#define    E1000_BLINK_RATE(x)    ((x) &    E1000_BLINK_MASK)
+
+#define E1000_ISR                   0x13    /* interrupt status reg */
+#define E1000_ISR_JABBER            0x0001
+#define E1000_ISR_POLARITY_CHANGE   0x0002
+#define E1000_ISR_MDIX_CHANGE       0x0040
+#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
+#define E1000_ISR_FALSE_CARRIER     0x0100
+#define E1000_ISR_SYMBOL_ERROR      0x0200
+#define E1000_ISR_LINK_STAT_CHANGE  0x0400
+#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
+#define E1000_ISR_PAGE_RECEIVED     0x1000
+#define E1000_ISR_DUPLEX_CHANGED    0x2000
+#define E1000_ISR_SPEED_CHANGED     0x4000
+#define E1000_ISR_AUTO_NEG_ERR      0x8000
+
+#define E1000_ESCR                  0x14    /* extended special control reg */
+#define E1000_ESCR_FIBER_LOOPBACK   0x4000
+#define E1000_ESCR_DOWN_NO_IDLE     0x8000
+#define E1000_ESCR_TX_CLK_2_5       0x0060
+#define E1000_ESCR_TX_CLK_25        0x0070
+#define E1000_ESCR_TX_CLK_0         0x0000
+
+#define E1000_RECR                  0x15    /* RX error counter reg */
+
+#define E1000_EADR                  0x16    /* extended address reg */
+
+#define E1000_LCR                   0x18    /* LED control reg */
+#define E1000_LCR_LED_TX            0x0001
+#define E1000_LCR_LED_RX            0x0002
+#define E1000_LCR_LED_DUPLEX        0x0004
+#define E1000_LCR_LINK              0x0008
+#define E1000_LCR_BLINK_42MS        0x0000
+#define E1000_LCR_BLINK_84MS        0x0100
+#define E1000_LCR_BLINK_170MS       0x0200
+#define E1000_LCR_BLINK_340MS       0x0300
+#define E1000_LCR_BLINK_670MS       0x0400
+#define E1000_LCR_PULSE_OFF         0x0000
+#define E1000_LCR_PULSE_21_42MS     0x1000
+#define E1000_LCR_PULSE_42_84MS     0x2000
+#define E1000_LCR_PULSE_84_170MS    0x3000
+#define E1000_LCR_PULSE_170_340MS   0x4000
+#define E1000_LCR_PULSE_340_670MS   0x5000
+#define E1000_LCR_PULSE_670_13S     0x6000
+#define E1000_LCR_PULSE_13_26S      0x7000
+
+/* The following register is found only on the 88E1011 Alaska PHY */
+#define E1000_ESSR                  0x1B    /* Extended PHY specific sts */
+#define E1000_ESSR_FIBER_LINK       0x2000
+#define E1000_ESSR_GMII_COPPER      0x000f
+#define E1000_ESSR_GMII_FIBER       0x0007
+#define E1000_ESSR_TBI_COPPER       0x000d
+#define E1000_ESSR_TBI_FIBER        0x0005
+
+struct e1000phy_softc {
+  struct mii_softc mii_sc;
+  INTN mii_model;
+  const struct msk_mii_data *mmd;
+  VOID *sc_if; /* parent logical controller */
+};
+
+#endif /* _E1000_PHYREG_H_ */
diff --git a/Drivers/Net/MarvellYukonDxe/if_media.h b/Drivers/Net/MarvellYukonDxe/if_media.h
new file mode 100644
index 0000000..cdc1a58
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/if_media.h
@@ -0,0 +1,273 @@
+/**  <at> file
+*  Prototypes and definitions for BSD/OS-compatible network interface media selection.
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/*  $NetBSD: if_media.h,v 1.3 1997/03/26 01:19:27 thorpej Exp $  */
+/* $FreeBSD: src/sys/net/if_media.h,v 1.47.2.1.4.1 2010/06/14 02:09:06 kensmith Exp $ */
+
+/*-
+ * Copyright (c) 1997
+ *  Jonathan Stone and Jason R. Thorpe.  All rights reserved.
+ *
+ * This software is derived from information provided by Matt Thomas.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *  This product includes software developed by Jonathan Stone
+ *  and Jason R. Thorpe for the NetBSD Project.
+ * 4. The names of the authors may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _NET_IF_MEDIA_H_
+#define _NET_IF_MEDIA_H_
+
+/*
+ * Prototypes and definitions for BSD/OS-compatible network interface
+ * media selection.
+ *
+ * Where it is safe to do so, this code strays slightly from the BSD/OS
+ * design.  Software which uses the API (device drivers, basically)
+ * shouldn't notice any difference.
+ *
+ * Many thanks to Matt Thomas for providing the information necessary
+ * to implement this interface.
+ */
+
+/*
+ * if_media Options word:
+ *  Bits  Use
+ *  ----  -------
+ *  0-4  Media variant
+ *  5-7  Media type
+ *  8-15  Type specific options
+ *  16-18  Mode (for multi-mode devices)
+ *  19  RFU
+ *  20-27  Shared (global) options
+ *  28-31  Instance
+ */
+
+/*
+ * Ethernet
+ */
+#define  IFM_ETHER          0x00000020
+#define  IFM_10_T           3   /* 10BaseT - RJ45 */
+#define  IFM_10_2           4   /* 10Base2 - Thinnet */
+#define  IFM_10_5           5   /* 10Base5 - AUI */
+#define  IFM_100_TX         6   /* 100BaseTX - RJ45 */
+#define  IFM_100_FX         7   /* 100BaseFX - Fiber */
+#define  IFM_100_T4         8   /* 100BaseT4 - 4 pair cat 3 */
+#define  IFM_100_VG         9   /* 100VG-AnyLAN */
+#define  IFM_100_T2         10  /* 100BaseT2 */
+#define  IFM_1000_SX        11  /* 1000BaseSX - multi-mode fiber */
+#define  IFM_10_STP         12  /* 10BaseT over shielded TP */
+#define  IFM_10_FL          13  /* 10BaseFL - Fiber */
+#define  IFM_1000_LX        14  /* 1000baseLX - single-mode fiber */
+#define  IFM_1000_CX        15  /* 1000baseCX - 150ohm STP */
+#define  IFM_1000_T         16  /* 1000baseT - 4 pair cat 5 */
+#define  IFM_HPNA_1         17  /* HomePNA 1.0 (1Mb/s) */
+#define  IFM_10G_LR         18  /* 10GBase-LR 1310nm Single-mode */
+#define  IFM_10G_SR         19  /* 10GBase-SR 850nm Multi-mode */
+#define  IFM_10G_CX4        20  /* 10GBase CX4 copper */
+#define IFM_2500_SX         21  /* 2500BaseSX - multi-mode fiber */
+#define IFM_10G_TWINAX      22  /* 10GBase Twinax copper */
+#define IFM_10G_TWINAX_LONG 23  /* 10GBase Twinax Long copper */
+#define IFM_10G_LRM         24  /* 10GBase-LRM 850nm Multi-mode */
+#define IFM_UNKNOWN         25  /* media types not defined yet */
+#define IFM_10G_T           26  /* 10GBase-T - RJ45 */
+
+
+/* note 31 is the max! */
+
+#define  IFM_ETH_MASTER  0x00000100  /* master mode (1000baseT) */
+
+/*
+ * Token ring
+ */
+#define  IFM_TOKEN        0x00000040
+#define  IFM_TOK_STP4     3    /* Shielded twisted pair 4m - DB9 */
+#define  IFM_TOK_STP16    4    /* Shielded twisted pair 16m - DB9 */
+#define  IFM_TOK_UTP4     5    /* Unshielded twisted pair 4m - RJ45 */
+#define  IFM_TOK_UTP16    6    /* Unshielded twisted pair 16m - RJ45 */
+#define  IFM_TOK_STP100   7    /* Shielded twisted pair 100m - DB9 */
+#define  IFM_TOK_UTP100   8    /* Unshielded twisted pair 100m - RJ45 */
+#define  IFM_TOK_ETR      0x00000200  /* Early token release */
+#define  IFM_TOK_SRCRT    0x00000400  /* Enable source routing features */
+#define  IFM_TOK_ALLR     0x00000800  /* All routes / Single route bcast */
+#define  IFM_TOK_DTR      0x00002000  /* Dedicated token ring */
+#define  IFM_TOK_CLASSIC  0x00004000  /* Classic token ring */
+#define  IFM_TOK_AUTO     0x00008000  /* Automatic Dedicate/Classic token ring */
+
+/*
+ * FDDI
+ */
+#define  IFM_FDDI       0x00000060
+#define  IFM_FDDI_SMF   3    /* Single-mode fiber */
+#define  IFM_FDDI_MMF   4    /* Multi-mode fiber */
+#define  IFM_FDDI_UTP   5    /* CDDI / UTP */
+#define  IFM_FDDI_DA    0x00000100  /* Dual attach / single attach */
+
+/*
+ * IEEE 802.11 Wireless
+ */
+#define  IFM_IEEE80211          0x00000080
+/* NB: 0,1,2 are auto, manual, none defined below */
+#define  IFM_IEEE80211_FH1      3  /* Frequency Hopping 1Mbps */
+#define  IFM_IEEE80211_FH2      4  /* Frequency Hopping 2Mbps */
+#define  IFM_IEEE80211_DS1      5  /* Direct Sequence 1Mbps */
+#define  IFM_IEEE80211_DS2      6  /* Direct Sequence 2Mbps */
+#define  IFM_IEEE80211_DS5      7  /* Direct Sequence 5.5Mbps */
+#define  IFM_IEEE80211_DS11     8  /* Direct Sequence 11Mbps */
+#define  IFM_IEEE80211_DS22     9  /* Direct Sequence 22Mbps */
+#define  IFM_IEEE80211_OFDM6    10  /* OFDM 6Mbps */
+#define  IFM_IEEE80211_OFDM9    11  /* OFDM 9Mbps */
+#define  IFM_IEEE80211_OFDM12   12  /* OFDM 12Mbps */
+#define  IFM_IEEE80211_OFDM18   13  /* OFDM 18Mbps */
+#define  IFM_IEEE80211_OFDM24   14  /* OFDM 24Mbps */
+#define  IFM_IEEE80211_OFDM36   15  /* OFDM 36Mbps */
+#define  IFM_IEEE80211_OFDM48   16  /* OFDM 48Mbps */
+#define  IFM_IEEE80211_OFDM54   17  /* OFDM 54Mbps */
+#define  IFM_IEEE80211_OFDM72   18  /* OFDM 72Mbps */
+#define  IFM_IEEE80211_DS354k   19  /* Direct Sequence 354Kbps */
+#define  IFM_IEEE80211_DS512k   20  /* Direct Sequence 512Kbps */
+#define  IFM_IEEE80211_OFDM3    21  /* OFDM 3Mbps */
+#define  IFM_IEEE80211_OFDM4    22  /* OFDM 4.5Mbps */
+#define  IFM_IEEE80211_OFDM27   23  /* OFDM 27Mbps */
+/* NB: not enough bits to express MCS fully */
+#define  IFM_IEEE80211_MCS      24  /* HT MCS rate */
+
+#define  IFM_IEEE80211_ADHOC    0x00000100  /* Operate in Adhoc mode */
+#define  IFM_IEEE80211_HOSTAP   0x00000200  /* Operate in Host AP mode */
+#define  IFM_IEEE80211_IBSS     0x00000400  /* Operate in IBSS mode */
+#define  IFM_IEEE80211_WDS      0x00000800  /* Operate in WDS mode */
+#define  IFM_IEEE80211_TURBO    0x00001000  /* Operate in turbo mode */
+#define  IFM_IEEE80211_MONITOR  0x00002000  /* Operate in monitor mode */
+#define  IFM_IEEE80211_MBSS     0x00004000  /* Operate in MBSS mode */
+
+/* operating mode for multi-mode devices */
+#define  IFM_IEEE80211_11A      0x00010000  /* 5Ghz, OFDM mode */
+#define  IFM_IEEE80211_11B      0x00020000  /* Direct Sequence mode */
+#define  IFM_IEEE80211_11G      0x00030000  /* 2Ghz, CCK mode */
+#define  IFM_IEEE80211_FH       0x00040000  /* 2Ghz, GFSK mode */
+#define  IFM_IEEE80211_11NA     0x00050000  /* 5Ghz, HT mode */
+#define  IFM_IEEE80211_11NG     0x00060000  /* 2Ghz, HT mode */
+
+/*
+ * ATM
+ */
+#define IFM_ATM             0x000000a0
+#define IFM_ATM_UNKNOWN     3
+#define IFM_ATM_UTP_25      4
+#define IFM_ATM_TAXI_100    5
+#define IFM_ATM_TAXI_140    6
+#define IFM_ATM_MM_155      7
+#define IFM_ATM_SM_155      8
+#define IFM_ATM_UTP_155     9
+#define IFM_ATM_MM_622      10
+#define IFM_ATM_SM_622      11
+#define  IFM_ATM_VIRTUAL    12
+#define IFM_ATM_SDH         0x00000100  /* SDH instead of SONET */
+#define IFM_ATM_NOSCRAMB    0x00000200  /* no scrambling */
+#define IFM_ATM_UNASSIGNED  0x00000400  /* unassigned cells */
+
+/*
+ * CARP Common Address Redundancy Protocol
+ */
+#define  IFM_CARP  0x000000c0
+
+/*
+ * Shared media sub-types
+ */
+#define  IFM_AUTO   0    /* Autoselect best media */
+#define  IFM_MANUAL 1    /* Jumper/dipswitch selects media */
+#define  IFM_NONE   2    /* Deselect all media */
+
+/*
+ * Shared options
+ */
+#define  IFM_FDX   0x00100000  /* Force full duplex */
+#define  IFM_HDX   0x00200000  /* Force half duplex */
+#define  IFM_FLAG0 0x01000000  /* Driver defined flag */
+#define  IFM_FLAG1 0x02000000  /* Driver defined flag */
+#define  IFM_FLAG2 0x04000000  /* Driver defined flag */
+#define  IFM_LOOP  0x08000000  /* Put hardware in loopback */
+
+/*
+ * Masks
+ */
+#define  IFM_NMASK  0x000000e0  /* Network type */
+#define  IFM_TMASK  0x0000001f  /* Media sub-type */
+#define  IFM_IMASK  0xf0000000  /* Instance */
+#define  IFM_ISHIFT 28    /* Instance shift */
+#define  IFM_OMASK  0x0000ff00  /* Type specific options */
+#define  IFM_MMASK  0x00070000  /* Mode */
+#define  IFM_MSHIFT 16    /* Mode shift */
+#define  IFM_GMASK  0x0ff00000  /* Global options */
+
+/*
+ * Status bits
+ */
+#define  IFM_AVALID  0x00000001  /* Active bit valid */
+#define  IFM_ACTIVE  0x00000002  /* Interface attached to working net */
+
+/* Mask of "status valid" bits, for ifconfig(8). */
+#define  IFM_STATUS_VALID  IFM_AVALID
+
+/* List of "status valid" bits, for ifconfig(8). */
+#define IFM_STATUS_VALID_LIST {            \
+  IFM_AVALID,              \
+  0                \
+  }
+
+/*
+ * Macros to extract various bits of information from the media word.
+ */
+#define  IFM_TYPE(x)         ((x) & IFM_NMASK)
+#define  IFM_SUBTYPE(x)      ((x) & IFM_TMASK)
+#define  IFM_TYPE_OPTIONS(x) ((x) & IFM_OMASK)
+#define  IFM_INST(x)         (((x) & IFM_IMASK) >> IFM_ISHIFT)
+#define  IFM_OPTIONS(x)      ((x) & (IFM_OMASK|IFM_GMASK))
+#define  IFM_MODE(x)         ((x) & IFM_MMASK)
+
+#define  IFM_INST_MAX  IFM_INST(IFM_IMASK)
+
+/*
+ * Macro to create a media word.
+ */
+#define  IFM_MAKEWORD(type, subtype, options, instance)      \
+  ((type) | (subtype) | (options) | ((instance) << IFM_ISHIFT))
+#define  IFM_MAKEMODE(mode) \
+  (((mode) << IFM_MSHIFT) & IFM_MMASK)
+
+
+#endif  /* _NET_IF_MEDIA_H_ */
diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.c b/Drivers/Net/MarvellYukonDxe/if_msk.c
new file mode 100644
index 0000000..3ab52b1
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/if_msk.c
@@ -0,0 +1,2977 @@
+/**  <at> file
+*  Support for PCIe Marvell Yukon gigabit ethernet adapter product family
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+/******************************************************************************
+ *
+ *  LICENSE:
+ *  Copyright (C) Marvell International Ltd. and/or its affiliates
+ *
+ *  The computer program files contained in this folder ("Files")
+ *  are provided to you under the BSD-type license terms provided
+ *  below, and any use of such Files and any derivative works
+ *  thereof created by you shall be governed by the following terms
+ *  and conditions:
+ *
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  - Neither the name of Marvell nor the names of its contributors
+ *    may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ *  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF  SUBSTITUTE GOODS OR SERVICES;
+ *  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ *  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ *  OF THE POSSIBILITY OF SUCH DAMAGE.
+ *  /LICENSE
+ *
+ *****************************************************************************/
+
+/*-
+ * Copyright (c) 1997, 1998, 1999, 2000
+ *  Bill Paul <wpaul <at> ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *  This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*-
+ * Copyright (c) 2003 Nathan L. Binkert <binkertn <at> umich.edu>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Device driver for the Marvell Yukon II Ethernet controller.
+ * Due to lack of documentation, this driver is based on the code from
+ * sk (4) and Marvell's myk (4) driver for FreeBSD 5.x.
+ */
+
+#include <Base.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/NetLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/PciIo.h>
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/Acpi.h>
+#include "miivar.h"
+#include "if_media.h"
+#include "if_mskreg.h"
+#include "if_msk.h"
+
+#define MSK_CSUM_FEATURES  (CSUM_TCP | CSUM_UDP)
+
+/*
+ * Devices supported by this driver.
+ */
+static struct msk_product {
+  UINT16  msk_vendorid;
+  UINT16  msk_deviceid;
+  const CHAR8  *msk_name;
+} msk_products[] = {
+{ VENDORID_SK,      DEVICEID_SK_YUKON2,       "SK-9Sxx Gigabit Ethernet" },
+{ VENDORID_SK,      DEVICEID_SK_YUKON2_EXPR,  "SK-9Exx Gigabit Ethernet"},
+{ VENDORID_MARVELL, DEVICEID_MRVL_8021CU,     "Marvell Yukon 88E8021CU Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8021X,      "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8022CU,     "Marvell Yukon 88E8022CU Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8022X,      "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8061CU,     "Marvell Yukon 88E8061CU Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8061X,      "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8062CU,     "Marvell Yukon 88E8062CU Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8062X,      "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8035,       "Marvell Yukon 88E8035 Fast Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8036,       "Marvell Yukon 88E8036 Fast Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8038,       "Marvell Yukon 88E8038 Fast Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8039,       "Marvell Yukon 88E8039 Fast Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8040,       "Marvell Yukon 88E8040 Fast Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8040T,      "Marvell Yukon 88E8040T Fast Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8042,       "Marvell Yukon 88E8042 Fast Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_8048,       "Marvell Yukon 88E8048 Fast Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_4361,       "Marvell Yukon 88E8050 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_4360,       "Marvell Yukon 88E8052 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_4362,       "Marvell Yukon 88E8053 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_4363,       "Marvell Yukon 88E8055 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_4364,       "Marvell Yukon 88E8056 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_4365,       "Marvell Yukon 88E8070 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_436A,       "Marvell Yukon 88E8058 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_436B,       "Marvell Yukon 88E8071 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_436C,       "Marvell Yukon 88E8072 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_4380,       "Marvell Yukon 88E8057 Gigabit Ethernet" },
+{ VENDORID_MARVELL, DEVICEID_MRVL_4381,       "Marvell Yukon 88E8059 Gigabit Ethernet" },
+{ VENDORID_DLINK,   DEVICEID_DLINK_DGE550SX,  "D-Link 550SX Gigabit Ethernet" },
+{ VENDORID_DLINK,   DEVICEID_DLINK_DGE560SX,  "D-Link 560SX Gigabit Ethernet" },
+{ VENDORID_DLINK,   DEVICEID_DLINK_DGE560T,   "D-Link 560T Gigabit Ethernet" }
+};
+
+#ifndef MDEPKG_NDEBUG
+static const CHAR8 *model_name[] = {
+  "Yukon XL",
+  "Yukon EC Ultra",
+  "Yukon EX",
+  "Yukon EC",
+  "Yukon FE",
+  "Yukon FE+",
+  "Yukon Supreme",
+  "Yukon Ultra 2",
+  "Yukon Unknown",
+  "Yukon Optima",
+};
+#endif
+
+//
+// Forward declarations
+//
+STATIC VOID mskc_setup_rambuffer (struct msk_softc *);
+STATIC VOID mskc_reset (struct msk_softc *);
+
+EFI_STATUS mskc_attach_if (struct msk_if_softc *, UINTN);
+VOID mskc_detach_if (struct msk_if_softc *);
+
+static VOID mskc_tick (IN EFI_EVENT, IN VOID*);
+STATIC VOID msk_intr (struct msk_softc *);
+static VOID msk_intr_phy (struct msk_if_softc *);
+static VOID msk_intr_gmac (struct msk_if_softc *);
+static __inline VOID msk_rxput (struct msk_if_softc *);
+STATIC INTN msk_handle_events (struct msk_softc *);
+static VOID msk_handle_hwerr (struct msk_if_softc *, UINT32);
+STATIC VOID msk_intr_hwerr (struct msk_softc *);
+static VOID msk_rxeof (struct msk_if_softc *, UINT32, UINT32, INTN);
+static VOID msk_txeof (struct msk_if_softc *, INTN);
+static EFI_STATUS msk_encap (struct msk_if_softc *, MSK_SYSTEM_BUF *);
+STATIC VOID msk_start (struct msk_if_softc *);
+STATIC VOID msk_set_prefetch (struct msk_if_softc *, INTN, EFI_PHYSICAL_ADDRESS, UINT32);
+static VOID msk_set_rambuffer (struct msk_if_softc *);
+static VOID msk_set_tx_stfwd (struct msk_if_softc *);
+static EFI_STATUS msk_init (struct msk_if_softc *);
+VOID mskc_stop_if (struct msk_if_softc *);
+static VOID msk_phy_power (struct msk_softc *, INTN);
+INTN msk_phy_readreg (struct msk_if_softc *, INTN);
+INTN msk_phy_writereg (struct msk_if_softc *, INTN, INTN);
+STATIC EFI_STATUS msk_status_dma_alloc (struct msk_softc *);
+STATIC VOID msk_status_dma_free (struct msk_softc *);
+static EFI_STATUS msk_txrx_dma_alloc (struct msk_if_softc *);
+static VOID msk_txrx_dma_free (struct msk_if_softc *);
+static EFI_STATUS msk_init_rx_ring (struct msk_if_softc *);
+static VOID msk_init_tx_ring (struct msk_if_softc *);
+static __inline VOID msk_discard_rxbuf (struct msk_if_softc *, INTN);
+static EFI_STATUS msk_newbuf (struct msk_if_softc *, INTN);
+
+static VOID msk_rxfilter (
+    struct msk_if_softc         *sc_if,
+    UINT32                      FilterFlags,
+    UINTN                       MCastFilterCnt,
+    EFI_MAC_ADDRESS             *MCastFilter
+    );
+static VOID msk_setvlan (struct msk_if_softc *);
+
+static VOID msk_stats_clear (struct msk_if_softc *);
+static VOID msk_stats_update (struct msk_if_softc *);
+STATIC VOID clear_pci_errors (struct msk_softc *);
+
+EFI_STATUS e1000_probe_and_attach (struct mii_data *, const struct msk_mii_data *, VOID *, VOID **);
+VOID e1000phy_tick (VOID *);
+VOID e1000phy_mediachg (VOID *);
+EFI_STATUS e1000phy_detach (VOID *);
+
+//
+// Functions
+//
+
+INTN
+msk_phy_readreg (
+    struct msk_if_softc  *sc_if,
+    INTN                 reg
+    )
+{
+  INTN  i;
+  INTN  val;
+  INTN              port;
+  struct msk_softc  *sc;
+
+  sc = sc_if->msk_softc;
+  port = sc_if->msk_md.port;
+
+  GMAC_WRITE_2 (sc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD (PHY_ADDR_MARV) | GM_SMI_CT_REG_AD (reg) | GM_SMI_CT_OP_RD);
+
+  for (i = 0; i < MSK_TIMEOUT; i++) {
+    gBS->Stall (1);
+    val = GMAC_READ_2 (sc, port, GM_SMI_CTRL);
+    if ((val & GM_SMI_CT_RD_VAL) != 0) {
+      val = GMAC_READ_2 (sc, port, GM_SMI_DATA);
+      break;
+    }
+  }
+
+  if (i == MSK_TIMEOUT) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: phy failed to come ready\n"));
+    val = 0;
+  }
+
+  return (val);
+}
+
+INTN
+msk_phy_writereg (
+    struct msk_if_softc  *sc_if,
+    INTN  reg,
+    INTN  val
+    )
+{
+  INTN i;
+  INTN              port;
+  struct msk_softc  *sc;
+
+  sc = sc_if->msk_softc;
+  port = sc_if->msk_md.port;
+
+  GMAC_WRITE_2 (sc, port, GM_SMI_DATA, val);
+  GMAC_WRITE_2 (sc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD (PHY_ADDR_MARV) | GM_SMI_CT_REG_AD (reg));
+  for (i = 0; i < MSK_TIMEOUT; i++) {
+    gBS->Stall (1);
+    if ((GMAC_READ_2 (sc, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) {
+      break;
+    }
+  }
+  if (i == MSK_TIMEOUT) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: phy write timeout\n"));
+  }
+
+  return (0);
+}
+
+VOID
+msk_miibus_statchg (
+    struct msk_if_softc  *sc_if
+    )
+{
+  struct mii_data       *mii;
+  UINT32                gmac;
+  UINTN                 port;
+  struct msk_softc      *sc;
+
+  sc = sc_if->msk_softc;
+  port = sc_if->msk_md.port;
+  mii = &sc_if->mii_d;
+  sc_if->msk_flags &= ~MSK_FLAG_LINK;
+
+  if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE)) {
+
+    DEBUG ((EFI_D_NET, "Marvell Yukon: msk_miibus_statchg, phy is active\n"));
+    switch (IFM_SUBTYPE (mii->mii_media_active)) {
+      case IFM_10_T:
+      case IFM_100_TX:
+        sc_if->msk_flags |= MSK_FLAG_LINK;
+        break;
+      case IFM_1000_T:
+      case IFM_1000_SX:
+      case IFM_1000_LX:
+      case IFM_1000_CX:
+        if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) {
+          sc_if->msk_flags |= MSK_FLAG_LINK;
+        }
+        break;
+      default:
+        break;
+    }
+  }
+
+  if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
+    // Enable Tx FIFO Underrun
+    DEBUG ((EFI_D_NET, "Marvell Yukon: msk_miibus_statchg, link up\n"));
+
+    CSR_WRITE_1 (sc, MR_ADDR (port, GMAC_IRQ_MSK), GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
+    //
+    // Because mii(4) notify msk (4) that it detected link status
+    // change, there is no need to enable automatic
+    // speed/flow-control/duplex updates.
+    //
+    gmac = GM_GPCR_AU_ALL_DIS;
+    switch (IFM_SUBTYPE (mii->mii_media_active)) {
+      case IFM_1000_SX:
+      case IFM_1000_T:
+        gmac |= GM_GPCR_SPEED_1000;
+        break;
+      case IFM_100_TX:
+        gmac |= GM_GPCR_SPEED_100;
+        break;
+      case IFM_10_T:
+        break;
+    }
+
+    // Disable Rx flow control
+    if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FLAG0) == 0) {
+      gmac |= GM_GPCR_FC_RX_DIS;
+    }
+    // Disable Tx flow control
+    if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FLAG1) == 0) {
+      gmac |= GM_GPCR_FC_TX_DIS;
+    }
+    if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FDX) != 0) {
+      gmac |= GM_GPCR_DUP_FULL;
+    } else {
+      gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;
+    }
+    gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
+    GMAC_WRITE_2 (sc, port, GM_GP_CTRL, gmac);
+    // Read again to ensure writing
+    GMAC_READ_2 (sc, port, GM_GP_CTRL);
+    gmac = GMC_PAUSE_OFF;
+    if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FDX) != 0) {
+      if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FLAG0) != 0) {
+        gmac = GMC_PAUSE_ON;
+      }
+    }
+    CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), gmac);
+
+    // Enable PHY interrupt for FIFO underrun/overflow
+    msk_phy_writereg (sc_if, PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
+  } else {
+    //
+    // Link state changed to down.
+    // Disable PHY interrupts.
+    //
+    DEBUG ((EFI_D_NET, "Marvell Yukon: msk_miibus_statchg, link down\n"));
+    msk_phy_writereg (sc_if, PHY_MARV_INT_MASK, 0);
+    // Disable Rx/Tx MAC
+    gmac = GMAC_READ_2 (sc, port, GM_GP_CTRL);
+    if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) {
+      gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
+      GMAC_WRITE_2 (sc, port, GM_GP_CTRL, gmac);
+      // Read again to ensure writing
+      GMAC_READ_2 (sc, port, GM_GP_CTRL);
+    }
+  }
+}
+
+UINT32
+ether_crc32_be (
+    const UINT8   *buf,
+    UINTN         len
+    )
+{
+  UINTN     i;
+  UINT32    crc;
+  UINT32    carry;
+  INTN      bit;
+  UINT8     data;
+
+  crc = 0xffffffff; // initial value
+
+  for (i = 0; i < len; i++) {
+    for (data = *buf++, bit = 0; bit < 8; bit++, data >>= 1) {
+      carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
+      crc <<= 1;
+      if (carry) {
+        crc = (crc ^ ETHER_CRC_POLY_BE) | carry;
+      }
+    }
+  }
+
+  return crc;
+}
+
+VOID
+mskc_rxfilter (
+    struct msk_if_softc         *sc_if,
+    UINT32                      FilterFlags,
+    UINTN                       MCastFilterCnt,
+    EFI_MAC_ADDRESS             *MCastFilter
+    )
+{
+  msk_rxfilter (sc_if, FilterFlags, MCastFilterCnt, MCastFilter);
+}
+
+static VOID
+msk_rxfilter (
+    struct msk_if_softc         *sc_if,
+    UINT32                      FilterFlags,
+    UINTN                       MCastFilterCnt,
+    EFI_MAC_ADDRESS             *MCastFilter
+    )
+{
+  UINT32  mchash[2];
+  UINT32  crc;
+  UINT16  mode;
+  INTN              port;
+  struct msk_softc  *sc;
+
+  sc = sc_if->msk_softc;
+  port = sc_if->msk_md.port;
+
+  gBS->SetMem (mchash, sizeof (mchash), 0);
+  mode = GMAC_READ_2 (sc, port, GM_RX_CTRL);
+  if ((FilterFlags & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) {
+    mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
+  }
+  else if ((FilterFlags & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) != 0) {
+    mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
+    mchash[0] = 0xffff;
+    mchash[1] = 0xffff;
+  } else {
+    mode |= GM_RXCR_UCF_ENA;
+    while (MCastFilterCnt-- > 0) {
+      crc = ether_crc32_be (MCastFilter[MCastFilterCnt].Addr, NET_ETHER_ADDR_LEN);
+      /* Just want the 6 least significant bits. */
+      crc &= 0x3f;
+      /* Set the corresponding bit in the hash table. */
+      mchash[crc >> 5] |= 1 << (crc & 0x1f);
+    }
+    if (mchash[0] != 0 || mchash[1] != 0) {
+      mode |= GM_RXCR_MCF_ENA;
+    }
+  }
+
+  GMAC_WRITE_2 (sc, port, GM_MC_ADDR_H1,  mchash[0]        & 0xffff  );
+  GMAC_WRITE_2 (sc, port, GM_MC_ADDR_H2, (mchash[0] >> 16) & 0xffff  );
+  GMAC_WRITE_2 (sc, port, GM_MC_ADDR_H3,  mchash[1]        & 0xffff  );
+  GMAC_WRITE_2 (sc, port, GM_MC_ADDR_H4, (mchash[1] >> 16) & 0xffff  );
+  GMAC_WRITE_2 (sc, port, GM_RX_CTRL,    mode                        );
+}
+
+static
+VOID
+msk_setvlan (
+    struct msk_if_softc   *sc_if
+    )
+{
+  //
+  // Disable automatic VLAN tagging/stripping
+  //
+  CSR_WRITE_4 (sc_if->msk_softc, MR_ADDR (sc_if->msk_md.port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
+  CSR_WRITE_4 (sc_if->msk_softc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
+}
+
+static
+EFI_STATUS
+msk_init_rx_ring (
+    struct msk_if_softc   *sc_if
+    )
+{
+  struct msk_ring_data  *rd;
+  struct msk_rxdesc     *rxd;
+  INTN                  i;
+  INTN                  prod;
+  INTN                  nbuf;
+  EFI_STATUS            Status;
+
+  sc_if->msk_cdata.msk_rx_cons = 0;
+  sc_if->msk_cdata.msk_rx_prod = 0;
+  sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
+
+  rd = &sc_if->msk_rdata;
+  gBS->SetMem (rd->msk_rx_ring, MSK_RX_RING_SZ, 0);
+  for (i = prod = 0; i < MSK_RX_RING_CNT; i++) {
+    rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
+    gBS->SetMem (&rxd->rx_m, sizeof (MSK_DMA_BUF), 0);
+    rxd->rx_le = &rd->msk_rx_ring[prod];
+    MSK_INC (prod, MSK_RX_RING_CNT);
+  }
+  nbuf = MSK_RX_BUF_CNT;
+  prod = 0;
+
+  for (i = 0; i < nbuf; i++) {
+     Status = msk_newbuf (sc_if, prod);
+     if (EFI_ERROR (Status)) {
+       return Status;
+     }
+     MSK_RX_INC(prod, MSK_RX_RING_CNT);
+   }
+
+  // Update prefetch unit.
+  sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1;
+  CSR_WRITE_2 (sc_if->msk_softc, Y2_PREF_Q_ADDR (sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+msk_init_tx_ring (
+    struct msk_if_softc   *sc_if
+    )
+{
+  struct msk_ring_data  *rd;
+  struct msk_txdesc     *txd;
+  INTN                  i;
+
+  sc_if->msk_cdata.msk_tx_prod = 0;
+  sc_if->msk_cdata.msk_tx_cons = 0;
+  sc_if->msk_cdata.msk_tx_cnt = 0;
+  sc_if->msk_cdata.msk_tx_high_addr = 0;
+
+  rd = &sc_if->msk_rdata;
+  gBS->SetMem (rd->msk_tx_ring, sizeof (struct msk_tx_desc) * MSK_TX_RING_CNT, 0);
+  for (i = 0; i < MSK_TX_RING_CNT; i++) {
+    txd = &sc_if->msk_cdata.msk_txdesc[i];
+    gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0);
+    txd->tx_le = &rd->msk_tx_ring[i];
+  }
+}
+
+static
+__inline
+VOID
+msk_discard_rxbuf (
+    struct msk_if_softc   *sc_if,
+    INTN                  idx
+    )
+{
+  struct msk_rx_desc  *rx_le;
+  struct msk_rxdesc   *rxd;
+  MSK_DMA_BUF         *DmaBuffer;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: discard rxbuf\n"));
+
+#ifdef MSK_64BIT_DMA
+  rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
+  rx_le = rxd->rx_le;
+  rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
+  MSK_INC(idx, MSK_RX_RING_CNT);
+#endif
+
+  rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
+  DmaBuffer = &rxd->rx_m;
+  rx_le = rxd->rx_le;
+  rx_le->msk_control = htole32 (DmaBuffer->Length | OP_PACKET | HW_OWNER);
+}
+
+static
+EFI_STATUS
+msk_newbuf (
+    IN struct msk_if_softc    *sc_if,
+    IN INTN                   idx
+    )
+{
+  struct msk_rx_desc    *rx_le;
+  struct msk_rxdesc     *rxd;
+  UINTN                 Length;
+  VOID                  *Buffer;
+  VOID                  *Mapping;
+  EFI_PHYSICAL_ADDRESS  PhysAddr;
+  EFI_PCI_IO_PROTOCOL   *PciIo;
+  EFI_STATUS            Status;
+
+  PciIo = sc_if->msk_softc->PciIo;
+  Length = MAX_SUPPORTED_PACKET_SIZE;
+
+  rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
+
+  Status = gBS->AllocatePool (EfiBootServicesData, Length, &Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  gBS->SetMem (Buffer, Length, 0);
+
+  Status = PciIo->Map (PciIo, EfiPciIoOperationBusMasterWrite, Buffer, &Length, &PhysAddr, &Mapping);
+  if (EFI_ERROR (Status)) {
+    gBS->FreePool (Buffer);
+    return Status;
+  }
+
+#ifdef MSK_64BIT_DMA
+  rx_le = rxd->rx_le;
+  rx_le->msk_addr = htole32(MSK_ADDR_HI(PhysAddr));
+  rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
+  MSK_INC(idx, MSK_RX_RING_CNT);
+  rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
+#endif
+
+  rxd->rx_m.DmaMapping = Mapping;
+  rxd->rx_m.Buf = Buffer;
+  rxd->rx_m.Length = Length;
+  rx_le = rxd->rx_le;
+  rx_le->msk_addr = htole32 (MSK_ADDR_LO (PhysAddr));
+  rx_le->msk_control = htole32 (Length | OP_PACKET | HW_OWNER);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+mskc_probe (
+    EFI_PCI_IO_PROTOCOL *PciIo
+    )
+{
+  struct msk_product  *mp;
+  UINT16              vendor;
+  UINT16              devid;
+  UINT32              PciID;
+  INTN                i;
+  EFI_STATUS          Status;
+
+  Status = PciIo->Pci.Read (
+        PciIo,
+        EfiPciIoWidthUint32,
+        PCI_VENDOR_ID_OFFSET,
+        1,
+        &PciID
+        );
+  if (EFI_ERROR (Status)) {
+    return EFI_UNSUPPORTED;
+  }
+
+  vendor = PciID & 0xFFFF;
+  devid = PciID >> 16;
+  mp = msk_products;
+  for (i = 0; i < sizeof (msk_products)/sizeof (msk_products[0]); i++, mp++) {
+    if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
+      DEBUG ((EFI_D_NET, "Marvell Yukon: Probe found device %a\n", mp->msk_name));
+      return EFI_SUCCESS;
+    }
+  }
+  return EFI_UNSUPPORTED;
+}
+
+static
+VOID
+mskc_setup_rambuffer (
+    struct msk_softc  *sc
+    )
+{
+  INTN next;
+  INTN i;
+
+  /* Get adapter SRAM size. */
+  sc->msk_ramsize = CSR_READ_1 (sc, B2_E_0) * 4;
+  DEBUG ((DEBUG_NET, "Marvell Yukon: RAM buffer size : %dKB\n", sc->msk_ramsize));
+  if (sc->msk_ramsize == 0) {
+    return;
+  }
+
+  sc->msk_pflags |= MSK_FLAG_RAMBUF;
+  /*
+   * Give receiver 2/3 of memory and round down to the multiple
+   * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple
+   * of 1024.
+   */
+  sc->msk_rxqsize = (((sc->msk_ramsize * 1024 * 2) / 3) / 1024) * 1024;
+  sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
+  for (i = 0, next = 0; i < sc->msk_num_port; i++) {
+    sc->msk_rxqstart[i] = next;
+    sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
+    next = sc->msk_rxqend[i] + 1;
+    sc->msk_txqstart[i] = next;
+    sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
+    next = sc->msk_txqend[i] + 1;
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
+            sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], sc->msk_rxqend[i]));
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
+            sc->msk_txqsize / 1024, sc->msk_txqstart[i], sc->msk_txqend[i]));
+  }
+}
+
+static
+VOID
+msk_phy_power (
+    struct msk_softc  *sc,
+    INTN              mode
+    )
+{
+  UINT32  our;
+  UINT32  val;
+  INTN    i;
+
+  switch (mode) {
+    case MSK_PHY_POWERUP:
+      // Switch power to VCC (WA for VAUX problem)
+      CSR_WRITE_1 (sc, B0_POWER_CTRL, PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
+
+      // Disable Core Clock Division, set Clock Select to 0
+      CSR_WRITE_4 (sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
+
+      val = 0;
+      if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
+        // Enable bits are inverted
+        val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
+            Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
+            Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
+      }
+      //
+      // Enable PCI & Core Clock, enable clock gating for both Links.
+      //
+      CSR_WRITE_1 (sc, B2_Y2_CLK_GATE, val);
+
+      val = CSR_PCI_READ_4 (sc, PCI_OUR_REG_1);
+      val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
+      if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
+        if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
+          // Deassert Low Power for 1st PHY
+          val |= PCI_Y2_PHY1_COMA;
+          if (sc->msk_num_port > 1) {
+            val |= PCI_Y2_PHY2_COMA;
+          }
+        }
+      }
+      // Release PHY from PowerDown/COMA mode
+      CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_1, val);
+
+      switch (sc->msk_hw_id) {
+        case CHIP_ID_YUKON_EC_U:
+        case CHIP_ID_YUKON_EX:
+        case CHIP_ID_YUKON_FE_P:
+        case CHIP_ID_YUKON_UL_2:
+        case CHIP_ID_YUKON_OPT:
+          CSR_WRITE_2 (sc, B0_CTST, Y2_HW_WOL_OFF);
+
+          // Enable all clocks
+          CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_3, 0);
+          our = CSR_PCI_READ_4 (sc, PCI_OUR_REG_4);
+          our &= (PCI_FORCE_ASPM_REQUEST | PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | PCI_ASPM_CLKRUN_REQUEST);
+          // Set all bits to 0 except bits 15..12
+          CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_4, our);
+          our = CSR_PCI_READ_4 (sc, PCI_OUR_REG_5);
+          our &= PCI_CTL_TIM_VMAIN_AV_MSK;
+          CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_5, our);
+          CSR_PCI_WRITE_4 (sc, PCI_CFG_REG_1, 0);
+          //
+          // Disable status race, workaround for
+          // Yukon EC Ultra & Yukon EX.
+          //
+          val = CSR_READ_4 (sc, B2_GP_IO);
+          val |= GLB_GPIO_STAT_RACE_DIS;
+          CSR_WRITE_4 (sc, B2_GP_IO, val);
+          CSR_READ_4 (sc, B2_GP_IO);
+          break;
+        default:
+          break;
+      }
+      for (i = 0; i < sc->msk_num_port; i++) {
+        CSR_WRITE_2 (sc, MR_ADDR (i, GMAC_LINK_CTRL), GMLC_RST_SET);
+        CSR_WRITE_2 (sc, MR_ADDR (i, GMAC_LINK_CTRL), GMLC_RST_CLR);
+      }
+      break;
+    case MSK_PHY_POWERDOWN:
+      val = CSR_PCI_READ_4 (sc, PCI_OUR_REG_1);
+      val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
+      if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
+        val &= ~PCI_Y2_PHY1_COMA;
+        if (sc->msk_num_port > 1) {
+          val &= ~PCI_Y2_PHY2_COMA;
+        }
+      }
+      CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_1, val);
+
+      val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
+          Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
+          Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
+      if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
+        // Enable bits are inverted
+        val = 0;
+      }
+      //
+      // Disable PCI & Core Clock, disable clock gating for
+      // both Links.
+      //
+      CSR_WRITE_1 (sc, B2_Y2_CLK_GATE, val);
+      CSR_WRITE_1 (sc, B0_POWER_CTRL, PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
+      break;
+    default:
+      break;
+  }
+}
+
+static
+VOID
+clear_pci_errors (
+    struct msk_softc  *sc
+    )
+{
+  EFI_STATUS  Status;
+  UINT16      val;
+  EFI_PCI_IO_PROTOCOL  *PciIo;
+
+  PciIo = sc->PciIo;
+
+  // Clear all error bits in the PCI status register.
+  Status = PciIo->Pci.Read (
+        PciIo,
+        EfiPciIoWidthUint16,
+        PCI_PRIMARY_STATUS_OFFSET,
+        1,
+        &val
+        );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: Warning - Reading PCI Status failed: %r", Status));
+  }
+  CSR_WRITE_1 (sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
+  val |= PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
+      PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT;
+  Status = PciIo->Pci.Write (
+        PciIo,
+        EfiPciIoWidthUint16,
+        PCI_PRIMARY_STATUS_OFFSET,
+        1,
+        &val
+        );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: Warning - Writing PCI Status failed: %r", Status));
+  }
+  CSR_WRITE_2 (sc, B0_CTST, CS_MRST_CLR);
+}
+
+static
+VOID
+mskc_reset (
+    struct msk_softc  *sc
+    )
+{
+  EFI_STATUS            Status;
+  EFI_PHYSICAL_ADDRESS  PhysAddr;
+  UINT16                status;
+  UINT32                val;
+  INTN                  i;
+  EFI_PCI_IO_PROTOCOL   *PciIo;
+
+  PciIo = sc->PciIo;
+
+  CSR_WRITE_2 (sc, B0_CTST, CS_RST_CLR);
+
+  // Disable ASF
+  if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
+    status = CSR_READ_2 (sc, B28_Y2_ASF_HCU_CCSR);
+    // Clear AHB bridge & microcontroller reset
+    status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | Y2_ASF_HCU_CCSR_CPU_RST_MODE);
+    // Clear ASF microcontroller state
+    status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
+    CSR_WRITE_2 (sc, B28_Y2_ASF_HCU_CCSR, status);
+  } else {
+    CSR_WRITE_1 (sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
+  }
+  CSR_WRITE_2 (sc, B0_CTST, Y2_ASF_DISABLE);
+
+  //
+  // Since we disabled ASF, S/W reset is required for Power Management.
+  //
+  CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);
+  CSR_WRITE_2 (sc, B0_CTST, CS_RST_CLR);
+
+  clear_pci_errors (sc);
+  switch (sc->msk_bustype) {
+    case MSK_PEX_BUS:
+      // Clear all PEX errors
+      CSR_PCI_WRITE_4 (sc, PEX_UNC_ERR_STAT, 0xffffffff);
+      val = CSR_PCI_READ_4 (sc, PEX_UNC_ERR_STAT);
+      if ((val & PEX_RX_OV) != 0) {
+        sc->msk_intrmask &= ~Y2_IS_HW_ERR;
+        sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
+      }
+      break;
+    case MSK_PCI_BUS:
+    case MSK_PCIX_BUS:
+      // Set Cache Line Size to 2 (8bytes) if configured to 0
+      Status = PciIo->Pci.Read (
+            PciIo,
+            EfiPciIoWidthUint8,
+            PCI_CACHELINE_SIZE_OFFSET,
+            1,
+            &val
+            );
+      if (EFI_ERROR (Status)) {
+        DEBUG ((EFI_D_ERROR, "Marvell Yukon: Warning - Reading PCI cache line size failed: %r", Status));
+      }
+      if (val == 0) {
+        val = 2;
+        Status = PciIo->Pci.Write (
+              PciIo,
+              EfiPciIoWidthUint8,
+              PCI_CACHELINE_SIZE_OFFSET,
+              1,
+              &val
+              );
+        if (EFI_ERROR (Status)) {
+          DEBUG ((EFI_D_ERROR, "Marvell Yukon: Warning - Writing PCI cache line size failed: %r", Status));
+        }
+      }
+      if (sc->msk_bustype == MSK_PCIX_BUS) {
+        Status = PciIo->Pci.Read (
+              PciIo,
+              EfiPciIoWidthUint32,
+              PCI_OUR_REG_1,
+              1,
+              &val
+              );
+        if (EFI_ERROR (Status)) {
+          DEBUG ((EFI_D_ERROR, "Marvell Yukon: Warning - Reading Our Reg 1 failed: %r", Status));
+        }
+        val |= PCI_CLS_OPT;
+        Status = PciIo->Pci.Write (
+              PciIo,
+              EfiPciIoWidthUint32,
+              PCI_OUR_REG_1,
+              1,
+              &val
+              );
+        if (EFI_ERROR (Status)) {
+          DEBUG ((EFI_D_ERROR, "Marvell Yukon: Warning - Writing Our Reg 1 failed: %r", Status));
+        }
+      }
+      break;
+  }
+
+  // Set PHY power state
+  msk_phy_power (sc, MSK_PHY_POWERUP);
+
+  // Reset GPHY/GMAC Control
+  for (i = 0; i < sc->msk_num_port; i++) {
+    // GPHY Control reset
+    CSR_WRITE_4 (sc, MR_ADDR (i, GPHY_CTRL), GPC_RST_SET);
+    CSR_WRITE_4 (sc, MR_ADDR (i, GPHY_CTRL), GPC_RST_CLR);
+    if (sc->msk_hw_id == CHIP_ID_YUKON_UL_2) {
+      // Magic value observed under Linux.
+      CSR_WRITE_4 (sc, MR_ADDR (i, GPHY_CTRL), 0x00105226);
+    }
+    // GMAC Control reset
+    CSR_WRITE_4 (sc, MR_ADDR (i, GMAC_CTRL), GMC_RST_SET);
+    CSR_WRITE_4 (sc, MR_ADDR (i, GMAC_CTRL), GMC_RST_CLR);
+    CSR_WRITE_4 (sc, MR_ADDR (i, GMAC_CTRL), GMC_F_LOOPB_OFF);
+    if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
+      CSR_WRITE_4 (sc, MR_ADDR (i, GMAC_CTRL), GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | GMC_BYP_RETR_ON);
+    }
+  }
+  if ((sc->msk_hw_id == CHIP_ID_YUKON_OPT) && (sc->msk_hw_rev == 0)) {
+    // Disable PCIe PHY powerdown (reg 0x80, bit7)
+    CSR_WRITE_4 (sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
+  }
+  CSR_WRITE_1 (sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
+
+  // LED On
+  CSR_WRITE_2 (sc, B0_CTST, Y2_LED_STAT_ON);
+
+  // Enable plug in go
+  CSR_WRITE_2 (sc, B0_CTST, Y_ULTRA_2_PLUG_IN_GO_EN);
+
+  // Clear TWSI IRQ
+  CSR_WRITE_4 (sc, B2_I2C_IRQ, I2C_CLR_IRQ);
+
+  // Turn off hardware timer
+  CSR_WRITE_1 (sc, B2_TI_CTRL, TIM_STOP);
+  CSR_WRITE_1 (sc, B2_TI_CTRL, TIM_CLR_IRQ);
+
+  // Turn off descriptor polling
+  CSR_WRITE_1 (sc, B28_DPT_CTRL, DPT_STOP);
+
+  // Turn off time stamps
+  CSR_WRITE_1 (sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
+  CSR_WRITE_1 (sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
+
+  // Configure timeout values
+  for (i = 0; i < sc->msk_num_port; i++) {
+    CSR_WRITE_2 (sc, SELECT_RAM_BUFFER (i, B3_RI_CTRL),    RI_RST_SET);
+    CSR_WRITE_2 (sc, SELECT_RAM_BUFFER (i, B3_RI_CTRL),    RI_RST_CLR);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_R1),  MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XA1), MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XS1), MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_R1),  MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XA1), MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XS1), MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_R2),  MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XA2), MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XS2), MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_R2),  MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XA2), MSK_RI_TO_53);
+    CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XS2), MSK_RI_TO_53);
+  }
+
+  // Disable all interrupts
+  CSR_WRITE_4 (sc, B0_HWE_IMSK, 0);
+  CSR_READ_4 (sc, B0_HWE_IMSK);
+  CSR_WRITE_4 (sc, B0_IMSK, 0);
+  CSR_READ_4 (sc, B0_IMSK);
+
+  // Clear status list
+  gBS->SetMem (sc->msk_stat_ring, sizeof (struct msk_stat_desc) * MSK_STAT_RING_CNT, 0);
+  sc->msk_stat_cons = 0;
+  CSR_WRITE_4 (sc, STAT_CTRL, SC_STAT_RST_SET);
+  CSR_WRITE_4 (sc, STAT_CTRL, SC_STAT_RST_CLR);
+
+  // Set the status list base address
+  PhysAddr = sc->msk_stat_ring_paddr;
+  CSR_WRITE_4 (sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO (PhysAddr));
+  CSR_WRITE_4 (sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI (PhysAddr));
+
+  // Set the status list last index
+  CSR_WRITE_2 (sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
+  if ((sc->msk_hw_id == CHIP_ID_YUKON_EC) && (sc->msk_hw_rev == CHIP_REV_YU_EC_A1)) {
+    // WA for dev. #4.3
+    CSR_WRITE_2 (sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
+    // WA for dev. #4.18
+    CSR_WRITE_1 (sc, STAT_FIFO_WM, 0x21);
+    CSR_WRITE_1 (sc, STAT_FIFO_ISR_WM, 0x07);
+  } else {
+    CSR_WRITE_2 (sc, STAT_TX_IDX_TH, 0x0a);
+    CSR_WRITE_1 (sc, STAT_FIFO_WM, 0x10);
+    if ((sc->msk_hw_id == CHIP_ID_YUKON_XL) && (sc->msk_hw_rev == CHIP_REV_YU_XL_A0)) {
+      CSR_WRITE_1 (sc, STAT_FIFO_ISR_WM, 0x04);
+    } else {
+      CSR_WRITE_1 (sc, STAT_FIFO_ISR_WM, 0x10);
+    }
+    CSR_WRITE_4 (sc, STAT_ISR_TIMER_INI, 0x0190);
+  }
+  //
+  // Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
+  //
+  CSR_WRITE_4 (sc, STAT_TX_TIMER_INI, MSK_USECS (sc, 1000));
+
+  // Enable status unit
+  CSR_WRITE_4 (sc, STAT_CTRL, SC_STAT_OP_ON);
+
+  CSR_WRITE_1 (sc, STAT_TX_TIMER_CTRL, TIM_START);
+  CSR_WRITE_1 (sc, STAT_LEV_TIMER_CTRL, TIM_START);
+  CSR_WRITE_1 (sc, STAT_ISR_TIMER_CTRL, TIM_START);
+}
+
+EFI_STATUS
+mskc_attach_if (
+    struct msk_if_softc   *sc_if,
+    UINTN                 Port
+    )
+{
+  INTN                  i;
+  EFI_STATUS            Status;
+
+  sc_if->msk_md.port = Port;
+  sc_if->msk_flags = sc_if->msk_softc->msk_pflags;
+
+  // Setup Tx/Rx queue register offsets
+  if (Port == MSK_PORT_A) {
+    sc_if->msk_txq = Q_XA1;
+    sc_if->msk_txsq = Q_XS1;
+    sc_if->msk_rxq = Q_R1;
+  } else {
+    sc_if->msk_txq = Q_XA2;
+    sc_if->msk_txsq = Q_XS2;
+    sc_if->msk_rxq = Q_R2;
+  }
+
+  Status = msk_txrx_dma_alloc (sc_if);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  /*
+   * Get station address for this interface. Note that
+   * dual port cards actually come with three station
+   * addresses: one for each port, plus an extra. The
+   * extra one is used by the SysKonnect driver software
+   * as a 'virtual' station address for when both ports
+   * are operating in failover mode. Currently we don't
+   * use this extra address.
+   */
+  for (i = 0; i < NET_ETHER_ADDR_LEN; i++) {
+    sc_if->MacAddress.Addr[i] = CSR_READ_1 (sc_if->msk_softc, B2_MAC_1 + (Port * 8) + i);
+  }
+
+  DEBUG ((EFI_D_NET,"Marvell Yukon: Mac Address %02x:%02x:%02x:%02x:%02x:%02x\n",
+          sc_if->MacAddress.Addr[0], sc_if->MacAddress.Addr[1], sc_if->MacAddress.Addr[2],
+      sc_if->MacAddress.Addr[3], sc_if->MacAddress.Addr[4], sc_if->MacAddress.Addr[5]));
+
+  Status = e1000_probe_and_attach (&sc_if->mii_d, &sc_if->msk_md, sc_if, &sc_if->phy_softc);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  InitializeListHead (&sc_if->TransmitQueueHead);
+  InitializeListHead (&sc_if->TransmitFreeQueueHead);
+  InitializeListHead (&sc_if->ReceiveQueueHead);
+  sc_if->active = TRUE;
+
+  return (Status);
+}
+
+/*
+ * Attach the interface. Allocate softc structures, do ifmedia
+ * setup and ethernet/BPF attach.
+ */
+EFI_STATUS
+mskc_attach (
+    IN  EFI_PCI_IO_PROTOCOL   *PciIo,
+    OUT struct msk_softc      **ScData
+    )
+{
+  struct msk_mii_data   *mmd;
+  UINT64                Supports;
+  UINT8                 *PciBarResources;
+  EFI_STATUS            Status;
+  struct msk_if_softc   *ScIf;
+  struct msk_softc      *sc;
+
+  Status = gBS->AllocatePool (EfiBootServicesData,
+                              sizeof (struct msk_softc),
+                              (VOID**) &sc);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Save original PCI attributes
+  //
+  gBS->SetMem (sc, sizeof (struct msk_softc), 0);
+  sc->PciIo = PciIo;
+  Status = PciIo->Attributes (
+        PciIo,
+        EfiPciIoAttributeOperationGet,
+        0,
+        &sc->OriginalPciAttributes
+        );
+  if (EFI_ERROR (Status)) {
+    gBS->FreePool (sc);
+    return Status;
+  }
+
+  Status = PciIo->Attributes (
+        PciIo,
+        EfiPciIoAttributeOperationSupported,
+        0,
+        &Supports
+        );
+  if (!EFI_ERROR (Status)) {
+    Supports &= EFI_PCI_DEVICE_ENABLE;
+    Status = PciIo->Attributes (
+          PciIo,
+          EfiPciIoAttributeOperationEnable,
+          Supports | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
+          NULL
+          );
+  }
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: Failed to enable NIC controller\n"));
+    goto RESTORE_PCI_ATTRIBS;
+  }
+
+  Status = PciIo->GetBarAttributes (PciIo, 0, &Supports, (VOID**)&PciBarResources);
+  if (!EFI_ERROR (Status) && (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR)) {
+    if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+      if (!(((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->SpecificFlag & ACPI_SPECFLAG_PREFETCHABLE)) {
+        sc->RegBase = ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->AddrRangeMin;
+        // Should assert that Bar is 32 bits wide
+        DEBUG ((DEBUG_NET, "Marvell Yukon: GlobalRegistersBase = 0x%x\n", sc->RegBase));
+      } else {
+        Status = EFI_NOT_FOUND;
+      }
+    } else {
+      Status = EFI_NOT_FOUND;
+    }
+  }
+  if (EFI_ERROR (Status)) {
+    goto RESTORE_PCI_ATTRIBS;
+  }
+
+  // Clear Software Reset
+  CSR_WRITE_2 (sc, B0_CTST, CS_RST_CLR);
+
+  // Get Hardware ID & Revision
+  sc->msk_hw_id = CSR_READ_1 (sc, B2_CHIP_ID);
+  sc->msk_hw_rev = (CSR_READ_1 (sc, B2_MAC_CFG) >> 4) & 0x0f;
+
+  // Bail out if chip is not recognized
+  if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
+      sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
+      sc->msk_hw_id == CHIP_ID_YUKON_SUPR ||
+      sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
+    DEBUG ((DEBUG_NET, "Marvell Yukon: unknown device: id=0x%02x, rev=0x%02x\n", sc->msk_hw_id, sc->msk_hw_rev));
+    Status = EFI_DEVICE_ERROR;
+    goto RESTORE_PCI_ATTRIBS;
+  }
+  DEBUG ((EFI_D_NET, "Marvell Yukon: Marvell Technology Group Ltd. %a Id:0x%02x Rev:0x%02x\n",
+          model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, sc->msk_hw_rev));
+
+  sc->msk_process_limit = MSK_PROC_DEFAULT;
+  sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
+
+  // Check if MAC address is valid
+  if ((CSR_READ_4 (sc, B2_MAC_1) == 0) && (CSR_READ_4 (sc, B2_MAC_1+4) == 0)) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: MAC address is invalid (00:00:00:00:00:00)\n"));
+  }
+
+  // Soft reset
+  CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);
+  CSR_WRITE_2 (sc, B0_CTST, CS_RST_CLR);
+  sc->msk_pmd = CSR_READ_1 (sc, B2_PMD_TYP);
+
+  // Check number of MACs
+  sc->msk_num_port = 1;
+  if ((CSR_READ_1 (sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
+    if (!(CSR_READ_1 (sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) {
+      sc->msk_num_port++;
+    }
+  }
+
+  /* Check bus type. */
+  sc->msk_bustype = MSK_PEX_BUS; /* Only support PCI Express */
+  sc->msk_expcap = 1;
+
+  switch (sc->msk_hw_id) {
+    case CHIP_ID_YUKON_EC:
+      sc->msk_clock = 125;  /* 125 MHz */
+      sc->msk_pflags |= MSK_FLAG_JUMBO;
+      break;
+    case CHIP_ID_YUKON_EC_U:
+      sc->msk_clock = 125;  /* 125 MHz */
+      sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
+      break;
+    case CHIP_ID_YUKON_EX:
+      sc->msk_clock = 125;  /* 125 MHz */
+      sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | MSK_FLAG_AUTOTX_CSUM;
+      /*
+     * Yukon Extreme seems to have silicon bug for
+     * automatic Tx checksum calculation capability.
+     */
+      if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) {
+        sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
+      }
+      /*
+     * Yukon Extreme A0 could not use store-and-forward
+     * for jumbo frames, so disable Tx checksum
+     * offloading for jumbo frames.
+     */
+      if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) {
+        sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
+      }
+      break;
+    case CHIP_ID_YUKON_FE:
+      sc->msk_clock = 100;  /* 100 MHz */
+      sc->msk_pflags |= MSK_FLAG_FASTETHER;
+      break;
+    case CHIP_ID_YUKON_FE_P:
+      sc->msk_clock = 50;  /* 50 MHz */
+      sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | MSK_FLAG_AUTOTX_CSUM;
+      if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
+        /*
+       * XXX
+       * FE+ A0 has status LE writeback bug so msk (4)
+       * does not rely on status word of received frame
+       * in msk_rxeof () which in turn disables all
+       * hardware assistance bits reported by the status
+       * word as well as validity of the recevied frame.
+       * Just pass received frames to upper stack with
+       * minimal test and let upper stack handle them.
+       */
+        sc->msk_pflags |= MSK_FLAG_NOHWVLAN | MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;
+      }
+      break;
+    case CHIP_ID_YUKON_XL:
+      sc->msk_clock = 156;  /* 156 MHz */
+      sc->msk_pflags |= MSK_FLAG_JUMBO;
+      break;
+    case CHIP_ID_YUKON_UL_2:
+      sc->msk_clock = 125;  /* 125 MHz */
+      sc->msk_pflags |= MSK_FLAG_JUMBO;
+      break;
+    case CHIP_ID_YUKON_OPT:
+      sc->msk_clock = 125;  /* 125 MHz */
+      sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
+      break;
+    default:
+      sc->msk_clock = 156;  /* 156 MHz */
+      break;
+  }
+
+  Status = msk_status_dma_alloc (sc);
+  if (EFI_ERROR (Status)) {
+    goto fail;
+  }
+
+  // Set base interrupt mask
+  sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
+  sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
+
+  // Reset the adapter
+  mskc_reset (sc);
+
+  mskc_setup_rambuffer (sc);
+
+  Status = gBS->AllocatePool (EfiBootServicesData,
+                              sizeof (struct msk_if_softc),
+                              (VOID**) &ScIf);
+  if (EFI_ERROR (Status)) {
+    goto fail;
+  }
+  gBS->SetMem (ScIf, sizeof (struct msk_if_softc), 0);
+  ScIf->msk_softc = sc;
+  sc->msk_if[MSK_PORT_A] = ScIf;
+  Status = mskc_attach_if (sc->msk_if[MSK_PORT_A], MSK_PORT_A);
+  if (EFI_ERROR (Status)) {
+    goto fail;
+  }
+
+  mmd = &ScIf->msk_md;
+  mmd->port = MSK_PORT_A;
+  mmd->pmd = sc->msk_pmd;
+  if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') {
+    mmd->mii_flags |= MIIF_HAVEFIBER;
+  }
+
+  if (sc->msk_num_port > 1) {
+    Status = gBS->AllocatePool (EfiBootServicesData,
+                                sizeof (struct msk_if_softc),
+                                (VOID**) &ScIf);
+    if (EFI_ERROR (Status)) {
+      goto fail;
+    }
+    gBS->SetMem (ScIf, sizeof (struct msk_if_softc), 0);
+    ScIf->msk_softc = sc;
+    sc->msk_if[MSK_PORT_B] = ScIf;
+    Status = mskc_attach_if (sc->msk_if[MSK_PORT_B], MSK_PORT_B);
+    if (EFI_ERROR (Status)) {
+      goto fail;
+    }
+
+    mmd = &ScIf->msk_md;
+    mmd->port = MSK_PORT_B;
+    mmd->pmd = sc->msk_pmd;
+    if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') {
+      mmd->mii_flags |= MIIF_HAVEFIBER;
+    }
+  }
+
+  // Return new msk_softc structure
+  *ScData = sc;
+
+  // Create timer for tick
+  Status = gBS->CreateEvent (
+        EVT_NOTIFY_SIGNAL | EVT_TIMER,
+        TPL_CALLBACK,
+        mskc_tick,
+        (VOID *)sc,
+        &sc->Timer
+        );
+  if (EFI_ERROR (Status)) {
+    goto fail;
+  }
+
+  Status = gBS->SetTimer (sc->Timer, TimerPeriodic, TICKS_PER_SECOND);
+  if (EFI_ERROR (Status)) {
+    goto fail;
+  }
+
+fail:
+  if (EFI_ERROR (Status)) {
+    mskc_detach (sc);
+  }
+
+  return (Status);
+
+RESTORE_PCI_ATTRIBS:
+  //
+  // Restore original PCI attributes
+  //
+  PciIo->Attributes (
+        PciIo,
+        EfiPciIoAttributeOperationSet,
+        sc->OriginalPciAttributes,
+        NULL
+        );
+  gBS->FreePool (sc);
+  return Status;
+}
+
+/*
+ * Shutdown hardware and free up resources. This can be called any
+ * time after the mutex has been initialized. It is called in both
+ * the error case in attach and the normal detach case so it needs
+ * to be careful about only freeing resources that have actually been
+ * allocated.
+ */
+VOID
+mskc_detach_if (
+    struct msk_if_softc  *sc_if
+    )
+{
+  if (sc_if->active) {
+    mskc_stop_if (sc_if);
+    msk_txrx_dma_free (sc_if);
+    e1000phy_detach (sc_if->phy_softc);
+    sc_if->phy_softc = NULL;
+    sc_if->active = FALSE;
+  }
+}
+
+VOID
+mskc_detach (
+    struct msk_softc  *sc
+    )
+{
+  EFI_TPL OldTpl;
+  EFI_PCI_IO_PROTOCOL *PciIo;
+
+  if (sc == NULL) {
+    return;
+  }
+
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  PciIo = sc->PciIo;
+
+  if (sc->msk_if[MSK_PORT_A] != NULL) {
+    mskc_detach_if (sc->msk_if[MSK_PORT_A]);
+    gBS->FreePool (sc->msk_if[MSK_PORT_A]);
+    sc->msk_if[MSK_PORT_A] = NULL;
+  }
+  if (sc->msk_if[MSK_PORT_B] != NULL) {
+    mskc_detach_if (sc->msk_if[MSK_PORT_B]);
+    gBS->FreePool (sc->msk_if[MSK_PORT_B]);
+    sc->msk_if[MSK_PORT_B] = NULL;
+  }
+
+  /* Disable all interrupts. */
+  CSR_WRITE_4 (sc, B0_IMSK, 0);
+  CSR_READ_4 (sc, B0_IMSK);
+  CSR_WRITE_4 (sc, B0_HWE_IMSK, 0);
+  CSR_READ_4 (sc, B0_HWE_IMSK);
+
+  // LED Off.
+  CSR_WRITE_2 (sc, B0_CTST, Y2_LED_STAT_OFF);
+
+  // Put hardware reset.
+  CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);
+
+  msk_status_dma_free (sc);
+
+  if (sc->Timer != NULL) {
+    gBS->SetTimer (sc->Timer, TimerCancel, 0);
+    gBS->CloseEvent (sc->Timer);
+
+    sc->Timer = NULL;
+  }
+  //
+  // Restore original PCI attributes
+  //
+  PciIo->Attributes (
+        PciIo,
+        EfiPciIoAttributeOperationSet,
+        sc->OriginalPciAttributes,
+        NULL
+        );
+
+  gBS->RestoreTPL (OldTpl);
+}
+
+/* Create status DMA region. */
+static
+EFI_STATUS
+msk_status_dma_alloc (
+    struct msk_softc  *sc
+    )
+{
+  EFI_STATUS  Status;
+  UINTN       Length;
+  EFI_PCI_IO_PROTOCOL *PciIo;
+
+  PciIo = sc->PciIo;
+
+  Status = PciIo->AllocateBuffer (PciIo, AllocateAnyPages, EfiBootServicesData,
+                                   EFI_SIZE_TO_PAGES (MSK_STAT_RING_SZ), (VOID**)&sc->msk_stat_ring, 0);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: failed to allocate DMA'able memory for status ring\n"));
+    return Status;
+  }
+  ASSERT (sc->msk_stat_ring != NULL);
+
+  Length = MSK_STAT_RING_SZ;
+  Status = PciIo->Map (PciIo, EfiPciIoOperationBusMasterCommonBuffer, sc->msk_stat_ring,
+                        &Length, &sc->msk_stat_ring_paddr, &sc->msk_stat_map);
+  ASSERT (Length == MSK_STAT_RING_SZ);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: failed to map DMA'able memory for status ring\n"));
+  }
+
+  return Status;
+}
+
+static
+VOID
+msk_status_dma_free (
+    struct msk_softc  *sc
+    )
+{
+  EFI_PCI_IO_PROTOCOL *PciIo;
+
+  PciIo = sc->PciIo;
+
+  if (sc->msk_stat_map) {
+    PciIo->Unmap (PciIo, sc->msk_stat_map);
+    if (sc->msk_stat_ring) {
+      PciIo->FreeBuffer (PciIo, EFI_SIZE_TO_PAGES (MSK_STAT_RING_SZ), sc->msk_stat_ring);
+      sc->msk_stat_ring = NULL;
+    }
+    sc->msk_stat_map = NULL;
+  }
+}
+
+static
+EFI_STATUS
+msk_txrx_dma_alloc (
+    struct msk_if_softc   *sc_if
+    )
+{
+  struct msk_txdesc   *txd;
+  struct msk_rxdesc   *rxd;
+  INTN                i;
+  UINTN               Length;
+  EFI_STATUS          Status;
+  EFI_PCI_IO_PROTOCOL *PciIo;
+
+  PciIo = sc_if->msk_softc->PciIo;
+
+  Status = PciIo->AllocateBuffer (PciIo, AllocateAnyPages, EfiBootServicesData,
+                                   EFI_SIZE_TO_PAGES (MSK_TX_RING_SZ), (VOID**)&sc_if->msk_rdata.msk_tx_ring, 0);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: failed to allocate DMA'able memory for Tx ring\n"));
+    goto fail;
+  }
+  ASSERT (sc_if->msk_rdata.msk_tx_ring != NULL);
+
+  Length = MSK_TX_RING_SZ;
+  Status = PciIo->Map (PciIo, EfiPciIoOperationBusMasterCommonBuffer, sc_if->msk_rdata.msk_tx_ring,
+                        &Length, &sc_if->msk_rdata.msk_tx_ring_paddr, &sc_if->msk_cdata.msk_tx_ring_map);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: failed to map DMA'able memory for Tx ring\n"));
+    goto fail;
+  }
+  ASSERT (Length == MSK_TX_RING_SZ);
+
+  Status = PciIo->AllocateBuffer (PciIo, AllocateAnyPages, EfiBootServicesData,
+                                   EFI_SIZE_TO_PAGES (MSK_RX_RING_SZ), (VOID**)&sc_if->msk_rdata.msk_rx_ring, 0);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: failed to allocate DMA'able memory for Rx ring\n"));
+    goto fail;
+  }
+  ASSERT (sc_if->msk_rdata.msk_rx_ring != NULL);
+
+  Length = MSK_RX_RING_SZ;
+  Status = PciIo->Map (PciIo, EfiPciIoOperationBusMasterCommonBuffer, sc_if->msk_rdata.msk_rx_ring,
+                        &Length, &sc_if->msk_rdata.msk_rx_ring_paddr, &sc_if->msk_cdata.msk_rx_ring_map);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: failed to map DMA'able memory for Rx ring\n"));
+    goto fail;
+  }
+  ASSERT (Length == MSK_RX_RING_SZ);
+
+  // Create DMA maps for Tx buffers.
+  for (i = 0; i < MSK_TX_RING_CNT; i++) {
+    txd = &sc_if->msk_cdata.msk_txdesc[i];
+    gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0);
+  }
+  // Create DMA maps for Rx buffers.
+  for (i = 0; i < MSK_RX_RING_CNT; i++) {
+    rxd = &sc_if->msk_cdata.msk_rxdesc[i];
+    gBS->SetMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF), 0);
+  }
+
+fail:
+  return (Status);
+}
+
+static
+VOID
+msk_txrx_dma_free (
+    struct msk_if_softc *sc_if
+    )
+{
+  struct msk_txdesc   *txd;
+  struct msk_rxdesc   *rxd;
+  INTN                i;
+  EFI_PCI_IO_PROTOCOL *PciIo;
+
+  PciIo = sc_if->msk_softc->PciIo;
+
+  // Tx ring
+  if (sc_if->msk_cdata.msk_tx_ring_map) {
+    PciIo->Unmap (PciIo, sc_if->msk_cdata.msk_tx_ring_map);
+    if (sc_if->msk_rdata.msk_tx_ring) {
+      PciIo->FreeBuffer (PciIo, EFI_SIZE_TO_PAGES (MSK_TX_RING_SZ), sc_if->msk_rdata.msk_tx_ring);
+      sc_if->msk_rdata.msk_tx_ring = NULL;
+    }
+    sc_if->msk_cdata.msk_tx_ring_map = NULL;
+  }
+
+  // Rx ring
+  if (sc_if->msk_cdata.msk_rx_ring_map) {
+    PciIo->Unmap (PciIo, sc_if->msk_cdata.msk_rx_ring_map);
+    if (sc_if->msk_rdata.msk_rx_ring) {
+      PciIo->FreeBuffer (PciIo, EFI_SIZE_TO_PAGES (MSK_RX_RING_SZ), sc_if->msk_rdata.msk_rx_ring);
+      sc_if->msk_rdata.msk_rx_ring = NULL;
+    }
+    sc_if->msk_cdata.msk_rx_ring_map = NULL;
+  }
+
+  // Tx buffers
+  for (i = 0; i < MSK_TX_RING_CNT; i++) {
+    txd = &sc_if->msk_cdata.msk_txdesc[i];
+    if (txd->tx_m.DmaMapping) {
+      PciIo->Unmap (PciIo, txd->tx_m.DmaMapping);
+      gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0);
+      // We don't own the transmit buffers so don't free them
+    }
+  }
+  // Rx buffers
+  for (i = 0; i < MSK_RX_RING_CNT; i++) {
+    rxd = &sc_if->msk_cdata.msk_rxdesc[i];
+    if (rxd->rx_m.DmaMapping) {
+      PciIo->Unmap (PciIo, rxd->rx_m.DmaMapping);
+      // Free Rx buffers as we own these
+      if(rxd->rx_m.Buf != NULL) {
+        gBS->FreePool (rxd->rx_m.Buf);
+        rxd->rx_m.Buf = NULL;
+      }
+      gBS->SetMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF), 0);
+    }
+  }
+}
+
+static
+EFI_STATUS
+msk_encap (
+    struct msk_if_softc   *sc_if,
+    MSK_SYSTEM_BUF        *m_head
+    )
+{
+  struct msk_txdesc     *txd;
+  struct msk_txdesc     *txd_last;
+  struct msk_tx_desc    *tx_le;
+  VOID                  *Mapping;
+  EFI_PHYSICAL_ADDRESS  BusPhysAddr;
+  UINTN                 BusLength;
+  UINT32                control;
+  UINT32                prod;
+  UINT32                si;
+  EFI_STATUS            Status;
+  EFI_PCI_IO_PROTOCOL   *PciIo;
+
+  PciIo = sc_if->msk_softc->PciIo;
+  prod = sc_if->msk_cdata.msk_tx_prod;
+  txd = &sc_if->msk_cdata.msk_txdesc[prod];
+  txd_last = txd;
+  BusLength = m_head->Length;
+  Status = PciIo->Map (PciIo, EfiPciIoOperationBusMasterRead, m_head->Buf,
+                        &BusLength, &BusPhysAddr, &txd->tx_m.DmaMapping);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: failed to map DMA'able memory for Tx buffer\n"));
+    return Status;
+  }
+  ASSERT (BusLength == m_head->Length);
+
+  control = 0;
+
+#ifdef MSK_64BIT_DMA
+  if (MSK_ADDR_HI(BusPhysAddr) !=
+    sc_if->msk_cdata.msk_tx_high_addr) {
+      sc_if->msk_cdata.msk_tx_high_addr =
+          MSK_ADDR_HI(BusPhysAddr);
+      tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
+      tx_le->msk_addr = htole32(MSK_ADDR_HI(BusPhysAddr));
+      tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
+      sc_if->msk_cdata.msk_tx_cnt++;
+      MSK_INC(prod, MSK_TX_RING_CNT);
+  }
+#endif
+
+  si = prod;
+  tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
+  tx_le->msk_addr = htole32 (MSK_ADDR_LO (BusPhysAddr));
+  tx_le->msk_control = htole32 (BusLength | control | OP_PACKET);
+  sc_if->msk_cdata.msk_tx_cnt++;
+  MSK_INC (prod, MSK_TX_RING_CNT);
+
+  // Update producer index
+  sc_if->msk_cdata.msk_tx_prod = prod;
+
+  // Set EOP on the last descriptor
+  prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
+  tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
+  tx_le->msk_control |= htole32 (EOP);
+
+  // Turn the first descriptor ownership to hardware
+  tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
+  tx_le->msk_control |= htole32 (HW_OWNER);
+
+  txd = &sc_if->msk_cdata.msk_txdesc[prod];
+  Mapping = txd_last->tx_m.DmaMapping;
+  txd_last->tx_m.DmaMapping = txd->tx_m.DmaMapping;
+  txd->tx_m.DmaMapping = Mapping;
+  txd->tx_m.Buf = m_head->Buf;
+  txd->tx_m.Length = m_head->Length;
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+mskc_transmit (
+    struct msk_if_softc  *sc_if,
+    UINTN   BufferSize,
+    VOID    *Buffer
+    )
+{
+  MSK_LINKED_SYSTEM_BUF   *LinkedSystemBuf;
+  EFI_STATUS               Status;
+
+  Status = gBS->AllocatePool (EfiBootServicesData,
+                              sizeof (MSK_LINKED_SYSTEM_BUF),
+                              (VOID**) &LinkedSystemBuf);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  gBS->SetMem (LinkedSystemBuf, sizeof (MSK_LINKED_SYSTEM_BUF), 0);
+  LinkedSystemBuf->Signature = TX_MBUF_SIGNATURE;
+  //
+  // Add the passed Buffer to the transmit queue. Don't copy.
+  //
+  LinkedSystemBuf->SystemBuf.Buf = Buffer;
+  LinkedSystemBuf->SystemBuf.Length = BufferSize;
+  InsertTailList (&sc_if->TransmitQueueHead, &LinkedSystemBuf->Link);
+  msk_start (sc_if);
+  return EFI_SUCCESS;
+}
+
+void
+mskc_getstatus (
+    struct msk_if_softc  *sc_if,
+    OUT UINT32                     *InterruptStatus, OPTIONAL
+    OUT VOID                       **TxBuf           OPTIONAL
+    )
+{
+  MSK_LINKED_SYSTEM_BUF *m_head;
+
+  // Interrupt status is not read from the device when InterruptStatus is NULL
+  if (InterruptStatus != NULL) {
+    // Check the interrupt lines
+    msk_intr (sc_if->msk_softc);
+  }
+
+  // The transmit buffer status is not read when TxBuf is NULL
+  if (TxBuf != NULL) {
+    *((UINT8 **) TxBuf) = (UINT8 *) 0;
+    if (!IsListEmpty (&sc_if->TransmitFreeQueueHead))
+    {
+      m_head = CR (GetFirstNode (&sc_if->TransmitFreeQueueHead), MSK_LINKED_SYSTEM_BUF, Link, TX_MBUF_SIGNATURE);
+      if(m_head != NULL) {
+        *TxBuf = m_head->SystemBuf.Buf;
+        RemoveEntryList (&m_head->Link);
+        gBS->FreePool (m_head);
+      }
+    }
+  }
+}
+
+static
+VOID
+msk_start (
+    struct msk_if_softc  *sc_if
+    )
+{
+  EFI_STATUS            Status;
+  MSK_LINKED_SYSTEM_BUF *m_head;
+  INTN                  enq;
+
+  for (enq = 0; !IsListEmpty (&sc_if->TransmitQueueHead) &&
+       sc_if->msk_cdata.msk_tx_cnt < (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); )
+  {
+
+    m_head = CR (GetFirstNode (&sc_if->TransmitQueueHead), MSK_LINKED_SYSTEM_BUF, Link, TX_MBUF_SIGNATURE);
+    if (m_head == NULL) {
+      break;
+    }
+    //
+    // Pack the data into the transmit ring. If we
+    // don't have room, set the OACTIVE flag and wait
+    // for the NIC to drain the ring.
+    //
+    Status = msk_encap (sc_if, &m_head->SystemBuf);
+    if (EFI_ERROR (Status)) {
+      break;
+    }
+
+    RemoveEntryList (&m_head->Link);
+    InsertTailList (&sc_if->TransmitFreeQueueHead, &m_head->Link);
+    enq++;
+  }
+
+  if (enq > 0) {
+    // Transmit
+    CSR_WRITE_2 (sc_if->msk_softc, Y2_PREF_Q_ADDR (sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
+                 sc_if->msk_cdata.msk_tx_prod);
+  }
+}
+
+VOID
+mskc_shutdown (
+    struct msk_softc  *sc
+    )
+{
+  INTN i;
+  EFI_TPL OldTpl;
+
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  for (i = 0; i < sc->msk_num_port; i++) {
+    if (sc->msk_if[i] != NULL) {
+      mskc_stop_if (sc->msk_if[i]);
+    }
+  }
+  gBS->SetTimer (sc->Timer, TimerCancel, 0);
+
+  /* Put hardware reset. */
+  CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);
+
+  gBS->RestoreTPL (OldTpl);
+}
+
+EFI_STATUS
+mskc_receive (
+    struct msk_if_softc  *sc_if,
+    IN OUT UINTN  *BufferSize,
+    OUT    VOID   *Buffer
+    )
+{
+  MSK_LINKED_SYSTEM_BUF   *mBuf;
+
+  msk_intr (sc_if->msk_softc); // check the interrupt lines
+
+  if (IsListEmpty (&sc_if->ReceiveQueueHead)) {
+    *BufferSize = 0;
+    return EFI_NOT_READY;
+  }
+
+  mBuf = CR (GetFirstNode (&sc_if->ReceiveQueueHead), MSK_LINKED_SYSTEM_BUF, Link, RX_MBUF_SIGNATURE);
+  if (mBuf->SystemBuf.Length > *BufferSize) {
+    *BufferSize = mBuf->SystemBuf.Length;
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Receive buffer is too small: Provided = %d, Received = %d\n",
+            *BufferSize, mBuf->SystemBuf.Length));
+    return EFI_BUFFER_TOO_SMALL;
+  }
+  *BufferSize = mBuf->SystemBuf.Length;
+  RemoveEntryList (&mBuf->Link);
+  gBS->CopyMem (Buffer, mBuf->SystemBuf.Buf, *BufferSize);
+  gBS->FreePool(mBuf->SystemBuf.Buf);
+  gBS->FreePool (mBuf);
+  return EFI_SUCCESS;
+}
+
+static VOID
+msk_rxeof (
+    struct msk_if_softc   *sc_if,
+    UINT32                status,
+    UINT32                control,
+    INTN                  len
+    )
+{
+  EFI_STATUS            Status;
+  MSK_LINKED_SYSTEM_BUF *m_link;
+  struct msk_rxdesc     *rxd;
+  INTN                  cons;
+  INTN                  rxlen;
+  MSK_DMA_BUF           m;
+  EFI_PCI_IO_PROTOCOL    *PciIo;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: rxeof\n"));
+
+  PciIo = sc_if->msk_softc->PciIo;
+  cons = sc_if->msk_cdata.msk_rx_cons;
+  do {
+    rxlen = status >> 16;
+    if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
+      //
+      // For controllers that returns bogus status code
+      // just do minimal check and let upper stack
+      // handle this frame.
+      //
+      if (len > MAX_SUPPORTED_PACKET_SIZE || len < NET_ETHER_ADDR_LEN) {
+        msk_discard_rxbuf (sc_if, cons);
+        break;
+      }
+    } else if (len > sc_if->msk_framesize ||
+               ((status & GMR_FS_ANY_ERR) != 0) ||
+               ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
+      msk_discard_rxbuf (sc_if, cons);
+      break;
+    }
+
+#ifdef MSK_64BIT_DMA
+    rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % MSK_RX_RING_CNT];
+#else
+    rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
+#endif
+
+    m.Buf = rxd->rx_m.Buf;
+    m.DmaMapping = rxd->rx_m.DmaMapping;
+    m.Length = rxd->rx_m.Length;
+
+    Status = msk_newbuf (sc_if, cons);
+    if (EFI_ERROR (Status)) {
+      // This is a dropped packet, but we aren't counting drops
+      // Reuse old buffer
+      msk_discard_rxbuf (sc_if, cons);
+      break;
+    }
+
+    Status = PciIo->Flush (PciIo);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((EFI_D_NET, "Marvell Yukon: failed to Flush DMA\n"));
+    }
+
+    Status = PciIo->Unmap (PciIo, rxd->rx_m.DmaMapping);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((EFI_D_NET, "Marvell Yukon: failed to Unmap DMA\n"));
+    }
+
+    Status = gBS->AllocatePool (EfiBootServicesData,
+                                sizeof (MSK_LINKED_SYSTEM_BUF),
+                                (VOID**) &m_link);
+    if (!EFI_ERROR (Status)) {
+      gBS->SetMem (m_link, sizeof (MSK_LINKED_SYSTEM_BUF), 0);
+      m_link->Signature = RX_MBUF_SIGNATURE;
+      m_link->SystemBuf.Buf = m.Buf;
+      m_link->SystemBuf.Length = len;
+
+      InsertTailList (&sc_if->ReceiveQueueHead, &m_link->Link);
+    } else {
+      DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate receive buffer link. Dropping Frame\n"));
+      gBS->FreePool (m.Buf);
+    }
+  } while (0);
+
+  MSK_RX_INC (sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
+  MSK_RX_INC (sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
+}
+
+static
+VOID
+msk_txeof (
+    struct msk_if_softc   *sc_if,
+    INTN                  idx
+    )
+{
+  struct msk_txdesc   *txd;
+  struct msk_tx_desc  *cur_tx;
+  UINT32              control;
+  INTN                cons;
+  INTN                prog;
+  EFI_PCI_IO_PROTOCOL  *PciIo;
+
+  DEBUG ((EFI_D_NET, "Marvell Yukon: txeof\n"));
+
+  PciIo = sc_if->msk_softc->PciIo;
+
+  //
+  // Go through our tx ring and free mbufs for those
+  // frames that have been sent.
+  //
+  cons = sc_if->msk_cdata.msk_tx_cons;
+  prog = 0;
+  for (; cons != idx; MSK_INC (cons, MSK_TX_RING_CNT)) {
+    if (sc_if->msk_cdata.msk_tx_cnt <= 0) {
+      break;
+    }
+    prog++;
+    cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
+    control = le32toh (cur_tx->msk_control);
+    sc_if->msk_cdata.msk_tx_cnt--;
+    if ((control & EOP) == 0) {
+      continue;
+    }
+    txd = &sc_if->msk_cdata.msk_txdesc[cons];
+    PciIo->Unmap (PciIo, txd->tx_m.DmaMapping);
+    gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0);
+    // We don't own the transmit buffers so don't free them
+  }
+
+  if (prog > 0) {
+    sc_if->msk_cdata.msk_tx_cons = cons;
+    // No need to sync LEs as we didn't update LEs.
+  }
+}
+
+VOID
+mskc_tick (
+    IN EFI_EVENT  Event,
+    IN VOID       *Context
+    )
+{
+  EFI_TPL OldTpl;
+  struct msk_softc    *sc;
+
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  sc = (struct msk_softc *)Context;
+
+  if (sc->msk_if[MSK_PORT_A] != NULL && sc->msk_if[MSK_PORT_A]->active) {
+    e1000phy_tick (sc->msk_if[MSK_PORT_A]->phy_softc);
+  }
+  if (sc->msk_if[MSK_PORT_B] != NULL && sc->msk_if[MSK_PORT_B]->active) {
+    e1000phy_tick (sc->msk_if[MSK_PORT_B]->phy_softc);
+  }
+
+  msk_handle_events (sc);
+
+  gBS->RestoreTPL (OldTpl);
+}
+
+static
+VOID
+msk_intr_phy (
+    struct msk_if_softc   *sc_if
+    )
+{
+  UINT16  status;
+
+  msk_phy_readreg (sc_if, PHY_MARV_INT_STAT);
+  status = msk_phy_readreg (sc_if, PHY_MARV_INT_STAT);
+
+  // Handle FIFO Underrun/Overflow ?
+  if ((status & PHY_M_IS_FIFO_ERROR)) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: PHY FIFO underrun/overflow.\n"));
+  }
+}
+
+static
+VOID
+msk_intr_gmac (
+    struct msk_if_softc   *sc_if
+    )
+{
+  UINT8   status;
+  struct msk_softc  *sc;
+
+  sc = sc_if->msk_softc;
+
+  status = CSR_READ_1 (sc, MR_ADDR (sc_if->msk_md.port, GMAC_IRQ_SRC));
+
+  // GMAC Rx FIFO overrun.
+  if ((status & GM_IS_RX_FF_OR) != 0) {
+    CSR_WRITE_4 (sc, MR_ADDR (sc_if->msk_md.port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
+  }
+  // GMAC Tx FIFO underrun.
+  if ((status & GM_IS_TX_FF_UR) != 0) {
+    CSR_WRITE_4 (sc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
+    //device_printf (sc_if->msk_if_dev, "Tx FIFO underrun!\n");*/
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Tx FIFO underrun!\n"));
+    /*
+     * XXX
+     * In case of Tx underrun, we may need to flush/reset
+     * Tx MAC but that would also require resynchronization
+     * with status LEs. Reintializing status LEs would
+     * affect other port in dual MAC configuration so it
+     * should be aVOIDed as possible as we can.
+     * Due to lack of documentation it's all vague guess but
+     * it needs more investigation.
+     */
+  }
+}
+
+static
+VOID
+msk_handle_hwerr (
+    struct msk_if_softc   *sc_if,
+    UINT32                status
+    )
+{
+  struct msk_softc  *sc;
+
+  sc = sc_if->msk_softc;
+
+  if ((status & Y2_IS_PAR_RD1) != 0) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: RAM buffer read parity error\n"));
+    // Clear IRQ.
+    CSR_WRITE_2 (sc, SELECT_RAM_BUFFER (sc_if->msk_md.port, B3_RI_CTRL), RI_CLR_RD_PERR);
+  }
+  if ((status & Y2_IS_PAR_WR1) != 0) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: RAM buffer write parity error\n"));
+    // Clear IRQ
+    CSR_WRITE_2 (sc, SELECT_RAM_BUFFER (sc_if->msk_md.port, B3_RI_CTRL), RI_CLR_WR_PERR);
+  }
+  if ((status & Y2_IS_PAR_MAC1) != 0) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Tx MAC parity error\n"));
+    // Clear IRQ
+    CSR_WRITE_4 (sc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
+  }
+  if ((status & Y2_IS_PAR_RX1) != 0) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Rx parity error\n"));
+    // Clear IRQ
+    CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
+  }
+  if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: TCP segmentation error\n"));
+    // Clear IRQ
+    CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
+  }
+}
+
+static
+VOID
+msk_intr_hwerr (
+    struct msk_softc    *sc
+    )
+{
+  UINT32  status;
+  UINT32  tlphead[4];
+
+  status = CSR_READ_4 (sc, B0_HWE_ISRC);
+
+  // Time Stamp timer overflow.
+  if ((status & Y2_IS_TIST_OV) != 0) {
+    CSR_WRITE_1 (sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
+  }
+  if ((status & Y2_IS_PCI_NEXP) != 0) {
+    /*
+     * PCI Express Error occured which is not described in PEX
+     * spec.
+     * This error is also mapped either to Master Abort (
+     * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
+     * can only be cleared there.
+     */
+    DEBUG ((EFI_D_NET, "Marvell Yukon: PCI Express protocol violation error\n"));
+  }
+
+  if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
+
+    if ((status & Y2_IS_MST_ERR) != 0) {
+      DEBUG ((EFI_D_NET, "Marvell Yukon: unexpected IRQ Status error\n"));
+    } else {
+      DEBUG ((EFI_D_NET, "Marvell Yukon: unexpected IRQ Master error\n"));
+    }
+    // Reset all bits in the PCI status register
+    clear_pci_errors (sc);
+  }
+
+  // Check for PCI Express Uncorrectable Error.
+  if ((status & Y2_IS_PCI_EXP) != 0) {
+    UINT32 v32;
+
+    /*
+     * On PCI Express bus bridges are called root complexes (RC).
+     * PCI Express errors are recognized by the root complex too,
+     * which requests the system to handle the problem. After
+     * error occurrence it may be that no access to the adapter
+     * may be performed any longer.
+     */
+
+    v32 = CSR_PCI_READ_4 (sc, PEX_UNC_ERR_STAT);
+    if ((v32 & PEX_UNSUP_REQ) != 0) {
+      // Ignore unsupported request error.
+      DEBUG ((EFI_D_NET, "Marvell Yukon: Uncorrectable PCI Express error\n"));
+    }
+    if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
+      INTN i;
+
+      // Get TLP header form Log Registers.
+      for (i = 0; i < 4; i++) {
+        tlphead[i] = CSR_PCI_READ_4 (sc, PEX_HEADER_LOG + i * 4);
+      }
+      // Check for vendor defined broadcast message.
+      if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
+        sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
+        CSR_WRITE_4 (sc, B0_HWE_IMSK, sc->msk_intrhwemask);
+        CSR_READ_4 (sc, B0_HWE_IMSK);
+      }
+    }
+    // Clear the interrupt
+    CSR_WRITE_1 (sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
+    CSR_PCI_WRITE_4 (sc, PEX_UNC_ERR_STAT, 0xffffffff);
+    CSR_WRITE_1 (sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
+  }
+
+  if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) {
+    msk_handle_hwerr (sc->msk_if[MSK_PORT_A], status);
+  }
+  if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) {
+    msk_handle_hwerr (sc->msk_if[MSK_PORT_B], status >> 8);
+  }
+}
+
+static
+__inline
+VOID
+msk_rxput (
+    struct msk_if_softc   *sc_if
+    )
+{
+  CSR_WRITE_2 (sc_if->msk_softc, Y2_PREF_Q_ADDR (sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
+}
+
+static
+INTN
+msk_handle_events (
+    struct msk_softc  *sc
+    )
+{
+  INTN                  rxput[2];
+  struct msk_stat_desc  *sd;
+  UINT32                control;
+  UINT32                status;
+  INTN                  cons;
+  INTN                  len;
+  INTN                  port;
+  INTN                  rxprog;
+  struct msk_if_softc   *sc_if;
+
+  if (sc->msk_stat_cons == CSR_READ_2 (sc, STAT_PUT_IDX)) {
+    return (0);
+  }
+
+  rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
+  rxprog = 0;
+  cons = sc->msk_stat_cons;
+  for (;;) {
+    sd = &sc->msk_stat_ring[cons];
+    control = le32toh (sd->msk_control);
+    if ((control & HW_OWNER) == 0) {
+      break;
+    }
+    control &= ~HW_OWNER;
+    sd->msk_control = htole32 (control);
+    status = le32toh (sd->msk_status);
+    len = control & STLE_LEN_MASK;
+    port = (control >> 16) & 0x01;
+    sc_if = sc->msk_if[port];
+    if (sc_if == NULL) {
+      DEBUG ((EFI_D_NET, "Marvell Yukon: invalid port opcode 0x%08x\n", control & STLE_OP_MASK));
+      continue;
+    }
+
+    switch (control & STLE_OP_MASK) {
+      case OP_RXSTAT:
+        msk_rxeof (sc_if, status, control, len);
+        rxprog++;
+        //
+        // Because there is no way to sync single Rx LE
+        // put the DMA sync operation off until the end of
+        // event processing.
+        //
+        rxput[port]++;
+        // Update prefetch unit if we've passed water mark
+        if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
+          msk_rxput (sc_if);
+          rxput[port] = 0;
+        }
+        break;
+      case OP_TXINDEXLE:
+        if (sc->msk_if[MSK_PORT_A] != NULL) {
+          msk_txeof (sc->msk_if[MSK_PORT_A], status & STLE_TXA1_MSKL);
+        }
+        if (sc->msk_if[MSK_PORT_B] != NULL) {
+          msk_txeof (sc->msk_if[MSK_PORT_B],
+                     ((status & STLE_TXA2_MSKL) >>
+                      STLE_TXA2_SHIFTL) |
+                     ((len & STLE_TXA2_MSKH) <<
+                      STLE_TXA2_SHIFTH));
+        }
+        break;
+      default:
+        DEBUG ((EFI_D_NET, "Marvell Yukon: unhandled opcode 0x%08x\n", control & STLE_OP_MASK));
+        break;
+    }
+    MSK_INC (cons, MSK_STAT_RING_CNT);
+    if (rxprog > sc->msk_process_limit) {
+      break;
+    }
+  }
+
+  sc->msk_stat_cons = cons;
+
+  if (rxput[MSK_PORT_A] > 0) {
+    msk_rxput (sc->msk_if[MSK_PORT_A]);
+  }
+  if (rxput[MSK_PORT_B] > 0) {
+    msk_rxput (sc->msk_if[MSK_PORT_B]);
+  }
+
+  return (sc->msk_stat_cons != CSR_READ_2 (sc, STAT_PUT_IDX));
+}
+
+STATIC
+VOID
+msk_intr (
+    struct msk_softc  *sc
+    )
+{
+  struct msk_if_softc   *sc_if0;
+  struct msk_if_softc   *sc_if1;
+  UINT32                Status;
+  INTN                  domore;
+
+  // Reading B0_Y2_SP_ISRC2 masks further interrupts
+  Status = CSR_READ_4 (sc, B0_Y2_SP_ISRC2);
+  if (Status == 0 || Status == 0xffffffff ||
+      (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
+      (Status & sc->msk_intrmask) == 0)
+  {
+    // Leave ISR - Reenable interrupts
+    CSR_WRITE_4 (sc, B0_Y2_SP_ICR, 2);
+    return;
+  }
+
+  sc_if0 = sc->msk_if[MSK_PORT_A];
+  sc_if1 = sc->msk_if[MSK_PORT_B];
+
+  if ((Status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) {
+    msk_intr_phy (sc_if0);
+  }
+  if ((Status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) {
+    msk_intr_phy (sc_if1);
+  }
+  if ((Status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) {
+    msk_intr_gmac (sc_if0);
+  }
+  if ((Status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) {
+    msk_intr_gmac (sc_if1);
+  }
+  if ((Status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Rx descriptor error\n"));
+    sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
+    CSR_WRITE_4 (sc, B0_IMSK, sc->msk_intrmask);
+    CSR_READ_4 (sc, B0_IMSK);
+  }
+  if ((Status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Tx descriptor error\n"));
+    sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
+    CSR_WRITE_4 (sc, B0_IMSK, sc->msk_intrmask);
+    CSR_READ_4 (sc, B0_IMSK);
+  }
+  if ((Status & Y2_IS_HW_ERR) != 0) {
+    msk_intr_hwerr (sc);
+  }
+
+  domore = msk_handle_events (sc);
+  if ((Status & Y2_IS_STAT_BMU) != 0 && domore == 0) {
+    CSR_WRITE_4 (sc, STAT_CTRL, SC_STAT_CLR_IRQ);
+  }
+
+  // Leave ISR - Reenable interrupts
+  CSR_WRITE_4 (sc, B0_Y2_SP_ICR, 2);
+}
+
+static
+VOID
+msk_set_tx_stfwd (
+    struct msk_if_softc   *sc_if
+    )
+{
+  // Disable jumbo frames for Tx
+  CSR_WRITE_4 (sc_if->msk_softc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), TX_JUMBO_DIS | TX_STFW_ENA);
+}
+
+EFI_STATUS
+mskc_init (
+    struct msk_if_softc  *sc_if
+    )
+{
+  EFI_STATUS  Status;
+
+  Status = msk_init (sc_if);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return Status;
+}
+
+static
+EFI_STATUS
+msk_init (
+    IN struct msk_if_softc  *sc_if
+    )
+{
+  UINT8       *eaddr;
+  UINT16      gmac;
+  UINT32      reg;
+  EFI_STATUS  Status;
+  INTN                 port;
+  IN struct msk_softc  *sc;
+
+  sc = sc_if->msk_softc;
+  port = sc_if->msk_md.port;
+
+  // Cancel pending I/O and free all Rx/Tx buffers.
+  mskc_stop_if (sc_if);
+
+  sc_if->msk_framesize = MAX_SUPPORTED_PACKET_SIZE;
+
+  // GMAC Control reset.
+  CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_RST_SET);
+  CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_RST_CLR);
+  CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_F_LOOPB_OFF);
+  if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
+    CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | GMC_BYP_RETR_ON);
+  }
+
+  //
+  // Initialize GMAC first such that speed/duplex/flow-control
+  // parameters are renegotiated when interface is brought up.
+  //
+  GMAC_WRITE_2 (sc, port, GM_GP_CTRL, 0);
+
+  // Dummy read the Interrupt Source Register
+  CSR_READ_1 (sc, MR_ADDR (port, GMAC_IRQ_SRC));
+
+  // Clear MIB stats
+  msk_stats_clear (sc_if);
+
+  // Disable FCS
+  GMAC_WRITE_2 (sc, port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
+
+  // Setup Transmit Control Register
+  GMAC_WRITE_2 (sc, port, GM_TX_CTRL, TX_COL_THR (TX_COL_DEF));
+
+  // Setup Transmit Flow Control Register
+  GMAC_WRITE_2 (sc, port, GM_TX_FLOW_CTRL, 0xffff);
+
+  // Setup Transmit Parameter Register
+  GMAC_WRITE_2 (sc, port, GM_TX_PARAM,
+                TX_JAM_LEN_VAL (TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL (TX_JAM_IPG_DEF) |
+                TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
+
+  gmac = DATA_BLIND_VAL (DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA | IPG_DATA_VAL (IPG_DATA_DEF);
+
+  GMAC_WRITE_2 (sc, port, GM_SERIAL_MODE, gmac);
+
+  // Set station address
+  eaddr = sc_if->MacAddress.Addr;
+  GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_1L, eaddr[0] | (eaddr[1] << 8));
+  GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_1M, eaddr[2] | (eaddr[3] << 8));
+  GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_1H, eaddr[4] | (eaddr[5] << 8));
+  GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_2L, eaddr[0] | (eaddr[1] << 8));
+  GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_2M, eaddr[2] | (eaddr[3] << 8));
+  GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_2H, eaddr[4] | (eaddr[5] << 8));
+
+  // Disable interrupts for counter overflows
+  GMAC_WRITE_2 (sc, port, GM_TX_IRQ_MSK, 0);
+  GMAC_WRITE_2 (sc, port, GM_RX_IRQ_MSK, 0);
+  GMAC_WRITE_2 (sc, port, GM_TR_IRQ_MSK, 0);
+
+  // Configure Rx MAC FIFO
+  CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_SET);
+  CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_CLR);
+  reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
+  if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || sc->msk_hw_id == CHIP_ID_YUKON_EX) {
+    reg |= GMF_RX_OVER_ON;
+  }
+  CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), reg);
+
+  if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
+    // Clear flush mask - HW bug
+    CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_FL_MSK), 0);
+  } else {
+    // Flush Rx MAC FIFO on any flow control or error
+    CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
+  }
+
+  //
+  // Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
+  // due to hardware hang on receipt of pause frames.
+  //
+  reg = RX_GMF_FL_THR_DEF + 1;
+  // Another magic for Yukon FE+ - From Linux
+  if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
+    reg = 0x178;
+  }
+  CSR_WRITE_2 (sc, MR_ADDR (port, RX_GMF_FL_THR), reg);
+
+  // Configure Tx MAC FIFO
+  CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_SET);
+  CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_CLR);
+  CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_OPER_ON);
+
+  // Configure hardware VLAN tag insertion/stripping
+  msk_setvlan (sc_if);
+
+  if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
+    // Set Rx Pause threshould.
+    CSR_WRITE_2 (sc, MR_ADDR (port, RX_GMF_LP_THR), MSK_ECU_LLPP);
+    CSR_WRITE_2 (sc, MR_ADDR (port, RX_GMF_UP_THR), MSK_ECU_ULPP);
+    // Configure store-and-forward for Tx.
+    msk_set_tx_stfwd (sc_if);
+  }
+
+  if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
+    // Disable dynamic watermark - from Linux
+    reg = CSR_READ_4 (sc, MR_ADDR (port, TX_GMF_EA));
+    reg &= ~0x03;
+    CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_EA), reg);
+  }
+
+  //
+  // Disable Force Sync bit and Alloc bit in Tx RAM interface
+  // arbiter as we don't use Sync Tx queue.
+  //
+  CSR_WRITE_1 (sc, MR_ADDR (port, TXA_CTRL), TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
+  // Enable the RAM Interface Arbiter
+  CSR_WRITE_1 (sc, MR_ADDR (port, TXA_CTRL), TXA_ENA_ARB);
+
+  // Setup RAM buffer
+  msk_set_rambuffer (sc_if);
+
+  // Disable Tx sync Queue
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
+
+  // Setup Tx Queue Bus Memory Interface
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
+  CSR_WRITE_2 (sc, Q_ADDR (sc_if->msk_txq, Q_WM),  MSK_BMU_TX_WM);
+  switch (sc->msk_hw_id) {
+    case CHIP_ID_YUKON_EC_U:
+      if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
+        // Fix for Yukon-EC Ultra: set BMU FIFO level
+        CSR_WRITE_2 (sc, Q_ADDR (sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV);
+      }
+      break;
+    case CHIP_ID_YUKON_EX:
+      //
+      // Yukon Extreme seems to have silicon bug for
+      // automatic Tx checksum calculation capability.
+      //
+      if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) {
+        CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_F), F_TX_CHK_AUTO_OFF);
+      }
+      break;
+  }
+
+  // Setup Rx Queue Bus Memory Interface
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
+  CSR_WRITE_2 (sc, Q_ADDR (sc_if->msk_rxq, Q_WM),  MSK_BMU_RX_WM);
+  if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
+    // MAC Rx RAM Read is controlled by hardware
+    CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
+  }
+
+  // truncate too-large frames - from linux
+  CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_TR_THR), 0x17a);
+  CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), RX_TRUNC_ON);
+
+  msk_set_prefetch (sc_if, sc_if->msk_txq, sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
+  msk_init_tx_ring (sc_if);
+
+  // Disable Rx checksum offload and RSS hash
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH);
+  msk_set_prefetch (sc_if, sc_if->msk_rxq, sc_if->msk_rdata.msk_rx_ring_paddr, MSK_RX_RING_CNT - 1);
+  Status = msk_init_rx_ring (sc_if);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Marvell Yukon: Initialization failed: no memory for Rx buffers\n"));
+    mskc_stop_if (sc_if);
+    return Status;
+  }
+
+  if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
+    // Disable flushing of non-ASF packets
+    CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RX_MACSEC_FLUSH_OFF);
+  }
+
+  // Configure interrupt handling
+  if (port == MSK_PORT_A) {
+    sc->msk_intrmask |= Y2_IS_PORT_A;
+    sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
+  } else {
+    sc->msk_intrmask |= Y2_IS_PORT_B;
+    sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
+  }
+  // Configure IRQ moderation mask.
+  CSR_WRITE_4 (sc, B2_IRQM_MSK, sc->msk_intrmask);
+  if (sc->msk_int_holdoff > 0) {
+    // Configure initial IRQ moderation timer value.
+    CSR_WRITE_4 (sc, B2_IRQM_INI, MSK_USECS (sc, sc->msk_int_holdoff));
+    CSR_WRITE_4 (sc, B2_IRQM_VAL, MSK_USECS (sc, sc->msk_int_holdoff));
+    // Start IRQ moderation.
+    CSR_WRITE_1 (sc, B2_IRQM_CTRL, TIM_START);
+  }
+  CSR_WRITE_4 (sc, B0_HWE_IMSK, sc->msk_intrhwemask);
+  CSR_READ_4 (sc, B0_HWE_IMSK);
+  CSR_WRITE_4 (sc, B0_IMSK, sc->msk_intrmask);
+  CSR_READ_4 (sc, B0_IMSK);
+
+  sc_if->msk_flags &= ~MSK_FLAG_LINK;
+  e1000phy_mediachg (sc_if->phy_softc);
+
+  return Status;
+}
+
+STATIC
+VOID
+msk_set_rambuffer (
+    struct msk_if_softc *sc_if
+    )
+{
+  INTN ltpp, utpp;
+  INTN              port;
+  struct msk_softc  *sc;
+
+  sc = sc_if->msk_softc;
+  port = sc_if->msk_md.port;
+
+  if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
+    return;
+
+  // Setup Rx Queue
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_START), sc->msk_rxqstart[port] / 8);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_END), sc->msk_rxqend[port] / 8);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_WP), sc->msk_rxqstart[port] / 8);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RP), sc->msk_rxqstart[port] / 8);
+
+  utpp = (sc->msk_rxqend[port] + 1 - sc->msk_rxqstart[port] - MSK_RB_ULPP) / 8;
+  ltpp = (sc->msk_rxqend[port] + 1 - sc->msk_rxqstart[port] - MSK_RB_LLPP_B) / 8;
+  if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) {
+    ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
+  }
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RX_UTPP), utpp);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RX_LTPP), ltpp);
+  // Set Rx priority (RB_RX_UTHP/RB_RX_LTHP) thresholds?
+
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
+  CSR_READ_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL));
+
+  // Setup Tx Queue.
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_txq, RB_START), sc->msk_txqstart[port] / 8);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_txq, RB_END), sc->msk_txqend[port] / 8);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_txq, RB_WP), sc->msk_txqstart[port] / 8);
+  CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_txq, RB_RP), sc->msk_txqstart[port] / 8);
+
+  // Enable Store & Forward for Tx side
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
+  CSR_READ_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL));
+}
+
+STATIC
+VOID
+msk_set_prefetch (
+    struct msk_if_softc   *sc_if,
+    INTN qaddr,
+    EFI_PHYSICAL_ADDRESS addr,
+    UINT32 count
+    )
+{
+  struct msk_softc     *sc;
+
+  sc = sc_if->msk_softc;
+
+  // Reset the prefetch unit
+  CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
+  CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR);
+  // Set LE base address
+  CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_ADDR_LOW_REG), MSK_ADDR_LO (addr));
+  CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_ADDR_HI_REG), MSK_ADDR_HI (addr));
+
+  // Set the list last index
+  CSR_WRITE_2 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_LAST_IDX_REG), count);
+  // Turn on prefetch unit
+  CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON);
+  // Dummy read to ensure write
+  CSR_READ_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG));
+}
+
+VOID
+mskc_stop_if (
+    struct msk_if_softc  *sc_if
+    )
+{
+  struct msk_txdesc   *txd;
+  struct msk_rxdesc   *rxd;
+  UINT32              val;
+  INTN                i;
+  INTN                 port;
+  EFI_PCI_IO_PROTOCOL  *PciIo;
+  struct msk_softc     *sc;
+
+  sc = sc_if->msk_softc;
+  PciIo = sc->PciIo;
+  port = sc_if->msk_md.port;
+
+  // Disable interrupts
+  if (port == MSK_PORT_A) {
+    sc->msk_intrmask &= ~Y2_IS_PORT_A;
+    sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
+  } else {
+    sc->msk_intrmask &= ~Y2_IS_PORT_B;
+    sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
+  }
+  CSR_WRITE_4 (sc, B0_HWE_IMSK, sc->msk_intrhwemask);
+  CSR_READ_4 (sc, B0_HWE_IMSK);
+  CSR_WRITE_4 (sc, B0_IMSK, sc->msk_intrmask);
+  CSR_READ_4 (sc, B0_IMSK);
+
+  // Disable Tx/Rx MAC.
+  val = GMAC_READ_2 (sc, port, GM_GP_CTRL);
+  val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
+  GMAC_WRITE_2 (sc, port, GM_GP_CTRL, val);
+  // Read again to ensure writing.
+  GMAC_READ_2 (sc, port, GM_GP_CTRL);
+  // Update stats and clear counters
+  msk_stats_update (sc_if);
+
+  // Stop Tx BMU
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_STOP);
+  val = CSR_READ_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR));
+  for (i = 0; i < MSK_TIMEOUT; i++) {
+    if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
+      CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_STOP);
+      val = CSR_READ_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR));
+    } else {
+      break;
+    }
+    gBS->Stall (1);
+  }
+  if (i == MSK_TIMEOUT) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Tx BMU stop failed\n"));
+  }
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_SET | RB_DIS_OP_MD);
+
+  // Disable all GMAC interrupt.
+  CSR_WRITE_1 (sc, MR_ADDR (port, GMAC_IRQ_MSK), 0);
+  // Disable PHY interrupt. */
+  msk_phy_writereg (sc_if, PHY_MARV_INT_MASK, 0);
+
+  // Disable the RAM Interface Arbiter.
+  CSR_WRITE_1 (sc, MR_ADDR (port, TXA_CTRL), TXA_DIS_ARB);
+
+  // Reset the PCI FIFO of the async Tx queue
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
+
+  // Reset the Tx prefetch units
+  CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (sc_if->msk_txq, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
+
+  // Reset the RAM Buffer async Tx queue
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_SET);
+
+  // Reset Tx MAC FIFO.
+  CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_SET);
+  // Set Pause Off.
+  CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_PAUSE_OFF);
+
+  /*
+   * The Rx Stop command will not work for Yukon-2 if the BMU does not
+   * reach the end of packet and since we can't make sure that we have
+   * incoming data, we must reset the BMU while it is not during a DMA
+   * transfer. Since it is possible that the Rx path is still active,
+   * the Rx RAM buffer will be stopped first, so any possible incoming
+   * data will not trigger a DMA. After the RAM buffer is stopped, the
+   * BMU is polled until any DMA in progress is ended and only then it
+   * will be reset.
+   */
+
+  // Disable the RAM Buffer receive queue
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
+  for (i = 0; i < MSK_TIMEOUT; i++) {
+    if (CSR_READ_1 (sc, RB_ADDR (sc_if->msk_rxq, Q_RSL)) == CSR_READ_1 (sc, RB_ADDR (sc_if->msk_rxq, Q_RL))) {
+      break;
+    }
+    gBS->Stall (1);
+  }
+  if (i == MSK_TIMEOUT) {
+    DEBUG ((EFI_D_NET, "Marvell Yukon: Rx BMU stop failed\n"));
+  }
+  CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
+  // Reset the Rx prefetch unit.
+  CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (sc_if->msk_rxq, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
+  // Reset the RAM Buffer receive queue.
+  CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
+  // Reset Rx MAC FIFO.
+  CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_SET);
+
+  // Free Rx and Tx mbufs still in the queues
+  for (i = 0; i < MSK_RX_RING_CNT; i++) {
+    rxd = &sc_if->msk_cdata.msk_rxdesc[i];
+    if (rxd->rx_m.Buf != NULL) {
+      PciIo->Unmap (PciIo, rxd->rx_m.DmaMapping);
+      if(rxd->rx_m.Buf != NULL) {
+        gBS->FreePool (rxd->rx_m.Buf);
+        rxd->rx_m.Buf = NULL;
+      }
+      gBS->SetMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF), 0);
+    }
+  }
+
+  for (i = 0; i < MSK_TX_RING_CNT; i++) {
+    txd = &sc_if->msk_cdata.msk_txdesc[i];
+    if (txd->tx_m.Buf != NULL) {
+      PciIo->Unmap (PciIo, txd->tx_m.DmaMapping);
+      gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0);
+      // We don't own the transmit buffers so don't free them
+    }
+  }
+
+  /*
+   * Mark the interface down.
+   */
+  sc_if->msk_flags &= ~MSK_FLAG_LINK;
+}
+
+/*
+ * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
+ * counter clears high 16 bits of the counter such that accessing
+ * lower 16 bits should be the last operation.
+ */
+#define  MSK_READ_MIB32(x, y)    (((UINT32)GMAC_READ_2 (sc, x, (y) + 4)) << 16) +  (UINT32)GMAC_READ_2 (sc, x, y)
+#define  MSK_READ_MIB64(x, y)    (((UINT64)MSK_READ_MIB32 (x, (y) + 8)) << 32) + (UINT64)MSK_READ_MIB32 (x, y)
+
+static
+VOID
+msk_stats_clear (
+    struct msk_if_softc   *sc_if
+    )
+{
+  UINT16      gmac;
+  INTN        val;
+  INTN        i;
+  INTN              port;
+  struct msk_softc  *sc;
+
+  sc = sc_if->msk_softc;
+  port = sc_if->msk_md.port;
+
+  // Set MIB Clear Counter Mode.
+  gmac = GMAC_READ_2 (sc, port, GM_PHY_ADDR);
+  GMAC_WRITE_2 (sc, port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
+  // Read all MIB Counters with Clear Mode set
+  for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof (UINT32)) {
+    val = MSK_READ_MIB32 (port, i);
+    if (val); //Workaround: to prevent the GCC error: 'value computed is not used'
+  }
+  // Clear MIB Clear Counter Mode
+  gmac &= ~GM_PAR_MIB_CLR;
+  GMAC_WRITE_2 (sc, port, GM_PHY_ADDR, gmac);
+}
+
+static
+VOID
+msk_stats_update (
+    struct msk_if_softc   *sc_if
+    )
+{
+  struct msk_hw_stats   *stats;
+  UINT16                gmac;
+  INTN                  val;
+  INTN                 port;
+  struct msk_softc     *sc;
+
+  sc = sc_if->msk_softc;
+  port = sc_if->msk_md.port;
+  stats = &sc_if->msk_stats;
+  /* Set MIB Clear Counter Mode. */
+  gmac = GMAC_READ_2 (sc, port, GM_PHY_ADDR);
+  GMAC_WRITE_2 (sc, port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
+
+  /* Rx stats. */
+  stats->rx_ucast_frames    += MSK_READ_MIB32 (port, GM_RXF_UC_OK);
+  stats->rx_bcast_frames    += MSK_READ_MIB32 (port, GM_RXF_BC_OK);
+  stats->rx_pause_frames    += MSK_READ_MIB32 (port, GM_RXF_MPAUSE);
+  stats->rx_mcast_frames    += MSK_READ_MIB32 (port, GM_RXF_MC_OK);
+  stats->rx_crc_errs        += MSK_READ_MIB32 (port, GM_RXF_FCS_ERR);
+  val = MSK_READ_MIB32 (port, GM_RXF_SPARE1);
+  stats->rx_good_octets     += MSK_READ_MIB64 (port, GM_RXO_OK_LO);
+  stats->rx_bad_octets      += MSK_READ_MIB64 (port, GM_RXO_ERR_LO);
+  stats->rx_runts           += MSK_READ_MIB32 (port, GM_RXF_SHT);
+  stats->rx_runt_errs       += MSK_READ_MIB32 (port, GM_RXE_FRAG);
+  stats->rx_pkts_64         += MSK_READ_MIB32 (port, GM_RXF_64B);
+  stats->rx_pkts_65_127     += MSK_READ_MIB32 (port, GM_RXF_127B);
+  stats->rx_pkts_128_255    += MSK_READ_MIB32 (port, GM_RXF_255B);
+  stats->rx_pkts_256_511    += MSK_READ_MIB32 (port, GM_RXF_511B);
+  stats->rx_pkts_512_1023   += MSK_READ_MIB32 (port, GM_RXF_1023B);
+  stats->rx_pkts_1024_1518  += MSK_READ_MIB32 (port, GM_RXF_1518B);
+  stats->rx_pkts_1519_max   += MSK_READ_MIB32 (port, GM_RXF_MAX_SZ);
+  stats->rx_pkts_too_long   += MSK_READ_MIB32 (port, GM_RXF_LNG_ERR);
+  stats->rx_pkts_jabbers    += MSK_READ_MIB32 (port, GM_RXF_JAB_PKT);
+  val = MSK_READ_MIB32 (port, GM_RXF_SPARE2);
+  stats->rx_fifo_oflows     += MSK_READ_MIB32 (port, GM_RXE_FIFO_OV);
+  val = MSK_READ_MIB32 (port, GM_RXF_SPARE3);
+
+  /* Tx stats. */
+  stats->tx_ucast_frames    += MSK_READ_MIB32 (port, GM_TXF_UC_OK);
+  stats->tx_bcast_frames    += MSK_READ_MIB32 (port, GM_TXF_BC_OK);
+  stats->tx_pause_frames    += MSK_READ_MIB32 (port, GM_TXF_MPAUSE);
+  stats->tx_mcast_frames    += MSK_READ_MIB32 (port, GM_TXF_MC_OK);
+  stats->tx_octets          += MSK_READ_MIB64 (port, GM_TXO_OK_LO);
+  stats->tx_pkts_64         += MSK_READ_MIB32 (port, GM_TXF_64B);
+  stats->tx_pkts_65_127     += MSK_READ_MIB32 (port, GM_TXF_127B);
+  stats->tx_pkts_128_255    += MSK_READ_MIB32 (port, GM_TXF_255B);
+  stats->tx_pkts_256_511    += MSK_READ_MIB32 (port, GM_TXF_511B);
+  stats->tx_pkts_512_1023   += MSK_READ_MIB32 (port, GM_TXF_1023B);
+  stats->tx_pkts_1024_1518  += MSK_READ_MIB32 (port, GM_TXF_1518B);
+  stats->tx_pkts_1519_max   += MSK_READ_MIB32 (port, GM_TXF_MAX_SZ);
+  val = MSK_READ_MIB32 (port, GM_TXF_SPARE1);
+  stats->tx_colls           += MSK_READ_MIB32 (port, GM_TXF_COL);
+  stats->tx_late_colls      += MSK_READ_MIB32 (port, GM_TXF_LAT_COL);
+  stats->tx_excess_colls    += MSK_READ_MIB32 (port, GM_TXF_ABO_COL);
+  stats->tx_multi_colls     += MSK_READ_MIB32 (port, GM_TXF_MUL_COL);
+  stats->tx_single_colls    += MSK_READ_MIB32 (port, GM_TXF_SNG_COL);
+  stats->tx_underflows      += MSK_READ_MIB32 (port, GM_TXE_FIFO_UR);
+
+  if (val); //Workaround: to prevent the GCC error: 'value computed is not used'
+
+  /* Clear MIB Clear Counter Mode. */
+  gmac &= ~GM_PAR_MIB_CLR;
+  GMAC_WRITE_2 (sc, port, GM_PHY_ADDR, gmac);
+}
+
+#undef MSK_READ_MIB32
+#undef MSK_READ_MIB64
diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.h b/Drivers/Net/MarvellYukonDxe/if_msk.h
new file mode 100644
index 0000000..835d336
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/if_msk.h
@@ -0,0 +1,66 @@
+/**  <at> file
+*  API to ported msk driver
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IF_MSK_H_
+#define _IF_MSK_H_
+
+#include <Uefi.h>
+#include <Protocol/PciIo.h>
+#include "if_mskreg.h"
+#include "miivar.h"
+
+#define MAX_SUPPORTED_PACKET_SIZE   (1566) /* No jumbo frame size support */
+
+EFI_STATUS mskc_probe (EFI_PCI_IO_PROTOCOL *PciIo);
+
+EFI_STATUS mskc_attach (EFI_PCI_IO_PROTOCOL  *, struct msk_softc **);
+EFI_STATUS mskc_attach_if (struct msk_if_softc *, UINTN);
+VOID mskc_detach (struct msk_softc  *);
+VOID mskc_detach_if (struct msk_if_softc *);
+
+EFI_STATUS mskc_init (struct msk_if_softc *);
+VOID mskc_shutdown (struct msk_softc  *);
+VOID mskc_stop_if (struct msk_if_softc *);
+
+void
+mskc_rxfilter (
+    IN struct msk_if_softc         *sc_if,
+    IN UINT32                      FilterFlags,
+    IN UINTN                       MCastFilterCnt,
+    IN EFI_MAC_ADDRESS             *MCastFilter
+    );
+
+EFI_STATUS
+mskc_transmit (
+    IN struct msk_if_softc         *sc_if,
+    IN UINTN                       BufferSize,
+    IN VOID                        *Buffer
+    );
+
+EFI_STATUS
+mskc_receive (
+    IN struct msk_if_softc         *sc_if,
+    IN OUT UINTN                   *BufferSize,
+    OUT VOID                       *Buffer
+    );
+
+void
+mskc_getstatus (
+    IN struct msk_if_softc         *sc,
+    OUT UINT32                     *InterruptStatus, OPTIONAL
+    OUT VOID                       **TxBuf           OPTIONAL
+    );
+
+#endif /* _IF_MSK_H_ */
diff --git a/Drivers/Net/MarvellYukonDxe/if_mskreg.h b/Drivers/Net/MarvellYukonDxe/if_mskreg.h
new file mode 100644
index 0000000..0e18598
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/if_mskreg.h
@@ -0,0 +1,2516 @@
+/**  <at> file
+*  Defines and macros for the PCIe Marvell Yukon gigabit ethernet adapter product family
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/******************************************************************************
+ *
+ *  LICENSE:
+ *  Copyright (C) Marvell International Ltd. and/or its affiliates
+ *
+ *  The computer program files contained in this folder ("Files")
+ *  are provided to you under the BSD-type license terms provided
+ *  below, and any use of such Files and any derivative works
+ *  thereof created by you shall be governed by the following terms
+ *  and conditions:
+ *
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  - Neither the name of Marvell nor the names of its contributors
+ *    may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ *  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF  SUBSTITUTE GOODS OR SERVICES;
+ *  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ *  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ *  OF THE POSSIBILITY OF SUCH DAMAGE.
+ *  /LICENSE
+ *
+ ******************************************************************************/
+
+/*-
+ * Copyright (c) 1997, 1998, 1999, 2000
+ *  Bill Paul <wpaul <at> ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *  This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2003 Nathan L. Binkert <binkertn <at> umich.edu>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*$FreeBSD: src/sys/dev/msk/if_mskreg.h,v 1.27.2.10.2.1 2010/06/14 02:09:06 kensmith Exp $*/
+
+#ifndef _IF_MSKREG_H_
+#define _IF_MSKREG_H_
+
+#include "miivar.h"
+
+/*
+ * SysKonnect PCI vendor ID
+ */
+#define VENDORID_SK                         0x1148
+
+/*
+ * Marvell PCI vendor ID
+ */
+#define VENDORID_MARVELL                    0x11AB
+
+/*
+ * D-Link PCI vendor ID
+ */
+#define  VENDORID_DLINK                     0x1186
+
+/*
+ * SysKonnect ethernet device IDs
+ */
+#define DEVICEID_SK_YUKON2                  0x9000
+#define DEVICEID_SK_YUKON2_EXPR             0x9e00
+
+/*
+ * Marvell gigabit ethernet device IDs
+ */
+#define DEVICEID_MRVL_8021CU                0x4340
+#define DEVICEID_MRVL_8022CU                0x4341
+#define DEVICEID_MRVL_8061CU                0x4342
+#define DEVICEID_MRVL_8062CU                0x4343
+#define DEVICEID_MRVL_8021X                 0x4344
+#define DEVICEID_MRVL_8022X                 0x4345
+#define DEVICEID_MRVL_8061X                 0x4346
+#define DEVICEID_MRVL_8062X                 0x4347
+#define DEVICEID_MRVL_8035                  0x4350
+#define DEVICEID_MRVL_8036                  0x4351
+#define DEVICEID_MRVL_8038                  0x4352
+#define DEVICEID_MRVL_8039                  0x4353
+#define DEVICEID_MRVL_8040                  0x4354
+#define DEVICEID_MRVL_8040T                 0x4355
+#define DEVICEID_MRVL_8042                  0x4357
+#define DEVICEID_MRVL_8048                  0x435A
+#define DEVICEID_MRVL_4360                  0x4360
+#define DEVICEID_MRVL_4361                  0x4361
+#define DEVICEID_MRVL_4362                  0x4362
+#define DEVICEID_MRVL_4363                  0x4363
+#define DEVICEID_MRVL_4364                  0x4364
+#define DEVICEID_MRVL_4365                  0x4365
+#define DEVICEID_MRVL_436A                  0x436A
+#define DEVICEID_MRVL_436B                  0x436B
+#define DEVICEID_MRVL_436C                  0x436C
+#define DEVICEID_MRVL_4380                  0x4380
+#define DEVICEID_MRVL_4381                  0x4381
+
+/*
+ * D-Link gigabit ethernet device ID
+ */
+#define DEVICEID_DLINK_DGE550SX             0x4001
+#define DEVICEID_DLINK_DGE560SX             0x4002
+#define DEVICEID_DLINK_DGE560T              0x4b00
+
+#define BIT_31                              ((UINT32)1 << 31)
+#define BIT_30                              (1 << 30)
+#define BIT_29                              (1 << 29)
+#define BIT_28                              (1 << 28)
+#define BIT_27                              (1 << 27)
+#define BIT_26                              (1 << 26)
+#define BIT_25                              (1 << 25)
+#define BIT_24                              (1 << 24)
+#define BIT_23                              (1 << 23)
+#define BIT_22                              (1 << 22)
+#define BIT_21                              (1 << 21)
+#define BIT_20                              (1 << 20)
+#define BIT_19                              (1 << 19)
+#define BIT_18                              (1 << 18)
+#define BIT_17                              (1 << 17)
+#define BIT_16                              (1 << 16)
+#define BIT_15                              (1 << 15)
+#define BIT_14                              (1 << 14)
+#define BIT_13                              (1 << 13)
+#define BIT_12                              (1 << 12)
+#define BIT_11                              (1 << 11)
+#define BIT_10                              (1 << 10)
+#define BIT_9                               (1 << 9)
+#define BIT_8                               (1 << 8)
+#define BIT_7                               (1 << 7)
+#define BIT_6                               (1 << 6)
+#define BIT_5                               (1 << 5)
+#define BIT_4                               (1 << 4)
+#define BIT_3                               (1 << 3)
+#define BIT_2                               (1 << 2)
+#define BIT_1                               (1 << 1)
+#define BIT_0                               (1 << 0)
+
+#define SHIFT31(x)                          ((x) << 31)
+#define SHIFT30(x)                          ((x) << 30)
+#define SHIFT29(x)                          ((x) << 29)
+#define SHIFT28(x)                          ((x) << 28)
+#define SHIFT27(x)                          ((x) << 27)
+#define SHIFT26(x)                          ((x) << 26)
+#define SHIFT25(x)                          ((x) << 25)
+#define SHIFT24(x)                          ((x) << 24)
+#define SHIFT23(x)                          ((x) << 23)
+#define SHIFT22(x)                          ((x) << 22)
+#define SHIFT21(x)                          ((x) << 21)
+#define SHIFT20(x)                          ((x) << 20)
+#define SHIFT19(x)                          ((x) << 19)
+#define SHIFT18(x)                          ((x) << 18)
+#define SHIFT17(x)                          ((x) << 17)
+#define SHIFT16(x)                          ((x) << 16)
+#define SHIFT15(x)                          ((x) << 15)
+#define SHIFT14(x)                          ((x) << 14)
+#define SHIFT13(x)                          ((x) << 13)
+#define SHIFT12(x)                          ((x) << 12)
+#define SHIFT11(x)                          ((x) << 11)
+#define SHIFT10(x)                          ((x) << 10)
+#define SHIFT9(x)                           ((x) << 9)
+#define SHIFT8(x)                           ((x) << 8)
+#define SHIFT7(x)                           ((x) << 7)
+#define SHIFT6(x)                           ((x) << 6)
+#define SHIFT5(x)                           ((x) << 5)
+#define SHIFT4(x)                           ((x) << 4)
+#define SHIFT3(x)                           ((x) << 3)
+#define SHIFT2(x)                           ((x) << 2)
+#define SHIFT1(x)                           ((x) << 1)
+#define SHIFT0(x)                           ((x) << 0)
+
+/*
+ * PCI Configuration Space header
+ */
+#define PCI_BASE_1ST                        0x10  /* 32 bit 1st Base address */
+#define PCI_BASE_2ND                        0x14  /* 32 bit 2nd Base address */
+#define PCI_OUR_REG_1                       0x40  /* 32 bit Our Register 1 */
+#define PCI_OUR_REG_2                       0x44  /* 32 bit Our Register 2 */
+#define PCI_OUR_STATUS                      0x7c  /* 32 bit Adapter Status Register */
+#define PCI_OUR_REG_3                       0x80  /* 32 bit Our Register 3 */
+#define PCI_OUR_REG_4                       0x84  /* 32 bit Our Register 4 */
+#define PCI_OUR_REG_5                       0x88  /* 32 bit Our Register 5 */
+#define PCI_CFG_REG_0                       0x90  /* 32 bit Config Register 0 */
+#define PCI_CFG_REG_1                       0x94  /* 32 bit Config Register 1 */
+
+/* PCI Express Capability */
+#define PEX_CAP_ID                          0xe0  /*  8 bit PEX Capability ID */
+#define PEX_NITEM                           0xe1  /*  8 bit PEX Next Item Pointer */
+#define PEX_CAP_REG                         0xe2  /* 16 bit PEX Capability Register */
+#define PEX_DEV_CAP                         0xe4  /* 32 bit PEX Device Capabilities */
+#define PEX_DEV_CTRL                        0xe8  /* 16 bit PEX Device Control */
+#define PEX_DEV_STAT                        0xea  /* 16 bit PEX Device Status */
+#define PEX_LNK_CAP                         0xec  /* 32 bit PEX Link Capabilities */
+#define PEX_LNK_CTRL                        0xf0  /* 16 bit PEX Link Control */
+#define PEX_LNK_STAT                        0xf2  /* 16 bit PEX Link Status */
+
+/* PCI Express Extended Capabilities */
+#define PEX_ADV_ERR_REP                     0x100  /* 32 bit PEX Advanced Error Reporting */
+#define PEX_UNC_ERR_STAT                    0x104  /* 32 bit PEX Uncorr. Errors Status */
+#define PEX_UNC_ERR_MASK                    0x108  /* 32 bit PEX Uncorr. Errors Mask */
+#define PEX_UNC_ERR_SEV                     0x10c  /* 32 bit PEX Uncorr. Errors Severity */
+#define PEX_COR_ERR_STAT                    0x110  /* 32 bit PEX Correc. Errors Status */
+#define PEX_COR_ERR_MASK                    0x114  /* 32 bit PEX Correc. Errors Mask */
+#define PEX_ADV_ERR_CAP_C                   0x118  /* 32 bit PEX Advanced Error Cap./Ctrl */
+#define PEX_HEADER_LOG                      0x11c  /* 4x32 bit PEX Header Log Register */
+
+/*  PCI_OUR_REG_1  32 bit  Our Register 1 */
+#define PCI_Y2_PIG_ENA                      BIT_31  /* Enable Plug-in-Go (YUKON-2) */
+#define PCI_Y2_DLL_DIS                      BIT_30  /* Disable PCI DLL (YUKON-2) */
+#define PCI_Y2_PHY2_COMA                    BIT_29  /* Set PHY 2 to Coma Mode (YUKON-2) */
+#define PCI_Y2_PHY1_COMA                    BIT_28  /* Set PHY 1 to Coma Mode (YUKON-2) */
+#define PCI_Y2_PHY2_POWD                    BIT_27  /* Set PHY 2 to Power Down (YUKON-2) */
+#define PCI_Y2_PHY1_POWD                    BIT_26  /* Set PHY 1 to Power Down (YUKON-2) */
+#define PCI_DIS_BOOT                        BIT_24  /* Disable BOOT via ROM */
+#define PCI_EN_IO                           BIT_23  /* Mapping to I/O space */
+#define PCI_EN_FPROM                        BIT_22  /* Enable FLASH mapping to memory */
+/* 1 = Map Flash to memory */
+/* 0 = Disable addr. dec */
+#define PCI_PAGESIZE                        (3L<<20)/* Bit 21..20:  FLASH Page Size  */
+#define PCI_PAGE_16                         (0L<<20)/*    16 k pages  */
+#define PCI_PAGE_32K                        (1L<<20)/*    32 k pages  */
+#define PCI_PAGE_64K                        (2L<<20)/*    64 k pages  */
+#define PCI_PAGE_128K                       (3L<<20)/*    128 k pages  */
+#define PCI_PAGEREG                         (7L<<16)/* Bit 18..16:  Page Register  */
+#define PCI_PEX_LEGNAT                      BIT_15  /* PEX PM legacy/native mode (YUKON-2) */
+#define PCI_FORCE_BE                        BIT_14  /* Assert all BEs on MR */
+#define PCI_DIS_MRL                         BIT_13  /* Disable Mem Read Line */
+#define PCI_DIS_MRM                         BIT_12  /* Disable Mem Read Multiple */
+#define PCI_DIS_MWI                         BIT_11  /* Disable Mem Write & Invalidate */
+#define PCI_DISC_CLS                        BIT_10  /* Disc: cacheLsz bound */
+#define PCI_BURST_DIS                       BIT_9  /* Burst Disable */
+#define PCI_DIS_PCI_CLK                     BIT_8  /* Disable PCI clock driving */
+#define PCI_SKEW_DAS                        (0xfL<<4)/* Bit  7.. 4:  Skew Ctrl, DAS Ext */
+#define PCI_SKEW_BASE                       0xfL  /* Bit  3.. 0:  Skew Ctrl, Base  */
+#define PCI_CLS_OPT                         BIT_3  /* Cache Line Size opt. PCI-X (YUKON-2) */
+
+/*  PCI_OUR_REG_2  32 bit  Our Register 2 */
+#define PCI_VPD_WR_THR                      (0xff<<24)  /* Bit 31..24:  VPD Write Threshold */
+#define PCI_DEV_SEL                         (0x7f<<17)  /* Bit 23..17:  EEPROM Device Select */
+#define PCI_VPD_ROM_SZ                      (0x07<<14)  /* Bit 16..14:  VPD ROM Size  */
+/* Bit 13..12:  reserved  */
+#define PCI_PATCH_DIR                       (0x0f<<8)  /* Bit 11.. 8:  Ext Patches dir 3..0 */
+#define PCI_PATCH_DIR_3                     BIT_11
+#define PCI_PATCH_DIR_2                     BIT_10
+#define PCI_PATCH_DIR_1                     BIT_9
+#define PCI_PATCH_DIR_0                     BIT_8
+#define PCI_EXT_PATCHS                      (0x0f<<4)  /* Bit  7.. 4:  Extended Patches 3..0 */
+#define PCI_EXT_PATCH_3                     BIT_7
+#define PCI_EXT_PATCH_2                     BIT_6
+#define PCI_EXT_PATCH_1                     BIT_5
+#define PCI_EXT_PATCH_0                     BIT_4
+#define PCI_EN_DUMMY_RD                     BIT_3    /* Enable Dummy Read */
+#define PCI_REV_DESC                        BIT_2    /* Reverse Desc. Bytes */
+#define PCI_USEDATA64                       BIT_0    /* Use 64Bit Data bus ext */
+
+/* PCI_OUR_STATUS  32 bit  Adapter Status Register (Yukon-2) */
+#define PCI_OS_PCI64B                       BIT_31    /* Conventional PCI 64 bits Bus */
+#define PCI_OS_PCIX                         BIT_30    /* PCI-X Bus */
+#define PCI_OS_MODE_MSK                     (3<<28)    /* Bit 29..28:  PCI-X Bus Mode Mask */
+#define PCI_OS_PCI66M                       BIT_27    /* PCI 66 MHz Bus */
+#define PCI_OS_PCI_X                        BIT_26    /* PCI/PCI-X Bus (0 = PEX) */
+#define PCI_OS_DLLE_MSK                     (3<<24)    /* Bit 25..24:  DLL Status Indication */
+#define PCI_OS_DLLR_MSK                     (0x0f<<20)  /* Bit 23..20:  DLL Row Counters Values */
+#define PCI_OS_DLLC_MSK                     (0x0f<<16)  /* Bit 19..16:  DLL Col. Counters Values */
+
+#define PCI_OS_SPEED(val)                   ((val & PCI_OS_MODE_MSK) >> 28)  /* PCI-X Speed */
+/* possible values for the speed field of the register */
+#define PCI_OS_SPD_PCI                      0  /* PCI Conventional Bus */
+#define PCI_OS_SPD_X66                      1  /* PCI-X 66MHz Bus */
+#define PCI_OS_SPD_X100                     2  /* PCI-X 100MHz Bus */
+#define PCI_OS_SPD_X133                     3  /* PCI-X 133MHz Bus */
+
+/* PCI_OUR_REG_4  32 bit  Our Register 4 (Yukon-ECU only) */
+#define  PCI_TIMER_VALUE_MSK                (0xff<<16)  /* Bit 23..16:  Timer Value Mask */
+#define  PCI_FORCE_ASPM_REQUEST             BIT_15  /* Force ASPM Request (A1 only) */
+#define  PCI_ASPM_GPHY_LINK_DOWN            BIT_14  /* GPHY Link Down (A1 only) */
+#define  PCI_ASPM_INT_FIFO_EMPTY            BIT_13  /* Internal FIFO Empty (A1 only) */
+#define  PCI_ASPM_CLKRUN_REQUEST            BIT_12  /* CLKRUN Request (A1 only) */
+#define  PCI_ASPM_FORCE_CLKREQ_ENA          BIT_4  /* Force CLKREQ Enable (A1b only) */
+#define  PCI_ASPM_CLKREQ_PAD_CTL            BIT_3  /* CLKREQ PAD Control (A1 only) */
+#define  PCI_ASPM_A1_MODE_SELECT            BIT_2  /* A1 Mode Select (A1 only) */
+#define  PCI_CLK_GATE_PEX_UNIT_ENA          BIT_1  /* Enable Gate PEX Unit Clock */
+#define  PCI_CLK_GATE_ROOT_COR_ENA          BIT_0  /* Enable Gate Root Core Clock */
+
+/* PCI_OUR_REG_5  32 bit  Our Register 5 (Yukon-ECU only) */
+/* Bit 31..27: for A3 & later */
+#define  PCI_CTL_DIV_CORE_CLK_ENA           BIT_31  /* Divide Core Clock Enable */
+#define  PCI_CTL_SRESET_VMAIN_AV            BIT_30  /* Soft Reset for Vmain_av De-Glitch */
+#define  PCI_CTL_BYPASS_VMAIN_AV            BIT_29  /* Bypass En. for Vmain_av De-Glitch */
+#define  PCI_CTL_TIM_VMAIN_AV1              BIT_28  /* Bit 28..27: Timer Vmain_av Mask */
+#define  PCI_CTL_TIM_VMAIN_AV0              BIT_27  /* Bit 28..27: Timer Vmain_av Mask */
+#define  PCI_CTL_TIM_VMAIN_AV_MSK           (BIT_28 | BIT_27)
+/* Bit 26..16: Release Clock on Event */
+#define  PCI_REL_PCIE_RST_DE_ASS            BIT_26  /* PCIe Reset De-Asserted */
+#define  PCI_REL_GPHY_REC_PACKET            BIT_25  /* GPHY Received Packet */
+#define  PCI_REL_INT_FIFO_N_EMPTY           BIT_24  /* Internal FIFO Not Empty */
+#define  PCI_REL_MAIN_PWR_AVAIL             BIT_23  /* Main Power Available */
+#define  PCI_REL_CLKRUN_REQ_REL             BIT_22  /* CLKRUN Request Release */
+#define  PCI_REL_PCIE_RESET_ASS             BIT_21  /* PCIe Reset Asserted */
+#define  PCI_REL_PME_ASSERTED               BIT_20  /* PME Asserted */
+#define  PCI_REL_PCIE_EXIT_L1_ST            BIT_19  /* PCIe Exit L1 State */
+#define  PCI_REL_LOADER_NOT_FIN             BIT_18  /* EPROM Loader Not Finished */
+#define  PCI_REL_PCIE_RX_EX_IDLE            BIT_17  /* PCIe Rx Exit Electrical Idle State */
+#define  PCI_REL_GPHY_LINK_UP               BIT_16  /* GPHY Link Up */
+/* Bit 10.. 0: Mask for Gate Clock */
+#define  PCI_GAT_PCIE_RST_ASSERTED          BIT_10  /* PCIe Reset Asserted */
+#define  PCI_GAT_GPHY_N_REC_PACKET          BIT_9  /* GPHY Not Received Packet */
+#define  PCI_GAT_INT_FIFO_EMPTY             BIT_8  /* Internal FIFO Empty */
+#define  PCI_GAT_MAIN_PWR_N_AVAIL           BIT_7  /* Main Power Not Available */
+#define  PCI_GAT_CLKRUN_REQ_REL             BIT_6  /* CLKRUN Not Requested */
+#define  PCI_GAT_PCIE_RESET_ASS             BIT_5  /* PCIe Reset Asserted */
+#define  PCI_GAT_PME_DE_ASSERTED            BIT_4  /* PME De-Asserted */
+#define  PCI_GAT_PCIE_ENTER_L1_ST           BIT_3  /* PCIe Enter L1 State */
+#define  PCI_GAT_LOADER_FINISHED            BIT_2  /* EPROM Loader Finished */
+#define  PCI_GAT_PCIE_RX_EL_IDLE            BIT_1  /* PCIe Rx Electrical Idle State */
+#define  PCI_GAT_GPHY_LINK_DOWN             BIT_0  /* GPHY Link Down */
+
+/* PCI_CFG_REG_1  32 bit  Config Register 1 */
+#define  PCI_CF1_DIS_REL_EVT_RST            BIT_24  /* Dis. Rel. Event during PCIE reset */
+/* Bit 23..21: Release Clock on Event */
+#define  PCI_CF1_REL_LDR_NOT_FIN            BIT_23  /* EEPROM Loader Not Finished */
+#define  PCI_CF1_REL_VMAIN_AVLBL            BIT_22  /* Vmain available */
+#define  PCI_CF1_REL_PCIE_RESET             BIT_21  /* PCI-E reset */
+/* Bit 20..18: Gate Clock       on Event */
+#define  PCI_CF1_GAT_LDR_NOT_FIN            BIT_20  /* EEPROM Loader Finished */
+#define  PCI_CF1_GAT_PCIE_RX_IDLE           BIT_19  /* PCI-E Rx Electrical idle */
+#define  PCI_CF1_GAT_PCIE_RESET             BIT_18  /* PCI-E Reset */
+#define  PCI_CF1_PRST_PHY_CLKREQ            BIT_17  /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
+#define  PCI_CF1_PCIE_RST_CLKREQ            BIT_16  /* Enable PCI-E rst generate CLKREQ */
+
+#define  PCI_CF1_ENA_CFG_LDR_DONE           BIT_8  /* Enable core level Config loader done */
+#define  PCI_CF1_ENA_TXBMU_RD_IDLE          BIT_1  /* Enable TX BMU Read  IDLE for ASPM */
+#define  PCI_CF1_ENA_TXBMU_WR_IDLE          BIT_0  /* Enable TX BMU Write IDLE for ASPM */
+
+/* PEX_DEV_CTRL  16 bit  PEX Device Control (Yukon-2) */
+#define PEX_DC_MAX_RRS_MSK                  (7<<12)  /* Bit 14..12:  Max. Read Request Size */
+#define PEX_DC_EN_NO_SNOOP                  BIT_11  /* Enable No Snoop */
+#define PEX_DC_EN_AUX_POW                   BIT_10  /* Enable AUX Power */
+#define PEX_DC_EN_PHANTOM                   BIT_9  /* Enable Phantom Functions */
+#define PEX_DC_EN_EXT_TAG                   BIT_8  /* Enable Extended Tag Field */
+#define PEX_DC_MAX_PLS_MSK                  (7<<5)  /* Bit  7.. 5:  Max. Payload Size Mask */
+#define PEX_DC_EN_REL_ORD                   BIT_4  /* Enable Relaxed Ordering */
+#define PEX_DC_EN_UNS_RQ_RP                 BIT_3  /* Enable Unsupported Request Reporting */
+#define PEX_DC_EN_FAT_ER_RP                 BIT_2  /* Enable Fatal Error Reporting */
+#define PEX_DC_EN_NFA_ER_RP                 BIT_1  /* Enable Non-Fatal Error Reporting */
+#define PEX_DC_EN_COR_ER_RP                 BIT_0  /* Enable Correctable Error Reporting */
+
+#define PEX_DC_MAX_RD_RQ_SIZE(x)            (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
+
+/* PEX_LNK_STAT  16 bit  PEX Link Status (Yukon-2) */
+#define PEX_LS_SLOT_CLK_CFG                 BIT_12  /* Slot Clock Config */
+#define PEX_LS_LINK_TRAIN                   BIT_11  /* Link Training */
+#define PEX_LS_TRAIN_ERROR                  BIT_10  /* Training Error */
+#define PEX_LS_LINK_WI_MSK                  (0x3f<<4) /* Bit  9.. 4: Neg. Link Width Mask */
+#define PEX_LS_LINK_SP_MSK                  0x0f  /* Bit  3.. 0:  Link Speed Mask */
+
+/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
+#define PEX_UNSUP_REQ                       BIT_20    /* Unsupported Request Error */
+#define PEX_MALFOR_TLP                      BIT_18    /* Malformed TLP */
+#define  PEX_RX_OV                          BIT_17    /* Receiver Overflow (not supported) */
+#define PEX_UNEXP_COMP                      BIT_16    /* Unexpected Completion */
+#define PEX_COMP_TO                         BIT_14    /* Completion Timeout */
+#define PEX_FLOW_CTRL_P                     BIT_13    /* Flow Control Protocol Error */
+#define PEX_POIS_TLP                        BIT_12    /* Poisoned TLP */
+#define PEX_DATA_LINK_P                     BIT_4    /* Data Link Protocol Error */
+
+#define PEX_FATAL_ERRORS                    (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
+
+/*  Control Register File (Address Map) */
+
+/*
+ *  Bank 0
+ */
+#define B0_RAP                              0x0000  /*  8 bit Register Address Port */
+#define B0_CTST                             0x0004  /* 16 bit Control/Status register */
+#define B0_LED                              0x0006  /*  8 Bit LED register */
+#define B0_POWER_CTRL                       0x0007  /*  8 Bit Power Control reg (YUKON only) */
+#define B0_ISRC                             0x0008  /* 32 bit Interrupt Source Register */
+#define B0_IMSK                             0x000c  /* 32 bit Interrupt Mask Register */
+#define B0_HWE_ISRC                         0x0010  /* 32 bit HW Error Interrupt Src Reg */
+#define B0_HWE_IMSK                         0x0014  /* 32 bit HW Error Interrupt Mask Reg */
+#define B0_SP_ISRC                          0x0018  /* 32 bit Special Interrupt Source Reg 1 */
+
+/* Special ISR registers (Yukon-2 only) */
+#define B0_Y2_SP_ISRC2                      0x001c  /* 32 bit Special Interrupt Source Reg 2 */
+#define B0_Y2_SP_ISRC3                      0x0020  /* 32 bit Special Interrupt Source Reg 3 */
+#define B0_Y2_SP_EISR                       0x0024  /* 32 bit Enter ISR Reg */
+#define B0_Y2_SP_LISR                       0x0028  /* 32 bit Leave ISR Reg */
+#define B0_Y2_SP_ICR                        0x002c  /* 32 bit Interrupt Control Reg */
+
+/*
+ *  Bank 1
+ *  - completely empty (this is the RAP Block window)
+ *  Note: if RAP = 1 this page is reserved
+ */
+
+/*
+ *  Bank 2
+ */
+/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
+#define B2_MAC_1                            0x0100  /* NA reg MAC Address 1 */
+#define B2_MAC_2                            0x0108  /* NA reg MAC Address 2 */
+#define B2_MAC_3                            0x0110  /* NA reg MAC Address 3 */
+#define B2_CONN_TYP                         0x0118  /*  8 bit Connector type */
+#define B2_PMD_TYP                          0x0119  /*  8 bit PMD type */
+#define B2_MAC_CFG                          0x011a  /*  8 bit MAC Configuration / Chip Revision */
+#define B2_CHIP_ID                          0x011b  /*  8 bit Chip Identification Number */
+#define B2_E_0                              0x011c  /*  8 bit EPROM Byte 0 (ext. SRAM size */
+#define B2_Y2_CLK_GATE                      0x011d  /*  8 bit Clock Gating (Yukon-2) */
+#define B2_Y2_HW_RES                        0x011e  /*  8 bit HW Resources (Yukon-2) */
+#define B2_E_3                              0x011f  /*  8 bit EPROM Byte 3 */
+#define B2_Y2_CLK_CTRL                      0x0120  /* 32 bit Core Clock Frequency Control */
+#define B2_TI_INI                           0x0130  /* 32 bit Timer Init Value */
+#define B2_TI_VAL                           0x0134  /* 32 bit Timer Value */
+#define B2_TI_CTRL                          0x0138  /*  8 bit Timer Control */
+#define B2_TI_TEST                          0x0139  /*  8 Bit Timer Test */
+#define B2_IRQM_INI                         0x0140  /* 32 bit IRQ Moderation Timer Init Reg.*/
+#define B2_IRQM_VAL                         0x0144  /* 32 bit IRQ Moderation Timer Value */
+#define B2_IRQM_CTRL                        0x0148  /*  8 bit IRQ Moderation Timer Control */
+#define B2_IRQM_TEST                        0x0149  /*  8 bit IRQ Moderation Timer Test */
+#define B2_IRQM_MSK                         0x014c  /* 32 bit IRQ Moderation Mask */
+#define B2_IRQM_HWE_MSK                     0x0150  /* 32 bit IRQ Moderation HW Error Mask */
+#define B2_TST_CTRL1                        0x0158  /*  8 bit Test Control Register 1 */
+#define B2_TST_CTRL2                        0x0159  /*  8 bit Test Control Register 2 */
+#define B2_GP_IO                            0x015c  /* 32 bit General Purpose I/O Register */
+#define B2_I2C_CTRL                         0x0160  /* 32 bit I2C HW Control Register */
+#define B2_I2C_DATA                         0x0164  /* 32 bit I2C HW Data Register */
+#define B2_I2C_IRQ                          0x0168  /* 32 bit I2C HW IRQ Register */
+#define B2_I2C_SW                           0x016c  /* 32 bit I2C SW Port Register */
+
+#define Y2_PEX_PHY_DATA                     0x0170  /* 16 bit PEX PHY Data Register */
+#define Y2_PEX_PHY_ADDR                     0x0172  /* 16 bit PEX PHY Address Register */
+
+/*
+ *  Bank 3
+ */
+/* RAM Random Registers */
+#define B3_RAM_ADDR                         0x0180  /* 32 bit RAM Address, to read or write */
+#define B3_RAM_DATA_LO                      0x0184  /* 32 bit RAM Data Word (low dWord) */
+#define B3_RAM_DATA_HI                      0x0188  /* 32 bit RAM Data Word (high dWord) */
+
+#define SELECT_RAM_BUFFER(rb, addr)         (addr | (rb << 6))  /* Yukon-2 only */
+
+/* RAM Interface Registers */
+/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
+/*
+ * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
+ * not usable in SW. Please notice these are NOT real timeouts, these are
+ * the number of qWords transferred continuously.
+ */
+#define B3_RI_WTO_R1                        0x0190  /*  8 bit WR Timeout Queue R1 (TO0) */
+#define B3_RI_WTO_XA1                       0x0191  /*  8 bit WR Timeout Queue XA1 (TO1) */
+#define B3_RI_WTO_XS1                       0x0192  /*  8 bit WR Timeout Queue XS1 (TO2) */
+#define B3_RI_RTO_R1                        0x0193  /*  8 bit RD Timeout Queue R1 (TO3) */
+#define B3_RI_RTO_XA1                       0x0194  /*  8 bit RD Timeout Queue XA1 (TO4) */
+#define B3_RI_RTO_XS1                       0x0195  /*  8 bit RD Timeout Queue XS1 (TO5) */
+#define B3_RI_WTO_R2                        0x0196  /*  8 bit WR Timeout Queue R2 (TO6) */
+#define B3_RI_WTO_XA2                       0x0197  /*  8 bit WR Timeout Queue XA2 (TO7) */
+#define B3_RI_WTO_XS2                       0x0198  /*  8 bit WR Timeout Queue XS2 (TO8) */
+#define B3_RI_RTO_R2                        0x0199  /*  8 bit RD Timeout Queue R2 (TO9) */
+#define B3_RI_RTO_XA2                       0x019a  /*  8 bit RD Timeout Queue XA2 (TO10)*/
+#define B3_RI_RTO_XS2                       0x019b  /*  8 bit RD Timeout Queue XS2 (TO11)*/
+#define B3_RI_TO_VAL                        0x019c  /*  8 bit Current Timeout Count Val */
+#define B3_RI_CTRL                          0x01a0  /* 16 bit RAM Interface Control Register */
+#define B3_RI_TEST                          0x01a2  /*  8 bit RAM Interface Test Register */
+
+/*
+ *  Bank 4 - 5
+ */
+/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
+#define TXA_ITI_INI                         0x0200  /* 32 bit Tx Arb Interval Timer Init Val*/
+#define TXA_ITI_VAL                         0x0204  /* 32 bit Tx Arb Interval Timer Value */
+#define TXA_LIM_INI                         0x0208  /* 32 bit Tx Arb Limit Counter Init Val */
+#define TXA_LIM_VAL                         0x020c  /* 32 bit Tx Arb Limit Counter Value */
+#define TXA_CTRL                            0x0210  /*  8 bit Tx Arbiter Control Register */
+#define TXA_TEST                            0x0211  /*  8 bit Tx Arbiter Test Register */
+#define TXA_STAT                            0x0212  /*  8 bit Tx Arbiter Status Register */
+
+#define MR_ADDR(Mac, Offs)                  (((Mac) << 7) + (Offs))
+
+/* RSS key registers for Yukon-2 Family */
+#define B4_RSS_KEY                          0x0220  /* 4x32 bit RSS Key register (Yukon-2) */
+/* RSS key register offsets */
+#define KEY_IDX_0                           0      /* offset for location of KEY 0 */
+#define KEY_IDX_1                           4      /* offset for location of KEY 1 */
+#define KEY_IDX_2                           8      /* offset for location of KEY 2 */
+#define KEY_IDX_3                           12    /* offset for location of KEY 3 */
+/* 0x0280 - 0x0292:  MAC 2 */
+#define RSS_KEY_ADDR(Port, KeyIndex)        ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
+
+/*
+ *  Bank 8 - 15
+ */
+/* Receive and Transmit Queue Registers, use Q_ADDR() to access */
+#define B8_Q_REGS                           0x0400
+
+/* Queue Register Offsets, use Q_ADDR() to access */
+#define Q_D                                 0x00  /* 8*32  bit Current Descriptor */
+#define Q_DA_L                              0x20  /* 32 bit Current Descriptor Address Low dWord */
+#define Q_DONE                              0x24  /* 16 bit Done Index */
+#define Q_AC_L                              0x28  /* 32 bit Current Address Counter Low dWord */
+#define Q_AC_H                              0x2c  /* 32 bit Current Address Counter High dWord */
+#define Q_BC                                0x30  /* 32 bit Current Byte Counter */
+#define Q_CSR                               0x34  /* 32 bit BMU Control/Status Register */
+#define Q_F                                 0x38  /* 32 bit Flag Register */
+#define Q_T1                                0x3c  /* 32 bit Test Register 1 */
+#define Q_T1_TR                             0x3c  /*  8 bit Test Register 1 Transfer SM */
+#define Q_T1_WR                             0x3d  /*  8 bit Test Register 1 Write Descriptor SM */
+#define Q_T1_RD                             0x3e  /*  8 bit Test Register 1 Read Descriptor SM */
+#define Q_T1_SV                             0x3f  /*  8 bit Test Register 1 Supervisor SM */
+#define Q_WM                                0x40  /* 16 bit FIFO Watermark */
+#define Q_AL                                0x42  /*  8 bit FIFO Alignment */
+#define Q_RSP                               0x44  /* 16 bit FIFO Read Shadow Pointer */
+#define Q_RSL                               0x46  /*  8 bit FIFO Read Shadow Level */
+#define Q_RP                                0x48  /*  8 bit FIFO Read Pointer */
+#define Q_RL                                0x4a  /*  8 bit FIFO Read Level */
+#define Q_WP                                0x4c  /*  8 bit FIFO Write Pointer */
+#define Q_WSP                               0x4d  /*  8 bit FIFO Write Shadow Pointer */
+#define Q_WL                                0x4e  /*  8 bit FIFO Write Level */
+#define Q_WSL                               0x4f  /*  8 bit FIFO Write Shadow Level */
+
+#define Q_ADDR(Queue, Offs)                 (B8_Q_REGS + (Queue) + (Offs))
+
+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */
+#define Y2_B8_PREF_REGS                     0x0450
+
+#define PREF_UNIT_CTRL_REG                  0x00  /* 32 bit Prefetch Control register */
+#define PREF_UNIT_LAST_IDX_REG              0x04  /* 16 bit Last Index */
+#define PREF_UNIT_ADDR_LOW_REG              0x08  /* 32 bit List start addr, low part */
+#define PREF_UNIT_ADDR_HI_REG               0x0c  /* 32 bit List start addr, high part*/
+#define PREF_UNIT_GET_IDX_REG               0x10  /* 16 bit Get Index */
+#define PREF_UNIT_PUT_IDX_REG               0x14  /* 16 bit Put Index */
+#define PREF_UNIT_FIFO_WP_REG               0x20  /*  8 bit FIFO write pointer */
+#define PREF_UNIT_FIFO_RP_REG               0x24  /*  8 bit FIFO read pointer */
+#define PREF_UNIT_FIFO_WM_REG               0x28  /*  8 bit FIFO watermark */
+#define PREF_UNIT_FIFO_LEV_REG              0x2c  /*  8 bit FIFO level */
+
+#define PREF_UNIT_MASK_IDX                  0x0fff
+
+#define Y2_PREF_Q_ADDR(Queue, Offs)         (Y2_B8_PREF_REGS + (Queue) + (Offs))
+
+/*
+ *  Bank 16 - 23
+ */
+/* RAM Buffer Registers */
+#define B16_RAM_REGS                        0x0800
+
+/* RAM Buffer Register Offsets, use RB_ADDR() to access */
+#define RB_START                            0x00  /* 32 bit RAM Buffer Start Address */
+#define RB_END                              0x04  /* 32 bit RAM Buffer End Address */
+#define RB_WP                               0x08  /* 32 bit RAM Buffer Write Pointer */
+#define RB_RP                               0x0c  /* 32 bit RAM Buffer Read Pointer */
+#define RB_RX_UTPP                          0x10  /* 32 bit Rx Upper Threshold, Pause Packet */
+#define RB_RX_LTPP                          0x14  /* 32 bit Rx Lower Threshold, Pause Packet */
+#define RB_RX_UTHP                          0x18  /* 32 bit Rx Upper Threshold, High Prio */
+#define RB_RX_LTHP                          0x1c  /* 32 bit Rx Lower Threshold, High Prio */
+#define RB_PC                               0x20  /* 32 bit RAM Buffer Packet Counter */
+#define RB_LEV                              0x24  /* 32 bit RAM Buffer Level Register */
+#define RB_CTRL                             0x28  /*  8 bit RAM Buffer Control Register */
+#define RB_TST1                             0x29  /*  8 bit RAM Buffer Test Register 1 */
+#define RB_TST2                             0x2a  /*  8 bit RAM Buffer Test Register 2 */
+
+/*
+ *  Bank 24
+ */
+/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
+#define RX_GMF_EA                           0x0c40  /* 32 bit Rx GMAC FIFO End Address */
+#define RX_GMF_AF_THR                       0x0c44  /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
+#define RX_GMF_CTRL_T                       0x0c48  /* 32 bit Rx GMAC FIFO Control/Test */
+#define RX_GMF_FL_MSK                       0x0c4c  /* 32 bit Rx GMAC FIFO Flush Mask */
+#define RX_GMF_FL_THR                       0x0c50  /* 32 bit Rx GMAC FIFO Flush Threshold */
+#define RX_GMF_TR_THR                       0x0c54  /* 32 bit Rx Truncation Threshold (Yukon-2) */
+#define  RX_GMF_UP_THR                      0x0c58  /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
+#define  RX_GMF_LP_THR                      0x0c5a  /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
+#define RX_GMF_VLAN                         0x0c5c  /* 32 bit Rx VLAN Type Register (Yukon-2) */
+#define RX_GMF_WP                           0x0c60  /* 32 bit Rx GMAC FIFO Write Pointer */
+#define RX_GMF_WLEV                         0x0c68  /* 32 bit Rx GMAC FIFO Write Level */
+#define RX_GMF_RP                           0x0c70  /* 32 bit Rx GMAC FIFO Read Pointer */
+#define RX_GMF_RLEV                         0x0c78  /* 32 bit Rx GMAC FIFO Read Level */
+
+/*
+ *  Bank 25
+ */
+/* 0x0c80 - 0x0cbf:  MAC 2 */
+/* 0x0cc0 - 0x0cff:  reserved */
+
+/*
+ *  Bank 26
+ */
+/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
+#define TX_GMF_EA                           0x0d40  /* 32 bit Tx GMAC FIFO End Address */
+#define TX_GMF_AE_THR                       0x0d44  /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
+#define TX_GMF_CTRL_T                       0x0d48  /* 32 bit Tx GMAC FIFO Control/Test */
+#define TX_GMF_VLAN                         0x0d5c  /* 32 bit Tx VLAN Type Register (Yukon-2) */
+#define TX_GMF_WP                           0x0d60  /* 32 bit Tx GMAC FIFO Write Pointer */
+#define TX_GMF_WSP                          0x0d64  /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
+#define TX_GMF_WLEV                         0x0d68  /* 32 bit Tx GMAC FIFO Write Level */
+#define TX_GMF_RP                           0x0d70  /* 32 bit Tx GMAC FIFO Read Pointer */
+#define TX_GMF_RSTP                         0x0d74  /* 32 bit Tx GMAC FIFO Restart Pointer */
+#define TX_GMF_RLEV                         0x0d78  /* 32 bit Tx GMAC FIFO Read Level */
+
+/*
+ *  Bank 27
+ */
+/* 0x0d80 - 0x0dbf:  MAC 2 */
+/* 0x0daa - 0x0dff:  reserved */
+
+/*
+ *  Bank 28
+ */
+/* Descriptor Poll Timer Registers */
+#define B28_DPT_INI                         0x0e00  /* 24 bit Descriptor Poll Timer Init Val */
+#define B28_DPT_VAL                         0x0e04  /* 24 bit Descriptor Poll Timer Curr Val */
+#define B28_DPT_CTRL                        0x0e08  /*  8 bit Descriptor Poll Timer Ctrl Reg */
+#define B28_DPT_TST                         0x0e0a  /*  8 bit Descriptor Poll Timer Test Reg */
+/* Time Stamp Timer Registers (YUKON only) */
+#define GMAC_TI_ST_VAL                      0x0e14  /* 32 bit Time Stamp Timer Curr Val */
+#define GMAC_TI_ST_CTRL                     0x0e18  /*  8 bit Time Stamp Timer Ctrl Reg */
+#define GMAC_TI_ST_TST                      0x0e1a  /*  8 bit Time Stamp Timer Test Reg */
+/* Polling Unit Registers (Yukon-2 only) */
+#define POLL_CTRL                           0x0e20  /* 32 bit Polling Unit Control Reg */
+#define POLL_LAST_IDX                       0x0e24  /* 16 bit Polling Unit List Last Index */
+#define POLL_LIST_ADDR_LO                   0x0e28  /* 32 bit Poll. List Start Addr (low) */
+#define POLL_LIST_ADDR_HI                   0x0e2c  /* 32 bit Poll. List Start Addr (high) */
+/* ASF Subsystem Registers (Yukon-2 only) */
+#define B28_Y2_SMB_CONFIG                   0x0e40  /* 32 bit ASF SMBus Config Register */
+#define B28_Y2_SMB_CSD_REG                  0x0e44  /* 32 bit ASF SMB Control/Status/Data */
+#define B28_Y2_ASF_IRQ_V_BASE               0x0e60  /* 32 bit ASF IRQ Vector Base */
+#define B28_Y2_ASF_STAT_CMD                 0x0e68  /* 32 bit ASF Status and Command Reg */
+#define B28_Y2_ASF_HCU_CCSR                 0x0e68  /* 32 bit ASF HCU CCSR (Yukon EX) */
+#define B28_Y2_ASF_HOST_COM                 0x0e6c  /* 32 bit ASF Host Communication Reg */
+#define B28_Y2_DATA_REG_1                   0x0e70  /* 32 bit ASF/Host Data Register 1 */
+#define B28_Y2_DATA_REG_2                   0x0e74  /* 32 bit ASF/Host Data Register 2 */
+#define B28_Y2_DATA_REG_3                   0x0e78  /* 32 bit ASF/Host Data Register 3 */
+#define B28_Y2_DATA_REG_4                   0x0e7c  /* 32 bit ASF/Host Data Register 4 */
+
+/*
+ *  Bank 29
+ */
+
+/* Status BMU Registers (Yukon-2 only)*/
+#define STAT_CTRL                           0x0e80  /* 32 bit Status BMU Control Reg */
+#define STAT_LAST_IDX                       0x0e84  /* 16 bit Status BMU Last Index */
+#define STAT_LIST_ADDR_LO                   0x0e88  /* 32 bit Status List Start Addr (low) */
+#define STAT_LIST_ADDR_HI                   0x0e8c  /* 32 bit Status List Start Addr (high) */
+#define STAT_TXA1_RIDX                      0x0e90  /* 16 bit Status TxA1 Report Index Reg */
+#define STAT_TXS1_RIDX                      0x0e92  /* 16 bit Status TxS1 Report Index Reg */
+#define STAT_TXA2_RIDX                      0x0e94  /* 16 bit Status TxA2 Report Index Reg */
+#define STAT_TXS2_RIDX                      0x0e96  /* 16 bit Status TxS2 Report Index Reg */
+#define STAT_TX_IDX_TH                      0x0e98  /* 16 bit Status Tx Index Threshold Reg */
+#define STAT_PUT_IDX                        0x0e9c  /* 16 bit Status Put Index Reg */
+/* FIFO Control/Status Registers (Yukon-2 only)*/
+#define STAT_FIFO_WP                        0x0ea0  /*  8 bit Status FIFO Write Pointer Reg */
+#define STAT_FIFO_RP                        0x0ea4  /*  8 bit Status FIFO Read Pointer Reg */
+#define STAT_FIFO_RSP                       0x0ea6  /*  8 bit Status FIFO Read Shadow Ptr */
+#define STAT_FIFO_LEVEL                     0x0ea8  /*  8 bit Status FIFO Level Reg */
+#define STAT_FIFO_SHLVL                     0x0eaa  /*  8 bit Status FIFO Shadow Level Reg */
+#define STAT_FIFO_WM                        0x0eac  /*  8 bit Status FIFO Watermark Reg */
+#define STAT_FIFO_ISR_WM                    0x0ead  /*  8 bit Status FIFO ISR Watermark Reg */
+/* Level and ISR Timer Registers (Yukon-2 only)*/
+#define STAT_LEV_TIMER_INI                  0x0eb0  /* 32 bit Level Timer Init. Value Reg */
+#define STAT_LEV_TIMER_CNT                  0x0eb4  /* 32 bit Level Timer Counter Reg */
+#define STAT_LEV_TIMER_CTRL                 0x0eb8  /*  8 bit Level Timer Control Reg */
+#define STAT_LEV_TIMER_TEST                 0x0eb9  /*  8 bit Level Timer Test Reg */
+#define STAT_TX_TIMER_INI                   0x0ec0  /* 32 bit Tx Timer Init. Value Reg */
+#define STAT_TX_TIMER_CNT                   0x0ec4  /* 32 bit Tx Timer Counter Reg */
+#define STAT_TX_TIMER_CTRL                  0x0ec8  /*  8 bit Tx Timer Control Reg */
+#define STAT_TX_TIMER_TEST                  0x0ec9  /*  8 bit Tx Timer Test Reg */
+#define STAT_ISR_TIMER_INI                  0x0ed0  /* 32 bit ISR Timer Init. Value Reg */
+#define STAT_ISR_TIMER_CNT                  0x0ed4  /* 32 bit ISR Timer Counter Reg */
+#define STAT_ISR_TIMER_CTRL                 0x0ed8  /*  8 bit ISR Timer Control Reg */
+#define STAT_ISR_TIMER_TEST                 0x0ed9  /*  8 bit ISR Timer Test Reg */
+
+#define  ST_LAST_IDX_MASK                   0x007f  /* Last Index Mask */
+#define  ST_TXRP_IDX_MASK                   0x0fff  /* Tx Report Index Mask */
+#define  ST_TXTH_IDX_MASK                   0x0fff  /* Tx Threshold Index Mask */
+#define  ST_WM_IDX_MASK                     0x3f    /* FIFO Watermark Index Mask */
+
+/*
+ *  Bank 30
+ */
+/* GMAC and GPHY Control Registers (YUKON only) */
+#define GMAC_CTRL                           0x0f00  /* 32 bit GMAC Control Reg */
+#define GPHY_CTRL                           0x0f04  /* 32 bit GPHY Control Reg */
+#define GMAC_IRQ_SRC                        0x0f08  /*  8 bit GMAC Interrupt Source Reg */
+#define GMAC_IRQ_MSK                        0x0f0c  /*  8 bit GMAC Interrupt Mask Reg */
+#define GMAC_LINK_CTRL                      0x0f10  /* 16 bit Link Control Reg */
+
+/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
+
+#define WOL_REG_OFFS                        0x20  /* HW-Bug: Address is + 0x20 against spec. */
+
+#define WOL_CTRL_STAT                       0x0f20  /* 16 bit WOL Control/Status Reg */
+#define WOL_MATCH_CTL                       0x0f22  /*  8 bit WOL Match Control Reg */
+#define WOL_MATCH_RES                       0x0f23  /*  8 bit WOL Match Result Reg */
+#define WOL_MAC_ADDR_LO                     0x0f24  /* 32 bit WOL MAC Address Low */
+#define WOL_MAC_ADDR_HI                     0x0f28  /* 16 bit WOL MAC Address High */
+#define WOL_PATT_PME                        0x0f2a  /*  8 bit WOL PME Match Enable (Yukon-2) */
+#define WOL_PATT_ASFM                       0x0f2b  /*  8 bit WOL ASF Match Enable (Yukon-2) */
+#define WOL_PATT_RPTR                       0x0f2c  /*  8 bit WOL Pattern Read Pointer */
+
+/* WOL Pattern Length Registers (YUKON only) */
+
+#define WOL_PATT_LEN_LO                     0x0f30  /* 32 bit WOL Pattern Length 3..0 */
+#define WOL_PATT_LEN_HI                     0x0f34  /* 24 bit WOL Pattern Length 6..4 */
+
+/* WOL Pattern Counter Registers (YUKON only) */
+
+#define WOL_PATT_CNT_0                      0x0f38  /* 32 bit WOL Pattern Counter 3..0 */
+#define WOL_PATT_CNT_4                      0x0f3c  /* 24 bit WOL Pattern Counter 6..4 */
+
+/*
+ *  Bank 32  - 33
+ */
+#define WOL_PATT_RAM_1                      0x1000  /*  WOL Pattern RAM Link 1 */
+#define WOL_PATT_RAM_2                      0x1400  /*  WOL Pattern RAM Link 2 */
+
+/* offset to configuration space on Yukon-2 */
+#define Y2_CFG_SPC                          0x1c00
+#define BASE_GMAC_1                         0x2800  /* GMAC 1 registers */
+#define BASE_GMAC_2                         0x3800  /* GMAC 2 registers */
+
+/*
+ *  Control Register Bit Definitions:
+ */
+/*  B0_CTST  24 bit  Control/Status register */
+#define Y2_VMAIN_AVAIL                      BIT_17  /* VMAIN available (YUKON-2 only) */
+#define Y2_VAUX_AVAIL                       BIT_16  /* VAUX available (YUKON-2 only) */
+#define  Y2_HW_WOL_ON                       BIT_15  /* HW WOL On  (Yukon-EC Ultra A1 only) */
+#define  Y2_HW_WOL_OFF                      BIT_14  /* HW WOL Off (Yukon-EC Ultra A1 only) */
+#define Y2_ASF_ENABLE                       BIT_13  /* ASF Unit Enable (YUKON-2 only) */
+#define Y2_ASF_DISABLE                      BIT_12  /* ASF Unit Disable (YUKON-2 only) */
+#define Y2_CLK_RUN_ENA                      BIT_11  /* CLK_RUN Enable  (YUKON-2 only) */
+#define Y2_CLK_RUN_DIS                      BIT_10  /* CLK_RUN Disable (YUKON-2 only) */
+#define Y2_LED_STAT_ON                      BIT_9  /* Status LED On  (YUKON-2 only) */
+#define Y2_LED_STAT_OFF                     BIT_8  /* Status LED Off (YUKON-2 only) */
+#define CS_ST_SW_IRQ                        BIT_7  /* Set IRQ SW Request */
+#define CS_CL_SW_IRQ                        BIT_6  /* Clear IRQ SW Request */
+#define CS_STOP_DONE                        BIT_5  /* Stop Master is finished */
+#define CS_STOP_MAST                        BIT_4  /* Command Bit to stop the master */
+#define CS_MRST_CLR                         BIT_3  /* Clear Master Reset */
+#define CS_MRST_SET                         BIT_2  /* Set   Master Reset */
+#define CS_RST_CLR                          BIT_1  /* Clear Software Reset  */
+#define CS_RST_SET                          BIT_0  /* Set   Software Reset  */
+#define Y_ULTRA_2_PLUG_IN_GO_EN             BIT_15
+
+#define LED_STAT_ON                         BIT_1  /* Status LED On  */
+#define LED_STAT_OFF                        BIT_0  /* Status LED Off  */
+
+/* B0_POWER_CTRL   8 Bit  Power Control reg (YUKON only) */
+#define PC_VAUX_ENA                         BIT_7  /* Switch VAUX Enable  */
+#define PC_VAUX_DIS                         BIT_6  /* Switch VAUX Disable */
+#define PC_VCC_ENA                          BIT_5  /* Switch VCC Enable  */
+#define PC_VCC_DIS                          BIT_4  /* Switch VCC Disable */
+#define PC_VAUX_ON                          BIT_3  /* Switch VAUX On  */
+#define PC_VAUX_OFF                         BIT_2  /* Switch VAUX Off */
+#define PC_VCC_ON                           BIT_1  /* Switch VCC On  */
+#define PC_VCC_OFF                          BIT_0  /* Switch VCC Off */
+
+/*  B0_ISRC    32 bit  Interrupt Source Register */
+/*  B0_IMSK    32 bit  Interrupt Mask Register */
+/*  B0_SP_ISRC  32 bit  Special Interrupt Source Reg */
+/*  B2_IRQM_MSK  32 bit  IRQ Moderation Mask */
+/*  B0_Y2_SP_ISRC2  32 bit  Special Interrupt Source Reg 2 */
+/*  B0_Y2_SP_ISRC3  32 bit  Special Interrupt Source Reg 3 */
+/*  B0_Y2_SP_EISR  32 bit  Enter ISR Reg */
+/*  B0_Y2_SP_LISR  32 bit  Leave ISR Reg */
+#define Y2_IS_PORT_MASK(Port, Mask)         ((Mask) << (Port*8))
+#define Y2_IS_HW_ERR                        BIT_31  /* Interrupt HW Error */
+#define Y2_IS_STAT_BMU                      BIT_30  /* Status BMU Interrupt */
+#define Y2_IS_ASF                           BIT_29  /* ASF subsystem Interrupt */
+#define Y2_IS_POLL_CHK                      BIT_27  /* Check IRQ from polling unit */
+#define Y2_IS_TWSI_RDY                      BIT_26  /* IRQ on end of TWSI Tx */
+#define Y2_IS_IRQ_SW                        BIT_25  /* SW forced IRQ  */
+#define Y2_IS_TIMINT                        BIT_24  /* IRQ from Timer  */
+#define Y2_IS_IRQ_PHY2                      BIT_12  /* Interrupt from PHY 2 */
+#define Y2_IS_IRQ_MAC2                      BIT_11  /* Interrupt from MAC 2 */
+#define Y2_IS_CHK_RX2                       BIT_10  /* Descriptor error Rx 2 */
+#define Y2_IS_CHK_TXS2                      BIT_9  /* Descriptor error TXS 2 */
+#define Y2_IS_CHK_TXA2                      BIT_8  /* Descriptor error TXA 2 */
+#define Y2_IS_PSM_ACK                       BIT_7  /* PSM Ack (Yukon Optima) */
+#define Y2_IS_PTP_TIST                      BIT_6  /* PTP TIme Stamp (Yukon Optima) */
+#define Y2_IS_PHY_QLNK                      BIT_5  /* PHY Quick Link (Yukon Optima) */
+#define Y2_IS_IRQ_PHY1                      BIT_4  /* Interrupt from PHY 1 */
+#define Y2_IS_IRQ_MAC1                      BIT_3  /* Interrupt from MAC 1 */
+#define Y2_IS_CHK_RX1                       BIT_2  /* Descriptor error Rx 1 */
+#define Y2_IS_CHK_TXS1                      BIT_1  /* Descriptor error TXS 1 */
+#define Y2_IS_CHK_TXA1                      BIT_0  /* Descriptor error TXA 1 */
+
+#define Y2_IS_L1_MASK                       0x0000001f  /* IRQ Mask for port 1 */
+
+#define Y2_IS_L2_MASK                       0x00001f00  /* IRQ Mask for port 2 */
+
+#define Y2_IS_ALL_MSK                       0xef001f1f  /* All Interrupt bits */
+
+#define  Y2_IS_PORT_A                       (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1)
+#define  Y2_IS_PORT_B                       (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2)
+
+/*  B0_HWE_ISRC  32 bit  HW Error Interrupt Src Reg */
+/*  B0_HWE_IMSK  32 bit  HW Error Interrupt Mask Reg */
+/*  B2_IRQM_HWE_MSK  32 bit  IRQ Moderation HW Error Mask */
+#define Y2_IS_TIST_OV                       BIT_29  /* Time Stamp Timer overflow interrupt */
+#define Y2_IS_SENSOR                        BIT_28  /* Sensor interrupt */
+#define Y2_IS_MST_ERR                       BIT_27  /* Master error interrupt */
+#define Y2_IS_IRQ_STAT                      BIT_26  /* Status exception interrupt */
+#define Y2_IS_PCI_EXP                       BIT_25  /* PCI-Express interrupt */
+#define Y2_IS_PCI_NEXP                      BIT_24  /* PCI-Express error similar to PCI error */
+#define Y2_IS_PAR_RD2                       BIT_13  /* Read RAM parity error interrupt */
+#define Y2_IS_PAR_WR2                       BIT_12  /* Write RAM parity error interrupt */
+#define Y2_IS_PAR_MAC2                      BIT_11  /* MAC hardware fault interrupt */
+#define Y2_IS_PAR_RX2                       BIT_10  /* Parity Error Rx Queue 2 */
+#define Y2_IS_TCP_TXS2                      BIT_9  /* TCP length mismatch sync Tx queue IRQ */
+#define Y2_IS_TCP_TXA2                      BIT_8  /* TCP length mismatch async Tx queue IRQ */
+#define Y2_IS_PAR_RD1                       BIT_5  /* Read RAM parity error interrupt */
+#define Y2_IS_PAR_WR1                       BIT_4  /* Write RAM parity error interrupt */
+#define Y2_IS_PAR_MAC1                      BIT_3  /* MAC hardware fault interrupt */
+#define Y2_IS_PAR_RX1                       BIT_2  /* Parity Error Rx Queue 1 */
+#define Y2_IS_TCP_TXS1                      BIT_1  /* TCP length mismatch sync Tx queue IRQ */
+#define Y2_IS_TCP_TXA1                      BIT_0  /* TCP length mismatch async Tx queue IRQ */
+
+#define Y2_HWE_L1_MASK                      (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
+#define Y2_HWE_L2_MASK                      (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
+
+#define Y2_HWE_ALL_MSK                      (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR  | Y2_IS_IRQ_STAT | \
+  Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP  |    Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
+
+/*  B2_MAC_CFG   8 bit  MAC Configuration / Chip Revision */
+#define CFG_CHIP_R_MSK                      (0x0f<<4) /* Bit 7.. 4: Chip Revision */
+#define CFG_DIS_M2_CLK                      BIT_1  /* Disable Clock for 2nd MAC */
+#define CFG_SNG_MAC                         BIT_0  /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
+
+/*  B2_CHIP_ID   8 bit  Chip Identification Number */
+#define CHIP_ID_GENESIS                     0x0a /* Chip ID for GENESIS */
+#define CHIP_ID_YUKON                       0xb0 /* Chip ID for YUKON */
+#define CHIP_ID_YUKON_LITE                  0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
+#define CHIP_ID_YUKON_LP                    0xb2 /* Chip ID for YUKON-LP */
+#define CHIP_ID_YUKON_XL                    0xb3 /* Chip ID for YUKON-2 XL */
+#define CHIP_ID_YUKON_EC_U                  0xb4 /* Chip ID for YUKON-2 EC Ultra */
+#define CHIP_ID_YUKON_EX                    0xb5 /* Chip ID for YUKON-2 Extreme */
+#define CHIP_ID_YUKON_EC                    0xb6 /* Chip ID for YUKON-2 EC */
+#define CHIP_ID_YUKON_FE                    0xb7 /* Chip ID for YUKON-2 FE */
+#define CHIP_ID_YUKON_FE_P                  0xb8 /* Chip ID for YUKON-2 FE+ */
+#define CHIP_ID_YUKON_SUPR                  0xb9 /* Chip ID for YUKON-2 Supreme */
+#define CHIP_ID_YUKON_UL_2                  0xba /* Chip ID for YUKON-2 Ultra 2 */
+#define CHIP_ID_YUKON_UNKNOWN               0xbb
+#define CHIP_ID_YUKON_OPT                   0xbc /* Chip ID for YUKON-2 Optima */
+
+#define  CHIP_REV_YU_XL_A0                  0 /* Chip Rev. for Yukon-2 A0 */
+#define  CHIP_REV_YU_XL_A1                  1 /* Chip Rev. for Yukon-2 A1 */
+#define  CHIP_REV_YU_XL_A2                  2 /* Chip Rev. for Yukon-2 A2 */
+#define  CHIP_REV_YU_XL_A3                  3 /* Chip Rev. for Yukon-2 A3 */
+
+#define CHIP_REV_YU_EC_A1                   0 /* Chip Rev. for Yukon-EC A1/A0 */
+#define CHIP_REV_YU_EC_A2                   1 /* Chip Rev. for Yukon-EC A2 */
+#define CHIP_REV_YU_EC_A3                   2 /* Chip Rev. for Yukon-EC A3 */
+
+#define  CHIP_REV_YU_EC_U_A0                1
+#define  CHIP_REV_YU_EC_U_A1                2
+
+#define  CHIP_REV_YU_FE_P_A0                0 /* Chip Rev. for Yukon-2 FE+ A0 */
+
+#define  CHIP_REV_YU_EX_A0                  1 /* Chip Rev. for Yukon-2 EX A0 */
+#define  CHIP_REV_YU_EX_B0                  2 /* Chip Rev. for Yukon-2 EX B0 */
+
+/*  B2_Y2_CLK_GATE   8 bit  Clock Gating (Yukon-2 only) */
+#define Y2_STATUS_LNK2_INAC                 BIT_7  /* Status Link 2 inactiv (0 = activ) */
+#define Y2_CLK_GAT_LNK2_DIS                 BIT_6  /* Disable clock gating Link 2 */
+#define Y2_COR_CLK_LNK2_DIS                 BIT_5  /* Disable Core clock Link 2 */
+#define Y2_PCI_CLK_LNK2_DIS                 BIT_4  /* Disable PCI clock Link 2 */
+#define Y2_STATUS_LNK1_INAC                 BIT_3  /* Status Link 1 inactiv (0 = activ) */
+#define Y2_CLK_GAT_LNK1_DIS                 BIT_2  /* Disable clock gating Link 1 */
+#define Y2_COR_CLK_LNK1_DIS                 BIT_1  /* Disable Core clock Link 1 */
+#define Y2_PCI_CLK_LNK1_DIS                 BIT_0  /* Disable PCI clock Link 1 */
+
+/*  B2_Y2_HW_RES  8 bit  HW Resources (Yukon-2 only) */
+#define CFG_LED_MODE_MSK                    (0x07<<2)  /* Bit  4.. 2:  LED Mode Mask */
+#define CFG_LINK_2_AVAIL                    BIT_1  /* Link 2 available */
+#define CFG_LINK_1_AVAIL                    BIT_0  /* Link 1 available */
+
+#define CFG_LED_MODE(x)                     (((x) & CFG_LED_MODE_MSK) >> 2)
+#define CFG_DUAL_MAC_MSK                    (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
+
+/*  B2_E_3     8 bit  lower 4 bits used for HW self test result */
+#define B2_E3_RES_MASK                      0x0f
+
+/*  B2_Y2_CLK_CTRL  32 bit  Core Clock Frequency Control Register (Yukon-2/EC) */
+/* Yukon-EC/FE */
+#define Y2_CLK_DIV_VAL_MSK                  (0xff<<16) /* Bit 23..16: Clock Divisor Value */
+#define Y2_CLK_DIV_VAL(x)                   (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
+/* Yukon-2 */
+#define Y2_CLK_DIV_VAL2_MSK                 (0x07<<21) /* Bit 23..21: Clock Divisor Value */
+#define Y2_CLK_SELECT2_MSK                  (0x1f<<16) /* Bit 20..16: Clock Select */
+#define Y2_CLK_DIV_VAL_2(x)                 (SHIFT21 (x) & Y2_CLK_DIV_VAL2_MSK)
+#define Y2_CLK_SEL_VAL_2(x)                 (SHIFT16 (x) & Y2_CLK_SELECT2_MSK)
+#define Y2_CLK_DIV_ENA                      BIT_1  /* Enable  Core Clock Division */
+#define Y2_CLK_DIV_DIS                      BIT_0  /* Disable Core Clock Division */
+
+/*  B2_TI_CTRL   8 bit  Timer control */
+/*  B2_IRQM_CTRL   8 bit  IRQ Moderation Timer Control */
+#define TIM_START                           BIT_2  /* Start Timer */
+#define TIM_STOP                            BIT_1  /* Stop  Timer */
+#define TIM_CLR_IRQ                         BIT_0  /* Clear Timer IRQ (!IRQM) */
+
+/*  B2_TI_TEST   8 Bit  Timer Test */
+/*  B2_IRQM_TEST   8 bit  IRQ Moderation Timer Test */
+/*  B28_DPT_TST   8 bit  Descriptor Poll Timer Test Reg */
+#define TIM_T_ON                            BIT_2  /* Test mode on */
+#define TIM_T_OFF                           BIT_1  /* Test mode off */
+#define TIM_T_STEP                          BIT_0  /* Test step */
+
+/*  B28_DPT_INI  32 bit  Descriptor Poll Timer Init Val */
+/*  B28_DPT_VAL  32 bit  Descriptor Poll Timer Curr Val */
+#define DPT_MSK                             0x00ffffff  /* Bit 23.. 0:  Desc Poll Timer Bits */
+
+/*  B28_DPT_CTRL   8 bit  Descriptor Poll Timer Ctrl Reg */
+#define DPT_START                           BIT_1  /* Start Descriptor Poll Timer */
+#define DPT_STOP                            BIT_0  /* Stop  Descriptor Poll Timer */
+
+/*  B2_TST_CTRL1   8 bit  Test Control Register 1 */
+#define TST_FRC_DPERR_MR                    BIT_7  /* force DATAPERR on MST RD */
+#define TST_FRC_DPERR_MW                    BIT_6  /* force DATAPERR on MST WR */
+#define TST_FRC_DPERR_TR                    BIT_5  /* force DATAPERR on TRG RD */
+#define TST_FRC_DPERR_TW                    BIT_4  /* force DATAPERR on TRG WR */
+#define TST_FRC_APERR_M                     BIT_3  /* force ADDRPERR on MST */
+#define TST_FRC_APERR_T                     BIT_2  /* force ADDRPERR on TRG */
+#define TST_CFG_WRITE_ON                    BIT_1  /* Enable  Config Reg WR */
+#define TST_CFG_WRITE_OFF                   BIT_0  /* Disable Config Reg WR */
+
+/*  B2_GP_IO */
+#define  GLB_GPIO_CLK_DEB_ENA               BIT_31  /* Clock Debug Enable */
+#define  GLB_GPIO_CLK_DBG_MSK               0x3c000000  /* Clock Debug */
+
+#define  GLB_GPIO_INT_RST_D3_DIS            BIT_15  /* Disable Internal Reset After D3 to D0 */
+#define  GLB_GPIO_LED_PAD_SPEED_UP          BIT_14  /* LED PAD Speed Up */
+#define  GLB_GPIO_STAT_RACE_DIS             BIT_13  /* Status Race Disable */
+#define  GLB_GPIO_TEST_SEL_MSK              0x00001800  /* Testmode Select */
+#define  GLB_GPIO_TEST_SEL_BASE             BIT_11
+#define  GLB_GPIO_RAND_ENA                  BIT_10  /* Random Enable */
+#define  GLB_GPIO_RAND_BIT_1                BIT_9  /* Random Bit 1 */
+
+/*  B2_I2C_CTRL  32 bit  I2C HW Control Register */
+#define I2C_FLAG                            BIT_31    /* Start read/write if WR */
+#define I2C_ADDR                            (0x7fff<<16)  /* Bit 30..16:  Addr to be RD/WR */
+#define I2C_DEV_SEL                         (0x7f<<9)  /* Bit 15.. 9:  I2C Device Select */
+#define I2C_BURST_LEN                       BIT_4    /* Burst Len, 1/4 bytes */
+#define I2C_DEV_SIZE                        (7<<1)    /* Bit  3.. 1:  I2C Device Size  */
+#define I2C_025K_DEV                        (0<<1)    /*    0: 256 Bytes or smal. */
+#define I2C_05K_DEV                         (1<<1)    /*     1: 512  Bytes  */
+#define I2C_1K_DEV                          (2<<1)    /*    2: 1024 Bytes  */
+#define I2C_2K_DEV                          (3<<1)    /*    3: 2048  Bytes  */
+#define I2C_4K_DEV                          (4<<1)    /*    4: 4096 Bytes  */
+#define I2C_8K_DEV                          (5<<1)    /*    5: 8192 Bytes  */
+#define I2C_16K_DEV                         (6<<1)    /*    6: 16384 Bytes  */
+#define I2C_32K_DEV                         (7<<1)    /*    7: 32768 Bytes  */
+#define I2C_STOP                            BIT_0    /* Interrupt I2C transfer */
+
+/*  B2_I2C_IRQ  32 bit  I2C HW IRQ Register */
+#define I2C_CLR_IRQ                         BIT_0    /* Clear I2C IRQ */
+
+/*  B2_I2C_SW  32 bit (8 bit access)  I2C HW SW Port Register */
+#define I2C_DATA_DIR                        BIT_2    /* direction of I2C_DATA */
+#define I2C_DATA                            BIT_1    /* I2C Data Port  */
+#define I2C_CLK                             BIT_0    /* I2C Clock Port  */
+
+/* I2C Address */
+#define I2C_SENS_ADDR                       LM80_ADDR  /* I2C Sensor Address (Volt and Temp) */
+
+
+/*  B2_BSC_CTRL   8 bit  Blink Source Counter Control */
+#define BSC_START                           BIT_1    /* Start Blink Source Counter */
+#define BSC_STOP                            BIT_0    /* Stop  Blink Source Counter */
+
+/*  B2_BSC_STAT   8 bit  Blink Source Counter Status */
+#define BSC_SRC                             BIT_0    /* Blink Source, 0=Off / 1=On */
+
+/*  B2_BSC_TST  16 bit  Blink Source Counter Test Reg */
+#define BSC_T_ON                            BIT_2    /* Test mode on */
+#define BSC_T_OFF                           BIT_1    /* Test mode off */
+#define BSC_T_STEP                          BIT_0    /* Test step */
+
+/*  Y2_PEX_PHY_ADDR/DATA  PEX PHY address and data reg  (Yukon-2 only) */
+#define PEX_RD_ACCESS                       BIT_31  /* Access Mode Read = 1, Write = 0 */
+#define PEX_DB_ACCESS                       BIT_30  /* Access to debug register */
+
+/*  B3_RAM_ADDR    32 bit  RAM Address, to read or write */
+#define RAM_ADR_RAN                         0x0007ffff  /* Bit 18.. 0:  RAM Address Range */
+
+/* RAM Interface Registers */
+/*  B3_RI_CTRL    16 bit  RAM Interface Control Register */
+#define RI_CLR_RD_PERR                      BIT_9  /* Clear IRQ RAM Read  Parity Err */
+#define RI_CLR_WR_PERR                      BIT_8  /* Clear IRQ RAM Write Parity Err */
+#define RI_RST_CLR                          BIT_1  /* Clear RAM Interface Reset */
+#define RI_RST_SET                          BIT_0  /* Set   RAM Interface Reset */
+
+#define  MSK_RI_TO_53                       36  /* RAM interface timeout */
+
+/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
+/*  TXA_ITI_INI  32 bit  Tx Arb Interval Timer Init Val */
+/*  TXA_ITI_VAL  32 bit  Tx Arb Interval Timer Value */
+/*  TXA_LIM_INI  32 bit  Tx Arb Limit Counter Init Val */
+/*  TXA_LIM_VAL  32 bit  Tx Arb Limit Counter Value */
+#define TXA_MAX_VAL                         0x00ffffff/* Bit 23.. 0:  Max TXA Timer/Cnt Val */
+
+/*  TXA_CTRL   8 bit  Tx Arbiter Control Register */
+#define TXA_ENA_FSYNC                       BIT_7  /* Enable  force of sync Tx queue */
+#define TXA_DIS_FSYNC                       BIT_6  /* Disable force of sync Tx queue */
+#define TXA_ENA_ALLOC                       BIT_5  /* Enable  alloc of free bandwidth */
+#define TXA_DIS_ALLOC                       BIT_4  /* Disable alloc of free bandwidth */
+#define TXA_START_RC                        BIT_3  /* Start sync Rate Control */
+#define TXA_STOP_RC                         BIT_2  /* Stop  sync Rate Control */
+#define TXA_ENA_ARB                         BIT_1  /* Enable  Tx Arbiter */
+#define TXA_DIS_ARB                         BIT_0  /* Disable Tx Arbiter */
+
+/*  TXA_TEST   8 bit  Tx Arbiter Test Register */
+#define TXA_INT_T_ON                        BIT_5  /* Tx Arb Interval Timer Test On */
+#define TXA_INT_T_OFF                       BIT_4  /* Tx Arb Interval Timer Test Off */
+#define TXA_INT_T_STEP                      BIT_3  /* Tx Arb Interval Timer Step */
+#define TXA_LIM_T_ON                        BIT_2  /* Tx Arb Limit Timer Test On */
+#define TXA_LIM_T_OFF                       BIT_1  /* Tx Arb Limit Timer Test Off */
+#define TXA_LIM_T_STEP                      BIT_0  /* Tx Arb Limit Timer Step */
+
+/*  TXA_STAT   8 bit  Tx Arbiter Status Register */
+#define TXA_PRIO_XS                         BIT_0  /* sync queue has prio to send */
+
+/*  Q_BC    32 bit  Current Byte Counter */
+#define BC_MAX                              0xffff  /* Bit 15.. 0:  Byte counter */
+
+/* Rx BMU Control / Status Registers (Yukon-2) */
+#define BMU_IDLE                            BIT_31  /* BMU Idle State */
+#define BMU_RX_TCP_PKT                      BIT_30  /* Rx TCP Packet (when RSS Hash enabled) */
+#define BMU_RX_IP_PKT                       BIT_29  /* Rx IP  Packet (when RSS Hash enabled) */
+#define BMU_ENA_RX_RSS_HASH                 BIT_15  /* Enable  Rx RSS Hash */
+#define BMU_DIS_RX_RSS_HASH                 BIT_14  /* Disable Rx RSS Hash */
+#define BMU_ENA_RX_CHKSUM                   BIT_13  /* Enable  Rx TCP/IP Checksum Check */
+#define BMU_DIS_RX_CHKSUM                   BIT_12  /* Disable Rx TCP/IP Checksum Check */
+#define BMU_CLR_IRQ_PAR                     BIT_11  /* Clear IRQ on Parity errors (Rx) */
+#define BMU_CLR_IRQ_TCP                     BIT_11  /* Clear IRQ on TCP segmen. error (Tx) */
+#define BMU_CLR_IRQ_CHK                     BIT_10  /* Clear IRQ Check */
+#define BMU_STOP                            BIT_9  /* Stop  Rx/Tx Queue */
+#define BMU_START                           BIT_8  /* Start Rx/Tx Queue */
+#define BMU_FIFO_OP_ON                      BIT_7  /* FIFO Operational On */
+#define BMU_FIFO_OP_OFF                     BIT_6  /* FIFO Operational Off */
+#define BMU_FIFO_ENA                        BIT_5  /* Enable FIFO */
+#define BMU_FIFO_RST                        BIT_4  /* Reset  FIFO */
+#define BMU_OP_ON                           BIT_3  /* BMU Operational On */
+#define BMU_OP_OFF                          BIT_2  /* BMU Operational Off */
+#define BMU_RST_CLR                         BIT_1  /* Clear BMU Reset (Enable) */
+#define BMU_RST_SET                         BIT_0  /* Set   BMU Reset */
+
+#define BMU_CLR_RESET                       (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
+#define BMU_OPER_INIT                       (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | BMU_FIFO_ENA | BMU_OP_ON)
+
+/* Tx BMU Control / Status Registers (Yukon-2) */
+/* Bit 31: same as for Rx */
+#define BMU_TX_IPIDINCR_ON                  BIT_13  /* Enable  IP ID Increment */
+#define BMU_TX_IPIDINCR_OFF                 BIT_12  /* Disable IP ID Increment */
+#define BMU_TX_CLR_IRQ_TCP                  BIT_11  /* Clear IRQ on TCP segm. length mism. */
+/* Bit 10..0: same as for Rx */
+
+/*  Q_F    32 bit  Flag Register */
+#define F_TX_CHK_AUTO_OFF                   BIT_31  /* Tx checksum auto-calc Off(Yukon EX)*/
+#define F_TX_CHK_AUTO_ON                    BIT_30  /* Tx checksum auto-calc On(Yukon EX)*/
+#define F_ALM_FULL                          BIT_28  /* Rx FIFO: almost full */
+#define F_EMPTY                             BIT_27  /* Tx FIFO: empty flag */
+#define F_FIFO_EOF                          BIT_26  /* Tag (EOF Flag) bit in FIFO */
+#define F_WM_REACHED                        BIT_25  /* Watermark reached */
+#define F_M_RX_RAM_DIS                      BIT_24  /* MAC Rx RAM Read Port disable */
+#define F_FIFO_LEVEL                        (0x1f<<16)
+/* Bit 23..16:  # of Qwords in FIFO */
+#define F_WATER_MARK                        0x0007ff/* Bit 10.. 0:  Watermark */
+
+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
+/* PREF_UNIT_CTRL_REG  32 bit  Prefetch Control register */
+#define PREF_UNIT_OP_ON                     BIT_3  /* prefetch unit operational */
+#define PREF_UNIT_OP_OFF                    BIT_2  /* prefetch unit not operational */
+#define PREF_UNIT_RST_CLR                   BIT_1  /* Clear Prefetch Unit Reset */
+#define PREF_UNIT_RST_SET                   BIT_0  /* Set   Prefetch Unit Reset */
+
+/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
+/*  RB_START  32 bit  RAM Buffer Start Address */
+/*  RB_END    32 bit  RAM Buffer End Address */
+/*  RB_WP    32 bit  RAM Buffer Write Pointer */
+/*  RB_RP    32 bit  RAM Buffer Read Pointer */
+/*  RB_RX_UTPP  32 bit  Rx Upper Threshold, Pause Pack */
+/*  RB_RX_LTPP  32 bit  Rx Lower Threshold, Pause Pack */
+/*  RB_RX_UTHP  32 bit  Rx Upper Threshold, High Prio */
+/*  RB_RX_LTHP  32 bit  Rx Lower Threshold, High Prio */
+/*  RB_PC    32 bit  RAM Buffer Packet Counter */
+/*  RB_LEV    32 bit  RAM Buffer Level Register */
+#define RB_MSK                              0x0007ffff  /* Bit 18.. 0:  RAM Buffer Pointer Bits */
+
+/*  RB_TST2     8 bit  RAM Buffer Test Register 2 */
+#define RB_PC_DEC                           BIT_3  /* Packet Counter Decrement */
+#define RB_PC_T_ON                          BIT_2  /* Packet Counter Test On */
+#define RB_PC_T_OFF                         BIT_1  /* Packet Counter Test Off */
+#define RB_PC_INC                           BIT_0  /* Packet Counter Increment */
+
+/*  RB_TST1     8 bit  RAM Buffer Test Register 1 */
+#define RB_WP_T_ON                          BIT_6  /* Write Pointer Test On */
+#define RB_WP_T_OFF                         BIT_5  /* Write Pointer Test Off */
+#define RB_WP_INC                           BIT_4  /* Write Pointer Increment */
+#define RB_RP_T_ON                          BIT_2  /* Read Pointer Test On */
+#define RB_RP_T_OFF                         BIT_1  /* Read Pointer Test Off */
+#define RB_RP_INC                           BIT_0  /* Read Pointer Increment */
+
+/*  RB_CTRL     8 bit  RAM Buffer Control Register */
+#define RB_ENA_STFWD                        BIT_5  /* Enable  Store & Forward */
+#define RB_DIS_STFWD                        BIT_4  /* Disable Store & Forward */
+#define RB_ENA_OP_MD                        BIT_3  /* Enable  Operation Mode */
+#define RB_DIS_OP_MD                        BIT_2  /* Disable Operation Mode */
+#define RB_RST_CLR                          BIT_1  /* Clear RAM Buf STM Reset */
+#define RB_RST_SET                          BIT_0  /* Set   RAM Buf STM Reset */
+
+/* RAM Buffer High Pause Threshold values */
+#define  MSK_RB_ULPP                          (8 * 1024)  /* Upper Level in kB/8 */
+#define  MSK_RB_LLPP_S                        (10 * 1024)  /* Lower Level for small Queues */
+#define  MSK_RB_LLPP_B                        (16 * 1024)  /* Lower Level for big Queues */
+
+/* Threshold values for Yukon-EC Ultra */
+#define  MSK_ECU_ULPP                       0x0080  /* Upper Pause Threshold (multiples of 8) */
+#define  MSK_ECU_LLPP                       0x0060  /* Lower Pause Threshold (multiples of 8) */
+#define  MSK_ECU_AE_THR                     0x0070  /* Almost Empty Threshold */
+#define  MSK_ECU_TXFF_LEV                   0x01a0  /* Tx BMU FIFO Level */
+#define  MSK_ECU_JUMBO_WM                   0x01
+
+#define MSK_BMU_RX_WM                       0x80  /* BMU Rx Watermark */
+#define MSK_BMU_TX_WM                       0x600  /* BMU Tx Watermark */
+/* performance sensitive drivers should set this define to 0x80 */
+#define MSK_BMU_RX_WM_PEX                   0x600  /* BMU Rx Watermark for PEX */
+
+/* Receive and Transmit Queues */
+#define Q_R1                                0x0000  /* Receive Queue 1 */
+#define Q_R2                                0x0080  /* Receive Queue 2 */
+#define Q_XS1                               0x0200  /* Synchronous Transmit Queue 1 */
+#define Q_XA1                               0x0280  /* Asynchronous Transmit Queue 1 */
+#define Q_XS2                               0x0300  /* Synchronous Transmit Queue 2 */
+#define Q_XA2                               0x0380  /* Asynchronous Transmit Queue 2 */
+
+#define Q_ASF_R1                            0x100  /* ASF Rx Queue 1 */
+#define Q_ASF_R2                            0x180  /* ASF Rx Queue 2 */
+#define Q_ASF_T1                            0x140  /* ASF Tx Queue 1 */
+#define Q_ASF_T2                            0x1c0  /* ASF Tx Queue 2 */
+
+#define RB_ADDR(Queue, Offs)                (B16_RAM_REGS + (Queue) + (Offs))
+
+/* Minimum RAM Buffer Rx Queue Size */
+#define  MSK_MIN_RXQ_SIZE                   10
+/* Minimum RAM Buffer Tx Queue Size */
+#define  MSK_MIN_TXQ_SIZE                   10
+/* Percentage of queue size from whole memory. 80 % for receive */
+#define  MSK_RAM_QUOTA_RX                   80
+
+/*  WOL_CTRL_STAT  16 bit  WOL Control/Status Reg */
+#define WOL_CTL_LINK_CHG_OCC                BIT_15
+#define WOL_CTL_MAGIC_PKT_OCC               BIT_14
+#define WOL_CTL_PATTERN_OCC                 BIT_13
+#define WOL_CTL_CLEAR_RESULT                BIT_12
+#define WOL_CTL_ENA_PME_ON_LINK_CHG         BIT_11
+#define WOL_CTL_DIS_PME_ON_LINK_CHG         BIT_10
+#define WOL_CTL_ENA_PME_ON_MAGIC_PKT        BIT_9
+#define WOL_CTL_DIS_PME_ON_MAGIC_PKT        BIT_8
+#define WOL_CTL_ENA_PME_ON_PATTERN          BIT_7
+#define WOL_CTL_DIS_PME_ON_PATTERN          BIT_6
+#define WOL_CTL_ENA_LINK_CHG_UNIT           BIT_5
+#define WOL_CTL_DIS_LINK_CHG_UNIT           BIT_4
+#define WOL_CTL_ENA_MAGIC_PKT_UNIT          BIT_3
+#define WOL_CTL_DIS_MAGIC_PKT_UNIT          BIT_2
+#define WOL_CTL_ENA_PATTERN_UNIT            BIT_1
+#define WOL_CTL_DIS_PATTERN_UNIT            BIT_0
+
+#define WOL_CTL_DEFAULT                     (WOL_CTL_DIS_PME_ON_LINK_CHG  |  WOL_CTL_DIS_PME_ON_PATTERN |  \
+  WOL_CTL_DIS_PME_ON_MAGIC_PKT |  WOL_CTL_DIS_LINK_CHG_UNIT  |  \
+  WOL_CTL_DIS_PATTERN_UNIT     | WOL_CTL_DIS_MAGIC_PKT_UNIT)
+
+/*  WOL_MATCH_CTL   8 bit  WOL Match Control Reg */
+#define WOL_CTL_PATT_ENA(x)                  (BIT_0 << (x))
+
+/*  WOL_PATT_PME  8 bit  WOL PME Match Enable (Yukon-2) */
+#define WOL_PATT_FORCE_PME                  BIT_7  /* Generates a PME */
+#define WOL_PATT_MATCH_PME_ALL              0x7f
+
+
+/*
+ * Marvel-PHY Registers, indirect addressed over GMAC
+ */
+#define PHY_MARV_CTRL                       0x00  /* 16 bit r/w  PHY Control Register */
+#define PHY_MARV_STAT                       0x01  /* 16 bit r/o  PHY Status Register */
+#define PHY_MARV_ID0                        0x02  /* 16 bit r/o  PHY ID0 Register */
+#define PHY_MARV_ID1                        0x03  /* 16 bit r/o  PHY ID1 Register */
+#define PHY_MARV_AUNE_ADV                   0x04  /* 16 bit r/w  Auto-Neg. Advertisement */
+#define PHY_MARV_AUNE_LP                    0x05  /* 16 bit r/o  Link Part Ability Reg */
+#define PHY_MARV_AUNE_EXP                   0x06  /* 16 bit r/o  Auto-Neg. Expansion Reg */
+#define PHY_MARV_NEPG                       0x07  /* 16 bit r/w  Next Page Register */
+#define PHY_MARV_NEPG_LP                    0x08  /* 16 bit r/o  Next Page Link Partner */
+/* Marvel-specific registers */
+#define PHY_MARV_1000T_CTRL                 0x09  /* 16 bit r/w  1000Base-T Control Reg */
+#define PHY_MARV_1000T_STAT                 0x0a  /* 16 bit r/o  1000Base-T Status Reg */
+/* 0x0b - 0x0e:    reserved */
+#define PHY_MARV_EXT_STAT                   0x0f  /* 16 bit r/o  Extended Status Reg */
+#define PHY_MARV_PHY_CTRL                   0x10  /* 16 bit r/w  PHY Specific Control Reg */
+#define PHY_MARV_PHY_STAT                   0x11  /* 16 bit r/o  PHY Specific Status Reg */
+#define PHY_MARV_INT_MASK                   0x12  /* 16 bit r/w  Interrupt Mask Reg */
+#define PHY_MARV_INT_STAT                   0x13  /* 16 bit r/o  Interrupt Status Reg */
+#define PHY_MARV_EXT_CTRL                   0x14  /* 16 bit r/w  Ext. PHY Specific Ctrl */
+#define PHY_MARV_RXE_CNT                    0x15  /* 16 bit r/w  Receive Error Counter */
+#define PHY_MARV_EXT_ADR                    0x16  /* 16 bit r/w  Ext. Ad. for Cable Diag. */
+#define PHY_MARV_PORT_IRQ                   0x17  /* 16 bit r/o  Port 0 IRQ (88E1111 only) */
+#define PHY_MARV_LED_CTRL                   0x18  /* 16 bit r/w  LED Control Reg */
+#define PHY_MARV_LED_OVER                   0x19  /* 16 bit r/w  Manual LED Override Reg */
+#define PHY_MARV_EXT_CTRL_2                 0x1a  /* 16 bit r/w  Ext. PHY Specific Ctrl 2 */
+#define PHY_MARV_EXT_P_STAT                 0x1b  /* 16 bit r/w  Ext. PHY Spec. Stat Reg */
+#define PHY_MARV_CABLE_DIAG                 0x1c  /* 16 bit r/o  Cable Diagnostic Reg */
+#define PHY_MARV_PAGE_ADDR                  0x1d  /* 16 bit r/w  Extended Page Address Reg */
+#define PHY_MARV_PAGE_DATA                  0x1e  /* 16 bit r/w  Extended Page Data Reg */
+
+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_MARV_FE_LED_PAR                 0x16  /* 16 bit r/w  LED Parallel Select Reg. */
+#define PHY_MARV_FE_LED_SER                 0x17  /* 16 bit r/w  LED Stream Select S. LED */
+#define PHY_MARV_FE_VCT_TX                  0x1a  /* 16 bit r/w  VCT Reg. for TXP/N Pins */
+#define PHY_MARV_FE_VCT_RX                  0x1b  /* 16 bit r/o  VCT Reg. for RXP/N Pins */
+#define PHY_MARV_FE_SPEC_2                  0x1c  /* 16 bit r/w  Specific Control Reg. 2 */
+
+#define PHY_CT_RESET                        (1<<15)  /* Bit 15: (sc)  clear all PHY related regs */
+#define PHY_CT_LOOP                         (1<<14)  /* Bit 14:  enable Loopback over PHY */
+#define PHY_CT_SPS_LSB                      (1<<13) /* Bit 13:  Speed select, lower bit */
+#define PHY_CT_ANE                          (1<<12)  /* Bit 12:  Auto-Negotiation Enabled */
+#define PHY_CT_PDOWN                        (1<<11)  /* Bit 11:  Power Down Mode */
+#define PHY_CT_ISOL                         (1<<10)  /* Bit 10:  Isolate Mode */
+#define PHY_CT_RE_CFG                       (1<<9)  /* Bit  9:  (sc) Restart Auto-Negotiation */
+#define PHY_CT_DUP_MD                       (1<<8)  /* Bit  8:  Duplex Mode */
+#define PHY_CT_COL_TST                      (1<<7)  /* Bit  7:  Collision Test enabled */
+#define PHY_CT_SPS_MSB                      (1<<6)  /* Bit  6:  Speed select, upper bit */
+
+#define PHY_CT_SP1000                       PHY_CT_SPS_MSB  /* enable speed of 1000 Mbps */
+#define PHY_CT_SP100                        PHY_CT_SPS_LSB  /* enable speed of  100 Mbps */
+#define PHY_CT_SP10                         (0)    /* enable speed of   10 Mbps */
+
+#define PHY_ST_EXT_ST                       (1<<8)  /* Bit  8:  Extended Status Present */
+#define PHY_ST_PRE_SUP                      (1<<6)  /* Bit  6:  Preamble Suppression */
+#define PHY_ST_AN_OVER                      (1<<5)  /* Bit  5:  Auto-Negotiation Over */
+#define PHY_ST_REM_FLT                      (1<<4)  /* Bit  4:  Remote Fault Condition Occured */
+#define PHY_ST_AN_CAP                       (1<<3)  /* Bit  3:  Auto-Negotiation Capability */
+#define PHY_ST_LSYNC                        (1<<2)  /* Bit  2:  Link Synchronized */
+#define PHY_ST_JAB_DET                      (1<<1)  /* Bit  1:  Jabber Detected */
+#define PHY_ST_EXT_REG                      (1<<0)  /* Bit  0:  Extended Register available */
+
+#define PHY_I1_OUI_MSK                      (0x3f<<10)  /* Bit 15..10:  Organization Unique ID */
+#define PHY_I1_MOD_NUM                      (0x3f<<4)  /* Bit  9.. 4:  Model Number */
+#define PHY_I1_REV_MSK                      0xf    /* Bit  3.. 0:  Revision Number */
+
+/* different Marvell PHY Ids */
+#define PHY_MARV_ID0_VAL                    0x0141  /* Marvell Unique Identifier */
+
+#define PHY_MARV_ID1_B0                     0x0C23  /* Yukon (PHY 88E1011) */
+#define PHY_MARV_ID1_B2                     0x0C25  /* Yukon-Plus (PHY 88E1011) */
+#define PHY_MARV_ID1_C2                     0x0CC2  /* Yukon-EC (PHY 88E1111) */
+#define PHY_MARV_ID1_Y2                     0x0C91  /* Yukon-2 (PHY 88E1112) */
+#define PHY_MARV_ID1_FE                     0x0C83  /* Yukon-FE (PHY 88E3082 Rev.A1) */
+#define PHY_MARV_ID1_ECU                    0x0CB0  /* Yukon-2 (PHY 88E1149 Rev.B2?) */
+
+/*****  PHY_MARV_1000T_STAT  16 bit r/o  1000Base-T Status Reg *****/
+#define PHY_B_1000S_MSF                     (1<<15)  /* Bit 15:  Master/Slave Fault */
+#define PHY_B_1000S_MSR                     (1<<14)  /* Bit 14:  Master/Slave Result */
+#define PHY_B_1000S_LRS                     (1<<13)  /* Bit 13:  Local Receiver Status */
+#define PHY_B_1000S_RRS                     (1<<12)  /* Bit 12:  Remote Receiver Status */
+#define PHY_B_1000S_LP_FD                   (1<<11)  /* Bit 11:  Link Partner can FD */
+#define PHY_B_1000S_LP_HD                   (1<<10)  /* Bit 10:  Link Partner can HD */
+#define PHY_B_1000S_IEC                     0xff  /* Bit  7..0:  Idle Error Count */
+
+/*****  PHY_MARV_AUNE_ADV  16 bit r/w  Auto-Negotiation Advertisement *****/
+/*****  PHY_MARV_AUNE_LP  16 bit r/w  Link Part Ability Reg *****/
+#define PHY_M_AN_NXT_PG                     BIT_15  /* Request Next Page */
+#define PHY_M_AN_ACK                        BIT_14  /* (ro)  Acknowledge Received */
+#define PHY_M_AN_RF                         BIT_13  /* Remote Fault */
+#define PHY_M_AN_ASP                        BIT_11  /* Asymmetric Pause */
+#define PHY_M_AN_PC                         BIT_10  /* MAC Pause implemented */
+#define PHY_M_AN_100_T4                     BIT_9  /* Not cap. 100Base-T4 (always 0) */
+#define PHY_M_AN_100_FD                     BIT_8  /* Advertise 100Base-TX Full Duplex */
+#define PHY_M_AN_100_HD                     BIT_7  /* Advertise 100Base-TX Half Duplex */
+#define PHY_M_AN_10_FD                      BIT_6  /* Advertise 10Base-TX Full Duplex */
+#define PHY_M_AN_10_HD                      BIT_5  /* Advertise 10Base-TX Half Duplex */
+#define PHY_M_AN_SEL_MSK                    (0x1f<<4)  /* Bit  4.. 0: Selector Field Mask */
+
+/* special defines for FIBER (88E1011S only) */
+#define PHY_M_AN_ASP_X                      BIT_8  /* Asymmetric Pause */
+#define PHY_M_AN_PC_X                       BIT_7  /* MAC Pause implemented */
+#define PHY_M_AN_1000X_AHD                  BIT_6  /* Advertise 10000Base-X Half Duplex */
+#define PHY_M_AN_1000X_AFD                  BIT_5  /* Advertise 10000Base-X Full Duplex */
+
+/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
+#define PHY_M_P_NO_PAUSE_X                  (0<<7)  /* Bit  8.. 7:  no Pause Mode */
+#define PHY_M_P_SYM_MD_X                    (1<<7)  /* Bit  8.. 7:  symmetric Pause Mode */
+#define PHY_M_P_ASYM_MD_X                   (2<<7)  /* Bit  8.. 7:  asymmetric Pause Mode */
+#define PHY_M_P_BOTH_MD_X                   (3<<7)  /* Bit  8.. 7:  both Pause Mode */
+
+/*****  PHY_MARV_1000T_CTRL  16 bit r/w  1000Base-T Control Reg *****/
+#define PHY_M_1000C_TEST                    (7<<13)  /* Bit 15..13:  Test Modes */
+#define PHY_M_1000C_MSE                     BIT_12  /* Manual Master/Slave Enable */
+#define PHY_M_1000C_MSC                     BIT_11  /* M/S Configuration (1=Master) */
+#define PHY_M_1000C_MPD                     BIT_10  /* Multi-Port Device */
+#define PHY_M_1000C_AFD                     BIT_9  /* Advertise Full Duplex */
+#define PHY_M_1000C_AHD                     BIT_8  /* Advertise Half Duplex */
+
+/*****  PHY_MARV_PHY_CTRL  16 bit r/w  PHY Specific Ctrl Reg *****/
+#define PHY_M_PC_TX_FFD_MSK                 (3<<14)  /* Bit 15..14: Tx FIFO Depth Mask */
+#define PHY_M_PC_RX_FFD_MSK                 (3<<12)  /* Bit 13..12: Rx FIFO Depth Mask */
+#define PHY_M_PC_ASS_CRS_TX                 BIT_11  /* Assert CRS on Transmit */
+#define PHY_M_PC_FL_GOOD                    BIT_10  /* Force Link Good */
+#define PHY_M_PC_EN_DET_MSK                 (3<<8)  /* Bit  9.. 8: Energy Detect Mask */
+#define PHY_M_PC_ENA_EXT_D                  BIT_7  /* Enable Ext. Distance (10BT) */
+#define PHY_M_PC_MDIX_MSK                   (3<<5)  /* Bit  6.. 5: MDI/MDIX Config. Mask */
+#define PHY_M_PC_DIS_125CLK                 BIT_4  /* Disable 125 CLK */
+#define PHY_M_PC_MAC_POW_UP                 BIT_3  /* MAC Power up */
+#define PHY_M_PC_SQE_T_ENA                  BIT_2  /* SQE Test Enabled */
+#define PHY_M_PC_POL_R_DIS                  BIT_1  /* Polarity Reversal Disabled */
+#define PHY_M_PC_DIS_JABBER                 BIT_0  /* Disable Jabber */
+
+#define PHY_M_PC_EN_DET                     SHIFT8(2)  /* Energy Detect (Mode 1) */
+#define PHY_M_PC_EN_DET_PLUS                SHIFT8(3)  /* Energy Detect Plus (Mode 2) */
+
+#define PHY_M_PC_MDI_XMODE(x)               (SHIFT5(x) & PHY_M_PC_MDIX_MSK)
+
+#define PHY_M_PC_MAN_MDI                    0  /* 00 = Manual MDI configuration */
+#define PHY_M_PC_MAN_MDIX                   1  /* 01 = Manual MDIX configuration */
+#define PHY_M_PC_ENA_AUTO                   3  /* 11 = Enable Automatic Crossover */
+
+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
+#define PHY_M_PC_DIS_LINK_P                 BIT_15  /* Disable Link Pulses */
+#define PHY_M_PC_DSC_MSK                    (7<<12)  /* Bit 14..12:  Downshift Counter */
+#define PHY_M_PC_DOWN_S_ENA                 BIT_11  /* Downshift Enable */
+/* !!! Errata in spec. (1 = disable) */
+
+#define PHY_M_PC_DSC(x)                     (SHIFT12(x) & PHY_M_PC_DSC_MSK)
+/* 000=1x; 001=2x; 010=3x; 011=4x */
+/* 100=5x; 101=6x; 110=7x; 111=8x */
+
+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_M_PC_ENA_DTE_DT                 BIT_15  /* Enable Data Terminal Equ. (DTE) Detect */
+#define PHY_M_PC_ENA_ENE_DT                 BIT_14  /* Enable Energy Detect (sense & pulse) */
+#define PHY_M_PC_DIS_NLP_CK                 BIT_13  /* Disable Normal Link Puls (NLP) Check */
+#define PHY_M_PC_ENA_LIP_NP                 BIT_12  /* Enable Link Partner Next Page Reg. */
+#define PHY_M_PC_DIS_NLP_GN                 BIT_11  /* Disable Normal Link Puls Generation */
+#define PHY_M_PC_DIS_SCRAMB                 BIT_9  /* Disable Scrambler */
+#define PHY_M_PC_DIS_FEFI                   BIT_8  /* Disable Far End Fault Indic. (FEFI) */
+#define PHY_M_PC_SH_TP_SEL                  BIT_6  /* Shielded Twisted Pair Select */
+#define PHY_M_PC_RX_FD_MSK                  (3<<2)  /* Bit  3.. 2: Rx FIFO Depth Mask */
+
+/*****  PHY_MARV_PHY_STAT  16 bit r/o  PHY Specific Status Reg *****/
+#define PHY_M_PS_SPEED_MSK                  (3<<14)  /* Bit 15..14: Speed Mask */
+#define PHY_M_PS_SPEED_1000                 BIT_15  /*  10 = 1000 Mbps */
+#define PHY_M_PS_SPEED_100                  BIT_14  /*  01 =  100 Mbps */
+#define PHY_M_PS_SPEED_10                   0  /*  00 =   10 Mbps */
+#define PHY_M_PS_FULL_DUP                   BIT_13  /* Full Duplex */
+#define PHY_M_PS_PAGE_REC                   BIT_12  /* Page Received */
+#define PHY_M_PS_SPDUP_RES                  BIT_11  /* Speed & Duplex Resolved */
+#define PHY_M_PS_LINK_UP                    BIT_10  /* Link Up */
+#define PHY_M_PS_CABLE_MSK                  (7<<7)  /* Bit  9.. 7: Cable Length Mask */
+#define PHY_M_PS_MDI_X_STAT                 BIT_6  /* MDI Crossover Stat (1=MDIX) */
+#define PHY_M_PS_DOWNS_STAT                 BIT_5  /* Downshift Status (1=downsh.) */
+#define PHY_M_PS_ENDET_STAT                 BIT_4  /* Energy Detect Status (1=act) */
+#define PHY_M_PS_TX_P_EN                    BIT_3  /* Tx Pause Enabled */
+#define PHY_M_PS_RX_P_EN                    BIT_2  /* Rx Pause Enabled */
+#define PHY_M_PS_POL_REV                    BIT_1  /* Polarity Reversed */
+#define PHY_M_PS_JABBER                     BIT_0  /* Jabber */
+
+#define PHY_M_PS_PAUSE_MSK                  (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
+
+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+#define PHY_M_PS_DTE_DETECT                 BIT_15  /* Data Terminal Equipment (DTE) Detected */
+#define PHY_M_PS_RES_SPEED                  BIT_14  /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
+
+/*****  PHY_MARV_INT_MASK  16 bit r/w  Interrupt Mask Reg *****/
+/*****  PHY_MARV_INT_STAT  16 bit r/o  Interrupt Status Reg *****/
+#define PHY_M_IS_AN_ERROR                   BIT_15  /* Auto-Negotiation Error */
+#define PHY_M_IS_LSP_CHANGE                 BIT_14  /* Link Speed Changed */
+#define PHY_M_IS_DUP_CHANGE                 BIT_13  /* Duplex Mode Changed */
+#define PHY_M_IS_AN_PR                      BIT_12  /* Page Received */
+#define PHY_M_IS_AN_COMPL                   BIT_11  /* Auto-Negotiation Completed */
+#define PHY_M_IS_LST_CHANGE                 BIT_10  /* Link Status Changed */
+#define PHY_M_IS_SYMB_ERROR                 BIT_9  /* Symbol Error */
+#define PHY_M_IS_FALSE_CARR                 BIT_8  /* False Carrier */
+#define PHY_M_IS_FIFO_ERROR                 BIT_7  /* FIFO Overflow/Underrun Error */
+#define PHY_M_IS_MDI_CHANGE                 BIT_6  /* MDI Crossover Changed */
+#define PHY_M_IS_DOWNSH_DET                 BIT_5  /* Downshift Detected */
+#define PHY_M_IS_END_CHANGE                 BIT_4  /* Energy Detect Changed */
+#define PHY_M_IS_DTE_CHANGE                 BIT_2  /* DTE Power Det. Status Changed */
+#define PHY_M_IS_POL_CHANGE                 BIT_1  /* Polarity Changed */
+#define PHY_M_IS_JABBER                     BIT_0  /* Jabber */
+
+#define PHY_M_DEF_MSK                       (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
+
+/*****  PHY_MARV_EXT_CTRL  16 bit r/w  Ext. PHY Specific Ctrl *****/
+#define PHY_M_EC_ENA_BC_EXT                 BIT_15  /* Enable Block Carr. Ext. (88E1111 only) */
+#define PHY_M_EC_ENA_LIN_LB                 BIT_14  /* Enable Line Loopback (88E1111 only) */
+#define PHY_M_EC_DIS_LINK_P                 BIT_12  /* Disable Link Pulses (88E1111 only) */
+#define PHY_M_EC_M_DSC_MSK                  (3<<10)  /* Bit 11..10:  Master Downshift Counter */
+/* (88E1011 only) */
+#define PHY_M_EC_S_DSC_MSK                  (3<<8)  /* Bit  9.. 8:  Slave  Downshift Counter */
+/* (88E1011 only) */
+#define PHY_M_EC_DSC_MSK_2                  (7<<9)  /* Bit 11.. 9:  Downshift Counter */
+/* (88E1111 only) */
+#define PHY_M_EC_DOWN_S_ENA                 BIT_8  /* Downshift Enable (88E1111 only) */
+/* !!! Errata in spec. (1 = disable) */
+#define PHY_M_EC_RX_TIM_CT                  BIT_7  /* RGMII Rx Timing Control*/
+#define PHY_M_EC_MAC_S_MSK                  (7<<4)  /* Bit  6.. 4:  Def. MAC interface speed */
+#define PHY_M_EC_FIB_AN_ENA                 BIT_3  /* Fiber Auto-Neg. Enable (88E1011S only) */
+#define PHY_M_EC_DTE_D_ENA                  BIT_2  /* DTE Detect Enable (88E1111 only) */
+#define PHY_M_EC_TX_TIM_CT                  BIT_1  /* RGMII Tx Timing Control */
+#define PHY_M_EC_TRANS_DIS                  BIT_0  /* Transmitter Disable (88E1111 only) */
+
+#define PHY_M_EC_M_DSC(x)                    (SHIFT10 (x) & PHY_M_EC_M_DSC_MSK)
+/* 00=1x; 01=2x; 10=3x; 11=4x */
+#define PHY_M_EC_S_DSC(x)                   (SHIFT8 (x) & PHY_M_EC_S_DSC_MSK)
+/* 00=dis; 01=1x; 10=2x; 11=3x */
+#define PHY_M_EC_MAC_S(x)                   (SHIFT4 (x) & PHY_M_EC_MAC_S_MSK)
+/* 01X=0; 110=2.5; 111=25 (MHz) */
+
+#define PHY_M_EC_DSC_2(x)                   (SHIFT9 (x) & PHY_M_EC_DSC_MSK_2)
+/* 000=1x; 001=2x; 010=3x; 011=4x */
+/* 100=5x; 101=6x; 110=7x; 111=8x */
+#define MAC_TX_CLK_0_MHZ                    2
+#define MAC_TX_CLK_2_5_MHZ                  6
+#define MAC_TX_CLK_25_MHZ                   7
+
+/*****  PHY_MARV_LED_CTRL  16 bit r/w  LED Control Reg *****/
+#define PHY_M_LEDC_DIS_LED                  BIT_15  /* Disable LED */
+#define PHY_M_LEDC_PULS_MSK                 (7<<12)  /* Bit 14..12: Pulse Stretch Mask */
+#define PHY_M_LEDC_F_INT                    BIT_11  /* Force Interrupt */
+#define PHY_M_LEDC_BL_R_MSK                 (7<<8)  /* Bit 10.. 8: Blink Rate Mask */
+#define PHY_M_LEDC_DP_C_LSB                 BIT_7  /* Duplex Control (LSB, 88E1111 only) */
+#define PHY_M_LEDC_TX_C_LSB                 BIT_6  /* Tx Control (LSB, 88E1111 only) */
+#define PHY_M_LEDC_LK_C_MSK                 (7<<3)  /* Bit  5.. 3: Link Control Mask */
+/* (88E1111 only) */
+#define PHY_M_LEDC_LINK_MSK                 (3<<3)  /* Bit  4.. 3: Link Control Mask */
+/* (88E1011 only) */
+#define PHY_M_LEDC_DP_CTRL                  BIT_2  /* Duplex Control */
+#define PHY_M_LEDC_DP_C_MSB                 BIT_2  /* Duplex Control (MSB, 88E1111 only) */
+#define PHY_M_LEDC_RX_CTRL                  BIT_1  /* Rx Activity / Link */
+#define PHY_M_LEDC_TX_CTRL                  BIT_0  /* Tx Activity / Link */
+#define PHY_M_LEDC_TX_C_MSB                 BIT_0  /* Tx Control (MSB, 88E1111 only) */
+
+#define PHY_M_LED_PULS_DUR(x)               (SHIFT12 (x) & PHY_M_LEDC_PULS_MSK)
+
+#define PULS_NO_STR                         0  /* no pulse stretching */
+#define PULS_21MS                           1  /* 21 ms to 42 ms */
+#define PULS_42MS                           2  /* 42 ms to 84 ms */
+#define PULS_84MS                           3  /* 84 ms to 170 ms */
+#define PULS_170MS                          4  /* 170 ms to 340 ms */
+#define PULS_340MS                          5  /* 340 ms to 670 ms */
+#define PULS_670MS                          6  /* 670 ms to 1.3 s */
+#define PULS_1300MS                         7  /* 1.3 s to 2.7 s */
+
+#define PHY_M_LED_BLINK_RT(x)                (SHIFT8 (x) & PHY_M_LEDC_BL_R_MSK)
+
+#define BLINK_42MS                          0  /* 42 ms */
+#define BLINK_84MS                          1  /* 84 ms */
+#define BLINK_170MS                         2  /* 170 ms */
+#define BLINK_340MS                         3  /* 340 ms */
+#define BLINK_670MS                         4  /* 670 ms */
+
+/*****  PHY_MARV_LED_OVER  16 bit r/w  Manual LED Override Reg *****/
+#define PHY_M_LED_MO_SGMII(x)               SHIFT14 (x)  /* Bit 15..14:  SGMII AN Timer */
+#define PHY_M_LED_MO_DUP(x)                 SHIFT10 (x)  /* Bit 11..10:  Duplex */
+#define PHY_M_LED_MO_10(x)                  SHIFT8 (x)  /* Bit  9.. 8:  Link 10 */
+#define PHY_M_LED_MO_100(x)                 SHIFT6 (x)  /* Bit  7.. 6:  Link 100 */
+#define PHY_M_LED_MO_1000(x)                SHIFT4 (x)  /* Bit  5.. 4:  Link 1000 */
+#define PHY_M_LED_MO_RX(x)                  SHIFT2 (x)  /* Bit  3.. 2:  Rx */
+#define PHY_M_LED_MO_TX(x)                  SHIFT0 (x)  /* Bit  1.. 0:  Tx */
+
+#define MO_LED_NORM                         0
+#define MO_LED_BLINK                        1
+#define MO_LED_OFF                          2
+#define MO_LED_ON                           3
+
+/*****  PHY_MARV_EXT_CTRL_2  16 bit r/w  Ext. PHY Specific Ctrl 2 *****/
+#define PHY_M_EC2_FI_IMPED                  BIT_6  /* Fiber Input  Impedance */
+#define PHY_M_EC2_FO_IMPED                  BIT_5  /* Fiber Output Impedance */
+#define PHY_M_EC2_FO_M_CLK                  BIT_4  /* Fiber Mode Clock Enable */
+#define PHY_M_EC2_FO_BOOST                  BIT_3  /* Fiber Output Boost */
+#define PHY_M_EC2_FO_AM_MSK                  7  /* Bit  2.. 0:  Fiber Output Amplitude */
+
+/*****  PHY_MARV_EXT_P_STAT 16 bit r/w  Ext. PHY Specific Status *****/
+#define PHY_M_FC_AUTO_SEL                   BIT_15  /* Fiber/Copper Auto Sel. Dis. */
+#define PHY_M_FC_AN_REG_ACC                 BIT_14  /* Fiber/Copper AN Reg. Access */
+#define PHY_M_FC_RESOLUTION                 BIT_13  /* Fiber/Copper Resolution */
+#define PHY_M_SER_IF_AN_BP                  BIT_12  /* Ser. IF AN Bypass Enable */
+#define PHY_M_SER_IF_BP_ST                  BIT_11  /* Ser. IF AN Bypass Status */
+#define PHY_M_IRQ_POLARITY                  BIT_10  /* IRQ polarity */
+#define PHY_M_DIS_AUT_MED                   BIT_9  /* Disable Aut. Medium Reg. Selection */
+/* (88E1111 only) */
+#define PHY_M_UNDOC1                        BIT_7  /* undocumented bit !! */
+#define PHY_M_DTE_POW_STAT                  BIT_4  /* DTE Power Status (88E1111 only) */
+#define PHY_M_MODE_MASK                     0xf  /* Bit  3.. 0: copy of HWCFG MODE[3:0] */
+
+/*****  PHY_MARV_CABLE_DIAG  16 bit r/o  Cable Diagnostic Reg *****/
+#define PHY_M_CABD_ENA_TEST                 BIT_15  /* Enable Test (Page 0) */
+#define PHY_M_CABD_DIS_WAIT                 BIT_15  /* Disable Waiting Period (Page 1) */
+/* (88E1111 only) */
+#define PHY_M_CABD_STAT_MSK                 (3<<13)    /* Bit 14..13: Status Mask */
+#define PHY_M_CABD_AMPL_MSK                 (0x1f<<8)  /* Bit 12.. 8: Amplitude Mask */
+/* (88E1111 only) */
+#define PHY_M_CABD_DIST_MSK                 0xff    /* Bit  7.. 0: Distance Mask */
+
+/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
+#define CABD_STAT_NORMAL                    0
+#define CABD_STAT_SHORT                     1
+#define CABD_STAT_OPEN                      2
+#define CABD_STAT_FAIL                      3
+
+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
+/*****  PHY_MARV_FE_LED_PAR  16 bit r/w  LED Parallel Select Reg. *****/
+#define PHY_M_FELP_LED2_MSK                 (0xf<<8)  /* Bit 11.. 8: LED2 Mask (LINK) */
+#define PHY_M_FELP_LED1_MSK                 (0xf<<4)  /* Bit  7.. 4: LED1 Mask (ACT) */
+#define PHY_M_FELP_LED0_MSK                 0xf    /* Bit  3.. 0: LED0 Mask (SPEED) */
+
+#define PHY_M_FELP_LED2_CTRL(x)             (SHIFT8 (x) & PHY_M_FELP_LED2_MSK)
+#define PHY_M_FELP_LED1_CTRL(x)             (SHIFT4 (x) & PHY_M_FELP_LED1_MSK)
+#define PHY_M_FELP_LED0_CTRL(x)             (SHIFT0 (x) & PHY_M_FELP_LED0_MSK)
+
+#define LED_PAR_CTRL_COLX                   0x00
+#define LED_PAR_CTRL_ERROR                  0x01
+#define LED_PAR_CTRL_DUPLEX                 0x02
+#define LED_PAR_CTRL_DP_COL                 0x03
+#define LED_PAR_CTRL_SPEED                  0x04
+#define LED_PAR_CTRL_LINK                   0x05
+#define LED_PAR_CTRL_TX                     0x06
+#define LED_PAR_CTRL_RX                     0x07
+#define LED_PAR_CTRL_ACT                    0x08
+#define LED_PAR_CTRL_LNK_RX                 0x09
+#define LED_PAR_CTRL_LNK_AC                 0x0a
+#define LED_PAR_CTRL_ACT_BL                 0x0b
+#define LED_PAR_CTRL_TX_BL                  0x0c
+#define LED_PAR_CTRL_RX_BL                  0x0d
+#define LED_PAR_CTRL_COL_BL                 0x0e
+#define LED_PAR_CTRL_INACT                  0x0f
+
+/*****  PHY_MARV_FE_SPEC_2  16 bit r/w Specific Control Reg. 2 *****/
+#define PHY_M_FESC_DIS_WAIT                 BIT_2  /* Disable TDR Waiting Period */
+#define PHY_M_FESC_ENA_MCLK                 BIT_1  /* Enable MAC Rx Clock in sleep mode */
+#define PHY_M_FESC_SEL_CL_A                 BIT_0  /* Select Class A driver (100B-TX) */
+
+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
+/*****  PHY_MARV_PHY_CTRL (page 1)  16 bit r/w Fiber Specific Ctrl *****/
+#define PHY_M_FIB_FORCE_LNK                 BIT_10  /* Force Link Good */
+#define PHY_M_FIB_SIGD_POL                  BIT_9  /* SIGDET Polarity */
+#define PHY_M_FIB_TX_DIS                    BIT_3  /* Transmitter Disable */
+
+/*****  PHY_MARV_PHY_CTRL (page 2)  16 bit r/w MAC Specific Ctrl *****/
+#define PHY_M_MAC_MD_MSK                    (7<<7)  /* Bit  9.. 7: Mode Select Mask */
+#define PHY_M_MAC_MD_AUTO                   3  /* Auto Copper/1000Base-X */
+#define PHY_M_MAC_MD_COPPER                 5  /* Copper only */
+#define PHY_M_MAC_MD_1000BX                 7  /* 1000Base-X only */
+#define PHY_M_MAC_MODE_SEL(x)               (SHIFT7 (x) & PHY_M_MAC_MD_MSK)
+
+/*****  PHY_MARV_PHY_CTRL (page 3)  16 bit r/w LED Control Reg. *****/
+#define PHY_M_LEDC_LOS_MSK                  (0xf<<12)  /* Bit 15..12: LOS LED Ctrl. Mask */
+#define PHY_M_LEDC_INIT_MSK                 (0xf<<8)  /* Bit 11.. 8: INIT LED Ctrl. Mask */
+#define PHY_M_LEDC_STA1_MSK                 (0xf<<4)  /* Bit  7.. 4: STAT1 LED Ctrl. Mask */
+#define PHY_M_LEDC_STA0_MSK                 0xf    /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
+
+#define PHY_M_LEDC_LOS_CTRL(x)              (SHIFT12 (x) & PHY_M_LEDC_LOS_MSK)
+#define PHY_M_LEDC_INIT_CTRL(x)             (SHIFT8 (x) & PHY_M_LEDC_INIT_MSK)
+#define PHY_M_LEDC_STA1_CTRL(x)             (SHIFT4 (x) & PHY_M_LEDC_STA1_MSK)
+#define PHY_M_LEDC_STA0_CTRL(x)             (SHIFT0 (x) & PHY_M_LEDC_STA0_MSK)
+
+/*****  PHY_MARV_PHY_STAT (page 3)  16 bit r/w Polarity Control Reg. *****/
+#define PHY_M_POLC_LS1M_MSK                 (0xf<<12)  /* Bit 15..12: LOS,STAT1 Mix % Mask */
+#define PHY_M_POLC_IS0M_MSK                 (0xf<<8)  /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
+#define PHY_M_POLC_LOS_MSK                  (0x3<<6)  /* Bit  7.. 6: LOS Pol. Ctrl. Mask */
+#define PHY_M_POLC_INIT_MSK                 (0x3<<4)  /* Bit  5.. 4: INIT Pol. Ctrl. Mask */
+#define PHY_M_POLC_STA1_MSK                 (0x3<<2)  /* Bit  3.. 2: STAT1 Pol. Ctrl. Mask */
+#define PHY_M_POLC_STA0_MSK                 0x3    /* Bit  1.. 0: STAT0 Pol. Ctrl. Mask */
+
+#define PHY_M_POLC_LS1_P_MIX(x)             (SHIFT12 (x) & PHY_M_POLC_LS1M_MSK)
+#define PHY_M_POLC_IS0_P_MIX(x)             (SHIFT8 (x) & PHY_M_POLC_IS0M_MSK)
+#define PHY_M_POLC_LOS_CTRL(x)              (SHIFT6 (x) & PHY_M_POLC_LOS_MSK)
+#define PHY_M_POLC_INIT_CTRL(x)             (SHIFT4 (x) & PHY_M_POLC_INIT_MSK)
+#define PHY_M_POLC_STA1_CTRL(x)             (SHIFT2 (x) & PHY_M_POLC_STA1_MSK)
+#define PHY_M_POLC_STA0_CTRL(x)             (SHIFT0 (x) & PHY_M_POLC_STA0_MSK)
+
+/*
+ * GMAC registers
+ *
+ * The GMAC registers are 16 or 32 bits wide.
+ * The GMACs host processor interface is 16 bits wide,
+ * therefore ALL registers will be addressed with 16 bit accesses.
+ *
+ * Note:  NA reg  = Network Address e.g DA, SA etc.
+ */
+
+/* Port Registers */
+#define GM_GP_STAT                          0x0000  /* 16 bit r/o  General Purpose Status */
+#define GM_GP_CTRL                          0x0004  /* 16 bit r/w  General Purpose Control */
+#define GM_TX_CTRL                          0x0008  /* 16 bit r/w  Transmit Control Reg. */
+#define GM_RX_CTRL                          0x000c  /* 16 bit r/w  Receive Control Reg. */
+#define GM_TX_FLOW_CTRL                     0x0010  /* 16 bit r/w  Transmit Flow-Control */
+#define GM_TX_PARAM                         0x0014  /* 16 bit r/w  Transmit Parameter Reg. */
+#define GM_SERIAL_MODE                      0x0018  /* 16 bit r/w  Serial Mode Register */
+
+/* Source Address Registers */
+#define GM_SRC_ADDR_1L                      0x001c  /* 16 bit r/w  Source Address 1 (low) */
+#define GM_SRC_ADDR_1M                      0x0020  /* 16 bit r/w  Source Address 1 (middle) */
+#define GM_SRC_ADDR_1H                      0x0024  /* 16 bit r/w  Source Address 1 (high) */
+#define GM_SRC_ADDR_2L                      0x0028  /* 16 bit r/w  Source Address 2 (low) */
+#define GM_SRC_ADDR_2M                      0x002c  /* 16 bit r/w  Source Address 2 (middle) */
+#define GM_SRC_ADDR_2H                      0x0030  /* 16 bit r/w  Source Address 2 (high) */
+
+/* Multicast Address Hash Registers */
+#define GM_MC_ADDR_H1                       0x0034  /* 16 bit r/w  Multicast Address Hash 1 */
+#define GM_MC_ADDR_H2                       0x0038  /* 16 bit r/w  Multicast Address Hash 2 */
+#define GM_MC_ADDR_H3                       0x003c  /* 16 bit r/w  Multicast Address Hash 3 */
+#define GM_MC_ADDR_H4                       0x0040  /* 16 bit r/w  Multicast Address Hash 4 */
+
+/* Interrupt Source Registers */
+#define GM_TX_IRQ_SRC                       0x0044  /* 16 bit r/o  Tx Overflow IRQ Source */
+#define GM_RX_IRQ_SRC                       0x0048  /* 16 bit r/o  Rx Overflow IRQ Source */
+#define GM_TR_IRQ_SRC                       0x004c  /* 16 bit r/o  Tx/Rx Over. IRQ Source */
+
+/* Interrupt Mask Registers */
+#define GM_TX_IRQ_MSK                       0x0050  /* 16 bit r/w  Tx Overflow IRQ Mask */
+#define GM_RX_IRQ_MSK                       0x0054  /* 16 bit r/w  Rx Overflow IRQ Mask */
+#define GM_TR_IRQ_MSK                       0x0058  /* 16 bit r/w  Tx/Rx Over. IRQ Mask */
+
+/* Serial Management Interface (SMI) Registers */
+#define GM_SMI_CTRL                         0x0080  /* 16 bit r/w  SMI Control Register */
+#define GM_SMI_DATA                         0x0084  /* 16 bit r/w  SMI Data Register */
+#define GM_PHY_ADDR                         0x0088  /* 16 bit r/w  GPHY Address Register */
+
+/* MIB Counters */
+#define GM_MIB_CNT_BASE                     0x0100  /* Base Address of MIB Counters */
+#define GM_MIB_CNT_SIZE                     44  /* Number of MIB Counters */
+
+/*
+ * MIB Counters base address definitions (low word) -
+ * use offset 4 for access to high word  (32 bit r/o)
+ */
+#define GM_RXF_UC_OK                        (GM_MIB_CNT_BASE + 0)  /* Unicast Frames Received OK */
+#define GM_RXF_BC_OK                        (GM_MIB_CNT_BASE + 8)  /* Broadcast Frames Received OK */
+#define GM_RXF_MPAUSE                       (GM_MIB_CNT_BASE + 16)  /* Pause MAC Ctrl Frames Received */
+#define GM_RXF_MC_OK                        (GM_MIB_CNT_BASE + 24)  /* Multicast Frames Received OK */
+#define GM_RXF_FCS_ERR                      (GM_MIB_CNT_BASE + 32)  /* Rx Frame Check Seq. Error */
+#define GM_RXF_SPARE1                       (GM_MIB_CNT_BASE + 40)  /* Rx spare 1 */
+#define GM_RXO_OK_LO                        (GM_MIB_CNT_BASE + 48)  /* Octets Received OK Low */
+#define GM_RXO_OK_HI                        (GM_MIB_CNT_BASE + 56)  /* Octets Received OK High */
+#define GM_RXO_ERR_LO                       (GM_MIB_CNT_BASE + 64)  /* Octets Received Invalid Low */
+#define GM_RXO_ERR_HI                       (GM_MIB_CNT_BASE + 72)  /* Octets Received Invalid High */
+#define GM_RXF_SHT                          (GM_MIB_CNT_BASE + 80)  /* Frames <64 Byte Received OK */
+#define GM_RXE_FRAG                         (GM_MIB_CNT_BASE + 88)  /* Frames <64 Byte Received with FCS Err */
+#define GM_RXF_64B                          (GM_MIB_CNT_BASE + 96)  /* 64 Byte Rx Frame */
+#define GM_RXF_127B                         (GM_MIB_CNT_BASE + 104)  /* 65-127 Byte Rx Frame */
+#define GM_RXF_255B                         (GM_MIB_CNT_BASE + 112)  /* 128-255 Byte Rx Frame */
+#define GM_RXF_511B                         (GM_MIB_CNT_BASE + 120)  /* 256-511 Byte Rx Frame */
+#define GM_RXF_1023B                        (GM_MIB_CNT_BASE + 128)  /* 512-1023 Byte Rx Frame */
+#define GM_RXF_1518B                        (GM_MIB_CNT_BASE + 136)  /* 1024-1518 Byte Rx Frame */
+#define GM_RXF_MAX_SZ                       (GM_MIB_CNT_BASE + 144)  /* 1519-MaxSize Byte Rx Frame */
+#define GM_RXF_LNG_ERR                      (GM_MIB_CNT_BASE + 152)  /* Rx Frame too Long Error */
+#define GM_RXF_JAB_PKT                      (GM_MIB_CNT_BASE + 160)  /* Rx Jabber Packet Frame */
+#define GM_RXF_SPARE2                       (GM_MIB_CNT_BASE + 168)  /* Rx spare 2 */
+#define GM_RXE_FIFO_OV                      (GM_MIB_CNT_BASE + 176)  /* Rx FIFO overflow Event */
+#define GM_RXF_SPARE3                       (GM_MIB_CNT_BASE + 184)  /* Rx spare 3 */
+#define GM_TXF_UC_OK                        (GM_MIB_CNT_BASE + 192)  /* Unicast Frames Xmitted OK */
+#define GM_TXF_BC_OK                        (GM_MIB_CNT_BASE + 200)  /* Broadcast Frames Xmitted OK */
+#define GM_TXF_MPAUSE                       (GM_MIB_CNT_BASE + 208)  /* Pause MAC Ctrl Frames Xmitted */
+#define GM_TXF_MC_OK                        (GM_MIB_CNT_BASE + 216)  /* Multicast Frames Xmitted OK */
+#define GM_TXO_OK_LO                        (GM_MIB_CNT_BASE + 224)  /* Octets Transmitted OK Low */
+#define GM_TXO_OK_HI                        (GM_MIB_CNT_BASE + 232)  /* Octets Transmitted OK High */
+#define GM_TXF_64B                          (GM_MIB_CNT_BASE + 240)  /* 64 Byte Tx Frame */
+#define GM_TXF_127B                         (GM_MIB_CNT_BASE + 248)  /* 65-127 Byte Tx Frame */
+#define GM_TXF_255B                         (GM_MIB_CNT_BASE + 256)  /* 128-255 Byte Tx Frame */
+#define GM_TXF_511B                         (GM_MIB_CNT_BASE + 264)  /* 256-511 Byte Tx Frame */
+#define GM_TXF_1023B                        (GM_MIB_CNT_BASE + 272)  /* 512-1023 Byte Tx Frame */
+#define GM_TXF_1518B                        (GM_MIB_CNT_BASE + 280)  /* 1024-1518 Byte Tx Frame */
+#define GM_TXF_MAX_SZ                       (GM_MIB_CNT_BASE + 288)  /* 1519-MaxSize Byte Tx Frame */
+#define GM_TXF_SPARE1                       (GM_MIB_CNT_BASE + 296)  /* Tx spare 1 */
+#define GM_TXF_COL                          (GM_MIB_CNT_BASE + 304)  /* Tx Collision */
+#define GM_TXF_LAT_COL                      (GM_MIB_CNT_BASE + 312)  /* Tx Late Collision */
+#define GM_TXF_ABO_COL                      (GM_MIB_CNT_BASE + 320)  /* Tx aborted due to Exces. Col. */
+#define GM_TXF_MUL_COL                      (GM_MIB_CNT_BASE + 328)  /* Tx Multiple Collision */
+#define GM_TXF_SNG_COL                      (GM_MIB_CNT_BASE + 336)  /* Tx Single Collision */
+#define GM_TXE_FIFO_UR                      (GM_MIB_CNT_BASE + 344)  /* Tx FIFO Underrun Event */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * GMAC Bit Definitions
+ *
+ * If the bit access behaviour differs from the register access behaviour
+ * (r/w, r/o) this is documented after the bit number.
+ * The following bit access behaviours are used:
+ *  (sc)  self clearing
+ *  (r/o)  read only
+ */
+
+/*  GM_GP_STAT  16 bit r/o  General Purpose Status Register */
+#define GM_GPSR_SPEED                       BIT_15  /* Port Speed (1 = 100 Mbps) */
+#define GM_GPSR_DUPLEX                      BIT_14  /* Duplex Mode (1 = Full) */
+#define GM_GPSR_FC_TX_DIS                   BIT_13  /* Tx Flow-Control Mode Disabled */
+#define GM_GPSR_LINK_UP                     BIT_12  /* Link Up Status */
+#define GM_GPSR_PAUSE                       BIT_11  /* Pause State */
+#define GM_GPSR_TX_ACTIVE                   BIT_10  /* Tx in Progress */
+#define GM_GPSR_EXC_COL                     BIT_9  /* Excessive Collisions Occured */
+#define GM_GPSR_LAT_COL                     BIT_8  /* Late Collisions Occured */
+#define GM_GPSR_PHY_ST_CH                   BIT_5  /* PHY Status Change */
+#define GM_GPSR_GIG_SPEED                   BIT_4  /* Gigabit Speed (1 = 1000 Mbps) */
+#define GM_GPSR_PART_MODE                   BIT_3  /* Partition mode */
+#define GM_GPSR_FC_RX_DIS                   BIT_2  /* Rx Flow-Control Mode Disabled */
+
+/*  GM_GP_CTRL  16 bit r/w  General Purpose Control Register */
+#define GM_GPCR_RMII_PH_ENA                 BIT_15  /* Enable RMII for PHY (Yukon-FE only) */
+#define GM_GPCR_RMII_LB_ENA                 BIT_14  /* Enable RMII Loopback (Yukon-FE only) */
+#define GM_GPCR_FC_TX_DIS                   BIT_13  /* Disable Tx Flow-Control Mode */
+#define GM_GPCR_TX_ENA                      BIT_12  /* Enable Transmit */
+#define GM_GPCR_RX_ENA                      BIT_11  /* Enable Receive */
+#define GM_GPCR_LOOP_ENA                    BIT_9  /* Enable MAC Loopback Mode */
+#define GM_GPCR_PART_ENA                    BIT_8  /* Enable Partition Mode */
+#define GM_GPCR_GIGS_ENA                    BIT_7  /* Gigabit Speed (1000 Mbps) */
+#define GM_GPCR_FL_PASS                     BIT_6  /* Force Link Pass */
+#define GM_GPCR_DUP_FULL                    BIT_5  /* Full Duplex Mode */
+#define GM_GPCR_FC_RX_DIS                   BIT_4  /* Disable Rx Flow-Control Mode */
+#define GM_GPCR_SPEED_100                   BIT_3  /* Port Speed 100 Mbps */
+#define GM_GPCR_AU_DUP_DIS                  BIT_2  /* Disable Auto-Update Duplex */
+#define GM_GPCR_AU_FCT_DIS                  BIT_1  /* Disable Auto-Update Flow-C. */
+#define GM_GPCR_AU_SPD_DIS                  BIT_0  /* Disable Auto-Update Speed */
+
+#define GM_GPCR_SPEED_1000                  (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
+#define GM_GPCR_AU_ALL_DIS                  (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | GM_GPCR_AU_SPD_DIS)
+
+/*  GM_TX_CTRL  16 bit r/w  Transmit Control Register */
+#define GM_TXCR_FORCE_JAM                    BIT_15  /* Force Jam / Flow-Control */
+#define GM_TXCR_CRC_DIS                      BIT_14  /* Disable insertion of CRC */
+#define GM_TXCR_PAD_DIS                      BIT_13  /* Disable padding of packets */
+#define GM_TXCR_COL_THR_MSK                  (7<<10)  /* Bit 12..10: Collision Threshold Mask */
+#define GM_TXCR_PAD_PAT_MSK                  0xff  /* Bit  7.. 0: Padding Pattern Mask */
+/* (Yukon-2 only) */
+
+#define TX_COL_THR(x)                       (SHIFT10 (x) & GM_TXCR_COL_THR_MSK)
+#define TX_COL_DEF                          0x04
+
+/*  GM_RX_CTRL  16 bit r/w  Receive Control Register */
+#define GM_RXCR_UCF_ENA                      BIT_15  /* Enable Unicast filtering */
+#define GM_RXCR_MCF_ENA                      BIT_14  /* Enable Multicast filtering */
+#define GM_RXCR_CRC_DIS                      BIT_13  /* Remove 4-byte CRC */
+#define GM_RXCR_PASS_FC                      BIT_12  /* Pass FC packets to FIFO (Yukon-1 only) */
+
+/*  GM_TX_PARAM  16 bit r/w  Transmit Parameter Register */
+#define GM_TXPA_JAMLEN_MSK                  (3<<14)    /* Bit 15..14: Jam Length Mask */
+#define GM_TXPA_JAMIPG_MSK                  (0x1f<<9)  /* Bit 13.. 9: Jam IPG Mask */
+#define GM_TXPA_JAMDAT_MSK                  (0x1f<<4)  /* Bit  8.. 4: IPG Jam to Data Mask */
+#define GM_TXPA_BO_LIM_MSK                  0x0f    /* Bit  3.. 0: Backoff Limit Mask */
+/* (Yukon-2 only) */
+
+#define TX_JAM_LEN_VAL(x)                   (SHIFT14 (x) & GM_TXPA_JAMLEN_MSK)
+#define TX_JAM_IPG_VAL(x)                   (SHIFT9 (x) & GM_TXPA_JAMIPG_MSK)
+#define TX_IPG_JAM_DATA(x)                  (SHIFT4  (x) & GM_TXPA_JAMDAT_MSK)
+#define TX_BACK_OFF_LIM(x)                  ((x) & GM_TXPA_BO_LIM_MSK)
+
+#define TX_JAM_LEN_DEF                      0x03
+#define TX_JAM_IPG_DEF                      0x0b
+#define TX_IPG_JAM_DEF                      0x1c
+#define TX_BOF_LIM_DEF                      0x04
+
+/*  GM_SERIAL_MODE  16 bit r/w  Serial Mode Register */
+#define GM_SMOD_DATABL_MSK                  (0x1f<<11)  /* Bit 15..11:  Data Blinder */
+/* r/o on Yukon, r/w on Yukon-EC */
+#define GM_SMOD_LIMIT_4                     BIT_10  /* 4 consecutive Tx trials */
+#define GM_SMOD_VLAN_ENA                    BIT_9  /* Enable VLAN  (Max. Frame Len) */
+#define GM_SMOD_JUMBO_ENA                   BIT_8  /* Enable Jumbo (Max. Frame Len) */
+#define GM_SMOD_IPG_MSK                     0x1f  /* Bit  4.. 0:  Inter-Packet Gap (IPG) */
+
+#define DATA_BLIND_VAL(x)                   (SHIFT11 (x) & GM_SMOD_DATABL_MSK)
+#define IPG_DATA_VAL(x)                     ((x) & GM_SMOD_IPG_MSK)
+
+#define DATA_BLIND_DEF                      0x04
+#define IPG_DATA_DEF                        0x1e
+
+/*  GM_SMI_CTRL  16 bit r/w  SMI Control Register */
+#define GM_SMI_CT_PHY_A_MSK                 (0x1f<<11)  /* Bit 15..11:  PHY Device Address */
+#define GM_SMI_CT_REG_A_MSK                 (0x1f<<6)  /* Bit 10.. 6:  PHY Register Address */
+#define GM_SMI_CT_OP_RD                     BIT_5  /* OpCode Read (0=Write)*/
+#define GM_SMI_CT_RD_VAL                    BIT_4  /* Read Valid (Read completed) */
+#define GM_SMI_CT_BUSY                      BIT_3  /* Busy (Operation in progress) */
+
+#define GM_SMI_CT_PHY_AD(x)                 (SHIFT11 (x) & GM_SMI_CT_PHY_A_MSK)
+#define GM_SMI_CT_REG_AD(x)                 (SHIFT6 (x) & GM_SMI_CT_REG_A_MSK)
+
+/*  GM_PHY_ADDR  16 bit r/w  GPHY Address Register */
+#define GM_PAR_MIB_CLR                      BIT_5  /* Set MIB Clear Counter Mode */
+#define GM_PAR_MIB_TST                      BIT_4  /* MIB Load Counter (Test Mode) */
+
+/* Receive Frame Status Encoding */
+#define GMR_FS_LEN_MSK                      (0xffff<<16)  /* Bit 31..16:  Rx Frame Length */
+#define GMR_FS_VLAN                         BIT_13  /* VLAN Packet */
+#define GMR_FS_JABBER                       BIT_12  /* Jabber Packet */
+#define GMR_FS_UN_SIZE                      BIT_11  /* Undersize Packet */
+#define GMR_FS_MC                           BIT_10  /* Multicast Packet */
+#define GMR_FS_BC                           BIT_9  /* Broadcast Packet */
+#define GMR_FS_RX_OK                        BIT_8  /* Receive OK (Good Packet) */
+#define GMR_FS_GOOD_FC                      BIT_7  /* Good Flow-Control Packet */
+#define GMR_FS_BAD_FC                       BIT_6  /* Bad  Flow-Control Packet */
+#define GMR_FS_MII_ERR                      BIT_5  /* MII Error */
+#define GMR_FS_LONG_ERR                     BIT_4  /* Too Long Packet */
+#define GMR_FS_FRAGMENT                     BIT_3  /* Fragment */
+#define GMR_FS_CRC_ERR                      BIT_1  /* CRC Error */
+#define GMR_FS_RX_FF_OV                     BIT_0  /* Rx FIFO Overflow */
+
+#define GMR_FS_LEN_SHIFT                    16
+
+#define GMR_FS_ANY_ERR    ( \
+  GMR_FS_RX_FF_OV | \
+  GMR_FS_CRC_ERR | \
+  GMR_FS_FRAGMENT | \
+  GMR_FS_LONG_ERR | \
+  GMR_FS_MII_ERR | \
+  GMR_FS_BAD_FC | \
+  GMR_FS_GOOD_FC | \
+  GMR_FS_UN_SIZE | \
+  GMR_FS_JABBER)
+
+/* Rx GMAC FIFO Flush Mask (default) */
+#define RX_FF_FL_DEF_MSK                    GMR_FS_ANY_ERR
+
+/*  Receive and Transmit GMAC FIFO Registers (YUKON only) */
+
+/*  RX_GMF_EA      32 bit  Rx GMAC FIFO End Address */
+/*  RX_GMF_AF_THR  32 bit  Rx GMAC FIFO Almost Full Thresh. */
+/*  RX_GMF_WP      32 bit  Rx GMAC FIFO Write Pointer */
+/*  RX_GMF_WLEV    32 bit  Rx GMAC FIFO Write Level */
+/*  RX_GMF_RP      32 bit  Rx GMAC FIFO Read Pointer */
+/*  RX_GMF_RLEV    32 bit  Rx GMAC FIFO Read Level */
+/*  TX_GMF_EA      32 bit  Tx GMAC FIFO End Address */
+/*  TX_GMF_AE_THR  32 bit  Tx GMAC FIFO Almost Empty Thresh.*/
+/*  TX_GMF_WP      32 bit  Tx GMAC FIFO Write Pointer */
+/*  TX_GMF_WSP    32 bit  Tx GMAC FIFO Write Shadow Pointer */
+/*  TX_GMF_WLEV    32 bit  Tx GMAC FIFO Write Level */
+/*  TX_GMF_RP      32 bit  Tx GMAC FIFO Read Pointer */
+/*  TX_GMF_RSTP    32 bit  Tx GMAC FIFO Restart Pointer */
+/*  TX_GMF_RLEV    32 bit  Tx GMAC FIFO Read Level */
+
+/*  RX_GMF_CTRL_T  32 bit  Rx GMAC FIFO Control/Test */
+#define RX_TRUNC_ON                         BIT_27  /* enable  packet truncation */
+#define RX_TRUNC_OFF                        BIT_26  /* disable packet truncation */
+#define RX_VLAN_STRIP_ON                    BIT_25  /* enable  VLAN stripping */
+#define RX_VLAN_STRIP_OFF                   BIT_24  /* disable VLAN stripping */
+#define GMF_RX_MACSEC_FLUSH_ON              BIT_23
+#define GMF_RX_MACSEC_FLUSH_OFF             BIT_22
+#define GMF_RX_OVER_ON                      BIT_19  /* enable flushing on receive overrun */
+#define GMF_RX_OVER_OFF                     BIT_18  /* disable flushing on receive overrun */
+#define GMF_ASF_RX_OVER_ON                  BIT_17  /* enable flushing of ASF when overrun */
+#define GMF_ASF_RX_OVER_OFF                 BIT_16  /* disable flushing of ASF when overrun */
+#define GMF_WP_TST_ON                       BIT_14  /* Write Pointer Test On */
+#define GMF_WP_TST_OFF                      BIT_13  /* Write Pointer Test Off */
+#define GMF_WP_STEP                         BIT_12  /* Write Pointer Step/Increment */
+#define GMF_RP_TST_ON                       BIT_10  /* Read Pointer Test On */
+#define GMF_RP_TST_OFF                      BIT_9  /* Read Pointer Test Off */
+#define GMF_RP_STEP                         BIT_8  /* Read Pointer Step/Increment */
+#define GMF_RX_F_FL_ON                      BIT_7  /* Rx FIFO Flush Mode On */
+#define GMF_RX_F_FL_OFF                     BIT_6  /* Rx FIFO Flush Mode Off */
+#define GMF_CLI_RX_FO                       BIT_5  /* Clear IRQ Rx FIFO Overrun */
+#define GMF_CLI_RX_FC                       BIT_4  /* Clear IRQ Rx Frame Complete */
+#define GMF_OPER_ON                         BIT_3  /* Operational Mode On */
+#define GMF_OPER_OFF                        BIT_2  /* Operational Mode Off */
+#define GMF_RST_CLR                         BIT_1  /* Clear GMAC FIFO Reset */
+#define GMF_RST_SET                         BIT_0  /* Set   GMAC FIFO Reset */
+
+/*  TX_GMF_CTRL_T  32 bit  Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
+#define  TX_STFW_DIS                        BIT_31  /* Disable Store & Forward (Yukon-EC Ultra) */
+#define  TX_STFW_ENA                        BIT_30  /* Enable Store & Forward (Yukon-EC Ultra) */
+#define TX_VLAN_TAG_ON                      BIT_25  /* enable  VLAN tagging */
+#define TX_VLAN_TAG_OFF                     BIT_24  /* disable VLAN tagging */
+#define  TX_JUMBO_ENA                       BIT_23  /* Enable Jumbo Mode (Yukon-EC Ultra) */
+#define  TX_JUMBO_DIS                       BIT_22  /* Disable Jumbo Mode (Yukon-EC Ultra) */
+#define GMF_WSP_TST_ON                      BIT_18  /* Write Shadow Pointer Test On */
+#define GMF_WSP_TST_OFF                     BIT_17  /* Write Shadow Pointer Test Off */
+#define GMF_WSP_STEP                        BIT_16  /* Write Shadow Pointer Step/Increment */
+/* Bits 15..8: same as for RX_GMF_CTRL_T */
+#define GMF_CLI_TX_FU                       BIT_6  /* Clear IRQ Tx FIFO Underrun */
+#define GMF_CLI_TX_FC                       BIT_5  /* Clear IRQ Tx Frame Complete */
+#define GMF_CLI_TX_PE                       BIT_4  /* Clear IRQ Tx Parity Error */
+/* Bits 3..0: same as for RX_GMF_CTRL_T */
+
+#define GMF_RX_CTRL_DEF                     (GMF_OPER_ON | GMF_RX_F_FL_ON)
+#define GMF_TX_CTRL_DEF                     GMF_OPER_ON
+
+#define RX_GMF_AF_THR_MIN                    0x0c  /* Rx GMAC FIFO Almost Full Thresh. min. */
+#define RX_GMF_FL_THR_DEF                    0x0a  /* Rx GMAC FIFO Flush Threshold default */
+
+/*  GMAC_TI_ST_CTRL   8 bit  Time Stamp Timer Ctrl Reg (YUKON only) */
+#define GMT_ST_START                        BIT_2  /* Start Time Stamp Timer */
+#define GMT_ST_STOP                         BIT_1  /* Stop  Time Stamp Timer */
+#define GMT_ST_CLR_IRQ                      BIT_0  /* Clear Time Stamp Timer IRQ */
+
+/*  POLL_CTRL  32 bit  Polling Unit control register (Yukon-2 only) */
+#define PC_CLR_IRQ_CHK                      BIT_5  /* Clear IRQ Check */
+#define PC_POLL_RQ                          BIT_4  /* Poll Request Start */
+#define PC_POLL_OP_ON                       BIT_3  /* Operational Mode On */
+#define PC_POLL_OP_OFF                      BIT_2  /* Operational Mode Off */
+#define PC_POLL_RST_CLR                     BIT_1  /* Clear Polling Unit Reset (Enable) */
+#define PC_POLL_RST_SET                     BIT_0  /* Set   Polling Unit Reset */
+
+/* B28_Y2_ASF_STAT_CMD    32 bit  ASF Status and Command Reg */
+/* This register is used by the host driver software */
+#define Y2_ASF_OS_PRES                      BIT_4  /* ASF operation system present */
+#define Y2_ASF_RESET                        BIT_3  /* ASF system in reset state */
+#define Y2_ASF_RUNNING                      BIT_2  /* ASF system operational */
+#define Y2_ASF_CLR_HSTI                     BIT_1  /* Clear ASF IRQ */
+#define Y2_ASF_IRQ                          BIT_0  /* Issue an IRQ to ASF system */
+
+#define Y2_ASF_UC_STATE                     (3<<2)  /* ASF uC State */
+#define Y2_ASF_CLK_HALT                     0  /* ASF system clock stopped */
+
+/* B28_Y2_ASF_HCU_CCSR  32bit CPU Control and Status Register (Yukon EX) */
+#define  Y2_ASF_HCU_CCSR_SMBALERT_MONITOR    BIT_27  /* SMBALERT pin monitor */
+#define  Y2_ASF_HCU_CCSR_CPU_SLEEP           BIT_26  /* CPU sleep status */
+#define  Y2_ASF_HCU_CCSR_CS_TO               BIT_25  /* Clock Stretching Timeout */
+#define  Y2_ASF_HCU_CCSR_WDOG                BIT_24  /* Watchdog Reset */
+#define  Y2_ASF_HCU_CCSR_CLR_IRQ_HOST        BIT_17  /* Clear IRQ_HOST */
+#define  Y2_ASF_HCU_CCSR_SET_IRQ_HCU         BIT_16  /* Set IRQ_HCU */
+#define  Y2_ASF_HCU_CCSR_AHB_RST             BIT_9  /* Reset AHB bridge */
+#define  Y2_ASF_HCU_CCSR_CPU_RST_MODE        BIT_8  /* CPU Reset Mode */
+#define  Y2_ASF_HCU_CCSR_SET_SYNC_CPU        BIT_5
+#define  Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1     BIT_4
+#define  Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0     BIT_3
+#define  Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK  (BIT_4 | BIT_3)  /* CPU Clock Divide */
+#define  Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3
+#define  Y2_ASF_HCU_CCSR_OS_PRSNT            BIT_2  /* ASF OS Present */
+/* Microcontroller State */
+#define  Y2_ASF_HCU_CCSR_UC_STATE_MSK        3
+#define  Y2_ASF_HCU_CCSR_UC_STATE_BASE       BIT_0
+#define  Y2_ASF_HCU_CCSR_ASF_RESET           0
+#define  Y2_ASF_HCU_CCSR_ASF_HALTED          BIT_1
+#define  Y2_ASF_HCU_CCSR_ASF_RUNNING         BIT_0
+
+/* B28_Y2_ASF_HOST_COM  32 bit  ASF Host Communication Reg */
+/* This register is used by the ASF firmware */
+#define Y2_ASF_CLR_ASFI                      BIT_1  /* Clear host IRQ */
+#define Y2_ASF_HOST_IRQ                      BIT_0  /* Issue an IRQ to HOST system */
+
+/*  STAT_CTRL  32 bit  Status BMU control register (Yukon-2 only) */
+#define SC_STAT_CLR_IRQ                     BIT_4  /* Status Burst IRQ clear */
+#define SC_STAT_OP_ON                       BIT_3  /* Operational Mode On */
+#define SC_STAT_OP_OFF                      BIT_2  /* Operational Mode Off */
+#define SC_STAT_RST_CLR                     BIT_1  /* Clear Status Unit Reset (Enable) */
+#define SC_STAT_RST_SET                     BIT_0  /* Set   Status Unit Reset */
+
+/*  GMAC_CTRL  32 bit  GMAC Control Reg (YUKON only) */
+#define GMC_SEC_RST                         BIT_15  /* MAC SEC RST */
+#define GMC_SEC_RST_OFF                     BIT_14  /* MAC SEC RST Off */
+#define GMC_BYP_MACSECRX_ON                 BIT_13  /* Bypass MAC SEC RX */
+#define GMC_BYP_MACSECRX_OFF                BIT_12  /* Bypass MAC SEC RX Off */
+#define GMC_BYP_MACSECTX_ON                 BIT_11  /* Bypass MAC SEC TX */
+#define GMC_BYP_MACSECTX_OFF                BIT_10  /* Bypass MAC SEC TX Off */
+#define GMC_BYP_RETR_ON                     BIT_9  /* Bypass MAC retransmit FIFO On */
+#define GMC_BYP_RETR_OFF                    BIT_8  /* Bypass MAC retransmit FIFO Off */
+#define GMC_H_BURST_ON                      BIT_7  /* Half Duplex Burst Mode On */
+#define GMC_H_BURST_OFF                     BIT_6  /* Half Duplex Burst Mode Off */
+#define GMC_F_LOOPB_ON                      BIT_5  /* FIFO Loopback On */
+#define GMC_F_LOOPB_OFF                     BIT_4  /* FIFO Loopback Off */
+#define GMC_PAUSE_ON                        BIT_3  /* Pause On */
+#define GMC_PAUSE_OFF                       BIT_2  /* Pause Off */
+#define GMC_RST_CLR                         BIT_1  /* Clear GMAC Reset */
+#define GMC_RST_SET                         BIT_0  /* Set   GMAC Reset */
+
+/*  GPHY_CTRL  32 bit  GPHY Control Reg (YUKON only) */
+#define GPC_SEL_BDT                         BIT_28  /* Select Bi-Dir. Transfer for MDC/MDIO */
+#define GPC_INT_POL                         BIT_27  /* IRQ Polarity is Active Low */
+#define GPC_75_OHM                          BIT_26  /* Use 75 Ohm Termination instead of 50 */
+#define GPC_DIS_FC                          BIT_25  /* Disable Automatic Fiber/Copper Detection */
+#define GPC_DIS_SLEEP                       BIT_24  /* Disable Energy Detect */
+#define GPC_HWCFG_M_3                       BIT_23  /* HWCFG_MODE[3] */
+#define GPC_HWCFG_M_2                       BIT_22  /* HWCFG_MODE[2] */
+#define GPC_HWCFG_M_1                       BIT_21  /* HWCFG_MODE[1] */
+#define GPC_HWCFG_M_0                       BIT_20  /* HWCFG_MODE[0] */
+#define GPC_ANEG_0                          BIT_19  /* ANEG[0] */
+#define GPC_ENA_XC                          BIT_18  /* Enable MDI crossover */
+#define GPC_DIS_125                         BIT_17  /* Disable 125 MHz clock */
+#define GPC_ANEG_3                          BIT_16  /* ANEG[3] */
+#define GPC_ANEG_2                          BIT_15  /* ANEG[2] */
+#define GPC_ANEG_1                          BIT_14  /* ANEG[1] */
+#define GPC_ENA_PAUSE                       BIT_13  /* Enable Pause (SYM_OR_REM) */
+#define GPC_PHYADDR_4                       BIT_12  /* Bit 4 of Phy Addr */
+#define GPC_PHYADDR_3                       BIT_11  /* Bit 3 of Phy Addr */
+#define GPC_PHYADDR_2                       BIT_10  /* Bit 2 of Phy Addr */
+#define GPC_PHYADDR_1                       BIT_9  /* Bit 1 of Phy Addr */
+#define GPC_PHYADDR_0                       BIT_8  /* Bit 0 of Phy Addr */
+#define GPC_RST_CLR                         BIT_1  /* Clear GPHY Reset */
+#define GPC_RST_SET                         BIT_0  /* Set   GPHY Reset */
+
+/*  GMAC_IRQ_SRC   8 bit  GMAC Interrupt Source Reg (YUKON only) */
+/*  GMAC_IRQ_MSK   8 bit  GMAC Interrupt Mask   Reg (YUKON only) */
+#define GM_IS_RX_CO_OV                      BIT_5  /* Receive Counter Overflow IRQ */
+#define GM_IS_TX_CO_OV                      BIT_4  /* Transmit Counter Overflow IRQ */
+#define GM_IS_TX_FF_UR                      BIT_3  /* Transmit FIFO Underrun */
+#define GM_IS_TX_COMPL                      BIT_2  /* Frame Transmission Complete */
+#define GM_IS_RX_FF_OR                      BIT_1  /* Receive FIFO Overrun */
+#define GM_IS_RX_COMPL                      BIT_0  /* Frame Reception Complete */
+
+#define GMAC_DEF_MSK                        (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR)
+
+//  GMAC_LINK_CTRL  16 bit  GMAC Link Control Reg (YUKON only)
+#define GMLC_RST_CLR                        BIT_1  // Clear GMAC Link Reset
+#define GMLC_RST_SET                        BIT_0  // Set   GMAC Link Reset
+
+#define MSK_PORT_A                          0
+#define MSK_PORT_B                          1
+
+// Register access macros
+#define CSR_WRITE_4(sc, reg, val)            MmioWrite32 ((sc)->RegBase + (reg), (val))
+#define CSR_WRITE_2(sc, reg, val)            MmioWrite16 ((sc)->RegBase + (reg), (val))
+#define CSR_WRITE_1(sc, reg, val)            MmioWrite8 ((sc)->RegBase + (reg), (val))
+
+#define CSR_READ_4(sc, reg)                  MmioRead32 ((sc)->RegBase + (reg))
+#define CSR_READ_2(sc, reg)                  MmioRead16 ((sc)->RegBase + (reg))
+#define CSR_READ_1(sc, reg)                  MmioRead8 ((sc)->RegBase + (reg))
+
+#define CSR_PCI_WRITE_4(sc, reg, val)        MmioWrite32 ((sc)->RegBase + Y2_CFG_SPC + (reg), (val))
+#define CSR_PCI_WRITE_2(sc, reg, val)        MmioWrite16 ((sc)->RegBase + Y2_CFG_SPC + (reg), (val))
+#define CSR_PCI_WRITE_1(sc, reg, val)        MmioWrite8 ((sc)->RegBase + Y2_CFG_SPC + (reg), (val))
+
+#define CSR_PCI_READ_4(sc, reg)              MmioRead32 ((sc)->RegBase + Y2_CFG_SPC + (reg))
+#define CSR_PCI_READ_2(sc, reg)              MmioRead16 ((sc)->RegBase + Y2_CFG_SPC + (reg))
+#define CSR_PCI_READ_1(sc, reg)              MmioRead8 ((sc)->RegBase + Y2_CFG_SPC + (reg))
+
+#define GMAC_REG(port, reg)                  ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
+#define  GMAC_WRITE_2(sc, port, reg, val)    CSR_WRITE_2 ((sc), GMAC_REG((port), (reg)), (val))
+#define  GMAC_READ_2(sc, port, reg)          CSR_READ_2 ((sc), GMAC_REG((port), (reg)))
+
+// GPHY address (bits 15..11 of SMI control reg)
+#define PHY_ADDR_MARV                        0
+
+#define MSK_ADDR_LO(x)                      ((UINT64) (x) & 0xffffffffUL)
+#define MSK_ADDR_HI(x)                      ((UINT64) (x) >> 32)
+
+// PCI Status error definitions (not all of these are defined in MdePkg/Include/IndustryStandard/Pci22.h
+#define PCIM_STATUS_CAPPRESENT              0x0010
+#define PCIM_STATUS_66CAPABLE               0x0020
+#define PCIM_STATUS_BACKTOBACK              0x0080
+#define PCIM_STATUS_PERRREPORT              0x0100
+#define PCIM_STATUS_SEL_FAST                0x0000
+#define PCIM_STATUS_SEL_MEDIMUM             0x0200
+#define PCIM_STATUS_SEL_SLOW                0x0400
+#define PCIM_STATUS_SEL_MASK                0x0600
+#define PCIM_STATUS_STABORT                 0x0800
+#define PCIM_STATUS_RTABORT                 0x1000
+#define PCIM_STATUS_RMABORT                 0x2000
+#define PCIM_STATUS_SERR                    0x4000
+#define PCIM_STATUS_PERR                    0x8000
+
+//
+// At first I guessed 8 bytes, the size of a single descriptor, would be
+// required alignment constraints. But, it seems that Yukon II have 4096
+// bytes boundary alignment constraints.
+//
+#define MSK_RING_ALIGN                      4096
+#define MSK_STAT_ALIGN                      4096
+
+// Rx descriptor data structure
+struct msk_rx_desc {
+  UINT32  msk_addr;
+  UINT32  msk_control;
+};
+
+// Tx descriptor data structure
+struct msk_tx_desc {
+  UINT32  msk_addr;
+  UINT32  msk_control;
+};
+
+// Status descriptor data structure
+struct msk_stat_desc {
+  UINT32  msk_status;
+  UINT32  msk_control;
+};
+
+// Mask and shift value to get Tx async queue status for port 1
+#define STLE_TXA1_MSKL                      0x00000fff
+#define STLE_TXA1_SHIFTL                    0
+
+// Mask and shift value to get Tx sync queue status for port 1
+#define STLE_TXS1_MSKL                      0x00fff000
+#define STLE_TXS1_SHIFTL                    12
+
+// Mask and shift value to get Tx async queue status for port 2
+#define STLE_TXA2_MSKL                      0xff000000
+#define STLE_TXA2_SHIFTL                    24
+#define STLE_TXA2_MSKH                      0x000f
+// This one shifts up
+#define STLE_TXA2_SHIFTH                    8
+
+// Mask and shift value to get Tx sync queue status for port 2
+#define STLE_TXS2_MSKL                      0x00000000
+#define STLE_TXS2_SHIFTL                    0
+#define STLE_TXS2_MSKH                      0xfff0
+#define STLE_TXS2_SHIFTH                    4
+
+// YUKON-2 bit values
+#define HW_OWNER                            0x80000000
+#define SW_OWNER                            0x00000000
+
+#define PU_PUTIDX_VALID                     0x10000000
+
+// YUKON-2 Control flags
+#define UDPTCP                              0x00010000
+#define CALSUM                              0x00020000
+#define WR_SUM                              0x00040000
+#define INIT_SUM                            0x00080000
+#define LOCK_SUM                            0x00100000
+#define INS_VLAN                            0x00200000
+#define FRC_STAT                            0x00400000
+#define EOP                                 0x00800000
+
+#define TX_LOCK                             0x01000000
+#define BUF_SEND                            0x02000000
+#define PACKET_SEND                         0x04000000
+
+#define NO_WARNING                          0x40000000
+#define NO_UPDATE                           0x80000000
+
+// YUKON-2 Rx/Tx opcodes defines
+#define OP_TCPWRITE                         0x11000000
+#define OP_TCPSTART                         0x12000000
+#define OP_TCPINIT                          0x14000000
+#define OP_TCPLCK                           0x18000000
+#define OP_TCPCHKSUM                        OP_TCPSTART
+#define OP_TCPIS                            (OP_TCPINIT | OP_TCPSTART)
+#define OP_TCPLW                            (OP_TCPLCK | OP_TCPWRITE)
+#define OP_TCPLSW                           (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
+#define OP_TCPLISW                          (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
+#define OP_ADDR64                           0x21000000
+#define OP_VLAN                             0x22000000
+#define OP_ADDR64VLAN                       (OP_ADDR64 | OP_VLAN)
+#define OP_LRGLEN                           0x24000000
+#define OP_LRGLENVLAN                       (OP_LRGLEN | OP_VLAN)
+#define OP_MSS                              0x28000000
+#define OP_MSSVLAN                          (OP_MSS | OP_VLAN)
+#define OP_BUFFER                           0x40000000
+#define OP_PACKET                           0x41000000
+#define OP_LARGESEND                        0x43000000
+
+// YUKON-2 STATUS opcodes defines
+#define OP_RXSTAT                           0x60000000
+#define OP_RXTIMESTAMP                      0x61000000
+#define OP_RXVLAN                           0x62000000
+#define OP_RXCHKS                           0x64000000
+#define OP_RXCHKSVLAN                       (OP_RXCHKS | OP_RXVLAN)
+#define OP_RXTIMEVLAN                       (OP_RXTIMESTAMP | OP_RXVLAN)
+#define OP_RSS_HASH                         0x65000000
+#define OP_TXINDEXLE                        0x68000000
+
+// YUKON-2 SPECIAL opcodes defines
+#define OP_PUTIDX                           0x70000000
+
+#define  STLE_OP_MASK                       0xff000000
+#define  STLE_CSS_MASK                      0x00ff0000
+#define  STLE_LEN_MASK                      0x0000ffff
+
+// CSS defined in status LE(valid for       descriptor V2 format)
+#define  CSS_TCPUDP_CSUM_OK                  0x00800000
+#define  CSS_UDP                             0x00400000
+#define  CSS_TCP                             0x00200000
+#define  CSS_IPFRAG                          0x00100000
+#define  CSS_IPV6                            0x00080000
+#define  CSS_IPV4_CSUM_OK                    0x00040000
+#define  CSS_IPV4                            0x00020000
+#define  CSS_PORT                            0x00010000
+
+// Descriptor Bit Definition
+//  TxCtrl    Transmit Buffer Control Field
+//  RxCtrl    Receive  Buffer Control Field
+#define BMU_OWN                             BIT_31  // OWN bit: 0=host/1=BMU
+#define BMU_STF                             BIT_30  // Start of Frame
+#define BMU_EOF                             BIT_29  // End of Frame
+#define BMU_IRQ_EOB                         BIT_28  // Req "End of Buffer" IRQ
+#define BMU_IRQ_EOF                         BIT_27  // Req "End of Frame" IRQ
+// TxCtrl specific bits
+#define BMU_STFWD                           BIT_26  // (Tx)  Store & Forward Frame
+#define BMU_NO_FCS                          BIT_25  // (Tx) Disable MAC FCS (CRC) generation
+#define BMU_SW                              BIT_24  // (Tx)  1 bit res. for SW use
+// RxCtrl specific bits
+#define BMU_DEV_0                           BIT_26  // (Rx)  Transfer data to Dev0
+#define BMU_STAT_VAL                        BIT_25  // (Rx)  Rx Status Valid
+#define BMU_TIST_VAL                        BIT_24  // (Rx)  Rx TimeStamp Valid
+// Bit 23..16:  BMU Check Opcodes
+#define BMU_CHECK                           (0x55<<16)  // Default BMU check
+#define BMU_TCP_CHECK                       (0x56<<16)  // Descr with TCP ext
+#define BMU_UDP_CHECK                       (0x57<<16)  // Descr with UDP ext (YUKON only)
+#define BMU_BBC                             0xffff  // Bit 15.. 0:  Buffer Byte Counter
+
+/* Use 64-bit DMA in all cases in UEFI. After much discussion on the mailing
+ * list, it was determined that there is not currently a good way to detect
+ * whether 32-bit DMA should be used (if ever) or whether there are any
+ * supported platforms on which 64-bit DMA would not work */
+#define MSK_64BIT_DMA
+
+#define MSK_TX_RING_CNT                     512
+#define MSK_RX_RING_CNT                     512
+#define MSK_RX_BUF_ALIGN                    8
+#define MSK_JUMBO_RX_RING_CNT               MSK_RX_RING_CNT
+#define MSK_STAT_RING_CNT                   512
+#define MSK_MAXTXSEGS                       32
+#define MSK_TSO_MAXSGSIZE                   4096
+#define MSK_TSO_MAXSIZE                     (65535 + sizeof (struct ether_vlan_header))
+
+/*
+ * It seems that the hardware requires extra decriptors(LEs) to offload
+ * TCP/UDP checksum, VLAN hardware tag inserstion and TSO.
+ *
+ * 1 descriptor for TCP/UDP checksum offload.
+ * 1 descriptor VLAN hardware tag insertion.
+ * 1 descriptor for TSO(TCP Segmentation Offload)
+ * 1 descriptor for 64bits DMA : Not applicatable due to the use of
+ *  BUS_SPACE_MAXADDR_32BIT in parent DMA tag creation.
+ */
+#define  MSK_RESERVED_TX_DESC_CNT            3
+
+/*
+ * Jumbo buffer stuff. Note that we must allocate more jumbo
+ * buffers than there are descriptors in the receive ring. This
+ * is because we don't know how long it will take for a packet
+ * to be released after we hand it off to the upper protocol
+ * layers. To be safe, we allocate 1.5 times the number of
+ * receive descriptors.
+ */
+/*#define MSK_JUMBO_FRAMELEN  9022
+#define MSK_JUMBO_MTU    (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
+#define MSK_MAX_FRAMELEN    \
+  (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
+#define MSK_MIN_FRAMELEN  (ETHER_MIN_LEN - ETHER_CRC_LEN)
+*/
+
+#define htole32(x)                          (x) // All UEFI platforms are little endian
+#define le32toh(x)                          (x)
+#define ACPI_SPECFLAG_PREFETCHABLE          0x06
+#define TX_MBUF_SIGNATURE                   SIGNATURE_32 ('t','x','m','b')
+#define RX_MBUF_SIGNATURE                   SIGNATURE_32 ('r','x','m','b')
+#define ETHER_CRC_POLY_LE                   0xedb88320
+#define ETHER_CRC_POLY_BE                   0x04c11db6
+//#define JUMBO_RX_MBUF_SIGNATURE   SIGNATURE_32('j','r','x','m')
+
+typedef struct {
+  VOID            *Buf;
+  UINTN           Length;
+} MSK_SYSTEM_BUF;
+
+typedef struct {
+  UINTN           Signature;
+  LIST_ENTRY      Link;
+  MSK_SYSTEM_BUF  SystemBuf;
+} MSK_LINKED_SYSTEM_BUF;
+
+typedef struct {
+  VOID            *Buf;
+  UINTN           Length;
+  VOID            *DmaMapping;
+} MSK_DMA_BUF;
+
+typedef struct {
+  UINTN           Signature;
+  LIST_ENTRY      Link;
+  MSK_DMA_BUF     DmaBuf;
+} MSK_LINKED_DMA_BUF;
+
+struct msk_txdesc {
+  MSK_DMA_BUF          tx_m;
+  struct msk_tx_desc  *tx_le;
+};
+
+struct msk_rxdesc {
+  MSK_DMA_BUF         rx_m;
+  struct msk_rx_desc  *rx_le;
+};
+
+struct msk_chain_data {
+  struct msk_txdesc  msk_txdesc[MSK_TX_RING_CNT];
+  struct msk_rxdesc  msk_rxdesc[MSK_RX_RING_CNT];
+  void              *msk_tx_ring_map;
+  void              *msk_rx_ring_map;
+  //  struct msk_rxdesc  msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT];
+  INTN     msk_tx_high_addr;
+  INTN     msk_tx_prod;
+  INTN     msk_tx_cons;
+  INTN     msk_tx_cnt;
+  INTN     msk_tx_put;
+  INTN     msk_rx_cons;
+  INTN     msk_rx_prod;
+  INTN     msk_rx_putwm;
+};
+
+struct msk_ring_data {
+  struct msk_tx_desc      *msk_tx_ring;
+  EFI_PHYSICAL_ADDRESS    msk_tx_ring_paddr;
+  struct msk_rx_desc      *msk_rx_ring;
+  EFI_PHYSICAL_ADDRESS    msk_rx_ring_paddr;
+  //  struct msk_rx_desc      *msk_jumbo_rx_ring;
+  //  EFI_PHYSICAL_ADDRESS    msk_jumbo_rx_ring_paddr;
+};
+
+#define MSK_TX_RING_ADDR(sc, i)  \
+  ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof (struct msk_tx_desc) * (i))
+#define MSK_RX_RING_ADDR(sc, i) \
+  ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof (struct msk_rx_desc) * (i))
+
+#define MSK_TX_RING_SZ                      (sizeof (struct msk_tx_desc) * MSK_TX_RING_CNT)
+#define MSK_RX_RING_SZ                      (sizeof (struct msk_rx_desc) * MSK_RX_RING_CNT)
+#define MSK_JUMBO_RX_RING_SZ                (sizeof (struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT)
+#define MSK_STAT_RING_SZ                    (sizeof (struct msk_stat_desc) * MSK_STAT_RING_CNT)
+
+#define MSK_INC(x, y)                       ((x) = (x + 1) % y)
+#ifdef MSK_64BIT_DMA
+#define MSK_RX_INC(x, y)        (x) = (x + 2) % y
+#define MSK_RX_BUF_CNT          (MSK_RX_RING_CNT / 2)
+#define MSK_JUMBO_RX_BUF_CNT    (MSK_JUMBO_RX_RING_CNT / 2)
+#else
+#define MSK_RX_INC(x, y)        (x) = (x + 1) % y
+#define MSK_RX_BUF_CNT          MSK_RX_RING_CNT
+#define MSK_JUMBO_RX_BUF_CNT    MSK_JUMBO_RX_RING_CNT
+#endif
+
+#define  MSK_PCI_BUS                         0
+#define  MSK_PCIX_BUS                        1
+#define  MSK_PEX_BUS                         2
+
+#define  MSK_PROC_DEFAULT                    (MSK_RX_RING_CNT / 2)
+#define  MSK_PROC_MIN                        30
+#define  MSK_PROC_MAX                        (MSK_RX_RING_CNT - 1)
+
+#define  MSK_INT_HOLDOFF_DEFAULT             100
+
+#define  MSK_TX_TIMEOUT                      5
+#define  MSK_PUT_WM                          10
+
+/* Forward decl. */
+struct msk_if_softc;
+
+struct msk_hw_stats {
+  /* Rx stats. */
+  UINT32 rx_ucast_frames;
+  UINT32 rx_bcast_frames;
+  UINT32 rx_pause_frames;
+  UINT32 rx_mcast_frames;
+  UINT32 rx_crc_errs;
+  UINT32 rx_spare1;
+  UINT64 rx_good_octets;
+  UINT64 rx_bad_octets;
+  UINT32 rx_runts;
+  UINT32 rx_runt_errs;
+  UINT32 rx_pkts_64;
+  UINT32 rx_pkts_65_127;
+  UINT32 rx_pkts_128_255;
+  UINT32 rx_pkts_256_511;
+  UINT32 rx_pkts_512_1023;
+  UINT32 rx_pkts_1024_1518;
+  UINT32 rx_pkts_1519_max;
+  UINT32 rx_pkts_too_long;
+  UINT32 rx_pkts_jabbers;
+  UINT32 rx_spare2;
+  UINT32 rx_fifo_oflows;
+  UINT32 rx_spare3;
+  /* Tx stats. */
+  UINT32 tx_ucast_frames;
+  UINT32 tx_bcast_frames;
+  UINT32 tx_pause_frames;
+  UINT32 tx_mcast_frames;
+  UINT64 tx_octets;
+  UINT32 tx_pkts_64;
+  UINT32 tx_pkts_65_127;
+  UINT32 tx_pkts_128_255;
+  UINT32 tx_pkts_256_511;
+  UINT32 tx_pkts_512_1023;
+  UINT32 tx_pkts_1024_1518;
+  UINT32 tx_pkts_1519_max;
+  UINT32 tx_spare1;
+  UINT32 tx_colls;
+  UINT32 tx_late_colls;
+  UINT32 tx_excess_colls;
+  UINT32 tx_multi_colls;
+  UINT32 tx_single_colls;
+  UINT32 tx_underflows;
+};
+
+/* Softc for the Marvell Yukon II controller. */
+struct msk_softc {
+  UINT32    RegBase;
+  UINT64    OriginalPciAttributes;
+  UINT8      msk_hw_id;
+  UINT8      msk_hw_rev;
+  UINT8      msk_bustype;
+  UINT8      msk_num_port;
+  INTN      msk_expcap;
+  //  INTN      msk_pcixcap;
+  INTN      msk_ramsize;  /* amount of SRAM on NIC */
+  UINT32    msk_pmd;  /* physical media type */
+  UINT32    msk_intrmask;
+  UINT32    msk_intrhwemask;
+  UINT32    msk_pflags;
+  INTN      msk_clock;
+  struct msk_if_softc  *msk_if[2];
+  INTN      msk_txqsize;
+  INTN      msk_rxqsize;
+  INTN      msk_txqstart[2];
+  INTN      msk_txqend[2];
+  INTN      msk_rxqstart[2];
+  INTN      msk_rxqend[2];
+  void                  *msk_stat_map;
+  struct msk_stat_desc  *msk_stat_ring;
+  EFI_PHYSICAL_ADDRESS  msk_stat_ring_paddr;
+  INTN      msk_int_holdoff;
+  INTN      msk_process_limit;
+  INTN      msk_stat_cons;
+  EFI_EVENT Timer;
+  EFI_PCI_IO_PROTOCOL *PciIo;
+};
+
+#define  MSK_USECS(sc, us)                   ((sc)->msk_clock * (us))
+
+/* Softc for each logical interface. */
+struct msk_if_softc {
+  //  INT32      msk_port;  /* port # on controller */
+  struct msk_mii_data msk_md;
+  struct mii_data mii_d;
+  INTN      msk_framesize;
+  INTN      msk_phytype;
+  INTN      msk_phyaddr;
+  UINT32    msk_flags;
+#define  MSK_FLAG_MSI                        0x0001
+#define  MSK_FLAG_FASTETHER                  0x0004
+#define  MSK_FLAG_JUMBO                      0x0008
+#define  MSK_FLAG_JUMBO_NOCSUM               0x0010
+#define  MSK_FLAG_RAMBUF                     0x0020
+#define  MSK_FLAG_DESCV2                     0x0040
+#define  MSK_FLAG_AUTOTX_CSUM                0x0080
+#define  MSK_FLAG_NOHWVLAN                   0x0100
+#define  MSK_FLAG_NORXCHK                    0x0200
+#define  MSK_FLAG_NORX_CSUM                  0x0400
+#define  MSK_FLAG_SUSPEND                    0x2000
+#define  MSK_FLAG_DETACH                     0x4000
+#define  MSK_FLAG_LINK                       0x8000
+  //  INTN      msk_watchdog_timer;
+  UINT32    msk_txq;  /* Tx. Async Queue offset */
+  UINT32    msk_txsq;  /* Tx. Syn Queue offset */
+  UINT32    msk_rxq;  /* Rx. Qeueue offset */
+  struct msk_chain_data  msk_cdata;
+  struct msk_ring_data  msk_rdata;
+  struct msk_hw_stats  msk_stats;
+  struct msk_softc *msk_softc; /* parent controller */
+  VOID        *phy_softc; /* interface phy */
+  BOOLEAN     active;
+  LIST_ENTRY  TransmitQueueHead;
+  LIST_ENTRY  TransmitFreeQueueHead;
+  LIST_ENTRY  ReceiveQueueHead;
+  EFI_MAC_ADDRESS MacAddress;
+};
+
+#define MSK_TIMEOUT                          1000
+#define  MSK_PHY_POWERUP                     1
+#define  MSK_PHY_POWERDOWN                   0
+
+#endif /* _IF_MSKREG_H_ */
diff --git a/Drivers/Net/MarvellYukonDxe/miivar.h b/Drivers/Net/MarvellYukonDxe/miivar.h
new file mode 100644
index 0000000..ff28017
--- /dev/null
+++ b/Drivers/Net/MarvellYukonDxe/miivar.h
@@ -0,0 +1,187 @@
+/**  <at> file
+*  Media Independent Interface configuration definitions. Ported from FreeBSD.
+*
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/*-
+ * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *  This product includes software developed by the NetBSD
+ *  Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/mii/miivar.h,v 1.21.10.1.4.1 2010/06/14 02:09:06 kensmith Exp $
+ */
+
+#ifndef _DEV_MII_MIIVAR_H_
+#define  _DEV_MII_MIIVAR_H_
+
+/*
+ * A network interface driver has one of these structures in its softc.
+ * It is the interface from the network interface driver to the MII
+ * layer.
+ */
+struct mii_data {
+  /*
+   * PHY driver fills this in with active media status.
+   */
+  INTN mii_media_status;
+  INTN mii_media_active;
+};
+
+/*
+ * Requests that can be made to the downcall.
+ */
+#define  MII_TICK                    1  /* once-per-second tick */
+#define  MII_MEDIACHG                2  /* user changed media; perform the switch */
+#define  MII_POLLSTAT                3  /* user requested media status; fill it in */
+
+/*
+ * Each PHY driver's softc has one of these as the first member.
+ * XXX This would be better named "phy_softc", but this is the name
+ * XXX BSDI used, and we would like to have the same interface.
+ */
+struct mii_softc {
+  struct mii_data *mii_pdata;  /* pointer to parent's mii_data */
+
+  INTN mii_flags;           /* misc. flags; see below */
+  INTN mii_capabilities;    /* capabilities from BMSR */
+  INTN mii_extcapabilities; /* extended capabilities */
+  INTN mii_ticks;           /* MII_TICK counter */
+  INTN mii_anegticks;       /* ticks before retrying aneg */
+  INTN mii_media_active;    /* last active media */
+  INTN mii_media_status;    /* last active status */
+};
+
+/* mii_flags */
+#define  MIIF_INITDONE              0x0001    /* has been initialized (mii_data) */
+#define  MIIF_NOISOLATE             0x0002    /* do not isolate the PHY */
+#define  MIIF_NOLOOP                0x0004    /* no loopback capability */
+#define MIIF_AUTOTSLEEP             0x0010    /* use tsleep(), not callout() */
+#define MIIF_HAVEFIBER              0x0020    /* from parent: has fiber interface */
+#define  MIIF_HAVE_GTCR             0x0040    /* has 100base-T2/1000base-T CR */
+#define  MIIF_IS_1000X              0x0080    /* is a 1000BASE-X device */
+#define  MIIF_DOPAUSE               0x0100    /* advertise PAUSE capability */
+#define  MIIF_IS_HPNA               0x0200    /* is a HomePNA device */
+#define  MIIF_FORCEANEG             0x0400    /* force auto-negotiation */
+
+/* Default mii_anegticks values */
+#define  MII_ANEGTICKS              5
+#define  MII_ANEGTICKS_GIGE         17
+
+#define  MIIF_INHERIT_MASK          (MIIF_NOISOLATE|MIIF_NOLOOP|MIIF_AUTOTSLEEP)
+
+#define MII_OUI_MARVELL             0x005043
+#define MII_OUI_xxMARVELL           0x000ac2
+
+#define MII_MODEL_MARVELL_E1000     0x0000
+#define MII_MODEL_MARVELL_E1011     0x0002
+#define MII_MODEL_MARVELL_E1000_3   0x0003
+#define MII_MODEL_MARVELL_E1000S    0x0004
+#define MII_MODEL_MARVELL_E1000_5   0x0005
+#define MII_MODEL_MARVELL_E1000_6   0x0006
+#define MII_MODEL_MARVELL_E3082     0x0008
+#define MII_MODEL_MARVELL_E1112     0x0009
+#define MII_MODEL_MARVELL_E1149     0x000b
+#define MII_MODEL_MARVELL_E1111     0x000c
+#define MII_MODEL_MARVELL_E1116     0x0021
+#define MII_MODEL_MARVELL_E1116R    0x0024
+#define MII_MODEL_MARVELL_E1118     0x0022
+#define MII_MODEL_MARVELL_E3016     0x0026
+#define MII_MODEL_MARVELL_PHYG65G   0x0027
+#define MII_MODEL_xxMARVELL_E1000   0x0000
+#define MII_MODEL_xxMARVELL_E1011   0x0002
+#define MII_MODEL_xxMARVELL_E1000_3 0x0003
+#define MII_MODEL_xxMARVELL_E1000_5 0x0005
+#define MII_MODEL_xxMARVELL_E1111   0x000c
+
+#define MII_STR_MARVELL_E1000       "Marvell 88E1000 Gigabit PHY"
+#define MII_STR_MARVELL_E1011       "Marvell 88E1011 Gigabit PHY"
+#define MII_STR_MARVELL_E1000_3     "Marvell 88E1000_3 Gigabit PHY"
+#define MII_STR_MARVELL_E1000S      "Marvell 88E1000S Gigabit PHY"
+#define MII_STR_MARVELL_E1000_5     "Marvell 88E1000_5 Gigabit PHY"
+#define MII_STR_MARVELL_E1000_6     "Marvell 88E1000_6 Gigabit PHY"
+#define MII_STR_MARVELL_E3082       "Marvell 88E3082 10/100 Fast Ethernet PHY"
+#define MII_STR_MARVELL_E1112       "Marvell 88E1112 Gigabit PHY"
+#define MII_STR_MARVELL_E1149       "Marvell 88E1149 Gigabit PHY"
+#define MII_STR_MARVELL_E1111       "Marvell 88E1111 Gigabit PHY"
+#define MII_STR_MARVELL_E1116       "Marvell 88E1116 Gigabit PHY"
+#define MII_STR_MARVELL_E1116R      "Marvell 88E1116R Gigabit PHY"
+#define MII_STR_MARVELL_E1118       "Marvell 88E1118 Gigabit PHY"
+#define MII_STR_MARVELL_E3016       "Marvell 88E3016 10/100 Fast Ethernet PHY"
+#define MII_STR_MARVELL_PHYG65G     "Marvell PHYG65G Gigabit PHY"
+#define MII_STR_xxMARVELL_E1000     "Marvell 88E1000 Gigabit PHY"
+#define MII_STR_xxMARVELL_E1011     "Marvell 88E1011 Gigabit PHY"
+#define MII_STR_xxMARVELL_E1000_3   "Marvell 88E1000_3 Gigabit PHY"
+#define MII_STR_xxMARVELL_E1000_5   "Marvell 88E1000_5 Gigabit PHY"
+#define MII_STR_xxMARVELL_E1111     "Marvell 88E1111 Gigabit PHY"
+
+/*
+ * Used to attach a PHY to a parent.
+ */
+struct mii_attach_args {
+  struct mii_data *mii_data;  /* pointer to parent data */
+  INTN mii_id1;      /* PHY ID register 1 */
+  INTN mii_id2;      /* PHY ID register 2 */
+};
+
+/*
+ * Used to match a PHY.
+ */
+struct mii_phydesc {
+  UINT32      mpd_oui;    /* the PHY's OUI */
+  UINT32      mpd_model;  /* the PHY's model */
+  const CHAR8 *mpd_name;  /* the PHY's name */
+};
+#define MII_PHY_DESC(a, b)          { MII_OUI_ ## a, MII_MODEL_ ## a ## _ ## b, MII_STR_ ## a ## _ ## b }
+#define MII_PHY_END                 { 0, 0, NULL }
+
+#define PHY_READ(p, r)           msk_phy_readreg ((p)->sc_if, (r))
+
+#define PHY_WRITE(p, r, v)       msk_phy_writereg ((p)->sc_if, (r), (v))
+
+struct msk_mii_data {
+  INTN    port;
+  UINT32  pmd;
+  INTN    mii_flags;
+};
+
+#endif /* _DEV_MII_MIIVAR_H_ */
diff --git a/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Drivers/Net/MvMdioDxe/MvMdioDxe.c
new file mode 100644
index 0000000..ae466d7
--- /dev/null
+++ b/Drivers/Net/MvMdioDxe/MvMdioDxe.c
@@ -0,0 +1,237 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <Protocol/DriverBinding.h>
+#include <Protocol/Mdio.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include "MvMdioDxe.h"
+
+UINT64 MdioBase = 0;
+
+STATIC
+EFI_STATUS
+MdioCheckParam (
+ INTN PhyAddr,
+ INTN RegOff
+ )
+{
+  if (PhyAddr > MVEBU_PHY_ADDR_MASK) {
+    DEBUG((DEBUG_ERROR, "Invalid PHY address %d\n", PhyAddr));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (RegOff > MVEBU_PHY_REG_MASK) {
+    DEBUG((DEBUG_ERROR, "Invalid register offset %d\n", RegOff));
+    return EFI_INVALID_PARAMETER;
+  }
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+MdioWaitReady (
+  VOID
+  )
+{
+  UINT32 Timeout = MVEBU_SMI_TIMEOUT;
+  UINT32 MdioReg;
+
+  /* wait till the SMI is not busy */
+  do {
+    /* read smi register */
+    MdioReg = MmioRead32(MdioBase);
+    if (Timeout-- == 0) {
+      DEBUG((DEBUG_ERROR, "SMI busy Timeout\n"));
+      return EFI_TIMEOUT;
+    }
+  } while (MdioReg & MVEBU_SMI_BUSY);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+MdioWaitValid (
+  VOID
+  )
+{
+  UINT32 Timeout = MVEBU_SMI_TIMEOUT;
+  UINT32 MdioReg;
+
+  /* wait till read value is ready */
+  do {
+    /* read smi register */
+    MdioReg = MmioRead32 (MdioBase);
+    if (Timeout-- == 0) {
+      DEBUG((DEBUG_ERROR, "SMI read ready time-out\n"));
+      return EFI_TIMEOUT;
+    }
+  } while (!(MdioReg & MVEBU_SMI_READ_VALID));
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+MdioOperation (
+  IN CONST MARVELL_MDIO_PROTOCOL *This,
+  IN UINT32 PhyAddr,
+  IN UINT32 RegOff,
+  IN BOOLEAN Write,
+  IN OUT UINT32 *Data
+  )
+{
+  UINT32 MdioReg;
+  EFI_STATUS Status;
+
+  Status = MdioCheckParam (PhyAddr, RegOff);
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "MdioDxe: wrong parameters\n"));
+    return Status;
+  }
+
+  /* wait till the SMI is not busy */
+  Status = MdioWaitReady ();
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "MdioDxe: MdioWaitReady error\n"));
+    return Status;
+  }
+
+  /* fill the phy addr and reg offset and write opcode and data */
+  MdioReg = (PhyAddr << MVEBU_SMI_DEV_ADDR_OFFS)
+      | (RegOff << MVEBU_SMI_REG_ADDR_OFFS);
+  if (Write) {
+    MdioReg &= ~MVEBU_SMI_OPCODE_READ;
+    MdioReg |= (*Data << MVEBU_SMI_DATA_OFFS);
+  } else {
+    MdioReg |= MVEBU_SMI_OPCODE_READ;
+  }
+
+  /* write the smi register */
+  MdioRegWrite32 (MdioReg, MdioBase);
+
+  /* make sure that the write transaction  is over */
+  Status = Write ? MdioWaitReady () : MdioWaitValid ();
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "MdioDxe: MdioWaitReady error\n"));
+    return Status;
+  }
+
+  if (!Write) {
+    *Data = MmioRead32 (MdioBase) & MVEBU_SMI_DATA_MASK;
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+MvMdioRead (
+  IN CONST MARVELL_MDIO_PROTOCOL *This,
+  IN UINT32 PhyAddr,
+  IN UINT32 RegOff,
+  IN UINT32 *Data
+  )
+{
+  EFI_STATUS Status;
+
+  Status = MdioOperation (
+            This,
+            PhyAddr,
+            RegOff,
+            FALSE,
+            Data
+            );
+
+  return Status;
+}
+
+EFI_STATUS
+MvMdioWrite (
+  IN CONST MARVELL_MDIO_PROTOCOL *This,
+  IN UINT32 PhyAddr,
+  IN UINT32 RegOff,
+  IN UINT32 Data
+  )
+{
+  return MdioOperation (
+            This,
+            PhyAddr,
+            RegOff,
+            TRUE,
+            &Data
+            );
+}
+
+EFI_STATUS
+EFIAPI
+MvMdioDxeInitialise (
+  IN EFI_HANDLE  ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  MARVELL_MDIO_PROTOCOL *Mdio;
+  EFI_STATUS Status;
+  EFI_HANDLE Handle = NULL;
+
+  Mdio = AllocateZeroPool (sizeof (MARVELL_MDIO_PROTOCOL));
+  Mdio->Read = MvMdioRead;
+  Mdio->Write = MvMdioWrite;
+  MdioBase = PcdGet64 (PcdMdioBaseAddress);
+  if (MdioBase == 0) {
+    DEBUG((DEBUG_ERROR, "MdioDxe: PcdMdioBaseAddress not set\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gMarvellMdioProtocolGuid, Mdio,
+                  NULL
+                  );
+
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "Failed to install interfaces\n"));
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/Net/MvMdioDxe/MvMdioDxe.h b/Drivers/Net/MvMdioDxe/MvMdioDxe.h
new file mode 100644
index 0000000..b41a1e6
--- /dev/null
+++ b/Drivers/Net/MvMdioDxe/MvMdioDxe.h
@@ -0,0 +1,57 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MDIO_DXE_H__
+#define __MDIO_DXE_H__
+
+#include <Uefi.h>
+
+#define MVEBU_SMI_TIMEOUT      10000
+
+/* SMI register fields */
+#define  MVEBU_SMI_DATA_OFFS      0  /* Data */
+#define  MVEBU_SMI_DATA_MASK      (0xffff << MVEBU_SMI_DATA_OFFS)
+#define  MVEBU_SMI_DEV_ADDR_OFFS      16  /* PHY device address */
+#define  MVEBU_SMI_REG_ADDR_OFFS      21  /* PHY device reg addr*/
+#define  MVEBU_SMI_OPCODE_OFFS      26  /* Write/Read opcode */
+#define  MVEBU_SMI_OPCODE_READ      (1 << MVEBU_SMI_OPCODE_OFFS)
+#define  MVEBU_SMI_READ_VALID      (1 << 27)  /* Read Valid */
+#define  MVEBU_SMI_BUSY        (1 << 28)  /* Busy */
+
+#define  MVEBU_PHY_REG_MASK      0x1f
+#define  MVEBU_PHY_ADDR_MASK      0x1f
+
+#define MdioRegWrite32(x, y) MmioWrite32((y), (x))
+
+#endif // __MDIO_DXE_H__
diff --git a/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
new file mode 100644
index 0000000..c6dc443
--- /dev/null
+++ b/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
@@ -0,0 +1,69 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+#  * Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+#  * Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+#  * Neither the name of Marvell nor the names of its contributors may be
+#    used to endorse or promote products derived from this software without
+#    specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MdioDxe
+  FILE_GUID                      = 59fc3843-d8d4-40ba-ae07-38967138509c
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = MvMdioDxeInitialise
+
+[Sources.common]
+  MvMdioDxe.c
+  MvMdioDxe.h
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  IoLib
+  PcdLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Protocols]
+  gMarvellMdioProtocolGuid
+
+[Pcd]
+  gMarvellTokenSpaceGuid.PcdMdioBaseAddress
+
+[Depex]
+  TRUE
diff --git a/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c
new file mode 100644
index 0000000..aeb6f7a
--- /dev/null
+++ b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c
@@ -0,0 +1,438 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <Protocol/DriverBinding.h>
+#include <Protocol/Mdio.h>
+#include <Protocol/MvPhy.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include "MvPhyDxe.h"
+
+#define TIMEOUT   500
+
+STATIC MARVELL_MDIO_PROTOCOL *Mdio;
+
+STATIC MV_PHY_DEVICE MvPhyDevices[] = {
+  { MV_PHY_DEVICE_1512, MvPhyInit1512 },
+  { 0, NULL }
+};
+
+EFI_STATUS
+MvPhyStatus (
+  IN CONST MARVELL_PHY_PROTOCOL *This,
+  IN PHY_DEVICE  *PhyDev
+  );
+
+EFI_STATUS
+MvPhyReset (
+  IN UINT32 PhyAddr
+  )
+{
+  UINT32 Reg = 0;
+  INTN timeout = TIMEOUT;
+
+  Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg);
+  Reg |= BMCR_RESET;
+  Mdio->Write(Mdio, PhyAddr, MII_BMCR, Reg);
+
+  while ((Reg & BMCR_RESET) && timeout--) {
+    Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg);
+    gBS->Stall(1000);
+  }
+
+  if (Reg & BMCR_RESET) {
+    DEBUG((DEBUG_ERROR, "PHY reset timed out\n"));
+    return EFI_TIMEOUT;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/* Marvell 88E1111S */
+EFI_STATUS
+MvPhyM88e1111sConfig (
+  IN PHY_DEVICE *PhyDev
+  )
+{
+  UINT32 Reg;
+
+  if ((PhyDev->Connection == PHY_CONNECTION_RGMII) ||
+      (PhyDev->Connection == PHY_CONNECTION_RGMII_ID) ||
+      (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) ||
+      (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID)) {
+    Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg);
+
+    if ((PhyDev->Connection == PHY_CONNECTION_RGMII) ||
+      (PhyDev->Connection == PHY_CONNECTION_RGMII_ID)) {
+      Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
+    } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) {
+      Reg &= ~MIIM_88E1111_TX_DELAY;
+      Reg |= MIIM_88E1111_RX_DELAY;
+    } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID) {
+      Reg &= ~MIIM_88E1111_RX_DELAY;
+      Reg |= MIIM_88E1111_TX_DELAY;
+    }
+
+    Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg);
+
+    Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg);
+
+    Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
+
+    if (Reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
+      Reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
+    else
+      Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
+
+    Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg);
+  }
+
+  if (PhyDev->Connection == PHY_CONNECTION_SGMII) {
+    Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg);
+
+    Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
+    Reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
+    Reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
+
+    Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg);
+  }
+
+  if (PhyDev->Connection == PHY_CONNECTION_RTBI) {
+    Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg);
+    Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
+    Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg);
+
+    Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg);
+    Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
+      MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
+    Reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
+    Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg);
+
+    /* Soft reset */
+    MvPhyReset(PhyDev->Addr);
+
+    Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg);
+    Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
+      MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
+    Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
+      MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
+    Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg);
+  }
+
+  Mdio->Read(Mdio, PhyDev->Addr, MII_BMCR, &Reg);
+  Reg |= (BMCR_ANENABLE | BMCR_ANRESTART);
+  Reg &= ~BMCR_ISOLATE;
+  Mdio->Write(Mdio, PhyDev->Addr, MII_BMCR, Reg);
+
+  /* Soft reset */
+  MvPhyReset(PhyDev->Addr);
+
+  MvPhyReset(PhyDev->Addr);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MvPhyParseStatus (
+  IN PHY_DEVICE *PhyDev
+  )
+{
+  UINT32 Data;
+  UINT32 Speed;
+
+  Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data);
+
+  if ((Data & MIIM_88E1xxx_PHYSTAT_LINK) &&
+    !(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
+    INTN i = 0;
+
+    DEBUG((DEBUG_ERROR,"MvPhyDxe: Waiting for PHY realtime link"));
+    while (!(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
+      if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+        DEBUG((DEBUG_ERROR," TIMEOUT !\n"));
+        PhyDev->LinkUp = FALSE;
+        break;
+      }
+
+      if ((i++ % 1000) == 0)
+        DEBUG((DEBUG_ERROR, "."));
+      gBS->Stall(1000);
+      Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data);
+    }
+    DEBUG((DEBUG_ERROR," done\n"));
+    gBS->Stall(500000);
+  } else {
+    if (Data & MIIM_88E1xxx_PHYSTAT_LINK) {
+      DEBUG((DEBUG_ERROR, "MvPhyDxe: link up, "));
+      PhyDev->LinkUp = TRUE;
+    } else {
+      DEBUG((DEBUG_ERROR, "MvPhyDxe: link down, "));
+      PhyDev->LinkUp = FALSE;
+    }
+  }
+
+  if (Data & MIIM_88E1xxx_PHYSTAT_DUPLEX) {
+    DEBUG((DEBUG_ERROR, "full duplex, "));
+    PhyDev->FullDuplex = TRUE;
+  } else {
+    DEBUG((DEBUG_ERROR, "half duplex, "));
+    PhyDev->FullDuplex = FALSE;
+  }
+
+  Speed = Data & MIIM_88E1xxx_PHYSTAT_SPEED;
+
+  switch (Speed) {
+  case MIIM_88E1xxx_PHYSTAT_GBIT:
+    DEBUG((DEBUG_ERROR, "speed 1000\n"));
+    PhyDev->Speed = SPEED_1000;
+    break;
+  case MIIM_88E1xxx_PHYSTAT_100:
+    DEBUG((DEBUG_ERROR, "speed 100\n"));
+    PhyDev->Speed = SPEED_100;
+    break;
+  default:
+    DEBUG((DEBUG_ERROR, "speed 10\n"));
+    PhyDev->Speed = SPEED_10;
+    break;
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+MvPhy1512WriteBits (
+  IN UINT32 PhyAddr,
+  IN UINT8 RegNum,
+  IN UINT16 Offset,
+  IN UINT16 Len,
+  IN UINT16 Data)
+{
+  UINT32 Reg, Mask;
+
+  if ((Len + Offset) >= 16)
+    Mask = 0 - (1 << Offset);
+  else
+    Mask = (1 << (Len + Offset)) - (1 << Offset);
+
+  Mdio->Read(Mdio, PhyAddr, RegNum, &Reg);
+
+  Reg &= ~Mask;
+  Reg |= Data << Offset;
+
+  Mdio->Write(Mdio, PhyAddr, RegNum, Reg);
+}
+
+STATIC
+EFI_STATUS
+MvPhyInit1512 (
+    IN CONST MARVELL_PHY_PROTOCOL *Snp,
+    IN UINT32 PhyAddr,
+    IN OUT PHY_DEVICE *PhyDev
+    )
+{
+  UINT32 Data;
+  INTN i;
+
+  if (PhyDev->Connection == PHY_CONNECTION_SGMII) {
+    /* Select page 0xff and update configuration registers according to
+     * Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 Rev A0,
+     * Errata Section 3.1 - needed in SGMII mode.
+     */
+    Mdio->Write(Mdio, PhyAddr, 22, 0x00ff);
+    Mdio->Write(Mdio, PhyAddr, 17, 0x214B);
+    Mdio->Write(Mdio, PhyAddr, 16, 0x2144);
+    Mdio->Write(Mdio, PhyAddr, 17, 0x0C28);
+    Mdio->Write(Mdio, PhyAddr, 16, 0x2146);
+    Mdio->Write(Mdio, PhyAddr, 17, 0xB233);
+    Mdio->Write(Mdio, PhyAddr, 16, 0x214D);
+    Mdio->Write(Mdio, PhyAddr, 17, 0xCC0C);
+    Mdio->Write(Mdio, PhyAddr, 16, 0x2159);
+
+    /* Reset page selection and select page 0x12 */
+    Mdio->Write(Mdio, PhyAddr, 22, 0x0000);
+    Mdio->Write(Mdio, PhyAddr, 22, 0x0012);
+
+    /* Write HWCFG_MODE = SGMII to Copper */
+    MvPhy1512WriteBits(PhyAddr, 20, 0, 3, 1);
+
+    /* Phy reset - necessary after changing mode */
+    MvPhy1512WriteBits(PhyAddr, 20, 15, 1, 1);
+
+    /* Reset page selection */
+    Mdio->Write(Mdio, PhyAddr, 22, 0x0000);
+    gBS->Stall(100);
+  }
+
+  MvPhyM88e1111sConfig (PhyDev);
+
+  /* autonegotiation on startup is not always required */
+  if (!PcdGetBool (PcdPhyStartupAutoneg))
+    return EFI_SUCCESS;
+
+  Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data);
+
+  if ((Data & BMSR_ANEGCAPABLE) && !(Data & BMSR_ANEGCOMPLETE)) {
+
+    DEBUG((DEBUG_ERROR, "MvPhyDxe: Waiting for PHY auto negotiation... "));
+    for (i = 0; !(Data & BMSR_ANEGCOMPLETE); i++) {
+      if (i > PHY_ANEG_TIMEOUT) {
+        DEBUG((DEBUG_ERROR, "timeout\n"));
+        PhyDev->LinkUp = FALSE;
+        return EFI_TIMEOUT;
+      }
+
+      gBS->Stall(1000);  /* 1 ms */
+      Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data);
+    }
+    PhyDev->LinkUp = TRUE;
+    DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n"));
+  } else {
+    Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data);
+
+    if (Data & BMSR_LSTATUS) {
+      PhyDev->LinkUp = TRUE;
+      DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n"));
+    } else {
+      PhyDev->LinkUp = FALSE;
+      DEBUG((DEBUG_INFO, "MvPhyDxe: link down\n"));
+    }
+  }
+  MvPhyParseStatus (PhyDev);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MvPhyInit (
+  IN CONST MARVELL_PHY_PROTOCOL *Snp,
+  IN UINT32 PhyAddr,
+  IN PHY_CONNECTION PhyConnection,
+  IN OUT PHY_DEVICE **OutPhyDev
+  )
+{
+  EFI_STATUS Status;
+  PHY_DEVICE *PhyDev;
+  UINT8 *DeviceIds;
+  INTN i;
+
+  Status = gBS->LocateProtocol (
+      &gMarvellMdioProtocolGuid,
+      NULL,
+      (VOID **) &Mdio
+      );
+  if (EFI_ERROR(Status))
+    return Status;
+
+  /* perform setup common for all PHYs */
+  PhyDev = AllocateZeroPool (sizeof (PHY_DEVICE));
+  PhyDev->Addr = PhyAddr;
+  PhyDev->Connection = PhyConnection;
+  DEBUG((DEBUG_INFO, "MvPhyDxe: PhyAddr is %d, connection %d\n",
+        PhyAddr, PhyConnection));
+  *OutPhyDev = PhyDev;
+
+  DeviceIds = PcdGetPtr (PcdPhyDeviceIds);
+  for (i = 0; i < PcdGetSize (PcdPhyDeviceIds); i++) {
+    /* find MvPhyDevices fitting entry */
+    if (MvPhyDevices[i].DevId == DeviceIds[i]) {
+      ASSERT (MvPhyDevices[i].DevInit != NULL);
+      /* proceed with PHY-specific initialization */
+      return MvPhyDevices[i].DevInit(Snp, PhyAddr, PhyDev);
+    }
+  }
+
+  /* if we are here, no matching DevId was found */
+  Status = EFI_INVALID_PARAMETER;
+  FreePool (PhyDev);
+  return Status;
+}
+
+EFI_STATUS
+MvPhyStatus (
+  IN CONST MARVELL_PHY_PROTOCOL *This,
+  IN PHY_DEVICE  *PhyDev
+  )
+{
+  UINT32 Data;
+
+  Mdio->Read(Mdio, PhyDev->Addr, MII_BMSR, &Data);
+  Mdio->Read(Mdio, PhyDev->Addr, MII_BMSR, &Data);
+
+  if ((Data & BMSR_LSTATUS) == 0) {
+    PhyDev->LinkUp = FALSE;
+  } else {
+    PhyDev->LinkUp = TRUE;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvPhyDxeInitialise (
+  IN EFI_HANDLE  ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  MARVELL_PHY_PROTOCOL *Phy;
+  EFI_STATUS Status;
+  EFI_HANDLE Handle = NULL;
+
+  Phy = AllocateZeroPool (sizeof (MARVELL_PHY_PROTOCOL));
+  Phy->Status = MvPhyStatus;
+  Phy->Init = MvPhyInit;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gMarvellPhyProtocolGuid, Phy,
+                  NULL
+                  );
+
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "Failed to install interfaces\n"));
+    return Status;
+  }
+  DEBUG((DEBUG_ERROR, "Succesfully installed protocol interfaces\n"));
+
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h
new file mode 100644
index 0000000..6bd06c5
--- /dev/null
+++ b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h
@@ -0,0 +1,194 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __MV_PHY_DXE_H__
+#define __MV_PHY_DXE_H__
+
+#define MII_BMCR      0x00  /* Basic mode control Register */
+#define MII_BMSR      0x01  /* Basic mode status Register  */
+#define MII_PHYSID1      0x02  /* PHYS ID 1           */
+#define MII_PHYSID2      0x03  /* PHYS ID 2           */
+#define MII_ADVERTISE      0x04  /* Advertisement control Reg   */
+#define MII_LPA        0x05  /* Link partner ability Reg    */
+#define MII_EXPANSION      0x06  /* Expansion Register         */
+#define MII_CTRL1000      0x09  /* 1000BASE-T control         */
+#define MII_STAT1000      0x0a  /* 1000BASE-T status         */
+#define MII_ESTATUS      0x0f  /* Extended Status */
+#define MII_DCOUNTER      0x12  /* Disconnect counter         */
+#define MII_FCSCOUNTER      0x13  /* False carrier counter       */
+#define MII_NWAYTEST      0x14  /* N-way auto-neg test Reg     */
+#define MII_RERRCOUNTER     0x15  /* Receive error counter       */
+#define MII_SREVISION      0x16  /* Silicon revision         */
+#define MII_RESV1      0x17  /* Reserved...           */
+#define MII_LBRERROR      0x18  /* Lpback, rx, bypass error    */
+#define MII_PHYADDR      0x19  /* PHY address           */
+#define MII_RESV2      0x1a  /* Reserved...           */
+#define MII_TPISTATUS      0x1b  /* TPI status for 10mbps       */
+#define MII_NCONFIG      0x1c  /* Network interface config    */
+
+/* Basic mode control Register. */
+#define BMCR_RESV    0x003f  /* Unused...           */
+#define BMCR_SPEED1000    0x0040  /* MSB of Speed (1000)         */
+#define BMCR_CTST    0x0080  /* Collision test         */
+#define BMCR_FULLDPLX    0x0100  /* Full duplex           */
+#define BMCR_ANRESTART    0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE    0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN    0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE    0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100    0x2000  /* Select 100Mbps         */
+#define BMCR_LOOPBACK    0x4000  /* TXD loopback bits         */
+#define BMCR_RESET    0x8000  /* Reset the DP83840         */
+
+/* Basic mode status Register. */
+#define BMSR_ERCAP    0x0001  /* Ext-Reg capability         */
+#define BMSR_JCD    0x0002  /* Jabber detected         */
+#define BMSR_LSTATUS    0x0004  /* Link status           */
+#define BMSR_ANEGCAPABLE  0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT    0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE  0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV    0x00c0  /* Unused...           */
+#define BMSR_ESTATEN    0x0100  /* Extended Status in R15 */
+#define BMSR_100HALF2    0x0200  /* Can do 100BASE-T2 HDX */
+#define BMSR_100FULL2    0x0400  /* Can do 100BASE-T2 FDX */
+#define BMSR_10HALF    0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL    0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF    0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL    0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4    0x8000  /* Can do 100mbps, 4k packets  */
+
+#define PHY_ANEG_TIMEOUT 4000
+
+#define PHY_INTERFACE_MODE_RGMII 0
+#define PHY_INTERFACE_MODE_RGMII_ID 1
+#define PHY_INTERFACE_MODE_RGMII_RXID 2
+#define PHY_INTERFACE_MODE_RGMII_TXID 3
+#define PHY_INTERFACE_MODE_SGMII 4
+#define PHY_INTERFACE_MODE_RTBI 5
+
+#define PHY_AUTONEGOTIATE_TIMEOUT 5000
+
+/* 88E1011 PHY Status Register */
+#define MIIM_88E1xxx_PHY_STATUS    0x11
+#define MIIM_88E1xxx_PHYSTAT_SPEED  0xc000
+#define MIIM_88E1xxx_PHYSTAT_GBIT  0x8000
+#define MIIM_88E1xxx_PHYSTAT_100  0x4000
+#define MIIM_88E1xxx_PHYSTAT_DUPLEX  0x2000
+#define MIIM_88E1xxx_PHYSTAT_SPDDONE  0x0800
+#define MIIM_88E1xxx_PHYSTAT_LINK  0x0400
+
+#define MIIM_88E1xxx_PHY_SCR    0x10
+#define MIIM_88E1xxx_PHY_MDI_X_AUTO  0x0060
+
+/* 88E1111 PHY LED Control Register */
+#define MIIM_88E1111_PHY_LED_CONTROL  24
+#define MIIM_88E1111_PHY_LED_DIRECT  0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE  0x411C
+
+/* 88E1111 Extended PHY Specific Control Register */
+#define MIIM_88E1111_PHY_EXT_CR    0x14
+#define MIIM_88E1111_RX_DELAY    0x80
+#define MIIM_88E1111_TX_DELAY    0x2
+
+/* 88E1111 Extended PHY Specific Status Register */
+#define MIIM_88E1111_PHY_EXT_SR    0x1b
+#define MIIM_88E1111_HWCFG_MODE_MASK    0xf
+#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII  0xb
+#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII  0x3
+#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK  0x4
+#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI  0x9
+#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO  0x8000
+#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES  0x2000
+
+#define MIIM_88E1111_COPPER    0
+#define MIIM_88E1111_FIBER    1
+
+/* 88E1118 PHY defines */
+#define MIIM_88E1118_PHY_PAGE    22
+#define MIIM_88E1118_PHY_LED_PAGE  3
+
+/* 88E1121 PHY LED Control Register */
+#define MIIM_88E1121_PHY_LED_CTRL  16
+#define MIIM_88E1121_PHY_LED_PAGE  3
+#define MIIM_88E1121_PHY_LED_DEF  0x0030
+
+/* 88E1121 PHY IRQ Enable/Status Register */
+#define MIIM_88E1121_PHY_IRQ_EN    18
+#define MIIM_88E1121_PHY_IRQ_STATUS  19
+
+#define MIIM_88E1121_PHY_PAGE    22
+
+/* 88E1145 Extended PHY Specific Control Register */
+#define MIIM_88E1145_PHY_EXT_CR 20
+#define MIIM_M88E1145_RGMII_RX_DELAY  0x0080
+#define MIIM_M88E1145_RGMII_TX_DELAY  0x0002
+
+#define MIIM_88E1145_PHY_LED_CONTROL  24
+#define MIIM_88E1145_PHY_LED_DIRECT  0x4100
+
+#define MIIM_88E1145_PHY_PAGE  29
+#define MIIM_88E1145_PHY_CAL_OV 30
+
+#define MIIM_88E1149_PHY_PAGE  29
+
+/* 88E1310 PHY defines */
+#define MIIM_88E1310_PHY_LED_CTRL  16
+#define MIIM_88E1310_PHY_IRQ_EN    18
+#define MIIM_88E1310_PHY_RGMII_CTRL  21
+#define MIIM_88E1310_PHY_PAGE    22
+
+typedef enum {
+  MV_PHY_DEVICE_1512
+} MV_PHY_DEVICE_ID;
+
+typedef
+EFI_STATUS
+(*MV_PHY_DEVICE_INIT) (
+    IN CONST MARVELL_PHY_PROTOCOL *Snp,
+    IN UINT32 PhyAddr,
+    IN OUT PHY_DEVICE *PhyDev
+    );
+
+typedef struct {
+  MV_PHY_DEVICE_ID DevId;
+  MV_PHY_DEVICE_INIT DevInit;
+} MV_PHY_DEVICE;
+
+STATIC
+EFI_STATUS
+MvPhyInit1512 (
+    IN CONST MARVELL_PHY_PROTOCOL *Snp,
+    IN UINT32 PhyAddr,
+    IN OUT PHY_DEVICE *PhyDev
+    );
+
+#endif
diff --git a/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
new file mode 100644
index 0000000..713eada
--- /dev/null
+++ b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
@@ -0,0 +1,71 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+#  * Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+#  * Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+#  * Neither the name of Marvell nor the names of its contributors may be
+#    used to endorse or promote products derived from this software without
+#    specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MvPhyDxe
+  FILE_GUID                      = 5aac3843-d8d4-40ba-ae07-38967138509c
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = MvPhyDxeInitialise
+
+[Sources.common]
+  MvPhyDxe.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  IoLib
+  PcdLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Protocols]
+  gMarvellMdioProtocolGuid
+  gMarvellPhyProtocolGuid
+
+[Pcd]
+  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
+
+[Depex]
+  TRUE
diff --git a/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
new file mode 100644
index 0000000..cdd0979
--- /dev/null
+++ b/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
@@ -0,0 +1,4839 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "Mvpp2Lib.h"
+#include "Mvpp2LibHw.h"
+#include "Pp2Dxe.h"
+
+/* Parser configuration routines */
+
+/* Update parser Tcam and Sram hw entries */
+STATIC
+INT32
+Mvpp2PrsHwWrite (
+  IN MVPP2_SHARED *Priv,
+  IN OUT MVPP2_PRS_ENTRY *Pe
+  )
+{
+  INT32 i;
+
+  if (Pe->Index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) {
+    return MVPP2_EINVAL;
+  }
+
+  /* Clear entry invalidation bit */
+  Pe->Tcam.Word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
+
+  /* Write Tcam Index - indirect access */
+  Mvpp2Write (Priv, MVPP2_PRS_TCAM_IDX_REG, Pe->Index);
+  for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) {
+    Mvpp2Write (Priv, MVPP2_PRS_TCAM_DATA_REG(i), Pe->Tcam.Word[i]);
+  }
+
+  /* Write Sram Index - indirect access */
+  Mvpp2Write (Priv, MVPP2_PRS_SRAM_IDX_REG, Pe->Index);
+  for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) {
+    Mvpp2Write (Priv, MVPP2_PRS_SRAM_DATA_REG(i), Pe->Sram.Word[i]);
+  }
+
+  return 0;
+}
+
+/* Read Tcam entry from hw */
+STATIC
+INT32
+Mvpp2PrsHwRead (
+  IN MVPP2_SHARED *Priv,
+  IN OUT MVPP2_PRS_ENTRY *Pe
+  )
+{
+  INT32 i;
+
+  if (Pe->Index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) {
+    return MVPP2_EINVAL;
+  }
+
+  /* Write Tcam Index - indirect access */
+  Mvpp2Write (Priv, MVPP2_PRS_TCAM_IDX_REG, Pe->Index);
+
+  Pe->Tcam.Word[MVPP2_PRS_TCAM_INV_WORD] =
+    Mvpp2Read (Priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
+  if (Pe->Tcam.Word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) {
+    return MVPP2_PRS_TCAM_ENTRY_INVALID;
+  }
+
+  for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) {
+    Pe->Tcam.Word[i] = Mvpp2Read (Priv, MVPP2_PRS_TCAM_DATA_REG(i));
+  }
+
+  /* Write Sram Index - indirect access */
+  Mvpp2Write (Priv, MVPP2_PRS_SRAM_IDX_REG, Pe->Index);
+  for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) {
+    Pe->Sram.Word[i] = Mvpp2Read (Priv, MVPP2_PRS_SRAM_DATA_REG(i));
+  }
+
+  return 0;
+}
+
+/* Invalidate Tcam hw entry */
+STATIC
+VOID
+Mvpp2PrsHwInv (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Index
+  )
+{
+  /* Write Index - indirect access */
+  Mvpp2Write (Priv, MVPP2_PRS_TCAM_IDX_REG, Index);
+  Mvpp2Write (Priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
+        MVPP2_PRS_TCAM_INV_MASK);
+}
+
+/* Enable shadow table entry and set its lookup ID */
+STATIC
+VOID
+Mvpp2PrsShadowSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Index,
+  IN INT32 Lu
+  )
+{
+  Priv->PrsShadow[Index].Valid = TRUE;
+  Priv->PrsShadow[Index].Lu = Lu;
+}
+
+/* Update Ri fields in shadow table entry */
+STATIC
+VOID
+Mvpp2PrsShadowRiSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Index,
+  IN UINT32 Ri,
+  IN UINT32 RiMask
+  )
+{
+  Priv->PrsShadow[Index].RiMask = RiMask;
+  Priv->PrsShadow[Index].Ri = Ri;
+}
+
+/* Update lookup field in Tcam sw entry */
+STATIC
+VOID
+Mvpp2PrsTcamLuSet (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 Lu
+  )
+{
+  INT32 EnableOff = MVPP2_PRS_TCAM_EN_OFFS (MVPP2_PRS_TCAM_LU_BYTE);
+
+  Pe->Tcam.Byte[MVPP2_PRS_TCAM_LU_BYTE] = Lu;
+  Pe->Tcam.Byte[EnableOff] = MVPP2_PRS_LU_MASK;
+}
+
+/* Update Mask for single Port in Tcam sw entry */
+STATIC
+VOID
+Mvpp2PrsTcamPortSet (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 PortId,
+  IN BOOLEAN Add
+  )
+{
+  INT32 EnableOff = MVPP2_PRS_TCAM_EN_OFFS (MVPP2_PRS_TCAM_PORT_BYTE);
+
+  if (Add) {
+    Pe->Tcam.Byte[EnableOff] &= ~(1 << PortId);
+  } else {
+    Pe->Tcam.Byte[EnableOff] |= 1 << PortId;
+  }
+}
+
+/* Update Port map in Tcam sw entry */
+STATIC
+VOID
+Mvpp2PrsTcamPortMapSet (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 PortMask
+  )
+{
+  INT32 EnableOff = MVPP2_PRS_TCAM_EN_OFFS (MVPP2_PRS_TCAM_PORT_BYTE);
+  UINT8 Mask = MVPP2_PRS_PORT_MASK;
+
+  Pe->Tcam.Byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
+  Pe->Tcam.Byte[EnableOff] &= ~Mask;
+  Pe->Tcam.Byte[EnableOff] |= ~PortMask & MVPP2_PRS_PORT_MASK;
+}
+
+/* Obtain Port map from Tcam sw entry */
+STATIC
+UINT32
+Mvpp2PrsTcamPortMapGet (
+  IN MVPP2_PRS_ENTRY *Pe
+  )
+{
+  INT32 EnableOff = MVPP2_PRS_TCAM_EN_OFFS (MVPP2_PRS_TCAM_PORT_BYTE);
+
+  return ~(Pe->Tcam.Byte[EnableOff]) & MVPP2_PRS_PORT_MASK;
+}
+
+/* Set Byte of data and its enable bits in Tcam sw entry */
+STATIC
+VOID
+Mvpp2PrsTcamDataByteSet (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 Offs,
+  IN UINT8 Byte,
+  IN UINT8 Enable
+  )
+{
+  Pe->Tcam.Byte[MVPP2_PRS_TCAM_DATA_BYTE(Offs)] = Byte;
+  Pe->Tcam.Byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(Offs)] = Enable;
+}
+
+/* Get Byte of data and its enable bits from Tcam sw entry */
+STATIC
+VOID
+Mvpp2PrsTcamDataByteGet (
+  IN MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 Offs,
+  OUT UINT8 *Byte,
+  OUT UINT8 *Enable
+  )
+{
+  *Byte = Pe->Tcam.Byte[MVPP2_PRS_TCAM_DATA_BYTE(Offs)];
+  *Enable = Pe->Tcam.Byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(Offs)];
+}
+
+/* Compare Tcam data bytes with a pattern */
+STATIC
+BOOLEAN
+Mvpp2PrsTcamDataCmp (
+  IN MVPP2_PRS_ENTRY *Pe,
+  IN INT32 Offset,
+  IN UINT16 Data
+  )
+{
+  INT32 ByteOffset = MVPP2_PRS_TCAM_DATA_BYTE(Offset);
+  UINT16 TcamData;
+
+  TcamData = (Pe->Tcam.Byte[ByteOffset + 1] << 8) | Pe->Tcam.Byte[ByteOffset];
+  if (TcamData != Data) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/* Update ai bits in Tcam sw entry */
+STATIC
+VOID
+Mvpp2PrsTcamAiUpdate (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 Bits,
+  IN UINT32 Enable
+  )
+{
+  INT32 i, AiIdx = MVPP2_PRS_TCAM_AI_BYTE;
+
+  for (i = 0; i < MVPP2_PRS_AI_BITS; i++) {
+
+    if (!(Enable & BIT (i))) {
+      continue;
+    }
+
+    if (Bits & BIT (i)) {
+      Pe->Tcam.Byte[AiIdx] |= 1 << i;
+    } else {
+      Pe->Tcam.Byte[AiIdx] &= ~(1 << i);
+    }
+  }
+
+  Pe->Tcam.Byte[MVPP2_PRS_TCAM_EN_OFFS (AiIdx)] |= Enable;
+}
+
+/* Get ai bits from Tcam sw entry */
+STATIC
+INT32
+Mvpp2PrsTcamAiGet (
+  IN MVPP2_PRS_ENTRY *Pe
+  )
+{
+  return Pe->Tcam.Byte[MVPP2_PRS_TCAM_AI_BYTE];
+}
+
+/* Get word of data and its enable bits from Tcam sw entry */
+STATIC
+VOID
+Mvpp2PrsTcamDataWordGet (
+  IN MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 DataOffset,
+  OUT UINT32 *Word,
+  OUT UINT32 *Enable
+  )
+{
+  INT32 Index, Position;
+  UINT8 Byte, Mask;
+
+  for (Index = 0; Index < 4; Index++) {
+    Position = (DataOffset * sizeof (INT32)) + Index;
+    Mvpp2PrsTcamDataByteGet (Pe, Position, &Byte, &Mask);
+    ((UINT8 *)Word)[Index] = Byte;
+    ((UINT8 *)Enable)[Index] = Mask;
+  }
+}
+
+/* Set ethertype in Tcam sw entry */
+STATIC
+VOID
+Mvpp2PrsMatchEtype (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN INT32 Offset,
+  IN UINT16 EtherType
+  )
+{
+  Mvpp2PrsTcamDataByteSet (Pe, Offset + 0, EtherType >> 8, 0xff);
+  Mvpp2PrsTcamDataByteSet (Pe, Offset + 1, EtherType & 0xff, 0xff);
+}
+
+/* Set bits in Sram sw entry */
+STATIC
+VOID
+Mvpp2PrsSramBitsSet (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN INT32 BitNum,
+  IN INT32 Val
+  )
+{
+  Pe->Sram.Byte[MVPP2_BIT_TO_BYTE(BitNum)] |= (Val << (BitNum % 8));
+}
+
+/* Clear bits in Sram sw entry */
+STATIC
+VOID
+Mvpp2PrsSramBitsClear (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN INT32 BitNum,
+  IN INT32 Val
+  )
+{
+  Pe->Sram.Byte[MVPP2_BIT_TO_BYTE(BitNum)] &= ~(Val << (BitNum % 8));
+}
+
+/* Update Ri bits in Sram sw entry */
+STATIC
+VOID
+Mvpp2PrsSramRiUpdate (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 bits,
+  IN UINT32 Mask
+  )
+{
+  UINT32 i;
+
+  for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
+    INT32 RiOff = MVPP2_PRS_SRAM_RI_OFFS;
+
+    if (!(Mask & BIT (i))) {
+      continue;
+    }
+
+    if (bits & BIT (i)) {
+      Mvpp2PrsSramBitsSet (Pe, RiOff + i, 1);
+    } else {
+      Mvpp2PrsSramBitsClear (Pe, RiOff + i, 1);
+    }
+
+    Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
+  }
+}
+
+/* Obtain Ri bits from Sram sw entry */
+STATIC
+INT32
+Mvpp2PrsSramRiGet (
+  IN MVPP2_PRS_ENTRY *Pe
+  )
+{
+  return Pe->Sram.Word[MVPP2_PRS_SRAM_RI_WORD];
+}
+
+/* Update ai bits in Sram sw entry */
+STATIC
+VOID
+Mvpp2PrsSramAiUpdate (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 Bits,
+  UINT32 Mask
+  )
+{
+  UINT32 i;
+  INT32 AiOff = MVPP2_PRS_SRAM_AI_OFFS;
+
+  for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
+
+    if (!(Mask & BIT (i))) {
+      continue;
+    }
+
+    if (Bits & BIT (i)) {
+      Mvpp2PrsSramBitsSet (Pe, AiOff + i, 1);
+    } else {
+      Mvpp2PrsSramBitsClear (Pe, AiOff + i, 1);
+    }
+
+    Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
+  }
+}
+
+/* Read ai bits from Sram sw entry */
+STATIC
+INT32
+Mvpp2PrsSramAiGet (
+  IN MVPP2_PRS_ENTRY *Pe
+  )
+{
+  UINT8 bits;
+  INT32 AiOff = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
+  INT32 AiEnOff = AiOff + 1;
+  INT32 AiShift = MVPP2_PRS_SRAM_AI_OFFS % 8;
+
+  bits = (Pe->Sram.Byte[AiOff] >> AiShift) |
+         (Pe->Sram.Byte[AiEnOff] << (8 - AiShift));
+
+  return bits;
+}
+
+/*
+ * In Sram sw entry set lookup ID field of the
+ * Tcam key to be used in the next lookup iteration
+ */
+STATIC
+VOID
+Mvpp2PrsSramNextLuSet (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 Lu
+  )
+{
+  INT32 SramNextOff = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
+
+  Mvpp2PrsSramBitsClear (Pe, SramNextOff, MVPP2_PRS_SRAM_NEXT_LU_MASK);
+  Mvpp2PrsSramBitsSet (Pe, SramNextOff, Lu);
+}
+
+/*
+ * In the Sram sw entry set sign and value of the next lookup Offset
+ * and the Offset value generated to the classifier
+ */
+STATIC
+VOID
+Mvpp2PrsSramShiftSet (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN INT32 Shift,
+  IN UINT32 Op
+  )
+{
+  /* Set sign */
+  if (Shift < 0) {
+    Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
+    Shift = -Shift;
+  } else {
+    Mvpp2PrsSramBitsClear (Pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
+  }
+
+  /* Set value */
+  Pe->Sram.Byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = (UINT8)Shift;
+
+  /* Reset and set operation */
+  Mvpp2PrsSramBitsClear (Pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
+  Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, Op);
+
+  /* Set base Offset as current */
+  Mvpp2PrsSramBitsClear (Pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
+}
+
+/*
+ * In the Sram sw entry set sign and value of the user defined offset
+ * generated for the classifier
+ */
+STATIC
+VOID
+Mvpp2PrsSramOffsetSet (
+  IN OUT MVPP2_PRS_ENTRY *Pe,
+  IN UINT32 Type,
+  IN INT32 Offset,
+  IN UINT32 Op
+  )
+{
+  UINT8 UdfByte = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + MVPP2_PRS_SRAM_UDF_BITS);
+  UINT8 UdfByteOffset = (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8));
+  UINT8 OpSelUdfByte = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + MVPP2_PRS_SRAM_OP_SEL_UDF_BITS);
+  UINT8 OpSelUdfByteOffset = (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8));
+
+  /* Set sign */
+  if (Offset < 0) {
+    Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
+    Offset = -Offset;
+  } else {
+    Mvpp2PrsSramBitsClear (Pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
+  }
+
+  /* Set value */
+  Mvpp2PrsSramBitsClear (Pe, MVPP2_PRS_SRAM_UDF_OFFS, MVPP2_PRS_SRAM_UDF_MASK);
+  Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_UDF_OFFS, Offset);
+
+  Pe->Sram.Byte[UdfByte] &= ~(MVPP2_PRS_SRAM_UDF_MASK >> UdfByteOffset);
+  Pe->Sram.Byte[UdfByte] |= (Offset >> UdfByteOffset);
+
+  /* Set Offset Type */
+  Mvpp2PrsSramBitsClear (Pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, MVPP2_PRS_SRAM_UDF_TYPE_MASK);
+  Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, Type);
+
+  /* Set Offset operation */
+  Mvpp2PrsSramBitsClear (Pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
+  Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, Op);
+
+  Pe->Sram.Byte[OpSelUdfByte] &= ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >> OpSelUdfByteOffset);
+  Pe->Sram.Byte[OpSelUdfByte] |= (Op >> OpSelUdfByteOffset);
+
+  /* Set base Offset as current */
+  Mvpp2PrsSramBitsClear (Pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
+}
+
+/* Find parser Flow entry */
+STATIC
+MVPP2_PRS_ENTRY *
+Mvpp2PrsFlowFind (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Flow
+  )
+{
+  MVPP2_PRS_ENTRY *Pe;
+  INT32 Tid;
+  UINT32 Word, Enable;
+
+  Pe = Mvpp2Alloc (sizeof (*Pe));
+  if (Pe == NULL) {
+    return NULL;
+  }
+
+  Mvpp2PrsTcamLuSet (Pe, MVPP2_PRS_LU_FLOWS);
+
+  /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
+  for (Tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; Tid >= 0; Tid--) {
+    UINT8 Bits;
+
+    if (!Priv->PrsShadow[Tid].Valid || Priv->PrsShadow[Tid].Lu != MVPP2_PRS_LU_FLOWS) {
+      continue;
+    }
+
+    Pe->Index = Tid;
+    Mvpp2PrsHwRead (Priv, Pe);
+
+    /*
+     * Check result info, because there maybe
+     * several TCAM lines to generate the same Flow
+     */
+    Mvpp2PrsTcamDataWordGet (Pe, 0, &Word, &Enable);
+    if ((Word != 0) || (Enable != 0)) {
+      continue;
+    }
+
+    Bits = Mvpp2PrsSramAiGet (Pe);
+
+    /* Sram store classification lookup ID in AI Bits [5:0] */
+    if ((Bits & MVPP2_PRS_FLOW_ID_MASK) == Flow) {
+      return Pe;
+    }
+  }
+
+  Mvpp2Free (Pe);
+
+  return NULL;
+}
+
+/* Return first free Tcam Index, seeking from start to end */
+STATIC
+INT32
+Mvpp2PrsTcamFirstFree (
+  IN MVPP2_SHARED *Priv,
+  IN UINT8 Start,
+  IN UINT8 End
+  )
+{
+  INT32 Tid;
+
+  if (Start > End) {
+    Mvpp2SwapVariables (Start, End);
+  }
+
+  if (End >= MVPP2_PRS_TCAM_SRAM_SIZE) {
+    End = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
+  }
+
+  for (Tid = Start; Tid <= End; Tid++) {
+    if (!Priv->PrsShadow[Tid].Valid) {
+      return Tid;
+    }
+  }
+
+  return MVPP2_EINVAL;
+}
+
+/* Enable/disable dropping all mac Da's */
+STATIC
+VOID
+Mvpp2PrsMacDropAllSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN BOOLEAN Add
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+
+  if (Priv->PrsShadow[MVPP2_PE_DROP_ALL].Valid) {
+    /* Entry exist - update PortId only */
+    Pe.Index = MVPP2_PE_DROP_ALL;
+    Mvpp2PrsHwRead (Priv, &Pe);
+  } else {
+    /* Entry doesn't exist - create new */
+    Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+    Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_MAC);
+    Pe.Index = MVPP2_PE_DROP_ALL;
+
+    /* Non-promiscuous mode for all Ports - DROP unknown packets */
+    Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_DROP_MASK, MVPP2_PRS_RI_DROP_MASK);
+
+    Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+    Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+
+    /* Update shadow table */
+    Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_MAC);
+
+    /* Mask all Ports */
+    Mvpp2PrsTcamPortMapSet (&Pe, 0);
+  }
+
+  /* Update PortId Mask */
+  Mvpp2PrsTcamPortSet (&Pe, PortId, Add);
+
+  Mvpp2PrsHwWrite (Priv, &Pe);
+}
+
+/* Set port to promiscuous mode */
+VOID
+Mvpp2PrsMacPromiscSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN BOOLEAN Add
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+
+  /* Promiscuous mode - Accept unknown packets */
+
+  if (Priv->PrsShadow[MVPP2_PE_MAC_PROMISCUOUS].Valid) {
+    /* Entry exist - update port only */
+    Pe.Index = MVPP2_PE_MAC_PROMISCUOUS;
+    Mvpp2PrsHwRead (Priv, &Pe);
+  } else {
+    /* Entry doesn't exist - create new */
+    Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+    Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_MAC);
+    Pe.Index = MVPP2_PE_MAC_PROMISCUOUS;
+
+    /* Continue - set next lookup */
+    Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_DSA);
+
+    /* Set result info bits */
+    Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_CAST_MASK);
+
+    /* Shift to ethertype with 2 of MAC Address length */
+    Mvpp2PrsSramShiftSet (&Pe, 2 * MV_ETH_ALEN, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+    /* Mask all Ports */
+    Mvpp2PrsTcamPortMapSet (&Pe, 0);
+
+    /* Update shadow table */
+    Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_MAC);
+  }
+
+  /* Update port Mask */
+  Mvpp2PrsTcamPortSet (&Pe, PortId, Add);
+
+  Mvpp2PrsHwWrite (Priv, &Pe);
+}
+
+/* Accept multicast */
+VOID
+Mvpp2PrsMacMultiSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN INT32 Index,
+  IN BOOLEAN Add
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  UINT8 DaMc;
+
+  /*
+   * Ethernet multicast Address first Byte is
+   * 0x01 for IPv4 and 0x33 for IPv6
+   */
+  DaMc = (Index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
+
+  if (Priv->PrsShadow[Index].Valid) {
+    /* Entry exist - update port only */
+    Pe.Index = Index;
+    Mvpp2PrsHwRead (Priv, &Pe);
+  } else {
+    /* Entry doesn't exist - create new */
+    Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+    Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_MAC);
+    Pe.Index = Index;
+
+    /* Continue - set next lookup */
+    Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_DSA);
+
+    /* Set result info bits */
+    Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L2_MCAST, MVPP2_PRS_RI_L2_CAST_MASK);
+
+    /* Update Tcam entry data first Byte */
+    Mvpp2PrsTcamDataByteSet (&Pe, 0, DaMc, 0xff);
+
+    /* Shift to ethertype */
+    Mvpp2PrsSramShiftSet (&Pe, 2 * MV_ETH_ALEN, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+    /* Mask all ports */
+    Mvpp2PrsTcamPortMapSet (&Pe, 0);
+
+    /* Update shadow table */
+    Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_MAC);
+  }
+
+  /* Update port Mask */
+  Mvpp2PrsTcamPortSet (&Pe, PortId, Add);
+
+  Mvpp2PrsHwWrite (Priv, &Pe);
+}
+
+/* Set entry for dsa packets */
+STATIC
+VOID
+Mvpp2PrsDsaTagSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN BOOLEAN Add,
+  IN BOOLEAN Tagged,
+  IN BOOLEAN Extend
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Tid, Shift;
+
+  if (Extend) {
+    Tid = Tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED;
+    Shift = 8;
+  } else {
+    Tid = Tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED;
+    Shift = 4;
+  }
+
+  if (Priv->PrsShadow[Tid].Valid) {
+    /* Entry exist - update port only */
+    Pe.Index = Tid;
+    Mvpp2PrsHwRead (Priv, &Pe);
+  } else {
+    /* Entry doesn't exist - create new */
+    Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+    Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_DSA);
+    Pe.Index = Tid;
+
+    /* Shift 4 bytes if DSA tag or 8 bytes in case of EDSA tag*/
+    Mvpp2PrsSramShiftSet (&Pe, Shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+    /* Update shadow table */
+    Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_DSA);
+
+    if (Tagged) {
+      /* Set Tagged bit in DSA tag */
+      Mvpp2PrsTcamDataByteSet (&Pe, 0, MVPP2_PRS_TCAM_DSA_TAGGED_BIT, MVPP2_PRS_TCAM_DSA_TAGGED_BIT);
+
+      /* Clear all ai bits for next iteration */
+      Mvpp2PrsSramAiUpdate (&Pe, 0, MVPP2_PRS_SRAM_AI_MASK);
+
+      /* If packet is Tagged continue check vlans */
+      Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_VLAN);
+    } else {
+      /* Set result info bits to 'no vlans' */
+      Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_VLAN_NONE, MVPP2_PRS_RI_VLAN_MASK);
+      Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_L2);
+    }
+
+    /* Mask all Ports */
+    Mvpp2PrsTcamPortMapSet (&Pe, 0);
+  }
+
+  /* Update port Mask */
+  Mvpp2PrsTcamPortSet (&Pe, PortId, Add);
+
+  Mvpp2PrsHwWrite (Priv, &Pe);
+}
+
+/* Set entry for dsa ethertype */
+STATIC
+VOID
+Mvpp2PrsDsaTagEthertypeSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN BOOLEAN Add,
+  IN BOOLEAN Tagged,
+  IN BOOLEAN Extend
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Tid, Shift, PortMask;
+
+  if (Extend) {
+    Tid = Tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED : MVPP2_PE_ETYPE_EDSA_UNTAGGED;
+    PortMask = 0;
+    Shift = 8;
+  } else {
+    Tid = Tagged ? MVPP2_PE_ETYPE_DSA_TAGGED : MVPP2_PE_ETYPE_DSA_UNTAGGED;
+    PortMask = MVPP2_PRS_PORT_MASK;
+    Shift = 4;
+  }
+
+  if (Priv->PrsShadow[Tid].Valid) {
+    /* Entry exist - update PortId only */
+    Pe.Index = Tid;
+    Mvpp2PrsHwRead (Priv, &Pe);
+  } else {
+    /* Entry doesn't exist - create new */
+    Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+    Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_DSA);
+    Pe.Index = Tid;
+
+    /*
+     * Set ethertype at offset 0 for DSA and
+     * clear it at offset 2 - obtained from Marvell.
+     */
+    Mvpp2PrsMatchEtype (&Pe, 0, MV_ETH_P_EDSA);
+    Mvpp2PrsMatchEtype (&Pe, 2, 0);
+
+    Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_DSA_MASK,
+           MVPP2_PRS_RI_DSA_MASK);
+
+    /* Shift ethertype + 2 Byte reserved + tag */
+    Mvpp2PrsSramShiftSet (&Pe, 2 + MVPP2_ETH_TYPE_LEN + Shift,
+           MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+    /* Update shadow table */
+    Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_DSA);
+
+    if (Tagged) {
+      /* Set Tagged bit in DSA tag */
+      Mvpp2PrsTcamDataByteSet (
+                      &Pe,
+                      MVPP2_ETH_TYPE_LEN + 2 + 3,
+                      MVPP2_PRS_TCAM_DSA_TAGGED_BIT,
+                      MVPP2_PRS_TCAM_DSA_TAGGED_BIT
+                    );
+
+      /* Clear all ai bits for next iteration */
+      Mvpp2PrsSramAiUpdate (&Pe, 0, MVPP2_PRS_SRAM_AI_MASK);
+
+      /* If packet is Tagged continue check vlans */
+      Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_VLAN);
+    } else {
+      /* Set result info bits to 'no vlans' */
+      Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_VLAN_NONE, MVPP2_PRS_RI_VLAN_MASK);
+      Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_L2);
+    }
+
+    /* Mask/unmask all ports, depending on dsa type */
+    Mvpp2PrsTcamPortMapSet (&Pe, PortMask);
+  }
+
+  /* Update port Mask */
+  Mvpp2PrsTcamPortSet (&Pe, PortId, Add);
+
+  Mvpp2PrsHwWrite (Priv, &Pe);
+}
+
+/* Search for existing single/triple vlan entry */
+STATIC
+MVPP2_PRS_ENTRY *
+Mvpp2PrsVlanFind (
+  IN MVPP2_SHARED *Priv,
+  IN UINT16 Tpid,
+  IN INT32 Ai
+  )
+{
+  MVPP2_PRS_ENTRY *Pe;
+  INT32 Tid;
+
+  Pe = Mvpp2Alloc (sizeof (*Pe));
+  if (Pe == NULL) {
+    return NULL;
+  }
+
+  Mvpp2PrsTcamLuSet (Pe, MVPP2_PRS_LU_VLAN);
+
+  /* Go through the all entries with MVPP2_PRS_LU_VLAN */
+  for (Tid = MVPP2_PE_FIRST_FREE_TID; Tid <= MVPP2_PE_LAST_FREE_TID; Tid++) {
+    UINT32 RiBits, AiBits;
+    BOOLEAN match;
+
+    if (!Priv->PrsShadow[Tid].Valid || Priv->PrsShadow[Tid].Lu != MVPP2_PRS_LU_VLAN) {
+      continue;
+    }
+
+    Pe->Index = Tid;
+
+    Mvpp2PrsHwRead (Priv, Pe);
+    match = Mvpp2PrsTcamDataCmp (Pe, 0, Mvpp2SwapBytes16 (Tpid));
+    if (!match) {
+      continue;
+    }
+
+    /* Get vlan type */
+    RiBits = Mvpp2PrsSramRiGet (Pe);
+    RiBits &= MVPP2_PRS_RI_VLAN_MASK;
+
+    /* Get current Ai value from Tcam */
+    AiBits = Mvpp2PrsTcamAiGet (Pe);
+
+    /* Clear double vlan bit */
+    AiBits &= ~MVPP2_PRS_DBL_VLAN_AI_BIT;
+
+    if (Ai != AiBits) {
+      continue;
+    }
+
+    if (RiBits == MVPP2_PRS_RI_VLAN_SINGLE || RiBits == MVPP2_PRS_RI_VLAN_TRIPLE) {
+      return Pe;
+    }
+  }
+
+  Mvpp2Free (Pe);
+
+  return NULL;
+}
+
+/* Add/update single/triple vlan entry */
+INT32
+Mvpp2PrsVlanAdd (
+  IN MVPP2_SHARED *Priv,
+  IN UINT16 Tpid,
+  IN INT32 Ai,
+  IN UINT32 PortMap
+  )
+{
+  MVPP2_PRS_ENTRY *Pe;
+  INT32 TidAux, Tid;
+  INT32 Ret = 0;
+
+  Pe = Mvpp2PrsVlanFind (Priv, Tpid, Ai);
+
+  if (!Pe) {
+    /* Create new Tcam entry */
+    Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_LAST_FREE_TID, MVPP2_PE_FIRST_FREE_TID);
+    if (Tid < 0) {
+      return Tid;
+    }
+
+    Pe = Mvpp2Alloc (sizeof (*Pe));
+    if (Pe == NULL) {
+      return MVPP2_ENOMEM;
+    }
+
+    /* Get last double vlan Tid */
+    for (TidAux = MVPP2_PE_LAST_FREE_TID; TidAux >= MVPP2_PE_FIRST_FREE_TID; TidAux--) {
+      UINT32 RiBits;
+
+      if (!Priv->PrsShadow[TidAux].Valid || Priv->PrsShadow[TidAux].Lu != MVPP2_PRS_LU_VLAN) {
+        continue;
+      }
+
+      Pe->Index = TidAux;
+      Mvpp2PrsHwRead (Priv, Pe);
+      RiBits = Mvpp2PrsSramRiGet (Pe);
+      if ((RiBits & MVPP2_PRS_RI_VLAN_MASK) == MVPP2_PRS_RI_VLAN_DOUBLE) {
+        break;
+      }
+    }
+
+    if (Tid <= TidAux) {
+      Ret = MVPP2_EINVAL;
+      goto error;
+    }
+
+    Mvpp2Memset (Pe, 0 , sizeof (MVPP2_PRS_ENTRY));
+    Mvpp2PrsTcamLuSet (Pe, MVPP2_PRS_LU_VLAN);
+    Pe->Index = Tid;
+
+    /* Set VLAN type's offset to 0 bytes - obtained from Marvell */
+    Mvpp2PrsMatchEtype (Pe, 0, Tpid);
+
+    Mvpp2PrsSramNextLuSet (Pe, MVPP2_PRS_LU_L2);
+
+    /* Shift 4 bytes - skip 1 vlan tag */
+    Mvpp2PrsSramShiftSet (Pe, MVPP2_VLAN_TAG_LEN,
+           MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+    /* Clear all Ai bits for next iteration */
+    Mvpp2PrsSramAiUpdate (Pe, 0, MVPP2_PRS_SRAM_AI_MASK);
+
+    if (Ai == MVPP2_PRS_SINGLE_VLAN_AI) {
+      Mvpp2PrsSramRiUpdate (Pe, MVPP2_PRS_RI_VLAN_SINGLE, MVPP2_PRS_RI_VLAN_MASK);
+    } else {
+      Ai |= MVPP2_PRS_DBL_VLAN_AI_BIT;
+      Mvpp2PrsSramRiUpdate (Pe, MVPP2_PRS_RI_VLAN_TRIPLE, MVPP2_PRS_RI_VLAN_MASK);
+    }
+
+    Mvpp2PrsTcamAiUpdate (Pe, Ai, MVPP2_PRS_SRAM_AI_MASK);
+
+    Mvpp2PrsShadowSet (Priv, Pe->Index, MVPP2_PRS_LU_VLAN);
+  }
+
+  /* Update Ports' Mask */
+  Mvpp2PrsTcamPortMapSet (Pe, PortMap);
+  Mvpp2PrsHwWrite (Priv, Pe);
+
+error:
+  Mvpp2Free (Pe);
+
+  return Ret;
+}
+
+/* Get first free double vlan ai number */
+INT32
+Mvpp2PrsDoubleVlanAiFreeGet (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  INT32 i;
+
+  for (i = 1; i < MVPP2_PRS_DBL_VLANS_MAX; i++) {
+    if (!Priv->PrsDoubleVlans[i]) {
+      return i;
+    }
+  }
+
+  return MVPP2_EINVAL;
+}
+
+/* Search for existing double vlan entry */
+MVPP2_PRS_ENTRY *Mvpp2PrsDoubleVlanFind (
+  IN MVPP2_SHARED *Priv,
+  IN UINT16 Tpid1,
+  IN UINT16 Tpid2
+  )
+{
+  MVPP2_PRS_ENTRY *Pe;
+  INT32 Tid;
+
+  Pe = Mvpp2Alloc (sizeof (*Pe));
+  if (Pe == NULL) {
+    return NULL;
+  }
+
+  Mvpp2PrsTcamLuSet (Pe, MVPP2_PRS_LU_VLAN);
+
+  /* Go through the all entries with MVPP2_PRS_LU_VLAN */
+  for (Tid = MVPP2_PE_FIRST_FREE_TID; Tid <= MVPP2_PE_LAST_FREE_TID; Tid++) {
+    UINT32 RiMask;
+    BOOLEAN match;
+
+    if (!Priv->PrsShadow[Tid].Valid || Priv->PrsShadow[Tid].Lu != MVPP2_PRS_LU_VLAN) {
+      continue;
+    }
+
+    Pe->Index = Tid;
+    Mvpp2PrsHwRead (Priv, Pe);
+
+    match = Mvpp2PrsTcamDataCmp (Pe, 0, Mvpp2SwapBytes16 (Tpid1)) &&
+            Mvpp2PrsTcamDataCmp (Pe, 4, Mvpp2SwapBytes16 (Tpid2));
+
+    if (!match) {
+      continue;
+    }
+
+    RiMask = Mvpp2PrsSramRiGet (Pe) & MVPP2_PRS_RI_VLAN_MASK;
+    if (RiMask == MVPP2_PRS_RI_VLAN_DOUBLE) {
+      return Pe;
+    }
+  }
+
+  Mvpp2Free (Pe);
+
+  return NULL;
+}
+
+/* Add or update double vlan entry */
+INT32
+Mvpp2PrsDoubleVlanAdd (
+  IN MVPP2_SHARED *Priv,
+  IN UINT16 Tpid1,
+  IN UINT16 Tpid2,
+  IN UINT32 PortMap
+  )
+{
+  MVPP2_PRS_ENTRY *Pe;
+  INT32 TidAux, Tid, Ai, Ret = 0;
+
+  Pe = Mvpp2PrsDoubleVlanFind (Priv, Tpid1, Tpid2);
+
+  if (!Pe) {
+    /* Create new Tcam entry */
+    Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+    if (Tid < 0) {
+      return Tid;
+    }
+
+    Pe = Mvpp2Alloc (sizeof (*Pe));
+    if (Pe == NULL) {
+      return MVPP2_ENOMEM;
+    }
+
+    /* Set Ai value for new double vlan entry */
+    Ai = Mvpp2PrsDoubleVlanAiFreeGet (Priv);
+    if (Ai < 0) {
+      Ret = Ai;
+      goto error;
+    }
+
+    /* Get first single/triple vlan Tid */
+    for (TidAux = MVPP2_PE_FIRST_FREE_TID; TidAux <= MVPP2_PE_LAST_FREE_TID; TidAux++) {
+      UINT32 RiBits;
+
+      if (!Priv->PrsShadow[TidAux].Valid || Priv->PrsShadow[TidAux].Lu != MVPP2_PRS_LU_VLAN) {
+        continue;
+      }
+
+      Pe->Index = TidAux;
+      Mvpp2PrsHwRead (Priv, Pe);
+      RiBits = Mvpp2PrsSramRiGet (Pe);
+      RiBits &= MVPP2_PRS_RI_VLAN_MASK;
+
+      if (RiBits == MVPP2_PRS_RI_VLAN_SINGLE || RiBits == MVPP2_PRS_RI_VLAN_TRIPLE) {
+        break;
+      }
+    }
+
+    if (Tid >= TidAux) {
+      Ret = MVPP2_ERANGE;
+      goto error;
+    }
+
+    Mvpp2Memset (Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+    Mvpp2PrsTcamLuSet (Pe, MVPP2_PRS_LU_VLAN);
+    Pe->Index = Tid;
+
+    Priv->PrsDoubleVlans[Ai] = TRUE;
+
+    /* Set both VLAN types' offsets to 0 and 4 bytes - obtained from Marvell */
+    Mvpp2PrsMatchEtype (Pe, 0, Tpid1);
+    Mvpp2PrsMatchEtype (Pe, 4, Tpid2);
+
+    Mvpp2PrsSramNextLuSet (Pe, MVPP2_PRS_LU_VLAN);
+
+    /* Shift 8 bytes - skip 2 vlan tags */
+    Mvpp2PrsSramShiftSet (Pe, 2 * MVPP2_VLAN_TAG_LEN, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+    Mvpp2PrsSramRiUpdate (Pe, MVPP2_PRS_RI_VLAN_DOUBLE, MVPP2_PRS_RI_VLAN_MASK);
+    Mvpp2PrsSramAiUpdate (Pe, Ai | MVPP2_PRS_DBL_VLAN_AI_BIT, MVPP2_PRS_SRAM_AI_MASK);
+
+    Mvpp2PrsShadowSet (Priv, Pe->Index, MVPP2_PRS_LU_VLAN);
+  }
+
+  /* Update Ports' Mask */
+  Mvpp2PrsTcamPortMapSet (Pe, PortMap);
+  Mvpp2PrsHwWrite (Priv, Pe);
+
+error:
+  Mvpp2Free (Pe);
+  return Ret;
+}
+
+/* IPv4 header parsing for fragmentation and L4 Offset */
+STATIC
+INT32
+Mvpp2PrsIp4Proto (
+  IN MVPP2_SHARED *Priv,
+  IN UINT16 Proto,
+  IN UINT32 Ri,
+  IN UINT32 RiMask
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Tid;
+
+  if ((Proto != MV_IPPR_TCP) && (Proto != MV_IPPR_UDP) && (Proto != MV_IPPR_IGMP)) {
+    return MVPP2_EINVAL;
+  }
+
+  /* Fragmented packet */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP4);
+  Pe.Index = Tid;
+
+  /* Set next Lu to IPv4 - 12 bytes shift */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsSramShiftSet (&Pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+  /* Set L4 offset 4 bytes relative IPv4 header size (current position) */
+  Mvpp2PrsSramOffsetSet (
+                  &Pe,
+                  MVPP2_PRS_SRAM_UDF_TYPE_L4,
+                  sizeof (Mvpp2Iphdr) - 4,
+                  MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
+                );
+
+  Mvpp2PrsSramAiUpdate (&Pe, MVPP2_PRS_IPV4_DIP_AI_BIT, MVPP2_PRS_IPV4_DIP_AI_BIT);
+  Mvpp2PrsSramRiUpdate (&Pe, Ri | MVPP2_PRS_RI_IP_FRAG_MASK, RiMask | MVPP2_PRS_RI_IP_FRAG_MASK);
+
+  Mvpp2PrsTcamDataByteSet (&Pe, 5, Proto, MVPP2_PRS_TCAM_PROTO_MASK);
+  Mvpp2PrsTcamAiUpdate (&Pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Not fragmented packet */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Pe.Index = Tid;
+
+  /* Clear Ri before updating */
+  Pe.Sram.Word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
+  Pe.Sram.Word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
+  Mvpp2PrsSramRiUpdate (&Pe, Ri, RiMask);
+
+  Mvpp2PrsTcamDataByteSet (&Pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L);
+  Mvpp2PrsTcamDataByteSet (&Pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/* IPv4 L3 multicast or broadcast */
+STATIC
+INT32
+Mvpp2PrsIp4Cast (
+  IN MVPP2_SHARED *Priv,
+  IN UINT16 L3Cast
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Mask, Tid;
+
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP4);
+  Pe.Index = Tid;
+
+  switch (L3Cast) {
+  case MVPP2_PRS_L3_MULTI_CAST:
+    Mvpp2PrsTcamDataByteSet (&Pe, 0, MVPP2_PRS_IPV4_MC, MVPP2_PRS_IPV4_MC_MASK);
+    Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_MCAST, MVPP2_PRS_RI_L3_ADDR_MASK);
+    break;
+  case  MVPP2_PRS_L3_BROAD_CAST:
+    Mask = MVPP2_PRS_IPV4_BC_MASK;
+    Mvpp2PrsTcamDataByteSet (&Pe, 0, Mask, Mask);
+    Mvpp2PrsTcamDataByteSet (&Pe, 1, Mask, Mask);
+    Mvpp2PrsTcamDataByteSet (&Pe, 2, Mask, Mask);
+    Mvpp2PrsTcamDataByteSet (&Pe, 3, Mask, Mask);
+    Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_BCAST, MVPP2_PRS_RI_L3_ADDR_MASK);
+    break;
+  default:
+    return MVPP2_EINVAL;
+  }
+
+  /* Finished: go to Flowid generation */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+
+  Mvpp2PrsTcamAiUpdate (&Pe, MVPP2_PRS_IPV4_DIP_AI_BIT, MVPP2_PRS_IPV4_DIP_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/* Set entries for protocols over IPv6  */
+STATIC
+INT32
+Mvpp2PrsIp6Proto (
+  IN MVPP2_SHARED *Priv,
+  IN UINT16 Proto,
+  IN UINT32 Ri,
+  IN UINT32 RiMask
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Tid;
+
+  if ((Proto != MV_IPPR_TCP) && (Proto != MV_IPPR_UDP) &&
+      (Proto != MV_IPPR_ICMPV6) && (Proto != MV_IPPR_IPIP))
+  {
+    return MVPP2_EINVAL;
+  }
+
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Pe.Index = Tid;
+
+  /* Finished: go to Flowid generation */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramRiUpdate (&Pe, Ri, RiMask);
+
+  /* Set offset for protocol 6 bytes relative to IPv6 header size */
+  Mvpp2PrsSramOffsetSet (
+                  &Pe,
+                  MVPP2_PRS_SRAM_UDF_TYPE_L4,
+                  sizeof (Mvpp2Ipv6hdr) - 6,
+                  MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
+                );
+
+  Mvpp2PrsTcamDataByteSet (&Pe, 0, Proto, MVPP2_PRS_TCAM_PROTO_MASK);
+  Mvpp2PrsTcamAiUpdate (&Pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Write HW */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP6);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/* IPv6 L3 multicast entry */
+STATIC
+INT32
+Mvpp2PrsIp6Cast (
+  IN MVPP2_SHARED *Priv,
+  IN UINT16 L3Cast
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Tid;
+
+  if (L3Cast != MVPP2_PRS_L3_MULTI_CAST) {
+    return MVPP2_EINVAL;
+  }
+
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Pe.Index = Tid;
+
+  /* Finished: go to Flowid generation */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_MCAST, MVPP2_PRS_RI_L3_ADDR_MASK);
+  Mvpp2PrsSramAiUpdate (&Pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
+
+  /* Shift back to IPv6 by 18 bytes - byte count provided by Marvell */
+  Mvpp2PrsSramShiftSet (&Pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+  Mvpp2PrsTcamDataByteSet (&Pe, 0, MVPP2_PRS_IPV6_MC, MVPP2_PRS_IPV6_MC_MASK);
+  Mvpp2PrsTcamAiUpdate (&Pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP6);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/* Parser per-Port initialization */
+STATIC
+VOID
+Mvpp2PrsHwPortInit (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN INT32 LuFirst,
+  IN INT32 LuMax,
+  IN INT32 Offset
+  )
+{
+  UINT32 Val;
+
+  /* Set lookup ID */
+  Val = Mvpp2Read (Priv, MVPP2_PRS_INIT_LOOKUP_REG);
+  Val &= ~MVPP2_PRS_PORT_LU_MASK (PortId);
+  Val |=  MVPP2_PRS_PORT_LU_VAL (PortId, LuFirst);
+  Mvpp2Write (Priv, MVPP2_PRS_INIT_LOOKUP_REG, Val);
+
+  /* Set maximum number of loops for packet received from PortId */
+  Val = Mvpp2Read (Priv, MVPP2_PRS_MAX_LOOP_REG(PortId));
+  Val &= ~MVPP2_PRS_MAX_LOOP_MASK (PortId);
+  Val |= MVPP2_PRS_MAX_LOOP_VAL (PortId, LuMax);
+  Mvpp2Write (Priv, MVPP2_PRS_MAX_LOOP_REG(PortId), Val);
+
+  /*
+   * Set initial Offset for packet header extraction for the first
+   * searching loop
+   */
+  Val = Mvpp2Read (Priv, MVPP2_PRS_INIT_OFFS_REG(PortId));
+  Val &= ~MVPP2_PRS_INIT_OFF_MASK (PortId);
+  Val |= MVPP2_PRS_INIT_OFF_VAL (PortId, Offset);
+  Mvpp2Write (Priv, MVPP2_PRS_INIT_OFFS_REG(PortId), Val);
+}
+
+/* Default Flow entries initialization for all Ports */
+STATIC
+VOID
+Mvpp2PrsDefFlowInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 PortId;
+
+  for (PortId = 0; PortId < MVPP2_MAX_PORTS; PortId++) {
+    Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+    Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+    Pe.Index = MVPP2_PE_FIRST_DEFAULT_FLOW - PortId;
+
+    /* Mask all Ports */
+    Mvpp2PrsTcamPortMapSet (&Pe, 0);
+
+    /* Set Flow ID*/
+    Mvpp2PrsSramAiUpdate (&Pe, PortId, MVPP2_PRS_FLOW_ID_MASK);
+    Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
+
+    /* Update shadow table and hw entry */
+    Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_FLOWS);
+    Mvpp2PrsHwWrite (Priv, &Pe);
+  }
+}
+
+/* Set default entry for Marvell Header field */
+STATIC
+VOID
+Mvpp2PrsMhInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+
+  Pe.Index = MVPP2_PE_MH_DEFAULT;
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_MH);
+  Mvpp2PrsSramShiftSet (&Pe, MVPP2_MH_SIZE, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_MAC);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_MH);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+}
+
+/*
+ * Set default entires (place holder) for promiscuous, non-promiscuous and
+ * multicast MAC Addresses
+ */
+STATIC
+VOID
+Mvpp2PrsMacInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+
+  /* Non-promiscuous mode for all Ports - DROP unknown packets */
+  Pe.Index = MVPP2_PE_MAC_NON_PROMISCUOUS;
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_MAC);
+
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_DROP_MASK, MVPP2_PRS_RI_DROP_MASK);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_MAC);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Place holders only - no Ports */
+  Mvpp2PrsMacDropAllSet (Priv, 0, FALSE);
+  Mvpp2PrsMacPromiscSet (Priv, 0, FALSE);
+  Mvpp2PrsMacMultiSet (Priv, MVPP2_PE_MAC_MC_ALL, 0, FALSE);
+  Mvpp2PrsMacMultiSet (Priv, MVPP2_PE_MAC_MC_IP6, 0, FALSE);
+}
+
+/* Set default entries for various types of dsa packets */
+STATIC
+VOID
+Mvpp2PrsDsaInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+
+  /* None tagged EDSA entry - place holder */
+  Mvpp2PrsDsaTagSet (Priv, 0, FALSE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
+
+  /* Tagged EDSA entry - place holder */
+  Mvpp2PrsDsaTagSet (Priv, 0, FALSE, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
+
+  /* None tagged DSA entry - place holder */
+  Mvpp2PrsDsaTagSet (Priv, 0, FALSE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
+
+  /* Tagged DSA entry - place holder */
+  Mvpp2PrsDsaTagSet (Priv, 0, FALSE, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
+
+  /* None tagged EDSA ethertype entry - place holder*/
+  Mvpp2PrsDsaTagEthertypeSet (Priv, 0, FALSE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
+
+  /* Tagged EDSA ethertype entry - place holder*/
+  Mvpp2PrsDsaTagEthertypeSet (Priv, 0, FALSE, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
+
+  /* None tagged DSA ethertype entry */
+  Mvpp2PrsDsaTagEthertypeSet (Priv, 0, TRUE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
+
+  /* Tagged DSA ethertype entry */
+  Mvpp2PrsDsaTagEthertypeSet (Priv, 0, TRUE, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
+
+  /* Set default entry, in case DSA or EDSA tag not found */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_DSA);
+  Pe.Index = MVPP2_PE_DSA_DEFAULT;
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_VLAN);
+
+  /* Shift 0 bytes */
+  Mvpp2PrsSramShiftSet (&Pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_MAC);
+
+  /* Clear all Sram ai bits for next iteration */
+  Mvpp2PrsSramAiUpdate (&Pe, 0, MVPP2_PRS_SRAM_AI_MASK);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  Mvpp2PrsHwWrite (Priv, &Pe);
+}
+
+/* Match basic ethertypes */
+STATIC
+INT32
+Mvpp2PrsEtypeInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Tid;
+
+  /* Ethertype: PPPoE */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_L2);
+  Pe.Index = Tid;
+
+  /* Set PPPoE type offset to 0 - obtained from Marvell */
+  Mvpp2PrsMatchEtype (&Pe, 0, MV_ETH_P_PPP_SES);
+
+  Mvpp2PrsSramShiftSet (&Pe, MVPP2_PPPOE_HDR_SIZE, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_PPPOE);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_PPPOE_MASK, MVPP2_PRS_RI_PPPOE_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_L2);
+  Priv->PrsShadow[Pe.Index].Udf = MVPP2_PRS_UDF_L2_DEF;
+  Priv->PrsShadow[Pe.Index].Finish = FALSE;
+  Mvpp2PrsShadowRiSet (Priv, Pe.Index, MVPP2_PRS_RI_PPPOE_MASK, MVPP2_PRS_RI_PPPOE_MASK);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Ethertype: ARP */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_L2);
+  Pe.Index = Tid;
+
+  /* Set ARP type offset to 0 - obtained from Marvell */
+  Mvpp2PrsMatchEtype (&Pe, 0, MV_ETH_P_ARP);
+
+  /* Generate Flow in the next iteration*/
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_ARP, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Set L3 Offset */
+  Mvpp2PrsSramOffsetSet (&Pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_L2);
+  Priv->PrsShadow[Pe.Index].Udf = MVPP2_PRS_UDF_L2_DEF;
+  Priv->PrsShadow[Pe.Index].Finish = TRUE;
+  Mvpp2PrsShadowRiSet (Priv, Pe.Index, MVPP2_PRS_RI_L3_ARP, MVPP2_PRS_RI_L3_PROTO_MASK);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Ethertype: LBTD */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_L2);
+  Pe.Index = Tid;
+
+  /* Set LBTD type offset to 0 - obtained from Marvell */
+  Mvpp2PrsMatchEtype (&Pe, 0, MVPP2_IP_LBDT_TYPE);
+
+  /* Generate Flow in the next iteration*/
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramRiUpdate (
+                  &Pe,
+                  MVPP2_PRS_RI_CPU_CODE_RX_SPEC | MVPP2_PRS_RI_UDF3_RX_SPECIAL,
+                  MVPP2_PRS_RI_CPU_CODE_MASK | MVPP2_PRS_RI_UDF3_MASK
+                );
+
+  /* Set L3 Offset */
+  Mvpp2PrsSramOffsetSet (&Pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_L2);
+  Priv->PrsShadow[Pe.Index].Udf = MVPP2_PRS_UDF_L2_DEF;
+  Priv->PrsShadow[Pe.Index].Finish = TRUE;
+  Mvpp2PrsShadowRiSet (
+                  Priv,
+                  Pe.Index,
+                  MVPP2_PRS_RI_CPU_CODE_RX_SPEC | MVPP2_PRS_RI_UDF3_RX_SPECIAL,
+                  MVPP2_PRS_RI_CPU_CODE_MASK | MVPP2_PRS_RI_UDF3_MASK
+                );
+
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Ethertype: IPv4 without options */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_L2);
+  Pe.Index = Tid;
+
+  /* Set IPv4 type offset to 0 - obtained from Marvell */
+  Mvpp2PrsMatchEtype (&Pe, 0, MV_ETH_P_IP);
+  Mvpp2PrsTcamDataByteSet (
+                  &Pe,
+                  MVPP2_ETH_TYPE_LEN,
+                  MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
+                  MVPP2_PRS_IPV4_HEAD_MASK | MVPP2_PRS_IPV4_IHL_MASK
+                );
+
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_IP4, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Skip EthType + 4 bytes of IP header */
+  Mvpp2PrsSramShiftSet (&Pe, MVPP2_ETH_TYPE_LEN + 4, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+  /* Set L3 Offset */
+  Mvpp2PrsSramOffsetSet (&Pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_L2);
+  Priv->PrsShadow[Pe.Index].Udf = MVPP2_PRS_UDF_L2_DEF;
+  Priv->PrsShadow[Pe.Index].Finish = FALSE;
+  Mvpp2PrsShadowRiSet (Priv, Pe.Index, MVPP2_PRS_RI_L3_IP4, MVPP2_PRS_RI_L3_PROTO_MASK);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Ethertype: IPv4 with options */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Pe.Index = Tid;
+
+  /* Clear Tcam data before updating */
+  Pe.Tcam.Byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
+  Pe.Tcam.Byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
+
+  Mvpp2PrsTcamDataByteSet (&Pe, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_IPV4_HEAD, MVPP2_PRS_IPV4_HEAD_MASK);
+
+  /* Clear Ri before updating */
+  Pe.Sram.Word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
+  Pe.Sram.Word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_IP4_OPT, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_L2);
+  Priv->PrsShadow[Pe.Index].Udf = MVPP2_PRS_UDF_L2_DEF;
+  Priv->PrsShadow[Pe.Index].Finish = FALSE;
+  Mvpp2PrsShadowRiSet (Priv, Pe.Index, MVPP2_PRS_RI_L3_IP4_OPT, MVPP2_PRS_RI_L3_PROTO_MASK);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Ethertype: IPv6 without options */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_L2);
+  Pe.Index = Tid;
+
+  /* Set IPv6 type offset to 0 - obtained from Marvell */
+  Mvpp2PrsMatchEtype (&Pe, 0, MV_ETH_P_IPV6);
+
+  /* Skip DIP of IPV6 header - value provided by Marvell */
+  Mvpp2PrsSramShiftSet (&Pe, MVPP2_ETH_TYPE_LEN + 8 + MVPP2_MAX_L3_ADDR_SIZE, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_IP6, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Set L3 Offset */
+  Mvpp2PrsSramOffsetSet (&Pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_L2);
+  Priv->PrsShadow[Pe.Index].Udf = MVPP2_PRS_UDF_L2_DEF;
+  Priv->PrsShadow[Pe.Index].Finish = FALSE;
+  Mvpp2PrsShadowRiSet (Priv, Pe.Index, MVPP2_PRS_RI_L3_IP6, MVPP2_PRS_RI_L3_PROTO_MASK);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_L2);
+  Pe.Index = MVPP2_PE_ETH_TYPE_UN;
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Generate Flow in the next iteration*/
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_UN, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Set L3 Offset even it's unknown L3 */
+  Mvpp2PrsSramOffsetSet (&Pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_L2);
+  Priv->PrsShadow[Pe.Index].Udf = MVPP2_PRS_UDF_L2_DEF;
+  Priv->PrsShadow[Pe.Index].Finish = TRUE;
+  Mvpp2PrsShadowRiSet (Priv, Pe.Index, MVPP2_PRS_RI_L3_UN, MVPP2_PRS_RI_L3_PROTO_MASK);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/*
+ * Configure vlan entries and detect up to 2 successive VLAN tags.
+ * Possible options:
+ * 0x8100, 0x88A8
+ * 0x8100, 0x8100
+ * 0x8100, 0x88A8
+ */
+STATIC
+INT32
+Mvpp2PrsVlanInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Err;
+
+  /* Double VLAN: 0x8100, 0x88A8 */
+  Err = Mvpp2PrsDoubleVlanAdd (Priv, MV_ETH_P_8021Q, MV_ETH_P_8021AD, MVPP2_PRS_PORT_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* Double VLAN: 0x8100, 0x8100 */
+  Err = Mvpp2PrsDoubleVlanAdd (Priv, MV_ETH_P_8021Q, MV_ETH_P_8021Q, MVPP2_PRS_PORT_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* Single VLAN: 0x88a8 */
+  Err = Mvpp2PrsVlanAdd (Priv, MV_ETH_P_8021AD, MVPP2_PRS_SINGLE_VLAN_AI, MVPP2_PRS_PORT_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* Single VLAN: 0x8100 */
+  Err = Mvpp2PrsVlanAdd (Priv, MV_ETH_P_8021Q, MVPP2_PRS_SINGLE_VLAN_AI, MVPP2_PRS_PORT_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* Set default double vlan entry */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_VLAN);
+  Pe.Index = MVPP2_PE_VLAN_DBL;
+
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_L2);
+
+  /* Clear ai for next iterations */
+  Mvpp2PrsSramAiUpdate (&Pe, 0, MVPP2_PRS_SRAM_AI_MASK);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_VLAN_DOUBLE, MVPP2_PRS_RI_VLAN_MASK);
+
+  Mvpp2PrsTcamAiUpdate (&Pe, MVPP2_PRS_DBL_VLAN_AI_BIT, MVPP2_PRS_DBL_VLAN_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_VLAN);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Set default vlan none entry */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_VLAN);
+  Pe.Index = MVPP2_PE_VLAN_NONE;
+
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_L2);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_VLAN_NONE, MVPP2_PRS_RI_VLAN_MASK);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_VLAN);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/* Set entries for PPPoE ethertype */
+STATIC
+INT32
+Mvpp2PrsPppoeInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Tid;
+
+  /* IPv4 over PPPoE with options */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_PPPOE);
+  Pe.Index = Tid;
+
+  /* Set IPv4 over PPPoE type offset to 0 - obtained from Marvell */
+  Mvpp2PrsMatchEtype (&Pe, 0, MV_PPP_IP);
+
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_IP4_OPT, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Skip EthType + 4 bytes of IP header */
+  Mvpp2PrsSramShiftSet (&Pe, MVPP2_ETH_TYPE_LEN + 4, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+  /* Set L3 Offset */
+  Mvpp2PrsSramOffsetSet (&Pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_PPPOE);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* IPv4 over PPPoE without options */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Pe.Index = Tid;
+
+  Mvpp2PrsTcamDataByteSet (
+                  &Pe,
+                  MVPP2_ETH_TYPE_LEN,
+                  MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
+                  MVPP2_PRS_IPV4_HEAD_MASK | MVPP2_PRS_IPV4_IHL_MASK
+                );
+
+  /* Clear Ri before updating */
+  Pe.Sram.Word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
+  Pe.Sram.Word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_IP4, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_PPPOE);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* IPv6 over PPPoE */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_PPPOE);
+  Pe.Index = Tid;
+
+  /* Set IPv6 over PPPoE type offset to 0 - obtained from Marvell */
+  Mvpp2PrsMatchEtype (&Pe, 0, MV_PPP_IPV6);
+
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_IP6, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Skip EthType + 4 bytes of IPv6 header */
+  Mvpp2PrsSramShiftSet (&Pe, MVPP2_ETH_TYPE_LEN + 4, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+  /* Set L3 Offset */
+  Mvpp2PrsSramOffsetSet (&Pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_PPPOE);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Non-IP over PPPoE */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_PPPOE);
+  Pe.Index = Tid;
+
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_UN, MVPP2_PRS_RI_L3_PROTO_MASK);
+
+  /* Finished: go to Flowid generation */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+
+  /* Set L3 Offset even if it's unknown L3 */
+  Mvpp2PrsSramOffsetSet (&Pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, MVPP2_ETH_TYPE_LEN, MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_PPPOE);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/* Initialize entries for IPv4 */
+STATIC
+INT32
+Mvpp2PrsIp4Init (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Err;
+
+  /* Set entries for TCP, UDP and IGMP over IPv4 */
+  Err = Mvpp2PrsIp4Proto (Priv, MV_IPPR_TCP, MVPP2_PRS_RI_L4_TCP, MVPP2_PRS_RI_L4_PROTO_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  Err = Mvpp2PrsIp4Proto (Priv, MV_IPPR_UDP, MVPP2_PRS_RI_L4_UDP, MVPP2_PRS_RI_L4_PROTO_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  Err = Mvpp2PrsIp4Proto (
+                  Priv,
+                  MV_IPPR_IGMP,
+                  MVPP2_PRS_RI_CPU_CODE_RX_SPEC | MVPP2_PRS_RI_UDF3_RX_SPECIAL,
+                  MVPP2_PRS_RI_CPU_CODE_MASK | MVPP2_PRS_RI_UDF3_MASK
+                );
+
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* IPv4 Broadcast */
+  Err = Mvpp2PrsIp4Cast (Priv, MVPP2_PRS_L3_BROAD_CAST);
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* IPv4 Multicast */
+  Err = Mvpp2PrsIp4Cast (Priv, MVPP2_PRS_L3_MULTI_CAST);
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* Default IPv4 entry for unknown protocols */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP4);
+  Pe.Index = MVPP2_PE_IP4_PROTO_UN;
+
+  /* Set next Lu to IPv4 and shift by 12 bytes - obtained from Marvell*/
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsSramShiftSet (&Pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+  /* Set L4 offset 4 bytes relative IPv4 header size (current position) */
+  Mvpp2PrsSramOffsetSet (
+                  &Pe,
+                  MVPP2_PRS_SRAM_UDF_TYPE_L4,
+                  sizeof (Mvpp2Iphdr) - 4,
+                  MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
+                );
+
+  Mvpp2PrsSramAiUpdate (&Pe, MVPP2_PRS_IPV4_DIP_AI_BIT, MVPP2_PRS_IPV4_DIP_AI_BIT);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L4_OTHER, MVPP2_PRS_RI_L4_PROTO_MASK);
+
+  Mvpp2PrsTcamAiUpdate (&Pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Default IPv4 entry for unicast Address */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP4);
+  Pe.Index = MVPP2_PE_IP4_ADDR_UN;
+
+  /* Finished: go to Flowid generation */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_UCAST, MVPP2_PRS_RI_L3_ADDR_MASK);
+
+  Mvpp2PrsTcamAiUpdate (&Pe, MVPP2_PRS_IPV4_DIP_AI_BIT, MVPP2_PRS_IPV4_DIP_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/* Initialize entries for IPv6 */
+STATIC
+INT32
+Mvpp2PrsIp6Init (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Tid, Err;
+
+  /* Set entries for TCP, UDP and ICMP over IPv6 */
+  Err = Mvpp2PrsIp6Proto (Priv, MV_IPPR_TCP, MVPP2_PRS_RI_L4_TCP, MVPP2_PRS_RI_L4_PROTO_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  Err = Mvpp2PrsIp6Proto (Priv, MV_IPPR_UDP, MVPP2_PRS_RI_L4_UDP, MVPP2_PRS_RI_L4_PROTO_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  Err = Mvpp2PrsIp6Proto (
+                  Priv,
+                  MV_IPPR_ICMPV6,
+                  MVPP2_PRS_RI_CPU_CODE_RX_SPEC | MVPP2_PRS_RI_UDF3_RX_SPECIAL,
+                  MVPP2_PRS_RI_CPU_CODE_MASK | MVPP2_PRS_RI_UDF3_MASK
+                );
+
+  if (Err != 0) {
+    return Err;
+  }
+
+  /*
+   * IPv4 is the last header. This is similar case as 6-TCP or 17-UDP
+   * Result Info: UDF7=1, DS lite
+   */
+  Err = Mvpp2PrsIp6Proto (Priv, MV_IPPR_IPIP, MVPP2_PRS_RI_UDF7_IP6_LITE, MVPP2_PRS_RI_UDF7_MASK);
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* IPv6 multicast */
+  Err = Mvpp2PrsIp6Cast (Priv, MVPP2_PRS_L3_MULTI_CAST);
+  if (Err != 0) {
+    return Err;
+  }
+
+  /* Entry for checking hop limit */
+  Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, MVPP2_PE_LAST_FREE_TID);
+  if (Tid < 0) {
+    return Tid;
+  }
+
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Pe.Index = Tid;
+
+  /* Finished: go to Flowid generation */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramRiUpdate (
+                  &Pe,
+                  MVPP2_PRS_RI_L3_UN | MVPP2_PRS_RI_DROP_MASK,
+                  MVPP2_PRS_RI_L3_PROTO_MASK | MVPP2_PRS_RI_DROP_MASK
+                );
+
+  Mvpp2PrsTcamDataByteSet (&Pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK);
+  Mvpp2PrsTcamAiUpdate (&Pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Default IPv6 entry for unknown protocols */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Pe.Index = MVPP2_PE_IP6_PROTO_UN;
+
+  /* Finished: go to Flowid generation */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L4_OTHER, MVPP2_PRS_RI_L4_PROTO_MASK);
+
+  /* Set L4 offset 6 bytes relative IPv6 header size (current position) */
+  Mvpp2PrsSramOffsetSet (
+                  &Pe,
+                  MVPP2_PRS_SRAM_UDF_TYPE_L4,
+                  sizeof (Mvpp2Ipv6hdr) - 6,
+                  MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
+                );
+
+  Mvpp2PrsTcamAiUpdate (&Pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Default IPv6 entry for unknown ext protocols */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Pe.Index = MVPP2_PE_IP6_EXT_PROTO_UN;
+
+  /* Finished: go to Flowid generation */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_FLOWS);
+  Mvpp2PrsSramBitsSet (&Pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L4_OTHER, MVPP2_PRS_RI_L4_PROTO_MASK);
+
+  Mvpp2PrsTcamAiUpdate (&Pe, MVPP2_PRS_IPV6_EXT_AI_BIT, MVPP2_PRS_IPV6_EXT_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP4);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  /* Default IPv6 entry for unicast Address */
+  Mvpp2Memset (&Pe, 0, sizeof (MVPP2_PRS_ENTRY));
+  Mvpp2PrsTcamLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Pe.Index = MVPP2_PE_IP6_ADDR_UN;
+
+  /* Finished: go to IPv6 again */
+  Mvpp2PrsSramNextLuSet (&Pe, MVPP2_PRS_LU_IP6);
+  Mvpp2PrsSramRiUpdate (&Pe, MVPP2_PRS_RI_L3_UCAST, MVPP2_PRS_RI_L3_ADDR_MASK);
+  Mvpp2PrsSramAiUpdate (&Pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
+
+  /* Shift back to IPv6 by 18 bytes - byte count provided by Marvell */
+  Mvpp2PrsSramShiftSet (&Pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+  Mvpp2PrsTcamAiUpdate (&Pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
+
+  /* Unmask all Ports */
+  Mvpp2PrsTcamPortMapSet (&Pe, MVPP2_PRS_PORT_MASK);
+
+  /* Update shadow table and hw entry */
+  Mvpp2PrsShadowSet (Priv, Pe.Index, MVPP2_PRS_LU_IP6);
+  Mvpp2PrsHwWrite (Priv, &Pe);
+
+  return 0;
+}
+
+/* Parser default initialization */
+INT32
+Mvpp2PrsDefaultInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  INT32 Err, Index, i;
+
+  /* Enable Tcam table */
+  Mvpp2Write (Priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
+
+  /* Clear all Tcam and Sram entries */
+  for (Index = 0; Index < MVPP2_PRS_TCAM_SRAM_SIZE; Index++) {
+    Mvpp2Write (Priv, MVPP2_PRS_TCAM_IDX_REG, Index);
+    for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) {
+      Mvpp2Write (Priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
+    }
+
+    Mvpp2Write (Priv, MVPP2_PRS_SRAM_IDX_REG, Index);
+    for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) {
+      Mvpp2Write (Priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
+    }
+  }
+
+  /* Invalidate all Tcam entries */
+  for (Index = 0; Index < MVPP2_PRS_TCAM_SRAM_SIZE; Index++) {
+    Mvpp2PrsHwInv (Priv, Index);
+  }
+
+  /* Always start from lookup = 0 */
+  for (Index = 0; Index < MVPP2_MAX_PORTS; Index++) {
+    Mvpp2PrsHwPortInit (Priv, Index, MVPP2_PRS_LU_MH, MVPP2_PRS_PORT_LU_MAX, 0);
+  }
+
+  Mvpp2PrsDefFlowInit (Priv);
+
+  Mvpp2PrsMhInit (Priv);
+
+  Mvpp2PrsMacInit (Priv);
+
+  Mvpp2PrsDsaInit (Priv);
+
+  Err = Mvpp2PrsEtypeInit (Priv);
+  if (Err != 0) {
+    return Err;
+  }
+
+  Err = Mvpp2PrsVlanInit (Priv);
+  if (Err != 0) {
+    return Err;
+  }
+
+  Err = Mvpp2PrsPppoeInit (Priv);
+  if (Err != 0) {
+    return Err;
+  }
+
+  Err = Mvpp2PrsIp6Init (Priv);
+  if (Err != 0) {
+    return Err;
+  }
+
+  Err = Mvpp2PrsIp4Init (Priv);
+  if (Err != 0) {
+    return Err;
+  }
+
+  return 0;
+}
+
+/* Compare MAC DA with Tcam entry data */
+STATIC
+BOOLEAN
+Mvpp2PrsMacRangeEquals (
+  IN MVPP2_PRS_ENTRY *Pe,
+  IN const UINT8 *Da,
+  IN UINT8 *Mask
+  )
+{
+  UINT8 TcamByte, TcamMask;
+  INT32 Index;
+
+  for (Index = 0; Index < MV_ETH_ALEN; Index++) {
+    Mvpp2PrsTcamDataByteGet (Pe, Index, &TcamByte, &TcamMask);
+    if (TcamMask != Mask[Index]) {
+      return FALSE;
+    }
+
+    if ((TcamMask & TcamByte) != (Da[Index] & Mask[Index])) {
+      return FALSE;
+    }
+  }
+
+  return TRUE;
+}
+
+/* Find Tcam entry with matched pair <MAC DA, Port> */
+STATIC
+MVPP2_PRS_ENTRY *
+Mvpp2PrsMacDaRangeFind (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Pmap,
+  IN const UINT8 *Da,
+  IN UINT8 *Mask,
+  IN INT32 UdfType
+  )
+{
+  MVPP2_PRS_ENTRY *Pe;
+  INT32 Tid;
+
+  Pe = Mvpp2Alloc (sizeof (*Pe));
+  if (Pe == NULL) {
+    return NULL;
+  }
+  Mvpp2PrsTcamLuSet (Pe, MVPP2_PRS_LU_MAC);
+
+  /* Go through the all entires with MVPP2_PRS_LU_MAC */
+  for (Tid = MVPP2_PE_FIRST_FREE_TID; Tid <= MVPP2_PE_LAST_FREE_TID; Tid++) {
+    UINT32 EntryPmap;
+
+    if (!Priv->PrsShadow[Tid].Valid ||
+        (Priv->PrsShadow[Tid].Lu != MVPP2_PRS_LU_MAC) ||
+        (Priv->PrsShadow[Tid].Udf != UdfType))
+    {
+      continue;
+    }
+
+    Pe->Index = Tid;
+    Mvpp2PrsHwRead (Priv, Pe);
+    EntryPmap = Mvpp2PrsTcamPortMapGet (Pe);
+
+    if (Mvpp2PrsMacRangeEquals (Pe, Da, Mask) && EntryPmap == Pmap) {
+      return Pe;
+    }
+  }
+
+  Mvpp2Free (Pe);
+
+  return NULL;
+}
+
+/* Update parser's mac Da entry */
+INT32
+Mvpp2PrsMacDaAccept (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN const UINT8 *Da,
+  IN BOOLEAN Add
+  )
+{
+  MVPP2_PRS_ENTRY *Pe;
+  UINT32 Pmap, Len, Ri;
+  UINT8 Mask[MV_ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+  INT32 Tid;
+
+  /* Scan TCAM and see if entry with this <MAC DA, PortId> already exist */
+  Pe = Mvpp2PrsMacDaRangeFind (Priv, (1 << PortId), Da, Mask, MVPP2_PRS_UDF_MAC_DEF);
+
+  /* No such entry */
+  if (Pe == NULL) {
+    if (!Add) {
+      return 0;
+    }
+
+    /* Create new TCAM entry */
+    /* Find first range mac entry*/
+    for (Tid = MVPP2_PE_FIRST_FREE_TID; Tid <= MVPP2_PE_LAST_FREE_TID; Tid++) {
+      if (Priv->PrsShadow[Tid].Valid &&
+          (Priv->PrsShadow[Tid].Lu == MVPP2_PRS_LU_MAC) &&
+          (Priv->PrsShadow[Tid].Udf == MVPP2_PRS_UDF_MAC_RANGE))
+      {
+        break;
+      }
+    }
+
+
+    /* Go through the all entries from first to last */
+    Tid = Mvpp2PrsTcamFirstFree (Priv, MVPP2_PE_FIRST_FREE_TID, Tid - 1);
+    if (Tid < 0) {
+      return Tid;
+    }
+
+    Pe = Mvpp2Alloc (sizeof (*Pe));
+    if (Pe == NULL) {
+      return -1;
+    }
+
+    Mvpp2PrsTcamLuSet (Pe, MVPP2_PRS_LU_MAC);
+    Pe->Index = Tid;
+
+    /* Mask all Ports */
+    Mvpp2PrsTcamPortMapSet (Pe, 0);
+  }
+
+  /* Update PortId Mask */
+  Mvpp2PrsTcamPortSet (Pe, PortId, Add);
+
+  /* Invalidate the entry if no Ports are left enabled */
+  Pmap = Mvpp2PrsTcamPortMapGet (Pe);
+  if (Pmap == 0) {
+    if (Add) {
+      Mvpp2Free (Pe);
+      return -1;
+    }
+
+    Mvpp2PrsHwInv (Priv, Pe->Index);
+    Priv->PrsShadow[Pe->Index].Valid = FALSE;
+
+    Mvpp2Free (Pe);
+
+    return 0;
+  }
+
+  /* Continue - set next lookup */
+  Mvpp2PrsSramNextLuSet (Pe, MVPP2_PRS_LU_DSA);
+
+  /* Set match on DA */
+  Len = MV_ETH_ALEN;
+  while (Len--) {
+    Mvpp2PrsTcamDataByteSet (Pe, Len, Da[Len], 0xff);
+  }
+
+  /* Set result info bits */
+  if (Mvpp2IsBroadcastEtherAddr (Da)) {
+    Ri = MVPP2_PRS_RI_L2_BCAST;
+  } else if (Mvpp2IsMulticastEtherAddr (Da)) {
+    Ri = MVPP2_PRS_RI_L2_MCAST;
+  } else {
+    Ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
+  }
+
+  Mvpp2PrsSramRiUpdate (Pe, Ri, MVPP2_PRS_RI_L2_CAST_MASK | MVPP2_PRS_RI_MAC_ME_MASK);
+  Mvpp2PrsShadowRiSet (Priv, Pe->Index, Ri, MVPP2_PRS_RI_L2_CAST_MASK | MVPP2_PRS_RI_MAC_ME_MASK);
+
+  /* Shift to ethertype */
+  Mvpp2PrsSramShiftSet (Pe, 2 * MV_ETH_ALEN, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
+
+  /* Update shadow table and hw entry */
+  Priv->PrsShadow[Pe->Index].Udf = MVPP2_PRS_UDF_MAC_DEF;
+  Mvpp2PrsShadowSet (Priv, Pe->Index, MVPP2_PRS_LU_MAC);
+  Mvpp2PrsHwWrite (Priv, Pe);
+
+  Mvpp2Free (Pe);
+
+  return 0;
+}
+
+/* Delete all Port's multicast simple (not range) entries */
+VOID
+Mvpp2PrsMcastDelAll (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId
+  )
+{
+  MVPP2_PRS_ENTRY Pe;
+  INT32 Index, Tid;
+
+  for (Tid = MVPP2_PE_FIRST_FREE_TID; Tid <= MVPP2_PE_LAST_FREE_TID; Tid++) {
+    UINT8 Da[MV_ETH_ALEN], DaMask[MV_ETH_ALEN];
+
+    if (!Priv->PrsShadow[Tid].Valid ||
+        (Priv->PrsShadow[Tid].Lu != MVPP2_PRS_LU_MAC) ||
+        (Priv->PrsShadow[Tid].Udf != MVPP2_PRS_UDF_MAC_DEF))
+    {
+      continue;
+    }
+
+    /* Only simple mac entries */
+    Pe.Index = Tid;
+    Mvpp2PrsHwRead (Priv, &Pe);
+
+    /* Read mac Addr from entry */
+    for (Index = 0; Index < MV_ETH_ALEN; Index++) {
+      Mvpp2PrsTcamDataByteGet (&Pe, Index, &Da[Index], &DaMask[Index]);
+    }
+
+    if (Mvpp2IsMulticastEtherAddr (Da) && !Mvpp2IsBroadcastEtherAddr (Da)) {
+      /* Delete this entry */
+      Mvpp2PrsMacDaAccept (Priv, PortId, Da, FALSE);
+    }
+  }
+}
+
+INT32
+Mvpp2PrsTagModeSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN INT32 Type
+  )
+{
+  switch (Type) {
+  case MVPP2_TAG_TYPE_EDSA:
+    /* Add PortId to EDSA entries */
+    Mvpp2PrsDsaTagSet (Priv, PortId, TRUE, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
+    Mvpp2PrsDsaTagSet (Priv, PortId, TRUE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
+    /* Remove PortId from DSA entries */
+    Mvpp2PrsDsaTagSet (Priv, PortId, FALSE, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
+    Mvpp2PrsDsaTagSet (Priv, PortId, FALSE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
+    break;
+  case MVPP2_TAG_TYPE_DSA:
+    /* Add PortId to DSA entries */
+    Mvpp2PrsDsaTagSet (Priv, PortId, TRUE, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
+    Mvpp2PrsDsaTagSet (Priv, PortId, TRUE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
+
+    /* Remove PortId from EDSA entries */
+    Mvpp2PrsDsaTagSet (Priv, PortId, FALSE, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
+    Mvpp2PrsDsaTagSet (Priv, PortId, FALSE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
+    break;
+  case MVPP2_TAG_TYPE_MH:
+  case MVPP2_TAG_TYPE_NONE:
+    /* Remove PortId form EDSA and DSA entries */
+    Mvpp2PrsDsaTagSet (Priv, PortId, FALSE, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
+    Mvpp2PrsDsaTagSet (Priv, PortId, FALSE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
+    Mvpp2PrsDsaTagSet (Priv, PortId, FALSE, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
+    Mvpp2PrsDsaTagSet (Priv, PortId, FALSE, MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
+    break;
+  default:
+    if ((Type < 0) || (Type > MVPP2_TAG_TYPE_EDSA)) {
+      return MVPP2_EINVAL;
+    }
+  }
+
+  return 0;
+}
+
+/* Set prs Flow for the Port */
+INT32
+Mvpp2PrsDefFlow (
+  IN PP2DXE_PORT *Port
+  )
+{
+  MVPP2_PRS_ENTRY *Pe;
+  INT32 Tid;
+
+  Pe = Mvpp2PrsFlowFind (Port->Priv, Port->Id);
+
+  /* Such entry not exist */
+  if (Pe == NULL) {
+    /* Go through the all entires from last to first */
+    Tid = Mvpp2PrsTcamFirstFree (Port->Priv, MVPP2_PE_LAST_FREE_TID, MVPP2_PE_FIRST_FREE_TID);
+    if (Tid < 0) {
+      return Tid;
+    }
+
+    Pe = Mvpp2Alloc (sizeof (*Pe));
+    if (Pe == NULL) {
+      return MVPP2_ENOMEM;
+    }
+
+    Mvpp2PrsTcamLuSet (Pe, MVPP2_PRS_LU_FLOWS);
+    Pe->Index = Tid;
+
+    /* Set Flow ID*/
+    Mvpp2PrsSramAiUpdate (Pe, Port->Id, MVPP2_PRS_FLOW_ID_MASK);
+    Mvpp2PrsSramBitsSet (Pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
+
+    /* Update shadow table */
+    Mvpp2PrsShadowSet (Port->Priv, Pe->Index, MVPP2_PRS_LU_FLOWS);
+  }
+
+  Mvpp2PrsTcamPortMapSet (Pe, (1 << Port->Id));
+  Mvpp2PrsHwWrite (Port->Priv, Pe);
+  Mvpp2Free (Pe);
+
+  return 0;
+}
+
+/* Classifier configuration routines */
+
+/* Update classification Flow table RegValisters */
+STATIC
+VOID
+Mvpp2ClsFlowWrite (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_CLS_FLOW_ENTRY *Fe
+  )
+{
+  Mvpp2Write (Priv, MVPP2_CLS_FLOW_INDEX_REG, Fe->Index);
+  Mvpp2Write (Priv, MVPP2_CLS_FLOW_TBL0_REG, Fe->Data[0]);
+  Mvpp2Write (Priv, MVPP2_CLS_FLOW_TBL1_REG, Fe->Data[1]);
+  Mvpp2Write (Priv, MVPP2_CLS_FLOW_TBL2_REG, Fe->Data[2]);
+}
+
+/* Update classification lookup table RegValister */
+VOID
+Mvpp2ClsLookupWrite (
+  IN MVPP2_SHARED *Priv,
+  IN OUT MVPP2_CLS_LOOKUP_ENTRY *Le
+  )
+{
+  UINT32 Val;
+
+  Val = (Le->Way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | Le->Lkpid;
+  Mvpp2Write (Priv, MVPP2_CLS_LKP_INDEX_REG, Val);
+  Mvpp2Write (Priv, MVPP2_CLS_LKP_TBL_REG, Le->Data);
+}
+
+/* Classifier default initialization */
+VOID
+Mvpp2ClsInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  MVPP2_CLS_LOOKUP_ENTRY Le;
+  MVPP2_CLS_FLOW_ENTRY Fe;
+  INT32 Index;
+
+  /* Enable classifier */
+  Mvpp2Write (Priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
+
+  /* Clear classifier Flow table */
+  Mvpp2Memset (&Fe.Data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
+  for (Index = 0; Index < MVPP2_CLS_FLOWS_TBL_SIZE; Index++) {
+    Fe.Index = Index;
+    Mvpp2ClsFlowWrite (Priv, &Fe);
+  }
+
+  /* Clear classifier lookup table */
+  Le.Data = 0;
+  for (Index = 0; Index < MVPP2_CLS_LKP_TBL_SIZE; Index++) {
+    Le.Lkpid = Index;
+    Le.Way = 0;
+    Mvpp2ClsLookupWrite (Priv, &Le);
+
+    Le.Way = 1;
+    Mvpp2ClsLookupWrite (Priv, &Le);
+  }
+}
+
+VOID
+Mvpp2ClsPortConfig (
+  IN PP2DXE_PORT *Port
+  )
+{
+  MVPP2_CLS_LOOKUP_ENTRY Le;
+  UINT32 Val;
+
+  /* Set way for the Port */
+  Val = Mvpp2Read (Port->Priv, MVPP2_CLS_PORT_WAY_REG);
+  Val &= ~MVPP2_CLS_PORT_WAY_MASK (Port->Id);
+  Mvpp2Write (Port->Priv, MVPP2_CLS_PORT_WAY_REG, Val);
+
+  /*
+   * Pick the entry to be accessed in lookup ID decoding table
+   * according to the way and lkpid.
+   */
+  Le.Lkpid = Port->Id;
+  Le.Way = 0;
+  Le.Data = 0;
+
+  /* Set initial CPU Queue for receiving packets */
+  Le.Data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
+  Le.Data |= Port->FirstRxq;
+
+  /* Disable classification engines */
+  Le.Data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
+
+  /* Update lookup ID table entry */
+  Mvpp2ClsLookupWrite (Port->Priv, &Le);
+}
+
+/* Set CPU Queue number for oversize packets */
+VOID
+Mvpp2ClsOversizeRxqSet (
+  IN PP2DXE_PORT *Port
+  )
+{
+
+  Mvpp2Write (
+          Port->Priv,
+          MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(Port->Id),
+          Port->FirstRxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK
+        );
+}
+
+/* BM helper routines */
+
+VOID
+Mvpp2BmPoolHwCreate (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_BMS_POOL *BmPool,
+  IN INT32 Size
+  )
+{
+  BmPool->Size = Size;
+
+  Mvpp2Write (Priv, MVPP2_BM_POOL_BASE_REG(BmPool->Id), Lower32Bits (BmPool->PhysAddr));
+  Mvpp2Write (Priv, MVPP22_BM_POOL_BASE_HIGH_REG, (Upper32Bits (BmPool->PhysAddr) & MVPP22_BM_POOL_BASE_HIGH_REG));
+  Mvpp2Write (Priv, MVPP2_BM_POOL_SIZE_REG(BmPool->Id), BmPool->Size);
+}
+
+/* Set Pool buffer Size */
+VOID
+Mvpp2BmPoolBufsizeSet (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_BMS_POOL *BmPool,
+  IN INT32 BufSize
+  )
+{
+  UINT32 Val;
+
+  BmPool->BufSize = BufSize;
+
+  Val = MVPP2_ALIGN (BufSize, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
+  Mvpp2Write (Priv, MVPP2_POOL_BUF_SIZE_REG(BmPool->Id), Val);
+}
+
+VOID
+Mvpp2BmStop (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Pool
+  )
+{
+  UINT32 Val, i;
+
+  for (i = 0; i < MVPP2_BM_SIZE; i++) {
+    Mvpp2Read (Priv, MVPP2_BM_PHY_ALLOC_REG(0));
+  }
+
+  Val = Mvpp2Read (Priv, MVPP2_BM_POOL_CTRL_REG(Pool));
+  Val |= MVPP2_BM_STOP_MASK;
+  Mvpp2Write (Priv, MVPP2_BM_POOL_CTRL_REG(Pool), Val);
+}
+
+VOID
+Mvpp2BmIrqClear (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Pool
+  )
+{
+  /* Mask BM all interrupts */
+  Mvpp2Write (Priv, MVPP2_BM_INTR_MASK_REG(Pool), 0);
+
+  /* Clear BM cause RegValister */
+  Mvpp2Write (Priv, MVPP2_BM_INTR_CAUSE_REG(Pool), 0);
+}
+
+/* Attach long Pool to Rxq */
+VOID
+Mvpp2RxqLongPoolSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Lrxq,
+  IN INT32 LongPool
+  )
+{
+  UINT32 Val;
+  INT32 Prxq;
+
+  /* Get Queue physical ID */
+  Prxq = Port->Rxqs[Lrxq].Id;
+
+  Val = Mvpp2Read (Port->Priv, MVPP2_RXQ_CONFIG_REG(Prxq));
+  Val &= ~MVPP2_RXQ_POOL_LONG_MASK;
+  Val |= ((LongPool << MVPP2_RXQ_POOL_LONG_OFFS) & MVPP2_RXQ_POOL_LONG_MASK);
+
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_CONFIG_REG(Prxq), Val);
+}
+
+/* Attach short Pool to Rxq */
+VOID
+Mvpp2RxqShortPoolSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Lrxq,
+  IN INT32 ShortPool
+  )
+{
+  UINT32 Val;
+  INT32 Prxq;
+
+  /* Get Queue physical ID */
+  Prxq = Port->Rxqs[Lrxq].Id;
+
+  Val = Mvpp2Read (Port->Priv, MVPP2_RXQ_CONFIG_REG(Prxq));
+  Val &= ~MVPP2_RXQ_POOL_SHORT_MASK;
+  Val |= ((ShortPool << MVPP2_RXQ_POOL_SHORT_OFFS) & MVPP2_RXQ_POOL_SHORT_MASK);
+
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_CONFIG_REG(Prxq), Val);
+}
+
+/* Release multicast buffer */
+VOID
+Mvpp2BmPoolMcPut (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Pool,
+  IN UINT32 BufPhysAddr,
+  IN UINT32 BufVirtAddr,
+  IN INT32 McId
+  )
+{
+  UINT32 Val = 0;
+
+  Val |= (McId & MVPP2_BM_MC_ID_MASK);
+  Mvpp2Write (Port->Priv, MVPP2_BM_MC_RLS_REG, Val);
+
+  Mvpp2BmPoolPut (Port->Priv, Pool, BufPhysAddr | MVPP2_BM_PHY_RLS_MC_BUFF_MASK, BufVirtAddr);
+}
+
+/* Refill BM Pool */
+VOID
+Mvpp2PoolRefill (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Bm,
+  IN UINT32 PhysAddr,
+  IN UINT32 cookie
+  )
+{
+  INT32 Pool = Mvpp2BmCookiePoolGet (Bm);
+
+  Mvpp2BmPoolPut (Port->Priv, Pool, PhysAddr, cookie);
+}
+
+INTN
+Mvpp2BmPoolCtrl (
+  IN MVPP2_SHARED *Priv,
+  IN INTN Pool,
+  IN enum Mvpp2Command Cmd
+  )
+{
+  UINT32 RegVal = 0;
+  RegVal = Mvpp2Read (Priv, MVPP2_BM_POOL_CTRL_REG(Pool));
+
+  switch (Cmd) {
+  case MVPP2_START:
+    RegVal |= MVPP2_BM_START_MASK;
+    break;
+
+  case MVPP2_STOP:
+    RegVal |= MVPP2_BM_STOP_MASK;
+    break;
+
+  default:
+    return -1;
+  }
+  Mvpp2Write (Priv, MVPP2_BM_POOL_CTRL_REG(Pool), RegVal);
+
+  return 0;
+}
+
+/* Mask the current CPU's Rx/Tx interrupts */
+VOID
+Mvpp2InterruptsMask (
+  IN VOID *arg
+  )
+{
+  PP2DXE_PORT *Port = arg;
+
+  Mvpp2Write (Port->Priv, MVPP2_ISR_RX_TX_MASK_REG(Port->Id), 0);
+}
+
+/* Unmask the current CPU's Rx/Tx interrupts */
+VOID
+Mvpp2InterruptsUnmask (
+  IN VOID *arg
+  )
+{
+  PP2DXE_PORT *Port = arg;
+
+  Mvpp2Write (
+          Port->Priv,
+          MVPP2_ISR_RX_TX_MASK_REG(Port->Id),
+          (MVPP2_CAUSE_MISC_SUM_MASK | MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK)
+        );
+}
+
+/* MAC configuration routines */
+
+STATIC
+VOID
+Mvpp2PortMiiSet (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+
+  Val = Mvpp2GmacRead (Port, MVPP2_GMAC_CTRL_2_REG);
+
+  switch (Port->PhyInterface) {
+  case MV_MODE_SGMII:
+    Val |= MVPP2_GMAC_INBAND_AN_MASK;
+    break;
+  case MV_MODE_RGMII:
+    Val |= MVPP2_GMAC_PORT_RGMII_MASK;
+  default:
+    Val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
+  }
+
+  Mvpp2GmacWrite (Port, MVPP2_GMAC_CTRL_2_REG, Val);
+}
+
+STATIC
+VOID Mvpp2PortFcAdvEnable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+
+  Val = Mvpp2GmacRead (Port, MVPP2_GMAC_AUTONEG_CONFIG);
+  Val |= MVPP2_GMAC_FC_ADV_EN;
+  Mvpp2GmacWrite (Port, MVPP2_GMAC_AUTONEG_CONFIG, Val);
+}
+
+VOID
+Mvpp2PortEnable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+
+  Val = Mvpp2GmacRead (Port, MVPP2_GMAC_CTRL_0_REG);
+  Val |= MVPP2_GMAC_PORT_EN_MASK;
+  Val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
+  Mvpp2GmacWrite (Port, MVPP2_GMAC_CTRL_0_REG, Val);
+}
+
+VOID
+Mvpp2PortDisable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+
+  Val = Mvpp2GmacRead (Port, MVPP2_GMAC_CTRL_0_REG);
+  Val &= ~(MVPP2_GMAC_PORT_EN_MASK);
+  Mvpp2GmacWrite (Port, MVPP2_GMAC_CTRL_0_REG, Val);
+}
+
+/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
+STATIC
+VOID
+Mvpp2PortPeriodicXonDisable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+
+  Val = Mvpp2GmacRead (Port, MVPP2_GMAC_CTRL_1_REG) & ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
+  Mvpp2GmacWrite (Port, MVPP2_GMAC_CTRL_1_REG, Val);
+}
+
+/* Configure loopback Port */
+STATIC
+VOID
+Mvpp2PortReset (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+
+  Val = Mvpp2GmacRead (Port, MVPP2_GMAC_CTRL_2_REG) & ~MVPP2_GMAC_PORT_RESET_MASK;
+  Mvpp2GmacWrite (Port, MVPP2_GMAC_CTRL_2_REG, Val);
+
+  while (Mvpp2GmacRead (Port, MVPP2_GMAC_CTRL_2_REG) & MVPP2_GMAC_PORT_RESET_MASK) {
+    continue;
+  }
+}
+
+/* Set defaults to the MVPP2 Port */
+VOID
+Mvpp2DefaultsSet (
+  IN PP2DXE_PORT *Port
+  )
+{
+  INT32 TxPortNum, Val, Queue, pTxq;
+
+  /* Disable Legacy WRR, Disable EJP, Release from Reset */
+  TxPortNum = Mvpp2EgressPort (Port);
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum);
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
+
+  /* Close bandwidth for all Queues */
+  for (Queue = 0; Queue < MVPP2_MAX_TXQ; Queue++) {
+    pTxq = Mvpp2TxqPhys (Port->Id, Queue);
+    Mvpp2Write (Port->Priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(pTxq), 0);
+  }
+
+
+  /* Set refill period to 1 Usec, refill tokens and bucket Size to maximum */
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PERIOD_REG, Port->Priv->Tclk / MVPP2_USEC_PER_SEC);
+  Val = Mvpp2Read (Port->Priv, MVPP2_TXP_SCHED_REFILL_REG);
+  Val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
+  Val |= MVPP2_TXP_REFILL_PERIOD_MASK (1);
+  Val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_REFILL_REG, Val);
+  Val = MVPP2_TXP_TOKEN_SIZE_MAX;
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, Val);
+
+  /* Set MaximumLowLatencyPacketSize value to 256 */
+  Mvpp2Write (
+          Port->Priv,
+          MVPP2_RX_CTRL_REG(Port->Id),
+          MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | MVPP2_RX_LOW_LATENCY_PKT_SIZE (256)
+        );
+
+  /* Mask all interrupts to all present cpus */
+  Mvpp2InterruptsDisable (Port, 0x1);
+}
+
+/* Enable/disable receiving packets */
+VOID
+Mvpp2IngressEnable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+  INT32 Lrxq, Queue;
+
+  for (Lrxq = 0; Lrxq < RxqNumber; Lrxq++) {
+    Queue = Port->Rxqs[Lrxq].Id;
+    Val = Mvpp2Read (Port->Priv, MVPP2_RXQ_CONFIG_REG(Queue));
+    Val &= ~MVPP2_RXQ_DISABLE_MASK;
+    Mvpp2Write (Port->Priv, MVPP2_RXQ_CONFIG_REG(Queue), Val);
+  }
+}
+
+VOID
+Mvpp2IngressDisable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+  INT32 Lrxq, Queue;
+
+  for (Lrxq = 0; Lrxq < RxqNumber; Lrxq++) {
+    Queue = Port->Rxqs[Lrxq].Id;
+    Val = Mvpp2Read (Port->Priv, MVPP2_RXQ_CONFIG_REG(Queue));
+    Val |= MVPP2_RXQ_DISABLE_MASK;
+    Mvpp2Write (Port->Priv, MVPP2_RXQ_CONFIG_REG(Queue), Val);
+  }
+}
+
+/* Enable transmit via physical egress Queue - HW starts take descriptors from DRAM */
+VOID
+Mvpp2EgressEnable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 qmap;
+  INT32 Queue;
+  INT32 TxPortNum = Mvpp2EgressPort (Port);
+
+  /* Enable all initialized TXs. */
+  qmap = 0;
+  for (Queue = 0; Queue < TxqNumber; Queue++) {
+    MVPP2_TX_QUEUE *Txq = &Port->Txqs[Queue];
+
+    if (Txq->Descs != NULL) {
+      qmap |= (1 << Queue);
+    }
+  }
+
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum);
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
+}
+
+/* Disable transmit via physical egress Queue - HW doesn't take descriptors from DRAM */
+VOID
+Mvpp2EgressDisable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 RegData;
+  INT32 Delay;
+  INT32 TxPortNum = Mvpp2EgressPort (Port);
+
+  /* Issue stop command for active channels only */
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum);
+  RegData = (Mvpp2Read (Port->Priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & MVPP2_TXP_SCHED_ENQ_MASK;
+  if (RegData != 0) {
+    Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_Q_CMD_REG, (RegData << MVPP2_TXP_SCHED_DISQ_OFFSET));
+  }
+
+  /* Wait for all Tx activity to terminate. */
+  Delay = 0;
+  do {
+    if (Delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
+      Mvpp2Printf ("Tx stop timed out, status=0x%08x\n", RegData);
+      break;
+    }
+    Mvpp2Mdelay (1);
+    Delay++;
+
+    /* Check Port TX Command RegValister that all Tx Queues are stopped */
+    RegData = Mvpp2Read (Port->Priv, MVPP2_TXP_SCHED_Q_CMD_REG);
+  } while (RegData & MVPP2_TXP_SCHED_ENQ_MASK);
+}
+
+/* Rx descriptors helper methods */
+
+/* Set rx Queue Offset */
+STATIC
+VOID
+Mvpp2RxqOffsetSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Prxq,
+  IN INT32 Offset
+  )
+{
+  UINT32 Val;
+
+  /* Convert Offset from bytes to units of 32 bytes */
+  Offset = Offset >> 5;
+
+  /* Clear previous value */
+  Val = Mvpp2Read (Port->Priv, MVPP2_RXQ_CONFIG_REG(Prxq));
+  Val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
+
+  /* Update packet Offset in received buffer */
+  Val |= ((Offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & MVPP2_RXQ_PACKET_OFFSET_MASK);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_CONFIG_REG(Prxq), Val);
+}
+
+/* Obtain BM cookie information from descriptor */
+UINT32
+Mvpp2BmCookieBuild (
+  IN MVPP2_RX_DESC *RxDesc,
+  IN INT32 Cpu
+  )
+{
+  INT32 Pool;
+  UINT32 ret;
+
+  Pool = (RxDesc->status & MVPP2_RXD_BM_POOL_ID_MASK) >> MVPP2_RXD_BM_POOL_ID_OFFS;
+
+  ret = ((Pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) | ((Cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
+
+  return ret;
+}
+
+/* Tx descriptors helper methods */
+
+INT32
+Mvpp2TxqDrainSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Txq,
+  IN BOOLEAN En
+  )
+{
+  UINT32 RegVal;
+  INT32 pTxq = Mvpp2TxqPhys (Port->Id, Txq);
+
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_NUM_REG, pTxq);
+  RegVal = Mvpp2Read (Port->Priv, MVPP2_TXQ_PREF_BUF_REG);
+
+  if (En) {
+    RegVal |= MVPP2_TXQ_DRAIN_EN_MASK;
+  } else {
+    RegVal &= ~MVPP2_TXQ_DRAIN_EN_MASK;
+  }
+
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_PREF_BUF_REG, RegVal);
+
+  return 0;
+}
+
+/* Get number of Tx descriptors waiting to be transmitted by HW */
+INT32
+Mvpp2TxqPendDescNumGet (
+  IN PP2DXE_PORT *Port,
+  IN MVPP2_TX_QUEUE *Txq
+  )
+{
+  UINT32 Val;
+
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_NUM_REG, Txq->Id);
+  Val = Mvpp2Read (Port->Priv, MVPP2_TXQ_PENDING_REG);
+
+  return Val & MVPP2_TXQ_PENDING_MASK;
+}
+
+/* Get number of occupied aggRegValated Tx descriptors */
+UINT32
+Mvpp2AggrTxqPendDescNumGet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Cpu
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Read (Priv, MVPP2_AGGR_TXQ_STATUS_REG(Cpu));
+
+  return RegVal & MVPP2_AGGR_TXQ_PENDING_MASK;
+}
+
+/* Get pointer to next Tx descriptor to be processed (send) by HW */
+MVPP2_TX_DESC *
+Mvpp2TxqNextDescGet (
+  MVPP2_TX_QUEUE *Txq
+  )
+{
+  INT32 TxDesc = Txq->NextDescToProc;
+
+  Txq->NextDescToProc = MVPP2_QUEUE_NEXT_DESC (Txq, TxDesc);
+
+  return Txq->Descs + TxDesc;
+}
+
+/* Update HW with number of aggRegValated Tx descriptors to be sent */
+VOID
+Mvpp2AggrTxqPendDescAdd (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Pending
+  )
+{
+  /* AggRegValated access - relevant TXQ number is written in TX desc */
+  Mvpp2Write (Port->Priv, MVPP2_AGGR_TXQ_UPDATE_REG, Pending);
+}
+
+/*
+ * Check if there are enough free descriptors in aggRegValated Txq.
+ * If not, update the number of occupied descriptors and repeat the check.
+ */
+INT32
+Mvpp2AggrDescNumCheck (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_TX_QUEUE *AggrTxq,
+  IN INT32 Num,
+  IN INT32 Cpu
+  )
+{
+  UINT32 Val;
+
+  if ((AggrTxq->count + Num) > AggrTxq->Size) {
+    /* Update number of occupied aggRegValated Tx descriptors */
+    Val = Mvpp2Read (Priv, MVPP2_AGGR_TXQ_STATUS_REG(Cpu));
+    AggrTxq->count = Val & MVPP2_AGGR_TXQ_PENDING_MASK;
+  }
+
+  if ((AggrTxq->count + Num) > AggrTxq->Size) {
+    return MVPP2_ENOMEM;
+  }
+
+  return 0;
+}
+
+/* Reserved Tx descriptors allocation request */
+INT32
+Mvpp2TxqAllocReservedDesc (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_TX_QUEUE *Txq,
+  IN INT32 Num
+  )
+{
+  UINT32 Val;
+
+  Val = (Txq->Id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | Num;
+  Mvpp2Write (Priv, MVPP2_TXQ_RSVD_REQ_REG, Val);
+
+  Val = Mvpp2Read (Priv, MVPP2_TXQ_RSVD_RSLT_REG);
+
+  return Val & MVPP2_TXQ_RSVD_RSLT_MASK;
+}
+
+/*
+ * Release the last allocated Tx descriptor. Useful to handle DMA
+ * mapping failures in the Tx path.
+ */
+VOID
+Mvpp2TxqDescPut (
+  IN MVPP2_TX_QUEUE *Txq
+  )
+{
+  if (Txq->NextDescToProc == 0) {
+    Txq->NextDescToProc = Txq->LastDesc - 1;
+  } else {
+    Txq->NextDescToProc--;
+  }
+}
+
+/* Set Tx descriptors fields relevant for CSUM calculation */
+UINT32
+Mvpp2TxqDescCsum (
+  IN INT32 L3Offs,
+  IN INT32 L3Proto,
+  IN INT32 IpHdrLen,
+  IN INT32 L4Proto
+  )
+{
+  UINT32 command;
+
+  /*
+   * Fields: L3_Offset, IP_hdrlen, L3_type, G_IPV4Chk,
+   * G_L4_chk, L4_type required only for checksum calculation
+   */
+  command = (L3Offs << MVPP2_TXD_L3_OFF_SHIFT);
+  command |= (IpHdrLen << MVPP2_TXD_IP_HLEN_SHIFT);
+  command |= MVPP2_TXD_IP_CSUM_DISABLE;
+
+  if (L3Proto == Mvpp2SwapBytes16 (MV_ETH_P_IP)) {
+    command &= ~MVPP2_TXD_IP_CSUM_DISABLE;  /* enable IPv4 csum */
+    command &= ~MVPP2_TXD_L3_IP6;           /* enable IPv4 */
+  } else {
+    command |= MVPP2_TXD_L3_IP6;            /* enable IPv6 */
+  }
+
+  if (L4Proto == MV_IPPR_TCP) {
+    command &= ~MVPP2_TXD_L4_UDP;           /* enable TCP */
+    command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
+  } else if (L4Proto == MV_IPPR_UDP) {
+    command |= MVPP2_TXD_L4_UDP;            /* enable UDP */
+    command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
+  } else {
+    command |= MVPP2_TXD_L4_CSUM_NOT;
+  }
+
+  return command;
+}
+
+/* Clear counter of sent packets */
+VOID
+Mvpp2TxqSentCounterClear (
+  IN OUT VOID *arg
+  )
+{
+  PP2DXE_PORT *Port = arg;
+  INT32 Queue;
+
+  for (Queue = 0; Queue < TxqNumber; Queue++) {
+    INT32 Id = Port->Txqs[Queue].Id;
+
+    Mvpp2Read (Port->Priv, MVPP2_TXQ_SENT_REG(Id));
+  }
+}
+
+/* Change maximum receive Size of the Port */
+VOID
+Mvpp2GmacMaxRxSizeSet (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val;
+
+  Val = Mvpp2GmacRead (Port, MVPP2_GMAC_CTRL_0_REG);
+  Val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
+  Val |= (((Port->PktSize - MVPP2_MH_SIZE) / 2) << MVPP2_GMAC_MAX_RX_SIZE_OFFS);
+  Mvpp2GmacWrite (Port, MVPP2_GMAC_CTRL_0_REG, Val);
+}
+
+/* Set max sizes for Tx Queues */
+VOID
+Mvpp2TxpMaxTxSizeSet (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32  Val, Size, mtu;
+  INT32 Txq, TxPortNum;
+
+  mtu = Port->PktSize * 8;
+  if (mtu > MVPP2_TXP_MTU_MAX) {
+    mtu = MVPP2_TXP_MTU_MAX;
+  }
+
+  /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
+  mtu = 3 * mtu;
+
+  /* Indirect access to RegValisters */
+  TxPortNum = Mvpp2EgressPort (Port);
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum);
+
+  /* Set MTU */
+  Val = Mvpp2Read (Port->Priv, MVPP2_TXP_SCHED_MTU_REG);
+  Val &= ~MVPP2_TXP_MTU_MAX;
+  Val |= mtu;
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_MTU_REG, Val);
+
+  /* TXP token Size and all TXQs token Size must be larger that MTU */
+  Val = Mvpp2Read (Port->Priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
+  Size = Val & MVPP2_TXP_TOKEN_SIZE_MAX;
+  if (Size < mtu) {
+    Size = mtu;
+    Val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
+    Val |= Size;
+    Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, Val);
+  }
+
+  for (Txq = 0; Txq < TxqNumber; Txq++) {
+    Val = Mvpp2Read (Port->Priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(Txq));
+    Size = Val & MVPP2_TXQ_TOKEN_SIZE_MAX;
+
+    if (Size < mtu) {
+      Size = mtu;
+      Val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
+      Val |= Size;
+      Mvpp2Write (Port->Priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(Txq), Val);
+    }
+  }
+}
+
+/*
+ * Set the number of packets that will be received before Rx interrupt
+ * will be generated by HW.
+ */
+VOID
+Mvpp2RxPktsCoalSet (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq,
+  IN UINT32 Pkts
+  )
+{
+  UINT32 Val;
+
+  Val = (Pkts & MVPP2_OCCUPIED_THRESH_MASK);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_NUM_REG, Rxq->Id);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_THRESH_REG, Val);
+
+  Rxq->PktsCoal = Pkts;
+}
+
+/* Set the time Delay in Usec before Rx INT32errupt */
+VOID
+Mvpp2RxTimeCoalSet (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq,
+  IN UINT32 Usec
+  )
+{
+  UINT32 Val;
+
+  Val = (Port->Priv->Tclk / MVPP2_USEC_PER_SEC) * Usec;
+  Mvpp2Write (Port->Priv, MVPP2_ISR_RX_THRESHOLD_REG(Rxq->Id), Val);
+
+  Rxq->TimeCoal = Usec;
+}
+
+/* Rx/Tx Queue initialization/cleanup methods */
+
+/* Configure RXQ's */
+VOID
+Mvpp2RxqHwInit (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq
+  )
+{
+  Rxq->LastDesc = Rxq->Size - 1;
+
+  /* Zero occupied and non-occupied counters - direct access */
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_STATUS_REG(Rxq->Id), 0);
+
+  /* Set Rx descriptors Queue starting Address - indirect access */
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_NUM_REG, Rxq->Id);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_DESC_ADDR_REG, Rxq->DescsPhys >> MVPP22_DESC_ADDR_SHIFT);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_DESC_SIZE_REG, Rxq->Size);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_INDEX_REG, 0);
+
+  /* Set Offset */
+  Mvpp2RxqOffsetSet (Port, Rxq->Id, MVPP2_RXQ_OFFSET);
+
+  /* Set coalescing pkts and time */
+  Mvpp2RxPktsCoalSet (Port, Rxq, MVPP2_RX_COAL_PKTS);
+  Mvpp2RxTimeCoalSet (Port, Rxq, Rxq->TimeCoal);
+
+  /* Add number of descriptors ready for receiving packets */
+  Mvpp2RxqStatusUpdate (Port, Rxq->Id, 0, Rxq->Size);
+}
+
+/* Push packets received by the RXQ to BM Pool */
+VOID
+Mvpp2RxqDropPkts (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq,
+  IN INT32 Cpu
+  )
+{
+  INT32 RxReceived;
+
+  RxReceived = Mvpp2RxqReceived (Port, Rxq->Id);
+  if (!RxReceived) {
+    return;
+  }
+
+  Mvpp2RxqStatusUpdate (Port, Rxq->Id, RxReceived, RxReceived);
+}
+
+VOID
+Mvpp2RxqHwDeinit (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq
+  )
+{
+  Rxq->Descs = NULL;
+  Rxq->LastDesc = 0;
+  Rxq->NextDescToProc = 0;
+  Rxq->DescsPhys = 0;
+
+  /*
+   * Clear Rx descriptors Queue starting Address and Size;
+   * free descriptor number
+   */
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_STATUS_REG(Rxq->Id), 0);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_NUM_REG, Rxq->Id);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
+  Mvpp2Write (Port->Priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
+}
+
+/* Configure TXQ's */
+VOID
+Mvpp2TxqHwInit (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_TX_QUEUE *Txq
+  )
+{
+  INT32 Desc, DescPerTxq, TxPortNum;
+  UINT32 Val;
+
+  Txq->LastDesc = Txq->Size - 1;
+
+  /* Set Tx descriptors Queue starting Address - indirect access */
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_NUM_REG, Txq->Id);
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_DESC_ADDR_REG, Txq->DescsPhys);
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_DESC_SIZE_REG, Txq->Size & MVPP2_TXQ_DESC_SIZE_MASK);
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_INDEX_REG, 0);
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_RSVD_CLR_REG, Txq->Id << MVPP2_TXQ_RSVD_CLR_OFFSET);
+  Val = Mvpp2Read (Port->Priv, MVPP2_TXQ_PENDING_REG);
+  Val &= ~MVPP2_TXQ_PENDING_MASK;
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_PENDING_REG, Val);
+
+  /*
+   * Calculate base Address in prefetch buffer. We reserve 16 descriptors
+   * for each existing TXQ.
+   * TCONTS for PON Port must be continuous from 0 to MVPP2_MAX_TCONT
+   * GBE Ports assumed to be continious from 0 to MVPP2_MAX_PORTS
+   */
+  DescPerTxq = 16;
+  Desc = (Port->Id * MVPP2_MAX_TXQ * DescPerTxq) + (Txq->LogId * DescPerTxq);
+
+  Mvpp2Write (
+          Port->Priv,
+          MVPP2_TXQ_PREF_BUF_REG,
+          MVPP2_PREF_BUF_PTR (Desc) | MVPP2_PREF_BUF_SIZE_16 | MVPP2_PREF_BUF_THRESH (DescPerTxq/2)
+        );
+
+  /* WRR / EJP configuration - indirect access */
+  TxPortNum = Mvpp2EgressPort (Port);
+  Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum);
+
+  Val = Mvpp2Read (Port->Priv, MVPP2_TXQ_SCHED_REFILL_REG(Txq->LogId));
+  Val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
+  Val |= MVPP2_TXQ_REFILL_PERIOD_MASK (1);
+  Val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_SCHED_REFILL_REG(Txq->LogId), Val);
+
+  Val = MVPP2_TXQ_TOKEN_SIZE_MAX;
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(Txq->LogId), Val);
+}
+
+VOID
+Mvpp2TxqHwDeinit (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_TX_QUEUE *Txq
+  )
+{
+  Txq->Descs = NULL;
+  Txq->LastDesc = 0;
+  Txq->NextDescToProc = 0;
+  Txq->DescsPhys = 0;
+
+  /* Set minimum bandwidth for disabled TXQs */
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(Txq->Id), 0);
+
+  /* Set Tx descriptors Queue starting Address and Size */
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_NUM_REG, Txq->Id);
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
+}
+
+/* Allocate and initialize descriptors for aggr TXQ */
+VOID
+Mvpp2AggrTxqHwInit (
+  IN OUT MVPP2_TX_QUEUE *AggrTxq,
+  IN INT32 DescNum,
+  IN INT32 Cpu,
+  IN MVPP2_SHARED *Priv
+  )
+{
+  AggrTxq->LastDesc = AggrTxq->Size - 1;
+
+  /* Aggr TXQ no Reset WA */
+  AggrTxq->NextDescToProc = Mvpp2Read (Priv, MVPP2_AGGR_TXQ_INDEX_REG(Cpu));
+
+  /* Set Tx descriptors Queue starting Address (indirect access) */
+  Mvpp2Write (Priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(Cpu), AggrTxq->DescsPhys >> MVPP22_DESC_ADDR_SHIFT);
+  Mvpp2Write (Priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(Cpu), DescNum & MVPP2_AGGR_TXQ_DESC_SIZE_MASK);
+}
+
+/* Enable gmac */
+VOID
+Mvpp2PortPowerUp (
+  IN PP2DXE_PORT *Port
+  )
+{
+  Mvpp2PortMiiSet (Port);
+  Mvpp2PortPeriodicXonDisable (Port);
+  Mvpp2PortFcAdvEnable (Port);
+  Mvpp2PortReset (Port);
+}
+
+/* Initialize Rx FIFO's */
+VOID
+Mvpp2RxFifoInit (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  INT32 PortId;
+
+  for (PortId = 0; PortId < MVPP2_MAX_PORTS; PortId++) {
+    Mvpp2Write (Priv, MVPP2_RX_DATA_FIFO_SIZE_REG(PortId), MVPP2_RX_FIFO_PORT_DATA_SIZE);
+    Mvpp2Write (Priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(PortId), MVPP2_RX_FIFO_PORT_ATTR_SIZE);
+  }
+
+  Mvpp2Write (Priv, MVPP2_RX_MIN_PKT_SIZE_REG, MVPP2_RX_FIFO_PORT_MIN_PKT);
+  Mvpp2Write (Priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
+}
+
+VOID
+MvGop110NetcActivePort (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, MV_NETCOMP_PORTS_CONTROL_1);
+  RegVal &= ~(NETC_PORTS_ACTIVE_MASK (PortId));
+
+  Val <<= NETC_PORTS_ACTIVE_OFFSET (PortId);
+  Val &= NETC_PORTS_ACTIVE_MASK (PortId);
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, MV_NETCOMP_PORTS_CONTROL_1, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcXauiEnable (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, SD1_CONTROL_1_REG);
+  RegVal &= ~SD1_CONTROL_XAUI_EN_MASK;
+
+  Val <<= SD1_CONTROL_XAUI_EN_OFFSET;
+  Val &= SD1_CONTROL_XAUI_EN_MASK;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, SD1_CONTROL_1_REG, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcRxaui0Enable (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, SD1_CONTROL_1_REG);
+  RegVal &= ~SD1_CONTROL_RXAUI0_L23_EN_MASK;
+
+  Val <<= SD1_CONTROL_RXAUI0_L23_EN_OFFSET;
+  Val &= SD1_CONTROL_RXAUI0_L23_EN_MASK;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, SD1_CONTROL_1_REG, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcRxaui1Enable (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, SD1_CONTROL_1_REG);
+  RegVal &= ~SD1_CONTROL_RXAUI1_L45_EN_MASK;
+
+  Val <<= SD1_CONTROL_RXAUI1_L45_EN_OFFSET;
+  Val &= SD1_CONTROL_RXAUI1_L45_EN_MASK;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, SD1_CONTROL_1_REG, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcMiiMode (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, MV_NETCOMP_CONTROL_0);
+  RegVal &= ~NETC_GBE_PORT1_MII_MODE_MASK;
+
+  Val <<= NETC_GBE_PORT1_MII_MODE_OFFSET;
+  Val &= NETC_GBE_PORT1_MII_MODE_MASK;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, MV_NETCOMP_CONTROL_0, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcGopReset (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, MV_GOP_SOFT_RESET_1_REG);
+  RegVal &= ~NETC_GOP_SOFT_RESET_MASK;
+
+  Val <<= NETC_GOP_SOFT_RESET_OFFSET;
+  Val &= NETC_GOP_SOFT_RESET_MASK;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, MV_GOP_SOFT_RESET_1_REG, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcGopClockLogicSet (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, MV_NETCOMP_PORTS_CONTROL_0);
+  RegVal &= ~NETC_CLK_DIV_PHASE_MASK;
+
+  Val <<= NETC_CLK_DIV_PHASE_OFFSET;
+  Val &= NETC_CLK_DIV_PHASE_MASK;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, MV_NETCOMP_PORTS_CONTROL_0, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcPortRfReset (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, MV_NETCOMP_PORTS_CONTROL_1);
+  RegVal &= ~(NETC_PORT_GIG_RF_RESET_MASK (PortId));
+
+  Val <<= NETC_PORT_GIG_RF_RESET_OFFSET (PortId);
+  Val &= NETC_PORT_GIG_RF_RESET_MASK (PortId);
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, MV_NETCOMP_PORTS_CONTROL_1, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcGbeSgmiiModeSelect (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal, Mask, Offset;
+
+  if (PortId == 2) {
+    Mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
+    Offset = NETC_GBE_PORT0_SGMII_MODE_OFFSET;
+  } else {
+    Mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
+    Offset = NETC_GBE_PORT1_SGMII_MODE_OFFSET;
+  }
+  RegVal = Mvpp2Rfu1Read (Port->Priv, MV_NETCOMP_CONTROL_0);
+  RegVal &= ~Mask;
+
+  Val <<= Offset;
+  Val &= Mask;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, MV_NETCOMP_CONTROL_0, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcBusWidthSelect (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, MV_NETCOMP_PORTS_CONTROL_0);
+  RegVal &= ~NETC_BUS_WIDTH_SELECT_MASK;
+
+  Val <<= NETC_BUS_WIDTH_SELECT_OFFSET;
+  Val &= NETC_BUS_WIDTH_SELECT_MASK;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, MV_NETCOMP_PORTS_CONTROL_0, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcSampleStagesTiming (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Val
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Rfu1Read (Port->Priv, MV_NETCOMP_PORTS_CONTROL_0);
+  RegVal &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
+
+  Val <<= NETC_GIG_RX_DATA_SAMPLE_OFFSET;
+  Val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
+
+  RegVal |= Val;
+
+  Mvpp2Rfu1Write (Port->Priv, MV_NETCOMP_PORTS_CONTROL_0, RegVal);
+}
+
+STATIC
+VOID
+MvGop110NetcMacToXgmii (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN enum MvNetcPhase Phase
+  )
+{
+  switch (Phase) {
+  case MV_NETC_FIRST_PHASE:
+
+    /* Set Bus Width to HB mode = 1 */
+    MvGop110NetcBusWidthSelect (Port, 0x1);
+
+    /* Select RGMII mode */
+    MvGop110NetcGbeSgmiiModeSelect (Port, PortId, MV_NETC_GBE_XMII);
+    break;
+  case MV_NETC_SECOND_PHASE:
+
+    /* De-assert the relevant PortId HB Reset */
+    MvGop110NetcPortRfReset (Port, PortId, 0x1);
+    break;
+  }
+}
+
+STATIC
+VOID
+MvGop110NetcMacToSgmii (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN enum MvNetcPhase Phase
+  )
+{
+  switch (Phase) {
+  case MV_NETC_FIRST_PHASE:
+
+    /* Set Bus Width to HB mode = 1 */
+    MvGop110NetcBusWidthSelect (Port, 1);
+
+    /* Select SGMII mode */
+    if (PortId >= 1) {
+      MvGop110NetcGbeSgmiiModeSelect (Port, PortId, MV_NETC_GBE_SGMII);
+    }
+
+    /* Configure the sample stages */
+    MvGop110NetcSampleStagesTiming (Port, 0);
+    break;
+  case MV_NETC_SECOND_PHASE:
+
+    /* De-assert the relevant PortId HB Reset */
+    MvGop110NetcPortRfReset (Port, PortId, 1);
+    break;
+  }
+}
+
+STATIC
+VOID
+MvGop110NetcMacToRxaui (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN enum MvNetcPhase Phase,
+  IN enum MvNetcLanes Lanes
+  )
+{
+  /* Currently only RXAUI0 supPorted */
+  if (PortId != 0)
+    return;
+
+  switch (Phase) {
+  case MV_NETC_FIRST_PHASE:
+
+    /* RXAUI Serdes/s Clock alignment */
+    if (Lanes == MV_NETC_LANE_23) {
+      MvGop110NetcRxaui0Enable (Port, PortId, 1);
+    } else {
+      MvGop110NetcRxaui1Enable (Port, PortId, 1);
+    }
+    break;
+  case MV_NETC_SECOND_PHASE:
+
+    /* De-assert the relevant PortId HB Reset */
+    MvGop110NetcPortRfReset (Port, PortId, 1);
+    break;
+  }
+}
+
+STATIC
+VOID
+MvGop110NetcMacToXaui (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 PortId,
+  IN enum MvNetcPhase Phase
+  )
+{
+  switch (Phase) {
+  case MV_NETC_FIRST_PHASE:
+
+    /* RXAUI Serdes/s Clock alignment */
+    MvGop110NetcXauiEnable (Port, PortId, 1);
+    break;
+  case MV_NETC_SECOND_PHASE:
+
+    /* De-assert the relevant PortId HB Reset */
+    MvGop110NetcPortRfReset (Port, PortId, 1);
+    break;
+  }
+}
+
+INT32
+MvGop110NetcInit (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 NetCompConfig,
+  IN enum MvNetcPhase Phase
+  )
+{
+  UINT32 c = NetCompConfig;
+
+  if (c & MV_NETC_GE_MAC0_RXAUI_L23) {
+    MvGop110NetcMacToRxaui (Port, 0, Phase, MV_NETC_LANE_23);
+  }
+
+  if (c & MV_NETC_GE_MAC0_RXAUI_L45) {
+    MvGop110NetcMacToRxaui (Port, 0, Phase, MV_NETC_LANE_45);
+  }
+
+  if (c & MV_NETC_GE_MAC0_XAUI) {
+    MvGop110NetcMacToXaui (Port, 0, Phase);
+  }
+
+  if (c & MV_NETC_GE_MAC2_SGMII) {
+    MvGop110NetcMacToSgmii (Port, 2, Phase);
+  } else {
+    MvGop110NetcMacToXgmii (Port, 2, Phase);
+  }
+
+  if (c & MV_NETC_GE_MAC3_SGMII) {
+    MvGop110NetcMacToSgmii (Port, 3, Phase);
+  } else {
+    MvGop110NetcMacToXgmii (Port, 3, Phase);
+    if (c & MV_NETC_GE_MAC3_RGMII) {
+      MvGop110NetcMiiMode (Port, 3, MV_NETC_GBE_RGMII);
+    } else {
+      MvGop110NetcMiiMode (Port, 3, MV_NETC_GBE_MII);
+    }
+  }
+
+  /* Activate gop Ports 0, 2, 3 */
+  MvGop110NetcActivePort (Port, 0, 1);
+  MvGop110NetcActivePort (Port, 2, 1);
+  MvGop110NetcActivePort (Port, 3, 1);
+
+  if (Phase == MV_NETC_SECOND_PHASE) {
+
+    /* Enable the GOP internal clock logic */
+    MvGop110NetcGopClockLogicSet (Port, 1);
+
+    /* De-assert GOP unit Reset */
+    MvGop110NetcGopReset (Port, 1);
+  }
+
+  return 0;
+}
+
+UINT32
+MvpPp2xGop110NetcCfgCreate (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val = 0;
+
+    if (Port->GopIndex == 0) {
+      if (Port->PhyInterface == MV_MODE_XAUI) {
+        Val |= MV_NETC_GE_MAC0_XAUI;
+      } else if (Port->PhyInterface == MV_MODE_RXAUI) {
+        Val |= MV_NETC_GE_MAC0_RXAUI_L23;
+      }
+    }
+
+    if (Port->GopIndex == 2) {
+      if (Port->PhyInterface == MV_MODE_SGMII) {
+        Val |= MV_NETC_GE_MAC2_SGMII;
+      }
+    }
+
+    if (Port->GopIndex == 3) {
+      if (Port->PhyInterface == MV_MODE_SGMII) {
+        Val |= MV_NETC_GE_MAC3_SGMII;
+      } else if (Port->PhyInterface == MV_MODE_RGMII) {
+        Val |= MV_NETC_GE_MAC3_RGMII;
+      }
+    }
+
+  return Val;
+}
+
+/*
+ * Initialize physical Port. Configure the Port mode and
+ * all its elements accordingly.
+ */
+INT32
+MvGop110PortInit (
+  IN PP2DXE_PORT *Port
+  )
+{
+
+  switch (Port->PhyInterface) {
+  case MV_MODE_RGMII:
+    MvGop110GmacReset (Port, RESET);
+
+    /* Configure PCS */
+    MvGop110GpcsModeCfg (Port, FALSE);
+    MvGop110BypassClkCfg (Port, TRUE);
+
+    /* Configure MAC */
+    MvGop110GmacModeCfg (Port);
+
+    /* PCS unreset */
+    MvGop110GpcsReset (Port, UNRESET);
+
+    /* MAC unreset */
+    MvGop110GmacReset (Port, UNRESET);
+  break;
+  case MV_MODE_SGMII:
+  case MV_MODE_QSGMII:
+
+    /* Configure PCS */
+    MvGop110GpcsModeCfg (Port, TRUE);
+
+    /* Configure MAC */
+    MvGop110GmacModeCfg (Port);
+
+    /* Select proper MAC mode */
+    MvGop110Xlg2GigMacCfg (Port);
+
+    /* PCS unreset */
+    MvGop110GpcsReset (Port, UNRESET);
+
+    /* MAC unreset */
+    MvGop110GmacReset (Port, UNRESET);
+  break;
+  default:
+    return -1;
+  }
+
+  return 0;
+}
+
+/* Set the MAC to Reset or exit from Reset */
+INT32
+MvGop110GmacReset (
+  IN PP2DXE_PORT *Port,
+  IN enum MvReset ResetCmd
+  )
+{
+  UINT32 RegAddr;
+  UINT32 Val;
+
+  RegAddr = MVPP2_PORT_CTRL2_REG;
+
+  Val = MvGop110GmacRead (Port, RegAddr);
+
+  if (ResetCmd == RESET) {
+    Val |= MVPP2_PORT_CTRL2_PORTMACRESET_MASK;
+  } else {
+    Val &= ~MVPP2_PORT_CTRL2_PORTMACRESET_MASK;
+  }
+
+  MvGop110GmacWrite (Port, RegAddr, Val);
+
+  return 0;
+}
+
+/* Enable/Disable Port to work with Gig PCS */
+INT32
+MvGop110GpcsModeCfg (
+  IN PP2DXE_PORT *Port,
+  BOOLEAN En
+  )
+{
+  UINT32 Val;
+
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL2_REG);
+
+  if (En) {
+    Val |= MVPP2_PORT_CTRL2_PCS_EN_MASK;
+  } else {
+    Val &= ~MVPP2_PORT_CTRL2_PCS_EN_MASK;
+  }
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL2_REG, Val);
+
+  return 0;
+}
+
+INT32
+MvGop110BypassClkCfg (
+  IN PP2DXE_PORT *Port,
+  IN BOOLEAN En
+  )
+{
+  UINT32 Val;
+
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL2_REG);
+
+  if (En) {
+    Val |= MVPP2_PORT_CTRL2_CLK_125_BYPS_EN_MASK;
+  } else {
+    Val &= ~MVPP2_PORT_CTRL2_CLK_125_BYPS_EN_MASK;
+  }
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL2_REG, Val);
+
+  return 0;
+}
+
+INT32
+MvGop110GpcsReset (
+  IN PP2DXE_PORT *Port,
+  IN enum MvReset ResetCmd
+  )
+{
+  UINT32 RegData;
+
+  RegData = MvGop110GmacRead (Port, MVPP2_PORT_CTRL2_REG);
+
+  if (ResetCmd == RESET) {
+    U32_SET_FIELD (
+            RegData,
+            MVPP2_PORT_CTRL2_SGMII_MODE_MASK,
+            0
+          );
+
+  } else {
+    U32_SET_FIELD (
+            RegData,
+            MVPP2_PORT_CTRL2_SGMII_MODE_MASK,
+            1 << MVPP2_PORT_CTRL2_SGMII_MODE_OFFS
+          );
+
+  }
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL2_REG, RegData);
+
+  return 0;
+}
+
+VOID
+MvGop110Xlg2GigMacCfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 RegVal;
+
+  /* Relevant only for MAC0 (XLG0 and GMAC0) */
+  if (Port->GopIndex > 0) {
+    return;
+  }
+
+  /* Configure 1Gig MAC mode */
+  RegVal = Mvpp2XlgRead (Port, MV_XLG_PORT_MAC_CTRL3_REG);
+  U32_SET_FIELD (
+          RegVal,
+          MV_XLG_MAC_CTRL3_MACMODESELECT_MASK,
+          (0 << MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS)
+        );
+
+  Mvpp2XlgWrite (Port, MV_XLG_PORT_MAC_CTRL3_REG, RegVal);
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+INT32
+MvGop110GmacModeCfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 RegAddr;
+  UINT32 Val;
+
+  /* Set TX FIFO thresholds */
+  switch (Port->PhyInterface) {
+  case MV_MODE_SGMII:
+    if (Port->Speed == MV_PORT_SPEED_2500) {
+      MvGop110GmacSgmii25Cfg (Port);
+    } else {
+      MvGop110GmacSgmiiCfg (Port);
+    }
+  break;
+  case MV_MODE_RGMII:
+    MvGop110GmacRgmiiCfg (Port);
+  break;
+  case MV_MODE_QSGMII:
+    MvGop110GmacQsgmiiCfg (Port);
+  break;
+  default:
+    return -1;
+  }
+
+  /* Jumbo frame supPort - 0x1400*2= 0x2800 bytes */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL0_REG);
+  U32_SET_FIELD (
+          Val,
+          MVPP2_PORT_CTRL0_FRAMESIZELIMIT_MASK,
+          (0x1400 << MVPP2_PORT_CTRL0_FRAMESIZELIMIT_OFFS)
+        );
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL0_REG, Val);
+
+  /* PeriodicXonEn disable */
+  RegAddr = MVPP2_PORT_CTRL1_REG;
+  Val = MvGop110GmacRead (Port, RegAddr);
+  Val &= ~MVPP2_PORT_CTRL1_EN_PERIODIC_FC_XON_MASK;
+  MvGop110GmacWrite (Port, RegAddr, Val);
+
+  /* Mask all Ports interrupts */
+  MvGop110GmacPortLinkEventMask (Port);
+
+#if MV_PP2x_INTERRUPT
+  /* Unmask link change interrupt */
+  Val = MvGop110GmacRead (Port, MVPP2_INTERRUPT_MASK_REG);
+  Val |= MVPP2_INTERRUPT_CAUSE_LINK_CHANGE_MASK;
+  Val |= 1; /* Unmask summary bit */
+  MvGop110GmacWrite (Port, MVPP2_INTERRUPT_MASK_REG, Val);
+#endif
+
+  return 0;
+}
+
+VOID
+MvGop110GmacRgmiiCfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val, thresh, an;
+
+  /* Configure minimal level of the Tx FIFO before the lower part starts to read a packet*/
+  thresh = MV_RGMII_TX_FIFO_MIN_TH;
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_FIFO_CFG_1_REG);
+  U32_SET_FIELD (
+          Val,
+          MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_MASK,
+          (thresh << MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_OFFS)
+        );
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_FIFO_CFG_1_REG, Val);
+
+  /* Disable bypass of sync module */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL4_REG);
+  Val |= MVPP2_PORT_CTRL4_SYNC_BYPASS_MASK;
+
+  /* Configure DP clock select according to mode */
+  Val &= ~MVPP2_PORT_CTRL4_DP_CLK_SEL_MASK;
+  Val |= MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+  Val |= MVPP2_PORT_CTRL4_EXT_PIN_GMII_SEL_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL4_REG, Val);
+
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL2_REG);
+  Val &= ~MVPP2_PORT_CTRL2_DIS_PADING_OFFS;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL2_REG, Val);
+
+  /* Configure GIG MAC to SGMII mode */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL0_REG);
+  Val &= ~MVPP2_PORT_CTRL0_PORTTYPE_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL0_REG, Val);
+
+  /* configure AN 0xb8e8 */
+  an = MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_FC_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_AUTO_NEG_CFG_REG, an);
+}
+
+VOID
+MvGop110GmacSgmii25Cfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val, thresh, an;
+
+  /*
+   * Configure minimal level of the Tx FIFO before
+   * the lower part starts to read a packet.
+   */
+  thresh = MV_SGMII2_5_TX_FIFO_MIN_TH;
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_FIFO_CFG_1_REG);
+  U32_SET_FIELD (
+          Val,
+          MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_MASK,
+          (thresh << MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_OFFS)
+        );
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_FIFO_CFG_1_REG, Val);
+
+  /* Disable bypass of sync module */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL4_REG);
+  Val |= MVPP2_PORT_CTRL4_SYNC_BYPASS_MASK;
+
+  /* Configure DP clock select according to mode */
+  Val |= MVPP2_PORT_CTRL4_DP_CLK_SEL_MASK;
+
+  /* Configure QSGMII bypass according to mode */
+  Val |= MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL4_REG, Val);
+
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL2_REG);
+  Val |= MVPP2_PORT_CTRL2_DIS_PADING_OFFS;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL2_REG, Val);
+
+  /* Configure GIG MAC to 1000Base-X mode connected to a fiber transceiver */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL0_REG);
+  Val |= MVPP2_PORT_CTRL0_PORTTYPE_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL0_REG, Val);
+
+  /* configure AN 0x9268 */
+  an = MVPP2_PORT_AUTO_NEG_CFG_EN_PCS_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_SET_MII_SPEED_MASK  |
+       MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_ADV_PAUSE_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_SET_FULL_DX_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_AUTO_NEG_CFG_REG, an);
+}
+
+VOID
+MvGop110GmacSgmiiCfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val, thresh, an;
+
+  /*
+   * Configure minimal level of the Tx FIFO before
+   * the lower part starts to read a packet.
+   */
+  thresh = MV_SGMII_TX_FIFO_MIN_TH;
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_FIFO_CFG_1_REG);
+  U32_SET_FIELD (Val, MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_MASK,
+    (thresh << MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_OFFS));
+  MvGop110GmacWrite (Port, MVPP2_PORT_FIFO_CFG_1_REG, Val);
+
+  /* Disable bypass of sync module */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL4_REG);
+  Val |= MVPP2_PORT_CTRL4_SYNC_BYPASS_MASK;
+
+  /* Configure DP clock select according to mode */
+  Val &= ~MVPP2_PORT_CTRL4_DP_CLK_SEL_MASK;
+
+  /* Configure QSGMII bypass according to mode */
+  Val |= MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL4_REG, Val);
+
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL2_REG);
+  Val |= MVPP2_PORT_CTRL2_DIS_PADING_OFFS;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL2_REG, Val);
+
+  /* Configure GIG MAC to SGMII mode */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL0_REG);
+  Val &= ~MVPP2_PORT_CTRL0_PORTTYPE_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL0_REG, Val);
+
+  /* Configure AN */
+  an = MVPP2_PORT_AUTO_NEG_CFG_EN_PCS_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_FC_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_AUTO_NEG_CFG_REG, an);
+}
+
+VOID
+MvGop110GmacQsgmiiCfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 Val, thresh, an;
+
+  /*
+   * Configure minimal level of the Tx FIFO before
+   * the lower part starts to read a packet.
+   */
+  thresh = MV_SGMII_TX_FIFO_MIN_TH;
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_FIFO_CFG_1_REG);
+  U32_SET_FIELD (
+          Val,
+          MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_MASK,
+          (thresh << MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_OFFS)
+        );
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_FIFO_CFG_1_REG, Val);
+
+  /* Disable bypass of sync module */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL4_REG);
+  Val |= MVPP2_PORT_CTRL4_SYNC_BYPASS_MASK;
+
+  /* Configure DP clock select according to mode */
+  Val &= ~MVPP2_PORT_CTRL4_DP_CLK_SEL_MASK;
+  Val &= ~MVPP2_PORT_CTRL4_EXT_PIN_GMII_SEL_MASK;
+
+  /* Configure QSGMII bypass according to mode */
+  Val &= ~MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL4_REG, Val);
+
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL2_REG);
+  Val &= ~MVPP2_PORT_CTRL2_DIS_PADING_OFFS;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL2_REG, Val);
+
+  /* Configure GIG MAC to SGMII mode */
+  Val = MvGop110GmacRead (Port, MVPP2_PORT_CTRL0_REG);
+  Val &= ~MVPP2_PORT_CTRL0_PORTTYPE_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL0_REG, Val);
+
+  /* Configure AN 0xB8EC */
+  an = MVPP2_PORT_AUTO_NEG_CFG_EN_PCS_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_FC_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_MASK |
+       MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_MASK;
+  MvGop110GmacWrite (Port, MVPP2_PORT_AUTO_NEG_CFG_REG, an);
+}
+
+INT32
+Mvpp2SmiPhyAddrCfg (
+  IN PP2DXE_PORT *Port,
+  IN INT32 PortId,
+  IN INT32 Addr
+  )
+{
+  Mvpp2SmiWrite (Port->Priv, MV_SMI_PHY_ADDRESS_REG(PortId), Addr);
+
+  return 0;
+}
+
+BOOLEAN
+MvGop110PortIsLinkUp (
+  IN PP2DXE_PORT *Port
+  )
+{
+  switch (Port->PhyInterface) {
+  case MV_MODE_RGMII:
+  case MV_MODE_SGMII:
+  case MV_MODE_QSGMII:
+    return MvGop110GmacLinkStatusGet (Port);
+  case MV_MODE_XAUI:
+  case MV_MODE_RXAUI:
+    return FALSE;
+  default:
+    return FALSE;
+  }
+}
+
+/* Get MAC link status */
+BOOLEAN
+MvGop110GmacLinkStatusGet (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 RegAddr;
+  UINT32 Val;
+
+  RegAddr = MVPP2_PORT_STATUS0_REG;
+
+  Val = MvGop110GmacRead (Port, RegAddr);
+
+  return (Val & 1) ? TRUE : FALSE;
+}
+
+VOID
+MvGop110PortDisable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  switch (Port->PhyInterface) {
+  case MV_MODE_RGMII:
+  case MV_MODE_SGMII:
+  case MV_MODE_QSGMII:
+    MvGop110GmacPortDisable (Port);
+    break;
+  default:
+    return;
+  }
+}
+
+VOID
+MvGop110PortEnable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  switch (Port->PhyInterface) {
+  case MV_MODE_RGMII:
+  case MV_MODE_SGMII:
+  case MV_MODE_QSGMII:
+    MvGop110GmacPortEnable (Port);
+    break;
+  default:
+    return;
+  }
+}
+
+/* Enable Port and MIB counters */
+VOID
+MvGop110GmacPortEnable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = MvGop110GmacRead (Port, MVPP2_PORT_CTRL0_REG);
+  RegVal |= MVPP2_PORT_CTRL0_PORTEN_MASK;
+  RegVal |= MVPP2_PORT_CTRL0_COUNT_EN_MASK;
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL0_REG, RegVal);
+}
+
+/* Disable Port */
+VOID
+MvGop110GmacPortDisable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 RegVal;
+
+  /* Mask all Ports interrupts */
+  MvGop110GmacPortLinkEventMask (Port);
+
+  RegVal = MvGop110GmacRead (Port, MVPP2_PORT_CTRL0_REG);
+  RegVal &= ~MVPP2_PORT_CTRL0_PORTEN_MASK;
+
+  MvGop110GmacWrite (Port, MVPP2_PORT_CTRL0_REG, RegVal);
+}
+
+VOID
+MvGop110GmacPortLinkEventMask (
+  IN PP2DXE_PORT *Port
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = MvGop110GmacRead (Port, MV_GMAC_INTERRUPT_SUM_MASK_REG);
+  RegVal &= ~MV_GMAC_INTERRUPT_SUM_CAUSE_LINK_CHANGE_MASK;
+  MvGop110GmacWrite (Port, MV_GMAC_INTERRUPT_SUM_MASK_REG, RegVal);
+}
+
+INT32
+MvGop110PortEventsMask (
+  IN PP2DXE_PORT *Port
+  )
+{
+
+  switch (Port->PhyInterface) {
+  case MV_MODE_RGMII:
+  case MV_MODE_SGMII:
+  case MV_MODE_QSGMII:
+    MvGop110GmacPortLinkEventMask (Port);
+    break;
+  default:
+    return -1;
+  }
+
+  return 0;
+}
+
+INT32
+MvGop110FlCfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  switch (Port->PhyInterface) {
+  case MV_MODE_RGMII:
+  case MV_MODE_SGMII:
+  case MV_MODE_QSGMII:
+    /* Disable AN */
+    MvGop110SpeedDuplexSet (Port, Port->Speed, MV_PORT_DUPLEX_FULL);
+    break;
+  case MV_MODE_XAUI:
+  case MV_MODE_RXAUI:
+    return 0;
+  default:
+    return -1;
+  }
+
+  return 0;
+}
+
+/* Set Port Speed and Duplex */
+INT32
+MvGop110SpeedDuplexSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Speed,
+  IN enum MvPortDuplex Duplex
+  )
+{
+  switch (Port->PhyInterface) {
+  case MV_MODE_RGMII:
+  case MV_MODE_SGMII:
+  case MV_MODE_QSGMII:
+    MvGop110GmacSpeedDuplexSet (Port, Speed, Duplex);
+    break;
+  case MV_MODE_XAUI:
+  case MV_MODE_RXAUI:
+    break;
+  default:
+    return -1;
+  }
+
+  return 0;
+}
+
+/*
+ * Sets Port Speed to Auto Negotiation / 1000 / 100 / 10 Mbps.
+ * Sets Port Duplex to Auto Negotiation / Full / Half Duplex.
+ */
+INT32
+MvGop110GmacSpeedDuplexSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Speed,
+  IN enum MvPortDuplex Duplex
+  )
+{
+  UINT32 RegVal;
+
+  RegVal = Mvpp2GmacRead (Port, MVPP2_PORT_AUTO_NEG_CFG_REG);
+
+  switch (Speed) {
+  case MV_PORT_SPEED_2500:
+  case MV_PORT_SPEED_1000:
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_MASK;
+    RegVal |= MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_MASK;
+    /* The 100/10 bit doesn't matter in this case */
+    break;
+  case MV_PORT_SPEED_100:
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_MASK;
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_MASK;
+    RegVal |= MVPP2_PORT_AUTO_NEG_CFG_SET_MII_SPEED_MASK;
+    break;
+  case MV_PORT_SPEED_10:
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_MASK;
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_MASK;
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_SET_MII_SPEED_MASK;
+    break;
+  default:
+    return MVPP2_EINVAL;
+  }
+
+  switch (Duplex) {
+  case MV_PORT_DUPLEX_AN:
+    RegVal  |= MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_MASK;
+    /* The other bits don't matter in this case */
+    break;
+  case MV_PORT_DUPLEX_HALF:
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_MASK;
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_SET_FULL_DX_MASK;
+    break;
+  case MV_PORT_DUPLEX_FULL:
+    RegVal &= ~MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_MASK;
+    RegVal |= MVPP2_PORT_AUTO_NEG_CFG_SET_FULL_DX_MASK;
+    break;
+  default:
+    return MVPP2_EINVAL;
+  }
+
+  Mvpp2GmacWrite (Port, MVPP2_PORT_AUTO_NEG_CFG_REG, RegVal);
+
+  return 0;
+}
+
+VOID
+Mvpp2AxiConfig (
+  IN MVPP2_SHARED *Priv
+  )
+{
+  /* Config AXI Read&Write Normal and Soop mode  */
+  Mvpp2Write (Priv, MVPP22_AXI_BM_WR_ATTR_REG, MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT);
+  Mvpp2Write (Priv, MVPP22_AXI_BM_RD_ATTR_REG, MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT);
+  Mvpp2Write (Priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT);
+  Mvpp2Write (Priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT);
+  Mvpp2Write (Priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT);
+  Mvpp2Write (Priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT);
+  Mvpp2Write (Priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT);
+  Mvpp2Write (Priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT);
+}
+
+/* Cleanup Tx Ports */
+VOID
+Mvpp2TxpClean (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Txp,
+  IN MVPP2_TX_QUEUE *Txq
+  )
+{
+  INT32 Delay, Pending;
+  UINT32 RegVal;
+
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_NUM_REG, Txq->Id);
+  RegVal = Mvpp2Read (Port->Priv, MVPP2_TXQ_PREF_BUF_REG);
+  RegVal |= MVPP2_TXQ_DRAIN_EN_MASK;
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_PREF_BUF_REG, RegVal);
+
+  /*
+   * The Queue has been stopped so wait for all packets
+   * to be transmitted.
+   */
+  Delay = 0;
+  do {
+    if (Delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
+      Mvpp2Printf ("Port %d: cleaning Queue %d timed out\n", Port->Id, Txq->LogId);
+      break;
+    }
+    Mvpp2Mdelay (1);
+    Delay++;
+
+    Pending = Mvpp2TxqPendDescNumGet (Port, Txq);
+  } while (Pending);
+
+  RegVal &= ~MVPP2_TXQ_DRAIN_EN_MASK;
+  Mvpp2Write (Port->Priv, MVPP2_TXQ_PREF_BUF_REG, RegVal);
+}
+
+/* Cleanup all Tx Queues */
+VOID
+Mvpp2CleanupTxqs (
+  IN PP2DXE_PORT *Port
+  )
+{
+  MVPP2_TX_QUEUE *Txq;
+  INT32 Txp, Queue;
+  UINT32 RegVal;
+
+  RegVal = Mvpp2Read (Port->Priv, MVPP2_TX_PORT_FLUSH_REG);
+
+  /* Reset Tx Ports and delete Tx Queues */
+  for (Txp = 0; Txp < Port->TxpNum; Txp++) {
+    RegVal |= MVPP2_TX_PORT_FLUSH_MASK (Port->Id);
+    Mvpp2Write (Port->Priv, MVPP2_TX_PORT_FLUSH_REG, RegVal);
+
+    for (Queue = 0; Queue < TxqNumber; Queue++) {
+      Txq = &Port->Txqs[Txp * TxqNumber + Queue];
+      Mvpp2TxpClean (Port, Txp, Txq);
+      Mvpp2TxqHwDeinit (Port, Txq);
+    }
+
+    RegVal &= ~MVPP2_TX_PORT_FLUSH_MASK (Port->Id);
+    Mvpp2Write (Port->Priv, MVPP2_TX_PORT_FLUSH_REG, RegVal);
+  }
+}
+
+/* Cleanup all Rx Queues */
+VOID
+Mvpp2CleanupRxqs (
+  IN PP2DXE_PORT *Port
+  )
+{
+  INT32 Queue;
+
+  for (Queue = 0; Queue < RxqNumber; Queue++) {
+    Mvpp2RxqHwDeinit (Port, &Port->Rxqs[Queue]);
+  }
+}
diff --git a/Drivers/Net/Pp2Dxe/Mvpp2Lib.h b/Drivers/Net/Pp2Dxe/Mvpp2Lib.h
new file mode 100644
index 0000000..d7d5dcb
--- /dev/null
+++ b/Drivers/Net/Pp2Dxe/Mvpp2Lib.h
@@ -0,0 +1,726 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MVPP2_LIB_H__
+#define __MVPP2_LIB_H__
+
+#include "Mvpp2LibHw.h"
+#include "Pp2Dxe.h"
+
+/* number of RXQs used by single Port */
+STATIC INT32 RxqNumber = 1;
+/* number of TXQs used by single Port */
+STATIC INT32 TxqNumber = 1;
+
+VOID
+Mvpp2PrsMacPromiscSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN BOOLEAN Add
+  );
+
+VOID
+Mvpp2PrsMacMultiSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN INT32 Index,
+  IN BOOLEAN Add
+  );
+
+INT32
+Mvpp2PrsDefaultInit (
+  IN MVPP2_SHARED *Priv
+  );
+
+INT32
+Mvpp2PrsMacDaAccept (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN const UINT8 *Da,
+  IN BOOLEAN Add
+  );
+
+VOID
+Mvpp2PrsMcastDelAll (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId
+  );
+
+INT32
+Mvpp2PrsTagModeSet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 PortId,
+  IN INT32 type
+  );
+
+INT32
+Mvpp2PrsDefFlow (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2ClsInit (
+  IN MVPP2_SHARED *Priv
+  );
+
+VOID
+Mvpp2ClsPortConfig (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2ClsOversizeRxqSet (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2BmPoolHwCreate (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_BMS_POOL *BmPool,
+  IN INT32 Size
+  );
+
+VOID
+Mvpp2BmPoolBufsizeSet (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_BMS_POOL *BmPool,
+  IN INT32 BufSize
+  );
+
+VOID
+Mvpp2BmStop (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Pool
+  );
+
+VOID
+Mvpp2BmIrqClear (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Pool
+  );
+
+VOID
+Mvpp2RxqLongPoolSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Lrxq,
+  IN INT32 LongPool
+  );
+
+VOID
+Mvpp2RxqShortPoolSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Lrxq,
+  IN INT32 ShortPool
+  );
+
+VOID
+Mvpp2BmPoolMcPut (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Pool,
+  IN UINT32 BufPhysAddr,
+  IN UINT32 BufVirtAddr,
+  IN INT32 McId
+  );
+
+VOID
+Mvpp2PoolRefill (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Bm,
+  IN UINT32 PhysAddr,
+  IN UINT32 Cookie
+  );
+
+INTN
+Mvpp2BmPoolCtrl (
+  IN MVPP2_SHARED *Priv,
+  IN INTN Pool,
+  IN enum Mvpp2Command cmd
+  );
+
+VOID
+Mvpp2InterruptsMask (
+  IN VOID *arg
+  );
+
+VOID
+Mvpp2InterruptsUnmask (
+  IN VOID *arg
+  );
+
+VOID
+Mvpp2PortEnable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2PortDisable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2DefaultsSet (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2IngressEnable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2IngressDisable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2EgressEnable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2EgressDisable (
+  IN PP2DXE_PORT *Port
+  );
+
+UINT32
+Mvpp2BmCookieBuild (
+  IN MVPP2_RX_DESC *RxDesc,
+  IN INT32 Cpu
+  );
+
+INT32
+Mvpp2TxqDrainSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Txq,
+  IN BOOLEAN En
+  );
+
+INT32
+Mvpp2TxqPendDescNumGet (
+  IN PP2DXE_PORT *Port,
+  IN MVPP2_TX_QUEUE *Txq
+  );
+
+UINT32
+Mvpp2AggrTxqPendDescNumGet (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Cpu
+  );
+
+MVPP2_TX_DESC *
+Mvpp2TxqNextDescGet (
+  MVPP2_TX_QUEUE *Txq
+  );
+
+VOID
+Mvpp2AggrTxqPendDescAdd (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Pending
+  );
+
+INT32
+Mvpp2AggrDescNumCheck (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_TX_QUEUE *AggrTxq,
+  IN INT32 Num,
+  IN INT32 Cpu
+  );
+
+INT32
+Mvpp2TxqAllocReservedDesc (
+  IN MVPP2_SHARED *Priv,
+  IN MVPP2_TX_QUEUE *Txq,
+  IN INT32 Num
+  );
+
+VOID
+Mvpp2TxqDescPut (
+  IN MVPP2_TX_QUEUE *Txq
+  );
+
+UINT32
+Mvpp2TxqDescCsum (
+  IN INT32 L3Offs,
+  IN INT32 L3Proto,
+  IN INT32 IpHdrLen,
+  IN INT32 L4Proto
+  );
+
+VOID
+Mvpp2TxqSentCounterClear (
+  IN OUT VOID *arg
+  );
+
+VOID
+Mvpp2GmacMaxRxSizeSet (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2TxpMaxTxSizeSet (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2RxPktsCoalSet (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq,
+  IN UINT32 Pkts
+  );
+
+VOID
+Mvpp2RxTimeCoalSet (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq,
+  IN UINT32 Usec
+  );
+
+VOID
+Mvpp2AggrTxqHwInit (
+  IN OUT MVPP2_TX_QUEUE *AggrTxq,
+  IN INT32 DescNum,
+  IN INT32 Cpu,
+  IN MVPP2_SHARED *Priv
+  );
+
+VOID
+Mvpp2RxqHwInit (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq
+  );
+
+VOID
+Mvpp2RxqDropPkts (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq,
+  IN INT32 Cpu
+  );
+
+VOID
+Mvpp2TxqHwInit (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_TX_QUEUE *Txq
+  );
+
+VOID
+Mvpp2TxqHwDeinit (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_TX_QUEUE *Txq
+  );
+
+VOID
+Mvpp2PortPowerUp (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2RxFifoInit (
+  IN MVPP2_SHARED *Priv
+  );
+
+VOID
+Mvpp2RxqHwDeinit (
+  IN PP2DXE_PORT *Port,
+  IN OUT MVPP2_RX_QUEUE *Rxq
+  );
+
+INT32
+MvGop110NetcInit (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 NetCompConfig,
+  IN enum MvNetcPhase phase
+  );
+
+UINT32
+MvpPp2xGop110NetcCfgCreate (
+  IN PP2DXE_PORT *Port
+  );
+
+INT32
+MvGop110PortInit (
+  IN PP2DXE_PORT *Port
+  );
+
+INT32
+MvGop110GmacReset (
+  IN PP2DXE_PORT *Port,
+  IN enum MvReset ResetCmd
+  );
+
+INT32
+MvGop110GpcsModeCfg (
+  IN PP2DXE_PORT *Port,
+  BOOLEAN En
+  );
+
+INT32
+MvGop110BypassClkCfg (
+  IN PP2DXE_PORT *Port,
+  IN BOOLEAN En
+  );
+
+INT32
+MvGop110GpcsReset (
+  IN PP2DXE_PORT *Port,
+  IN enum MvReset ResetCmd
+  );
+
+VOID
+MvGop110Xlg2GigMacCfg (
+  IN PP2DXE_PORT *Port
+  );
+
+INT32
+MvGop110GmacModeCfg (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110GmacRgmiiCfg (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110GmacSgmii25Cfg (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110GmacSgmiiCfg (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110GmacQsgmiiCfg (
+  IN PP2DXE_PORT *Port
+  );
+
+INT32
+Mvpp2SmiPhyAddrCfg (
+  IN PP2DXE_PORT *Port,
+  IN INT32 PortId,
+  IN INT32 Addr
+  );
+
+BOOLEAN
+MvGop110PortIsLinkUp (
+  IN PP2DXE_PORT *Port
+  );
+
+BOOLEAN
+MvGop110GmacLinkStatusGet (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110PortDisable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110PortEnable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110GmacPortEnable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110GmacPortDisable (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGop110GmacPortLinkEventMask (
+  IN PP2DXE_PORT *Port
+  );
+
+INT32
+MvGop110PortEventsMask (
+  IN PP2DXE_PORT *Port
+  );
+
+INT32
+MvGop110FlCfg (
+  IN PP2DXE_PORT *Port
+  );
+
+INT32
+MvGop110SpeedDuplexSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Speed,
+  IN enum MvPortDuplex Duplex
+  );
+
+INT32
+MvGop110GmacSpeedDuplexSet (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Speed,
+  IN enum MvPortDuplex Duplex
+  );
+
+VOID
+Mvpp2AxiConfig (
+  IN MVPP2_SHARED *Priv
+  );
+
+VOID
+Mvpp2TxpClean (
+  IN PP2DXE_PORT *Port,
+  IN INT32 Txp,
+  IN MVPP2_TX_QUEUE *Txq
+  );
+
+VOID
+Mvpp2CleanupTxqs (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+Mvpp2CleanupRxqs (
+  IN PP2DXE_PORT *Port
+  );
+
+/* Get number of physical egress Port */
+STATIC
+inline
+INT32
+Mvpp2EgressPort (
+  IN PP2DXE_PORT *Port
+  )
+{
+  return MVPP2_MAX_TCONT + Port->Id;
+}
+
+/* Get number of physical TXQ */
+STATIC
+inline
+INT32
+Mvpp2TxqPhys (
+  IN INT32 PortId,
+  IN INT32 Txq
+  )
+{
+  return (MVPP2_MAX_TCONT + PortId) * MVPP2_MAX_TXQ + Txq;
+}
+
+/* Set Pool number in a BM Cookie */
+STATIC
+inline
+UINT32
+Mvpp2BmCookiePoolSet (
+  IN UINT32 Cookie,
+  IN INT32 Pool
+  )
+{
+  UINT32 Bm;
+
+  Bm = Cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
+  Bm |= ((Pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
+
+  return Bm;
+}
+
+/* Get Pool number from a BM Cookie */
+STATIC
+inline
+INT32
+Mvpp2BmCookiePoolGet (
+  IN UINT32 Cookie
+  )
+{
+  return (Cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
+}
+
+/* Release buffer to BM */
+STATIC
+inline
+VOID
+Mvpp2BmPoolPut (
+  IN MVPP2_SHARED *Priv,
+  IN INT32 Pool,
+  IN UINT64 BufPhysAddr,
+  IN UINT64 BufVirtAddr
+  )
+{
+  UINT32 Val = 0;
+
+  Val = (Upper32Bits(BufVirtAddr) & MVPP22_ADDR_HIGH_MASK) << MVPP22_BM_VIRT_HIGH_RLS_OFFST;
+  Val |= (Upper32Bits(BufPhysAddr) & MVPP22_ADDR_HIGH_MASK) << MVPP22_BM_PHY_HIGH_RLS_OFFSET;
+  Mvpp2Write(Priv, MVPP22_BM_PHY_VIRT_HIGH_RLS_REG, Val);
+  Mvpp2Write(Priv, MVPP2_BM_VIRT_RLS_REG, (UINT32)BufVirtAddr);
+  Mvpp2Write(Priv, MVPP2_BM_PHY_RLS_REG(Pool), (UINT32)BufPhysAddr);
+}
+
+STATIC
+inline
+VOID
+Mvpp2InterruptsEnable (
+  IN PP2DXE_PORT *Port,
+  IN INT32 CpuMask
+  )
+{
+  Mvpp2Write(Port->Priv, MVPP2_ISR_ENABLE_REG(Port->Id), MVPP2_ISR_ENABLE_INTERRUPT(CpuMask));
+}
+
+STATIC
+inline
+VOID
+Mvpp2InterruptsDisable (
+  IN PP2DXE_PORT *Port,
+  IN INT32 CpuMask
+  )
+{
+  Mvpp2Write(Port->Priv, MVPP2_ISR_ENABLE_REG(Port->Id), MVPP2_ISR_DISABLE_INTERRUPT(CpuMask));
+}
+
+/* Get number of Rx descriptors occupied by received packets */
+STATIC
+inline
+INT32
+Mvpp2RxqReceived (
+  IN PP2DXE_PORT *Port,
+  IN INT32 RxqId
+  )
+{
+  UINT32 Val = Mvpp2Read(Port->Priv, MVPP2_RXQ_STATUS_REG(RxqId));
+
+  return Val & MVPP2_RXQ_OCCUPIED_MASK;
+}
+
+/*
+ * Update Rx Queue status with the number of occupied and available
+ * Rx descriptor slots.
+ */
+STATIC
+inline
+VOID
+Mvpp2RxqStatusUpdate (
+  IN PP2DXE_PORT *Port,
+  IN INT32 RxqId,
+  IN INT32 UsedCount,
+  IN INT32 FreeCount
+  )
+{
+  /*
+   * Decrement the number of used descriptors and increment count
+   * increment the number of free descriptors.
+   */
+  UINT32 Val = UsedCount | (FreeCount << MVPP2_RXQ_NUM_NEW_OFFSET);
+
+  Mvpp2Write(Port->Priv, MVPP2_RXQ_STATUS_UPDATE_REG(RxqId), Val);
+}
+
+/* Get pointer to next RX descriptor to be processed by SW */
+STATIC
+inline
+MVPP2_RX_DESC *
+Mvpp2RxqNextDescGet (
+  IN MVPP2_RX_QUEUE *Rxq
+  )
+{
+  INT32 RxDesc = Rxq->NextDescToProc;
+
+  Rxq->NextDescToProc = MVPP2_QUEUE_NEXT_DESC(Rxq, RxDesc);
+  Mvpp2Prefetch(Rxq->Descs + Rxq->NextDescToProc);
+  return Rxq->Descs + RxDesc;
+}
+
+/*
+ * Get number of sent descriptors and decrement counter.
+ * The number of sent descriptors is returned.
+ * Per-CPU access
+ */
+STATIC
+inline
+INT32
+Mvpp2TxqSentDescProc (
+  IN PP2DXE_PORT *Port,
+  IN MVPP2_TX_QUEUE *Txq
+  )
+{
+  UINT32 Val;
+
+  /* Reading status reg resets transmitted descriptor counter */
+#ifdef MVPP2V1
+  Val = Mvpp2Read(Port->Priv, MVPP2_TXQ_SENT_REG(Txq->Id));
+#else
+  Val = Mvpp2Read(Port->Priv, MVPP22_TXQ_SENT_REG(Txq->Id));
+#endif
+
+  return (Val & MVPP2_TRANSMITTED_COUNT_MASK) >> MVPP2_TRANSMITTED_COUNT_OFFSET;
+}
+
+STATIC
+inline
+MVPP2_RX_QUEUE *
+Mvpp2GetRxQueue (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Cause
+  )
+{
+  INT32 Queue = Mvpp2Fls(Cause) - 1;
+
+  return &Port->Rxqs[Queue];
+}
+
+STATIC
+inline
+MVPP2_TX_QUEUE *
+Mvpp2GetTxQueue (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Cause
+  )
+{
+  INT32 Queue = Mvpp2Fls(Cause) - 1;
+
+  return &Port->Txqs[Queue];
+}
+
+STATIC
+inline
+void
+Mvpp2x2TxdescPhysAddrSet (
+  IN DmaAddrT PhysAddr,
+  IN MVPP2_TX_DESC *TxDesc
+  )
+{
+  UINT64 *BufPhysAddrP = &TxDesc->BufPhysAddrHwCmd2;
+
+  *BufPhysAddrP &= ~(MVPP22_ADDR_MASK);
+  *BufPhysAddrP |= PhysAddr & MVPP22_ADDR_MASK;
+}
+#endif /* __MVPP2_LIB_H__ */
diff --git a/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
new file mode 100644
index 0000000..f283db2
--- /dev/null
+++ b/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
@@ -0,0 +1,1968 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MVPP2_LIB_HW__
+#define __MVPP2_LIB_HW__
+
+#ifndef BIT
+#define BIT(nr)         (1 << (nr))
+#endif
+
+/* RX Fifo Registers */
+#define MVPP2_RX_DATA_FIFO_SIZE_REG(port)                 (0x00 + 4 * (port))
+#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port)                 (0x20 + 4 * (port))
+#define MVPP2_RX_MIN_PKT_SIZE_REG                         0x60
+#define MVPP2_RX_FIFO_INIT_REG                            0x64
+
+/* RX DMA Top Registers */
+#define MVPP2_RX_CTRL_REG(port)                           (0x140 + 4 * (port))
+#define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s)                  (((s) & 0xfff) << 16)
+#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK                 BIT(31)
+#define MVPP2_POOL_BUF_SIZE_REG(pool)                     (0x180 + 4 * (pool))
+#define MVPP2_POOL_BUF_SIZE_OFFSET                        5
+#define MVPP2_RXQ_CONFIG_REG(rxq)                         (0x800 + 4 * (rxq))
+#define MVPP2_SNOOP_PKT_SIZE_MASK                         0x1ff
+#define MVPP2_SNOOP_BUF_HDR_MASK                          BIT(9)
+#define MVPP2_RXQ_POOL_SHORT_OFFS                         20
+#define MVPP2_RXQ_POOL_SHORT_MASK                         0x700000
+#define MVPP2_RXQ_POOL_LONG_OFFS                          24
+#define MVPP2_RXQ_POOL_LONG_MASK                          0x7000000
+#define MVPP2_RXQ_PACKET_OFFSET_OFFS                      28
+#define MVPP2_RXQ_PACKET_OFFSET_MASK                      0x70000000
+#define MVPP2_RXQ_DISABLE_MASK                            BIT(31)
+
+/* Parser Registers */
+#define MVPP2_PRS_INIT_LOOKUP_REG                         0x1000
+#define MVPP2_PRS_PORT_LU_MAX                             0xf
+#define MVPP2_PRS_PORT_LU_MASK(port)                      (0xff << ((port) * 4))
+#define MVPP2_PRS_PORT_LU_VAL(port, val)                  ((val) << ((port) * 4))
+#define MVPP2_PRS_INIT_OFFS_REG(port)                     (0x1004 + ((port) & 4))
+#define MVPP2_PRS_INIT_OFF_MASK(port)                     (0x3f << (((port) % 4) * 8))
+#define MVPP2_PRS_INIT_OFF_VAL(port, val)                 ((val) << (((port) % 4) * 8))
+#define MVPP2_PRS_MAX_LOOP_REG(port)                      (0x100c + ((port) & 4))
+#define MVPP2_PRS_MAX_LOOP_MASK(port)                     (0xff << (((port) % 4) * 8))
+#define MVPP2_PRS_MAX_LOOP_VAL(port, val)                 ((val) << (((port) % 4) * 8))
+#define MVPP2_PRS_TCAM_IDX_REG                            0x1100
+#define MVPP2_PRS_TCAM_DATA_REG(idx)                      (0x1104 + (idx) * 4)
+#define MVPP2_PRS_TCAM_INV_MASK                           BIT(31)
+#define MVPP2_PRS_SRAM_IDX_REG                            0x1200
+#define MVPP2_PRS_SRAM_DATA_REG(idx)                      (0x1204 + (idx) * 4)
+#define MVPP2_PRS_TCAM_CTRL_REG                           0x1230
+#define MVPP2_PRS_TCAM_EN_MASK                            BIT(0)
+
+/* Classifier Registers */
+#define MVPP2_CLS_MODE_REG                                0x1800
+#define MVPP2_CLS_MODE_ACTIVE_MASK                        BIT(0)
+#define MVPP2_CLS_PORT_WAY_REG                            0x1810
+#define MVPP2_CLS_PORT_WAY_MASK(port)                     (1 << (port))
+#define MVPP2_CLS_LKP_INDEX_REG                           0x1814
+#define MVPP2_CLS_LKP_INDEX_WAY_OFFS                      6
+#define MVPP2_CLS_LKP_TBL_REG                             0x1818
+#define MVPP2_CLS_LKP_TBL_RXQ_MASK                        0xff
+#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK                  BIT(25)
+#define MVPP2_CLS_FLOW_INDEX_REG                          0x1820
+#define MVPP2_CLS_FLOW_TBL0_REG                           0x1824
+#define MVPP2_CLS_FLOW_TBL1_REG                           0x1828
+#define MVPP2_CLS_FLOW_TBL2_REG                           0x182c
+#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port)              (0x1980 + ((port) * 4))
+#define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS                   3
+#define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK                   0x7
+#define MVPP2_CLS_SWFWD_P2HQ_REG(port)                    (0x19b0 + ((port) * 4))
+#define MVPP2_CLS_SWFWD_PCTRL_REG                         0x19d0
+#define MVPP2_CLS_SWFWD_PCTRL_MASK(port)                  (1 << (port))
+
+/* Descriptor Manager Top Registers */
+#define MVPP2_RXQ_NUM_REG                                 0x2040
+#define MVPP2_RXQ_DESC_ADDR_REG                           0x2044
+#define MVPP2_RXQ_DESC_SIZE_REG                           0x2048
+#define MVPP2_RXQ_DESC_SIZE_MASK                          0x3ff0
+#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq)                  (0x3000 + 4 * (rxq))
+#define MVPP2_RXQ_NUM_PROCESSED_OFFSET                    0
+#define MVPP2_RXQ_NUM_NEW_OFFSET                          16
+#define MVPP2_RXQ_STATUS_REG(rxq)                         (0x3400 + 4 * (rxq))
+#define MVPP2_RXQ_OCCUPIED_MASK                           0x3fff
+#define MVPP2_RXQ_NON_OCCUPIED_OFFSET                     16
+#define MVPP2_RXQ_NON_OCCUPIED_MASK                       0x3fff0000
+#define MVPP2_RXQ_THRESH_REG                              0x204c
+#define MVPP2_OCCUPIED_THRESH_OFFSET                      0
+#define MVPP2_OCCUPIED_THRESH_MASK                        0x3fff
+#define MVPP2_RXQ_INDEX_REG                               0x2050
+#define MVPP2_TXQ_NUM_REG                                 0x2080
+#define MVPP2_TXQ_DESC_ADDR_REG                           0x2084
+#define MVPP22_TXQ_DESC_ADDR_HIGH_REG                     0x20a8
+#define MVPP22_TXQ_DESC_ADDR_HIGH_MASK                    0xff
+#define MVPP2_TXQ_DESC_SIZE_REG                           0x2088
+#define MVPP2_TXQ_DESC_SIZE_MASK                          0x3ff0
+#define MVPP2_AGGR_TXQ_UPDATE_REG                         0x2090
+#define MVPP2_TXQ_THRESH_REG                              0x2094
+#define MVPP2_TRANSMITTED_THRESH_OFFSET                   16
+#define MVPP2_TRANSMITTED_THRESH_MASK                     0x3fff0000
+#define MVPP2_TXQ_INDEX_REG                               0x2098
+#define MVPP2_TXQ_PREF_BUF_REG                            0x209c
+#define MVPP2_PREF_BUF_PTR(desc)                          ((desc) & 0xfff)
+#define MVPP2_PREF_BUF_SIZE_4                             (BIT(12) | BIT(13))
+#define MVPP2_PREF_BUF_SIZE_16                            (BIT(12) | BIT(14))
+#define MVPP2_PREF_BUF_THRESH(val)                        ((val) << 17)
+#define MVPP2_TXQ_DRAIN_EN_MASK                           BIT(31)
+#define MVPP2_TXQ_PENDING_REG                             0x20a0
+#define MVPP2_TXQ_PENDING_MASK                            0x3fff
+#define MVPP2_TXQ_INT_STATUS_REG                          0x20a4
+#define MVPP2_TXQ_SENT_REG(txq)                           (0x3c00 + 4 * (txq))
+#define MVPP22_TXQ_SENT_REG(txq)                          (0x3e00 + 4 * (txq-128))
+#define MVPP2_TRANSMITTED_COUNT_OFFSET                    16
+#define MVPP2_TRANSMITTED_COUNT_MASK                      0x3fff0000
+#define MVPP2_TXQ_RSVD_REQ_REG                            0x20b0
+#define MVPP2_TXQ_RSVD_REQ_Q_OFFSET                       16
+#define MVPP2_TXQ_RSVD_RSLT_REG                           0x20b4
+#define MVPP2_TXQ_RSVD_RSLT_MASK                          0x3fff
+#define MVPP2_TXQ_RSVD_CLR_REG                            0x20b8
+#define MVPP2_TXQ_RSVD_CLR_OFFSET                         16
+#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu)                 (0x2100 + 4 * (cpu))
+#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu)                 (0x2140 + 4 * (cpu))
+#define MVPP2_AGGR_TXQ_DESC_SIZE_MASK                     0x3ff0
+#define MVPP2_AGGR_TXQ_STATUS_REG(cpu)                    (0x2180 + 4 * (cpu))
+#define MVPP2_AGGR_TXQ_PENDING_MASK                       0x3fff
+#define MVPP2_AGGR_TXQ_INDEX_REG(cpu)                     (0x21c0 + 4 * (cpu))
+
+/* MBUS bridge registers */
+#define MVPP2_WIN_BASE(w)                                 (0x4000 + ((w) << 2))
+#define MVPP2_WIN_SIZE(w)                                 (0x4020 + ((w) << 2))
+#define MVPP2_WIN_REMAP(w)                                (0x4040 + ((w) << 2))
+#define MVPP2_BASE_ADDR_ENABLE                            0x4060
+
+/* Interrupt Cause and Mask registers */
+#define MVPP2_ISR_RX_THRESHOLD_REG(rxq)                   (0x5200 + 4 * (rxq))
+#define MVPP2_ISR_RXQ_GROUP_REG(rxq)                      (0x5400 + 4 * (rxq))
+#define MVPP2_ISR_ENABLE_REG(port)                        (0x5420 + 4 * (port))
+#define MVPP2_ISR_ENABLE_INTERRUPT(mask)                  ((mask) & 0xffff)
+#define MVPP2_ISR_DISABLE_INTERRUPT(mask)                 (((mask) << 16) & 0xffff0000)
+#define MVPP2_ISR_RX_TX_CAUSE_REG(port)                   (0x5480 + 4 * (port))
+#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK               0xffff
+#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK               0xff0000
+#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK                  BIT(24)
+#define MVPP2_CAUSE_FCS_ERR_MASK                          BIT(25)
+#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK                 BIT(26)
+#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK                 BIT(29)
+#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK                 BIT(30)
+#define MVPP2_CAUSE_MISC_SUM_MASK                         BIT(31)
+#define MVPP2_ISR_RX_TX_MASK_REG(port)                    (0x54a0 + 4 * (port))
+#define MVPP2_ISR_PON_RX_TX_MASK_REG                      0x54bc
+#define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK           0xffff
+#define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK           0x3fc00000
+#define MVPP2_PON_CAUSE_MISC_SUM_MASK                     BIT(31)
+#define MVPP2_ISR_MISC_CAUSE_REG                          0x55b0
+
+/* Buffer Manager registers */
+#define MVPP2_BM_POOL_BASE_REG(pool)                      (0x6000 + ((pool) * 4))
+#define MVPP2_BM_POOL_BASE_ADDR_MASK                      0xfffff80
+#define MVPP2_BM_POOL_SIZE_REG(pool)                      (0x6040 + ((pool) * 4))
+#define MVPP2_BM_POOL_SIZE_MASK                           0xfff0
+#define MVPP2_BM_POOL_READ_PTR_REG(pool)                  (0x6080 + ((pool) * 4))
+#define MVPP2_BM_POOL_GET_READ_PTR_MASK                   0xfff0
+#define MVPP2_BM_POOL_PTRS_NUM_REG(pool)                  (0x60c0 + ((pool) * 4))
+#define MVPP2_BM_POOL_PTRS_NUM_MASK                       0xfff0
+#define MVPP2_BM_BPPI_READ_PTR_REG(pool)                  (0x6100 + ((pool) * 4))
+#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool)                  (0x6140 + ((pool) * 4))
+#define MVPP2_BM_BPPI_PTR_NUM_MASK                        0x7ff
+#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK                  BIT(16)
+#define MVPP2_BM_POOL_CTRL_REG(pool)                      (0x6200 + ((pool) * 4))
+#define MVPP2_BM_START_MASK                               BIT(0)
+#define MVPP2_BM_STOP_MASK                                BIT(1)
+#define MVPP2_BM_STATE_MASK                               BIT(4)
+#define MVPP2_BM_LOW_THRESH_OFFS                          8
+#define MVPP2_BM_LOW_THRESH_MASK                          0x7f00
+#define MVPP2_BM_LOW_THRESH_VALUE(val)                    ((val) << MVPP2_BM_LOW_THRESH_OFFS)
+#define MVPP2_BM_HIGH_THRESH_OFFS                         16
+#define MVPP2_BM_HIGH_THRESH_MASK                         0x7f0000
+#define MVPP2_BM_HIGH_THRESH_VALUE(val)                   ((val) << MVPP2_BM_HIGH_THRESH_OFFS)
+#define MVPP2_BM_INTR_CAUSE_REG(pool)                     (0x6240 + ((pool) * 4))
+#define MVPP2_BM_RELEASED_DELAY_MASK                      BIT(0)
+#define MVPP2_BM_ALLOC_FAILED_MASK                        BIT(1)
+#define MVPP2_BM_BPPE_EMPTY_MASK                          BIT(2)
+#define MVPP2_BM_BPPE_FULL_MASK                           BIT(3)
+#define MVPP2_BM_AVAILABLE_BP_LOW_MASK                    BIT(4)
+#define MVPP2_BM_INTR_MASK_REG(pool)                      (0x6280 + ((pool) * 4))
+#define MVPP2_BM_PHY_ALLOC_REG(pool)                      (0x6400 + ((pool) * 4))
+#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK                     BIT(0)
+#define MVPP2_BM_VIRT_ALLOC_REG                           0x6440
+#define MVPP2_BM_PHY_RLS_REG(pool)                        (0x6480 + ((pool) * 4))
+#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK                     BIT(0)
+#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK                     BIT(1)
+#define MVPP2_BM_PHY_RLS_GRNTD_MASK                       BIT(2)
+#define MVPP2_BM_VIRT_RLS_REG                             0x64c0
+#define MVPP2_BM_MC_RLS_REG                               0x64c4
+#define MVPP2_BM_MC_ID_MASK                               0xfff
+#define MVPP2_BM_FORCE_RELEASE_MASK                       BIT(12)
+
+#define MVPP22_BM_PHY_VIRT_HIGH_ALLOC_REG                 0x6444
+#define MVPP22_BM_PHY_HIGH_ALLOC_OFFSET                   0
+#define MVPP22_BM_VIRT_HIGH_ALLOC_OFFSET                  8
+#define MVPP22_BM_VIRT_HIGH_ALLOC_MASK                    0xff00
+
+#define MVPP22_BM_PHY_VIRT_HIGH_RLS_REG                   0x64c4
+
+#define MVPP22_BM_PHY_HIGH_RLS_OFFSET                     0
+#define MVPP22_BM_VIRT_HIGH_RLS_OFFST                     8
+
+#define MVPP22_BM_POOL_BASE_HIGH_REG                      0x6310
+#define MVPP22_BM_POOL_BASE_HIGH_MASK                     0xff
+#define MVPP2_BM_PRIO_CTRL_REG                            0x6800
+
+/* TX Scheduler registers */
+#define MVPP2_TXP_SCHED_PORT_INDEX_REG                    0x8000
+#define MVPP2_TXP_SCHED_Q_CMD_REG                         0x8004
+#define MVPP2_TXP_SCHED_ENQ_MASK                          0xff
+#define MVPP2_TXP_SCHED_DISQ_OFFSET                       8
+#define MVPP2_TXP_SCHED_CMD_1_REG                         0x8010
+#define MVPP2_TXP_SCHED_PERIOD_REG                        0x8018
+#define MVPP2_TXP_SCHED_MTU_REG                           0x801c
+#define MVPP2_TXP_MTU_MAX                                 0x7FFFF
+#define MVPP2_TXP_SCHED_REFILL_REG                        0x8020
+#define MVPP2_TXP_REFILL_TOKENS_ALL_MASK                  0x7ffff
+#define MVPP2_TXP_REFILL_PERIOD_ALL_MASK                  0x3ff00000
+#define MVPP2_TXP_REFILL_PERIOD_MASK(v)                   ((v) << 20)
+#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG                    0x8024
+#define MVPP2_TXP_TOKEN_SIZE_MAX                          0xffffffff
+#define MVPP2_TXQ_SCHED_REFILL_REG(q)                     (0x8040 + ((q) << 2))
+#define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK                  0x7ffff
+#define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK                  0x3ff00000
+#define MVPP2_TXQ_REFILL_PERIOD_MASK(v)                   ((v) << 20)
+#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q)                 (0x8060 + ((q) << 2))
+#define MVPP2_TXQ_TOKEN_SIZE_MAX                          0x7fffffff
+#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q)                 (0x8080 + ((q) << 2))
+#define MVPP2_TXQ_TOKEN_CNTR_MAX                          0xffffffff
+
+/* TX general registers */
+#define MVPP2_TX_SNOOP_REG                                0x8800
+#define MVPP2_TX_PORT_FLUSH_REG                           0x8810
+#define MVPP2_TX_PORT_FLUSH_MASK(port)                    (1 << (port))
+
+/* LMS registers */
+#define MVPP2_SRC_ADDR_MIDDLE                             0x24
+#define MVPP2_SRC_ADDR_HIGH                               0x28
+#define MVPP2_PHY_AN_CFG0_REG                             0x34
+#define MVPP2_PHY_AN_STOP_SMI0_MASK                       BIT(7)
+#define MVPP2_MIB_COUNTERS_BASE(port)                     (0x1000 + ((port) >> 1) * 0x400 + (port) * 0x400)
+#define MVPP2_MIB_LATE_COLLISION                          0x7c
+#define MVPP2_ISR_SUM_MASK_REG                            0x220c
+#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG                0x305c
+#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT                     0x27
+
+/* Per-port registers */
+#define MVPP2_GMAC_CTRL_0_REG                             0x0
+#define MVPP2_GMAC_PORT_EN_MASK                           BIT(0)
+#define MVPP2_GMAC_MAX_RX_SIZE_OFFS                       2
+#define MVPP2_GMAC_MAX_RX_SIZE_MASK                       0x7ffc
+#define MVPP2_GMAC_MIB_CNTR_EN_MASK                       BIT(15)
+#define MVPP2_GMAC_CTRL_1_REG                             0x4
+#define MVPP2_GMAC_PERIODIC_XON_EN_MASK                   BIT(1)
+#define MVPP2_GMAC_GMII_LB_EN_MASK                        BIT(5)
+#define MVPP2_GMAC_PCS_LB_EN_BIT                          6
+#define MVPP2_GMAC_PCS_LB_EN_MASK                         BIT(6)
+#define MVPP2_GMAC_SA_LOW_OFFS                            7
+#define MVPP2_GMAC_CTRL_2_REG                             0x8
+#define MVPP2_GMAC_INBAND_AN_MASK                         BIT(0)
+#define MVPP2_GMAC_PCS_ENABLE_MASK                        BIT(3)
+#define MVPP2_GMAC_PORT_RGMII_MASK                        BIT(4)
+#define MVPP2_GMAC_PORT_RESET_MASK                        BIT(6)
+#define MVPP2_GMAC_AUTONEG_CONFIG                         0xc
+#define MVPP2_GMAC_FORCE_LINK_DOWN                        BIT(0)
+#define MVPP2_GMAC_FORCE_LINK_PASS                        BIT(1)
+#define MVPP2_GMAC_CONFIG_MII_SPEED                       BIT(5)
+#define MVPP2_GMAC_CONFIG_GMII_SPEED                      BIT(6)
+#define MVPP2_GMAC_AN_SPEED_EN                            BIT(7)
+#define MVPP2_GMAC_FC_ADV_EN                              BIT(9)
+#define MVPP2_GMAC_CONFIG_FULL_DUPLEX                     BIT(12)
+#define MVPP2_GMAC_AN_DUPLEX_EN                           BIT(13)
+#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG                    0x1c
+#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS                    6
+#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK                0x1fc0
+#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v)                 (((v) << 6) & MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
+
+/* Port Interrupts */
+#define MV_GMAC_INTERRUPT_CAUSE_REG                       (0x0020)
+#define MV_GMAC_INTERRUPT_MASK_REG                        (0x0024)
+#define MV_GMAC_INTERRUPT_CAUSE_LINK_CHANGE_OFFS          1
+#define MV_GMAC_INTERRUPT_CAUSE_LINK_CHANGE_MASK          (0x1 << MV_GMAC_INTERRUPT_CAUSE_LINK_CHANGE_OFFS)
+
+/* Port Interrupt Summary */
+#define MV_GMAC_INTERRUPT_SUM_CAUSE_REG                   (0x00A0)
+#define MV_GMAC_INTERRUPT_SUM_MASK_REG                    (0x00A4)
+#define MV_GMAC_INTERRUPT_SUM_CAUSE_LINK_CHANGE_OFFS      1
+#define MV_GMAC_INTERRUPT_SUM_CAUSE_LINK_CHANGE_MASK      (0x1 << MV_GMAC_INTERRUPT_SUM_CAUSE_LINK_CHANGE_OFFS)
+
+/* Port Mac Control0 */
+#define MVPP2_PORT_CTRL0_REG                              (0x0000)
+#define MVPP2_PORT_CTRL0_PORTEN_OFFS    0
+#define MVPP2_PORT_CTRL0_PORTEN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL0_PORTEN_OFFS)
+
+#define MVPP2_PORT_CTRL0_PORTTYPE_OFFS    1
+#define MVPP2_PORT_CTRL0_PORTTYPE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL0_PORTTYPE_OFFS)
+
+#define MVPP2_PORT_CTRL0_FRAMESIZELIMIT_OFFS    2
+#define MVPP2_PORT_CTRL0_FRAMESIZELIMIT_MASK    \
+    (0x00001fff << MVPP2_PORT_CTRL0_FRAMESIZELIMIT_OFFS)
+
+#define MVPP2_PORT_CTRL0_COUNT_EN_OFFS    15
+#define MVPP2_PORT_CTRL0_COUNT_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL0_COUNT_EN_OFFS)
+
+/* Port Mac Control1 */
+#define MVPP2_PORT_CTRL1_REG                              (0x0004)
+#define MVPP2_PORT_CTRL1_EN_RX_CRC_CHECK_OFFS    0
+#define MVPP2_PORT_CTRL1_EN_RX_CRC_CHECK_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL1_EN_RX_CRC_CHECK_OFFS)
+
+#define MVPP2_PORT_CTRL1_EN_PERIODIC_FC_XON_OFFS    1
+#define MVPP2_PORT_CTRL1_EN_PERIODIC_FC_XON_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL1_EN_PERIODIC_FC_XON_OFFS)
+
+#define MVPP2_PORT_CTRL1_MGMII_MODE_OFFS    2
+#define MVPP2_PORT_CTRL1_MGMII_MODE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL1_MGMII_MODE_OFFS)
+
+#define MVPP2_PORT_CTRL1_PFC_CASCADE_PORT_ENABLE_OFFS   3
+#define MVPP2_PORT_CTRL1_PFC_CASCADE_PORT_ENABLE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL1_PFC_CASCADE_PORT_ENABLE_OFFS)
+
+#define MVPP2_PORT_CTRL1_DIS_EXCESSIVE_COL_OFFS   4
+#define MVPP2_PORT_CTRL1_DIS_EXCESSIVE_COL_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL1_DIS_EXCESSIVE_COL_OFFS)
+
+#define MVPP2_PORT_CTRL1_GMII_LOOPBACK_OFFS   5
+#define MVPP2_PORT_CTRL1_GMII_LOOPBACK_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL1_GMII_LOOPBACK_OFFS)
+
+#define MVPP2_PORT_CTRL1_PCS_LOOPBACK_OFFS    6
+#define MVPP2_PORT_CTRL1_PCS_LOOPBACK_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL1_PCS_LOOPBACK_OFFS)
+
+#define MVPP2_PORT_CTRL1_FC_SA_ADDR_LO_OFFS   7
+#define MVPP2_PORT_CTRL1_FC_SA_ADDR_LO_MASK    \
+    (0x000000ff << MVPP2_PORT_CTRL1_FC_SA_ADDR_LO_OFFS)
+
+#define MVPP2_PORT_CTRL1_EN_SHORT_PREAMBLE_OFFS   15
+#define MVPP2_PORT_CTRL1_EN_SHORT_PREAMBLE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL1_EN_SHORT_PREAMBLE_OFFS)
+
+/* Port Mac Control2 */
+#define MVPP2_PORT_CTRL2_REG                              (0x0008)
+#define MVPP2_PORT_CTRL2_SGMII_MODE_OFFS    0
+#define MVPP2_PORT_CTRL2_SGMII_MODE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_SGMII_MODE_OFFS)
+
+#define MVPP2_PORT_CTRL2_FC_MODE_OFFS   1
+#define MVPP2_PORT_CTRL2_FC_MODE_MASK    \
+    (0x00000003 << MVPP2_PORT_CTRL2_FC_MODE_OFFS)
+
+#define MVPP2_PORT_CTRL2_PCS_EN_OFFS    3
+#define MVPP2_PORT_CTRL2_PCS_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_PCS_EN_OFFS)
+
+#define MVPP2_PORT_CTRL2_RGMII_MODE_OFFS    4
+#define MVPP2_PORT_CTRL2_RGMII_MODE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_RGMII_MODE_OFFS)
+
+#define MVPP2_PORT_CTRL2_DIS_PADING_OFFS    5
+#define MVPP2_PORT_CTRL2_DIS_PADING_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_DIS_PADING_OFFS)
+
+#define MVPP2_PORT_CTRL2_PORTMACRESET_OFFS    6
+#define MVPP2_PORT_CTRL2_PORTMACRESET_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_PORTMACRESET_OFFS)
+
+#define MVPP2_PORT_CTRL2_TX_DRAIN_OFFS    7
+#define MVPP2_PORT_CTRL2_TX_DRAIN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_TX_DRAIN_OFFS)
+
+#define MVPP2_PORT_CTRL2_EN_MII_ODD_PRE_OFFS    8
+#define MVPP2_PORT_CTRL2_EN_MII_ODD_PRE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_EN_MII_ODD_PRE_OFFS)
+
+#define MVPP2_PORT_CTRL2_CLK_125_BYPS_EN_OFFS   9
+#define MVPP2_PORT_CTRL2_CLK_125_BYPS_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_CLK_125_BYPS_EN_OFFS)
+
+#define MVPP2_PORT_CTRL2_PRBS_CHECK_EN_OFFS   10
+#define MVPP2_PORT_CTRL2_PRBS_CHECK_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_PRBS_CHECK_EN_OFFS)
+
+#define MVPP2_PORT_CTRL2_PRBS_GEN_EN_OFFS   11
+#define MVPP2_PORT_CTRL2_PRBS_GEN_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_PRBS_GEN_EN_OFFS)
+
+#define MVPP2_PORT_CTRL2_SELECT_DATA_TO_TX_OFFS   12
+#define MVPP2_PORT_CTRL2_SELECT_DATA_TO_TX_MASK    \
+    (0x00000003 << MVPP2_PORT_CTRL2_SELECT_DATA_TO_TX_OFFS)
+
+#define MVPP2_PORT_CTRL2_EN_COL_ON_BP_OFFS    14
+#define MVPP2_PORT_CTRL2_EN_COL_ON_BP_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_EN_COL_ON_BP_OFFS)
+
+#define MVPP2_PORT_CTRL2_EARLY_REJECT_MODE_OFFS   15
+#define MVPP2_PORT_CTRL2_EARLY_REJECT_MODE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL2_EARLY_REJECT_MODE_OFFS)
+
+/* Port Auto-negotiation Configuration */
+#define MVPP2_PORT_AUTO_NEG_CFG_REG                       (0x000c)
+#define MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_OFFS    0
+#define MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_OFFS    1
+#define MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_EN_PCS_AN_OFFS    2
+#define MVPP2_PORT_AUTO_NEG_CFG_EN_PCS_AN_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_EN_PCS_AN_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_OFFS    3
+#define MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_INBAND_RESTARTAN_OFFS    4
+#define MVPP2_PORT_AUTO_NEG_CFG_INBAND_RESTARTAN_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_INBAND_RESTARTAN_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_SET_MII_SPEED_OFFS    5
+#define MVPP2_PORT_AUTO_NEG_CFG_SET_MII_SPEED_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_SET_MII_SPEED_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_OFFS   6
+#define MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_OFFS    7
+#define MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_ADV_PAUSE_OFFS    9
+#define MVPP2_PORT_AUTO_NEG_CFG_ADV_PAUSE_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_ADV_PAUSE_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_ADV_ASM_PAUSE_OFFS    10
+#define MVPP2_PORT_AUTO_NEG_CFG_ADV_ASM_PAUSE_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_ADV_ASM_PAUSE_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_EN_FC_AN_OFFS    11
+#define MVPP2_PORT_AUTO_NEG_CFG_EN_FC_AN_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_EN_FC_AN_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_SET_FULL_DX_OFFS    12
+#define MVPP2_PORT_AUTO_NEG_CFG_SET_FULL_DX_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_SET_FULL_DX_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_OFFS    13
+#define MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_PHY_MODE_OFFS    14
+#define MVPP2_PORT_AUTO_NEG_CFG_PHY_MODE_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_PHY_MODE_OFFS)
+
+#define MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_OFFS    15
+#define MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_MASK    \
+    (0x00000001 << MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG_OFFS)
+
+/* Port Status0 */
+#define MVPP2_PORT_STATUS0_REG                            (0x0010)
+#define MVPP2_PORT_STATUS0_LINKUP_OFFS    0
+#define MVPP2_PORT_STATUS0_LINKUP_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_LINKUP_OFFS)
+
+#define MVPP2_PORT_STATUS0_GMIISPEED_OFFS    1
+#define MVPP2_PORT_STATUS0_GMIISPEED_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_GMIISPEED_OFFS)
+
+#define MVPP2_PORT_STATUS0_MIISPEED_OFFS    2
+#define MVPP2_PORT_STATUS0_MIISPEED_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_MIISPEED_OFFS)
+
+#define MVPP2_PORT_STATUS0_FULLDX_OFFS    3
+#define MVPP2_PORT_STATUS0_FULLDX_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_FULLDX_OFFS)
+
+#define MVPP2_PORT_STATUS0_RXFCEN_OFFS    4
+#define MVPP2_PORT_STATUS0_RXFCEN_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_RXFCEN_OFFS)
+
+#define MVPP2_PORT_STATUS0_TXFCEN_OFFS    5
+#define MVPP2_PORT_STATUS0_TXFCEN_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_TXFCEN_OFFS)
+
+#define MVPP2_PORT_STATUS0_PORTRXPAUSE_OFFS    6
+#define MVPP2_PORT_STATUS0_PORTRXPAUSE_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_PORTRXPAUSE_OFFS)
+
+#define MVPP2_PORT_STATUS0_PORTTXPAUSE_OFFS    7
+#define MVPP2_PORT_STATUS0_PORTTXPAUSE_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_PORTTXPAUSE_OFFS)
+
+#define MVPP2_PORT_STATUS0_PORTIS_DOINGPRESSURE_OFFS    8
+#define MVPP2_PORT_STATUS0_PORTIS_DOINGPRESSURE_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_PORTIS_DOINGPRESSURE_OFFS)
+
+#define MVPP2_PORT_STATUS0_PORTBUFFULL_OFFS    9
+#define MVPP2_PORT_STATUS0_PORTBUFFULL_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_PORTBUFFULL_OFFS)
+
+#define MVPP2_PORT_STATUS0_SYNCFAIL10MS_OFFS    10
+#define MVPP2_PORT_STATUS0_SYNCFAIL10MS_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_SYNCFAIL10MS_OFFS)
+
+#define MVPP2_PORT_STATUS0_ANDONE_OFFS    11
+#define MVPP2_PORT_STATUS0_ANDONE_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_ANDONE_OFFS)
+
+#define MVPP2_PORT_STATUS0_INBAND_AUTONEG_BYPASSACT_OFFS    12
+#define MVPP2_PORT_STATUS0_INBAND_AUTONEG_BYPASSACT_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_INBAND_AUTONEG_BYPASSACT_OFFS)
+
+#define MVPP2_PORT_STATUS0_SERDESPLL_LOCKED_OFFS    13
+#define MVPP2_PORT_STATUS0_SERDESPLL_LOCKED_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_SERDESPLL_LOCKED_OFFS)
+
+#define MVPP2_PORT_STATUS0_SYNCOK_OFFS    14
+#define MVPP2_PORT_STATUS0_SYNCOK_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_SYNCOK_OFFS)
+
+#define MVPP2_PORT_STATUS0_SQUELCHNOT_DETECTED_OFFS    15
+#define MVPP2_PORT_STATUS0_SQUELCHNOT_DETECTED_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS0_SQUELCHNOT_DETECTED_OFFS)
+
+/* Port Serial Parameters Configuration */
+#define MVPP2_PORT_SERIAL_PARAM_CFG_REG                   (0x0014)
+#define MVPP2_PORT_SERIAL_PARAM_CFG_UNIDIRECTIONAL_ENABLE_OFFS    0
+#define MVPP2_PORT_SERIAL_PARAM_CFG_UNIDIRECTIONAL_ENABLE_MASK    \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_UNIDIRECTIONAL_ENABLE_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_RETRANSMIT_COLLISION_DOMAIN_OFFS    1
+#define MVPP2_PORT_SERIAL_PARAM_CFG_RETRANSMIT_COLLISION_DOMAIN_MASK    \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_RETRANSMIT_COLLISION_DOMAIN_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_PUMA2_BTS1444_EN_OFFS    2
+#define MVPP2_PORT_SERIAL_PARAM_CFG_PUMA2_BTS1444_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_PUMA2_BTS1444_EN_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_FORWARD_802_3X_FC_EN_OFFS    3
+#define MVPP2_PORT_SERIAL_PARAM_CFG_FORWARD_802_3X_FC_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_FORWARD_802_3X_FC_EN_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_BP_EN_OFFS    4
+#define MVPP2_PORT_SERIAL_PARAM_CFG_BP_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_BP_EN_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_RX_NEGEDGE_SAMPLE_EN_OFFS   5
+#define MVPP2_PORT_SERIAL_PARAM_CFG_RX_NEGEDGE_SAMPLE_EN_MASK   \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_RX_NEGEDGE_SAMPLE_EN_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_COL_DOMAIN_LIMIT_OFFS    6
+#define MVPP2_PORT_SERIAL_PARAM_CFG_COL_DOMAIN_LIMIT_MASK    \
+    (0x0000003f << MVPP2_PORT_SERIAL_PARAM_CFG_COL_DOMAIN_LIMIT_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_PERIODIC_TYPE_SELECT_OFFS   12
+#define MVPP2_PORT_SERIAL_PARAM_CFG_PERIODIC_TYPE_SELECT_MASK   \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_PERIODIC_TYPE_SELECT_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_PER_PRIORITY_FC_EN_OFFS   13
+#define MVPP2_PORT_SERIAL_PARAM_CFG_PER_PRIORITY_FC_EN_MASK   \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_PER_PRIORITY_FC_EN_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_TX_STANDARD_PRBS7_OFFS    14
+#define MVPP2_PORT_SERIAL_PARAM_CFG_TX_STANDARD_PRBS7_MASK    \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_TX_STANDARD_PRBS7_OFFS)
+
+#define MVPP2_PORT_SERIAL_PARAM_CFG_REVERSE_PRBS_RX_OFFS    15
+#define MVPP2_PORT_SERIAL_PARAM_CFG_REVERSE_PRBS_RX_MASK    \
+    (0x00000001 << MVPP2_PORT_SERIAL_PARAM_CFG_REVERSE_PRBS_RX_OFFS)
+
+/* Port Fifo Configuration 0 */
+#define MVPP2_PORT_FIFO_CFG_0_REG                         (0x0018)
+#define MVPP2_PORT_FIFO_CFG_0_TX_FIFO_HIGH_WM_OFFS    0
+#define MVPP2_PORT_FIFO_CFG_0_TX_FIFO_HIGH_WM_MASK    \
+    (0x000000ff << MVPP2_PORT_FIFO_CFG_0_TX_FIFO_HIGH_WM_OFFS)
+
+#define MVPP2_PORT_FIFO_CFG_0_TX_FIFO_LOW_WM_OFFS    8
+#define MVPP2_PORT_FIFO_CFG_0_TX_FIFO_LOW_WM_MASK    \
+    (0x000000ff << MVPP2_PORT_FIFO_CFG_0_TX_FIFO_LOW_WM_OFFS)
+
+/* Port Fifo Configuration 1 */
+#define MVPP2_PORT_FIFO_CFG_1_REG                         (0x001c)
+#define MVPP2_PORT_FIFO_CFG_1_RX_FIFO_MAX_TH_OFFS    0
+#define MVPP2_PORT_FIFO_CFG_1_RX_FIFO_MAX_TH_MASK    \
+    (0x0000003f << MVPP2_PORT_FIFO_CFG_1_RX_FIFO_MAX_TH_OFFS)
+
+#define MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_OFFS    6
+#define MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_MASK    \
+    (0x000000ff << MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH_OFFS)
+
+#define MVPP2_PORT_FIFO_CFG_1_PORT_EN_FIX_EN_OFFS    15
+#define MVPP2_PORT_FIFO_CFG_1_PORT_EN_FIX_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_FIFO_CFG_1_PORT_EN_FIX_EN_OFFS)
+
+/* Port Serdes Configuration0 */
+#define MVPP2_PORT_SERDES_CFG0_REG                        (0x0028)
+#define MVPP2_PORT_SERDES_CFG0_SERDESRESET_OFFS    0
+#define MVPP2_PORT_SERDES_CFG0_SERDESRESET_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_SERDESRESET_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_PU_TX_OFFS    1
+#define MVPP2_PORT_SERDES_CFG0_PU_TX_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_PU_TX_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_PU_RX_OFFS    2
+#define MVPP2_PORT_SERDES_CFG0_PU_RX_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_PU_RX_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_PU_PLL_OFFS    3
+#define MVPP2_PORT_SERDES_CFG0_PU_PLL_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_PU_PLL_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_PU_IVREF_OFFS    4
+#define MVPP2_PORT_SERDES_CFG0_PU_IVREF_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_PU_IVREF_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_TESTEN_OFFS    5
+#define MVPP2_PORT_SERDES_CFG0_TESTEN_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_TESTEN_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_DPHER_EN_OFFS    6
+#define MVPP2_PORT_SERDES_CFG0_DPHER_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_DPHER_EN_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_RUDI_INVALID_ENABLE_OFFS    7
+#define MVPP2_PORT_SERDES_CFG0_RUDI_INVALID_ENABLE_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_RUDI_INVALID_ENABLE_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_ACK_OVERRIDE_ENABLE_OFFS    8
+#define MVPP2_PORT_SERDES_CFG0_ACK_OVERRIDE_ENABLE_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_ACK_OVERRIDE_ENABLE_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_CONFIG_WORD_ENABLE_OFFS    9
+#define MVPP2_PORT_SERDES_CFG0_CONFIG_WORD_ENABLE_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_CONFIG_WORD_ENABLE_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_SYNC_FAIL_INT_ENABLE_OFFS    10
+#define MVPP2_PORT_SERDES_CFG0_SYNC_FAIL_INT_ENABLE_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_SYNC_FAIL_INT_ENABLE_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_MASTER_MODE_ENABLE_OFFS    11
+#define MVPP2_PORT_SERDES_CFG0_MASTER_MODE_ENABLE_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_MASTER_MODE_ENABLE_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_TERM75_TX_OFFS    12
+#define MVPP2_PORT_SERDES_CFG0_TERM75_TX_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_TERM75_TX_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_OUTAMP_OFFS    13
+#define MVPP2_PORT_SERDES_CFG0_OUTAMP_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_OUTAMP_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_BTS712_FIX_EN_OFFS    14
+#define MVPP2_PORT_SERDES_CFG0_BTS712_FIX_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_BTS712_FIX_EN_OFFS)
+
+#define MVPP2_PORT_SERDES_CFG0_BTS156_FIX_EN_OFFS    15
+#define MVPP2_PORT_SERDES_CFG0_BTS156_FIX_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_SERDES_CFG0_BTS156_FIX_EN_OFFS)
+
+/* Port Serdes Configuration1 */
+#define MVPP2_PORT_SERDES_CFG1_REG                        (0x002c)
+#define MVPP2_PORT_SERDES_CFG1_SMII_RX_10MB_CLK_EDGE_SEL_OFFS    0
+#define MVPP2_PORT_SERDES_CFG1_SMII_RX_10MB_CLK_EDGE_SEL_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_SMII_RX_10MB_CLK_EDGE_SEL_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_SMII_TX_10MB_CLK_EDGE_SEL_OFFS    1
+#define MVPP2_GMAC_PORT_SERDES_CFG1_SMII_TX_10MB_CLK_EDGE_SEL_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_SMII_TX_10MB_CLK_EDGE_SEL_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_MEN_OFFS    2
+#define MVPP2_GMAC_PORT_SERDES_CFG1_MEN_MASK    \
+    (0x00000003 << MVPP2_GMAC_PORT_SERDES_CFG1_MEN_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_VCMS_OFFS    4
+#define MVPP2_GMAC_PORT_SERDES_CFG1_VCMS_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_VCMS_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_USE_SIGDET_OFFS    5
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_USE_SIGDET_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_USE_SIGDET_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_EN_CRS_MASK_TX_OFFS    6
+#define MVPP2_GMAC_PORT_SERDES_CFG1_EN_CRS_MASK_TX_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_EN_CRS_MASK_TX_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_ENABLE_OFFS    7
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_ENABLE_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_100FX_ENABLE_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_PHY_ADDRESS_OFFS    8
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_PHY_ADDRESS_MASK    \
+    (0x0000001f << MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_PHY_ADDRESS_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SIGDET_POLARITY_OFFS    13
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SIGDET_POLARITY_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SIGDET_POLARITY_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_INTERRUPT_POLARITY_OFFS    14
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_INTERRUPT_POLARITY_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_INTERRUPT_POLARITY_OFFS)
+
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SERDES_POLARITY_OFFS    15
+#define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SERDES_POLARITY_MASK    \
+    (0x00000001 << MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SERDES_POLARITY_OFFS)
+
+/* Port Serdes Configuration2 */
+#define MVPP2_PORT_SERDES_CFG2_REG                        (0x0030)
+#define MVPP2_PORT_SERDES_CFG2_AN_ADV_CONFIGURATION_OFFS    0
+#define MVPP2_PORT_SERDES_CFG2_AN_ADV_CONFIGURATION_MASK    \
+    (0x0000ffff << MVPP2_PORT_SERDES_CFG2_AN_ADV_CONFIGURATION_OFFS)
+
+/* Port Serdes Configuration3 */
+#define MVPP2_PORT_SERDES_CFG3_REG                        (0x0034)
+#define MVPP2_PORT_SERDES_CFG3_ABILITY_MATCH_STATUS_OFFS    0
+#define MVPP2_PORT_SERDES_CFG3_ABILITY_MATCH_STATUS_MASK    \
+    (0x0000ffff << MVPP2_PORT_SERDES_CFG3_ABILITY_MATCH_STATUS_OFFS)
+
+/* Port Prbs Status */
+#define MVPP2_PORT_PRBS_STATUS_REG                        (0x0038)
+#define MVPP2_PORT_PRBS_STATUS_PRBSCHECK_LOCKED_OFFS    0
+#define MVPP2_PORT_PRBS_STATUS_PRBSCHECK_LOCKED_MASK    \
+    (0x00000001 << MVPP2_PORT_PRBS_STATUS_PRBSCHECK_LOCKED_OFFS)
+
+#define MVPP2_PORT_PRBS_STATUS_PRBSCHECKRDY_OFFS    1
+#define MVPP2_PORT_PRBS_STATUS_PRBSCHECKRDY_MASK    \
+    (0x00000001 << MVPP2_PORT_PRBS_STATUS_PRBSCHECKRDY_OFFS)
+
+/* Port Prbs Error Counter */
+#define MVPP2_PORT_PRBS_ERR_CNTR_REG                      (0x003c)
+#define MVPP2_PORT_PRBS_ERR_CNTR_PRBSBITERRCNT_OFFS    0
+#define MVPP2_PORT_PRBS_ERR_CNTR_PRBSBITERRCNT_MASK    \
+    (0x0000ffff << MVPP2_PORT_PRBS_ERR_CNTR_PRBSBITERRCNT_OFFS)
+
+/* Port Status1 */
+#define MVPP2_PORT_STATUS1_REG                            (0x0040)
+#define MVPP2_PORT_STATUS1_MEDIAACTIVE_OFFS    0
+#define MVPP2_PORT_STATUS1_MEDIAACTIVE_MASK    \
+    (0x00000001 << MVPP2_PORT_STATUS1_MEDIAACTIVE_OFFS)
+
+/* Port Mib Counters Control */
+#define MVPP2_PORT_MIB_CNTRS_CTRL_REG                     (0x0044)
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_COPY_TRIGGER_OFFS    0
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_COPY_TRIGGER_MASK    \
+    (0x00000001 << MVPP2_PORT_MIB_CNTRS_CTRL_MIB_COPY_TRIGGER_OFFS)
+
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_CLEAR_ON_READ__OFFS     1
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_CLEAR_ON_READ__MASK     \
+    (0x00000001 << MVPP2_PORT_MIB_CNTRS_CTRL_MIB_CLEAR_ON_READ__OFFS)
+
+#define MVPP2_PORT_MIB_CNTRS_CTRL_RX_HISTOGRAM_EN_OFFS    2
+#define MVPP2_PORT_MIB_CNTRS_CTRL_RX_HISTOGRAM_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_MIB_CNTRS_CTRL_RX_HISTOGRAM_EN_OFFS)
+
+#define MVPP2_PORT_MIB_CNTRS_CTRL_TX_HISTOGRAM_EN_OFFS    3
+#define MVPP2_PORT_MIB_CNTRS_CTRL_TX_HISTOGRAM_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_MIB_CNTRS_CTRL_TX_HISTOGRAM_EN_OFFS)
+
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__OFFS    4
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__MASK    \
+    (0x00000001 << MVPP2_PORT_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__OFFS)
+
+#define MVPP2_PORT_MIB_CNTRS_CTRL_XCAT_BTS_340_EN__OFFS    5
+#define MVPP2_PORT_MIB_CNTRS_CTRL_XCAT_BTS_340_EN__MASK    \
+    (0x00000001 << MVPP2_PORT_MIB_CNTRS_CTRL_XCAT_BTS_340_EN__OFFS)
+
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_OFFS    6
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_MASK    \
+    (0x00000001 << MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_OFFS)
+
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_OFFS    7
+#define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_MASK    \
+    (0x00000001 << MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_OFFS)
+
+/* Port Mac Control3 */
+#define MVPP2_PORT_CTRL3_REG                              (0x0048)
+#define MVPP2_PORT_CTRL3_BUF_SIZE_OFFS    0
+#define MVPP2_PORT_CTRL3_BUF_SIZE_MASK    \
+    (0x0000003f << MVPP2_PORT_CTRL3_BUF_SIZE_OFFS)
+
+#define MVPP2_PORT_CTRL3_IPG_DATA_OFFS    6
+#define MVPP2_PORT_CTRL3_IPG_DATA_MASK    \
+    (0x000001ff << MVPP2_PORT_CTRL3_IPG_DATA_OFFS)
+
+#define MVPP2_PORT_CTRL3_LLFC_GLOBAL_FC_ENABLE_OFFS    15
+#define MVPP2_PORT_CTRL3_LLFC_GLOBAL_FC_ENABLE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL3_LLFC_GLOBAL_FC_ENABLE_OFFS)
+#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK    0xff
+
+/* Port Mac Control4 */
+#define MVPP2_PORT_CTRL4_REG                              (0x0090)
+#define MVPP2_PORT_CTRL4_EXT_PIN_GMII_SEL_OFFS    0
+#define MVPP2_PORT_CTRL4_EXT_PIN_GMII_SEL_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_EXT_PIN_GMII_SEL_OFFS)
+
+#define MVPP2_PORT_CTRL4_PREAMBLE_FIX_OFFS    1
+#define MVPP2_PORT_CTRL4_PREAMBLE_FIX_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_PREAMBLE_FIX_OFFS)
+
+#define MVPP2_PORT_CTRL4_SQ_DETECT_FIX_EN_OFFS    2
+#define MVPP2_PORT_CTRL4_SQ_DETECT_FIX_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_SQ_DETECT_FIX_EN_OFFS)
+
+#define MVPP2_PORT_CTRL4_FC_EN_RX_OFFS    3
+#define MVPP2_PORT_CTRL4_FC_EN_RX_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_FC_EN_RX_OFFS)
+
+#define MVPP2_PORT_CTRL4_FC_EN_TX_OFFS    4
+#define MVPP2_PORT_CTRL4_FC_EN_TX_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_FC_EN_TX_OFFS)
+
+#define MVPP2_PORT_CTRL4_DP_CLK_SEL_OFFS    5
+#define MVPP2_PORT_CTRL4_DP_CLK_SEL_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_DP_CLK_SEL_OFFS)
+
+#define MVPP2_PORT_CTRL4_SYNC_BYPASS_OFFS   6
+#define MVPP2_PORT_CTRL4_SYNC_BYPASS_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_SYNC_BYPASS_OFFS)
+
+#define MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_OFFS    7
+#define MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE_OFFS)
+
+#define MVPP2_PORT_CTRL4_COUNT_EXTERNAL_FC_EN_OFFS    8
+#define MVPP2_PORT_CTRL4_COUNT_EXTERNAL_FC_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_COUNT_EXTERNAL_FC_EN_OFFS)
+
+#define MVPP2_PORT_CTRL4_MARVELL_HEADER_EN_OFFS    9
+#define MVPP2_PORT_CTRL4_MARVELL_HEADER_EN_MASK    \
+    (0x00000001 << MVPP2_PORT_CTRL4_MARVELL_HEADER_EN_OFFS)
+
+#define MVPP2_PORT_CTRL4_LEDS_NUMBER_OFFS    10
+#define MVPP2_PORT_CTRL4_LEDS_NUMBER_MASK    \
+    (0x0000003f << MVPP2_PORT_CTRL4_LEDS_NUMBER_OFFS)
+
+/* Descriptor ring Macros */
+#define MVPP2_QUEUE_NEXT_DESC(q, index)                   (((index) < (q)->LastDesc) ? ((index) + 1) : 0)
+
+/* Various constants */
+
+/* Coalescing */
+#define MVPP2_TXDONE_COAL_PKTS_THRESH                     15
+#define MVPP2_TXDONE_HRTIMER_PERIOD_NS                    1000000UL
+#define MVPP2_RX_COAL_PKTS                                32
+#define MVPP2_RX_COAL_USEC                                100
+
+/*
+ * The two bytes Marvell header. Either contains a special value used
+ * by Marvell switches when a specific hardware mode is enabled (not
+ * supported by this driver) or is filled automatically by zeroes on
+ * the RX side. Those two bytes being at the front of the Ethernet
+ * header, they allow to have the IP header aligned on a 4 bytes
+ * boundary automatically: the hardware skips those two bytes on its
+ * own.
+ */
+#define MVPP2_MH_SIZE                                     2
+#define MVPP2_ETH_TYPE_LEN                                2
+#define MVPP2_PPPOE_HDR_SIZE                              8
+#define MVPP2_VLAN_TAG_LEN                                4
+
+/* Lbtd 802.3 type */
+#define MVPP2_IP_LBDT_TYPE                                0xfffa
+
+#define MVPP2_CPU_D_CACHE_LINE_SIZE                       32
+#define MVPP2_TX_CSUM_MAX_SIZE                            9800
+
+/* Timeout constants */
+#define MVPP2_TX_DISABLE_TIMEOUT_MSEC                     1000
+#define MVPP2_TX_PENDING_TIMEOUT_MSEC                     1000
+
+#define MVPP2_TX_MTU_MAX                                  0x7ffff
+
+/* Maximum number of T-CONTs of PON port */
+#define MVPP2_MAX_TCONT                                   16
+
+/* Maximum number of supported ports */
+#define MVPP2_MAX_PORTS                                   4
+
+/* Maximum number of TXQs used by single port */
+#define MVPP2_MAX_TXQ                                     8
+
+/* Maximum number of RXQs used by single port */
+#define MVPP2_MAX_RXQ                                     8
+
+/* Dfault number of RXQs in use */
+#define MVPP2_DEFAULT_RXQ                                 4
+
+/* Total number of RXQs available to all ports */
+#define MVPP2_RXQ_TOTAL_NUM                               (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
+
+/* Max number of Rx descriptors */
+#define MVPP2_MAX_RXD                                     32
+
+/* Max number of Tx descriptors */
+#define MVPP2_MAX_TXD                                     32
+
+/* Amount of Tx descriptors that can be reserved at once by CPU */
+#define MVPP2_CPU_DESC_CHUNK                              64
+
+/* Max number of Tx descriptors in each aggregated queue */
+#define MVPP2_AGGR_TXQ_SIZE                               256
+
+/* Descriptor aligned size */
+#define MVPP2_DESC_ALIGNED_SIZE                           32
+
+/* Descriptor alignment mask */
+#define MVPP2_TX_DESC_ALIGN                               (MVPP2_DESC_ALIGNED_SIZE - 1)
+
+/* RX FIFO constants */
+#define MVPP2_RX_FIFO_PORT_DATA_SIZE                      0x2000
+#define MVPP2_RX_FIFO_PORT_ATTR_SIZE                      0x80
+#define MVPP2_RX_FIFO_PORT_MIN_PKT                        0x80
+
+#define MVPP2_BIT_TO_BYTE(bit)                            ((bit) / 8)
+
+/* IPv6 max L3 address size */
+#define MVPP2_MAX_L3_ADDR_SIZE                            16
+
+/* Port flags */
+#define MVPP2_F_LOOPBACK                                  BIT(0)
+
+/* SD1 Control1 */
+#define SD1_CONTROL_1_REG                                 (0x148)
+
+#define SD1_CONTROL_XAUI_EN_OFFSET    28
+#define SD1_CONTROL_XAUI_EN_MASK    (0x1 << SD1_CONTROL_XAUI_EN_OFFSET)
+
+#define SD1_CONTROL_RXAUI0_L23_EN_OFFSET    27
+#define SD1_CONTROL_RXAUI0_L23_EN_MASK    (0x1 << SD1_CONTROL_RXAUI0_L23_EN_OFFSET)
+
+#define SD1_CONTROL_RXAUI1_L45_EN_OFFSET    26
+#define SD1_CONTROL_RXAUI1_L45_EN_MASK    (0x1 << SD1_CONTROL_RXAUI1_L45_EN_OFFSET)
+
+/* System Soft Reset 1 */
+#define MV_GOP_SOFT_RESET_1_REG                           (0x108)
+
+#define NETC_GOP_SOFT_RESET_OFFSET    6
+#define NETC_GOP_SOFT_RESET_MASK    (0x1 << NETC_GOP_SOFT_RESET_OFFSET)
+
+/* Ports Control 0 */
+#define MV_NETCOMP_PORTS_CONTROL_0                        (0x110)
+
+#define NETC_CLK_DIV_PHASE_OFFSET    31
+#define NETC_CLK_DIV_PHASE_MASK    (0x1 << NETC_CLK_DIV_PHASE_OFFSET)
+
+#define NETC_GIG_RX_DATA_SAMPLE_OFFSET    29
+#define NETC_GIG_RX_DATA_SAMPLE_MASK    (0x1 << NETC_GIG_RX_DATA_SAMPLE_OFFSET)
+
+#define NETC_BUS_WIDTH_SELECT_OFFSET    1
+#define NETC_BUS_WIDTH_SELECT_MASK    (0x1 << NETC_BUS_WIDTH_SELECT_OFFSET)
+
+#define NETC_GOP_ENABLE_OFFSET    0
+#define NETC_GOP_ENABLE_MASK    (0x1 << NETC_GOP_ENABLE_OFFSET)
+
+/* Ports Control 1 */
+#define MV_NETCOMP_PORTS_CONTROL_1                        (0x114)
+
+#define NETC_PORT_GIG_RF_RESET_OFFSET(port)    (28 + port)
+#define NETC_PORT_GIG_RF_RESET_MASK(port)    (0x1 << NETC_PORT_GIG_RF_RESET_OFFSET(port))
+
+#define NETC_PORTS_ACTIVE_OFFSET(port)    (0 + port)
+#define NETC_PORTS_ACTIVE_MASK(port)    (0x1 << NETC_PORTS_ACTIVE_OFFSET(port))
+
+/* Ports Status */
+#define MV_NETCOMP_PORTS_STATUS                           (0x11C)
+#define NETC_PORTS_STATUS_OFFSET(port)    (0 + port)
+#define NETC_PORTS_STATUS_MASK(port)    (0x1 << NETC_PORTS_STATUS_OFFSET(port))
+
+/* Networking Complex Control 0 */
+#define MV_NETCOMP_CONTROL_0                              (0x120)
+
+#define NETC_GBE_PORT1_MII_MODE_OFFSET    2
+#define NETC_GBE_PORT1_MII_MODE_MASK    (0x1 << NETC_GBE_PORT1_MII_MODE_OFFSET)
+
+#define NETC_GBE_PORT1_SGMII_MODE_OFFSET    1
+#define NETC_GBE_PORT1_SGMII_MODE_MASK    (0x1 << NETC_GBE_PORT1_SGMII_MODE_OFFSET)
+
+#define NETC_GBE_PORT0_SGMII_MODE_OFFSET    0
+#define NETC_GBE_PORT0_SGMII_MODE_MASK    (0x1 << NETC_GBE_PORT0_SGMII_MODE_OFFSET)
+
+/* Port Mac Control0 */
+#define MV_XLG_PORT_MAC_CTRL0_REG     (                   0x0000)
+#define MV_XLG_MAC_CTRL0_PORTEN_OFFS    0
+#define MV_XLG_MAC_CTRL0_PORTEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_PORTEN_OFFS)
+
+#define MV_XLG_MAC_CTRL0_MACRESETN_OFFS    1
+#define MV_XLG_MAC_CTRL0_MACRESETN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_MACRESETN_OFFS)
+
+#define MV_XLG_MAC_CTRL0_FORCELINKDOWN_OFFS    2
+#define MV_XLG_MAC_CTRL0_FORCELINKDOWN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_FORCELINKDOWN_OFFS)
+
+#define MV_XLG_MAC_CTRL0_FORCELINKPASS_OFFS    3
+#define MV_XLG_MAC_CTRL0_FORCELINKPASS_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_FORCELINKPASS_OFFS)
+
+#define MV_XLG_MAC_CTRL0_TXIPGMODE_OFFS    5
+#define MV_XLG_MAC_CTRL0_TXIPGMODE_MASK    \
+    (0x00000003 << MV_XLG_MAC_CTRL0_TXIPGMODE_OFFS)
+
+#define MV_XLG_MAC_CTRL0_RXFCEN_OFFS    7
+#define MV_XLG_MAC_CTRL0_RXFCEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_RXFCEN_OFFS)
+
+#define MV_XLG_MAC_CTRL0_TXFCEN_OFFS    8
+#define MV_XLG_MAC_CTRL0_TXFCEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_TXFCEN_OFFS)
+
+#define MV_XLG_MAC_CTRL0_RXCRCCHECKEN_OFFS    9
+#define MV_XLG_MAC_CTRL0_RXCRCCHECKEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_RXCRCCHECKEN_OFFS)
+
+#define MV_XLG_MAC_CTRL0_PERIODICXONEN_OFFS    10
+#define MV_XLG_MAC_CTRL0_PERIODICXONEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_PERIODICXONEN_OFFS)
+
+#define MV_XLG_MAC_CTRL0_RXCRCSTRIPEN_OFFS    11
+#define MV_XLG_MAC_CTRL0_RXCRCSTRIPEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_RXCRCSTRIPEN_OFFS)
+
+#define MV_XLG_MAC_CTRL0_PADDINGDIS_OFFS    13
+#define MV_XLG_MAC_CTRL0_PADDINGDIS_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_PADDINGDIS_OFFS)
+
+#define MV_XLG_MAC_CTRL0_MIBCNTDIS_OFFS    14
+#define MV_XLG_MAC_CTRL0_MIBCNTDIS_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_MIBCNTDIS_OFFS)
+
+#define MV_XLG_MAC_CTRL0_PFC_CASCADE_PORT_ENABLE_OFFS    15
+#define MV_XLG_MAC_CTRL0_PFC_CASCADE_PORT_ENABLE_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL0_PFC_CASCADE_PORT_ENABLE_OFFS)
+
+/* Port Mac Control1 */
+#define MV_XLG_PORT_MAC_CTRL1_REG                         (0x0004)
+#define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS    0
+#define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK    \
+    (0x00001fff << MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS)
+
+#define MV_XLG_MAC_CTRL1_MACLOOPBACKEN_OFFS    13
+#define MV_XLG_MAC_CTRL1_MACLOOPBACKEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL1_MACLOOPBACKEN_OFFS)
+
+#define MV_XLG_MAC_CTRL1_XGMIILOOPBACKEN_OFFS    14
+#define MV_XLG_MAC_CTRL1_XGMIILOOPBACKEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL1_XGMIILOOPBACKEN_OFFS)
+
+#define MV_XLG_MAC_CTRL1_LOOPBACKCLOCKSELECT_OFFS    15
+#define MV_XLG_MAC_CTRL1_LOOPBACKCLOCKSELECT_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL1_LOOPBACKCLOCKSELECT_OFFS)
+
+/* Port Mac Control2 */
+#define MV_XLG_PORT_MAC_CTRL2_REG                         (0x0008)
+#define MV_XLG_MAC_CTRL2_SALOW_7_0_OFFS    0
+#define MV_XLG_MAC_CTRL2_SALOW_7_0_MASK    \
+    (0x000000ff << MV_XLG_MAC_CTRL2_SALOW_7_0_OFFS)
+
+#define MV_XLG_MAC_CTRL2_UNIDIRECTIONALEN_OFFS    8
+#define MV_XLG_MAC_CTRL2_UNIDIRECTIONALEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL2_UNIDIRECTIONALEN_OFFS)
+
+#define MV_XLG_MAC_CTRL2_FIXEDIPGBASE_OFFS    9
+#define MV_XLG_MAC_CTRL2_FIXEDIPGBASE_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL2_FIXEDIPGBASE_OFFS)
+
+#define MV_XLG_MAC_CTRL2_PERIODICXOFFEN_OFFS    10
+#define MV_XLG_MAC_CTRL2_PERIODICXOFFEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL2_PERIODICXOFFEN_OFFS)
+
+#define MV_XLG_MAC_CTRL2_SIMPLEXMODEEN_OFFS    13
+#define MV_XLG_MAC_CTRL2_SIMPLEXMODEEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL2_SIMPLEXMODEEN_OFFS)
+
+#define MV_XLG_MAC_CTRL2_FC_MODE_OFFS    14
+#define MV_XLG_MAC_CTRL2_FC_MODE_MASK    \
+    (0x00000003 << MV_XLG_MAC_CTRL2_FC_MODE_OFFS)
+
+/* Port Status */
+#define MV_XLG_MAC_PORT_STATUS_REG                        (0x000c)
+#define MV_XLG_MAC_PORT_STATUS_LINKSTATUS_OFFS    0
+#define MV_XLG_MAC_PORT_STATUS_LINKSTATUS_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_LINKSTATUS_OFFS)
+
+#define MV_XLG_MAC_PORT_STATUS_REMOTEFAULT_OFFS    1
+#define MV_XLG_MAC_PORT_STATUS_REMOTEFAULT_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_REMOTEFAULT_OFFS)
+
+#define MV_XLG_MAC_PORT_STATUS_LOCALFAULT_OFFS    2
+#define MV_XLG_MAC_PORT_STATUS_LOCALFAULT_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_LOCALFAULT_OFFS)
+
+#define MV_XLG_MAC_PORT_STATUS_LINKSTATUSCLEAN_OFFS    3
+#define MV_XLG_MAC_PORT_STATUS_LINKSTATUSCLEAN_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_LINKSTATUSCLEAN_OFFS)
+
+#define MV_XLG_MAC_PORT_STATUS_LOCALFAULTCLEAN_OFFS    4
+#define MV_XLG_MAC_PORT_STATUS_LOCALFAULTCLEAN_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_LOCALFAULTCLEAN_OFFS)
+
+#define MV_XLG_MAC_PORT_STATUS_REMOTEFAULTCLEAN_OFFS    5
+#define MV_XLG_MAC_PORT_STATUS_REMOTEFAULTCLEAN_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_REMOTEFAULTCLEAN_OFFS)
+
+#define MV_XLG_MAC_PORT_STATUS_PORTRXPAUSE_OFFS    6
+#define MV_XLG_MAC_PORT_STATUS_PORTRXPAUSE_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_PORTRXPAUSE_OFFS)
+
+#define MV_XLG_MAC_PORT_STATUS_PORTTXPAUSE_OFFS    7
+#define MV_XLG_MAC_PORT_STATUS_PORTTXPAUSE_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_PORTTXPAUSE_OFFS)
+
+#define MV_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_OFFS    8
+#define MV_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_OFFS)
+
+/* Port Fifos Thresholds Configuration */
+#define MV_XLG_PORT_FIFOS_THRS_CFG_REG                    (0x001)
+#define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS    0
+#define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_MASK    \
+    (0x0000001f << MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS)
+
+#define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_TXFIFOSIZE_OFFS    5
+#define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_TXFIFOSIZE_MASK    \
+    (0x0000003f << MV_XLG_MAC_PORT_FIFOS_THRS_CFG_TXFIFOSIZE_OFFS)
+
+#define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_TXRDTHR_OFFS    11
+#define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_TXRDTHR_MASK    \
+    (0x0000001f << MV_XLG_MAC_PORT_FIFOS_THRS_CFG_TXRDTHR_OFFS)
+
+/* Port Mac Control3 */
+#define MV_XLG_PORT_MAC_CTRL3_REG                         (0x001c)
+#define MV_XLG_MAC_CTRL3_BUFSIZE_OFFS    0
+#define MV_XLG_MAC_CTRL3_BUFSIZE_MASK    \
+    (0x0000003f << MV_XLG_MAC_CTRL3_BUFSIZE_OFFS)
+
+#define MV_XLG_MAC_CTRL3_XTRAIPG_OFFS    6
+#define MV_XLG_MAC_CTRL3_XTRAIPG_MASK    \
+    (0x0000007f << MV_XLG_MAC_CTRL3_XTRAIPG_OFFS)
+
+#define MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS    13
+#define MV_XLG_MAC_CTRL3_MACMODESELECT_MASK    \
+    (0x00000007 << MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS)
+
+/* Port Per Prio Flow Control Status */
+#define MV_XLG_PORT_PER_PRIO_FLOW_CTRL_STATUS_REG         (0x0020)
+#define MV_XLG_MAC_PORT_PER_PRIO_FLOW_CTRL_STATUS_PRIONSTATUS_OFFS    0
+#define MV_XLG_MAC_PORT_PER_PRIO_FLOW_CTRL_STATUS_PRIONSTATUS_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_PER_PRIO_FLOW_CTRL_STATUS_PRIONSTATUS_OFFS)
+
+/* Debug Bus Status */
+#define MV_XLG_DEBUG_BUS_STATUS_REG                       (0x0024)
+#define MV_XLG_MAC_DEBUG_BUS_STATUS_DEBUG_BUS_OFFS    0
+#define MV_XLG_MAC_DEBUG_BUS_STATUS_DEBUG_BUS_MASK    \
+    (0x0000ffff << MV_XLG_MAC_DEBUG_BUS_STATUS_DEBUG_BUS_OFFS)
+
+/* Port Metal Fix */
+#define MV_XLG_PORT_METAL_FIX_REG                         (0x002c)
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_EOP_IN_FIFO__OFFS    0
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_EOP_IN_FIFO__MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_EOP_IN_FIFO__OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_LTF_FIX__OFFS    1
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_LTF_FIX__MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_LTF_FIX__OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_HOLD_FIX__OFFS    2
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_HOLD_FIX__MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_HOLD_FIX__OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_LED_FIX__OFFS    3
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_LED_FIX__MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_LED_FIX__OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_PAD_PROTECT__OFFS    4
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_PAD_PROTECT__MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_PAD_PROTECT__OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS44__OFFS    5
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS44__MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS44__OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS42__OFFS    6
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS42__MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS42__OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_FLUSH_FIX_OFFS    7
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_FLUSH_FIX_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_FLUSH_FIX_OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_PORT_EN_FIX_OFFS    8
+#define MV_XLG_MAC_PORT_METAL_FIX_EN_PORT_EN_FIX_MASK    \
+    (0x00000001 << MV_XLG_MAC_PORT_METAL_FIX_EN_PORT_EN_FIX_OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_SPARE_DEF0_BITS_OFFS    9
+#define MV_XLG_MAC_PORT_METAL_FIX_SPARE_DEF0_BITS_MASK    \
+    (0x0000000f << MV_XLG_MAC_PORT_METAL_FIX_SPARE_DEF0_BITS_OFFS)
+
+#define MV_XLG_MAC_PORT_METAL_FIX_SPARE_DEF1_BITS_OFFS    13
+#define MV_XLG_MAC_PORT_METAL_FIX_SPARE_DEF1_BITS_MASK    \
+    (0x00000007 << MV_XLG_MAC_PORT_METAL_FIX_SPARE_DEF1_BITS_OFFS)
+
+/* Xg Mib Counters Control */
+#define MV_XLG_MIB_CNTRS_CTRL_REG                         (0x0030)
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGCAPTURETRIGGER_OFFS    0
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGCAPTURETRIGGER_MASK    \
+    (0x00000001 << MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGCAPTURETRIGGER_OFFS)
+
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGDONTCLEARAFTERREAD_OFFS    1
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGDONTCLEARAFTERREAD_MASK    \
+    (0x00000001 << MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGDONTCLEARAFTERREAD_OFFS)
+
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGRXHISTOGRAMEN_OFFS    2
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGRXHISTOGRAMEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGRXHISTOGRAMEN_OFFS)
+
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGTXHISTOGRAMEN_OFFS    3
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGTXHISTOGRAMEN_MASK    \
+    (0x00000001 << MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGTXHISTOGRAMEN_OFFS)
+
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__OFFS    4
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__MASK    \
+    (0x00000001 << MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE__OFFS)
+
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_LEDS_NUMBER_OFFS    5
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_LEDS_NUMBER_MASK    \
+    (0x0000003f << MV_XLG_MAC_XG_MIB_CNTRS_CTRL_LEDS_NUMBER_OFFS)
+
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_OFFS    11
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_MASK    \
+    (0x00000001 << MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST_OFFS)
+
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_OFFS    12
+#define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_MASK    \
+    (0x00000001 << MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522_OFFS)
+
+/* Cn/ccfc Timer%i */
+#define MV_XLG_CNCCFC_TIMERI_REG(t)                       ((0x0038 + (t) * 4))
+#define MV_XLG_MAC_CNCCFC_TIMERI_PORTSPEEDTIMER_OFFS    0
+#define MV_XLG_MAC_CNCCFC_TIMERI_PORTSPEEDTIMER_MASK    \
+    (0x0000ffff << MV_XLG_MAC_CNCCFC_TIMERI_PORTSPEEDTIMER_OFFS)
+
+/* Ppfc Control */
+#define MV_XLG_MAC_PPFC_CTRL_REG                          (0x0060)
+#define MV_XLG_MAC_PPFC_CTRL_GLOBAL_PAUSE_ENI_OFFS    0
+#define MV_XLG_MAC_PPFC_CTRL_GLOBAL_PAUSE_ENI_MASK    \
+    (0x00000001 << MV_XLG_MAC_PPFC_CTRL_GLOBAL_PAUSE_ENI_OFFS)
+
+#define MV_XLG_MAC_PPFC_CTRL_DIP_BTS_677_EN_OFFS    9
+#define MV_XLG_MAC_PPFC_CTRL_DIP_BTS_677_EN_MASK    \
+    (0x00000001 << MV_XLG_MAC_PPFC_CTRL_DIP_BTS_677_EN_OFFS)
+
+/* Fc Dsa Tag 0 */
+#define MV_XLG_MAC_FC_DSA_TAG_0_REG                       (0x0068)
+#define MV_XLG_MAC_FC_DSA_TAG_0_DSATAGREG0_OFFS    0
+#define MV_XLG_MAC_FC_DSA_TAG_0_DSATAGREG0_MASK    \
+    (0x0000ffff << MV_XLG_MAC_FC_DSA_TAG_0_DSATAGREG0_OFFS)
+
+/* Fc Dsa Tag 1 */
+#define MV_XLG_MAC_FC_DSA_TAG_1_REG                       (0x006c)
+#define MV_XLG_MAC_FC_DSA_TAG_1_DSATAGREG1_OFFS    0
+#define MV_XLG_MAC_FC_DSA_TAG_1_DSATAGREG1_MASK    \
+    (0x0000ffff << MV_XLG_MAC_FC_DSA_TAG_1_DSATAGREG1_OFFS)
+
+/* Fc Dsa Tag 2 */
+#define MV_XLG_MAC_FC_DSA_TAG_2_REG                       (0x0070)
+#define MV_XLG_MAC_FC_DSA_TAG_2_DSATAGREG2_OFFS    0
+#define MV_XLG_MAC_FC_DSA_TAG_2_DSATAGREG2_MASK    \
+    (0x0000ffff << MV_XLG_MAC_FC_DSA_TAG_2_DSATAGREG2_OFFS)
+
+/* Fc Dsa Tag 3 */
+#define MV_XLG_MAC_FC_DSA_TAG_3_REG                       (0x0074)
+#define MV_XLG_MAC_FC_DSA_TAG_3_DSATAGREG3_OFFS    0
+#define MV_XLG_MAC_FC_DSA_TAG_3_DSATAGREG3_MASK    \
+    (0x0000ffff << MV_XLG_MAC_FC_DSA_TAG_3_DSATAGREG3_OFFS)
+
+/* Dic Budget Compensation */
+#define MV_XLG_MAC_DIC_BUDGET_COMPENSATION_REG            (0x0080)
+#define MV_XLG_MAC_DIC_BUDGET_COMPENSATION_DIC_COUNTER_TO_ADD_8BYTES_OFFS    0
+#define MV_XLG_MAC_DIC_BUDGET_COMPENSATION_DIC_COUNTER_TO_ADD_8BYTES_MASK    \
+    (0x0000ffff << MV_XLG_MAC_DIC_BUDGET_COMPENSATION_DIC_COUNTER_TO_ADD_8BYTES_OFFS)
+
+/* Port Mac Control4 */
+#define MV_XLG_PORT_MAC_CTRL4_REG                         (0x0084)
+#define MV_XLG_MAC_CTRL4_LLFC_GLOBAL_FC_ENABLE_OFFS    0
+#define MV_XLG_MAC_CTRL4_LLFC_GLOBAL_FC_ENABLE_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_LLFC_GLOBAL_FC_ENABLE_OFFS)
+
+#define MV_XLG_MAC_CTRL4_LED_STREAM_SELECT_OFFS    1
+#define MV_XLG_MAC_CTRL4_LED_STREAM_SELECT_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_LED_STREAM_SELECT_OFFS)
+
+#define MV_XLG_MAC_CTRL4_DEBUG_BUS_SELECT_OFFS    2
+#define MV_XLG_MAC_CTRL4_DEBUG_BUS_SELECT_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_DEBUG_BUS_SELECT_OFFS)
+
+#define MV_XLG_MAC_CTRL4_MASK_PCS_RESET_OFFS    3
+#define MV_XLG_MAC_CTRL4_MASK_PCS_RESET_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_MASK_PCS_RESET_OFFS)
+
+#define MV_XLG_MAC_CTRL4_ENABLE_SHORT_PREAMBLE_FOR_XLG_OFFS    4
+#define MV_XLG_MAC_CTRL4_ENABLE_SHORT_PREAMBLE_FOR_XLG_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_ENABLE_SHORT_PREAMBLE_FOR_XLG_OFFS)
+
+#define MV_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_OFFS    5
+#define MV_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_OFFS)
+
+#define MV_XLG_MAC_CTRL4_FORWARD_PFC_EN_OFFS    6
+#define MV_XLG_MAC_CTRL4_FORWARD_PFC_EN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_FORWARD_PFC_EN_OFFS)
+
+#define MV_XLG_MAC_CTRL4_FORWARD_UNKNOWN_FC_EN_OFFS    7
+#define MV_XLG_MAC_CTRL4_FORWARD_UNKNOWN_FC_EN_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_FORWARD_UNKNOWN_FC_EN_OFFS)
+
+#define MV_XLG_MAC_CTRL4_USE_XPCS_OFFS    8
+#define MV_XLG_MAC_CTRL4_USE_XPCS_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_USE_XPCS_OFFS)
+
+#define MV_XLG_MAC_CTRL4_DMA_INTERFACE_IS_64_BIT_OFFS    9
+#define MV_XLG_MAC_CTRL4_DMA_INTERFACE_IS_64_BIT_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_DMA_INTERFACE_IS_64_BIT_OFFS)
+
+#define MV_XLG_MAC_CTRL4_TX_DMA_INTERFACE_BITS_OFFS    10
+#define MV_XLG_MAC_CTRL4_TX_DMA_INTERFACE_BITS_MASK    \
+    (0x00000003 << MV_XLG_MAC_CTRL4_TX_DMA_INTERFACE_BITS_OFFS)
+
+#define MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_OFFS    12
+#define MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_OFFS)
+
+/* Port Mac Control5 */
+#define MV_XLG_PORT_MAC_CTRL5_REG                         (0x0088)
+#define MV_XLG_MAC_CTRL5_TXIPGLENGTH_OFFS    0
+#define MV_XLG_MAC_CTRL5_TXIPGLENGTH_MASK    \
+    (0x0000000f << MV_XLG_MAC_CTRL5_TXIPGLENGTH_OFFS)
+
+#define MV_XLG_MAC_CTRL5_PREAMBLELENGTHTX_OFFS    4
+#define MV_XLG_MAC_CTRL5_PREAMBLELENGTHTX_MASK    \
+    (0x00000007 << MV_XLG_MAC_CTRL5_PREAMBLELENGTHTX_OFFS)
+
+#define MV_XLG_MAC_CTRL5_PREAMBLELENGTHRX_OFFS    7
+#define MV_XLG_MAC_CTRL5_PREAMBLELENGTHRX_MASK    \
+    (0x00000007 << MV_XLG_MAC_CTRL5_PREAMBLELENGTHRX_OFFS)
+
+#define MV_XLG_MAC_CTRL5_TXNUMCRCBYTES_OFFS    10
+#define MV_XLG_MAC_CTRL5_TXNUMCRCBYTES_MASK    \
+    (0x00000007 << MV_XLG_MAC_CTRL5_TXNUMCRCBYTES_OFFS)
+
+#define MV_XLG_MAC_CTRL5_RXNUMCRCBYTES_OFFS    13
+#define MV_XLG_MAC_CTRL5_RXNUMCRCBYTES_MASK    \
+    (0x00000007 << MV_XLG_MAC_CTRL5_RXNUMCRCBYTES_OFFS)
+
+/* External Control */
+#define MV_XLG_MAC_EXT_CTRL_REG                           (0x0090)
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL0_OFFS    0
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL0_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL0_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL1_OFFS    1
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL1_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL1_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL2_OFFS    2
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL2_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL2_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL3_OFFS    3
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL3_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL3_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL4_OFFS    4
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL4_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL4_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL5_OFFS    5
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL5_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL5_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL6_OFFS    6
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL6_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL6_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL7_OFFS    7
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL7_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL7_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL8_OFFS    8
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL8_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL8_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL9_OFFS    9
+#define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL9_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL9_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_10_OFFS    10
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_10_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXT_CTRL_10_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_11_OFFS    11
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_11_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXT_CTRL_11_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_12_OFFS    12
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_12_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXT_CTRL_12_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_13_OFFS    13
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_13_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXT_CTRL_13_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_14_OFFS    14
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_14_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXT_CTRL_14_OFFS)
+
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_15_OFFS    15
+#define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_15_MASK    \
+    (0x00000001 << MV_XLG_MAC_EXT_CTRL_EXT_CTRL_15_OFFS)
+
+/* Macro Control */
+#define MV_XLG_MAC_MACRO_CTRL_REG                         (0x0094)
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_0_OFFS    0
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_0_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_0_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_1_OFFS    1
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_1_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_1_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_2_OFFS    2
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_2_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_2_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_3_OFFS    3
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_3_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_3_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_4_OFFS    4
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_4_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_4_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_5_OFFS    5
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_5_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_5_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_6_OFFS    6
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_6_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_6_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_7_OFFS    7
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_7_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_7_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_8_OFFS    8
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_8_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_8_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_9_OFFS    9
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_9_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_9_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_10_OFFS    10
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_10_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_10_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_11_OFFS    11
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_11_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_11_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_12_OFFS    12
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_12_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_12_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_13_OFFS    13
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_13_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_13_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_14_OFFS    14
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_14_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_14_OFFS)
+
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_15_OFFS    15
+#define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_15_MASK    \
+    (0x00000001 << MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_15_OFFS)
+
+#define MV_XLG_MAC_DIC_PPM_IPG_REDUCE_REG                 (0x0094)
+
+/* Port Interrupt Cause */
+#define MV_XLG_INTERRUPT_CAUSE_REG                        (0x0014)
+/* Port Interrupt Mask */
+#define MV_XLG_INTERRUPT_MASK_REG                         (0x0018)
+#define MV_XLG_INTERRUPT_LINK_CHANGE_OFFS    1
+#define MV_XLG_INTERRUPT_LINK_CHANGE_MASK    \
+    (0x1 << MV_XLG_INTERRUPT_LINK_CHANGE_OFFS)
+
+/* Port Interrupt Summary Cause */
+#define MV_XLG_EXTERNAL_INTERRUPT_CAUSE_REG               (0x0058)
+/* Port Interrupt Summary Mask */
+#define MV_XLG_EXTERNAL_INTERRUPT_MASK_REG                (0x005C)
+#define MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_OFFS    1
+#define MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_MASK    \
+    (0x1 << MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_OFFS)
+
+/*All PPV22 Addresses are 40-bit */
+#define MVPP22_ADDR_HIGH_SIZE    8
+#define MVPP22_ADDR_HIGH_MASK    ((1<<MVPP22_ADDR_HIGH_SIZE) - 1)
+#define MVPP22_ADDR_MASK    (0xFFFFFFFFFF)
+
+/* Desc addr shift */
+#define MVPP21_DESC_ADDR_SHIFT    0 /*Applies to RXQ, AGGR_TXQ*/
+#define MVPP22_DESC_ADDR_SHIFT    8 /*Applies to RXQ, AGGR_TXQ*/
+
+/* AXI Bridge Registers */
+#define MVPP22_AXI_BM_WR_ATTR_REG                         0x4100
+#define MVPP22_AXI_BM_RD_ATTR_REG                         0x4104
+#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG                0x4110
+#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG                  0x4114
+#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG                  0x4118
+#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG                  0x411c
+#define MVPP22_AXI_RX_DATA_WR_ATTR_REG                    0x4120
+#define MVPP22_AXI_TX_DATA_RD_ATTR_REG                    0x4130
+#define MVPP22_AXI_RD_NORMAL_CODE_REG                     0x4150
+#define MVPP22_AXI_RD_SNP_CODE_REG                        0x4154
+#define MVPP22_AXI_WR_NORMAL_CODE_REG                     0x4160
+#define MVPP22_AXI_WR_SNP_CODE_REG                        0x4164
+
+#define MVPP22_AXI_RD_CODE_MASK    0x33
+#define MVPP22_AXI_WR_CODE_MASK    0x33
+
+#define MVPP22_AXI_ATTR_CACHE_OFFS    0
+#define MVPP22_AXI_ATTR_CACHE_SIZE    4
+#define MVPP22_AXI_ATTR_CACHE_MASK    0x0000000F
+
+#define MVPP22_AXI_ATTR_QOS_OFFS    4
+#define MVPP22_AXI_ATTR_QOS_SIZE    4
+#define MVPP22_AXI_ATTR_QOS_MASK    0x000000F0
+
+#define MVPP22_AXI_ATTR_TC_OFFS    8
+#define MVPP22_AXI_ATTR_TC_SIZE    4
+#define MVPP22_AXI_ATTR_TC_MASK    0x00000F00
+
+#define MVPP22_AXI_ATTR_DOMAIN_OFFS    12
+#define MVPP22_AXI_ATTR_DOMAIN_SIZE    2
+#define MVPP22_AXI_ATTR_DOMAIN_MASK    0x00003000
+
+#define MVPP22_AXI_ATTR_SNOOP_CNTRL_BIT    BIT(16)
+
+/* PHY address register */
+#define MV_SMI_PHY_ADDRESS_REG(n)                         (0xC + 0x4 * (n))
+#define MV_SMI_PHY_ADDRESS_PHYAD_OFFS    0
+#define MV_SMI_PHY_ADDRESS_PHYAD_MASK    \
+  (0x1F << MV_SMI_PHY_ADDRESS_PHYAD_OFFS)
+
+/* Marvell tag types */
+enum Mvpp2TagType {
+  MVPP2_TAG_TYPE_NONE = 0,
+  MVPP2_TAG_TYPE_MH   = 1,
+  MVPP2_TAG_TYPE_DSA  = 2,
+  MVPP2_TAG_TYPE_EDSA = 3,
+  MVPP2_TAG_TYPE_VLAN = 4,
+  MVPP2_TAG_TYPE_LAST = 5
+};
+
+/* Parser constants */
+#define MVPP2_PRS_TCAM_SRAM_SIZE    256
+#define MVPP2_PRS_TCAM_WORDS    6
+#define MVPP2_PRS_SRAM_WORDS    4
+#define MVPP2_PRS_FLOW_ID_SIZE    64
+#define MVPP2_PRS_FLOW_ID_MASK    0x3f
+#define MVPP2_PRS_TCAM_ENTRY_INVALID    1
+#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT    BIT(5)
+#define MVPP2_PRS_IPV4_HEAD    0x40
+#define MVPP2_PRS_IPV4_HEAD_MASK    0xf0
+#define MVPP2_PRS_IPV4_MC    0xe0
+#define MVPP2_PRS_IPV4_MC_MASK    0xf0
+#define MVPP2_PRS_IPV4_BC_MASK    0xff
+#define MVPP2_PRS_IPV4_IHL    0x5
+#define MVPP2_PRS_IPV4_IHL_MASK    0xf
+#define MVPP2_PRS_IPV6_MC    0xff
+#define MVPP2_PRS_IPV6_MC_MASK    0xff
+#define MVPP2_PRS_IPV6_HOP_MASK    0xff
+#define MVPP2_PRS_TCAM_PROTO_MASK    0xff
+#define MVPP2_PRS_TCAM_PROTO_MASK_L    0x3f
+#define MVPP2_PRS_DBL_VLANS_MAX    100
+
+/*
+ * Tcam structure:
+ * - lookup ID - 4 bits
+ * - port ID - 1 byte
+ * - additional information - 1 byte
+ * - header data - 8 bytes
+ * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
+ */
+#define MVPP2_PRS_AI_BITS    8
+#define MVPP2_PRS_PORT_MASK    0xff
+#define MVPP2_PRS_LU_MASK    0xf
+#define MVPP2_PRS_TCAM_DATA_BYTE(offs)    (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
+#define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)    (((offs) * 2) - ((offs) % 2)  + 2)
+#define MVPP2_PRS_TCAM_AI_BYTE    16
+#define MVPP2_PRS_TCAM_PORT_BYTE    17
+#define MVPP2_PRS_TCAM_LU_BYTE    20
+#define MVPP2_PRS_TCAM_EN_OFFS(offs)    ((offs) + 2)
+#define MVPP2_PRS_TCAM_INV_WORD    5
+/* Tcam entries ID */
+#define MVPP2_PE_DROP_ALL    0
+#define MVPP2_PE_FIRST_FREE_TID    1
+#define MVPP2_PE_LAST_FREE_TID    (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
+#define MVPP2_PE_IP6_EXT_PROTO_UN    (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
+#define MVPP2_PE_MAC_MC_IP6    (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
+#define MVPP2_PE_IP6_ADDR_UN    (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
+#define MVPP2_PE_IP4_ADDR_UN    (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
+#define MVPP2_PE_LAST_DEFAULT_FLOW    (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
+#define MVPP2_PE_FIRST_DEFAULT_FLOW    (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
+#define MVPP2_PE_EDSA_TAGGED    (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
+#define MVPP2_PE_EDSA_UNTAGGED    (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
+#define MVPP2_PE_DSA_TAGGED    (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
+#define MVPP2_PE_DSA_UNTAGGED    (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
+#define MVPP2_PE_ETYPE_EDSA_TAGGED    (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
+#define MVPP2_PE_ETYPE_EDSA_UNTAGGED    (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
+#define MVPP2_PE_ETYPE_DSA_TAGGED    (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
+#define MVPP2_PE_ETYPE_DSA_UNTAGGED    (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
+#define MVPP2_PE_MH_DEFAULT    (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
+#define MVPP2_PE_DSA_DEFAULT    (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
+#define MVPP2_PE_IP6_PROTO_UN    (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
+#define MVPP2_PE_IP4_PROTO_UN    (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
+#define MVPP2_PE_ETH_TYPE_UN    (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
+#define MVPP2_PE_VLAN_DBL    (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
+#define MVPP2_PE_VLAN_NONE    (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
+#define MVPP2_PE_MAC_MC_ALL    (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
+#define MVPP2_PE_MAC_PROMISCUOUS    (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
+#define MVPP2_PE_MAC_NON_PROMISCUOUS    (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
+
+/*
+ * Sram structure
+ * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
+ */
+#define MVPP2_PRS_SRAM_RI_OFFS    0
+#define MVPP2_PRS_SRAM_RI_WORD    0
+#define MVPP2_PRS_SRAM_RI_CTRL_OFFS    32
+#define MVPP2_PRS_SRAM_RI_CTRL_WORD    1
+#define MVPP2_PRS_SRAM_RI_CTRL_BITS    32
+#define MVPP2_PRS_SRAM_SHIFT_OFFS    64
+#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT    72
+#define MVPP2_PRS_SRAM_UDF_OFFS    73
+#define MVPP2_PRS_SRAM_UDF_BITS    8
+#define MVPP2_PRS_SRAM_UDF_MASK    0xff
+#define MVPP2_PRS_SRAM_UDF_SIGN_BIT    81
+#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS    82
+#define MVPP2_PRS_SRAM_UDF_TYPE_MASK    0x7
+#define MVPP2_PRS_SRAM_UDF_TYPE_L3    1
+#define MVPP2_PRS_SRAM_UDF_TYPE_L4    4
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS    85
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK    0x3
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD    1
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD    2
+#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD    3
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS    87
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS    2
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK    0x3
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD    0
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD    2
+#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD    3
+#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS    89
+#define MVPP2_PRS_SRAM_AI_OFFS    90
+#define MVPP2_PRS_SRAM_AI_CTRL_OFFS    98
+#define MVPP2_PRS_SRAM_AI_CTRL_BITS    8
+#define MVPP2_PRS_SRAM_AI_MASK    0xff
+#define MVPP2_PRS_SRAM_NEXT_LU_OFFS    106
+#define MVPP2_PRS_SRAM_NEXT_LU_MASK    0xf
+#define MVPP2_PRS_SRAM_LU_DONE_BIT    110
+#define MVPP2_PRS_SRAM_LU_GEN_BIT    111
+
+/* Sram result info bits assignment */
+#define MVPP2_PRS_RI_MAC_ME_MASK    0x1
+#define MVPP2_PRS_RI_DSA_MASK    0x2
+#define MVPP2_PRS_RI_VLAN_MASK    0xc
+#define MVPP2_PRS_RI_VLAN_NONE    ~(BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_VLAN_SINGLE    BIT(2)
+#define MVPP2_PRS_RI_VLAN_DOUBLE    BIT(3)
+#define MVPP2_PRS_RI_VLAN_TRIPLE    (BIT(2) | BIT(3))
+#define MVPP2_PRS_RI_CPU_CODE_MASK    0x70
+#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC    BIT(4)
+#define MVPP2_PRS_RI_L2_CAST_MASK    0x600
+#define MVPP2_PRS_RI_L2_UCAST    ~(BIT(9) | BIT(10))
+#define MVPP2_PRS_RI_L2_MCAST    BIT(9)
+#define MVPP2_PRS_RI_L2_BCAST    BIT(10)
+#define MVPP2_PRS_RI_PPPOE_MASK    0x800
+#define MVPP2_PRS_RI_L3_PROTO_MASK    0x7000
+#define MVPP2_PRS_RI_L3_UN    ~(BIT(12) | BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_IP4    BIT(12)
+#define MVPP2_PRS_RI_L3_IP4_OPT    BIT(13)
+#define MVPP2_PRS_RI_L3_IP4_OTHER    (BIT(12) | BIT(13))
+#define MVPP2_PRS_RI_L3_IP6    BIT(14)
+#define MVPP2_PRS_RI_L3_IP6_EXT    (BIT(12) | BIT(14))
+#define MVPP2_PRS_RI_L3_ARP    (BIT(13) | BIT(14))
+#define MVPP2_PRS_RI_L3_ADDR_MASK    0x18000
+#define MVPP2_PRS_RI_L3_UCAST    ~(BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_L3_MCAST    BIT(15)
+#define MVPP2_PRS_RI_L3_BCAST    (BIT(15) | BIT(16))
+#define MVPP2_PRS_RI_IP_FRAG_MASK    0x20000
+#define MVPP2_PRS_RI_UDF3_MASK    0x300000
+#define MVPP2_PRS_RI_UDF3_RX_SPECIAL    BIT(21)
+#define MVPP2_PRS_RI_L4_PROTO_MASK    0x1c00000
+#define MVPP2_PRS_RI_L4_TCP    BIT(22)
+#define MVPP2_PRS_RI_L4_UDP    BIT(23)
+#define MVPP2_PRS_RI_L4_OTHER    (BIT(22) | BIT(23))
+#define MVPP2_PRS_RI_UDF7_MASK    0x60000000
+#define MVPP2_PRS_RI_UDF7_IP6_LITE    BIT(29)
+#define MVPP2_PRS_RI_DROP_MASK    0x80000000
+
+/* Sram additional info bits assignment */
+#define MVPP2_PRS_IPV4_DIP_AI_BIT    BIT(0)
+#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT    BIT(0)
+#define MVPP2_PRS_IPV6_EXT_AI_BIT    BIT(1)
+#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT    BIT(2)
+#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT    BIT(3)
+#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT    BIT(4)
+#define MVPP2_PRS_SINGLE_VLAN_AI    0
+#define MVPP2_PRS_DBL_VLAN_AI_BIT    BIT(7)
+
+/* DSA/EDSA type */
+#define MVPP2_PRS_TAGGED    TRUE
+#define MVPP2_PRS_UNTAGGED    FALSE
+#define MVPP2_PRS_EDSA    TRUE
+#define MVPP2_PRS_DSA    FALSE
+
+/* MAC entries, shadow udf */
+enum Mvpp2PrsUdf {
+  MVPP2_PRS_UDF_MAC_DEF,
+  MVPP2_PRS_UDF_MAC_RANGE,
+  MVPP2_PRS_UDF_L2_DEF,
+  MVPP2_PRS_UDF_L2_DEF_COPY,
+  MVPP2_PRS_UDF_L2_USER,
+};
+
+/* Lookup ID */
+enum Mvpp2PrsLookup {
+  MVPP2_PRS_LU_MH,
+  MVPP2_PRS_LU_MAC,
+  MVPP2_PRS_LU_DSA,
+  MVPP2_PRS_LU_VLAN,
+  MVPP2_PRS_LU_L2,
+  MVPP2_PRS_LU_PPPOE,
+  MVPP2_PRS_LU_IP4,
+  MVPP2_PRS_LU_IP6,
+  MVPP2_PRS_LU_FLOWS,
+  MVPP2_PRS_LU_LAST,
+};
+
+/* L3 cast enum */
+enum Mvpp2PrsL3Cast {
+  MVPP2_PRS_L3_UNI_CAST,
+  MVPP2_PRS_L3_MULTI_CAST,
+  MVPP2_PRS_L3_BROAD_CAST
+};
+
+/* Classifier constants */
+#define MVPP2_CLS_FLOWS_TBL_SIZE    512
+#define MVPP2_CLS_FLOWS_TBL_DATA_WORDS    3
+#define MVPP2_CLS_LKP_TBL_SIZE    64
+
+/* BM cookie (32 bits) definition */
+#define MVPP2_BM_COOKIE_POOL_OFFS    8
+#define MVPP2_BM_COOKIE_CPU_OFFS    24
+
+/*
+ * The MVPP2_TX_DESC and MVPP2_RX_DESC structures describe the
+ * layout of the transmit and reception DMA descriptors, and their
+ * layout is therefore defined by the hardware design
+ */
+#define MVPP2_TXD_L3_OFF_SHIFT    0
+#define MVPP2_TXD_IP_HLEN_SHIFT    8
+#define MVPP2_TXD_L4_CSUM_FRAG    BIT(13)
+#define MVPP2_TXD_L4_CSUM_NOT    BIT(14)
+#define MVPP2_TXD_IP_CSUM_DISABLE    BIT(15)
+#define MVPP2_TXD_PADDING_DISABLE    BIT(23)
+#define MVPP2_TXD_L4_UDP    BIT(24)
+#define MVPP2_TXD_L3_IP6    BIT(26)
+#define MVPP2_TXD_L_DESC    BIT(28)
+#define MVPP2_TXD_F_DESC    BIT(29)
+
+#define MVPP2_RXD_ERR_SUMMARY    BIT(15)
+#define MVPP2_RXD_ERR_CODE_MASK    (BIT(13) | BIT(14))
+#define MVPP2_RXD_ERR_CRC    0x0
+#define MVPP2_RXD_ERR_OVERRUN    BIT(13)
+#define MVPP2_RXD_ERR_RESOURCE    (BIT(13) | BIT(14))
+#define MVPP2_RXD_BM_POOL_ID_OFFS    16
+#define MVPP2_RXD_BM_POOL_ID_MASK    (BIT(16) | BIT(17) | BIT(18))
+#define MVPP2_RXD_HWF_SYNC    BIT(21)
+#define MVPP2_RXD_L4_CSUM_OK    BIT(22)
+#define MVPP2_RXD_IP4_HEADER_ERR    BIT(24)
+#define MVPP2_RXD_L4_TCP    BIT(25)
+#define MVPP2_RXD_L4_UDP    BIT(26)
+#define MVPP2_RXD_L3_IP4    BIT(28)
+#define MVPP2_RXD_L3_IP6    BIT(30)
+#define MVPP2_RXD_BUF_HDR    BIT(31)
+
+typedef struct {
+  UINT32 command;   /* Options used by HW for packet transmitting.*/
+  UINT8  PacketOffset; /* the offset from the buffer beginning */
+  UINT8  PhysTxq;    /* destination queue ID     */
+  UINT16 DataSize;   /* data size of transmitted packet in bytes */
+  UINT64 RsrvdHwCmd1; /* HwCmd (BM, PON, PNC) */
+  UINT64 BufPhysAddrHwCmd2;
+  UINT64 BufCookieBmQsetHwCmd3;
+} MVPP2_TX_DESC;
+
+typedef struct {
+  UINT32 status;    /* info about received packet   */
+  UINT16 reserved1;   /* ParserInfo (for future use, PnC)  */
+  UINT16 DataSize;   /* size of received packet in bytes */
+  UINT16 RsrvdGem;   /* GemPortId (for future use, PON)  */
+  UINT16 RsrvdL4csum;  /* CsumL4 (for future use, PnC)  */
+  UINT32 RsrvdTimestamp;
+  UINT64 BufPhysAddrKeyHash;
+  UINT64 BufCookieBmQsetClsInfo;
+} MVPP2_RX_DESC;
+
+union Mvpp2PrsTcamEntry {
+  UINT32 Word[MVPP2_PRS_TCAM_WORDS];
+  UINT8 Byte[MVPP2_PRS_TCAM_WORDS * 4];
+};
+
+union Mvpp2PrsSramEntry {
+  UINT32 Word[MVPP2_PRS_SRAM_WORDS];
+  UINT8 Byte[MVPP2_PRS_SRAM_WORDS * 4];
+};
+
+typedef struct {
+  UINT32 Index;
+  union Mvpp2PrsTcamEntry Tcam;
+  union Mvpp2PrsSramEntry Sram;
+} MVPP2_PRS_ENTRY;
+
+typedef struct {
+  BOOLEAN Valid;
+  BOOLEAN Finish;
+
+  /* Lookup ID */
+  INT32 Lu;
+
+  /* User defined offset */
+  INT32 Udf;
+
+  /* Result info */
+  UINT32 Ri;
+  UINT32 RiMask;
+} MVPP2_PRS_SHADOW;
+
+typedef struct {
+  UINT32 Index;
+  UINT32 Data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
+} MVPP2_CLS_FLOW_ENTRY;
+
+typedef struct {
+  UINT32 Lkpid;
+  UINT32 Way;
+  UINT32 Data;
+} MVPP2_CLS_LOOKUP_ENTRY;
+
+typedef struct {
+  UINT32 NextBuffPhysAddr;
+  UINT32 NextBuffVirtAddr;
+  UINT16 ByteCount;
+  UINT16 info;
+  UINT8  reserved1;   /* BmQset (for future use, BM)   */
+} MVPP2_BUFF_HDR;
+
+/* Buffer header info bits */
+#define MVPP2_B_HDR_INFO_MC_ID_MASK    0xfff
+#define MVPP2_B_HDR_INFO_MC_ID(info)    ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
+#define MVPP2_B_HDR_INFO_LAST_OFFS    12
+#define MVPP2_B_HDR_INFO_LAST_MASK    BIT(12)
+#define MVPP2_B_HDR_INFO_IS_LAST(info)    ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
+
+/* Net Complex */
+enum MvNetcTopology {
+  MV_NETC_GE_MAC0_RXAUI_L23 = BIT(0),
+  MV_NETC_GE_MAC0_RXAUI_L45 = BIT(1),
+  MV_NETC_GE_MAC0_XAUI = BIT(2),
+  MV_NETC_GE_MAC2_SGMII = BIT(3),
+  MV_NETC_GE_MAC3_SGMII = BIT(4),
+  MV_NETC_GE_MAC3_RGMII = BIT(5),
+};
+
+enum MvNetcPhase {
+  MV_NETC_FIRST_PHASE,
+  MV_NETC_SECOND_PHASE,
+};
+
+enum MvNetcSgmiiXmiMode {
+  MV_NETC_GBE_SGMII,
+  MV_NETC_GBE_XMII,
+};
+
+enum MvNetcMiiMode {
+  MV_NETC_GBE_RGMII,
+  MV_NETC_GBE_MII,
+};
+
+enum MvNetcLanes {
+  MV_NETC_LANE_23,
+  MV_NETC_LANE_45,
+};
+
+/* Port related */
+enum MvReset {
+  RESET,
+  UNRESET
+};
+
+enum Mvpp2Command {
+  MVPP2_START,    /* Start     */
+  MVPP2_STOP,    /* Stop     */
+  MVPP2_PAUSE,    /* Pause    */
+  MVPP2_RESTART    /* Restart  */
+};
+
+enum MvPortDuplex {
+  MV_PORT_DUPLEX_AN,
+  MV_PORT_DUPLEX_HALF,
+  MV_PORT_DUPLEX_FULL
+};
+
+#endif /* __MVPP2_LIB_HW__ */
diff --git a/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Drivers/Net/Pp2Dxe/Pp2Dxe.c
new file mode 100644
index 0000000..8de2473
--- /dev/null
+++ b/Drivers/Net/Pp2Dxe/Pp2Dxe.c
@@ -0,0 +1,1271 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <Protocol/DevicePath.h>
+#include <Protocol/DriverBinding.h>
+#include <Protocol/SimpleNetwork.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NetLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include "Mvpp2LibHw.h"
+#include "Mvpp2Lib.h"
+#include "Pp2Dxe.h"
+
+#define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (status); } while(0)
+
+STATIC MVPP2_SHARED *Mvpp2Shared;
+STATIC BUFFER_LOCATION BufferLocation;
+STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate = {
+  {
+    {
+      MESSAGING_DEVICE_PATH,
+      MSG_MAC_ADDR_DP,
+      {
+        (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)),
+        (UINT8) ((sizeof(MAC_ADDR_DEVICE_PATH)) >> 8)
+      }
+    },
+    { { 0 } },
+    0
+  },
+  {
+    END_DEVICE_PATH_TYPE,
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0 }
+  }
+};
+
+EFI_SIMPLE_NETWORK_PROTOCOL Pp2SnpTemplate = {
+  EFI_SIMPLE_NETWORK_PROTOCOL_REVISION,                 // Revision
+  Pp2SnpStart,                                          // Start
+  Pp2SnpStop,                                           // Stop
+  Pp2DxeSnpInitialize,                                  // Initialize
+  Pp2SnpReset,                                          // Reset
+  Pp2SnpShutdown,                                       // Shutdown
+  Pp2SnpReceiveFilters,                                 // ReceiveFilters
+  Pp2SnpStationAddress,                                 // StationAddress
+  Pp2SnpNetStat,                                        // Statistics
+  Pp2SnpIpToMac,                                        // MCastIpToMac
+  NULL,                                                 // NvData
+  Pp2SnpGetStatus,                                      // GetStatus
+  Pp2SnpTransmit,                                       // Transmit
+  Pp2SnpReceive,                                        // Receive
+  NULL,                                                 // WaitForPacket
+  NULL                                                  // Mode
+};
+
+EFI_SIMPLE_NETWORK_MODE Pp2SnpModeTemplate = {
+  EfiSimpleNetworkStopped,                              // State
+  NET_ETHER_ADDR_LEN,                                   // HwAddressSize
+  sizeof (ETHER_HEAD),                                  // MediaHeaderSize
+  EFI_PAGE_SIZE,                                        // MaxPacketSize
+  0,                                                    // NvRamSize
+  0,                                                    // MvRamAccessSize
+  EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+  EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+  EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |
+  EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |
+  EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST,     // ReceiveFilterMask
+  EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+  EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+  EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST,                 // ReceiveFilterSetting
+  MAX_MCAST_FILTER_CNT,                                 // MacMCastFilterCount
+  0,                                                    // MCastFilterCount
+  {
+    { { 0 } }
+  },                                                    // MCastFilter
+  {
+    { 0 }
+  },                                                    // CurrentAddress
+  {
+    { 0 }
+  },                                                    // BroadcastAddress
+  {
+    { 0 }
+  },                                                    // Permanent Address
+  NET_IFTYPE_ETHERNET,                                  // IfType
+  TRUE,                                                 // MacAddressChangeable
+  FALSE,                                                // MultipleTxSupported
+  TRUE,                                                 // MediaPresentSupported
+  FALSE                                                 // MediaPresent
+};
+
+#define QueueNext(off)  ((((off) + 1) >= QUEUE_DEPTH) ? 0 : ((off) + 1))
+
+STATIC
+EFI_STATUS
+QueueInsert (
+  IN PP2DXE_CONTEXT *Pp2Context,
+  IN VOID *Buffer
+  )
+{
+
+  if (QueueNext (Pp2Context->CompletionQueueTail) == Pp2Context->CompletionQueueHead) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Pp2Context->CompletionQueue[Pp2Context->CompletionQueueTail] = Buffer;
+  Pp2Context->CompletionQueueTail = QueueNext (Pp2Context->CompletionQueueTail);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID *
+QueueRemove (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  VOID *Buffer;
+
+  if (Pp2Context->CompletionQueueTail == Pp2Context->CompletionQueueHead) {
+    return NULL;
+  }
+
+  Buffer = Pp2Context->CompletionQueue[Pp2Context->CompletionQueueHead];
+  Pp2Context->CompletionQueue[Pp2Context->CompletionQueueHead] = NULL;
+  Pp2Context->CompletionQueueHead = QueueNext (Pp2Context->CompletionQueueHead);
+
+  return Buffer;
+}
+
+STATIC
+EFI_STATUS
+Pp2DxeBmPoolInit (
+  VOID
+  )
+{
+  INTN Index;
+  UINT8 *PoolAddr;
+  UINT32 PoolSize = (sizeof(VOID *) * MVPP2_BM_SIZE) * 2 + MVPP2_BM_POOL_PTR_ALIGN;
+
+  ASSERT(MVPP2_BM_POOL_PTR_ALIGN >= sizeof(UINTN));
+
+  PoolSize = (sizeof(VOID *) * MVPP2_BM_SIZE) * 2 + MVPP2_BM_POOL_PTR_ALIGN;
+
+  for (Index = 0; Index < MVPP2_BM_POOLS_NUM; Index++) {
+    /* BmIrqClear */
+    Mvpp2BmIrqClear(Mvpp2Shared, Index);
+  }
+
+  Mvpp2Shared->BmPools = AllocateZeroPool (sizeof(MVPP2_BMS_POOL));
+
+  if (Mvpp2Shared->BmPools == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  PoolAddr = UncachedAllocateAlignedZeroPool (PoolSize, MVPP2_BM_POOL_PTR_ALIGN);
+  if (PoolAddr == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Mvpp2Shared->BmPools->Id = MVPP2_BM_POOL;
+  Mvpp2Shared->BmPools->VirtAddr = (UINT32 *)PoolAddr;
+  Mvpp2Shared->BmPools->PhysAddr = (UINTN)PoolAddr;
+
+  Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools, MVPP2_BM_SIZE);
+
+  return EFI_SUCCESS;
+}
+
+/* Enable and fill BM pool */
+STATIC
+EFI_STATUS
+Pp2DxeBmStart (
+  VOID
+  )
+{
+  UINT8 *Buff, *BuffPhys;
+  INTN Index;
+
+  ASSERT(BM_ALIGN >= sizeof(UINTN));
+
+  Mvpp2BmPoolCtrl(Mvpp2Shared, MVPP2_BM_POOL, MVPP2_START);
+  Mvpp2BmPoolBufsizeSet(Mvpp2Shared, Mvpp2Shared->BmPools, RX_BUFFER_SIZE);
+
+  /* Fill BM pool with Buffers */
+  for (Index = 0; Index < MVPP2_BM_SIZE; Index++) {
+    Buff = (UINT8 *)(BufferLocation.RxBuffers + (Index * RX_BUFFER_SIZE));
+    if (Buff == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+
+    BuffPhys = ALIGN_POINTER(Buff, BM_ALIGN);
+    Mvpp2BmPoolPut(Mvpp2Shared, MVPP2_BM_POOL, (UINTN)BuffPhys, (UINTN)BuffPhys);
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+Pp2DxeStartDev (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+
+  /* Config classifier decoding table */
+  Mvpp2ClsPortConfig(Port);
+  Mvpp2ClsOversizeRxqSet(Port);
+  MvGop110PortEventsMask(Port);
+  MvGop110PortEnable(Port);
+
+  /* Enable transmit and receive */
+  Mvpp2EgressEnable(Port);
+  Mvpp2IngressEnable(Port);
+}
+
+STATIC
+EFI_STATUS
+Pp2DxeSetupRxqs (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  INTN Queue;
+  EFI_STATUS Status;
+  MVPP2_RX_QUEUE *Rxq;
+
+  for (Queue = 0; Queue < RxqNumber; Queue++) {
+    Rxq = &Pp2Context->Port.Rxqs[Queue];
+    Rxq->DescsPhys = (DmaAddrT)Rxq->Descs;
+    if (Rxq->Descs == NULL) {
+      Status = EFI_OUT_OF_RESOURCES;
+      goto ErrCleanup;
+    }
+
+    Mvpp2RxqHwInit(&Pp2Context->Port, Rxq);
+  }
+
+  return EFI_SUCCESS;
+
+ErrCleanup:
+  Mvpp2CleanupRxqs(&Pp2Context->Port);
+  return Status;
+}
+
+STATIC
+EFI_STATUS
+Pp2DxeSetupTxqs (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  INTN Queue;
+  MVPP2_TX_QUEUE *Txq;
+  EFI_STATUS Status;
+
+  for (Queue = 0; Queue < TxqNumber; Queue++) {
+    Txq = &Pp2Context->Port.Txqs[Queue];
+    Txq->DescsPhys = (DmaAddrT)Txq->Descs;
+    if (Txq->Descs == NULL) {
+      Status = EFI_OUT_OF_RESOURCES;
+      goto ErrCleanup;
+    }
+
+    Mvpp2TxqHwInit(&Pp2Context->Port, Txq);
+  }
+
+  return EFI_SUCCESS;
+
+ErrCleanup:
+  Mvpp2CleanupTxqs(&Pp2Context->Port);
+  return Status;
+}
+
+STATIC
+EFI_STATUS
+Pp2DxeSetupAggrTxqs (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  MVPP2_TX_QUEUE *AggrTxq;
+
+  AggrTxq = Mvpp2Shared->AggrTxqs;
+  AggrTxq->DescsPhys = (DmaAddrT)AggrTxq->Descs;
+  if (AggrTxq->Descs == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Mvpp2AggrTxqHwInit(AggrTxq, AggrTxq->Size, 0, Mvpp2Shared);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+Pp2DxeOpen (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+  UINT8 MacBcast[NET_ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+  UINT8 DevAddr[NET_ETHER_ADDR_LEN];
+  INTN Ret;
+  EFI_STATUS Status;
+
+  CopyMem (DevAddr, Pp2Context->Snp.Mode->CurrentAddress.Addr, NET_ETHER_ADDR_LEN);
+
+  Ret = Mvpp2PrsMacDaAccept(Mvpp2Shared, Port->Id, MacBcast, TRUE);
+  if (Ret != 0) {
+    return EFI_DEVICE_ERROR;
+  }
+  Ret = Mvpp2PrsMacDaAccept(Mvpp2Shared, Port->Id, DevAddr, TRUE);
+  if (Ret != 0) {
+    return EFI_DEVICE_ERROR;
+  }
+  Ret = Mvpp2PrsTagModeSet(Mvpp2Shared, Port->Id, MVPP2_TAG_TYPE_MH);
+  if (Ret != 0) {
+    return EFI_DEVICE_ERROR;
+  }
+  Ret = Mvpp2PrsDefFlow(Port);
+  if (Ret != 0) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = Pp2DxeSetupRxqs(Pp2Context);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = Pp2DxeSetupTxqs(Pp2Context);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = Pp2DxeSetupAggrTxqs(Pp2Context);
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Pp2DxeStartDev(Pp2Context);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+Pp2DxeLatePortInitialize (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+  INTN Queue;
+
+  Port->TxRingSize = MVPP2_MAX_TXD;
+  Port->RxRingSize = MVPP2_MAX_RXD;
+
+  Mvpp2EgressDisable(Port);
+  MvGop110PortEventsMask(Port);
+  MvGop110PortDisable(Port);
+
+  Port->Txqs = AllocateZeroPool (sizeof(MVPP2_TX_QUEUE) * TxqNumber);
+  if (Port->Txqs == NULL) {
+    DEBUG((DEBUG_ERROR, "Failed to allocate Txqs\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  /* Use preallocated area */
+  Port->Txqs[0].Descs = BufferLocation.TxDescs;
+
+  for (Queue = 0; Queue < TxqNumber; Queue++) {
+    MVPP2_TX_QUEUE *Txq = &Port->Txqs[Queue];
+
+    Txq->Id = Mvpp2TxqPhys(Port->Id, Queue);
+    Txq->LogId = Queue;
+    Txq->Size = Port->TxRingSize;
+  }
+
+  Port->Rxqs = AllocateZeroPool (sizeof(MVPP2_RX_QUEUE) * RxqNumber);
+  if (Port->Rxqs == NULL) {
+    DEBUG((DEBUG_ERROR, "Failed to allocate Rxqs\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Port->Rxqs[0].Descs = BufferLocation.RxDescs;
+
+  for (Queue = 0; Queue < TxqNumber; Queue++) {
+    MVPP2_RX_QUEUE *Rxq = &Port->Rxqs[Queue];
+
+    Rxq->Id = Queue + Port->FirstRxq;
+    Rxq->Size = Port->RxRingSize;
+  }
+
+  Mvpp2IngressDisable(Port);
+
+  Mvpp2DefaultsSet(Port);
+
+  return Pp2DxeOpen(Pp2Context);
+}
+
+STATIC
+EFI_STATUS
+Pp2DxeLateInitialize (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+  EFI_STATUS Status;
+
+  if (!Pp2Context->LateInitialized) {
+    /* Full init on first call */
+    Status = Pp2DxeLatePortInitialize(Pp2Context);
+    if (EFI_ERROR(Status)) {
+      DEBUG((DEBUG_ERROR, "Pp2Dxe: late initialization failed\n"));
+      return Status;
+    }
+
+    /* Attach pool to Rxq */
+    Mvpp2RxqLongPoolSet(Port, 0, MVPP2_BM_POOL);
+    Mvpp2RxqShortPoolSet(Port, 0, MVPP2_BM_POOL);
+
+    /*
+     * Mark this port being fully initialized,
+     * otherwise it will be inited again
+     * during next networking transaction,
+     * including memory allocatation for
+     * TX/RX queue, PHY connect/configuration
+     * and address decode configuration.
+     */
+    Pp2Context->LateInitialized = TRUE;
+  } else {
+    /* Upon all following calls, this is enough */
+    MvGop110PortEventsMask(Port);
+    MvGop110PortEnable(Port);
+  }
+  return 0;
+}
+
+EFI_STATUS
+Pp2DxePhyInitialize (
+  PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  EFI_STATUS Status;
+  UINT8 *PhyAddresses;
+
+  PhyAddresses = PcdGetPtr (PcdPhySmiAddresses);
+  Status = gBS->LocateProtocol (
+               &gMarvellPhyProtocolGuid,
+               NULL,
+               (VOID **) &Pp2Context->Phy
+             );
+
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  if (PhyAddresses[Pp2Context->Instance] == 0xff) {
+    /* PHY iniitalization not required */
+    return EFI_SUCCESS;
+  }
+
+  Status = Pp2Context->Phy->Init(
+               Pp2Context->Phy,
+               PhyAddresses[Pp2Context->Instance],
+               Pp2Context->Port.PhyInterface,
+               &Pp2Context->PhyDev
+             );
+
+  if (EFI_ERROR(Status) && Status != EFI_TIMEOUT) {
+    return Status;
+  }
+
+  Pp2Context->Phy->Status(Pp2Context->Phy, Pp2Context->PhyDev);
+  Mvpp2SmiPhyAddrCfg(&Pp2Context->Port, Pp2Context->Port.GopIndex, Pp2Context->PhyDev->Addr);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+Pp2DxeSnpInitialize (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN UINTN                       ExtraRxBufferSize  OPTIONAL,
+  IN UINTN                       ExtraTxBufferSize  OPTIONAL
+  )
+{
+  EFI_STATUS Status;
+  PP2DXE_CONTEXT *Pp2Context;
+  Pp2Context = INSTANCE_FROM_SNP(This);
+  UINT32 State = This->Mode->State;
+  EFI_TPL SavedTpl;
+
+  if (ExtraRxBufferSize != 0 || ExtraTxBufferSize != 0) {
+    DEBUG((DEBUG_ERROR, "Pp2Dxe%d: non-zero buffer requests\n", Pp2Context->Instance));
+    return EFI_UNSUPPORTED;
+  }
+
+  SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  if (State != EfiSimpleNetworkStarted) {
+    switch (State) {
+    case EfiSimpleNetworkInitialized:
+      DEBUG((DEBUG_WARN, "Pp2Dxe%d: already initialized\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_SUCCESS);
+    case EfiSimpleNetworkStopped:
+      DEBUG((DEBUG_WARN, "Pp2Dxe%d: network stopped\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_NOT_STARTED);
+    default:
+      DEBUG((DEBUG_ERROR, "Pp2Dxe%d: wrong state\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_DEVICE_ERROR);
+    }
+  }
+
+  /* Successfully started, change state to Initialized */
+  This->Mode->State = EfiSimpleNetworkInitialized;
+
+  if (Pp2Context->Initialized) {
+    ReturnUnlock(SavedTpl, EFI_SUCCESS);
+  }
+
+  Pp2Context->Initialized = TRUE;
+
+  Status = Pp2DxePhyInitialize(Pp2Context);
+  if (EFI_ERROR(Status)) {
+    ReturnUnlock (SavedTpl, Status);
+  }
+
+  Status = Pp2DxeLateInitialize(Pp2Context);
+  ReturnUnlock (SavedTpl, Status);
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpStart (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL  *This
+  )
+{
+  PP2DXE_CONTEXT *Pp2Context;
+  UINT32 State = This->Mode->State;
+  EFI_TPL SavedTpl;
+
+  SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+  Pp2Context = INSTANCE_FROM_SNP(This);
+
+  if (State != EfiSimpleNetworkStopped) {
+    switch (State) {
+    case EfiSimpleNetworkStarted:
+    case EfiSimpleNetworkInitialized:
+      DEBUG((DEBUG_WARN, "Pp2Dxe%d: already initialized\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_ALREADY_STARTED);
+    default:
+      DEBUG((DEBUG_ERROR, "Pp2Dxe%d: wrong state\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_DEVICE_ERROR);
+    }
+  }
+
+  This->Mode->State = EfiSimpleNetworkStarted;
+  ReturnUnlock (SavedTpl, EFI_SUCCESS);
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpStop (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL  *This
+  )
+{
+  EFI_TPL SavedTpl;
+  SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+  PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(This);
+  UINT32 State = This->Mode->State;
+
+  if (State != EfiSimpleNetworkStarted && State != EfiSimpleNetworkInitialized) {
+    switch (State) {
+    case EfiSimpleNetworkStopped:
+      DEBUG((DEBUG_WARN, "Pp2Dxe%d: not started\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_NOT_STARTED);
+    default:
+      DEBUG((DEBUG_ERROR, "Pp2Dxe%d: wrong state\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_DEVICE_ERROR);
+    }
+  }
+
+  This->Mode->State = EfiSimpleNetworkStopped;
+  ReturnUnlock (SavedTpl, EFI_SUCCESS);
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpReset (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN BOOLEAN                     ExtendedVerification
+  )
+{
+  return EFI_SUCCESS;
+}
+
+VOID
+EFIAPI
+Pp2DxeHalt (
+  IN EFI_EVENT Event,
+  IN VOID *Context
+  )
+{
+  PP2DXE_CONTEXT *Pp2Context = Context;
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+  STATIC BOOLEAN CommonPartHalted = FALSE;
+
+  if (!CommonPartHalted) {
+    Mvpp2BmStop(Mvpp2Shared, MVPP2_BM_POOL);
+    CommonPartHalted = TRUE;
+  }
+
+  Mvpp2TxqDrainSet(Port, 0, TRUE);
+  Mvpp2IngressDisable(Port);
+  Mvpp2EgressDisable(Port);
+
+  MvGop110PortEventsMask(Port);
+  MvGop110PortDisable(Port);
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpShutdown (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+  )
+{
+  EFI_TPL SavedTpl;
+  SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+  PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(This);
+  UINT32 State = This->Mode->State;
+
+  if (State != EfiSimpleNetworkInitialized) {
+    switch (State) {
+    case EfiSimpleNetworkStopped:
+      DEBUG((DEBUG_WARN, "Pp2Dxe%d: not started\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_NOT_STARTED);
+    case EfiSimpleNetworkStarted:
+    /* Fall through */
+    default:
+      DEBUG((DEBUG_ERROR, "Pp2Dxe%d: wrong state\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_DEVICE_ERROR);
+    }
+  }
+
+  ReturnUnlock (SavedTpl, EFI_SUCCESS);
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpReceiveFilters (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN UINT32                      Enable,
+  IN UINT32                      Disable,
+  IN BOOLEAN                     ResetMCastFilter,
+  IN UINTN                       MCastFilterCnt     OPTIONAL,
+  IN EFI_MAC_ADDRESS             *MCastFilter OPTIONAL
+  )
+{
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpStationAddress (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+  IN BOOLEAN Reset,
+  IN EFI_MAC_ADDRESS *NewMac
+)
+{
+  PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(Snp);
+  PP2_DEVICE_PATH *Pp2DevicePath = Pp2Context->DevicePath;
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+  UINT32 State = Snp->Mode->State;
+  EFI_TPL SavedTpl;
+  INTN Ret;
+
+  /* Check Snp instance */
+  ASSERT(Snp != NULL);
+
+  /* Serialize access to data and registers */
+  SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  /* Check that driver was started and initialised */
+  if (State != EfiSimpleNetworkInitialized) {
+    switch (State) {
+    case EfiSimpleNetworkStopped:
+      DEBUG((DEBUG_WARN, "Pp2Dxe%d: not started\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_NOT_STARTED);
+    case EfiSimpleNetworkStarted:
+    /* Fall through */
+    default:
+      DEBUG((DEBUG_ERROR, "Pp2Dxe%d: wrong state\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_DEVICE_ERROR);
+    }
+  }
+
+  /* Invalidate old unicast address in parser */
+  Ret = Mvpp2PrsMacDaAccept(Mvpp2Shared, Port->Id, Snp->Mode->CurrentAddress.Addr, FALSE);
+  if (Ret != 0) {
+    DEBUG((DEBUG_ERROR, "Pp2SnpStationAddress - Fail\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (Reset) {
+    CopyMem (Snp->Mode->CurrentAddress.Addr, Snp->Mode->PermanentAddress.Addr, NET_ETHER_ADDR_LEN);
+    CopyMem (NewMac->Addr, Snp->Mode->PermanentAddress.Addr, NET_ETHER_ADDR_LEN);
+    CopyMem (Pp2DevicePath->Pp2Mac.MacAddress.Addr, Snp->Mode->PermanentAddress.Addr, NET_ETHER_ADDR_LEN);
+  } else {
+    if (NewMac == NULL) {
+      ReturnUnlock (SavedTpl, EFI_INVALID_PARAMETER);
+    }
+    CopyMem (Snp->Mode->CurrentAddress.Addr, NewMac->Addr, NET_ETHER_ADDR_LEN);
+    CopyMem (Pp2DevicePath->Pp2Mac.MacAddress.Addr, NewMac->Addr, NET_ETHER_ADDR_LEN);
+  }
+
+  /* Update parser with new unicast address */
+  Ret = Mvpp2PrsMacDaAccept(Mvpp2Shared, Port->Id, Snp->Mode->CurrentAddress.Addr, TRUE);
+  if (Ret != 0) {
+    DEBUG((DEBUG_ERROR, "Pp2SnpStationAddress - Fail\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  /* Restore TPL and return */
+  gBS->RestoreTPL (SavedTpl);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpNetStat (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN BOOLEAN                     Reset,
+  IN OUT UINTN                   *StatisticsSize   OPTIONAL,
+  OUT EFI_NETWORK_STATISTICS     *StatisticsTable  OPTIONAL
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpIpToMac (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN BOOLEAN                     IPv6,
+  IN EFI_IP_ADDRESS              *IP,
+  OUT EFI_MAC_ADDRESS            *MAC
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpNvData (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN BOOLEAN                     ReadWrite,
+  IN UINTN                       Offset,
+  IN UINTN                       BufferSize,
+  IN OUT VOID                    *Buffer
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpGetStatus (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+  OUT UINT32                     *InterruptStatus OPTIONAL,
+  OUT VOID                       **TxBuf OPTIONAL
+  )
+{
+  PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(Snp);
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+  BOOLEAN LinkUp;
+  EFI_TPL SavedTpl;
+
+  SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  if (!Pp2Context->Initialized)
+    ReturnUnlock(SavedTpl, EFI_NOT_READY);
+
+  LinkUp = Port->AlwaysUp ? TRUE : MvGop110PortIsLinkUp(Port);
+
+  if (LinkUp != Snp->Mode->MediaPresent) {
+    DEBUG((DEBUG_INFO, "Pp2Dxe%d: Link ", Pp2Context->Instance));
+    DEBUG((DEBUG_INFO, LinkUp ? "up\n" : "down\n"));
+  }
+  Snp->Mode->MediaPresent = LinkUp;
+
+  if (TxBuf != NULL) {
+    *TxBuf = QueueRemove (Pp2Context);
+  }
+
+  ReturnUnlock(SavedTpl, EFI_SUCCESS);
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpTransmit (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN UINTN                       HeaderSize,
+  IN UINTN                       BufferSize,
+  IN VOID                        *Buffer,
+  IN EFI_MAC_ADDRESS             *SrcAddr  OPTIONAL,
+  IN EFI_MAC_ADDRESS             *DestAddr OPTIONAL,
+  IN UINT16                      *EtherTypePtr OPTIONAL
+  )
+{
+  PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(This);
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+  MVPP2_TX_QUEUE *AggrTxq = Mvpp2Shared->AggrTxqs;
+  MVPP2_TX_DESC *TxDesc;
+  EFI_STATUS Status;
+  INTN PollingCount;
+  INTN TxSent;
+  UINT8 *DataPtr = Buffer;
+  UINT16 EtherType;
+  UINT32 State = This->Mode->State;
+  EFI_TPL SavedTpl;
+
+  if (This == NULL || Buffer == NULL) {
+    DEBUG((DEBUG_ERROR, "Pp2Dxe: NULL Snp or Buffer\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (HeaderSize != 0) {
+    ASSERT (HeaderSize == This->Mode->MediaHeaderSize);
+    ASSERT (EtherTypePtr != NULL);
+    ASSERT (DestAddr != NULL);
+  }
+
+  SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+
+  /* Check that driver was started and initialised */
+  if (State != EfiSimpleNetworkInitialized) {
+    switch (State) {
+    case EfiSimpleNetworkStopped:
+      DEBUG((DEBUG_WARN, "Pp2Dxe%d: not started\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_NOT_STARTED);
+    case EfiSimpleNetworkStarted:
+    /* Fall through */
+    default:
+      DEBUG((DEBUG_ERROR, "Pp2Dxe%d: wrong state\n", Pp2Context->Instance));
+      ReturnUnlock (SavedTpl, EFI_DEVICE_ERROR);
+    }
+  }
+
+  if (!This->Mode->MediaPresent) {
+    DEBUG((DEBUG_ERROR, "Pp2Dxe: link not ready\n"));
+    ReturnUnlock(SavedTpl, EFI_NOT_READY);
+  }
+
+  EtherType = HTONS (*EtherTypePtr);
+
+  /* Fetch next descriptor */
+  TxDesc = Mvpp2TxqNextDescGet(AggrTxq);
+
+  if (!TxDesc) {
+    DEBUG((DEBUG_ERROR, "No tx descriptor to use\n"));
+    ReturnUnlock(SavedTpl, EFI_OUT_OF_RESOURCES);
+  }
+
+  if (HeaderSize != 0) {
+    CopyMem(DataPtr, DestAddr, NET_ETHER_ADDR_LEN);
+
+    if (SrcAddr != NULL)
+      CopyMem(DataPtr + NET_ETHER_ADDR_LEN, SrcAddr, NET_ETHER_ADDR_LEN);
+    else
+      CopyMem(DataPtr + NET_ETHER_ADDR_LEN, &This->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);
+
+    CopyMem(DataPtr + NET_ETHER_ADDR_LEN * 2, &EtherType, 2);
+  }
+
+  /* Set descriptor fields */
+  TxDesc->command =  MVPP2_TXD_IP_CSUM_DISABLE | MVPP2_TXD_L4_CSUM_NOT |
+                     MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
+  TxDesc->DataSize = BufferSize;
+  TxDesc->PacketOffset = (PhysAddrT)DataPtr & MVPP2_TX_DESC_ALIGN;
+  Mvpp2x2TxdescPhysAddrSet((PhysAddrT)DataPtr & ~MVPP2_TX_DESC_ALIGN, TxDesc);
+  TxDesc->PhysTxq = Mvpp2TxqPhys(Port->Id, 0);
+
+  InvalidateDataCacheRange (DataPtr, BufferSize);
+
+  /* Issue send */
+  Mvpp2AggrTxqPendDescAdd(Port, 1);
+
+  /*
+   * Egress processing:
+   * Wait until packet is passed from per-cpu aggregated queue
+   * to physical per-port TXQ.
+   */
+  PollingCount = 0;
+  TxSent = Mvpp2AggrTxqPendDescNumGet(Mvpp2Shared, 0);
+  do {
+    if (PollingCount++ > MVPP2_TX_SEND_MAX_POLLING_COUNT) {
+      DEBUG((DEBUG_ERROR, "Pp2Dxe: transmit polling failed\n"));
+      ReturnUnlock(SavedTpl, EFI_TIMEOUT);
+    }
+    TxSent = Mvpp2AggrTxqPendDescNumGet(Mvpp2Shared, 0);
+  } while (TxSent);
+
+  /* Wait for packet to be transmitted by hardware. */
+  PollingCount = 0;
+  TxSent = Mvpp2TxqSentDescProc(Port, &Port->Txqs[0]);
+  while (!TxSent) {
+    if (PollingCount++ > MVPP2_TX_SEND_MAX_POLLING_COUNT) {
+      DEBUG((DEBUG_ERROR, "Pp2Dxe: transmit polling failed\n"));
+      ReturnUnlock(SavedTpl, EFI_TIMEOUT);
+    }
+    TxSent = Mvpp2TxqSentDescProc(Port, &Port->Txqs[0]);
+  }
+
+  /*
+   * At this point TxSent has increased - HW sent the packet
+   * Add buffer to completion queue and return.
+   */
+  Status = QueueInsert (Pp2Context, Buffer);
+  ReturnUnlock (SavedTpl, Status);
+}
+
+EFI_STATUS
+EFIAPI
+Pp2SnpReceive (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  OUT UINTN                      *HeaderSize OPTIONAL,
+  IN OUT UINTN                   *BufferSize,
+  OUT VOID                       *Buffer,
+  OUT EFI_MAC_ADDRESS            *SrcAddr OPTIONAL,
+  OUT EFI_MAC_ADDRESS            *DstAddr OPTIONAL,
+  OUT UINT16                     *EtherType OPTIONAL
+  )
+{
+  INTN ReceivedPackets;
+  PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(This);
+  PP2DXE_PORT *Port = &Pp2Context->Port;
+  UINTN PhysAddr, VirtAddr;
+  EFI_STATUS Status = EFI_SUCCESS;
+  EFI_TPL SavedTpl;
+  UINT32 StatusReg;
+  INTN PoolId;
+  UINTN PktLength;
+  UINT8 *DataPtr;
+  MVPP2_RX_DESC *RxDesc;
+  MVPP2_RX_QUEUE *Rxq = &Port->Rxqs[0];
+
+  ASSERT (Port != NULL);
+  ASSERT (Rxq != NULL);
+
+  SavedTpl = gBS->RaiseTPL (TPL_CALLBACK);
+  ReceivedPackets = Mvpp2RxqReceived(Port, Rxq->Id);
+
+  if (ReceivedPackets == 0) {
+    ReturnUnlock(SavedTpl, EFI_NOT_READY);
+  }
+
+  /* Process one packet per call */
+  RxDesc = Mvpp2RxqNextDescGet(Rxq);
+  StatusReg = RxDesc->status;
+
+  /* extract addresses from descriptor */
+  PhysAddr = RxDesc->BufPhysAddrKeyHash & MVPP22_ADDR_MASK;
+  VirtAddr = RxDesc->BufCookieBmQsetClsInfo & MVPP22_ADDR_MASK;
+
+  /* Drop packets with error or with buffer header (MC, SG) */
+  if ((StatusReg & MVPP2_RXD_BUF_HDR) || (StatusReg & MVPP2_RXD_ERR_SUMMARY)) {
+    DEBUG((DEBUG_WARN, "Pp2Dxe: dropping packet\n"));
+    Status = EFI_DEVICE_ERROR;
+    goto drop;
+  }
+
+  PktLength = (UINTN) RxDesc->DataSize - 2;
+  if (PktLength > *BufferSize) {
+    *BufferSize = PktLength;
+    DEBUG((DEBUG_ERROR, "Pp2Dxe: buffer too small\n"));
+    ReturnUnlock(SavedTpl, EFI_BUFFER_TOO_SMALL);
+  }
+
+  CopyMem (Buffer, (VOID*) (PhysAddr + 2), PktLength);
+  *BufferSize = PktLength;
+
+  if (HeaderSize != NULL) {
+    *HeaderSize = Pp2Context->Snp.Mode->MediaHeaderSize;
+  }
+
+  DataPtr = Buffer;
+
+  /* Extract the destination address */
+  if (DstAddr != NULL) {
+    ZeroMem (DstAddr, sizeof(EFI_MAC_ADDRESS));
+    CopyMem (DstAddr, &DataPtr[0], NET_ETHER_ADDR_LEN);
+  }
+
+  /* Get the source address */
+  if (SrcAddr != NULL) {
+    ZeroMem (SrcAddr, sizeof(EFI_MAC_ADDRESS));
+    CopyMem (SrcAddr, &DataPtr[6], NET_ETHER_ADDR_LEN);
+  }
+
+  /* Obtain Ether Type */
+  if (EtherType != NULL) {
+    *EtherType = NTOHS (*(UINT16 *)(&DataPtr[12]));
+  }
+
+drop:
+  /* Refill: pass packet back to BM */
+  PoolId = (StatusReg & MVPP2_RXD_BM_POOL_ID_MASK) >> MVPP2_RXD_BM_POOL_ID_OFFS;
+  Mvpp2BmPoolPut(Mvpp2Shared, PoolId, PhysAddr, VirtAddr);
+
+  /* Update counters with 1 packet received and 1 packet refilled */
+  Mvpp2RxqStatusUpdate(Port, Rxq->Id, 1, 1);
+
+  ReturnUnlock(SavedTpl, Status);
+}
+
+EFI_STATUS
+Pp2DxeSnpInstall (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  EFI_HANDLE Handle = NULL;
+  EFI_STATUS Status;
+  PP2_DEVICE_PATH *Pp2DevicePath;
+  EFI_SIMPLE_NETWORK_MODE *SnpMode;
+
+  Pp2DevicePath = AllocateCopyPool (sizeof (PP2_DEVICE_PATH), &Pp2DevicePathTemplate);
+  if (Pp2DevicePath == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  SnpMode = AllocateZeroPool (sizeof (EFI_SIMPLE_NETWORK_MODE));
+  if (SnpMode == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  /* Copy SNP data from templates */
+  CopyMem (&Pp2Context->Snp, &Pp2SnpTemplate, sizeof (EFI_SIMPLE_NETWORK_PROTOCOL));
+  CopyMem (SnpMode, &Pp2SnpModeTemplate, sizeof (EFI_SIMPLE_NETWORK_MODE));
+
+  /* Handle device path of the controller */
+  Pp2DevicePath->Pp2Mac.MacAddress.Addr[5] = Pp2Context->Instance + 1;
+  Pp2Context->Signature = PP2DXE_SIGNATURE;
+  Pp2Context->DevicePath = Pp2DevicePath;
+  Pp2DevicePath->Pp2Mac.IfType = SnpMode->IfType;
+
+  /* Update SNP Mode */
+  CopyMem (SnpMode->CurrentAddress.Addr, Pp2DevicePath->Pp2Mac.MacAddress.Addr, NET_ETHER_ADDR_LEN);
+  CopyMem (SnpMode->PermanentAddress.Addr, Pp2DevicePath->Pp2Mac.MacAddress.Addr, NET_ETHER_ADDR_LEN);
+  ZeroMem (&SnpMode->MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));
+  SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
+
+  Pp2Context->Snp.Mode = SnpMode;
+
+  /* Install protocol */
+  Status = gBS->InstallMultipleProtocolInterfaces (
+      &Handle,
+      &gEfiSimpleNetworkProtocolGuid, &Pp2Context->Snp,
+      &gEfiDevicePathProtocolGuid, Pp2DevicePath,
+      NULL
+      );
+
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "Failed to install protocols.\n"));
+  }
+
+  return Status;
+}
+
+STATIC
+VOID
+Pp2DxeParsePortPcd (
+  IN PP2DXE_CONTEXT *Pp2Context
+  )
+{
+  UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed;
+
+  PortIds = PcdGetPtr (PcdPp2PortIds);
+  GopIndexes = PcdGetPtr (PcdPp2GopIndexes);
+  PhyConnectionTypes = PcdGetPtr (PcdPhyConnectionTypes);
+  AlwaysUp = PcdGetPtr (PcdPp2InterfaceAlwaysUp);
+  Speed = PcdGetPtr (PcdPp2InterfaceSpeed);
+
+  ASSERT (PcdGetSize (PcdPp2GopIndexes) == PcdGetSize (PcdPp2PortIds));
+  ASSERT (PcdGetSize (PcdPhyConnectionTypes) == PcdGetSize (PcdPp2PortIds));
+  ASSERT (PcdGetSize (PcdPp2InterfaceAlwaysUp) == PcdGetSize (PcdPp2PortIds));
+  ASSERT (PcdGetSize (PcdPp2InterfaceSpeed) == PcdGetSize (PcdPp2PortIds));
+
+  Pp2Context->Port.Id = PortIds[Pp2Context->Instance];
+  Pp2Context->Port.GopIndex = GopIndexes[Pp2Context->Instance];
+  Pp2Context->Port.PhyInterface = PhyConnectionTypes[Pp2Context->Instance];
+  Pp2Context->Port.AlwaysUp = AlwaysUp[Pp2Context->Instance];
+  Pp2Context->Port.Speed = Speed[Pp2Context->Instance];
+  Pp2Context->Port.GmacBase = PcdGet64 (PcdPp2GmacBaseAddress) +
+                              PcdGet32 (PcdPp2GmacDevSize) * Pp2Context->Port.GopIndex;
+  Pp2Context->Port.XlgBase = PcdGet64 (PcdPp2XlgBaseAddress) +
+                             PcdGet32 (PcdPp2XlgDevSize) * Pp2Context->Port.GopIndex;
+}
+
+EFI_STATUS
+EFIAPI
+Pp2DxeInitialise (
+  IN EFI_HANDLE ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  PP2DXE_CONTEXT *Pp2Context = NULL;
+  EFI_STATUS Status;
+  INTN Index;
+  VOID *BufferSpace;
+  UINT32 NetCompConfig = 0;
+  UINT8 NumPorts = PcdGet32 (PcdPp2NumPorts);
+
+  if (NumPorts == 0) {
+    DEBUG((DEBUG_ERROR, "Pp2Dxe: port number set to 0\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  /* Initialize private data */
+  Mvpp2Shared = AllocateZeroPool (sizeof (MVPP2_SHARED));
+  if (Mvpp2Shared == NULL) {
+    DEBUG((DEBUG_ERROR, "Allocation fail.\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress);
+  Mvpp2Shared->Rfu1Base = PcdGet64 (PcdPp2Rfu1BaseAddress);
+  Mvpp2Shared->SmiBase = PcdGet64 (PcdPp2SmiBaseAddress);
+  Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
+
+  /* Prepare buffers */
+  BufferSpace = UncachedAllocateAlignedZeroPool (BD_SPACE, MVPP2_BUFFER_ALIGN_SIZE);
+  if (BufferSpace == NULL) {
+    DEBUG((DEBUG_ERROR, "Failed to allocate buffer space\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  BufferLocation.TxDescs = BufferSpace;
+  BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)((UINTN)BufferSpace + MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC));
+  BufferLocation.RxDescs = (MVPP2_RX_DESC *)((UINTN)BufferSpace +
+                                             (MVPP2_MAX_TXD + MVPP2_AGGR_TXQ_SIZE) * sizeof(MVPP2_TX_DESC));
+  BufferLocation.RxBuffers = (DmaAddrT)(BufferSpace +
+                                        (MVPP2_MAX_TXD + MVPP2_AGGR_TXQ_SIZE) * sizeof(MVPP2_TX_DESC) +
+                                        MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC));
+
+  /* Initialize HW */
+  Mvpp2AxiConfig(Mvpp2Shared);
+  Pp2DxeBmPoolInit();
+  Mvpp2RxFifoInit(Mvpp2Shared);
+
+  Mvpp2Shared->PrsShadow = AllocateZeroPool (sizeof(MVPP2_PRS_SHADOW) * MVPP2_PRS_TCAM_SRAM_SIZE);
+  if (Mvpp2Shared->PrsShadow == NULL) {
+    DEBUG((DEBUG_ERROR, "Failed to allocate PrsShadow\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Status = Mvpp2PrsDefaultInit(Mvpp2Shared);
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "Failed to intialize prs\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  Mvpp2ClsInit(Mvpp2Shared);
+
+  Status = Pp2DxeBmStart();
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "Pp2Dxe: BM start error\n"));
+    return Status;
+  }
+
+  /* Initialize aggregated transmit queues */
+  Mvpp2Shared->AggrTxqs = AllocateZeroPool (sizeof(MVPP2_TX_QUEUE));
+  if (Mvpp2Shared->AggrTxqs == NULL) {
+    DEBUG((DEBUG_ERROR, "Failed to allocate aggregated Txqs\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Mvpp2Shared->AggrTxqs->Descs = BufferLocation.AggrTxDescs;
+  Mvpp2Shared->AggrTxqs->Id = 0;
+  Mvpp2Shared->AggrTxqs->LogId = 0;
+  Mvpp2Shared->AggrTxqs->Size = MVPP2_AGGR_TXQ_SIZE;
+
+  for (Index = 0; Index < NumPorts; Index++) {
+    Pp2Context = AllocateZeroPool (sizeof (PP2DXE_CONTEXT));
+    if (Pp2Context == NULL) {
+      /*
+       * If allocation fails, all resources allocated before will get freed
+       * at ExitBootServices, as only EfiBootServicesData is used.
+       */
+      DEBUG((DEBUG_ERROR, "Allocation fail.\n"));
+      return EFI_OUT_OF_RESOURCES;
+    }
+
+    /* Instances are enumerated from 0 */
+    Pp2Context->Instance = Index;
+
+    /* Install SNP protocol */
+    Status = Pp2DxeSnpInstall(Pp2Context);
+    if (EFI_ERROR(Status)) {
+      return Status;
+    }
+
+    Pp2DxeParsePortPcd(Pp2Context);
+    Pp2Context->Port.TxpNum = 1;
+    Pp2Context->Port.Priv = Mvpp2Shared;
+    Pp2Context->Port.FirstRxq = 4 * Pp2Context->Instance;
+
+    /* Gather accumulated configuration data of all ports' MAC's */
+    NetCompConfig |= MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port);
+
+    MvGop110PortInit(&Pp2Context->Port);
+    MvGop110FlCfg(&Pp2Context->Port);
+
+    Status = gBS->CreateEvent (
+                 EVT_SIGNAL_EXIT_BOOT_SERVICES,
+                 TPL_NOTIFY,
+                 Pp2DxeHalt,
+                 Pp2Context,
+                 &Pp2Context->EfiExitBootServicesEvent
+               );
+
+    if (EFI_ERROR(Status)) {
+      return Status;
+    }
+  }
+
+  MvGop110NetcInit(&Pp2Context->Port, NetCompConfig, MV_NETC_FIRST_PHASE);
+  MvGop110NetcInit(&Pp2Context->Port, NetCompConfig, MV_NETC_SECOND_PHASE);
+
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Drivers/Net/Pp2Dxe/Pp2Dxe.h
new file mode 100644
index 0000000..3bb0c4a
--- /dev/null
+++ b/Drivers/Net/Pp2Dxe/Pp2Dxe.h
@@ -0,0 +1,614 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __PP2_DXE_H__
+#define __PP2_DXE_H__
+
+#include <Protocol/Cpu.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/DriverBinding.h>
+#include <Protocol/Ip4.h>
+#include <Protocol/Ip6.h>
+#include <Protocol/MvPhy.h>
+#include <Protocol/SimpleNetwork.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NetLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UncachedMemoryAllocationLib.h>
+
+#include "Mvpp2LibHw.h"
+
+#define PP2DXE_SIGNATURE                    SIGNATURE_32('P', 'P', '2', 'D')
+#define INSTANCE_FROM_SNP(a)                CR((a), PP2DXE_CONTEXT, Snp, PP2DXE_SIGNATURE)
+
+/* OS API */
+#define Mvpp2Alloc(v)                       AllocateZeroPool(v)
+#define Mvpp2Free(p)                        FreePool(p)
+#define Mvpp2Memset(a, v, s)                SetMem((a), (s), (v))
+#define Mvpp2Mdelay(t)                      gBS->Stall((t) * 1000)
+#define Mvpp2Fls(v)                         1
+#define Mvpp2IsBroadcastEtherAddr(da)       1
+#define Mvpp2IsMulticastEtherAddr(da)       1
+#define Mvpp2Prefetch(v)                    do {} while(0);
+#define Mvpp2Printf(...)                    do {} while(0);
+#define Mvpp2SwapVariables(a,b)             do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
+#define Mvpp2SwapBytes16(x)                 SwapBytes16((x))
+#define Mvpp2Iphdr                          EFI_IP4_HEADER
+#define Mvpp2Ipv6hdr                        EFI_IP6_HEADER
+#define MVPP2_ALIGN(x, m)                   ALIGN_VALUE((x), (m))
+#define MVPP2_ENOMEM                        -1
+#define MVPP2_EINVAL                        -2
+#define MVPP2_ERANGE                        -3
+#define MVPP2_USEC_PER_SEC                  1000000L
+
+#define DmaAddrT                            UINTN
+#define PhysAddrT                           UINTN
+
+#define Upper32Bits(n)                      ((UINT32)(((n) >> 16) >> 16))
+#define Lower32Bits(n)                      ((UINT32)(n))
+
+#define ARCH_DMA_MINALIGN                   64
+
+/* Port speeds */
+#define MV_PORT_SPEED_10                    SPEED_10
+#define MV_PORT_SPEED_100                   SPEED_100
+#define MV_PORT_SPEED_1000                  SPEED_1000
+#define MV_PORT_SPEED_2500                  SPEED_2500
+#define MV_PORT_SPEED_10000                 SPEED_10000
+
+/* L2 and L3 protocol macros */
+#define MV_IPPR_TCP                         0
+#define MV_IPPR_UDP                         1
+#define MV_IPPR_IPIP                        2
+#define MV_IPPR_ICMPV6                      3
+#define MV_IPPR_IGMP                        4
+#define MV_ETH_P_IP                         5
+#define MV_ETH_P_IPV6                       6
+#define MV_ETH_P_PPP_SES                    7
+#define MV_ETH_P_ARP                        8
+#define MV_ETH_P_8021Q                      9
+#define MV_ETH_P_8021AD                     10
+#define MV_ETH_P_EDSA                       11
+#define MV_PPP_IP                           12
+#define MV_PPP_IPV6                         13
+#define MV_ETH_ALEN                         NET_ETHER_ADDR_LEN
+
+/* PHY modes */
+#define MV_MODE_SGMII                       PHY_CONNECTION_SGMII
+#define MV_MODE_RGMII                       PHY_CONNECTION_RGMII
+#define MV_MODE_XAUI                        PHY_CONNECTION_XAUI
+#define MV_MODE_RXAUI                       PHY_CONNECTION_RXAUI
+#define MV_MODE_QSGMII                      100
+#define PP2DXE_MAX_PHY                      2
+
+/* Gop */
+/* Sets the field located at the specified in data */
+#define U32_SET_FIELD(data, mask, val)     ((data) = (((data) & ~(mask)) | (val)))
+#define MV_RGMII_TX_FIFO_MIN_TH            0x41
+#define MV_SGMII_TX_FIFO_MIN_TH            0x5
+#define MV_SGMII2_5_TX_FIFO_MIN_TH         0xB
+
+/* BM constants */
+#define MVPP2_BM_POOLS_NUM                 8
+#define MVPP2_BM_LONG_BUF_NUM              1024
+#define MVPP2_BM_SHORT_BUF_NUM             2048
+#define MVPP2_BM_POOL_SIZE_MAX             (SIZE_16KB - MVPP2_BM_POOL_PTR_ALIGN/4)
+#define MVPP2_BM_POOL_PTR_ALIGN            128
+#define MVPP2_BM_SWF_LONG_POOL(Port)       ((Port > 2) ? 2 : Port)
+#define MVPP2_BM_SWF_SHORT_POOL            3
+#define MVPP2_BM_POOL                      0
+#define MVPP2_BM_SIZE                      32
+
+/*
+ * BM short pool packet Size
+ * These value assure that for SWF the total number
+ * of bytes allocated for each buffer will be 512
+ */
+#define MVPP2_BM_SHORT_PKT_SIZE            512
+
+/*
+ * Page table entries are set to 1MB, or multiples of 1MB
+ * (not < 1MB). driver uses less bd's so use 1MB bdspace.
+ */
+#define BD_SPACE                           (1 << 20)
+
+/* Buffer has to be aligned to 1M */
+#define MVPP2_BUFFER_ALIGN_SIZE            (1 << 20)
+
+/* RX constants */
+#define RX_BUFFER_SIZE                     (ALIGN_VALUE(MTU + WRAP, ARCH_DMA_MINALIGN))
+#define MVPP2_RXQ_OFFSET                   0
+#define BUFF_HDR_OFFS                      32
+#define BM_ALIGN                           32
+#define ETH_HLEN                           14
+
+/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
+#define WRAP                              (2 + ETH_HLEN + 4 + 32)
+#define MTU                               1500
+
+/*
+ * Maximum retries of checking, wheter HW really sent the packet
+ * after it was done is software.
+ */
+#define MVPP2_TX_SEND_MAX_POLLING_COUNT   10000
+
+/* Structures */
+typedef struct {
+  /* Physical number of this Tx queue */
+  UINT8 Id;
+
+  /* Logical number of this Tx queue */
+  UINT8 LogId;
+
+  /* Number of Tx DMA descriptors in the descriptor ring */
+  INT32 Size;
+
+  /* Number of currently used Tx DMA descriptor in the descriptor ring */
+  INT32 count;
+
+  UINT32 DonePktsCoal;
+
+  /* Virtual address of thex Tx DMA descriptors array */
+  MVPP2_TX_DESC *Descs;
+
+  /* DMA address of the Tx DMA descriptors array */
+  DmaAddrT DescsPhys;
+
+  /* Index of the last Tx DMA descriptor */
+  INT32 LastDesc;
+
+  /* Index of the next Tx DMA descriptor to process */
+  INT32 NextDescToProc;
+} MVPP2_TX_QUEUE;
+
+typedef struct {
+  /* RX queue number, in the range 0-31 for physical RXQs */
+  UINT8 Id;
+
+  /* Num of rx descriptors in the rx descriptor ring */
+  INT32 Size;
+
+  UINT32 PktsCoal;
+  UINT32 TimeCoal;
+
+  /* Virtual address of the RX DMA descriptors array */
+  MVPP2_RX_DESC *Descs;
+
+  /* DMA address of the RX DMA descriptors array */
+  DmaAddrT DescsPhys;
+
+  /* Index of the last RX DMA descriptor */
+  INT32 LastDesc;
+
+  /* Index of the next RX DMA descriptor to process */
+  INT32 NextDescToProc;
+
+  /* ID of Port to which physical RXQ is mapped */
+  INT32 Port;
+
+  /* Port's logic RXQ number to which physical RXQ is mapped */
+  INT32 LogicRxq;
+} MVPP2_RX_QUEUE;
+
+enum Mvpp2BmType {
+  MVPP2_BM_FREE,
+  MVPP2_BM_SWF_LONG,
+  MVPP2_BM_SWF_SHORT
+};
+
+typedef struct {
+  /* Pool number in the range 0-7 */
+  INT32 Id;
+  enum Mvpp2BmType type;
+
+  /* Buffer Pointers Pool External (BPPE) Size */
+  INT32 Size;
+  /* Number of buffers for this pool */
+  INT32 BufNum;
+  /* Pool buffer Size */
+  INT32 BufSize;
+  /* Packet Size */
+  INT32 PktSize;
+
+  /* BPPE virtual base address */
+  UINT32 *VirtAddr;
+  /* BPPE physical base address */
+  DmaAddrT PhysAddr;
+
+  /* Ports using BM pool */
+  UINT32 PortMap;
+} MVPP2_BMS_POOL;
+
+typedef struct Pp2DxePort PP2DXE_PORT;
+
+/* Shared Packet Processor resources */
+typedef struct {
+  /* Shared registers' base addresses */
+  UINT64 Base;
+  UINT64 Rfu1Base;
+  UINT64 SmiBase;
+  VOID *LmsBase;
+
+  /* List of pointers to Port structures */
+  PP2DXE_PORT **PortList;
+
+  /* Aggregated TXQs */
+  MVPP2_TX_QUEUE *AggrTxqs;
+
+  /* BM pools */
+  MVPP2_BMS_POOL *BmPools;
+
+  /* PRS shadow table */
+  MVPP2_PRS_SHADOW *PrsShadow;
+  /* PRS auxiliary table for double vlan entries control */
+  BOOLEAN *PrsDoubleVlans;
+
+  /* Tclk value */
+  UINT32 Tclk;
+} MVPP2_SHARED;
+
+/* Individual Port structure */
+struct Pp2DxePort {
+  UINT8 Id;
+  UINT8 GopIndex;
+
+  INT32 Irq;
+
+  MVPP2_SHARED *Priv;
+
+  /* Per-Port registers' base address */
+  UINT64 GmacBase;
+  UINT64 XlgBase;
+
+  MVPP2_RX_QUEUE *Rxqs;
+  MVPP2_TX_QUEUE *Txqs;
+
+  INT32 PktSize;
+
+  UINT32 PendingCauseRx;
+
+  /* Flags */
+  UINTN Flags;
+
+  UINT16 TxRingSize;
+  UINT16 RxRingSize;
+
+  INT32 PhyInterface;
+  BOOLEAN Link;
+  BOOLEAN Duplex;
+  BOOLEAN AlwaysUp;
+  PHY_SPEED Speed;
+
+  MVPP2_BMS_POOL *PoolLong;
+  MVPP2_BMS_POOL *PoolShort;
+
+  UINT8 TxpNum;
+
+  /* Index of first Port's physical RXQ */
+  UINT8 FirstRxq;
+};
+
+/* Structure for preallocation for buffer */
+typedef struct {
+  MVPP2_TX_DESC *TxDescs;
+  MVPP2_TX_DESC *AggrTxDescs;
+  MVPP2_RX_DESC *RxDescs;
+  DmaAddrT RxBuffers;
+} BUFFER_LOCATION;
+
+typedef struct {
+  MAC_ADDR_DEVICE_PATH      Pp2Mac;
+  EFI_DEVICE_PATH_PROTOCOL  End;
+} PP2_DEVICE_PATH;
+
+#define QUEUE_DEPTH 64
+typedef struct {
+  UINT32                      Signature;
+  INTN                        Instance;
+  EFI_HANDLE                  Controller;
+  EFI_LOCK                    Lock;
+  EFI_SIMPLE_NETWORK_PROTOCOL Snp;
+  MARVELL_PHY_PROTOCOL        *Phy;
+  PHY_DEVICE                  *PhyDev;
+  PP2DXE_PORT                 Port;
+  BOOLEAN                     Initialized;
+  BOOLEAN                     LateInitialized;
+  VOID                        *CompletionQueue[QUEUE_DEPTH];
+  UINTN                       CompletionQueueHead;
+  UINTN                       CompletionQueueTail;
+  EFI_EVENT                   EfiExitBootServicesEvent;
+  PP2_DEVICE_PATH             *DevicePath;
+} PP2DXE_CONTEXT;
+
+/* Inline helpers */
+STATIC
+inline
+VOID
+Mvpp2Write (
+  IN MVPP2_SHARED *Priv,
+  IN UINT32 Offset,
+  IN UINT32 data
+  )
+{
+  ASSERT (Priv->Base != 0);
+  MmioWrite32 (Priv->Base + Offset, data);
+}
+
+STATIC
+inline
+UINT32
+Mvpp2Read (
+  IN MVPP2_SHARED *Priv,
+  IN UINT32 Offset
+  )
+{
+  ASSERT (Priv->Base != 0);
+  return MmioRead32 (Priv->Base + Offset);
+}
+
+STATIC
+inline
+UINT32
+Mvpp2Rfu1Read (
+  IN MVPP2_SHARED *Priv,
+  UINT32 Offset
+  )
+{
+  ASSERT (Priv->Rfu1Base != 0);
+  return MmioRead32 (Priv->Rfu1Base + Offset);
+}
+
+STATIC
+inline
+UINT32
+Mvpp2Rfu1Write (
+  IN MVPP2_SHARED *Priv,
+  IN UINT32 Offset,
+  IN UINT32 Data
+  )
+{
+  ASSERT (Priv->Rfu1Base != 0);
+  return MmioWrite32 (Priv->Rfu1Base + Offset, Data);
+}
+
+STATIC
+inline
+UINT32
+Mvpp2SmiRead (
+  IN MVPP2_SHARED *Priv,
+  IN UINT32 Offset
+  )
+{
+  ASSERT (Priv->SmiBase != 0);
+  return MmioRead32 (Priv->SmiBase + Offset);
+}
+
+STATIC
+inline
+UINT32
+Mvpp2SmiWrite (
+  IN MVPP2_SHARED *Priv,
+  IN UINT32 Offset,
+  IN UINT32 Data
+  )
+{
+  ASSERT (Priv->SmiBase != 0);
+  return MmioWrite32 (Priv->SmiBase + Offset, Data);
+}
+
+STATIC
+inline
+VOID
+Mvpp2GmacWrite (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Offset,
+  IN UINT32 Data
+  )
+{
+  ASSERT (Port->Priv->Base != 0);
+  MmioWrite32 (Port->Priv->Base + Offset, Data);
+}
+
+STATIC
+inline
+UINT32
+Mvpp2GmacRead (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Offset
+  )
+{
+  ASSERT (Port->Priv->Base != 0);
+  return MmioRead32 (Port->Priv->Base + Offset);
+}
+
+STATIC
+inline
+VOID
+MvGop110GmacWrite (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Offset,
+  IN UINT32 Data
+  )
+{
+  ASSERT (Port->GmacBase != 0);
+  MmioWrite32 (Port->GmacBase + Offset, Data);
+}
+
+STATIC
+inline
+UINT32
+MvGop110GmacRead (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Offset
+  )
+{
+  ASSERT (Port->GmacBase != 0);
+  return MmioRead32 (Port->GmacBase + Offset);
+}
+
+STATIC
+inline
+VOID
+Mvpp2XlgWrite (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Offset,
+  IN UINT32 Data
+  )
+{
+  ASSERT (Port->XlgBase != 0);
+  MmioWrite32 (Port->XlgBase + Offset, Data);
+}
+
+STATIC
+inline
+UINT32
+Mvpp2XlgRead (
+  IN PP2DXE_PORT *Port,
+  IN UINT32 Offset
+  )
+{
+  ASSERT (Port->XlgBase != 0);
+  return MmioRead32 (Port->XlgBase + Offset);
+}
+
+/* SNP callbacks */
+EFI_STATUS
+EFIAPI
+Pp2SnpStart (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpStop (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2DxeSnpInitialize (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN UINTN                       ExtraRxBufferSize OPTIONAL,
+  IN UINTN                       ExtraTxBufferSize OPTIONAL
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpReset (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN BOOLEAN                     ExtendedVerification
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpShutdown (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpReceiveFilters (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN UINT32                      Enable,
+  IN UINT32                      Disable,
+  IN BOOLEAN                     ResetMCastFilter,
+  IN UINTN                       MCastFilterCnt OPTIONAL,
+  IN EFI_MAC_ADDRESS             *MCastFilter OPTIONAL
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpStationAddress (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+  IN BOOLEAN Reset,
+  IN EFI_MAC_ADDRESS *NewMac
+);
+
+EFI_STATUS
+EFIAPI
+Pp2SnpNetStat (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN BOOLEAN                     Reset,
+  IN OUT UINTN                   *StatisticsSize OPTIONAL,
+  OUT EFI_NETWORK_STATISTICS     *StatisticsTable OPTIONAL
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpIpToMac (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN BOOLEAN                     IPv6,
+  IN EFI_IP_ADDRESS              *IP,
+  OUT EFI_MAC_ADDRESS            *MAC
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpGetStatus (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+  OUT UINT32                     *InterruptStatus OPTIONAL,
+  OUT VOID                       **TxBuf OPTIONAL
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpTransmit (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  IN UINTN                       HeaderSize,
+  IN UINTN                       BufferSize,
+  IN VOID                        *Buffer,
+  IN EFI_MAC_ADDRESS             *SrcAddr  OPTIONAL,
+  IN EFI_MAC_ADDRESS             *DestAddr OPTIONAL,
+  IN UINT16                      *EtherTypePtr OPTIONAL
+  );
+
+EFI_STATUS
+EFIAPI
+Pp2SnpReceive (
+  IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
+  OUT UINTN                      *HeaderSize OPTIONAL,
+  IN OUT UINTN                   *BufferSize,
+  OUT VOID                       *Buffer,
+  OUT EFI_MAC_ADDRESS            *SrcAddr OPTIONAL,
+  OUT EFI_MAC_ADDRESS            *DstAddr OPTIONAL,
+  OUT UINT16                     *EtherType OPTIONAL
+  );
+#endif
diff --git a/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
new file mode 100644
index 0000000..f6be915
--- /dev/null
+++ b/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
@@ -0,0 +1,91 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+#  * Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+#  * Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+#  * Neither the name of Marvell nor the names of its contributors may be
+#    used to endorse or promote products derived from this software without
+#    specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = Pp2Dxe
+  FILE_GUID                      = 5ffc3843-d8d4-40ba-ae07-38967138509c
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = Pp2DxeInitialise
+
+[Sources.common]
+  Pp2Dxe.c
+  Mvpp2Lib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  IoLib
+  PcdLib
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  UefiLib
+  NetLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  MemoryAllocationLib
+  UncachedMemoryAllocationLib
+  CacheMaintenanceLib
+
+[Protocols]
+  gEfiSimpleNetworkProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiCpuArchProtocolGuid
+  gMarvellMdioProtocolGuid
+  gMarvellPhyProtocolGuid
+
+[Pcd]
+  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses
+  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
+  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
+  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
+  gMarvellTokenSpaceGuid.PcdPp2NumPorts
+  gMarvellTokenSpaceGuid.PcdPp2PortIds
+  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
+  gMarvellTokenSpaceGuid.PcdPp2SharedAddress
+  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
+  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
+  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
+
+[Depex]
+  TRUE
diff --git a/Drivers/SdMmc/DwMmcHcDxe/ComponentName.c b/Drivers/SdMmc/DwMmcHcDxe/ComponentName.c
new file mode 100644
index 0000000..999abea
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/ComponentName.c
@@ -0,0 +1,214 @@
+/** @file
+  UEFI Component Name(2) protocol implementation for Designware SD/MMC host
+  controller driver.
+
+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DwMmcHcDxe.h"
+
+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gDwMmcHcComponentName = {
+  DwMmcHcComponentNameGetDriverName,
+  DwMmcHcComponentNameGetControllerName,
+  "eng"
+};
+
+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gDwMmcHcComponentName2 = {
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)     DwMmcHcComponentNameGetDriverName,
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) DwMmcHcComponentNameGetControllerName,
+  "en"
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mDwMmcHcDriverNameTable[] = {
+  { "eng;en", L"Designware Sd/Mmc Host Controller Driver" },
+  { NULL , NULL }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mDwMmcHcControllerNameTable[] = {
+  { "eng;en", L"Designware Sd/Mmc Host Controller" },
+  { NULL , NULL }
+};
+
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL     *This,
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **DriverName
+  )
+{
+  return LookupUnicodeString2 (
+           Language,
+           This->SupportedLanguages,
+           mDwMmcHcDriverNameTable,
+           DriverName,
+           (BOOLEAN)(This == &gDwMmcHcComponentName)
+           );
+}
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL     *This,
+  IN  EFI_HANDLE                      ControllerHandle,
+  IN  EFI_HANDLE                      ChildHandle, OPTIONAL
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **ControllerName
+  )
+{
+  EFI_STATUS         Status;
+
+  if (Language == NULL || ControllerName == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // This is a device driver, so ChildHandle must be NULL.
+  //
+  if (ChildHandle != NULL) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Make sure this driver is currently managing ControllerHandle
+  //
+  Status = EfiTestManagedDevice (
+             ControllerHandle,
+             gDwMmcHcDriverBinding.DriverBindingHandle,
+             &gEfiPciIoProtocolGuid
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return LookupUnicodeString2 (
+           Language,
+           This->SupportedLanguages,
+           mDwMmcHcControllerNameTable,
+           ControllerName,
+           (BOOLEAN)(This == &gDwMmcHcComponentName)
+           );
+}
diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.c b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.c
new file mode 100644
index 0000000..55e2fa4
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.c
@@ -0,0 +1,1363 @@
+/** @file
+  This driver is used to manage Designware SD/MMC host controller.
+
+  It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (C) 2016 Marvell International Ltd. All rigths reserved.<BR>
+  Copyright (C) 2017, Linaro Ltd. All rigths reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DwMmcHcDxe.h"
+
+//
+// Driver Global Variables
+//
+EFI_DRIVER_BINDING_PROTOCOL gDwMmcHcDriverBinding = {
+  DwMmcHcDriverBindingSupported,
+  DwMmcHcDriverBindingStart,
+  DwMmcHcDriverBindingStop,
+  0x10,
+  NULL,
+  NULL
+};
+
+//
+// Template for Designware SD/MMC host controller private data.
+//
+DW_MMC_HC_PRIVATE_DATA gDwMmcHcTemplate = {
+  DW_MMC_HC_PRIVATE_SIGNATURE,      // Signature
+  NULL,                             // ControllerHandle
+  NULL,                             // PciIo
+  {                                 // PassThru
+    sizeof (UINT32),
+    DwMmcPassThruPassThru,
+    DwMmcPassThruGetNextSlot,
+    DwMmcPassThruBuildDevicePath,
+    DwMmcPassThruGetSlotNumber,
+    DwMmcPassThruResetDevice
+  },
+  NULL,                             // PlatformDwMmc
+  0,                                // PciAttributes
+  0,                                // PreviousSlot
+  NULL,                             // TimerEvent
+  NULL,                             // ConnectEvent
+                                    // Queue
+  INITIALIZE_LIST_HEAD_VARIABLE (gDwMmcHcTemplate.Queue),
+  {                                 // Slot
+    {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0},
+    {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}
+  },
+  {                                 // Capability
+    {0},
+  },
+  {                                 // MaxCurrent
+    0,
+  },
+  0                                 // ControllerVersion
+};
+
+SD_DEVICE_PATH    mSdDpTemplate = {
+  {
+    MESSAGING_DEVICE_PATH,
+    MSG_SD_DP,
+    {
+      (UINT8) (sizeof (SD_DEVICE_PATH)),
+      (UINT8) ((sizeof (SD_DEVICE_PATH)) >> 8)
+    }
+  },
+  0
+};
+
+EMMC_DEVICE_PATH    mEmmcDpTemplate = {
+  {
+    MESSAGING_DEVICE_PATH,
+    MSG_EMMC_DP,
+    {
+      (UINT8) (sizeof (EMMC_DEVICE_PATH)),
+      (UINT8) ((sizeof (EMMC_DEVICE_PATH)) >> 8)
+    }
+  },
+  0
+};
+
+//
+// Prioritized function list to detect card type.
+// User could add other card detection logic here.
+//
+CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = {
+  EmmcIdentification,
+  SdCardIdentification,
+  NULL
+};
+
+/**
+  The entry point for SD host controller driver, used to install this driver on the ImageHandle.
+
+  @param[in]  ImageHandle   The firmware allocated handle for this driver image.
+  @param[in]  SystemTable   Pointer to the EFI system table.
+
+  @retval EFI_SUCCESS   Driver loaded.
+  @retval other         Driver not loaded.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeDwMmcHcDxe (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS           Status;
+
+  Status = EfiLibInstallDriverBindingComponentName2 (
+             ImageHandle,
+             SystemTable,
+             &gDwMmcHcDriverBinding,
+             ImageHandle,
+             &gDwMmcHcComponentName,
+             &gDwMmcHcComponentName2
+             );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+/**
+  Call back function when the timer event is signaled.
+
+  @param[in]  Event     The Event this notify function registered to.
+  @param[in]  Context   Pointer to the context data registered to the
+                        Event.
+
+**/
+VOID
+EFIAPI
+ProcessAsyncTaskList (
+  IN EFI_EVENT          Event,
+  IN VOID*              Context
+  )
+{
+  DW_MMC_HC_PRIVATE_DATA              *Private;
+  LIST_ENTRY                          *Link;
+  DW_MMC_HC_TRB                       *Trb;
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  BOOLEAN                             InfiniteWait;
+  EFI_EVENT                           TrbEvent;
+
+  Private = (DW_MMC_HC_PRIVATE_DATA *)Context;
+
+  //
+  // Check if the first entry in the async I/O queue is done or not.
+  //
+  Status = EFI_SUCCESS;
+  Trb    = NULL;
+  Link   = GetFirstNode (&Private->Queue);
+  if (!IsNull (&Private->Queue, Link)) {
+    Trb = DW_MMC_HC_TRB_FROM_THIS (Link);
+    if (!Private->Slot[Trb->Slot].MediaPresent) {
+      Status = EFI_NO_MEDIA;
+      goto Done;
+    }
+    if (!Trb->Started) {
+      //
+      // Check whether the cmd/data line is ready for transfer.
+      //
+      Status = DwMmcCheckTrbEnv (Private, Trb);
+      if (!EFI_ERROR (Status)) {
+        Trb->Started = TRUE;
+        Status = DwMmcExecTrb (Private, Trb);
+        if (EFI_ERROR (Status)) {
+          goto Done;
+        }
+      } else {
+        goto Done;
+      }
+    }
+    Status = DwMmcCheckTrbResult (Private, Trb);
+  }
+
+Done:
+  if ((Trb != NULL) && (Status == EFI_NOT_READY)) {
+    Packet = Trb->Packet;
+    if (Packet->Timeout == 0) {
+      InfiniteWait = TRUE;
+    } else {
+      InfiniteWait = FALSE;
+    }
+    if ((!InfiniteWait) && (Trb->Timeout-- == 0)) {
+      RemoveEntryList (Link);
+      Trb->Packet->TransactionStatus = EFI_TIMEOUT;
+      TrbEvent = Trb->Event;
+      DwMmcFreeTrb (Trb);
+      DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p EFI_TIMEOUT\n", TrbEvent));
+      gBS->SignalEvent (TrbEvent);
+      return;
+    }
+  }
+  if ((Trb != NULL) && (Status != EFI_NOT_READY)) {
+    RemoveEntryList (Link);
+    Trb->Packet->TransactionStatus = Status;
+    TrbEvent = Trb->Event;
+    DwMmcFreeTrb (Trb);
+    DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p with %r\n", TrbEvent, Status));
+    gBS->SignalEvent (TrbEvent);
+  }
+  return;
+}
+
+/**
+  Sd removable device enumeration callback function when the timer event is signaled.
+
+  @param[in]  Event     The Event this notify function registered to.
+  @param[in]  Context   Pointer to the context data registered to the
+                        Event.
+
+**/
+VOID
+EFIAPI
+DwMmcHcEnumerateDevice (
+  IN EFI_EVENT          Event,
+  IN VOID*              Context
+  )
+{
+  DW_MMC_HC_PRIVATE_DATA              *Private;
+  EFI_STATUS                          Status;
+  UINT8                               Slot;
+  BOOLEAN                             MediaPresent;
+  UINT32                              RoutineNum;
+  CARD_TYPE_DETECT_ROUTINE            *Routine;
+  UINTN                               Index;
+  LIST_ENTRY                          *Link;
+  LIST_ENTRY                          *NextLink;
+  DW_MMC_HC_TRB                       *Trb;
+  EFI_TPL                             OldTpl;
+
+return;
+  Private = (DW_MMC_HC_PRIVATE_DATA *)Context;
+
+  for (Slot = 0; Slot < DW_MMC_HC_MAX_SLOT; Slot++) {
+    if ((Private->Slot[Slot].Enable) && (Private->Slot[Slot].SlotType == RemovableSlot)) {
+      Status = DwMmcHcCardDetect (Private->PciIo, Slot, &MediaPresent);
+      if ((Status == EFI_MEDIA_CHANGED) && !MediaPresent) {
+        DEBUG ((DEBUG_INFO, "DwMmcHcEnumerateDevice: device disconnected at slot %d of pci %p\n", Slot, Private->PciIo));
+        Private->Slot[Slot].MediaPresent = FALSE;
+        //
+        // Signal all async task events at the slot with EFI_NO_MEDIA status.
+        //
+        OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+        for (Link = GetFirstNode (&Private->Queue);
+             !IsNull (&Private->Queue, Link);
+             Link = NextLink) {
+          NextLink = GetNextNode (&Private->Queue, Link);
+          Trb = DW_MMC_HC_TRB_FROM_THIS (Link);
+          if (Trb->Slot == Slot) {
+            RemoveEntryList (Link);
+            Trb->Packet->TransactionStatus = EFI_NO_MEDIA;
+            gBS->SignalEvent (Trb->Event);
+            DwMmcFreeTrb (Trb);
+          }
+        }
+        gBS->RestoreTPL (OldTpl);
+        //
+        // Notify the upper layer the connect state change through ReinstallProtocolInterface.
+        //
+        gBS->ReinstallProtocolInterface (
+              Private->ControllerHandle,
+              &gEfiSdMmcPassThruProtocolGuid,
+              &Private->PassThru,
+              &Private->PassThru
+              );
+      }
+      if ((Status == EFI_MEDIA_CHANGED) && MediaPresent) {
+        DEBUG ((DEBUG_INFO, "DwMmcHcEnumerateDevice: device connected at slot %d of pci %p\n", Slot, Private->PciIo));
+        //
+        // Initialize slot and start identification process for the new attached device
+        //
+        Status = DwMmcHcInitHost (Private->PciIo, Slot, Private->Capability[Slot]);
+        if (EFI_ERROR (Status)) {
+          continue;
+        }
+        //
+        // Reset the specified slot of the SD/MMC Pci Host Controller
+        //
+        Status = DwMmcHcReset (Private->PciIo, Slot, Private->Capability[Slot]);
+        if (EFI_ERROR (Status)) {
+          continue;
+        }
+
+        Private->Slot[Slot].MediaPresent = TRUE;
+        RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
+        for (Index = 0; Index < RoutineNum; Index++) {
+          Routine = &mCardTypeDetectRoutineTable[Index];
+          if (*Routine != NULL) {
+            Status = (*Routine) (Private, Slot);
+            if (!EFI_ERROR (Status)) {
+              break;
+            }
+          }
+        }
+        //
+        // This card doesn't get initialized correctly.
+        //
+        if (Index == RoutineNum) {
+        }
+
+        //
+        // Notify the upper layer the connect state change through ReinstallProtocolInterface.
+        //
+        gBS->ReinstallProtocolInterface (
+               Private->ControllerHandle,
+               &gEfiSdMmcPassThruProtocolGuid,
+               &Private->PassThru,
+               &Private->PassThru
+               );
+      }
+    }
+  }
+
+  return;
+}
+
+/**
+  Reset the specified SD/MMC host controller and enable all interrupts.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The software reset executes successfully.
+  @retval Others            The software reset fails.
+
+**/
+EFI_STATUS
+DwMmcHcReset (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    BlkSize;
+
+  //
+  // Enable all interrupt after reset all.
+  //
+  Status = DwMmcHcEnableInterrupt (PciIo, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcReset: enable interrupts fail: %r\n", Status));
+    return Status;
+  }
+  Status = DwMmcHcInitTimeoutCtrl (PciIo, Slot);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  BlkSize = DW_MMC_BLOCK_SIZE;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_BLKSIZ, FALSE, sizeof (BlkSize), &BlkSize);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcReset: set block size fails: %r\n", Status));
+    return Status;
+  }
+
+  Status = DwMmcHcInitClockFreq (PciIo, Slot, Capability);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = DwMmcHcSetBusWidth (PciIo, Slot, FALSE, 1);
+
+  return Status;
+}
+
+/**
+  Tests to see if this driver supports a given controller. If a child device is provided,
+  it further tests to see if this driver supports creating a handle for the specified child device.
+
+  This function checks to see if the driver specified by This supports the device specified by
+  ControllerHandle. Drivers will typically use the device path attached to
+  ControllerHandle and/or the services from the bus I/O abstraction attached to
+  ControllerHandle to determine if the driver supports ControllerHandle. This function
+  may be called many times during platform initialization. In order to reduce boot times, the tests
+  performed by this function must be very small, and take as little time as possible to execute. This
+  function must not change the state of any hardware devices, and this function must be aware that the
+  device specified by ControllerHandle may already be managed by the same driver or a
+  different driver. This function must match its calls to AllocatePages() with FreePages(),
+  AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+  Since ControllerHandle may have been previously started by the same driver, if a protocol is
+  already in the opened state, then it must not be closed with CloseProtocol(). This is required
+  to guarantee the state of ControllerHandle is not modified by this function.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to test. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For bus drivers, if this parameter is not NULL, then
+                                   the bus driver must determine if the bus controller specified
+                                   by ControllerHandle and the child controller specified
+                                   by RemainingDevicePath are both supported by this
+                                   bus driver.
+
+  @retval EFI_SUCCESS              The device specified by ControllerHandle and
+                                   RemainingDevicePath is supported by the driver specified by This.
+  @retval EFI_ALREADY_STARTED      The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by the driver
+                                   specified by This.
+  @retval EFI_ACCESS_DENIED        The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by a different
+                                   driver or an application that requires exclusive access.
+                                   Currently not implemented.
+  @retval EFI_UNSUPPORTED          The device specified by ControllerHandle and
+                                   RemainingDevicePath is not supported by the driver specified by This.
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL *This,
+  IN EFI_HANDLE                  Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL    *RemainingDevicePath
+  )
+{
+  EFI_STATUS                Status;
+  EFI_DEVICE_PATH_PROTOCOL  *ParentDevicePath;
+  EFI_PCI_IO_PROTOCOL       *PciIo;
+  PCI_TYPE00                PciData;
+  PLATFORM_DW_MMC_PROTOCOL  *PlatformDwMmc;
+
+  PciIo            = NULL;
+  ParentDevicePath = NULL;
+
+  Status = gBS->LocateProtocol (
+                  &gPlatformDwMmcProtocolGuid,
+                  NULL,
+                  (VOID **) &PlatformDwMmc
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // SdPciHcDxe is a device driver, and should ingore the
+  // "RemainingDevicePath" according to EFI spec.
+  //
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiDevicePathProtocolGuid,
+                  (VOID *) &ParentDevicePath,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    //
+    // EFI_ALREADY_STARTED is also an error.
+    //
+    return Status;
+  }
+  //
+  // Close the protocol because we don't use it here.
+  //
+  gBS->CloseProtocol (
+        Controller,
+        &gEfiDevicePathProtocolGuid,
+        This->DriverBindingHandle,
+        Controller
+        );
+
+  //
+  // Now test the EfiPciIoProtocol.
+  //
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiPciIoProtocolGuid,
+                  (VOID **) &PciIo,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Now further check the PCI header: Base class (offset 0x08) and
+  // Sub Class (offset 0x05). This controller should be an SD/MMC PCI
+  // Host Controller.
+  //
+  Status = PciIo->Pci.Read (
+                        PciIo,
+                        EfiPciIoWidthUint8,
+                        0,
+                        sizeof (PciData),
+                        &PciData
+                        );
+  if (EFI_ERROR (Status)) {
+    gBS->CloseProtocol (
+          Controller,
+          &gEfiPciIoProtocolGuid,
+          This->DriverBindingHandle,
+          Controller
+          );
+    return EFI_UNSUPPORTED;
+  }
+  //
+  // Since we already got the PciData, we can close protocol to avoid to carry it
+  // on for multiple exit points.
+  //
+  gBS->CloseProtocol (
+        Controller,
+        &gEfiPciIoProtocolGuid,
+        This->DriverBindingHandle,
+        Controller
+        );
+
+  //
+  // Examine SD PCI Host Controller PCI Configuration table fields.
+  //
+  if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) &&
+      (PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) &&
+      ((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) {
+    return EFI_SUCCESS;
+  }
+
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Starts a device controller or a bus controller.
+
+  The Start() function is designed to be invoked from the EFI boot service ConnectController().
+  As a result, much of the error checking on the parameters to Start() has been moved into this
+  common boot service. It is legal to call Start() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE.
+  2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
+     EFI_DEVICE_PATH_PROTOCOL.
+  3. Prior to calling Start(), the Supported() function for the driver specified by This must
+     have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to start. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For a bus driver, if this parameter is NULL, then handles
+                                   for all the children of Controller are created by this driver.
+                                   If this parameter is not NULL and the first Device Path Node is
+                                   not the End of Device Path Node, then only the handle for the
+                                   child device specified by the first Device Path Node of
+                                   RemainingDevicePath is created by this driver.
+                                   If the first Device Path Node of RemainingDevicePath is
+                                   the End of Device Path Node, no child handle is created by this
+                                   driver.
+
+  @retval EFI_SUCCESS              The device was started.
+  @retval EFI_DEVICE_ERROR         The device could not be started due to a device error.Currently not implemented.
+  @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+  @retval Others                   The driver failded to start the device.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN EFI_HANDLE                      Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath
+  )
+{
+  EFI_STATUS                      Status;
+  DW_MMC_HC_PRIVATE_DATA          *Private;
+  EFI_PCI_IO_PROTOCOL             *PciIo;
+  UINT64                          Supports;
+  UINT64                          PciAttributes;
+  UINT8                           Slot;
+  UINT8                           Index;
+  CARD_TYPE_DETECT_ROUTINE        *Routine;
+  UINT32                          RoutineNum;
+  BOOLEAN                         Support64BitDma;
+  BOOLEAN                         MediaPresent;
+  PLATFORM_DW_MMC_PROTOCOL        *PlatformDwMmc;
+
+  Status = gBS->LocateProtocol (
+                  &gPlatformDwMmcProtocolGuid,
+                  NULL,
+                  (VOID **) &PlatformDwMmc
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Open PCI I/O Protocol and save pointer to open protocol
+  // in private data area.
+  //
+  PciIo  = NULL;
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiPciIoProtocolGuid,
+                  (VOID **) &PciIo,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Enable the SD Host Controller MMIO space
+  //
+  Private = NULL;
+  Status  = PciIo->Attributes (
+                     PciIo,
+                     EfiPciIoAttributeOperationGet,
+                     0,
+                     &PciAttributes
+                     );
+
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationSupported,
+                    0,
+                    &Supports
+                    );
+
+  if (!EFI_ERROR (Status)) {
+    Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
+    Status    = PciIo->Attributes (
+                         PciIo,
+                         EfiPciIoAttributeOperationEnable,
+                         Supports,
+                         NULL
+                         );
+  } else {
+    goto Done;
+  }
+
+  Private = AllocateCopyPool (sizeof (DW_MMC_HC_PRIVATE_DATA), &gDwMmcHcTemplate);
+  if (Private == NULL) {
+    Status = EFI_OUT_OF_RESOURCES;
+    goto Done;
+  }
+
+  Private->ControllerHandle = Controller;
+  Private->PciIo            = PciIo;
+  Private->PciAttributes    = PciAttributes;
+  Private->PlatformDwMmc    = PlatformDwMmc;
+  InitializeListHead (&Private->Queue);
+
+  Support64BitDma = TRUE;
+
+  //for (Slot = 0; Slot < DW_MMC_HC_MAX_SLOT; Slot++) {
+  for (Slot = 0; Slot < 1; Slot++) {
+    Status = DwMmcHcGetCapability (PciIo, Controller, Slot, &Private->Capability[Slot]);
+    if (EFI_ERROR (Status)) {
+      break;
+    }
+
+    Support64BitDma &= Private->Capability[Slot].SysBus64;
+
+    if (Private->Capability[Slot].BaseClkFreq == 0) {
+      continue;
+    }
+
+    DumpCapabilityReg (Slot, &Private->Capability[Slot]);
+
+    MediaPresent = FALSE;
+    Status = DwMmcHcCardDetect (Private->PciIo, Slot, &MediaPresent);
+    if (MediaPresent == FALSE) {
+      continue;
+    }
+
+    //
+    // Initialize slot and start identification process for the new attached device
+    //
+    Status = DwMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    //
+    // Reset HC
+    //
+    Status = DwMmcHcReset (PciIo, Slot, Private->Capability[Slot]);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    Private->Slot[Slot].CardType = Private->Capability[Slot].CardType;
+    Private->Slot[Slot].Enable = TRUE;
+    Private->Slot[Slot].MediaPresent = TRUE;
+
+    RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
+    for (Index = 0; Index < RoutineNum; Index++) {
+      Routine = &mCardTypeDetectRoutineTable[Index];
+      if (*Routine != NULL) {
+        Status = (*Routine) (Private, Slot);
+        if (!EFI_ERROR (Status)) {
+          break;
+        }
+      }
+    }
+  }
+
+  //
+  // Enable 64-bit DMA support in the PCI layer if this controller
+  // supports it.
+  //
+  if (Support64BitDma) {
+    Status = PciIo->Attributes (
+                      PciIo,
+                      EfiPciIoAttributeOperationEnable,
+                      EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
+                      NULL
+                      );
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_WARN, "DwMmcHcDriverBindingStart: failed to enable 64-bit DMA (%r)\n", Status));
+    }
+  }
+
+  //
+  // Start the asynchronous I/O monitor
+  //
+  Status = gBS->CreateEvent (
+                  EVT_TIMER | EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  ProcessAsyncTaskList,
+                  Private,
+                  &Private->TimerEvent
+                  );
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, DW_MMC_HC_ASYNC_TIMER);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  //
+  // Start the Sd removable device connection enumeration
+  //
+  Status = gBS->CreateEvent (
+                  EVT_TIMER | EVT_NOTIFY_SIGNAL,
+                  TPL_CALLBACK,
+                  DwMmcHcEnumerateDevice,
+                  Private,
+                  &Private->ConnectEvent
+                  );
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = gBS->SetTimer (Private->ConnectEvent, TimerPeriodic, DW_MMC_HC_ENUM_TIMER);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Controller,
+                  &gEfiSdMmcPassThruProtocolGuid,
+                  &(Private->PassThru),
+                  NULL
+                  );
+
+  DEBUG ((DEBUG_INFO, "DwMmcHcDriverBindingStart: %r End on %x\n", Status, Controller));
+
+Done:
+  if (EFI_ERROR (Status)) {
+    if ((Private != NULL) && (Private->PciAttributes != 0)) {
+      //
+      // Restore original PCI attributes
+      //
+      PciIo->Attributes (
+               PciIo,
+               EfiPciIoAttributeOperationSet,
+               Private->PciAttributes,
+               NULL
+               );
+    }
+    gBS->CloseProtocol (
+          Controller,
+          &gEfiPciIoProtocolGuid,
+          This->DriverBindingHandle,
+          Controller
+          );
+
+    if ((Private != NULL) && (Private->TimerEvent != NULL)) {
+      gBS->CloseEvent (Private->TimerEvent);
+    }
+
+    if ((Private != NULL) && (Private->ConnectEvent != NULL)) {
+      gBS->CloseEvent (Private->ConnectEvent);
+    }
+
+    if (Private != NULL) {
+      FreePool (Private);
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Stops a device controller or a bus controller.
+
+  The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+  As a result, much of the error checking on the parameters to Stop() has been moved
+  into this common boot service. It is legal to call Stop() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
+     same driver's Start() function.
+  2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
+     EFI_HANDLE. In addition, all of these handles must have been created in this driver's
+     Start() function, and the Start() function must have called OpenProtocol() on
+     ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+  @param[in]  This              A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle  A handle to the device being stopped. The handle must
+                                support a bus specific I/O protocol for the driver
+                                to use to stop the device.
+  @param[in]  NumberOfChildren  The number of child device handles in ChildHandleBuffer.
+  @param[in]  ChildHandleBuffer An array of child handles to be freed. May be NULL
+                                if NumberOfChildren is 0.
+
+  @retval EFI_SUCCESS           The device was stopped.
+  @retval EFI_DEVICE_ERROR      The device could not be stopped due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN  EFI_HANDLE                      Controller,
+  IN  UINTN                           NumberOfChildren,
+  IN  EFI_HANDLE                      *ChildHandleBuffer
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_PROTOCOL       *PassThru;
+  DW_MMC_HC_PRIVATE_DATA              *Private;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+  LIST_ENTRY                          *Link;
+  LIST_ENTRY                          *NextLink;
+  DW_MMC_HC_TRB                       *Trb;
+
+  DEBUG ((DEBUG_INFO, "DwMmcHcDriverBindingStop: Start\n"));
+
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiSdMmcPassThruProtocolGuid,
+                  (VOID**) &PassThru,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  //
+  // Close Non-Blocking timer and free Task list.
+  //
+  if (Private->TimerEvent != NULL) {
+    gBS->CloseEvent (Private->TimerEvent);
+    Private->TimerEvent = NULL;
+  }
+  if (Private->ConnectEvent != NULL) {
+    gBS->CloseEvent (Private->ConnectEvent);
+    Private->ConnectEvent = NULL;
+  }
+  //
+  // As the timer is closed, there is no needs to use TPL lock to
+  // protect the critical region "queue".
+  //
+  for (Link = GetFirstNode (&Private->Queue);
+       !IsNull (&Private->Queue, Link);
+       Link = NextLink) {
+    NextLink = GetNextNode (&Private->Queue, Link);
+    RemoveEntryList (Link);
+    Trb = DW_MMC_HC_TRB_FROM_THIS (Link);
+    Trb->Packet->TransactionStatus = EFI_ABORTED;
+    gBS->SignalEvent (Trb->Event);
+    DwMmcFreeTrb (Trb);
+  }
+
+  //
+  // Uninstall Block I/O protocol from the device handle
+  //
+  Status = gBS->UninstallProtocolInterface (
+                  Controller,
+                  &gEfiSdMmcPassThruProtocolGuid,
+                  &(Private->PassThru)
+                  );
+
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  gBS->CloseProtocol (
+         Controller,
+         &gEfiPciIoProtocolGuid,
+         This->DriverBindingHandle,
+         Controller
+         );
+  //
+  // Restore original PCI attributes
+  //
+  PciIo  = Private->PciIo;
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationSet,
+                    Private->PciAttributes,
+                    NULL
+                    );
+  ASSERT_EFI_ERROR (Status);
+
+  FreePool (Private);
+
+  DEBUG ((DEBUG_INFO, "DwMmcHcDriverBindingStop: End with %r\n", Status));
+
+  return Status;
+}
+
+/**
+  Sends SD command to an SD card that is attached to the SD controller.
+
+  The PassThru() function sends the SD command specified by Packet to the SD card
+  specified by Slot.
+
+  If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.
+
+  If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
+
+  If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER
+  is returned.
+
+  If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
+  EFI_INVALID_PARAMETER is returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]     Slot           The slot number of the SD card to send the command to.
+  @param[in,out] Packet         A pointer to the SD command data structure.
+  @param[in]     Event          If Event is NULL, blocking I/O is performed. If Event is
+                                not NULL, then nonblocking I/O is performed, and Event
+                                will be signaled when the Packet completes.
+
+  @retval EFI_SUCCESS           The SD Command Packet was sent by the host.
+  @retval EFI_DEVICE_ERROR      A device error occurred while attempting to send the SD
+                                command Packet.
+  @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
+  @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
+                                OutDataBuffer are NULL.
+  @retval EFI_NO_MEDIA          SD Device not present in the Slot.
+  @retval EFI_UNSUPPORTED       The command described by the SD Command Packet is not
+                                supported by the host controller.
+  @retval EFI_BAD_BUFFER_SIZE   The InTransferLength or OutTransferLength exceeds the
+                                limit supported by SD card ( i.e. if the number of bytes
+                                exceed the Last LBA).
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruPassThru (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL         *This,
+  IN     UINT8                                 Slot,
+  IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   *Packet,
+  IN     EFI_EVENT                             Event    OPTIONAL
+  )
+{
+  EFI_STATUS                      Status;
+  DW_MMC_HC_PRIVATE_DATA          *Private;
+  DW_MMC_HC_TRB                   *Trb;
+  EFI_TPL                         OldTpl;
+
+  if ((This == NULL) || (Packet == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  if (!Private->Slot[Slot].Enable) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (!Private->Slot[Slot].MediaPresent) {
+    return EFI_NO_MEDIA;
+  }
+
+  Trb = DwMmcCreateTrb (Private, Slot, Packet, Event);
+  if (Trb == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  //
+  // Immediately return for async I/O.
+  //
+  if (Event != NULL) {
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Wait async I/O list is empty before execute sync I/O operation.
+  //
+  while (TRUE) {
+    OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+    if (IsListEmpty (&Private->Queue)) {
+      gBS->RestoreTPL (OldTpl);
+      break;
+    }
+    gBS->RestoreTPL (OldTpl);
+  }
+
+  Status = DwMmcWaitTrbEnv (Private, Trb);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = DwMmcExecTrb (Private, Trb);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = DwMmcWaitTrbResult (Private, Trb);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+Done:
+#if 0
+  if ((Trb != NULL) && (Trb->DmaDesc != NULL)) {
+    FreePages (Trb->DmaDesc, Trb->DmaDescPages);
+  }
+
+  if (Trb != NULL) {
+    FreePool (Trb);
+  }
+#else
+  if (Trb != NULL) {
+    DwMmcFreeTrb (Trb);
+  }
+#endif
+
+  return Status;
+}
+
+/**
+  Used to retrieve next slot numbers supported by the SD controller. The function
+  returns information about all available slots (populated or not-populated).
+
+  The GetNextSlot() function retrieves the next slot number on an SD controller.
+  If on input Slot is 0xFF, then the slot number of the first slot on the SD controller
+  is returned.
+
+  If Slot is a slot number that was returned on a previous call to GetNextSlot(), then
+  the slot number of the next slot on the SD controller is returned.
+
+  If Slot is not 0xFF and Slot was not returned on a previous call to GetNextSlot(),
+  EFI_INVALID_PARAMETER is returned.
+
+  If Slot is the slot number of the last slot on the SD controller, then EFI_NOT_FOUND
+  is returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
+  @param[in,out] Slot           On input, a pointer to a slot number on the SD controller.
+                                On output, a pointer to the next slot number on the SD controller.
+                                An input value of 0xFF retrieves the first slot number on the SD
+                                controller.
+
+  @retval EFI_SUCCESS           The next slot number on the SD controller was returned in Slot.
+  @retval EFI_NOT_FOUND         There are no more slots on this SD controller.
+  @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a previous call
+                                to GetNextSlot().
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruGetNextSlot (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL        *This,
+  IN OUT UINT8                                *Slot
+  )
+{
+  DW_MMC_HC_PRIVATE_DATA          *Private;
+  UINT8                           Index;
+
+  if ((This == NULL) || (Slot == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  if (*Slot == 0xFF) {
+    for (Index = 0; Index < DW_MMC_HC_MAX_SLOT; Index++) {
+      if (Private->Slot[Index].Enable) {
+        *Slot = Index;
+        Private->PreviousSlot = Index;
+        return EFI_SUCCESS;
+      }
+    }
+    return EFI_NOT_FOUND;
+  } else if (*Slot == Private->PreviousSlot) {
+    for (Index = *Slot + 1; Index < DW_MMC_HC_MAX_SLOT; Index++) {
+      if (Private->Slot[Index].Enable) {
+        *Slot = Index;
+        Private->PreviousSlot = Index;
+        return EFI_SUCCESS;
+      }
+    }
+    return EFI_NOT_FOUND;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+}
+
+/**
+  Used to allocate and build a device path node for an SD card on the SD controller.
+
+  The BuildDevicePath() function allocates and builds a single device node for the SD
+  card specified by Slot.
+
+  If the SD card specified by Slot is not present on the SD controller, then EFI_NOT_FOUND
+  is returned.
+
+  If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
+
+  If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES
+  is returned.
+
+  Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of
+  DevicePath are initialized to describe the SD card specified by Slot, and EFI_SUCCESS is
+  returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
+  @param[in]     Slot           Specifies the slot number of the SD card for which a device
+                                path node is to be allocated and built.
+  @param[in,out] DevicePath     A pointer to a single device path node that describes the SD
+                                card specified by Slot. This function is responsible for
+                                allocating the buffer DevicePath with the boot service
+                                AllocatePool(). It is the caller's responsibility to free
+                                DevicePath when the caller is finished with DevicePath.
+
+  @retval EFI_SUCCESS           The device path node that describes the SD card specified by
+                                Slot was allocated and returned in DevicePath.
+  @retval EFI_NOT_FOUND         The SD card specified by Slot does not exist on the SD controller.
+  @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to allocate DevicePath.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruBuildDevicePath (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL       *This,
+  IN     UINT8                               Slot,
+  IN OUT EFI_DEVICE_PATH_PROTOCOL            **DevicePath
+  )
+{
+  DW_MMC_HC_PRIVATE_DATA          *Private;
+  SD_DEVICE_PATH                  *SdNode;
+  EMMC_DEVICE_PATH                *EmmcNode;
+
+  if ((This == NULL) || (DevicePath == NULL) || (Slot >= DW_MMC_HC_MAX_SLOT)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  if ((!Private->Slot[Slot].Enable) || (!Private->Slot[Slot].MediaPresent)) {
+    return EFI_NOT_FOUND;
+  }
+
+  if (Private->Slot[Slot].CardType == SdCardType) {
+    SdNode = AllocateCopyPool (sizeof (SD_DEVICE_PATH), &mSdDpTemplate);
+    if (SdNode == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    SdNode->SlotNumber = Slot;
+
+    *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) SdNode;
+  } else if (Private->Slot[Slot].CardType == EmmcCardType) {
+    EmmcNode = AllocateCopyPool (sizeof (EMMC_DEVICE_PATH), &mEmmcDpTemplate);
+    if (EmmcNode == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    EmmcNode->SlotNumber = Slot;
+
+    *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) EmmcNode;
+  } else {
+    //
+    // Currently we only support SD and EMMC two device nodes.
+    //
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function retrieves an SD card slot number based on the input device path.
+
+  The GetSlotNumber() function retrieves slot number for the SD card specified by
+  the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is returned.
+
+  If DevicePath is not a device path node type that the SD Pass Thru driver supports,
+  EFI_UNSUPPORTED is returned.
+
+  @param[in]  This              A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  DevicePath        A pointer to the device path node that describes a SD
+                                card on the SD controller.
+  @param[out] Slot              On return, points to the slot number of an SD card on
+                                the SD controller.
+
+  @retval EFI_SUCCESS           SD card slot number is returned in Slot.
+  @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL.
+  @retval EFI_UNSUPPORTED       DevicePath is not a device path node type that the SD
+                                Pass Thru driver supports.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruGetSlotNumber (
+  IN  EFI_SD_MMC_PASS_THRU_PROTOCOL          *This,
+  IN  EFI_DEVICE_PATH_PROTOCOL               *DevicePath,
+  OUT UINT8                                  *Slot
+  )
+{
+  DW_MMC_HC_PRIVATE_DATA          *Private;
+  SD_DEVICE_PATH                  *SdNode;
+  EMMC_DEVICE_PATH                *EmmcNode;
+  UINT8                           SlotNumber;
+
+  if ((This == NULL) || (DevicePath == NULL) || (Slot == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  //
+  // Check whether the DevicePath belongs to SD_DEVICE_PATH or EMMC_DEVICE_PATH
+  //
+  if ((DevicePath->Type != MESSAGING_DEVICE_PATH) ||
+      ((DevicePath->SubType != MSG_SD_DP) &&
+       (DevicePath->SubType != MSG_EMMC_DP)) ||
+      (DevicePathNodeLength(DevicePath) != sizeof(SD_DEVICE_PATH)) ||
+      (DevicePathNodeLength(DevicePath) != sizeof(EMMC_DEVICE_PATH))) {
+    return EFI_UNSUPPORTED;
+  }
+
+  if (DevicePath->SubType == MSG_SD_DP) {
+    SdNode = (SD_DEVICE_PATH *) DevicePath;
+    SlotNumber = SdNode->SlotNumber;
+  } else {
+    EmmcNode = (EMMC_DEVICE_PATH *) DevicePath;
+    SlotNumber = EmmcNode->SlotNumber;
+  }
+
+  if (SlotNumber >= DW_MMC_HC_MAX_SLOT) {
+    return EFI_NOT_FOUND;
+  }
+
+  if (Private->Slot[SlotNumber].Enable) {
+    *Slot = SlotNumber;
+    return EFI_SUCCESS;
+  } else {
+    return EFI_NOT_FOUND;
+  }
+}
+
+/**
+  Resets an SD card that is connected to the SD controller.
+
+  The ResetDevice() function resets the SD card specified by Slot.
+
+  If this SD controller does not support a device reset operation, EFI_UNSUPPORTED is
+  returned.
+
+  If Slot is not in a valid slot number for this SD controller, EFI_INVALID_PARAMETER
+  is returned.
+
+  If the device reset operation is completed, EFI_SUCCESS is returned.
+
+  @param[in]  This              A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot              Specifies the slot number of the SD card to be reset.
+
+  @retval EFI_SUCCESS           The SD card specified by Slot was reset.
+  @retval EFI_UNSUPPORTED       The SD controller does not support a device reset operation.
+  @retval EFI_INVALID_PARAMETER Slot number is invalid.
+  @retval EFI_NO_MEDIA          SD Device not present in the Slot.
+  @retval EFI_DEVICE_ERROR      The reset command failed due to a device error
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruResetDevice (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL           *This,
+  IN UINT8                                   Slot
+  )
+{
+  DW_MMC_HC_PRIVATE_DATA          *Private;
+  LIST_ENTRY                      *Link;
+  LIST_ENTRY                      *NextLink;
+  DW_MMC_HC_TRB                   *Trb;
+  EFI_TPL                         OldTpl;
+
+  if (This == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  if (!Private->Slot[Slot].Enable) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (!Private->Slot[Slot].MediaPresent) {
+    return EFI_NO_MEDIA;
+  }
+
+  //
+  // Free all async I/O requests in the queue
+  //
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  for (Link = GetFirstNode (&Private->Queue);
+       !IsNull (&Private->Queue, Link);
+       Link = NextLink) {
+    NextLink = GetNextNode (&Private->Queue, Link);
+    RemoveEntryList (Link);
+    Trb = DW_MMC_HC_TRB_FROM_THIS (Link);
+    Trb->Packet->TransactionStatus = EFI_ABORTED;
+    gBS->SignalEvent (Trb->Event);
+    DwMmcFreeTrb (Trb);
+  }
+
+  gBS->RestoreTPL (OldTpl);
+
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.dec b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.dec
new file mode 100644
index 0000000..97382a3
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.dec
@@ -0,0 +1,40 @@
+#/** @file
+# Framework Module Development Environment Industry Standards
+#
+# This Package provides headers and libraries that conform to EFI/PI Industry standards.
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro. All rights reserved.<BR>
+#
+#    This program and the accompanying materials are licensed and made available under
+#    the terms and conditions of the BSD License which accompanies this distribution.
+#    The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = DwMmcHcDxePkg
+  PACKAGE_GUID                   = e73097ce-1fe2-41a6-a930-3136bc6d23ef
+  PACKAGE_VERSION                = 0.1
+
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+  gDwMmcHcDxeTokenSpaceGuid     = { 0x576c132e, 0x7d51, 0x4abb, { 0xbc, 0x60, 0x13, 0x08, 0x04, 0x0e, 0x90, 0x92 }}
+
+[Protocols.common]
+  gPlatformDwMmcProtocolGuid    = { 0x1d6dfde5, 0x76a7, 0x4404, { 0x85, 0x74, 0x7a, 0xdf, 0x1a, 0x8a, 0xa2, 0x0d }}
diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.h b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.h
new file mode 100644
index 0000000..4e175b9
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.h
@@ -0,0 +1,779 @@
+/** @file
+
+  Provides some data structure definitions used by the Designware SD/MMC
+  host controller driver.
+
+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (C) 2017, Linaro Ltd. All rigths reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DW_MMC_HC_DXE_H_
+#define _DW_MMC_HC_DXE_H_
+
+#include <Uefi.h>
+
+#include <IndustryStandard/Emmc.h>
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/Sd.h>
+
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/ComponentName.h>
+#include <Protocol/ComponentName2.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/DriverBinding.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PlatformDwMmc.h>
+#include <Protocol/SdMmcPassThru.h>
+
+#include "DwMmcHci.h"
+
+extern EFI_COMPONENT_NAME_PROTOCOL  gDwMmcHcComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gDwMmcHcComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL  gDwMmcHcDriverBinding;
+
+#define DW_MMC_HC_PRIVATE_SIGNATURE  SIGNATURE_32 ('d', 'w', 's', 'd')
+
+#define DW_MMC_HC_PRIVATE_FROM_THIS(a) \
+    CR(a, DW_MMC_HC_PRIVATE_DATA, PassThru, DW_MMC_HC_PRIVATE_SIGNATURE)
+
+//
+// Generic time out value, 1 microsecond as unit.
+//
+#define DW_MMC_HC_GENERIC_TIMEOUT     1 * 1000 * 1000
+
+//
+// SD/MMC async transfer timer interval, set by experience.
+// The unit is 100us, takes 1ms as interval.
+//
+#define DW_MMC_HC_ASYNC_TIMER   EFI_TIMER_PERIOD_MILLISECONDS(1)
+//
+// SD/MMC removable device enumeration timer interval, set by experience.
+// The unit is 100us, takes 100ms as interval.
+//
+#define DW_MMC_HC_ENUM_TIMER    EFI_TIMER_PERIOD_MILLISECONDS(100)
+
+typedef struct {
+  BOOLEAN                             Enable;
+  EFI_SD_MMC_SLOT_TYPE                SlotType;
+  BOOLEAN                             MediaPresent;
+  BOOLEAN                             Initialized;
+  SD_MMC_CARD_TYPE                    CardType;
+} DW_MMC_HC_SLOT;
+
+typedef struct {
+  UINTN                               Signature;
+
+  EFI_HANDLE                          ControllerHandle;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+
+  EFI_SD_MMC_PASS_THRU_PROTOCOL       PassThru;
+
+  PLATFORM_DW_MMC_PROTOCOL            *PlatformDwMmc;
+
+  UINT64                              PciAttributes;
+  //
+  // The field is used to record the previous slot in GetNextSlot().
+  //
+  UINT8                               PreviousSlot;
+  //
+  // For Non-blocking operation.
+  //
+  EFI_EVENT                           TimerEvent;
+  //
+  // For Sd removable device enumeration.
+  //
+  EFI_EVENT                           ConnectEvent;
+  LIST_ENTRY                          Queue;
+
+  DW_MMC_HC_SLOT                      Slot[DW_MMC_HC_MAX_SLOT];
+  DW_MMC_HC_SLOT_CAP                  Capability[DW_MMC_HC_MAX_SLOT];
+  UINT64                              MaxCurrent[DW_MMC_HC_MAX_SLOT];
+
+  UINT32                              ControllerVersion;
+} DW_MMC_HC_PRIVATE_DATA;
+
+#define DW_MMC_HC_TRB_SIG             SIGNATURE_32 ('D', 'T', 'R', 'B')
+
+//
+// TRB (Transfer Request Block) contains information for the cmd request.
+//
+typedef struct {
+  UINT32                              Signature;
+  LIST_ENTRY                          TrbList;
+
+  UINT8                               Slot;
+  UINT16                              BlockSize;
+
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  VOID                                *Data;
+  UINT32                              DataLen;
+  BOOLEAN                             Read;
+  EFI_PHYSICAL_ADDRESS                DataPhy;
+  VOID                                *DataMap;
+  DW_MMC_HC_TRANSFER_MODE             Mode;
+
+  EFI_EVENT                           Event;
+  BOOLEAN                             Started;
+  UINT64                              Timeout;
+
+  DW_MMC_HC_DMA_DESC_LINE             *DmaDesc;
+  EFI_PHYSICAL_ADDRESS                DmaDescPhy;
+  UINT32                              DmaDescPages;
+  VOID                                *DmaMap;
+
+  BOOLEAN                             UseFifo;
+
+  DW_MMC_HC_PRIVATE_DATA              *Private;
+} DW_MMC_HC_TRB;
+
+#define DW_MMC_HC_TRB_FROM_THIS(a) \
+    CR(a, DW_MMC_HC_TRB, TrbList, DW_MMC_HC_TRB_SIG)
+
+//
+// Task for Non-blocking mode.
+//
+typedef struct {
+  UINT32                              Signature;
+  LIST_ENTRY                          Link;
+
+  UINT8                               Slot;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  BOOLEAN                             IsStart;
+  EFI_EVENT                           Event;
+  UINT64                              RetryTimes;
+  BOOLEAN                             InfiniteWait;
+  VOID                                *Map;
+  VOID                                *MapAddress;
+} DW_MMC_HC_QUEUE;
+
+//
+// Prototypes
+//
+/**
+  Execute card identification procedure.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The card is identified correctly.
+  @retval Others            The card can't be identified.
+
+**/
+typedef
+EFI_STATUS
+(*CARD_TYPE_DETECT_ROUTINE) (
+  IN DW_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  );
+
+/**
+  Sends SD command to an SD card that is attached to the SD controller.
+
+  The PassThru() function sends the SD command specified by Packet to the SD card
+  specified by Slot.
+
+  If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.
+
+  If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
+
+  If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER
+  is returned.
+
+  If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
+  EFI_INVALID_PARAMETER is returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]     Slot           The slot number of the SD card to send the command to.
+  @param[in,out] Packet         A pointer to the SD command data structure.
+  @param[in]     Event          If Event is NULL, blocking I/O is performed. If Event is
+                                not NULL, then nonblocking I/O is performed, and Event
+                                will be signaled when the Packet completes.
+
+  @retval EFI_SUCCESS           The SD Command Packet was sent by the host.
+  @retval EFI_DEVICE_ERROR      A device error occurred while attempting to send the SD
+                                command Packet.
+  @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
+  @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
+                                OutDataBuffer are NULL.
+  @retval EFI_NO_MEDIA          SD Device not present in the Slot.
+  @retval EFI_UNSUPPORTED       The command described by the SD Command Packet is not
+                                supported by the host controller.
+  @retval EFI_BAD_BUFFER_SIZE   The InTransferLength or OutTransferLength exceeds the
+                                limit supported by SD card ( i.e. if the number of bytes
+                                exceed the Last LBA).
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruPassThru (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL         *This,
+  IN     UINT8                                 Slot,
+  IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   *Packet,
+  IN     EFI_EVENT                             Event    OPTIONAL
+  );
+
+/**
+  Used to retrieve next slot numbers supported by the SD controller. The function
+  returns information about all available slots (populated or not-populated).
+
+  The GetNextSlot() function retrieves the next slot number on an SD controller.
+  If on input Slot is 0xFF, then the slot number of the first slot on the SD controller
+  is returned.
+
+  If Slot is a slot number that was returned on a previous call to GetNextSlot(), then
+  the slot number of the next slot on the SD controller is returned.
+
+  If Slot is not 0xFF and Slot was not returned on a previous call to GetNextSlot(),
+  EFI_INVALID_PARAMETER is returned.
+
+  If Slot is the slot number of the last slot on the SD controller, then EFI_NOT_FOUND
+  is returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
+  @param[in,out] Slot           On input, a pointer to a slot number on the SD controller.
+                                On output, a pointer to the next slot number on the SD controller.
+                                An input value of 0xFF retrieves the first slot number on the SD
+                                controller.
+
+  @retval EFI_SUCCESS           The next slot number on the SD controller was returned in Slot.
+  @retval EFI_NOT_FOUND         There are no more slots on this SD controller.
+  @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a previous call
+                                to GetNextSlot().
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruGetNextSlot (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL        *This,
+  IN OUT UINT8                                *Slot
+  );
+
+/**
+  Used to allocate and build a device path node for an SD card on the SD controller.
+
+  The BuildDevicePath() function allocates and builds a single device node for the SD
+  card specified by Slot.
+
+  If the SD card specified by Slot is not present on the SD controller, then EFI_NOT_FOUND
+  is returned.
+
+  If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
+
+  If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES
+  is returned.
+
+  Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of
+  DevicePath are initialized to describe the SD card specified by Slot, and EFI_SUCCESS is
+  returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
+  @param[in]     Slot           Specifies the slot number of the SD card for which a device
+                                path node is to be allocated and built.
+  @param[in,out] DevicePath     A pointer to a single device path node that describes the SD
+                                card specified by Slot. This function is responsible for
+                                allocating the buffer DevicePath with the boot service
+                                AllocatePool(). It is the caller's responsibility to free
+                                DevicePath when the caller is finished with DevicePath.
+
+  @retval EFI_SUCCESS           The device path node that describes the SD card specified by
+                                Slot was allocated and returned in DevicePath.
+  @retval EFI_NOT_FOUND         The SD card specified by Slot does not exist on the SD controller.
+  @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to allocate DevicePath.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruBuildDevicePath (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL       *This,
+  IN     UINT8                               Slot,
+  IN OUT EFI_DEVICE_PATH_PROTOCOL            **DevicePath
+  );
+
+/**
+  This function retrieves an SD card slot number based on the input device path.
+
+  The GetSlotNumber() function retrieves slot number for the SD card specified by
+  the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is returned.
+
+  If DevicePath is not a device path node type that the SD Pass Thru driver supports,
+  EFI_UNSUPPORTED is returned.
+
+  @param[in]  This              A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  DevicePath        A pointer to the device path node that describes a SD
+                                card on the SD controller.
+  @param[out] Slot              On return, points to the slot number of an SD card on
+                                the SD controller.
+
+  @retval EFI_SUCCESS           SD card slot number is returned in Slot.
+  @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL.
+  @retval EFI_UNSUPPORTED       DevicePath is not a device path node type that the SD
+                                Pass Thru driver supports.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruGetSlotNumber (
+  IN  EFI_SD_MMC_PASS_THRU_PROTOCOL          *This,
+  IN  EFI_DEVICE_PATH_PROTOCOL               *DevicePath,
+  OUT UINT8                                  *Slot
+  );
+
+/**
+  Resets an SD card that is connected to the SD controller.
+
+  The ResetDevice() function resets the SD card specified by Slot.
+
+  If this SD controller does not support a device reset operation, EFI_UNSUPPORTED is
+  returned.
+
+  If Slot is not in a valid slot number for this SD controller, EFI_INVALID_PARAMETER
+  is returned.
+
+  If the device reset operation is completed, EFI_SUCCESS is returned.
+
+  @param[in]  This              A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot              Specifies the slot number of the SD card to be reset.
+
+  @retval EFI_SUCCESS           The SD card specified by Slot was reset.
+  @retval EFI_UNSUPPORTED       The SD controller does not support a device reset operation.
+  @retval EFI_INVALID_PARAMETER Slot number is invalid.
+  @retval EFI_NO_MEDIA          SD Device not present in the Slot.
+  @retval EFI_DEVICE_ERROR      The reset command failed due to a device error
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcPassThruResetDevice (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL           *This,
+  IN UINT8                                   Slot
+  );
+
+//
+// Driver model protocol interfaces
+//
+/**
+  Tests to see if this driver supports a given controller. If a child device is provided,
+  it further tests to see if this driver supports creating a handle for the specified child device.
+
+  This function checks to see if the driver specified by This supports the device specified by
+  ControllerHandle. Drivers will typically use the device path attached to
+  ControllerHandle and/or the services from the bus I/O abstraction attached to
+  ControllerHandle to determine if the driver supports ControllerHandle. This function
+  may be called many times during platform initialization. In order to reduce boot times, the tests
+  performed by this function must be very small, and take as little time as possible to execute. This
+  function must not change the state of any hardware devices, and this function must be aware that the
+  device specified by ControllerHandle may already be managed by the same driver or a
+  different driver. This function must match its calls to AllocatePages() with FreePages(),
+  AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+  Since ControllerHandle may have been previously started by the same driver, if a protocol is
+  already in the opened state, then it must not be closed with CloseProtocol(). This is required
+  to guarantee the state of ControllerHandle is not modified by this function.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to test. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For bus drivers, if this parameter is not NULL, then
+                                   the bus driver must determine if the bus controller specified
+                                   by ControllerHandle and the child controller specified
+                                   by RemainingDevicePath are both supported by this
+                                   bus driver.
+
+  @retval EFI_SUCCESS              The device specified by ControllerHandle and
+                                   RemainingDevicePath is supported by the driver specified by This.
+  @retval EFI_ALREADY_STARTED      The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by the driver
+                                   specified by This.
+  @retval EFI_ACCESS_DENIED        The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by a different
+                                   driver or an application that requires exclusive access.
+                                   Currently not implemented.
+  @retval EFI_UNSUPPORTED          The device specified by ControllerHandle and
+                                   RemainingDevicePath is not supported by the driver specified by This.
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL *This,
+  IN EFI_HANDLE                  Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL    *RemainingDevicePath
+  );
+
+/**
+  Starts a device controller or a bus controller.
+
+  The Start() function is designed to be invoked from the EFI boot service ConnectController().
+  As a result, much of the error checking on the parameters to Start() has been moved into this
+  common boot service. It is legal to call Start() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE.
+  2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
+     EFI_DEVICE_PATH_PROTOCOL.
+  3. Prior to calling Start(), the Supported() function for the driver specified by This must
+     have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to start. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For a bus driver, if this parameter is NULL, then handles
+                                   for all the children of Controller are created by this driver.
+                                   If this parameter is not NULL and the first Device Path Node is
+                                   not the End of Device Path Node, then only the handle for the
+                                   child device specified by the first Device Path Node of
+                                   RemainingDevicePath is created by this driver.
+                                   If the first Device Path Node of RemainingDevicePath is
+                                   the End of Device Path Node, no child handle is created by this
+                                   driver.
+
+  @retval EFI_SUCCESS              The device was started.
+  @retval EFI_DEVICE_ERROR         The device could not be started due to a device error.Currently not implemented.
+  @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+  @retval Others                   The driver failded to start the device.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN EFI_HANDLE                      Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath
+  );
+
+/**
+  Stops a device controller or a bus controller.
+
+  The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+  As a result, much of the error checking on the parameters to Stop() has been moved
+  into this common boot service. It is legal to call Stop() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
+     same driver's Start() function.
+  2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
+     EFI_HANDLE. In addition, all of these handles must have been created in this driver's
+     Start() function, and the Start() function must have called OpenProtocol() on
+     ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+  @param[in]  This              A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle  A handle to the device being stopped. The handle must
+                                support a bus specific I/O protocol for the driver
+                                to use to stop the device.
+  @param[in]  NumberOfChildren  The number of child device handles in ChildHandleBuffer.
+  @param[in]  ChildHandleBuffer An array of child handles to be freed. May be NULL
+                                if NumberOfChildren is 0.
+
+  @retval EFI_SUCCESS           The device was stopped.
+  @retval EFI_DEVICE_ERROR      The device could not be stopped due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN  EFI_HANDLE                      Controller,
+  IN  UINTN                           NumberOfChildren,
+  IN  EFI_HANDLE                      *ChildHandleBuffer
+  );
+
+//
+// EFI Component Name Functions
+//
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL     *This,
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **DriverName
+  );
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL     *This,
+  IN  EFI_HANDLE                      ControllerHandle,
+  IN  EFI_HANDLE                      ChildHandle, OPTIONAL
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **ControllerName
+  );
+
+/**
+  Create a new TRB for the SD/MMC cmd request.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Packet         A pointer to the SD command data structure.
+  @param[in] Event          If Event is NULL, blocking I/O is performed. If Event is
+                            not NULL, then nonblocking I/O is performed, and Event
+                            will be signaled when the Packet completes.
+
+  @return Created Trb or NULL.
+
+**/
+DW_MMC_HC_TRB *
+DwMmcCreateTrb (
+  IN DW_MMC_HC_PRIVATE_DATA              *Private,
+  IN UINT8                               Slot,
+  IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
+  IN EFI_EVENT                           Event
+  );
+
+/**
+  Free the resource used by the TRB.
+
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+**/
+VOID
+DwMmcFreeTrb (
+  IN DW_MMC_HC_TRB           *Trb
+  );
+
+/**
+  Check if the env is ready for execute specified TRB.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The env is ready for TRB execution.
+  @retval EFI_NOT_READY     The env is not ready for TRB execution.
+  @retval Others            Some erros happen.
+
+**/
+EFI_STATUS
+DwMmcCheckTrbEnv (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Wait for the env to be ready for execute specified TRB.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The env is ready for TRB execution.
+  @retval EFI_TIMEOUT       The env is not ready for TRB execution in time.
+  @retval Others            Some erros happen.
+
+**/
+EFI_STATUS
+DwMmcWaitTrbEnv (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Execute the specified TRB.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is sent to host controller successfully.
+  @retval Others            Some erros happen when sending this request to the host controller.
+
+**/
+EFI_STATUS
+DwMmcExecTrb (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Check the TRB execution result.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is executed successfully.
+  @retval EFI_NOT_READY     The TRB is not completed for execution.
+  @retval Others            Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+DwMmcCheckTrbResult (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Wait for the TRB execution result.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is executed successfully.
+  @retval Others            Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+DwMmcWaitTrbResult (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Execute EMMC device identification procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       There is a EMMC card.
+  @retval Others            There is not a EMMC card.
+
+**/
+EFI_STATUS
+EmmcIdentification (
+  IN DW_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  );
+
+/**
+  Execute EMMC device identification procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       There is a EMMC card.
+  @retval Others            There is not a EMMC card.
+
+**/
+EFI_STATUS
+SdCardIdentification (
+  IN DW_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  );
+
+#endif
diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf
new file mode 100644
index 0000000..add6cc9
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf
@@ -0,0 +1,66 @@
+## @file
+#  DwSdMmcHcDxe driver is used to manage those host controllers which comply with
+#  Designware SD Host Controller.
+#
+#  It will produce EFI_SD_MMC_PASS_THRU_PROTOCOL to allow sending SD/MMC/eMMC cmds
+#  to specified devices from upper layer.
+#
+#  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+#  Copyright (C) 2016, Marvell International Ltd. All rights reserved.<BR>
+#  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = DwMmcHcDxe
+  MODULE_UNI_FILE                = DwMmcHcDxe.uni
+  FILE_GUID                      = 9be4d260-208c-4efe-a524-0b5d3bf77f9d
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeDwMmcHcDxe
+
+[Sources]
+  ComponentName.c
+  DwMmcHcDxe.c
+  DwMmcHcDxe.h
+  DwMmcHci.c
+  DwMmcHci.h
+  EmmcDevice.c
+  SdDevice.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  CacheMaintenanceLib
+  DebugLib
+  DevicePathLib
+  MemoryAllocationLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+  UefiRuntimeServicesTableLib
+
+[Protocols]
+  gEfiDevicePathProtocolGuid                    ## TO_START
+  gEfiPciIoProtocolGuid                         ## TO_START
+  gEfiSdMmcPassThruProtocolGuid                 ## BY_START
+  gPlatformDwMmcProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  DwMmcHcDxeExtra.uni
diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c
new file mode 100644
index 0000000..9ca044b
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c
@@ -0,0 +1,1980 @@
+/** @file
+  This driver is used to manage Designware SD/MMC PCI host controllers.
+
+  It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DwMmcHcDxe.h"
+
+/**
+  Dump the content of SD/MMC host controller's Capability Register.
+
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[in]  Capability      The buffer to store the capability data.
+
+**/
+VOID
+DumpCapabilityReg (
+  IN UINT8                Slot,
+  IN DW_MMC_HC_SLOT_CAP   *Capability
+  )
+{
+  //
+  // Dump Capability Data
+  //
+  DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
+  DEBUG ((DEBUG_INFO, "   Base Clk Freq     %dMHz\n", Capability->BaseClkFreq));
+  DEBUG ((DEBUG_INFO, "   BusWidth          %d\n", Capability->BusWidth));
+  DEBUG ((DEBUG_INFO, "   HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Voltage 1.8       %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   64-bit Sys Bus    %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   SlotType          "));
+  if (Capability->SlotType == 0x00) {
+    DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
+  } else if (Capability->SlotType == 0x01) {
+    DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
+  } else if (Capability->SlotType == 0x02) {
+    DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
+  } else {
+    DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
+  }
+  DEBUG ((DEBUG_INFO, "   SDR50  Support    %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   SDR104 Support    %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   DDR50  Support    %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
+  return;
+}
+
+/**
+  Read SlotInfo register from SD/MMC host controller pci config space.
+
+  @param[in]  PciIo        The PCI IO protocol instance.
+  @param[out] FirstBar     The buffer to store the first BAR value.
+  @param[out] SlotNum      The buffer to store the supported slot number.
+
+  @retval EFI_SUCCESS      The operation succeeds.
+  @retval Others           The operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcGetSlotInfo (
+  IN     EFI_PCI_IO_PROTOCOL   *PciIo,
+     OUT UINT8                 *FirstBar,
+     OUT UINT8                 *SlotNum
+  )
+{
+  EFI_STATUS                   Status;
+  DW_MMC_HC_SLOT_INFO          SlotInfo;
+
+  Status = PciIo->Pci.Read (
+                        PciIo,
+                        EfiPciIoWidthUint8,
+                        DW_MMC_HC_SLOT_OFFSET,
+                        sizeof (SlotInfo),
+                        &SlotInfo
+                        );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  *FirstBar = SlotInfo.FirstBar;
+  *SlotNum  = SlotInfo.SlotNum + 1;
+  ASSERT ((*FirstBar + *SlotNum) < DW_MMC_HC_MAX_SLOT);
+  return EFI_SUCCESS;
+}
+
+/**
+  Read/Write specified SD/MMC host controller mmio register.
+
+  @param[in]      PciIo        The PCI IO protocol instance.
+  @param[in]      BarIndex     The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in]      Offset       The offset within the selected BAR to start the
+                               memory operation.
+  @param[in]      Read         A boolean to indicate it's read or write operation.
+  @param[in]      Count        The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in, out] Data         For read operations, the destination buffer to store
+                               the results. For write operations, the source buffer
+                               to write data from. The caller is responsible for
+                               having ownership of the data buffer and ensuring its
+                               size not less than Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The read/write operation succeeds.
+  @retval Others                The read/write operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcRwMmio (
+  IN     EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN     UINT8                 BarIndex,
+  IN     UINT32                Offset,
+  IN     BOOLEAN               Read,
+  IN     UINT8                 Count,
+  IN OUT VOID                  *Data
+  )
+{
+  EFI_STATUS                   Status;
+
+  if ((PciIo == NULL) || (Data == NULL))  {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Read) {
+    Status = PciIo->Mem.Read (
+                          PciIo,
+                          EfiPciIoWidthUint8,
+                          BarIndex,
+                          (UINT64) Offset,
+                          Count,
+                          Data
+                          );
+  } else {
+    Status = PciIo->Mem.Write (
+                          PciIo,
+                          EfiPciIoWidthUint8,
+                          BarIndex,
+                          (UINT64) Offset,
+                          Count,
+                          Data
+                          );
+  }
+
+  return Status;
+}
+
+/**
+  Do OR operation with the value of the specified SD/MMC host controller mmio register.
+
+  @param[in] PciIo             The PCI IO protocol instance.
+  @param[in] BarIndex          The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in] Offset            The offset within the selected BAR to start the
+                               memory operation.
+  @param[in] Count             The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in] OrData            The pointer to the data used to do OR operation.
+                               The caller is responsible for having ownership of
+                               the data buffer and ensuring its size not less than
+                               Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The OR operation succeeds.
+  @retval Others                The OR operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcOrMmio (
+  IN  EFI_PCI_IO_PROTOCOL      *PciIo,
+  IN  UINT8                    BarIndex,
+  IN  UINT32                   Offset,
+  IN  UINT8                    Count,
+  IN  VOID                     *OrData
+  )
+{
+  EFI_STATUS                   Status;
+  UINT64                       Data;
+  UINT64                       Or;
+
+  Status = DwMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if (Count == 1) {
+    Or = *(UINT8*) OrData;
+  } else if (Count == 2) {
+    Or = *(UINT16*) OrData;
+  } else if (Count == 4) {
+    Or = *(UINT32*) OrData;
+  } else if (Count == 8) {
+    Or = *(UINT64*) OrData;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Data  |= Or;
+  Status = DwMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
+
+  return Status;
+}
+
+/**
+  Do AND operation with the value of the specified SD/MMC host controller mmio register.
+
+  @param[in] PciIo             The PCI IO protocol instance.
+  @param[in] BarIndex          The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in] Offset            The offset within the selected BAR to start the
+                               memory operation.
+  @param[in] Count             The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in] AndData           The pointer to the data used to do AND operation.
+                               The caller is responsible for having ownership of
+                               the data buffer and ensuring its size not less than
+                               Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The AND operation succeeds.
+  @retval Others                The AND operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcAndMmio (
+  IN  EFI_PCI_IO_PROTOCOL      *PciIo,
+  IN  UINT8                    BarIndex,
+  IN  UINT32                   Offset,
+  IN  UINT8                    Count,
+  IN  VOID                     *AndData
+  )
+{
+  EFI_STATUS                   Status;
+  UINT64                       Data;
+  UINT64                       And;
+
+  Status = DwMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if (Count == 1) {
+    And = *(UINT8*) AndData;
+  } else if (Count == 2) {
+    And = *(UINT16*) AndData;
+  } else if (Count == 4) {
+    And = *(UINT32*) AndData;
+  } else if (Count == 8) {
+    And = *(UINT64*) AndData;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Data  &= And;
+  Status = DwMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
+
+  return Status;
+}
+
+/**
+  Wait for the value of the specified MMIO register set to the test value.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  BarIndex      The BAR index of the standard PCI Configuration
+                            header to use as the base address for the memory
+                            operation to perform.
+  @param[in]  Offset        The offset within the selected BAR to start the
+                            memory operation.
+  @param[in]  Count         The width of the mmio register in bytes.
+                            Must be 1, 2, 4 or 8 bytes.
+  @param[in]  MaskValue     The mask value of memory.
+  @param[in]  TestValue     The test value of memory.
+
+  @retval EFI_NOT_READY     The MMIO register hasn't set to the expected value.
+  @retval EFI_SUCCESS       The MMIO register has expected value.
+  @retval Others            The MMIO operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcCheckMmioSet (
+  IN  EFI_PCI_IO_PROTOCOL       *PciIo,
+  IN  UINT8                     BarIndex,
+  IN  UINT32                    Offset,
+  IN  UINT8                     Count,
+  IN  UINT64                    MaskValue,
+  IN  UINT64                    TestValue
+  )
+{
+  EFI_STATUS            Status;
+  UINT64                Value;
+
+  //
+  // Access PCI MMIO space to see if the value is the tested one.
+  //
+  Value  = 0;
+  Status = DwMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Value &= MaskValue;
+
+  if (Value == TestValue) {
+    return EFI_SUCCESS;
+  }
+
+  return EFI_NOT_READY;
+}
+
+/**
+  Wait for the value of the specified MMIO register set to the test value.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  BarIndex      The BAR index of the standard PCI Configuration
+                            header to use as the base address for the memory
+                            operation to perform.
+  @param[in]  Offset        The offset within the selected BAR to start the
+                            memory operation.
+  @param[in]  Count         The width of the mmio register in bytes.
+                            Must be 1, 2, 4 or 8 bytes.
+  @param[in]  MaskValue     The mask value of memory.
+  @param[in]  TestValue     The test value of memory.
+  @param[in]  Timeout       The time out value for wait memory set, uses 1
+                            microsecond as a unit.
+
+  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
+                            range.
+  @retval EFI_SUCCESS       The MMIO register has expected value.
+  @retval Others            The MMIO operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcWaitMmioSet (
+  IN  EFI_PCI_IO_PROTOCOL       *PciIo,
+  IN  UINT8                     BarIndex,
+  IN  UINT32                    Offset,
+  IN  UINT8                     Count,
+  IN  UINT64                    MaskValue,
+  IN  UINT64                    TestValue,
+  IN  UINT64                    Timeout
+  )
+{
+  EFI_STATUS            Status;
+  BOOLEAN               InfiniteWait;
+
+  if (Timeout == 0) {
+    InfiniteWait = TRUE;
+  } else {
+    InfiniteWait = FALSE;
+  }
+
+  while (InfiniteWait || (Timeout > 0)) {
+    Status = DwMmcHcCheckMmioSet (
+               PciIo,
+               BarIndex,
+               Offset,
+               Count,
+               MaskValue,
+               TestValue
+               );
+    if (Status != EFI_NOT_READY) {
+      return Status;
+    }
+
+    //
+    // Stall for 1 microsecond.
+    //
+    gBS->Stall (1);
+
+    Timeout--;
+  }
+
+  return EFI_TIMEOUT;
+}
+
+/**
+  Set all interrupt status bits in Normal and Error Interrupt Status Enable
+  register.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation executes successfully.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+DwMmcHcEnableInterrupt (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    IntStatus;
+  UINT32                    IdIntEn;
+  UINT32                    IdSts;
+
+  //
+  // Enable all bits in Interrupt Mask Register
+  //
+  IntStatus = 0;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_INTMASK, FALSE, sizeof (IntStatus), &IntStatus);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Clear status in Interrupt Status Register
+  //
+  IntStatus = ~0;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_RINTSTS, FALSE, sizeof (IntStatus), &IntStatus);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  IdIntEn = ~0;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_IDINTEN, FALSE, sizeof (IdIntEn), &IdIntEn);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcReset: init dma interrupts fail: %r\n", Status));
+    return Status;
+  }
+
+  IdSts = ~0;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_IDSTS, FALSE, sizeof (IdSts), &IdSts);
+  return Status;
+}
+
+/**
+  Get the capability data from the specified slot.
+
+  @param[in]  PciIo           The PCI IO protocol instance.
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[out] Capability      The buffer to store the capability data.
+
+  @retval EFI_SUCCESS         The operation executes successfully.
+  @retval Others              The operation fails.
+
+**/
+EFI_STATUS
+DwMmcHcGetCapability (
+  IN     EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN     EFI_HANDLE           Controller,
+  IN     UINT8                Slot,
+     OUT DW_MMC_HC_SLOT_CAP   *Capacity
+  )
+{
+  PLATFORM_DW_MMC_PROTOCOL    *PlatformDwMmc;
+  EFI_STATUS                Status;
+
+  if (Capacity == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = gBS->LocateProtocol (
+                  &gPlatformDwMmcProtocolGuid,
+                  NULL,
+                  (VOID **) &PlatformDwMmc
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = PlatformDwMmc->GetCapability (Controller, Slot, Capacity);
+  return Status;
+}
+
+/**
+  Get the maximum current capability data from the specified slot.
+
+  @param[in]  PciIo           The PCI IO protocol instance.
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[out] MaxCurrent      The buffer to store the maximum current capability data.
+
+  @retval EFI_SUCCESS         The operation executes successfully.
+  @retval Others              The operation fails.
+
+**/
+EFI_STATUS
+DwMmcHcGetMaxCurrent (
+  IN     EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN     UINT8                Slot,
+     OUT UINT64               *MaxCurrent
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
+  slot.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[out] MediaPresent  The pointer to the media present boolean value.
+
+  @retval EFI_SUCCESS       There is no media change happened.
+  @retval EFI_MEDIA_CHANGED There is media change happened.
+  @retval Others            The detection fails.
+
+**/
+EFI_STATUS
+DwMmcHcCardDetect (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+     OUT BOOLEAN            *MediaPresent
+  )
+{
+  PLATFORM_DW_MMC_PROTOCOL  *PlatformDwMmc;
+  EFI_STATUS                Status;
+
+  if (MediaPresent == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = gBS->LocateProtocol (
+                  &gPlatformDwMmcProtocolGuid,
+                  NULL,
+                  (VOID **) &PlatformDwMmc
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  *MediaPresent = PlatformDwMmc->CardDetect (Slot);
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+DwMmcHcUpdateClock (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    Cmd;
+  UINT32                    IntStatus;
+
+  Cmd = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
+        BIT_CMD_START;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CMD, FALSE, sizeof (Cmd), &Cmd);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  while (1) {
+    Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CMD, TRUE, sizeof (Cmd), &Cmd);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    if (!(Cmd & CMD_START_BIT)) {
+      break;
+    }
+    Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_RINTSTS, TRUE, sizeof (IntStatus), &IntStatus);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    if (IntStatus & DW_MMC_INT_HLE) {
+      DEBUG ((DEBUG_ERROR, "DwMmcHcUpdateClock: failed to update mmc clock frequency\n"));
+      return EFI_DEVICE_ERROR;
+    }
+  }
+  return EFI_SUCCESS;
+
+}
+
+/**
+  Stop SD/MMC card clock.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
+  @retval Others            Fail to stop SD/MMC clock.
+
+**/
+EFI_STATUS
+DwMmcHcStopClock (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    ClkEna;
+
+  // Disable MMC clock first
+  ClkEna = 0;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CLKENA, FALSE, sizeof (ClkEna), &ClkEna);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = DwMmcHcUpdateClock (PciIo, Slot);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return Status;
+}
+
+/**
+  SD/MMC card clock supply.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The clock is supplied successfully.
+  @retval Others            The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+DwMmcHcClockSupply (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT64                 ClockFreq,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    BaseClkFreq;
+  UINT32                    SettingFreq;
+  UINT32                    Divisor;
+  UINT32                    Remainder;
+  UINT32                    MmcStatus;
+  UINT32                    ClkEna;
+  UINT32                    ClkSrc;
+
+  //
+  // Calculate a divisor for SD clock frequency
+  //
+  ASSERT (Capability.BaseClkFreq != 0);
+
+  BaseClkFreq = Capability.BaseClkFreq;
+  if (ClockFreq == 0) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (ClockFreq > BaseClkFreq) {
+    ClockFreq = BaseClkFreq;
+  }
+
+  //
+  // Calculate the divisor of base frequency.
+  //
+  Divisor     = 0;
+  SettingFreq = BaseClkFreq;
+  while (ClockFreq < SettingFreq) {
+    Divisor++;
+
+    SettingFreq = BaseClkFreq / (2 * Divisor);
+    Remainder   = BaseClkFreq % (2 * Divisor);
+    if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
+      break;
+    }
+    if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
+      SettingFreq ++;
+    }
+  }
+
+  DEBUG ((DEBUG_INFO, "BaseClkFreq %dKHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
+
+  // Wait until MMC is idle
+  do {
+    Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_STATUS, TRUE, sizeof (MmcStatus), &MmcStatus);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  } while (MmcStatus & DW_MMC_STS_DATA_BUSY);
+
+  do {
+    Status = DwMmcHcStopClock (PciIo, Slot);
+  } while (EFI_ERROR (Status));
+
+  do {
+    ClkSrc = 0;
+    Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CLKSRC, FALSE, sizeof (ClkSrc), &ClkSrc);
+    if (EFI_ERROR (Status)) {
+      continue;
+    }
+    // Set clock divisor
+    Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CLKDIV, FALSE, sizeof (Divisor), &Divisor);
+    if (EFI_ERROR (Status)) {
+      continue;
+    }
+    // Enable MMC clock
+    ClkEna = 1;
+    Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CLKENA, FALSE, sizeof (ClkEna), &ClkEna);
+    if (EFI_ERROR (Status)) {
+      continue;
+    }
+    Status = DwMmcHcUpdateClock (PciIo, Slot);
+  } while (EFI_ERROR (Status));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  SD/MMC bus power control.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] PowerCtrl      The value setting to the power control register.
+
+  @retval TRUE              There is a SD/MMC card attached.
+  @retval FALSE             There is no a SD/MMC card attached.
+
+**/
+EFI_STATUS
+DwMmcHcPowerControl (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT8                  PowerCtrl
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Set the SD/MMC bus width.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
+
+  @retval EFI_SUCCESS       The bus width is set successfully.
+  @retval Others            The bus width isn't set successfully.
+
+**/
+EFI_STATUS
+DwMmcHcSetBusWidth (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN BOOLEAN                IsDdr,
+  IN UINT16                 BusWidth
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    Ctype;
+  UINT32                    Uhs;
+
+  switch (BusWidth) {
+  case 1:
+    Ctype = MMC_1BIT_MODE;
+    break;
+  case 4:
+    Ctype = MMC_4BIT_MODE;
+    break;
+  case 8:
+    Ctype = MMC_8BIT_MODE;
+    break;
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CTYPE, FALSE, sizeof (Ctype), &Ctype);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_UHSREG, TRUE, sizeof (Uhs), &Uhs);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  if (IsDdr) {
+    Uhs |= UHS_DDR_MODE;
+  } else {
+    Uhs &= ~(UHS_DDR_MODE);
+  }
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_UHSREG, FALSE, sizeof (Uhs), &Uhs);
+  return Status;
+}
+
+/**
+  Supply SD/MMC card with lowest clock frequency at initialization.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The clock is supplied successfully.
+  @retval Others            The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+DwMmcHcInitClockFreq (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    InitFreq;
+
+  //
+  // Calculate a divisor for SD clock frequency
+  //
+  if (Capability.BaseClkFreq == 0) {
+    //
+    // Don't support get Base Clock Frequency information via another method
+    //
+    return EFI_UNSUPPORTED;
+  }
+  //
+  // Supply 400KHz clock frequency at initialization phase.
+  //
+  InitFreq = DWMMC_INIT_CLOCK_FREQ;
+  Status = DwMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  MicroSecondDelay (100);
+  return Status;
+}
+
+/**
+  Supply SD/MMC card with maximum voltage at initialization.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The voltage is supplied successfully.
+  @retval Others            The voltage isn't supplied successfully.
+
+**/
+EFI_STATUS
+DwMmcHcInitPowerVoltage (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    Data;
+
+  Data = 0x1;
+  Status  = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_PWREN, FALSE, sizeof (Data), &Data);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcInitPowerVoltage: enable power fails: %r\n", Status));
+    return Status;
+  }
+
+  Data = DW_MMC_CTRL_RESET_ALL;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CTRL, FALSE, sizeof (Data), &Data);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcInitPowerVoltage: reset fails: %r\n", Status));
+    return Status;
+  }
+  Status = DwMmcHcWaitMmioSet (
+             PciIo,
+             Slot,
+             DW_MMC_CTRL,
+             sizeof (Data),
+             DW_MMC_CTRL_RESET_ALL,
+             0x00,
+             DW_MMC_HC_GENERIC_TIMEOUT
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "DwMmcHcInitPowerVoltage: reset done with %r\n", Status));
+    return Status;
+  }
+
+  Data = DW_MMC_CTRL_INT_EN;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_CTRL, FALSE, sizeof (Data), &Data);
+  return Status;
+}
+
+/**
+  Initialize the Timeout Control register with most conservative value at initialization.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The timeout control register is configured successfully.
+  @retval Others            The timeout control register isn't configured successfully.
+
+**/
+EFI_STATUS
+DwMmcHcInitTimeoutCtrl (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    Data;
+
+  Data = ~0;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_TMOUT, FALSE, sizeof (Data), &Data);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcInitTimeoutCtrl: set timeout fails: %r\n", Status));
+    return Status;
+  }
+
+  Data = 0x00FFFFFF;
+  Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_DEBNCE, FALSE, sizeof (Data), &Data);
+  return Status;
+}
+
+/**
+  Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
+  at initialization.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The host controller is initialized successfully.
+  @retval Others            The host controller isn't initialized successfully.
+
+**/
+EFI_STATUS
+DwMmcHcInitHost (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS       Status;
+
+  Status = DwMmcHcInitPowerVoltage (PciIo, Slot, Capability);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return Status;
+}
+
+EFI_STATUS
+DwMmcHcStartDma (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+  UINT32                              Ctrl;
+  UINT32                              Bmod;
+
+  PciIo  = Trb->Private->PciIo;
+
+  // Reset DMA
+  Ctrl = DW_MMC_CTRL_DMA_RESET;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_CTRL, FALSE, sizeof (Ctrl), &Ctrl);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcStartDma: reset fails: %r\n", Status));
+    return Status;
+  }
+  Status = DwMmcHcWaitMmioSet (
+             PciIo,
+             Trb->Slot,
+             DW_MMC_CTRL,
+             sizeof (Ctrl),
+             DW_MMC_CTRL_DMA_RESET,
+             0x00,
+             DW_MMC_HC_GENERIC_TIMEOUT
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "DwMmcHcStartDma: reset done with %r\n", Status));
+    return Status;
+  }
+  Bmod = DW_MMC_IDMAC_SWRESET;
+  Status = DwMmcHcOrMmio (PciIo, Trb->Slot, DW_MMC_BMOD, sizeof (Bmod), &Bmod);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcStartDma: set BMOD fail: %r\n", Status));
+    return Status;
+  }
+
+  // Select IDMAC
+  Ctrl = DW_MMC_CTRL_IDMAC_EN;
+  Status = DwMmcHcOrMmio (PciIo, Trb->Slot, DW_MMC_CTRL, sizeof (Ctrl), &Ctrl);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcStartDma: init IDMAC fail: %r\n", Status));
+    return Status;
+  }
+
+  // Enable IDMAC
+  Bmod = DW_MMC_IDMAC_ENABLE | DW_MMC_IDMAC_FB;
+  Status = DwMmcHcOrMmio (PciIo, Trb->Slot, DW_MMC_BMOD, sizeof (Bmod), &Bmod);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "DwMmcHcReset: set BMOD failure: %r\n", Status));
+    return Status;
+  }
+  return Status;
+}
+
+EFI_STATUS
+DwMmcHcStopDma (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+  UINT32                              Ctrl;
+  UINT32                              Bmod;
+
+  PciIo  = Trb->Private->PciIo;
+
+  // Disable and reset IDMAC
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_CTRL, TRUE, sizeof (Ctrl), &Ctrl);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Ctrl &= ~DW_MMC_CTRL_IDMAC_EN;
+  Ctrl |= DW_MMC_CTRL_DMA_RESET;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_CTRL, FALSE, sizeof (Ctrl), &Ctrl);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  // Stop IDMAC
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_BMOD, TRUE, sizeof (Bmod), &Bmod);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Bmod &= ~(DW_MMC_BMOD_FB | DW_MMC_BMOD_DE);
+  Bmod |= DW_MMC_BMOD_SWR;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_BMOD, FALSE, sizeof (Bmod), &Bmod);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return Status;
+}
+
+/**
+  Build DMA descriptor table for transfer.
+
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The DMA descriptor table is created successfully.
+  @retval Others            The DMA descriptor table isn't created successfully.
+
+**/
+EFI_STATUS
+BuildDmaDescTable (
+  IN DW_MMC_HC_TRB          *Trb
+  )
+{
+  EFI_PHYSICAL_ADDRESS      Data;
+  UINT64                    DataLen;
+  UINT64                    Entries;
+  UINT32                    Index;
+  UINT64                    Remaining;
+  UINTN                     TableSize;
+  EFI_PCI_IO_PROTOCOL       *PciIo;
+  EFI_STATUS                Status;
+  UINTN                     Bytes;
+  UINTN                     Blocks;
+  DW_MMC_HC_DMA_DESC_LINE   *DmaDesc;
+  UINT32                    DmaDescPhy;
+  UINT32                    Idsts;
+  UINT32                    BytCnt;
+  UINT32                    BlkSize;
+
+  Data    = Trb->DataPhy;
+  DataLen = Trb->DataLen;
+  PciIo   = Trb->Private->PciIo;
+  //
+  // Only support 32bit DMA Descriptor Table
+  //
+  if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  //
+  // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
+  // for 32-bit address descriptor table.
+  //
+  if ((Data & (BIT0 | BIT1)) != 0) {
+    DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct DMA desc is not aligned to 4 bytes boundary!\n", Data));
+  }
+
+  Entries   = (DataLen + DWMMC_DMA_BUF_SIZE - 1) / DWMMC_DMA_BUF_SIZE;
+  TableSize = Entries * sizeof (DW_MMC_HC_DMA_DESC_LINE);
+  Blocks    = (DataLen + DW_MMC_BLOCK_SIZE - 1) / DW_MMC_BLOCK_SIZE;
+
+  Trb->DmaDescPages = (UINT32)EFI_SIZE_TO_PAGES (Entries * DWMMC_DMA_BUF_SIZE);
+  Status = PciIo->AllocateBuffer (
+                    PciIo,
+                    AllocateAnyPages,
+                    EfiBootServicesData,
+                    EFI_SIZE_TO_PAGES (TableSize),
+                    (VOID **)&Trb->DmaDesc,
+                    0
+                    );
+  if (EFI_ERROR (Status)) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  ZeroMem (Trb->DmaDesc, TableSize);
+  Bytes  = TableSize;
+  Status = PciIo->Map (
+                    PciIo,
+                    EfiPciIoOperationBusMasterCommonBuffer,
+                    Trb->DmaDesc,
+                    &Bytes,
+                    &Trb->DmaDescPhy,
+                    &Trb->DmaMap
+                    );
+
+  if (EFI_ERROR (Status) || (Bytes != TableSize)) {
+    //
+    // Map error or unable to map the whole RFis buffer into a contiguous region.
+    //
+    PciIo->FreeBuffer (
+             PciIo,
+             EFI_SIZE_TO_PAGES (TableSize),
+             Trb->DmaDesc
+             );
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  if ((UINT64)(UINTN)Trb->DmaDescPhy > 0x100000000ul) {
+    //
+    // The DMA doesn't support 64bit addressing.
+    //
+    PciIo->Unmap (
+      PciIo,
+      Trb->DmaMap
+    );
+#if 0
+    PciIo->FreeBuffer (
+      PciIo,
+      EFI_SIZE_TO_PAGES (TableSize),
+      Trb->DmaDesc
+    );
+#endif
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (DataLen < DW_MMC_BLOCK_SIZE) {
+    BlkSize = DataLen;
+    BytCnt = DataLen;
+    Remaining = DataLen;
+  } else {
+    BlkSize = DW_MMC_BLOCK_SIZE;
+    BytCnt = DW_MMC_BLOCK_SIZE * Blocks;
+    Remaining = DW_MMC_BLOCK_SIZE * Blocks;
+  }
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_BLKSIZ, FALSE, sizeof (BlkSize), &BlkSize);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "BuildDmaDescTable: set block size fails: %r\n", Status));
+    return Status;
+  }
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_BYTCNT, FALSE, sizeof (BytCnt), &BytCnt);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  DmaDesc = Trb->DmaDesc;
+  for (Index = 0; Index < Entries; Index++, DmaDesc++) {
+    DmaDesc->Des0 = DW_MMC_IDMAC_DES0_OWN | DW_MMC_IDMAC_DES0_CH |
+                    DW_MMC_IDMAC_DES0_DIC;
+    DmaDesc->Des1 = DW_MMC_IDMAC_DES1_BS1 (DWMMC_DMA_BUF_SIZE);
+    // Buffer Address
+    DmaDesc->Des2 = (UINT32)((UINTN)Trb->DataPhy + (DWMMC_DMA_BUF_SIZE * Index));
+    // Next Descriptor Address
+    DmaDesc->Des3 = (UINT32)((UINTN)Trb->DmaDescPhy + sizeof (DW_MMC_HC_DMA_DESC_LINE) * (Index + 1));
+    Remaining = Remaining - DWMMC_DMA_BUF_SIZE;
+  }
+  // First Descriptor
+  Trb->DmaDesc[0].Des0 |= DW_MMC_IDMAC_DES0_FS;
+  // Last Descriptor
+  Trb->DmaDesc[Entries - 1].Des0 &= ~(DW_MMC_IDMAC_DES0_CH | DW_MMC_IDMAC_DES0_DIC);
+  Trb->DmaDesc[Entries - 1].Des0 |= DW_MMC_IDMAC_DES0_OWN | DW_MMC_IDMAC_DES0_LD;
+  Trb->DmaDesc[Entries - 1].Des1 = DW_MMC_IDMAC_DES1_BS1 (Remaining + DWMMC_DMA_BUF_SIZE);
+  // Set the next field of the Last Descriptor
+  Trb->DmaDesc[Entries - 1].Des3 = 0;
+  DmaDescPhy = (UINT32)Trb->DmaDescPhy;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_DBADDR, FALSE, sizeof (DmaDescPhy), &DmaDescPhy);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ArmDataSynchronizationBarrier ();
+  ArmInstructionSynchronizationBarrier ();
+  // Clear interrupts
+  Idsts = ~0;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_IDSTS, FALSE, sizeof (Idsts), &Idsts);
+  return Status;
+}
+
+EFI_STATUS
+ReadFifo (
+  IN DW_MMC_HC_TRB          *Trb
+  )
+{
+  EFI_STATUS                Status;
+  EFI_PCI_IO_PROTOCOL       *PciIo;
+  UINT32                    Data;
+  UINT32                    Received;
+  UINT32                    Count;
+  UINT32                    Intsts;
+  UINT32                    Sts;
+  UINT32                    FifoCount;
+
+  PciIo   = Trb->Private->PciIo;
+  Received = 0;
+  Count = (Trb->DataLen + 3) / 4;
+  while (1) {
+    Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RINTSTS, TRUE, sizeof (Intsts), &Intsts);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "ReadFifo: failed to read RINTSTS, Status:%r\n", Status));
+      return Status;
+    }
+    if (Intsts & DW_MMC_INT_DTO) {
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_STATUS, TRUE, sizeof (Sts), &Sts);
+      if (EFI_ERROR (Status)) {
+        DEBUG ((DEBUG_ERROR, "ReadFifo: failed to read STATUS, Status:%r\n", Status));
+        return Status;
+      }
+      // Convert to bytes
+      FifoCount = GET_STS_FIFO_COUNT (Sts) << 2;
+      Count = (MIN (FifoCount, Trb->DataLen) + 3) / 4;
+      Received = 0;
+      // Read FIFO
+      while (Count && (Received < Count)) {
+        Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_FIFO_START, TRUE, sizeof (Data), &Data);
+        if (EFI_ERROR (Status)) {
+          DEBUG ((DEBUG_ERROR, "ReadFifo: failed to read FIFO, Status:%r\n", Status));
+          return Status;
+        }
+        *(UINT32 *)((UINTN)Trb->Data + ((Count - Received - 1) << 2)) = SwapBytes32 (Data);
+        Received++;
+      }
+    }
+    if (Intsts & DW_MMC_INT_CMD_DONE) {
+      if ((Intsts == DW_MMC_INT_CMD_DONE) && Count) {
+        // CMD_DONE interrupt comes earlier before other interrupts. Just wait for a while.
+        continue;
+      } else {
+        break;
+      }
+    }
+  }
+  Intsts = ~0;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RINTSTS, FALSE, sizeof (Intsts), &Intsts);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ReadFifo: failed to write RINTSTS, Status:%r\n", Status));
+    return Status;
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Create a new TRB for the SD/MMC cmd request.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Packet         A pointer to the SD command data structure.
+  @param[in] Event          If Event is NULL, blocking I/O is performed. If Event is
+                            not NULL, then nonblocking I/O is performed, and Event
+                            will be signaled when the Packet completes.
+
+  @return Created Trb or NULL.
+
+**/
+DW_MMC_HC_TRB *
+DwMmcCreateTrb (
+  IN DW_MMC_HC_PRIVATE_DATA              *Private,
+  IN UINT8                               Slot,
+  IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
+  IN EFI_EVENT                           Event
+  )
+{
+  DW_MMC_HC_TRB                 *Trb;
+  EFI_STATUS                    Status;
+  EFI_TPL                       OldTpl;
+  EFI_PCI_IO_PROTOCOL_OPERATION Flag;
+  EFI_PCI_IO_PROTOCOL           *PciIo;
+  UINTN                         MapLength;
+
+  Trb = AllocateZeroPool (sizeof (DW_MMC_HC_TRB));
+  if (Trb == NULL) {
+    return NULL;
+  }
+
+  Trb->Signature = DW_MMC_HC_TRB_SIG;
+  Trb->Slot      = Slot;
+  Trb->BlockSize = 0x200;
+  Trb->Packet    = Packet;
+  Trb->Event     = Event;
+  Trb->Started   = FALSE;
+  Trb->Timeout   = Packet->Timeout;
+  Trb->Private   = Private;
+
+  if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
+    Trb->Data    = Packet->InDataBuffer;
+    Trb->DataLen = Packet->InTransferLength;
+    Trb->Read    = TRUE;
+    ZeroMem (Trb->Data, Trb->DataLen);
+  } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
+    Trb->Data    = Packet->OutDataBuffer;
+    Trb->DataLen = Packet->OutTransferLength;
+    Trb->Read    = FALSE;
+  } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
+    Trb->Data    = NULL;
+    Trb->DataLen = 0;
+  } else {
+    goto Error;
+  }
+
+  if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
+       (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
+      ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
+       (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
+    Trb->Mode = SdMmcPioMode;
+  } else {
+    if (Trb->Read) {
+      Flag = EfiPciIoOperationBusMasterWrite;
+    } else {
+      Flag = EfiPciIoOperationBusMasterRead;
+    }
+
+    PciIo = Private->PciIo;
+    if ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
+        (Trb->DataLen != 0) &&
+        (Trb->DataLen <= DWMMC_FIFO_THRESHOLD)) {
+      Trb->UseFifo = TRUE;
+    } else {
+      Trb->UseFifo = FALSE;
+      if (Trb->DataLen) {
+        MapLength = Trb->DataLen;
+        Status = PciIo->Map (
+                          PciIo,
+                          Flag,
+                          Trb->Data,
+                          &MapLength,
+                          &Trb->DataPhy,
+                          &Trb->DataMap
+                          );
+        if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
+          Status = EFI_BAD_BUFFER_SIZE;
+          goto Error;
+        }
+
+        Status = BuildDmaDescTable (Trb);
+        if (EFI_ERROR (Status)) {
+          PciIo->Unmap (PciIo, Trb->DataMap);
+          goto Error;
+        }
+        Status = DwMmcHcStartDma (Private, Trb);
+        if (EFI_ERROR (Status)) {
+          PciIo->Unmap (PciIo, Trb->DataMap);
+          goto Error;
+        }
+      }
+    }
+  } // TuningBlock
+
+  if (Event != NULL) {
+    OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+    InsertTailList (&Private->Queue, &Trb->TrbList);
+    gBS->RestoreTPL (OldTpl);
+  }
+
+  return Trb;
+
+Error:
+  //DwMmcFreeTrb (Trb);
+  return NULL;
+}
+
+/**
+  Free the resource used by the TRB.
+
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+**/
+VOID
+DwMmcFreeTrb (
+  IN DW_MMC_HC_TRB           *Trb
+  )
+{
+  EFI_PCI_IO_PROTOCOL        *PciIo;
+
+  PciIo = Trb->Private->PciIo;
+
+  if (Trb->DmaMap != NULL) {
+    PciIo->Unmap (
+      PciIo,
+      Trb->DmaMap
+    );
+  }
+#if 0
+  // Free is handled in Unmap().
+  if (Trb->DmaDesc != NULL) {
+    PciIo->FreeBuffer (
+      PciIo,
+      Trb->DmaDescPages,
+      Trb->DmaDesc
+    );
+  }
+#endif
+  if (Trb->DataMap != NULL) {
+    PciIo->Unmap (
+      PciIo,
+      Trb->DataMap
+    );
+  }
+  FreePool (Trb);
+  return;
+}
+
+/**
+  Check if the env is ready for execute specified TRB.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The env is ready for TRB execution.
+  @retval EFI_NOT_READY     The env is not ready for TRB execution.
+  @retval Others            Some erros happen.
+
+**/
+EFI_STATUS
+DwMmcCheckTrbEnv (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Wait for the env to be ready for execute specified TRB.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The env is ready for TRB execution.
+  @retval EFI_TIMEOUT       The env is not ready for TRB execution in time.
+  @retval Others            Some erros happen.
+
+**/
+EFI_STATUS
+DwMmcWaitTrbEnv (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  UINT64                              Timeout;
+  BOOLEAN                             InfiniteWait;
+
+  //
+  // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
+  //
+  Packet  = Trb->Packet;
+  Timeout = Packet->Timeout;
+  if (Timeout == 0) {
+    InfiniteWait = TRUE;
+  } else {
+    InfiniteWait = FALSE;
+  }
+
+  while (InfiniteWait || (Timeout > 0)) {
+    //
+    // Check Trb execution result by reading Normal Interrupt Status register.
+    //
+    Status = DwMmcCheckTrbEnv (Private, Trb);
+    if (Status != EFI_NOT_READY) {
+      return Status;
+    }
+    //
+    // Stall for 1 microsecond.
+    //
+    gBS->Stall (1);
+
+    Timeout--;
+  }
+
+  return EFI_TIMEOUT;
+}
+
+EFI_STATUS
+DwEmmcExecTrb (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+  UINT32                              Cmd;
+  UINT32                              MmcStatus;
+  UINT32                              IntStatus;
+  UINT32                              Argument;
+  UINT32                              ErrMask;
+
+  Packet = Trb->Packet;
+  PciIo  = Trb->Private->PciIo;
+
+  // Wait until MMC is idle
+  do {
+    Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_STATUS, TRUE, sizeof (MmcStatus), &MmcStatus);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  } while (MmcStatus & DW_MMC_STS_DATA_BUSY);
+
+  IntStatus = ~0;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RINTSTS, FALSE, sizeof (IntStatus), &IntStatus);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Cmd = CMD_INDEX (Packet->SdMmcCmdBlk->CommandIndex);
+  if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAc) ||
+      (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc)) {
+    switch (Packet->SdMmcCmdBlk->CommandIndex) {
+    case EMMC_SET_RELATIVE_ADDR:
+      Cmd |= BIT_CMD_SEND_INIT;
+      break;
+    case EMMC_SEND_STATUS:
+      Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE;
+      break;
+    case EMMC_STOP_TRANSMISSION:
+      Cmd |= BIT_CMD_STOP_ABORT_CMD;
+      break;
+    }
+    if (Packet->InTransferLength) {
+      Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
+    } else if (Packet->OutTransferLength) {
+      Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
+    }
+    Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+  } else {
+    switch (Packet->SdMmcCmdBlk->CommandIndex) {
+    case EMMC_GO_IDLE_STATE:
+      Cmd |= BIT_CMD_SEND_INIT;
+      break;
+    case EMMC_SEND_OP_COND:
+      Cmd |= BIT_CMD_RESPONSE_EXPECT;
+      break;
+    case EMMC_ALL_SEND_CID:
+      Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
+             BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
+      break;
+    }
+  }
+  switch (Packet->SdMmcCmdBlk->ResponseType) {
+  case SdMmcResponseTypeR2:
+    Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_LONG_RESPONSE;
+    break;
+  case SdMmcResponseTypeR3:
+    Cmd |= BIT_CMD_RESPONSE_EXPECT;
+    break;
+  }
+  Cmd |= BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
+
+  Argument = Packet->SdMmcCmdBlk->CommandArgument;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_CMDARG, FALSE, sizeof (Argument), &Argument);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_CMD, FALSE, sizeof (Cmd), &Cmd);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  ErrMask = DW_MMC_INT_EBE | DW_MMC_INT_HLE | DW_MMC_INT_RTO |
+            DW_MMC_INT_RCRC | DW_MMC_INT_RE;
+  ErrMask |= DW_MMC_INT_DCRC | DW_MMC_INT_DRT | DW_MMC_INT_SBE;
+  do {
+    MicroSecondDelay (500);
+    Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RINTSTS, TRUE, sizeof (IntStatus), &IntStatus);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    if (IntStatus & ErrMask) {
+      return EFI_DEVICE_ERROR;
+    }
+    if (IntStatus & DW_MMC_INT_DTO) {  // Transfer Done
+      break;
+    }
+  } while (!(IntStatus & DW_MMC_INT_CMD_DONE));
+  switch (Packet->SdMmcCmdBlk->ResponseType) {
+    case SdMmcResponseTypeR1:
+    case SdMmcResponseTypeR1b:
+    case SdMmcResponseTypeR3:
+    case SdMmcResponseTypeR4:
+    case SdMmcResponseTypeR5:
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP0, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp0), &Packet->SdMmcStatusBlk->Resp0);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      break;
+    case SdMmcResponseTypeR2:
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP0, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp0), &Packet->SdMmcStatusBlk->Resp0);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP1, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp1), &Packet->SdMmcStatusBlk->Resp1);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP2, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp2), &Packet->SdMmcStatusBlk->Resp2);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP3, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp3), &Packet->SdMmcStatusBlk->Resp3);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      break;
+  }
+
+  //
+  // The workaround on EMMC_SEND_CSD is used to be compatible with SDHC.
+  //
+  if (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_CSD) {
+    {
+      UINT32   Buf[4];
+      ZeroMem (Buf, sizeof (Buf));
+      CopyMem ((UINT8 *)Buf, (UINT8 *)&Packet->SdMmcStatusBlk->Resp0 + 1, sizeof (Buf) - 1);
+      CopyMem ((UINT8 *)&Packet->SdMmcStatusBlk->Resp0, (UINT8 *)Buf, sizeof (Buf) - 1);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DwSdExecTrb (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+  UINT32                              Cmd;
+  UINT32                              MmcStatus;
+  UINT32                              IntStatus;
+  UINT32                              Argument;
+  UINT32                              ErrMask;
+  UINT32                              Timeout;
+  UINT32                              Idsts;
+  UINT32                              BytCnt;
+  UINT32                              BlkSize;
+
+  Packet = Trb->Packet;
+  PciIo  = Trb->Private->PciIo;
+
+  ArmDataSynchronizationBarrier ();
+  ArmInstructionSynchronizationBarrier ();
+  // Wait until MMC is idle
+  do {
+    Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_STATUS, TRUE, sizeof (MmcStatus), &MmcStatus);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  } while (MmcStatus & DW_MMC_STS_DATA_BUSY);
+
+  IntStatus = ~0;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RINTSTS, FALSE, sizeof (IntStatus), &IntStatus);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Cmd = CMD_INDEX (Packet->SdMmcCmdBlk->CommandIndex);
+  if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAc) ||
+      (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc)) {
+    switch (Packet->SdMmcCmdBlk->CommandIndex) {
+    case SD_SET_RELATIVE_ADDR:
+      Cmd |= BIT_CMD_SEND_INIT;
+      break;
+    case SD_STOP_TRANSMISSION:
+      Cmd |= BIT_CMD_STOP_ABORT_CMD;
+      break;
+    }
+    if (Packet->InTransferLength) {
+      Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
+    } else if (Packet->OutTransferLength) {
+      Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
+    }
+    Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+  } else {
+    switch (Packet->SdMmcCmdBlk->CommandIndex) {
+    case SD_GO_IDLE_STATE:
+      Cmd |= BIT_CMD_SEND_INIT;
+      break;
+    }
+  }
+  switch (Packet->SdMmcCmdBlk->ResponseType) {
+  case SdMmcResponseTypeR2:
+    Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_LONG_RESPONSE;
+    break;
+  case SdMmcResponseTypeR3:
+    Cmd |= BIT_CMD_RESPONSE_EXPECT;
+    break;
+  case SdMmcResponseTypeR1b:
+  case SdMmcResponseTypeR4:
+  case SdMmcResponseTypeR6:
+  case SdMmcResponseTypeR7:
+    Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+    break;
+  }
+  Cmd |= BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
+
+  if (Trb->UseFifo == TRUE) {
+    BytCnt = Packet->InTransferLength;
+    Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_BYTCNT, FALSE, sizeof (BytCnt), &BytCnt);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    BlkSize = Packet->InTransferLength;
+    Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_BLKSIZ, FALSE, sizeof (BlkSize), &BlkSize);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "DwMmcHcReset: set block size fails: %r\n", Status));
+      return Status;
+    }
+  }
+
+  Argument = Packet->SdMmcCmdBlk->CommandArgument;
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_CMDARG, FALSE, sizeof (Argument), &Argument);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ArmDataSynchronizationBarrier ();
+  ArmInstructionSynchronizationBarrier ();
+  Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_CMD, FALSE, sizeof (Cmd), &Cmd);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ArmDataSynchronizationBarrier ();
+  ArmInstructionSynchronizationBarrier ();
+
+  ErrMask = DW_MMC_INT_EBE | DW_MMC_INT_HLE | DW_MMC_INT_RTO |
+            DW_MMC_INT_RCRC | DW_MMC_INT_RE;
+  ErrMask |= DW_MMC_INT_DRT | DW_MMC_INT_SBE;
+  if (Packet->InTransferLength || Packet->OutTransferLength) {
+    ErrMask |= DW_MMC_INT_DCRC;
+  }
+  if (Trb->UseFifo == TRUE) {
+    Status = ReadFifo (Trb);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  } else {
+    Timeout = 10000;
+    do {
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RINTSTS, TRUE, sizeof (IntStatus), &IntStatus);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      if (IntStatus & ErrMask) {
+        return EFI_DEVICE_ERROR;
+      }
+      if (IntStatus & DW_MMC_INT_DTO) {  // Transfer Done
+        break;
+      }
+      if (--Timeout == 0) {
+        break;
+      }
+      MicroSecondDelay (10);
+    } while (!(IntStatus & DW_MMC_INT_CMD_DONE));
+    if (Packet->InTransferLength) {
+      do {
+        Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_IDSTS, TRUE, sizeof (Idsts), &Idsts);
+        if (EFI_ERROR (Status)) {
+          return Status;
+        }
+      } while ((Idsts & DW_MMC_IDSTS_RI) == 0);
+      Status = DwMmcHcStopDma (Private, Trb);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+    } else if (Packet->OutTransferLength) {
+      do {
+        Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_IDSTS, TRUE, sizeof (Idsts), &Idsts);
+        if (EFI_ERROR (Status)) {
+          return Status;
+        }
+      } while ((Idsts & DW_MMC_IDSTS_TI) == 0);
+      Status = DwMmcHcStopDma (Private, Trb);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+    } // Packet->InTransferLength
+  } // UseFifo
+  switch (Packet->SdMmcCmdBlk->ResponseType) {
+    case SdMmcResponseTypeR1:
+    case SdMmcResponseTypeR1b:
+    case SdMmcResponseTypeR3:
+    case SdMmcResponseTypeR4:
+    case SdMmcResponseTypeR5:
+    case SdMmcResponseTypeR6:
+    case SdMmcResponseTypeR7:
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP0, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp0), &Packet->SdMmcStatusBlk->Resp0);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      break;
+    case SdMmcResponseTypeR2:
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP0, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp0), &Packet->SdMmcStatusBlk->Resp0);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP1, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp1), &Packet->SdMmcStatusBlk->Resp1);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP2, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp2), &Packet->SdMmcStatusBlk->Resp2);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RESP3, TRUE, sizeof (Packet->SdMmcStatusBlk->Resp3), &Packet->SdMmcStatusBlk->Resp3);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+      break;
+  }
+
+  //
+  // The workaround on SD_SEND_CSD is used to be compatible with SDHC.
+  //
+  if (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_CSD) {
+    {
+      UINT32   Buf[4];
+      ZeroMem (Buf, sizeof (Buf));
+      CopyMem ((UINT8 *)Buf, (UINT8 *)&Packet->SdMmcStatusBlk->Resp0 + 1, sizeof (Buf) - 1);
+      CopyMem ((UINT8 *)&Packet->SdMmcStatusBlk->Resp0, (UINT8 *)Buf, sizeof (Buf) - 1);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Execute the specified TRB.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is sent to host controller successfully.
+  @retval Others            Some erros happen when sending this request to the host controller.
+
+**/
+EFI_STATUS
+DwMmcExecTrb (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status = EFI_SUCCESS;
+  UINT32                              Slot;
+
+  Slot = Trb->Slot;
+  if (Private->Slot[Slot].CardType == EmmcCardType) {
+    Status = DwEmmcExecTrb (Private, Trb);
+  } else if (Private->Slot[Slot].CardType == SdCardType) {
+    Status = DwSdExecTrb (Private, Trb);
+  } else {
+    ASSERT (0);
+  }
+  return Status;
+}
+
+/**
+  Check the TRB execution result.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is executed successfully.
+  @retval EFI_NOT_READY     The TRB is not completed for execution.
+  @retval Others            Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+DwMmcCheckTrbResult (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  UINT32                              Idsts;
+
+  Packet  = Trb->Packet;
+  if (Trb->UseFifo == TRUE) {
+    return EFI_SUCCESS;
+  }
+  if (Packet->InTransferLength) {
+    do {
+      Status = DwMmcHcRwMmio (Private->PciIo, Trb->Slot, DW_MMC_IDSTS, TRUE, sizeof (Idsts), &Idsts);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+    } while ((Idsts & BIT1) == 0);
+  } else if (Packet->OutTransferLength) {
+    do {
+      Status = DwMmcHcRwMmio (Private->PciIo, Trb->Slot, DW_MMC_IDSTS, TRUE, sizeof (Idsts), &Idsts);
+      if (EFI_ERROR (Status)) {
+        return Status;
+      }
+    } while ((Idsts & BIT0) == 0);
+  } else {
+    return EFI_SUCCESS;
+  }
+  Idsts = ~0;
+  Status = DwMmcHcRwMmio (Private->PciIo, Trb->Slot, DW_MMC_IDSTS, FALSE, sizeof (Idsts), &Idsts);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Wait for the TRB execution result.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the DW_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is executed successfully.
+  @retval Others            Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+DwMmcWaitTrbResult (
+  IN DW_MMC_HC_PRIVATE_DATA           *Private,
+  IN DW_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  UINT64                              Timeout;
+  BOOLEAN                             InfiniteWait;
+
+  Packet = Trb->Packet;
+  //
+  // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
+  //
+  Timeout = Packet->Timeout;
+  if (Timeout == 0) {
+    InfiniteWait = TRUE;
+  } else {
+    InfiniteWait = FALSE;
+  }
+
+  while (InfiniteWait || (Timeout > 0)) {
+    //
+    // Check Trb execution result by reading Normal Interrupt Status register.
+    //
+    Status = DwMmcCheckTrbResult (Private, Trb);
+    if (Status != EFI_NOT_READY) {
+      return Status;
+    }
+    //
+    // Stall for 1 microsecond.
+    //
+    gBS->Stall (1);
+
+    Timeout--;
+  }
+
+  return EFI_TIMEOUT;
+}
diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.h b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.h
new file mode 100644
index 0000000..228b20f
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.h
@@ -0,0 +1,686 @@
+/** @file
+
+  Provides some data structure definitions used by the SD/MMC host controller driver.
+
+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DW_MMC_HCI_H_
+#define _DW_MMC_HCI_H_
+
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/TimerLib.h>
+
+#include <Protocol/PlatformDwMmc.h>
+
+//
+// SD Host Controller SlotInfo Register Offset
+//
+#define DW_MMC_HC_SLOT_OFFSET         0x40
+
+#define DW_MMC_HC_MAX_SLOT            6
+
+//
+// SD Host Controller MMIO Register Offset
+//
+#define DW_MMC_CTRL                   0x000
+#define DW_MMC_PWREN                  0x004
+#define DW_MMC_CLKDIV                 0x008
+#define DW_MMC_CLKSRC                 0x00c
+#define DW_MMC_CLKENA                 0x010
+#define DW_MMC_TMOUT                  0x014
+#define DW_MMC_CTYPE                  0x018
+#define DW_MMC_BLKSIZ                 0x01c
+#define DW_MMC_BYTCNT                 0x020
+#define DW_MMC_INTMASK                0x024
+#define DW_MMC_CMDARG                 0x028
+#define DW_MMC_CMD                    0x02c
+#define DW_MMC_RESP0                  0x030
+#define DW_MMC_RESP1                  0x034
+#define DW_MMC_RESP2                  0x038
+#define DW_MMC_RESP3                  0x03c
+#define DW_MMC_RINTSTS                0x044
+#define DW_MMC_STATUS                 0x048
+#define DW_MMC_FIFOTH                 0x04c
+#define DW_MMC_GPIO                   0x058
+#define DW_MMC_DEBNCE                 0x064
+#define DW_MMC_USRID                  0x068
+#define DW_MMC_VERID                  0x06c
+#define DW_MMC_HCON                   0x070
+#define DW_MMC_UHSREG                 0x074
+#define DW_MMC_BMOD                   0x080
+#define DW_MMC_DBADDR                 0x088
+#define DW_MMC_IDSTS                  0x08c
+#define DW_MMC_IDINTEN                0x090
+#define DW_MMC_DSCADDR                0x094
+#define DW_MMC_BUFADDR                0x098
+#define DW_MMC_CARDTHRCTL             0x100
+#define DW_MMC_UHSREG_EXT             0x108
+#define DW_MMC_ENABLE_SHIFT           0x110
+#define DW_MMC_FIFO_START             0x200
+
+#define GET_IDSTS_DMAC_FSM(x)                   (((x) >> 13) & 0xf)
+#define IDSTS_FSM_DMA_IDLE                      0
+#define IDSTS_FSM_DMA_SUSPEND                   1
+#define IDSTS_FSM_DESC_RD                       2
+#define IDSTS_FSM_DESC_CHK                      3
+#define IDSTS_FSM_DMA_RD_REQ_WAIT               4
+#define IDSTS_FSM_DMA_WR_REQ_WAIT               5
+#define IDSTS_FSM_DMA_RD                        6
+#define IDSTS_FSM_DMA_WR                        7
+#define IDSTS_FSM_DESC_CLOSE                    8
+#define IDSTS_FSM_MASK                          0xf
+
+#define CMD_UPDATE_CLK                          0x80202000
+#define CMD_START_BIT                           (1 << 31)
+
+#define MMC_8BIT_MODE                           (1 << 16)
+#define MMC_4BIT_MODE                           (1 << 0)
+#define MMC_1BIT_MODE                           0
+
+#define DW_MMC_BLOCK_SIZE                       512
+
+#define CMD_INDEX_MASK                          0x3F
+#define BIT_CMD_RESPONSE_EXPECT                 (1 << 6)
+#define BIT_CMD_LONG_RESPONSE                   (1 << 7)
+#define BIT_CMD_CHECK_RESPONSE_CRC              (1 << 8)
+#define BIT_CMD_DATA_EXPECTED                   (1 << 9)
+#define BIT_CMD_READ                            (0 << 10)
+#define BIT_CMD_WRITE                           (1 << 10)
+#define BIT_CMD_BLOCK_TRANSFER                  (0 << 11)
+#define BIT_CMD_STREAM_TRANSFER                 (1 << 11)
+#define BIT_CMD_SEND_AUTO_STOP                  (1 << 12)
+#define BIT_CMD_WAIT_PRVDATA_COMPLETE           (1 << 13)
+#define BIT_CMD_STOP_ABORT_CMD                  (1 << 14)
+#define BIT_CMD_SEND_INIT                       (1 << 15)
+#define BIT_CMD_UPDATE_CLOCK_ONLY               (1 << 21)
+#define BIT_CMD_READ_CEATA_DEVICE               (1 << 22)
+#define BIT_CMD_CCS_EXPECTED                    (1 << 23)
+#define BIT_CMD_ENABLE_BOOT                     (1 << 24)
+#define BIT_CMD_EXPECT_BOOT_ACK                 (1 << 25)
+#define BIT_CMD_DISABLE_BOOT                    (1 << 26)
+#define BIT_CMD_MANDATORY_BOOT                  (0 << 27)
+#define BIT_CMD_ALTERNATE_BOOT                  (1 << 27)
+#define BIT_CMD_VOLT_SWITCH                     (1 << 28)
+#define BIT_CMD_USE_HOLD_REG                    (1 << 29)
+#define BIT_CMD_START                           (1 << 31)
+
+#define CMD_INDEX(x)                            ((x) & CMD_INDEX_MASK)
+
+#define DW_MMC_INT_EBE                          (1 << 15)       /* End-bit Err */
+#define DW_MMC_INT_SBE                          (1 << 13)       /* Start-bit  Err */
+#define DW_MMC_INT_HLE                          (1 << 12)       /* Hardware-lock Err */
+#define DW_MMC_INT_FRUN                         (1 << 11)       /* FIFO UN/OV RUN */
+#define DW_MMC_INT_DRT                          (1 << 9)        /* Data timeout */
+#define DW_MMC_INT_RTO                          (1 << 8)        /* Response timeout */
+#define DW_MMC_INT_DCRC                         (1 << 7)        /* Data CRC err */
+#define DW_MMC_INT_RCRC                         (1 << 6)        /* Response CRC err */
+#define DW_MMC_INT_RXDR                         (1 << 5)        /* Receive FIFO data request */
+#define DW_MMC_INT_TXDR                         (1 << 4)        /* Transmit FIFO data request */
+#define DW_MMC_INT_DTO                          (1 << 3)        /* Data trans over */
+#define DW_MMC_INT_CMD_DONE                     (1 << 2)        /* Command done */
+#define DW_MMC_INT_RE                           (1 << 1)        /* Response error */
+
+#define DW_MMC_IDMAC_DES0_DIC                   (1 << 1)
+#define DW_MMC_IDMAC_DES0_LD                    (1 << 2)
+#define DW_MMC_IDMAC_DES0_FS                    (1 << 3)
+#define DW_MMC_IDMAC_DES0_CH                    (1 << 4)
+#define DW_MMC_IDMAC_DES0_ER                    (1 << 5)
+#define DW_MMC_IDMAC_DES0_CES                   (1 << 30)
+#define DW_MMC_IDMAC_DES0_OWN                   (1 << 31)
+#define DW_MMC_IDMAC_DES1_BS1(x)                ((x) & 0x1fff)
+#define DW_MMC_IDMAC_DES2_BS2(x)                (((x) & 0x1fff) << 13)
+#define DW_MMC_IDMAC_SWRESET                    (1 << 0)
+#define DW_MMC_IDMAC_FB                         (1 << 1)
+#define DW_MMC_IDMAC_ENABLE                     (1 << 7)
+
+#define DW_MMC_CTRL_RESET                       (1 << 0)
+#define DW_MMC_CTRL_FIFO_RESET                  (1 << 1)
+#define DW_MMC_CTRL_DMA_RESET                   (1 << 2)
+#define DW_MMC_CTRL_INT_EN                      (1 << 4)
+#define DW_MMC_CTRL_DMA_EN                      (1 << 5)
+#define DW_MMC_CTRL_IDMAC_EN                    (1 << 25)
+#define DW_MMC_CTRL_RESET_ALL                   (DW_MMC_CTRL_RESET | DW_MMC_CTRL_FIFO_RESET | DW_MMC_CTRL_DMA_RESET)
+
+#define DW_MMC_STS_DATA_BUSY                    (1 << 9)
+#define DW_MMC_STS_FIFO_COUNT(x)                (((x) & 0x1fff) << 17)   /* Number of filled locations in FIFO */
+#define GET_STS_FIFO_COUNT(x)                   (((x) >> 17) & 0x1fff)
+
+#define DW_MMC_BMOD_SWR                         (1 << 0)         /* Software Reset */
+#define DW_MMC_BMOD_FB                          (1 << 1)         /* Fix Burst */
+#define DW_MMC_BMOD_DE                          (1 << 7)         /* IDMAC Enable */
+
+#define DW_MMC_IDSTS_TI                         (1 << 0)         /* Transmit Interrupt */
+#define DW_MMC_IDSTS_RI                         (1 << 1)         /* Receive Interrupt */
+
+#define DW_MMC_FIFO_TWMARK(x)                   ((x) & 0xfff)
+#define DW_MMC_FIFO_RWMARK(x)                   (((x) & 0x1ff) << 16)
+#define DW_MMC_DMA_BURST_SIZE(x)                (((x) & 0x7) << 28)
+
+#define DW_MMC_CARD_RD_THR(x)                   (((x) & 0xfff) << 16)
+#define DW_MMC_CARD_RD_THR_EN                   (1 << 0)
+
+#define UHS_DDR_MODE                            (1 << 16)
+
+#define GENCLK_DIV                              7
+
+#define DW_MMC_GPIO_CLK_DIV(x)                  (((x) & 0xf) << 8)
+#define DW_MMC_GPIO_USE_SAMPLE_DLY(x)           (((x) & 1) << 13)
+#define DW_MMC_GPIO_CLK_ENABLE                  BIT16
+
+#define UHSEXT_SAMPLE_PHASE(x)                  (((x) & 0x1f) << 16)
+#define UHSEXT_SAMPLE_DRVPHASE(x)               (((x) & 0x1f) << 21)
+#define UHSEXT_SAMPLE_DLY(x)                    (((x) & 0x1f) << 26)
+
+#define DWMMC_DMA_BUF_SIZE                      (512 * 8)
+#define DWMMC_FIFO_THRESHOLD                    16
+
+#define DWMMC_INIT_CLOCK_FREQ                   400              // KHz
+
+//
+// The transfer modes supported by SD Host Controller
+// Simplified Spec 3.0 Table 1-2
+//
+typedef enum {
+  SdMmcNoData,
+  SdMmcPioMode,
+  SdMmcSdmaMode,
+  SdMmcAdmaMode
+} DW_MMC_HC_TRANSFER_MODE;
+
+//
+// The maximum data length of each descriptor line
+//
+#define ADMA_MAX_DATA_PER_LINE     0x10000
+
+#if 0
+typedef struct {
+  UINT32 Valid:1;
+  UINT32 End:1;
+  UINT32 Int:1;
+  UINT32 Reserved:1;
+  UINT32 Act:2;
+  UINT32 Reserved1:10;
+  UINT32 Length:16;
+  UINT32 Address;
+} DW_MMC_HC_ADMA_DESC_LINE;
+#endif
+
+
+typedef struct {
+  UINT32   Des0;
+  UINT32   Des1;
+  UINT32   Des2;
+  UINT32   Des3;
+} DW_MMC_HC_DMA_DESC_LINE;
+
+#define SD_MMC_SDMA_BOUNDARY          512 * 1024
+#define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
+
+typedef struct {
+  UINT8    FirstBar:3;        // bit 0:2
+  UINT8    Reserved:1;        // bit 3
+  UINT8    SlotNum:3;         // bit 4:6
+  UINT8    Reserved1:1;       // bit 7
+} DW_MMC_HC_SLOT_INFO;
+
+#if 0
+typedef struct {
+  UINT32   TimeoutFreq:6;     // bit 0:5
+  UINT32   Reserved:1;        // bit 6
+  UINT32   TimeoutUnit:1;     // bit 7
+  UINT32   BaseClkFreq:8;     // bit 8:15
+  UINT32   MaxBlkLen:2;       // bit 16:17
+  UINT32   BusWidth8:1;       // bit 18
+  UINT32   Adma2:1;           // bit 19
+  UINT32   Reserved2:1;       // bit 20
+  UINT32   HighSpeed:1;       // bit 21
+  UINT32   Sdma:1;            // bit 22
+  UINT32   SuspRes:1;         // bit 23
+  UINT32   Voltage33:1;       // bit 24
+  UINT32   Voltage30:1;       // bit 25
+  UINT32   Voltage18:1;       // bit 26
+  UINT32   Reserved3:1;       // bit 27
+  UINT32   SysBus64:1;        // bit 28
+  UINT32   AsyncInt:1;        // bit 29
+  UINT32   SlotType:2;        // bit 30:31
+  UINT32   Sdr50:1;           // bit 32
+  UINT32   Sdr104:1;          // bit 33
+  UINT32   Ddr50:1;           // bit 34
+  UINT32   Reserved4:1;       // bit 35
+  UINT32   DriverTypeA:1;     // bit 36
+  UINT32   DriverTypeC:1;     // bit 37
+  UINT32   DriverTypeD:1;     // bit 38
+  UINT32   DriverType4:1;     // bit 39
+  UINT32   TimerCount:4;      // bit 40:43
+  UINT32   Reserved5:1;       // bit 44
+  UINT32   TuningSDR50:1;     // bit 45
+  UINT32   RetuningMod:2;     // bit 46:47
+  UINT32   ClkMultiplier:8;   // bit 48:55
+  UINT32   Reserved6:7;       // bit 56:62
+  UINT32   Hs400:1;           // bit 63
+} DW_MMC_HC_SLOT_CAP;
+#endif
+
+/**
+  Dump the content of SD/MMC host controller's Capability Register.
+
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[in]  Capability      The buffer to store the capability data.
+
+**/
+VOID
+DumpCapabilityReg (
+  IN UINT8                Slot,
+  IN DW_MMC_HC_SLOT_CAP   *Capability
+  );
+
+/**
+  Read SlotInfo register from SD/MMC host controller pci config space.
+
+  @param[in]  PciIo        The PCI IO protocol instance.
+  @param[out] FirstBar     The buffer to store the first BAR value.
+  @param[out] SlotNum      The buffer to store the supported slot number.
+
+  @retval EFI_SUCCESS      The operation succeeds.
+  @retval Others           The operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcGetSlotInfo (
+  IN     EFI_PCI_IO_PROTOCOL   *PciIo,
+     OUT UINT8                 *FirstBar,
+     OUT UINT8                 *SlotNum
+  );
+
+/**
+  Read/Write specified SD/MMC host controller mmio register.
+
+  @param[in]      PciIo        The PCI IO protocol instance.
+  @param[in]      BarIndex     The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in]      Offset       The offset within the selected BAR to start the
+                               memory operation.
+  @param[in]      Read         A boolean to indicate it's read or write operation.
+  @param[in]      Count        The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in, out] Data         For read operations, the destination buffer to store
+                               the results. For write operations, the source buffer
+                               to write data from. The caller is responsible for
+                               having ownership of the data buffer and ensuring its
+                               size not less than Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The read/write operation succeeds.
+  @retval Others                The read/write operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcRwMmio (
+  IN     EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN     UINT8                 BarIndex,
+  IN     UINT32                Offset,
+  IN     BOOLEAN               Read,
+  IN     UINT8                 Count,
+  IN OUT VOID                  *Data
+  );
+
+/**
+  Do OR operation with the value of the specified SD/MMC host controller mmio register.
+
+  @param[in] PciIo             The PCI IO protocol instance.
+  @param[in] BarIndex          The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in] Offset            The offset within the selected BAR to start the
+                               memory operation.
+  @param[in] Count             The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in] OrData            The pointer to the data used to do OR operation.
+                               The caller is responsible for having ownership of
+                               the data buffer and ensuring its size not less than
+                               Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The OR operation succeeds.
+  @retval Others                The OR operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcOrMmio (
+  IN  EFI_PCI_IO_PROTOCOL      *PciIo,
+  IN  UINT8                    BarIndex,
+  IN  UINT32                   Offset,
+  IN  UINT8                    Count,
+  IN  VOID                     *OrData
+  );
+
+/**
+  Do AND operation with the value of the specified SD/MMC host controller mmio register.
+
+  @param[in] PciIo             The PCI IO protocol instance.
+  @param[in] BarIndex          The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in] Offset            The offset within the selected BAR to start the
+                               memory operation.
+  @param[in] Count             The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in] AndData           The pointer to the data used to do AND operation.
+                               The caller is responsible for having ownership of
+                               the data buffer and ensuring its size not less than
+                               Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The AND operation succeeds.
+  @retval Others                The AND operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcAndMmio (
+  IN  EFI_PCI_IO_PROTOCOL      *PciIo,
+  IN  UINT8                    BarIndex,
+  IN  UINT32                   Offset,
+  IN  UINT8                    Count,
+  IN  VOID                     *AndData
+  );
+
+/**
+  Wait for the value of the specified MMIO register set to the test value.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  BarIndex      The BAR index of the standard PCI Configuration
+                            header to use as the base address for the memory
+                            operation to perform.
+  @param[in]  Offset        The offset within the selected BAR to start the
+                            memory operation.
+  @param[in]  Count         The width of the mmio register in bytes.
+                            Must be 1, 2, 4 or 8 bytes.
+  @param[in]  MaskValue     The mask value of memory.
+  @param[in]  TestValue     The test value of memory.
+  @param[in]  Timeout       The time out value for wait memory set, uses 1
+                            microsecond as a unit.
+
+  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
+                            range.
+  @retval EFI_SUCCESS       The MMIO register has expected value.
+  @retval Others            The MMIO operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+DwMmcHcWaitMmioSet (
+  IN  EFI_PCI_IO_PROTOCOL       *PciIo,
+  IN  UINT8                     BarIndex,
+  IN  UINT32                    Offset,
+  IN  UINT8                     Count,
+  IN  UINT64                    MaskValue,
+  IN  UINT64                    TestValue,
+  IN  UINT64                    Timeout
+  );
+
+/**
+  Software reset the specified SD/MMC host controller.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The software reset executes successfully.
+  @retval Others            The software reset fails.
+
+**/
+EFI_STATUS
+DwMmcHcReset (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  );
+
+/**
+  Set all interrupt status bits in Normal and Error Interrupt Status Enable
+  register.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation executes successfully.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+DwMmcHcEnableInterrupt (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  );
+
+/**
+  Get the capability data from the specified slot.
+
+  @param[in]  PciIo           The PCI IO protocol instance.
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[out] Capability      The buffer to store the capability data.
+
+  @retval EFI_SUCCESS         The operation executes successfully.
+  @retval Others              The operation fails.
+
+**/
+EFI_STATUS
+DwMmcHcGetCapability (
+  IN     EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN     EFI_HANDLE           Controller,
+  IN     UINT8                Slot,
+     OUT DW_MMC_HC_SLOT_CAP   *Capability
+  );
+
+/**
+  Get the maximum current capability data from the specified slot.
+
+  @param[in]  PciIo           The PCI IO protocol instance.
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[out] MaxCurrent      The buffer to store the maximum current capability data.
+
+  @retval EFI_SUCCESS         The operation executes successfully.
+  @retval Others              The operation fails.
+
+**/
+EFI_STATUS
+DwMmcHcGetMaxCurrent (
+  IN     EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN     UINT8                Slot,
+     OUT UINT64               *MaxCurrent
+  );
+
+/**
+  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
+  slot.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[out] MediaPresent  The pointer to the media present boolean value.
+
+  @retval EFI_SUCCESS       There is no media change happened.
+  @retval EFI_MEDIA_CHANGED There is media change happened.
+  @retval Others            The detection fails.
+
+**/
+EFI_STATUS
+DwMmcHcCardDetect (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+     OUT BOOLEAN            *MediaPresent
+  );
+
+/**
+  Stop SD/MMC card clock.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
+  @retval Others            Fail to stop SD/MMC clock.
+
+**/
+EFI_STATUS
+DwMmcHcStopClock (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  );
+
+/**
+  SD/MMC card clock supply.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The clock is supplied successfully.
+  @retval Others            The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+DwMmcHcClockSupply (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT64                 ClockFreq,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  );
+
+/**
+  SD/MMC bus power control.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] PowerCtrl      The value setting to the power control register.
+
+  @retval TRUE              There is a SD/MMC card attached.
+  @retval FALSE             There is no a SD/MMC card attached.
+
+**/
+EFI_STATUS
+DwMmcHcPowerControl (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT8                  PowerCtrl
+  );
+
+/**
+  Set the SD/MMC bus width.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
+
+  @retval EFI_SUCCESS       The bus width is set successfully.
+  @retval Others            The bus width isn't set successfully.
+
+**/
+EFI_STATUS
+DwMmcHcSetBusWidth (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN BOOLEAN                IsDdr,
+  IN UINT16                 BusWidth
+  );
+
+/**
+  Supply SD/MMC card with lowest clock frequency at initialization.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The clock is supplied successfully.
+  @retval Others            The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+DwMmcHcInitClockFreq (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  );
+
+/**
+  Supply SD/MMC card with maximum voltage at initialization.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The voltage is supplied successfully.
+  @retval Others            The voltage isn't supplied successfully.
+
+**/
+EFI_STATUS
+DwMmcHcInitPowerVoltage (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  );
+
+/**
+  Initialize the Timeout Control register with most conservative value at initialization.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The timeout control register is configured successfully.
+  @retval Others            The timeout control register isn't configured successfully.
+
+**/
+EFI_STATUS
+DwMmcHcInitTimeoutCtrl (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  );
+
+/**
+  Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
+  at initialization.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The host controller is initialized successfully.
+  @retval Others            The host controller isn't initialized successfully.
+
+**/
+EFI_STATUS
+DwMmcHcInitHost (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN DW_MMC_HC_SLOT_CAP     Capability
+  );
+
+#endif /* _DW_MMC_HCI_H_ */
diff --git a/Drivers/SdMmc/DwMmcHcDxe/EmmcDevice.c b/Drivers/SdMmc/DwMmcHcDxe/EmmcDevice.c
new file mode 100644
index 0000000..c84e7f7
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/EmmcDevice.c
@@ -0,0 +1,1024 @@
+/** @file
+  This file provides some helper functions which are specific for EMMC device.
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DwMmcHcDxe.h"
+
+#define EMMC_GET_STATE(x)                   (((x) >> 9) & 0xf)
+#define EMMC_STATE_IDLE                     0
+#define EMMC_STATE_READY                    1
+#define EMMC_STATE_IDENT                    2
+#define EMMC_STATE_STBY                     3
+#define EMMC_STATE_TRAN                     4
+#define EMMC_STATE_DATA                     5
+#define EMMC_STATE_RCV                      6
+#define EMMC_STATE_PRG                      7
+#define EMMC_STATE_DIS                      8
+#define EMMC_STATE_BTST                     9
+#define EMMC_STATE_SLP                      10
+
+#define EMMC_CMD1_CAPACITY_LESS_THAN_2GB    0x00FF8080 // Capacity <= 2GB, byte addressing used
+#define EMMC_CMD1_CAPACITY_GREATER_THAN_2GB 0x40FF8080 // Capacity > 2GB, 512-byte sector addressing used
+
+/**
+  Send command GO_IDLE_STATE (CMD0 with argument of 0x00000000) to the device to
+  make it go to Idle State.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The EMMC device is reset correctly.
+  @retval Others            The device reset fails.
+
+**/
+EFI_STATUS
+EmmcReset (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBc;
+  SdMmcCmdBlk.ResponseType = 0;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  gBS->Stall (1000);
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_OP_COND to the EMMC device to get the data of the OCR register.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in]      PassThru  A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]      Slot      The slot number of the SD card to send the command to.
+  @param[in, out] Argument  On input, the argument of SEND_OP_COND is to send to the device.
+                            On output, the argument is the value of OCR register.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcGetOcr (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN OUT UINT32                         *Argument
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;
+  SdMmcCmdBlk.CommandArgument = *Argument;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    //
+    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+    //
+    *Argument = SdMmcStatusBlk.Resp0;
+  }
+
+  return Status;
+}
+
+/**
+  Broadcast command ALL_SEND_CID to the bus to ask all the EMMC devices to send the
+  data of their CID registers.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcGetAllCid (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SET_RELATIVE_ADDR to the EMMC device to assign a Relative device
+  Address (RCA).
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSetRca (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_CSD to the EMMC device to get the data of the CSD register.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+  @param[out] Csd           The buffer to store the content of the CSD register.
+                            Note the caller should ignore the lowest byte of this
+                            buffer as the content of this byte is meaningless even
+                            if the operation succeeds.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcGetCsd (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT EMMC_CSD                       *Csd
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_CSD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    //
+    // Copy 128bit data for CSD structure.
+    //
+    CopyMem ((VOID *)Csd + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);
+  }
+
+  return Status;
+}
+
+/**
+  Send command SELECT_DESELECT_CARD to the EMMC device to select/deselect it.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSelect (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_EXT_CSD to the EMMC device to get the data of the EXT_CSD register.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[out] ExtCsd        The buffer to store the content of the EXT_CSD register.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcGetExtCsd (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+     OUT EMMC_EXT_CSD                   *ExtCsd
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = 0x00000000;
+
+  Packet.InDataBuffer     = ExtCsd;
+  Packet.InTransferLength = sizeof (EMMC_EXT_CSD);
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  return Status;
+}
+
+/**
+  Send command SWITCH to the EMMC device to switch the mode of operation of the
+  selected Device or modifies the EXT_CSD registers.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Access        The access mode of SWTICH command.
+  @param[in]  Index         The offset of the field to be access.
+  @param[in]  Value         The value to be set to the specified field of EXT_CSD register.
+  @param[in]  CmdSet        The value of CmdSet field of EXT_CSD register.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitch (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT8                              Access,
+  IN UINT8                              Index,
+  IN UINT8                              Value,
+  IN UINT8                              CmdSet
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SWITCH;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
+  SdMmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_STATUS to the addressed EMMC device to get its status register.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of addressed device.
+  @param[out] DevStatus     The returned device status.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSendStatus (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT UINT32                         *DevStatus
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    *DevStatus = SdMmcStatusBlk.Resp0;
+  }
+
+  return Status;
+}
+
+/**
+  Send command SEND_TUNING_BLOCK to the EMMC device for HS200 optimal sampling point
+  detection.
+
+  It may be sent up to 40 times until the host finishes the tuning procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] BusWidth       The bus width to work.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSendTuningBlk (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT8                                 TuningBlock[128];
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  Packet.InDataBuffer = TuningBlock;
+  if (BusWidth == 8) {
+    Packet.InTransferLength = sizeof (TuningBlock);
+  } else {
+    Packet.InTransferLength = 64;
+  }
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Tunning the clock to get HS200 optimal sampling point.
+
+  Command SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the
+  tuning procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] BusWidth       The bus width to work.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcTuningClkForHs200 (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT8                              BusWidth
+  )
+{
+#if 0
+  EFI_STATUS          Status;
+  UINT8               HostCtrl2;
+  UINT8               Retry;
+
+  //
+  // Notify the host that the sampling clock tuning procedure starts.
+  //
+  HostCtrl2 = BIT6;
+  Status = DwMmcHcOrMmio (PciIo, Slot, DW_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
+  //
+  Retry = 0;
+  do {
+    Status = EmmcSendTuningBlk (PassThru, Slot, BusWidth);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "EmmcTuningClkForHs200: Send tuning block fails with %r\n", Status));
+      return Status;
+    }
+
+    Status = DwMmcHcRwMmio (PciIo, Slot, DW_MMC_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
+      break;
+    }
+
+    if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
+      return EFI_SUCCESS;
+    }
+  } while (++Retry < 40);
+
+  DEBUG ((DEBUG_ERROR, "EmmcTuningClkForHs200: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));
+  //
+  // Abort the tuning procedure and reset the tuning circuit.
+  //
+  HostCtrl2 = (UINT8)~(BIT6 | BIT7);
+  Status = DwMmcHcAndMmio (PciIo, Slot, DW_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return EFI_DEVICE_ERROR;
+#else
+  return EFI_SUCCESS;
+#endif
+}
+
+/**
+  Switch the bus width to specified width.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.9 and SD Host Controller
+  Simplified Spec 3.0 Figure 3-7 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] IsDdr          If TRUE, use dual data rate data simpling method. Otherwise
+                            use single data rate data simpling method.
+  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchBusWidth (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN BOOLEAN                            IsDdr,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_STATUS          Status;
+  UINT8               Access;
+  UINT8               Index;
+  UINT8               Value;
+  UINT8               CmdSet;
+  UINT32              DevStatus;
+
+  //
+  // Write Byte, the Value field is written into the byte pointed by Index.
+  //
+  Access = 0x03;
+  Index  = OFFSET_OF (EMMC_EXT_CSD, BusWidth);
+  if (BusWidth == 1) {
+    Value = 0;
+  } else {
+    if (BusWidth == 4) {
+      Value = 1;
+    } else if (BusWidth == 8) {
+      Value = 2;
+    } else {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    if (IsDdr) {
+      Value += 4;
+    }
+  }
+
+  CmdSet = 0;
+  Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Switch to bus width %d fails with %r\n", BusWidth, Status));
+    return Status;
+  }
+
+  do {
+    Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n", Status));
+      return Status;
+    }
+    //
+    // Check the switch operation is really successful or not.
+    //
+  } while ((DevStatus & 0xf) == EMMC_STATE_PRG);
+
+  Status = DwMmcHcSetBusWidth (PciIo, Slot, IsDdr, BusWidth);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return Status;
+}
+
+/**
+  Switch the clock frequency to the specified value.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Controller
+  Simplified Spec 3.0 Figure 3-3 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] HsTiming       The value to be written to HS_TIMING field of EXT_CSD register.
+  @param[in] ClockFreq      The max clock frequency to be set, the unit is MHz.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchClockFreq (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT8                              HsTiming,
+  IN UINT32                             ClockFreq
+  )
+{
+  EFI_STATUS                Status;
+  UINT8                     Access;
+  UINT8                     Index;
+  UINT8                     Value;
+  UINT8                     CmdSet;
+  UINT32                    DevStatus;
+  DW_MMC_HC_PRIVATE_DATA    *Private;
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  //
+  // Write Byte, the Value field is written into the byte pointed by Index.
+  //
+  Access = 0x03;
+  Index  = OFFSET_OF (EMMC_EXT_CSD, HsTiming);
+  Value  = HsTiming;
+  CmdSet = 0;
+
+  Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: Switch to hstiming %d fails with %r\n", HsTiming, Status));
+    return Status;
+  }
+
+  Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: Send status fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Check the switch operation is really successful or not.
+  //
+  if ((DevStatus & BIT7) != 0) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));
+    return EFI_DEVICE_ERROR;
+  }
+  //
+  // Convert the clock freq unit from MHz to KHz.
+  //
+  Status = DwMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->Capability[Slot]);
+
+  return Status;
+}
+
+/**
+  Switch to the High Speed timing according to request.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] ClockFreq      The max clock frequency to be set.
+  @param[in] IsDdr          If TRUE, use dual data rate data simpling method. Otherwise
+                            use single data rate data simpling method.
+  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchToHighSpeed (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT32                             ClockFreq,
+  IN BOOLEAN                            IsDdr,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_STATUS          Status;
+  UINT8               HsTiming;
+
+  HsTiming = 1;
+  Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Switch to the HS200 timing according to request.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] ClockFreq      The max clock frequency to be set.
+  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchToHS200 (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT32                             ClockFreq,
+  IN UINT8                              BusWidth
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Switch the high speed timing according to request.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSetBusMode (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca
+  )
+{
+  EFI_STATUS                    Status;
+  EMMC_CSD                      Csd;
+  EMMC_EXT_CSD                  ExtCsd;
+  UINT8                         HsTiming;
+  BOOLEAN                       IsDdr;
+  UINT32                        DevStatus;
+  UINT32                        ClockFreq;
+  UINT8                         BusWidth;
+  DW_MMC_HC_PRIVATE_DATA        *Private;
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  ASSERT (Private->Capability[Slot].BaseClkFreq != 0);
+
+  Status = EmmcGetCsd (PassThru, Slot, Rca, &Csd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetCsd fails with %r\n", Status));
+    return Status;
+  }
+
+  Status = EmmcSelect (PassThru, Slot, Rca);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: Select fails with %r\n", Status));
+    return Status;
+  }
+
+  do {
+    Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: Get Status fails with %r\n", Status));
+      return Status;
+    }
+  } while (EMMC_GET_STATE (DevStatus) != EMMC_STATE_TRAN);
+
+  BusWidth = 1;
+  Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, FALSE, BusWidth);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  BusWidth = Private->Capability[Slot].BusWidth;
+  //
+  // Get Deivce_Type from EXT_CSD register.
+  //
+  Status = EmmcGetExtCsd (PassThru, Slot, &ExtCsd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetExtCsd fails with %r\n", Status));
+    return Status;
+  }
+
+  //
+  // Calculate supported bus speed/bus width/clock frequency.
+  //
+  HsTiming  = 0;
+  IsDdr     = FALSE;
+  ClockFreq = 0;
+  if (((ExtCsd.DeviceType & (BIT4 | BIT5))  != 0) && (Private->Capability[Slot].Sdr104 != 0)) {
+    HsTiming  = 2;
+    IsDdr     = FALSE;
+    ClockFreq = 200;
+  } else if (((ExtCsd.DeviceType & (BIT2 | BIT3))  != 0) && (Private->Capability[Slot].Ddr50 != 0)) {
+    HsTiming  = 1;
+    IsDdr     = TRUE;
+    ClockFreq = 52;
+  } else if (((ExtCsd.DeviceType & BIT1)  != 0) && (Private->Capability[Slot].HighSpeed != 0)) {
+    HsTiming  = 1;
+    IsDdr     = FALSE;
+    ClockFreq = 52;
+  } else if (((ExtCsd.DeviceType & BIT0)  != 0) && (Private->Capability[Slot].HighSpeed != 0)) {
+    HsTiming  = 1;
+    IsDdr     = FALSE;
+    ClockFreq = 26;
+  }
+
+  if ((ClockFreq == 0) || (HsTiming == 0)) {
+    //
+    // Continue using default setting.
+    //
+    return EFI_SUCCESS;
+  }
+
+  DEBUG ((DEBUG_INFO, "EmmcSetBusMode: HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE"));
+
+  if (HsTiming == 2) {
+    //
+    // Execute HS200 timing switch procedure
+    //
+    Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, BusWidth);
+  } else {
+    //
+    // Execute High Speed timing switch procedure
+    //
+    Status = EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, ClockFreq, IsDdr, BusWidth);
+  }
+
+  DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Switch to %a %r\n", (HsTiming == 3) ? "HS400" : ((HsTiming == 2) ? "HS200" : "HighSpeed"), Status));
+
+  return Status;
+}
+
+/**
+  Execute EMMC device identification procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       There is a EMMC card.
+  @retval Others            There is not a EMMC card.
+
+**/
+EFI_STATUS
+EmmcIdentification (
+  IN DW_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  )
+{
+  EFI_STATUS                     Status;
+  EFI_PCI_IO_PROTOCOL            *PciIo;
+  EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru;
+  UINT32                         Ocr;
+  UINT16                         Rca;
+  UINT32                         DevStatus;
+  UINT32                         Timeout;
+
+  PciIo    = Private->PciIo;
+  PassThru = &Private->PassThru;
+
+  Status = EmmcReset (PassThru, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "EmmcIdentification: Executing Cmd0 fails with %r\n", Status));
+    return Status;
+  }
+
+  Timeout = 30;
+  do {
+    Ocr = EMMC_CMD1_CAPACITY_GREATER_THAN_2GB;
+    Status = EmmcGetOcr (PassThru, Slot, &Ocr);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_INFO, "EmmcIdentification: Executing Cmd1 fails with %r\n", Status));
+      return Status;
+    }
+    if (--Timeout <= 0) {
+      return EFI_DEVICE_ERROR;
+    }
+    MicroSecondDelay (100);
+  } while ((Ocr & BIT31) == 0);
+
+  Status = EmmcGetAllCid (PassThru, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "EmmcIdentification: Executing Cmd2 fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Slot starts from 0 and valid RCA starts from 1.
+  // Here we takes a simple formula to calculate the RCA.
+  // Don't support multiple devices on the slot, that is
+  // shared bus slot feature.
+  //
+  Rca    = Slot + 1;
+  Status = EmmcSetRca (PassThru, Slot, Rca);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "EmmcIdentification: Executing Cmd3 fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Enter Data Tranfer Mode.
+  //
+  DEBUG ((DEBUG_INFO, "EmmcIdentification: Found a EMMC device at slot [%d], RCA [%d]\n", Slot, Rca));
+  Private->Slot[Slot].CardType = EmmcCardType;
+
+  Status = EmmcSetBusMode (PciIo, PassThru, Slot, Rca);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Exit DATA Mode.
+  //
+  do {
+    Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_INFO, "EmmcSwitchBusWidth: Send status fails with %r\n", Status));
+      return Status;
+    }
+  } while ((DevStatus & 0xf) == EMMC_STATE_DATA);
+
+  return Status;
+}
diff --git a/Drivers/SdMmc/DwMmcHcDxe/SdDevice.c b/Drivers/SdMmc/DwMmcHcDxe/SdDevice.c
new file mode 100644
index 0000000..fdbe383
--- /dev/null
+++ b/Drivers/SdMmc/DwMmcHcDxe/SdDevice.c
@@ -0,0 +1,1055 @@
+/** @file
+  This file provides some helper functions which are specific for SD card device.
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DwMmcHcDxe.h"
+
+/**
+  Send command GO_IDLE_STATE to the device to make it go to Idle State.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The SD device is reset correctly.
+  @retval Others            The device reset fails.
+
+**/
+EFI_STATUS
+SdCardReset (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_GO_IDLE_STATE;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBc;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_IF_COND to the device to inquiry the SD Memory Card interface
+  condition.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] SupplyVoltage  The supplied voltage by the host.
+  @param[in] CheckPattern   The check pattern to be sent to the device.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardVoltageCheck (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT8                              SupplyVoltage,
+  IN UINT8                              CheckPattern
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_IF_COND;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR7;
+  SdMmcCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  if (!EFI_ERROR (Status)) {
+    if (SdMmcStatusBlk.Resp0 != SdMmcCmdBlk.CommandArgument) {
+      return EFI_DEVICE_ERROR;
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Send command SDIO_SEND_OP_COND to the device to see whether it is SDIO device.
+
+  Refer to SDIO Simplified Spec 3 Section 3.2 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] VoltageWindow  The supply voltage window.
+  @param[in] S18R           The boolean to show if it should switch to 1.8v.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdioSendOpCond (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT32                             VoltageWindow,
+  IN BOOLEAN                            S18R
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT32                                Switch;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SDIO_SEND_OP_COND;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR4;
+
+  Switch = S18R ? BIT24 : 0;
+
+  SdMmcCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SD_SEND_OP_COND to the device to see whether it is SDIO device.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot           The slot number of the SD card to send the command to.
+  @param[in]  Rca            The relative device address of addressed device.
+  @param[in]  VoltageWindow  The supply voltage window.
+  @param[in]  S18R           The boolean to show if it should switch to 1.8v.
+  @param[in]  Xpc            The boolean to show if it should provide 0.36w power control.
+  @param[in]  Hcs            The boolean to show if it support host capacity info.
+  @param[out] Ocr            The buffer to store returned OCR register value.
+
+  @retval EFI_SUCCESS        The operation is done correctly.
+  @retval Others             The operation fails.
+
+**/
+EFI_STATUS
+SdCardSendOpCond (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+  IN     UINT32                         VoltageWindow,
+  IN     BOOLEAN                        S18R,
+  IN     BOOLEAN                        Xpc,
+  IN     BOOLEAN                        Hcs,
+     OUT UINT32                         *Ocr
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT32                                Switch;
+  UINT32                                MaxPower;
+  UINT32                                HostCapacity;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_OP_COND;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;
+
+  Switch       = S18R ? BIT24 : 0;
+  MaxPower     = Xpc ? BIT28 : 0;
+  HostCapacity = Hcs ? BIT30 : 0;
+
+  SdMmcCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch | MaxPower | HostCapacity;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    //
+    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+    //
+    *Ocr = SdMmcStatusBlk.Resp0;
+  }
+
+  return Status;
+}
+
+/**
+  Broadcast command ALL_SEND_CID to the bus to ask all the SD devices to send the
+  data of their CID registers.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardAllSendCid (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_ALL_SEND_CID;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SET_RELATIVE_ADDR to the SD device to assign a Relative device
+  Address (RCA).
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[out] Rca           The relative device address to assign.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSetRca (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+     OUT UINT16                         *Rca
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SET_RELATIVE_ADDR;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR6;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    *Rca = (UINT16)(SdMmcStatusBlk.Resp0 >> 16);
+  }
+
+  return Status;
+}
+
+/**
+  Send command SEND_CSD to the SD device to get the data of the CSD register.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+  @param[out] Csd           The buffer to store the content of the CSD register.
+                            Note the caller should ignore the lowest byte of this
+                            buffer as the content of this byte is meaningless even
+                            if the operation succeeds.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardGetCsd (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT SD_CSD                         *Csd
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_CSD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    //
+    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+    //
+    CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (SD_CSD) - 1);
+  }
+
+  return Status;
+}
+
+/**
+  Send command SEND_CSD to the SD device to get the data of the CSD register.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+  @param[out] Scr           The buffer to store the content of the SCR register.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardGetScr (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT SD_SCR                         *Scr
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_SCR;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+
+  Packet.InDataBuffer     = Scr;
+  Packet.InTransferLength = sizeof (SD_SCR);
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SELECT_DESELECT_CARD to the SD device to select/deselect it.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSelect (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SELECT_DESELECT_CARD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  if (Rca != 0) {
+    SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
+  }
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command VOLTAGE_SWITCH to the SD device to switch the voltage of the device.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardVoltageSwitch (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SET_BUS_WIDTH to the SD device to set the bus width.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address of addressed device.
+  @param[in] BusWidth       The bus width to be set, it could be 1 or 4.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSetBusWidth (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT8                                 Value;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  SdMmcCmdBlk.CommandIndex = SD_SET_BUS_WIDTH;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+
+  if (BusWidth == 1) {
+    Value = 0;
+  } else if (BusWidth == 4) {
+    Value = 2;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  SdMmcCmdBlk.CommandArgument = Value & 0x3;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  return Status;
+}
+
+/**
+  Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  AccessMode    The value for access mode group.
+  @param[in]  CommandSystem The value for command set group.
+  @param[in]  DriveStrength The value for drive length group.
+  @param[in]  PowerLimit    The value for power limit group.
+  @param[in]  Mode          Switch or check function.
+  @param[out] SwitchResp    The return switch function status.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSwitch (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT8                          AccessMode,
+  IN     UINT8                          CommandSystem,
+  IN     UINT8                          DriveStrength,
+  IN     UINT8                          PowerLimit,
+  IN     BOOLEAN                        Mode,
+     OUT UINT8                          *SwitchResp
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT32                                ModeValue;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SWITCH_FUNC;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+
+  ModeValue = Mode ? BIT31 : 0;
+  SdMmcCmdBlk.CommandArgument = (AccessMode & 0xF) | ((PowerLimit & 0xF) << 4) | \
+                                ((DriveStrength & 0xF) << 8) | ((DriveStrength & 0xF) << 12) | \
+                                ModeValue;
+
+  Packet.InDataBuffer     = SwitchResp;
+  Packet.InTransferLength = 64;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_STATUS to the addressed SD device to get its status register.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of addressed device.
+  @param[out] DevStatus     The returned device status.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSendStatus (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT UINT32                         *DevStatus
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_STATUS;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    *DevStatus = SdMmcStatusBlk.Resp0;
+  }
+
+  return Status;
+}
+
+/**
+  Send command SEND_TUNING_BLOCK to the SD device for HS200 optimal sampling point
+  detection.
+
+  It may be sent up to 40 times until the host finishes the tuning procedure.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSendTuningBlk (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT8                                 TuningBlock[64];
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = DW_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  Packet.InDataBuffer     = TuningBlock;
+  Packet.InTransferLength = sizeof (TuningBlock);
+
+  Status = DwMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Switch the bus width to specified width.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
+  SD Host Controller Simplified Spec 3.0 section Figure 3-7 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSwitchBusWidth (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN BOOLEAN                            IsDdr,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_STATUS          Status;
+  UINT32              DevStatus;
+
+  Status = SdCardSetBusWidth (PassThru, Slot, Rca, BusWidth);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardSwitchBusWidth: Switch to bus width %d fails with %r\n", BusWidth, Status));
+    return Status;
+  }
+
+  Status = SdCardSendStatus (PassThru, Slot, Rca, &DevStatus);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardSwitchBusWidth: Send status fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Check the switch operation is really successful or not.
+  //
+  if ((DevStatus >> 16) != 0) {
+    DEBUG ((DEBUG_ERROR, "SdCardSwitchBusWidth: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = DwMmcHcSetBusWidth (PciIo, Slot, IsDdr, BusWidth);
+
+  return Status;
+}
+
+/**
+  Switch the high speed timing according to request.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
+  SD Host Controller Simplified Spec 3.0 section Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] S18A           The boolean to show if it's a UHS-I SD card.
+  @param[in] BusWidths      The bus width of the SD card.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSetBusMode (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN BOOLEAN                            S18A,
+  IN UINT32                             BusWidths
+  )
+{
+  EFI_STATUS                   Status;
+  DW_MMC_HC_SLOT_CAP           *Capability;
+  UINT32                       ClockFreq;
+  UINT8                        AccessMode;
+  UINT8                        SwitchResp[64];
+  DW_MMC_HC_PRIVATE_DATA       *Private;
+  BOOLEAN                      IsDdr;
+
+  Private = DW_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+
+  Capability = &Private->Capability[Slot];
+
+  if ((Capability->BusWidth == 1) || (Capability->BusWidth == 4)) {
+    BusWidths &= Capability[Slot].BusWidth;
+  } else {
+    DEBUG ((DEBUG_ERROR, "SdCardSetBusMode: BusWidths (%d) in capability are wrong\n", Capability->BusWidth));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (BusWidths == 0) {
+    DEBUG ((DEBUG_ERROR, "SdCardSetBusMode: Get wrong BusWidths:%d\n", BusWidths));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Private->Capability[Slot].Ddr50) {
+    IsDdr = TRUE;
+  } else {
+    IsDdr = FALSE;
+  }
+
+  Status = SdCardSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidths);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardSetBusMode: Executing SdCardSwitchBusWidth fails with %r\n", Status));
+    return Status;
+  }
+
+  //
+  // Get the supported bus speed from SWITCH cmd return data group #1.
+  //
+  Status = SdCardSwitch (PassThru, Slot, 0xF, 0xF, 0xF, 0xF, FALSE, SwitchResp);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Calculate supported bus speed/bus width/clock frequency by host and device capability.
+  //
+  ClockFreq = 0;
+  if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
+    ClockFreq = 208;
+    AccessMode = 3;
+  } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
+    ClockFreq = 100;
+    AccessMode = 2;
+  } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
+    ClockFreq = 50;
+    AccessMode = 4;
+  } else if ((SwitchResp[13] & BIT1) != 0) {
+    ClockFreq = 50;
+    AccessMode = 1;
+  } else {
+    ClockFreq = 25;
+    AccessMode = 0;
+  }
+
+  Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if ((SwitchResp[16] & 0xF) != AccessMode) {
+    DEBUG ((DEBUG_ERROR, "SdCardSetBusMode: Switch to AccessMode %d ClockFreq %d fails! The Switch response is 0x%1x\n", AccessMode, ClockFreq, SwitchResp[16] & 0xF));
+    return EFI_DEVICE_ERROR;
+  }
+
+  DEBUG ((DEBUG_INFO, "SdCardSetBusMode: Switch to AccessMode %d ClockFreq %d \n", AccessMode, ClockFreq));
+
+  Status = DwMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return Status;
+}
+
+/**
+  Execute SD device identification procedure.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 3.6 for details.
+
+  @param[in] Private        A pointer to the DW_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       There is a SD card.
+  @retval Others            There is not a SD card.
+
+**/
+EFI_STATUS
+SdCardIdentification (
+  IN DW_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  )
+{
+  EFI_STATUS                     Status;
+  EFI_PCI_IO_PROTOCOL            *PciIo;
+  EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru;
+  UINT32                         Ocr;
+  UINT16                         Rca;
+  BOOLEAN                        Xpc;
+  BOOLEAN                        S18r;
+  UINT64                         MaxCurrent;
+  SD_SCR                         Scr;
+  SD_CSD                         Csd;
+
+  PciIo    = Private->PciIo;
+  PassThru = &Private->PassThru;
+  //
+  // 1. Send Cmd0 to the device
+  //
+  Status = SdCardReset (PassThru, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing Cmd0 fails with %r\n", Status));
+    return Status;
+  }
+  MicroSecondDelay (10000);
+  //
+  // 2. Send Cmd8 to the device
+  //
+  Status = SdCardVoltageCheck (PassThru, Slot, 0x1, 0xFF);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing Cmd8 fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // 3. Send SDIO Cmd5 to the device to the SDIO device OCR register.
+  //
+  Status = SdioSendOpCond (PassThru, Slot, 0, FALSE);
+  if (!EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Found SDIO device, ignore it as we don't support\n"));
+    return EFI_DEVICE_ERROR;
+  }
+  MicroSecondDelay (10000);
+  //
+  // 4. Send Acmd41 with voltage window 0 to the device
+  //
+  Status = SdCardSendOpCond (PassThru, Slot, 0, 0, FALSE, FALSE, FALSE, &Ocr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing SdCardSendOpCond fails with %r\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (Private->Capability[Slot].Voltage33 != 0) {
+    //
+    // Support 3.3V
+    //
+    MaxCurrent = ((UINT32)Private->MaxCurrent[Slot] & 0xFF) * 4;
+    S18r = FALSE;
+  } else if (Private->Capability[Slot].Voltage30 != 0) {
+    //
+    // Support 3.0V
+    //
+    MaxCurrent = (((UINT32)Private->MaxCurrent[Slot] >> 8) & 0xFF) * 4;
+    S18r = FALSE;
+  } else if (Private->Capability[Slot].Voltage18 != 0) {
+    //
+    // Support 1.8V
+    //
+    MaxCurrent = (((UINT32)Private->MaxCurrent[Slot] >> 16) & 0xFF) * 4;
+    S18r = TRUE;
+  } else {
+    ASSERT (FALSE);
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (MaxCurrent >= 150) {
+    Xpc = TRUE;
+  } else {
+    Xpc = FALSE;
+  }
+
+  //
+  // 5. Repeatly send Acmd41 with supply voltage window to the device.
+  //    Note here we only support the cards complied with SD physical
+  //    layer simplified spec version 2.0 and version 3.0 and above.
+  //
+  do {
+    Status = SdCardSendOpCond (PassThru, Slot, 0, Ocr, S18r, Xpc, TRUE, &Ocr);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "SdCardIdentification: SdCardSendOpCond fails with %r Ocr %x, S18r %x, Xpc %x\n", Status, Ocr, S18r, Xpc));
+      return EFI_DEVICE_ERROR;
+    }
+  } while ((Ocr & BIT31) == 0);
+
+  Status = SdCardAllSendCid (PassThru, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardAllSendCid fails with %r\n", Status));
+    return Status;
+  }
+
+  Status = SdCardSetRca (PassThru, Slot, &Rca);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardSetRca fails with %r\n", Status));
+    return Status;
+  }
+
+  Status = SdCardGetCsd (PassThru, Slot, Rca, &Csd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardGetCsd fails with %r\n", Status));
+    return Status;
+  }
+
+  Status = SdCardSelect (PassThru, Slot, Rca);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardIdentification: Selecting card fails with %r\n", Status));
+    return Status;
+  }
+
+  Status = SdCardGetScr (PassThru, Slot, Rca, &Scr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardGetScr fails with %r\n", Status));
+    return Status;
+  }
+
+  //
+  // Enter Data Tranfer Mode.
+  //
+  DEBUG ((DEBUG_INFO, "SdCardIdentification: Found a SD device at slot [%d]\n", Slot));
+  Private->Slot[Slot].CardType = SdCardType;
+
+  Status = SdCardSetBusMode (PciIo, PassThru, Slot, Rca, S18r, Scr.SdBusWidths);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Private->Slot[Slot].Initialized = TRUE;
+
+  return Status;
+}
diff --git a/Drivers/SdMmc/XenonDxe/ComponentName.c b/Drivers/SdMmc/XenonDxe/ComponentName.c
new file mode 100644
index 0000000..3329929
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/ComponentName.c
@@ -0,0 +1,211 @@
+/** @file
+  UEFI Component Name(2) protocol implementation for SD/MMC host controller driver.
+
+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SdMmcPciHcDxe.h"
+
+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSdMmcPciHcComponentName = {
+  SdMmcPciHcComponentNameGetDriverName,
+  SdMmcPciHcComponentNameGetControllerName,
+  "eng"
+};
+
+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2 = {
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)     SdMmcPciHcComponentNameGetDriverName,
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SdMmcPciHcComponentNameGetControllerName,
+  "en"
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcDriverNameTable[] = {
+  { "eng;en", L"Edkii Sd/Mmc Host Controller Driver" },
+  { NULL , NULL }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSdMmcPciHcControllerNameTable[] = {
+  { "eng;en", L"Edkii Sd/Mmc Host Controller" },
+  { NULL , NULL }
+};
+
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL     *This,
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **DriverName
+  )
+{
+  return LookupUnicodeString2 (
+           Language,
+           This->SupportedLanguages,
+           mSdMmcPciHcDriverNameTable,
+           DriverName,
+           (BOOLEAN)(This == &gSdMmcPciHcComponentName)
+           );
+}
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL     *This,
+  IN  EFI_HANDLE                      ControllerHandle,
+  IN  EFI_HANDLE                      ChildHandle, OPTIONAL
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **ControllerName
+  )
+{
+  EFI_STATUS         Status;
+
+  if (Language == NULL || ControllerName == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // This is a device driver, so ChildHandle must be NULL.
+  //
+  if (ChildHandle != NULL) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Make sure this driver is currently managing ControllerHandle
+  //
+  Status = EfiTestManagedDevice (
+             ControllerHandle,
+             gSdMmcPciHcDriverBinding.DriverBindingHandle,
+             &gEfiPciIoProtocolGuid
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return LookupUnicodeString2 (
+           Language,
+           This->SupportedLanguages,
+           mSdMmcPciHcControllerNameTable,
+           ControllerName,
+           (BOOLEAN)(This == &gSdMmcPciHcComponentName)
+           );
+}
diff --git a/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Drivers/SdMmc/XenonDxe/EmmcDevice.c
new file mode 100755
index 0000000..3f73194
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/EmmcDevice.c
@@ -0,0 +1,1162 @@
+/** @file
+  This file provides some helper functions which are specific for EMMC device.
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SdMmcPciHcDxe.h"
+
+/**
+  Send command GO_IDLE_STATE (CMD0 with argument of 0x00000000) to the device to
+  make it go to Idle State.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The EMMC device is reset correctly.
+  @retval Others            The device reset fails.
+
+**/
+EFI_STATUS
+EmmcReset (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBc;
+  SdMmcCmdBlk.ResponseType = 0;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  gBS->Stall (1000);
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_OP_COND to the EMMC device to get the data of the OCR register.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in]      PassThru  A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]      Slot      The slot number of the SD card to send the command to.
+  @param[in, out] Argument  On input, the argument of SEND_OP_COND is to send to the device.
+                            On output, the argument is the value of OCR register.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcGetOcr (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN OUT UINT32                         *Argument
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;
+  SdMmcCmdBlk.CommandArgument = *Argument;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    //
+    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+    //
+    *Argument = SdMmcStatusBlk.Resp0;
+  }
+
+  return Status;
+}
+
+/**
+  Broadcast command ALL_SEND_CID to the bus to ask all the EMMC devices to send the
+  data of their CID registers.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcGetAllCid (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SET_RELATIVE_ADDR to the EMMC device to assign a Relative device
+  Address (RCA).
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSetRca (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_CSD to the EMMC device to get the data of the CSD register.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+  @param[out] Csd           The buffer to store the content of the CSD register.
+                            Note the caller should ignore the lowest byte of this
+                            buffer as the content of this byte is meaningless even
+                            if the operation succeeds.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcGetCsd (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT EMMC_CSD                       *Csd
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_CSD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    //
+    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+    //
+    CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);
+  }
+
+  return Status;
+}
+
+/**
+  Send command SELECT_DESELECT_CARD to the EMMC device to select/deselect it.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSelect (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_EXT_CSD to the EMMC device to get the data of the EXT_CSD register.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[out] ExtCsd        The buffer to store the content of the EXT_CSD register.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcGetExtCsd (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+     OUT EMMC_EXT_CSD                   *ExtCsd
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = 0x00000000;
+
+  Packet.InDataBuffer     = ExtCsd;
+  Packet.InTransferLength = sizeof (EMMC_EXT_CSD);
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  return Status;
+}
+
+/**
+  Send command SWITCH to the EMMC device to switch the mode of operation of the
+  selected Device or modifies the EXT_CSD registers.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Access        The access mode of SWTICH command.
+  @param[in]  Index         The offset of the field to be access.
+  @param[in]  Value         The value to be set to the specified field of EXT_CSD register.
+  @param[in]  CmdSet        The value of CmdSet field of EXT_CSD register.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitch (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT8                              Access,
+  IN UINT8                              Index,
+  IN UINT8                              Value,
+  IN UINT8                              CmdSet
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SWITCH;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
+  SdMmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_STATUS to the addressed EMMC device to get its status register.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of addressed device.
+  @param[out] DevStatus     The returned device status.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSendStatus (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT UINT32                         *DevStatus
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    *DevStatus = SdMmcStatusBlk.Resp0;
+  }
+
+  return Status;
+}
+
+/**
+  Send command SEND_TUNING_BLOCK to the EMMC device for HS200 optimal sampling point
+  detection.
+
+  It may be sent up to 40 times until the host finishes the tuning procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] BusWidth       The bus width to work.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSendTuningBlk (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT8                                 TuningBlock[128];
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  Packet.InDataBuffer = TuningBlock;
+  if (BusWidth == 8) {
+    Packet.InTransferLength = sizeof (TuningBlock);
+  } else {
+    Packet.InTransferLength = 64;
+  }
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Tunning the clock to get HS200 optimal sampling point.
+
+  Command SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the
+  tuning procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] BusWidth       The bus width to work.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcTuningClkForHs200 (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_STATUS          Status;
+  UINT8               HostCtrl2;
+  UINT8               Retry;
+
+  //
+  // Notify the host that the sampling clock tuning procedure starts.
+  //
+  HostCtrl2 = BIT6;
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
+  //
+  Retry = 0;
+  do {
+    Status = EmmcSendTuningBlk (PassThru, Slot, BusWidth);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "EmmcTuningClkForHs200: Send tuning block fails with %r\n", Status));
+      return Status;
+    }
+
+    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
+      break;
+    }
+
+    if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
+      return EFI_SUCCESS;
+    }
+  } while (++Retry < 40);
+
+  DEBUG ((DEBUG_ERROR, "EmmcTuningClkForHs200: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));
+  //
+  // Abort the tuning procedure and reset the tuning circuit.
+  //
+  HostCtrl2 = (UINT8)~(BIT6 | BIT7);
+  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return EFI_DEVICE_ERROR;
+}
+
+/**
+  Switch the bus width to specified width.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.9 and SD Host Controller
+  Simplified Spec 3.0 Figure 3-7 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] IsDdr          If TRUE, use dual data rate data simpling method. Otherwise
+                            use single data rate data simpling method.
+  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchBusWidth (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN BOOLEAN                            IsDdr,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_STATUS          Status;
+  UINT8               Access;
+  UINT8               Index;
+  UINT8               Value;
+  UINT8               CmdSet;
+  UINT32              DevStatus;
+
+  //
+  // Write Byte, the Value field is written into the byte pointed by Index.
+  //
+  Access = 0x03;
+  Index  = OFFSET_OF (EMMC_EXT_CSD, BusWidth);
+  if (BusWidth == 4) {
+    Value = 1;
+  } else if (BusWidth == 8) {
+    Value = 2;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (IsDdr) {
+    Value += 4;
+  }
+
+  CmdSet = 0;
+  Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Switch to bus width %d fails with %r\n", BusWidth, Status));
+    return Status;
+  }
+
+  Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Check the switch operation is really successful or not.
+  //
+  if ((DevStatus & BIT7) != 0) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);
+
+  return Status;
+}
+
+/**
+  Switch the clock frequency to the specified value.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Controller
+  Simplified Spec 3.0 Figure 3-3 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] HsTiming       The value to be written to HS_TIMING field of EXT_CSD register.
+  @param[in] ClockFreq      The max clock frequency to be set, the unit is MHz.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchClockFreq (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT8                              HsTiming,
+  IN UINT32                             ClockFreq
+  )
+{
+  EFI_STATUS                Status;
+  UINT8                     Access;
+  UINT8                     Index;
+  UINT8                     Value;
+  UINT8                     CmdSet;
+  UINT32                    DevStatus;
+  SD_MMC_HC_PRIVATE_DATA    *Private;
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  //
+  // Write Byte, the Value field is written into the byte pointed by Index.
+  //
+  Access = 0x03;
+  Index  = OFFSET_OF (EMMC_EXT_CSD, HsTiming);
+  Value  = HsTiming;
+  CmdSet = 0;
+
+  Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: Switch to hstiming %d fails with %r\n", HsTiming, Status));
+    return Status;
+  }
+
+  Status = EmmcSendStatus (PassThru, Slot, Rca, &DevStatus);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: Send status fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Check the switch operation is really successful or not.
+  //
+  if ((DevStatus & BIT7) != 0) {
+    DEBUG ((DEBUG_ERROR, "EmmcSwitchClockFreq: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));
+    return EFI_DEVICE_ERROR;
+  }
+  //
+  // Convert the clock freq unit from MHz to KHz.
+  //
+  Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->Capability[Slot]);
+
+  return Status;
+}
+
+/**
+  Switch to the High Speed timing according to request.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] ClockFreq      The max clock frequency to be set.
+  @param[in] IsDdr          If TRUE, use dual data rate data simpling method. Otherwise
+                            use single data rate data simpling method.
+  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchToHighSpeed (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT32                             ClockFreq,
+  IN BOOLEAN                            IsDdr,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_STATUS          Status;
+  UINT8               HsTiming;
+  UINT8               HostCtrl1;
+  UINT8               HostCtrl2;
+
+  Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set to Hight Speed timing
+  //
+  HostCtrl1 = BIT2;
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Clean UHS Mode Select field of Host Control 2 reigster before update
+  //
+  HostCtrl2 = (UINT8)~0x7;
+  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
+  //
+  if (IsDdr) {
+    HostCtrl2 = BIT2;
+  } else if (ClockFreq == 52) {
+    HostCtrl2 = BIT0;
+  } else {
+    HostCtrl2 = 0;
+  }
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  HsTiming = 1;
+  Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return Status;
+}
+
+/**
+  Switch to the HS200 timing according to request.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] ClockFreq      The max clock frequency to be set.
+  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchToHS200 (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT32                             ClockFreq,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_STATUS          Status;
+  UINT8               HsTiming;
+  UINT8               HostCtrl2;
+  UINT16              ClockCtrl;
+
+  if ((BusWidth != 4) && (BusWidth != 8)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, FALSE, BusWidth);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set to HS200/SDR104 timing
+  //
+  //
+  // Stop bus clock at first
+  //
+  Status = SdMmcHcStopClock (PciIo, Slot);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Clean UHS Mode Select field of Host Control 2 reigster before update
+  //
+  HostCtrl2 = (UINT8)~0x7;
+  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set UHS Mode Select field of Host Control 2 reigster to SDR104
+  //
+  HostCtrl2 = BIT0 | BIT1;
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
+  //
+  Status = SdMmcHcWaitMmioSet (
+             PciIo,
+             Slot,
+             SD_MMC_HC_CLOCK_CTRL,
+             sizeof (ClockCtrl),
+             BIT1,
+             BIT1,
+             SD_MMC_HC_GENERIC_TIMEOUT
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set SD Clock Enable in the Clock Control register to 1
+  //
+  ClockCtrl = BIT2;
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
+
+  HsTiming = 2;
+  Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth);
+
+  return Status;
+}
+
+/**
+  Switch to the HS400 timing according to request.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] ClockFreq      The max clock frequency to be set.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSwitchToHS400 (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT32                             ClockFreq
+  )
+{
+  EFI_STATUS          Status;
+  UINT8               HsTiming;
+  UINT8               HostCtrl2;
+
+  Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set to Hight Speed timing and set the clock frequency to a value less than 52MHz.
+  //
+  HsTiming = 1;
+  Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, 52);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // HS400 mode must use 8 data lines.
+  //
+  Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, TRUE, 8);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Clean UHS Mode Select field of Host Control 2 reigster before update
+  //
+  HostCtrl2 = (UINT8)~0x7;
+  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set UHS Mode Select field of Host Control 2 reigster to HS400
+  //
+  HostCtrl2 = BIT0 | BIT2;
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  HsTiming = 3;
+  Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
+
+  return Status;
+}
+
+/**
+  Switch the high speed timing according to request.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+  Simplified Spec 3.0 Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+EmmcSetBusMode (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca
+  )
+{
+  EFI_STATUS                    Status;
+  EMMC_CSD                      Csd;
+  EMMC_EXT_CSD                  ExtCsd;
+  UINT8                         HsTiming;
+  BOOLEAN                       IsDdr;
+  UINT32                        ClockFreq;
+  UINT8                         BusWidth;
+  SD_MMC_HC_PRIVATE_DATA        *Private;
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+
+  Status = EmmcGetCsd (PassThru, Slot, Rca, &Csd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetCsd fails with %r\n", Status));
+    return Status;
+  }
+
+  Status = EmmcSelect (PassThru, Slot, Rca);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: Select fails with %r\n", Status));
+    return Status;
+  }
+
+  ASSERT (Private->Capability[Slot].BaseClkFreq != 0);
+  //
+  // Check if the Host Controller support 8bits bus width.
+  //
+  if (Private->Capability[Slot].BusWidth8 != 0) {
+    BusWidth = 8;
+  } else {
+    BusWidth = 4;
+  }
+  //
+  // Get Deivce_Type from EXT_CSD register.
+  //
+  Status = EmmcGetExtCsd (PassThru, Slot, &ExtCsd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetExtCsd fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Calculate supported bus speed/bus width/clock frequency.
+  //
+  HsTiming  = 0;
+  IsDdr     = FALSE;
+  ClockFreq = 0;
+  if (((ExtCsd.DeviceType & (BIT4 | BIT5))  != 0) && (Private->Capability[Slot].Sdr104 != 0)) {
+    HsTiming  = 2;
+    IsDdr     = FALSE;
+    ClockFreq = 200;
+  } else if (((ExtCsd.DeviceType & (BIT2 | BIT3))  != 0) && (Private->Capability[Slot].Ddr50 != 0)) {
+    HsTiming  = 1;
+    IsDdr     = TRUE;
+    ClockFreq = 52;
+  } else if (((ExtCsd.DeviceType & BIT1)  != 0) && (Private->Capability[Slot].HighSpeed != 0)) {
+    HsTiming  = 1;
+    IsDdr     = FALSE;
+    ClockFreq = 52;
+  } else if (((ExtCsd.DeviceType & BIT0)  != 0) && (Private->Capability[Slot].HighSpeed != 0)) {
+    HsTiming  = 1;
+    IsDdr     = FALSE;
+    ClockFreq = 26;
+  }
+  //
+  // Check if both of the device and the host controller support HS400 DDR mode.
+  //
+  if (((ExtCsd.DeviceType & (BIT6 | BIT7))  != 0) && (Private->Capability[Slot].Hs400 != 0)) {
+    //
+    // The host controller supports 8bits bus.
+    //
+    ASSERT (BusWidth == 8);
+    HsTiming  = 3;
+    IsDdr     = TRUE;
+    ClockFreq = 200;
+  }
+
+  if ((ClockFreq == 0) || (HsTiming == 0)) {
+    //
+    // Continue using default setting.
+    //
+    return EFI_SUCCESS;
+  }
+
+  DEBUG ((DEBUG_INFO, "EmmcSetBusMode: HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE"));
+
+  if (HsTiming == 3) {
+    //
+    // Execute HS400 timing switch procedure
+    //
+    Status = EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, ClockFreq);
+  } else if (HsTiming == 2) {
+    //
+    // Execute HS200 timing switch procedure
+    //
+    Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, BusWidth);
+  } else {
+    //
+    // Execute High Speed timing switch procedure
+    //
+    Status = EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, ClockFreq, IsDdr, BusWidth);
+  }
+
+  DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Switch to %a %r\n", (HsTiming == 3) ? "HS400" : ((HsTiming == 2) ? "HS200" : "HighSpeed"), Status));
+
+  return Status;
+}
+
+/**
+  Execute EMMC device identification procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       There is a EMMC card.
+  @retval Others            There is not a EMMC card.
+
+**/
+EFI_STATUS
+EmmcIdentification (
+  IN SD_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  )
+{
+  EFI_STATUS                     Status;
+  EFI_PCI_IO_PROTOCOL            *PciIo;
+  EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru;
+  UINT32                         Ocr;
+  UINT16                         Rca;
+
+  PciIo    = Private->PciIo;
+  PassThru = &Private->PassThru;
+
+  Status = EmmcReset (PassThru, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd0 fails with %r\n", Status));
+    return Status;
+  }
+
+  Ocr = 0;
+  do {
+    Status = EmmcGetOcr (PassThru, Slot, &Ocr);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd1 fails with %r\n", Status));
+      return Status;
+    }
+    Ocr |= BIT30;
+  } while ((Ocr & BIT31) == 0);
+
+  Status = EmmcGetAllCid (PassThru, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_VERBOSE, "EmmcIdentification: Executing Cmd2 fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Slot starts from 0 and valid RCA starts from 1.
+  // Here we takes a simple formula to calculate the RCA.
+  // Don't support multiple devices on the slot, that is
+  // shared bus slot feature.
+  //
+  Rca    = Slot + 1;
+  Status = EmmcSetRca (PassThru, Slot, Rca);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "EmmcIdentification: Executing Cmd3 fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Enter Data Tranfer Mode.
+  //
+  DEBUG ((DEBUG_INFO, "EmmcIdentification: Found a EMMC device at slot [%d], RCA [%d]\n", Slot, Rca));
+  Private->Slot[Slot].CardType = EmmcCardType;
+
+  Status = EmmcSetBusMode (PciIo, PassThru, Slot, Rca);
+
+  return Status;
+}
+
diff --git a/Drivers/SdMmc/XenonDxe/SdDevice.c b/Drivers/SdMmc/XenonDxe/SdDevice.c
new file mode 100644
index 0000000..9122848
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/SdDevice.c
@@ -0,0 +1,1190 @@
+/** @file
+  This file provides some helper functions which are specific for SD card device.
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SdMmcPciHcDxe.h"
+
+/**
+  Send command GO_IDLE_STATE to the device to make it go to Idle State.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The SD device is reset correctly.
+  @retval Others            The device reset fails.
+
+**/
+EFI_STATUS
+SdCardReset (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_GO_IDLE_STATE;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBc;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_IF_COND to the device to inquiry the SD Memory Card interface
+  condition.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] SupplyVoltage  The supplied voltage by the host.
+  @param[in] CheckPattern   The check pattern to be sent to the device.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardVoltageCheck (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT8                              SupplyVoltage,
+  IN UINT8                              CheckPattern
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_IF_COND;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR7;
+  SdMmcCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  if (!EFI_ERROR (Status)) {
+    if (SdMmcStatusBlk.Resp0 != SdMmcCmdBlk.CommandArgument) {
+      return EFI_DEVICE_ERROR;
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Send command SDIO_SEND_OP_COND to the device to see whether it is SDIO device.
+
+  Refer to SDIO Simplified Spec 3 Section 3.2 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] VoltageWindow  The supply voltage window.
+  @param[in] S18R           The boolean to show if it should switch to 1.8v.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdioSendOpCond (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT32                             VoltageWindow,
+  IN BOOLEAN                            S18R
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT32                                Switch;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SDIO_SEND_OP_COND;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR4;
+
+  Switch = S18R ? BIT24 : 0;
+
+  SdMmcCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SD_SEND_OP_COND to the device to see whether it is SDIO device.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot           The slot number of the SD card to send the command to.
+  @param[in]  Rca            The relative device address of addressed device.
+  @param[in]  VoltageWindow  The supply voltage window.
+  @param[in]  S18R           The boolean to show if it should switch to 1.8v.
+  @param[in]  Xpc            The boolean to show if it should provide 0.36w power control.
+  @param[in]  Hcs            The boolean to show if it support host capacity info.
+  @param[out] Ocr            The buffer to store returned OCR register value.
+
+  @retval EFI_SUCCESS        The operation is done correctly.
+  @retval Others             The operation fails.
+
+**/
+EFI_STATUS
+SdCardSendOpCond (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+  IN     UINT32                         VoltageWindow,
+  IN     BOOLEAN                        S18R,
+  IN     BOOLEAN                        Xpc,
+  IN     BOOLEAN                        Hcs,
+     OUT UINT32                         *Ocr
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT32                                Switch;
+  UINT32                                MaxPower;
+  UINT32                                HostCapacity;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_OP_COND;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3;
+
+  Switch       = S18R ? BIT24 : 0;
+  MaxPower     = Xpc ? BIT28 : 0;
+  HostCapacity = Hcs ? BIT30 : 0;
+
+  SdMmcCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch | MaxPower | HostCapacity;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    //
+    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+    //
+    *Ocr = SdMmcStatusBlk.Resp0;
+  }
+
+  return Status;
+}
+
+/**
+  Broadcast command ALL_SEND_CID to the bus to ask all the SD devices to send the
+  data of their CID registers.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardAllSendCid (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_ALL_SEND_CID;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SET_RELATIVE_ADDR to the SD device to assign a Relative device
+  Address (RCA).
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[out] Rca           The relative device address to assign.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSetRca (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+     OUT UINT16                         *Rca
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SET_RELATIVE_ADDR;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeBcr;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR6;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    *Rca = (UINT16)(SdMmcStatusBlk.Resp0 >> 16);
+  }
+
+  return Status;
+}
+
+/**
+  Send command SEND_CSD to the SD device to get the data of the CSD register.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+  @param[out] Csd           The buffer to store the content of the CSD register.
+                            Note the caller should ignore the lowest byte of this
+                            buffer as the content of this byte is meaningless even
+                            if the operation succeeds.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardGetCsd (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT SD_CSD                         *Csd
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_CSD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    //
+    // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+    //
+    CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (SD_CSD) - 1);
+  }
+
+  return Status;
+}
+
+/**
+  Send command SEND_CSD to the SD device to get the data of the CSD register.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+  @param[out] Scr           The buffer to store the content of the SCR register.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardGetScr (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT SD_SCR                         *Scr
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_SCR;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+
+  Packet.InDataBuffer     = Scr;
+  Packet.InTransferLength = sizeof (SD_SCR);
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SELECT_DESELECT_CARD to the SD device to select/deselect it.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of selected device.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSelect (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SELECT_DESELECT_CARD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  if (Rca != 0) {
+    SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b;
+  }
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command VOLTAGE_SWITCH to the SD device to switch the voltage of the device.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardVoltageSwitch (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SET_BUS_WIDTH to the SD device to set the bus width.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address of addressed device.
+  @param[in] BusWidth       The bus width to be set, it could be 1 or 4.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSetBusWidth (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT8                                 Value;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  SdMmcCmdBlk.CommandIndex = SD_SET_BUS_WIDTH;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+
+  if (BusWidth == 1) {
+    Value = 0;
+  } else if (BusWidth == 4) {
+    Value = 2;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  SdMmcCmdBlk.CommandArgument = Value & 0x3;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  return Status;
+}
+
+/**
+  Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  AccessMode    The value for access mode group.
+  @param[in]  CommandSystem The value for command set group.
+  @param[in]  DriveStrength The value for drive length group.
+  @param[in]  PowerLimit    The value for power limit group.
+  @param[in]  Mode          Switch or check function.
+  @param[out] SwitchResp    The return switch function status.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSwitch (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT8                          AccessMode,
+  IN     UINT8                          CommandSystem,
+  IN     UINT8                          DriveStrength,
+  IN     UINT8                          PowerLimit,
+  IN     BOOLEAN                        Mode,
+     OUT UINT8                          *SwitchResp
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT32                                ModeValue;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SWITCH_FUNC;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+
+  ModeValue = Mode ? BIT31 : 0;
+  SdMmcCmdBlk.CommandArgument = (AccessMode & 0xF) | ((PowerLimit & 0xF) << 4) | \
+                                ((DriveStrength & 0xF) << 8) | ((DriveStrength & 0xF) << 12) | \
+                                ModeValue;
+
+  Packet.InDataBuffer     = SwitchResp;
+  Packet.InTransferLength = 64;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Send command SEND_STATUS to the addressed SD device to get its status register.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in]  PassThru      A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[in]  Rca           The relative device address of addressed device.
+  @param[out] DevStatus     The returned device status.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSendStatus (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN     UINT8                          Slot,
+  IN     UINT16                         Rca,
+     OUT UINT32                         *DevStatus
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_STATUS;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+  if (!EFI_ERROR (Status)) {
+    *DevStatus = SdMmcStatusBlk.Resp0;
+  }
+
+  return Status;
+}
+
+/**
+  Send command SEND_TUNING_BLOCK to the SD device for HS200 optimal sampling point
+  detection.
+
+  It may be sent up to 40 times until the host finishes the tuning procedure.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSendTuningBlk (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_SD_MMC_COMMAND_BLOCK              SdMmcCmdBlk;
+  EFI_SD_MMC_STATUS_BLOCK               SdMmcStatusBlk;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   Packet;
+  EFI_STATUS                            Status;
+  UINT8                                 TuningBlock[64];
+
+  ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+  ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+  ZeroMem (&Packet, sizeof (Packet));
+
+  Packet.SdMmcCmdBlk    = &SdMmcCmdBlk;
+  Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+  Packet.Timeout        = SD_MMC_HC_GENERIC_TIMEOUT;
+
+  SdMmcCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
+  SdMmcCmdBlk.CommandType  = SdMmcCommandTypeAdtc;
+  SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+  SdMmcCmdBlk.CommandArgument = 0;
+
+  Packet.InDataBuffer     = TuningBlock;
+  Packet.InTransferLength = sizeof (TuningBlock);
+
+  Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+  return Status;
+}
+
+/**
+  Tunning the sampling point of SDR104 or SDR50 bus speed mode.
+
+  Command SD_SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the
+  tuning procedure.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
+  SD Host Controller Simplified Spec 3.0 section Figure 3-7 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardTuningClock (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot
+  )
+{
+  EFI_STATUS          Status;
+  UINT8               HostCtrl2;
+  UINT8               Retry;
+
+  //
+  // Notify the host that the sampling clock tuning procedure starts.
+  //
+  HostCtrl2 = BIT6;
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
+  //
+  Retry = 0;
+  do {
+    Status = SdCardSendTuningBlk (PassThru, Slot);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "SdCardSendTuningBlk: Send tuning block fails with %r\n", Status));
+      return Status;
+    }
+
+    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
+      break;
+    }
+    if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
+      return EFI_SUCCESS;
+    }
+  } while (++Retry < 40);
+
+  DEBUG ((DEBUG_ERROR, "SdCardTuningClock: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));
+  //
+  // Abort the tuning procedure and reset the tuning circuit.
+  //
+  HostCtrl2 = (UINT8)~(BIT6 | BIT7);
+  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return EFI_DEVICE_ERROR;
+}
+
+/**
+  Switch the bus width to specified width.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
+  SD Host Controller Simplified Spec 3.0 section Figure 3-7 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] BusWidth       The bus width to be set, it could be 4 or 8.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSwitchBusWidth (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN UINT8                              BusWidth
+  )
+{
+  EFI_STATUS          Status;
+  UINT32              DevStatus;
+
+  Status = SdCardSetBusWidth (PassThru, Slot, Rca, BusWidth);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardSwitchBusWidth: Switch to bus width %d fails with %r\n", BusWidth, Status));
+    return Status;
+  }
+
+  Status = SdCardSendStatus (PassThru, Slot, Rca, &DevStatus);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardSwitchBusWidth: Send status fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Check the switch operation is really successful or not.
+  //
+  if ((DevStatus >> 16) != 0) {
+    DEBUG ((DEBUG_ERROR, "SdCardSwitchBusWidth: The switch operation fails as DevStatus is 0x%08x\n", DevStatus));
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);
+
+  return Status;
+}
+
+/**
+  Switch the high speed timing according to request.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
+  SD Host Controller Simplified Spec 3.0 section Figure 2-29 for details.
+
+  @param[in] PciIo          A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThru       A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Rca            The relative device address to be assigned.
+  @param[in] S18A           The boolean to show if it's a UHS-I SD card.
+
+  @retval EFI_SUCCESS       The operation is done correctly.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdCardSetBusMode (
+  IN EFI_PCI_IO_PROTOCOL                *PciIo,
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL      *PassThru,
+  IN UINT8                              Slot,
+  IN UINT16                             Rca,
+  IN BOOLEAN                            S18A
+  )
+{
+  EFI_STATUS                   Status;
+  SD_MMC_HC_SLOT_CAP           *Capability;
+  UINT32                       ClockFreq;
+  UINT8                        BusWidth;
+  UINT8                        AccessMode;
+  UINT8                        HostCtrl1;
+  UINT8                        HostCtrl2;
+  UINT8                        SwitchResp[64];
+  SD_MMC_HC_PRIVATE_DATA       *Private;
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+
+  Capability = &Private->Capability[Slot];
+
+  Status = SdCardSelect (PassThru, Slot, Rca);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  BusWidth = 4;
+
+  Status = SdCardSwitchBusWidth (PciIo, PassThru, Slot, Rca, BusWidth);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Get the supported bus speed from SWITCH cmd return data group #1.
+  //
+  Status = SdCardSwitch (PassThru, Slot, 0xF, 0xF, 0xF, 0xF, FALSE, SwitchResp);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Calculate supported bus speed/bus width/clock frequency by host and device capability.
+  //
+  ClockFreq = 0;
+  if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
+    ClockFreq = 208;
+    AccessMode = 3;
+  } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
+    ClockFreq = 100;
+    AccessMode = 2;
+  } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
+    ClockFreq = 50;
+    AccessMode = 4;
+  } else if ((SwitchResp[13] & BIT1) != 0) {
+    ClockFreq = 50;
+    AccessMode = 1;
+  } else {
+    ClockFreq = 25;
+    AccessMode = 0;
+  }
+
+  Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if ((SwitchResp[16] & 0xF) != AccessMode) {
+    DEBUG ((DEBUG_ERROR, "SdCardSetBusMode: Switch to AccessMode %d ClockFreq %d BusWidth %d fails! The Switch response is 0x%1x\n", AccessMode, ClockFreq, BusWidth, SwitchResp[16] & 0xF));
+    return EFI_DEVICE_ERROR;
+  }
+
+  DEBUG ((DEBUG_INFO, "SdCardSetBusMode: Switch to AccessMode %d ClockFreq %d BusWidth %d\n", AccessMode, ClockFreq, BusWidth));
+
+  //
+  // Set to Hight Speed timing
+  //
+  if (AccessMode == 1) {
+    HostCtrl1 = BIT2;
+    Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+
+  HostCtrl2 = (UINT8)~0x7;
+  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  HostCtrl2 = AccessMode;
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if ((AccessMode == 3) || ((AccessMode == 2) && (Capability->TuningSDR50 != 0))) {
+    Status = SdCardTuningClock (PciIo, PassThru, Slot);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Execute SD device identification procedure.
+
+  Refer to SD Physical Layer Simplified Spec 4.1 Section 3.6 for details.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       There is a SD card.
+  @retval Others            There is not a SD card.
+
+**/
+EFI_STATUS
+SdCardIdentification (
+  IN SD_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  )
+{
+  EFI_STATUS                     Status;
+  EFI_PCI_IO_PROTOCOL            *PciIo;
+  EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru;
+  UINT32                         Ocr;
+  UINT16                         Rca;
+  BOOLEAN                        Xpc;
+  BOOLEAN                        S18r;
+  UINT64                         MaxCurrent;
+  UINT16                         ControllerVer;
+  UINT8                          PowerCtrl;
+  UINT32                         PresentState;
+  UINT8                          HostCtrl2;
+
+  PciIo    = Private->PciIo;
+  PassThru = &Private->PassThru;
+  //
+  // 1. Send Cmd0 to the device
+  //
+  Status = SdCardReset (PassThru, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing Cmd0 fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // 2. Send Cmd8 to the device
+  //
+  Status = SdCardVoltageCheck (PassThru, Slot, 0x1, 0xFF);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing Cmd8 fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // 3. Send SDIO Cmd5 to the device to the SDIO device OCR register.
+  //
+  Status = SdioSendOpCond (PassThru, Slot, 0, FALSE);
+  if (!EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Found SDIO device, ignore it as we don't support\n"));
+    return EFI_DEVICE_ERROR;
+  }
+  //
+  // 4. Send Acmd41 with voltage window 0 to the device
+  //
+  Status = SdCardSendOpCond (PassThru, Slot, 0, 0, FALSE, FALSE, FALSE, &Ocr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Executing SdCardSendOpCond fails with %r\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (Private->Capability[Slot].Voltage33 != 0) {
+    //
+    // Support 3.3V
+    //
+    MaxCurrent = ((UINT32)Private->MaxCurrent[Slot] & 0xFF) * 4;
+  } else if (Private->Capability[Slot].Voltage30 != 0) {
+    //
+    // Support 3.0V
+    //
+    MaxCurrent = (((UINT32)Private->MaxCurrent[Slot] >> 8) & 0xFF) * 4;
+  } else if (Private->Capability[Slot].Voltage18 != 0) {
+    //
+    // Support 1.8V
+    //
+    MaxCurrent = (((UINT32)Private->MaxCurrent[Slot] >> 16) & 0xFF) * 4;
+  } else {
+    ASSERT (FALSE);
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (MaxCurrent >= 150) {
+    Xpc = TRUE;
+  } else {
+    Xpc = FALSE;
+  }
+
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if ((ControllerVer & 0xFF) == 2) {
+    S18r = TRUE;
+  } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
+    S18r = FALSE;
+  } else {
+    ASSERT (FALSE);
+    return EFI_UNSUPPORTED;
+  }
+  //
+  // 5. Repeatly send Acmd41 with supply voltage window to the device.
+  //    Note here we only support the cards complied with SD physical
+  //    layer simplified spec version 2.0 and version 3.0 and above.
+  //
+  do {
+    Status = SdCardSendOpCond (PassThru, Slot, 0, Ocr, S18r, Xpc, TRUE, &Ocr);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "SdCardIdentification: SdCardSendOpCond fails with %r Ocr %x, S18r %x, Xpc %x\n", Status, Ocr, S18r, Xpc));
+      return EFI_DEVICE_ERROR;
+    }
+  } while ((Ocr & BIT31) == 0);
+
+  //
+  // 6. If the S18A bit is set and the Host Controller supports 1.8V signaling
+  //    (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the
+  //    Capabilities register), switch its voltage to 1.8V.
+  //
+  if ((Private->Capability[Slot].Sdr50 != 0 ||
+       Private->Capability[Slot].Sdr104 != 0 ||
+       Private->Capability[Slot].Ddr50 != 0) &&
+       ((Ocr & BIT24) != 0)) {
+    Status = SdCardVoltageSwitch (PassThru, Slot);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardVoltageSwitch fails with %r\n", Status));
+      Status = EFI_DEVICE_ERROR;
+      goto Error;
+    } else {
+      Status = SdMmcHcStopClock (PciIo, Slot);
+      if (EFI_ERROR (Status)) {
+        Status = EFI_DEVICE_ERROR;
+        goto Error;
+      }
+
+      SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
+      if (((PresentState >> 20) & 0xF) != 0) {
+        DEBUG ((DEBUG_ERROR, "SdCardIdentification: SwitchVoltage fails with PresentState = 0x%x\n", PresentState));
+        Status = EFI_DEVICE_ERROR;
+        goto Error;
+      }
+      HostCtrl2  = BIT3;
+      SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+
+      gBS->Stall (5000);
+
+      SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
+      if ((HostCtrl2 & BIT3) == 0) {
+        DEBUG ((DEBUG_ERROR, "SdCardIdentification: SwitchVoltage fails with HostCtrl2 = 0x%x\n", HostCtrl2));
+        Status = EFI_DEVICE_ERROR;
+        goto Error;
+      }
+
+      SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]);
+
+      gBS->Stall (1000);
+
+      SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
+      if (((PresentState >> 20) & 0xF) != 0xF) {
+        DEBUG ((DEBUG_ERROR, "SdCardIdentification: SwitchVoltage fails with PresentState = 0x%x, It should be 0xF\n", PresentState));
+        Status = EFI_DEVICE_ERROR;
+        goto Error;
+      }
+    }
+    DEBUG ((DEBUG_INFO, "SdCardIdentification: Switch to 1.8v signal voltage success\n"));
+  }
+
+  Status = SdCardAllSendCid (PassThru, Slot);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardAllSendCid fails with %r\n", Status));
+    return Status;
+  }
+
+  Status = SdCardSetRca (PassThru, Slot, &Rca);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdCardIdentification: Executing SdCardSetRca fails with %r\n", Status));
+    return Status;
+  }
+  //
+  // Enter Data Tranfer Mode.
+  //
+  DEBUG ((DEBUG_INFO, "SdCardIdentification: Found a SD device at slot [%d]\n", Slot));
+  Private->Slot[Slot].CardType = SdCardType;
+
+  Status = SdCardSetBusMode (PciIo, PassThru, Slot, Rca, ((Ocr & BIT24) != 0));
+
+  return Status;
+
+Error:
+  //
+  // Set SD Bus Power = 0
+  //
+  PowerCtrl = (UINT8)~BIT0;
+  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);
+  return EFI_DEVICE_ERROR;
+}
+
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c
new file mode 100644
index 0000000..981eab5
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c
@@ -0,0 +1,1315 @@
+/** @file
+  This driver is used to manage SD/MMC PCI host controllers which are compliance
+  with SD Host Controller Simplified Specification version 3.00.
+
+  It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (C) 2016 Marvell International Ltd. All rigths reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SdMmcPciHcDxe.h"
+#include "XenonSdhci.h"
+
+//
+// Driver Global Variables
+//
+EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding = {
+  SdMmcPciHcDriverBindingSupported,
+  SdMmcPciHcDriverBindingStart,
+  SdMmcPciHcDriverBindingStop,
+  0x10,
+  NULL,
+  NULL
+};
+
+//
+// Template for SD/MMC host controller private data.
+//
+SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
+  SD_MMC_HC_PRIVATE_SIGNATURE,      // Signature
+  NULL,                             // ControllerHandle
+  NULL,                             // PciIo
+  {                                 // PassThru
+    sizeof (UINT32),
+    SdMmcPassThruPassThru,
+    SdMmcPassThruGetNextSlot,
+    SdMmcPassThruBuildDevicePath,
+    SdMmcPassThruGetSlotNumber,
+    SdMmcPassThruResetDevice
+  },
+  0,                                // PciAttributes
+  0,                                // PreviousSlot
+  NULL,                             // TimerEvent
+  NULL,                             // ConnectEvent
+                                    // Queue
+  INITIALIZE_LIST_HEAD_VARIABLE (gSdMmcPciHcTemplate.Queue),
+  {                                 // Slot
+    {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0},
+    {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}
+  },
+  {                                 // Capability
+    {0},
+  },
+  {                                 // MaxCurrent
+    0,
+  },
+  0                                 // ControllerVersion
+};
+
+SD_DEVICE_PATH    mSdDpTemplate = {
+  {
+    MESSAGING_DEVICE_PATH,
+    MSG_SD_DP,
+    {
+      (UINT8) (sizeof (SD_DEVICE_PATH)),
+      (UINT8) ((sizeof (SD_DEVICE_PATH)) >> 8)
+    }
+  },
+  0
+};
+
+EMMC_DEVICE_PATH    mEmmcDpTemplate = {
+  {
+    MESSAGING_DEVICE_PATH,
+    MSG_EMMC_DP,
+    {
+      (UINT8) (sizeof (EMMC_DEVICE_PATH)),
+      (UINT8) ((sizeof (EMMC_DEVICE_PATH)) >> 8)
+    }
+  },
+  0
+};
+
+//
+// Prioritized function list to detect card type.
+// User could add other card detection logic here.
+//
+CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = {
+  EmmcIdentification,
+  SdCardIdentification,
+  NULL
+};
+
+/**
+  The entry point for SD host controller driver, used to install this driver on the ImageHandle.
+
+  @param[in]  ImageHandle   The firmware allocated handle for this driver image.
+  @param[in]  SystemTable   Pointer to the EFI system table.
+
+  @retval EFI_SUCCESS   Driver loaded.
+  @retval other         Driver not loaded.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeSdMmcPciHcDxe (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS           Status;
+
+  Status = EfiLibInstallDriverBindingComponentName2 (
+             ImageHandle,
+             SystemTable,
+             &gSdMmcPciHcDriverBinding,
+             ImageHandle,
+             &gSdMmcPciHcComponentName,
+             &gSdMmcPciHcComponentName2
+             );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+/**
+  Call back function when the timer event is signaled.
+
+  @param[in]  Event     The Event this notify function registered to.
+  @param[in]  Context   Pointer to the context data registered to the
+                        Event.
+
+**/
+VOID
+EFIAPI
+ProcessAsyncTaskList (
+  IN EFI_EVENT          Event,
+  IN VOID*              Context
+  )
+{
+  SD_MMC_HC_PRIVATE_DATA              *Private;
+  LIST_ENTRY                          *Link;
+  SD_MMC_HC_TRB                       *Trb;
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  BOOLEAN                             InfiniteWait;
+  EFI_EVENT                           TrbEvent;
+
+  Private = (SD_MMC_HC_PRIVATE_DATA*)Context;
+
+  //
+  // Check if the first entry in the async I/O queue is done or not.
+  //
+  Status = EFI_SUCCESS;
+  Trb    = NULL;
+  Link   = GetFirstNode (&Private->Queue);
+  if (!IsNull (&Private->Queue, Link)) {
+    Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
+    if (!Private->Slot[Trb->Slot].MediaPresent) {
+      Status = EFI_NO_MEDIA;
+      goto Done;
+    }
+    if (!Trb->Started) {
+      //
+      // Check whether the cmd/data line is ready for transfer.
+      //
+      Status = SdMmcCheckTrbEnv (Private, Trb);
+      if (!EFI_ERROR (Status)) {
+        Trb->Started = TRUE;
+        Status = SdMmcExecTrb (Private, Trb);
+        if (EFI_ERROR (Status)) {
+          goto Done;
+        }
+      } else {
+        goto Done;
+      }
+    }
+    Status = SdMmcCheckTrbResult (Private, Trb);
+  }
+
+Done:
+  if ((Trb != NULL) && (Status == EFI_NOT_READY)) {
+    Packet = Trb->Packet;
+    if (Packet->Timeout == 0) {
+      InfiniteWait = TRUE;
+    } else {
+      InfiniteWait = FALSE;
+    }
+    if ((!InfiniteWait) && (Trb->Timeout-- == 0)) {
+      RemoveEntryList (Link);
+      Trb->Packet->TransactionStatus = EFI_TIMEOUT;
+      TrbEvent = Trb->Event;
+      SdMmcFreeTrb (Trb);
+      DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p EFI_TIMEOUT\n", TrbEvent));
+      gBS->SignalEvent (TrbEvent);
+      return;
+    }
+  }
+  if ((Trb != NULL) && (Status != EFI_NOT_READY)) {
+    RemoveEntryList (Link);
+    Trb->Packet->TransactionStatus = Status;
+    TrbEvent = Trb->Event;
+    SdMmcFreeTrb (Trb);
+    DEBUG ((DEBUG_VERBOSE, "ProcessAsyncTaskList(): Signal Event %p with %r\n", TrbEvent, Status));
+    gBS->SignalEvent (TrbEvent);
+  }
+  return;
+}
+
+/**
+  Sd removable device enumeration callback function when the timer event is signaled.
+
+  @param[in]  Event     The Event this notify function registered to.
+  @param[in]  Context   Pointer to the context data registered to the
+                        Event.
+
+**/
+VOID
+EFIAPI
+SdMmcPciHcEnumerateDevice (
+  IN EFI_EVENT          Event,
+  IN VOID*              Context
+  )
+{
+  SD_MMC_HC_PRIVATE_DATA              *Private;
+  EFI_STATUS                          Status;
+  UINT8                               Slot;
+  BOOLEAN                             MediaPresent;
+  UINT32                              RoutineNum;
+  CARD_TYPE_DETECT_ROUTINE            *Routine;
+  UINTN                               Index;
+  LIST_ENTRY                          *Link;
+  LIST_ENTRY                          *NextLink;
+  SD_MMC_HC_TRB                       *Trb;
+  EFI_TPL                             OldTpl;
+
+  Private = (SD_MMC_HC_PRIVATE_DATA*)Context;
+
+  for (Slot = 0; Slot < SD_MMC_HC_MAX_SLOT; Slot++) {
+    if ((Private->Slot[Slot].Enable) && (Private->Slot[Slot].SlotType == RemovableSlot)) {
+      Status = SdMmcHcCardDetect (Private->PciIo, Slot, &MediaPresent);
+      if ((Status == EFI_MEDIA_CHANGED) && !MediaPresent) {
+        DEBUG ((DEBUG_INFO, "SdMmcPciHcEnumerateDevice: device disconnected at slot %d of pci %p\n", Slot, Private->PciIo));
+        Private->Slot[Slot].MediaPresent = FALSE;
+        Private->Slot[Slot].Initialized  = FALSE;
+        //
+        // Signal all async task events at the slot with EFI_NO_MEDIA status.
+        //
+        OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+        for (Link = GetFirstNode (&Private->Queue);
+             !IsNull (&Private->Queue, Link);
+             Link = NextLink) {
+          NextLink = GetNextNode (&Private->Queue, Link);
+          Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
+          if (Trb->Slot == Slot) {
+            RemoveEntryList (Link);
+            Trb->Packet->TransactionStatus = EFI_NO_MEDIA;
+            gBS->SignalEvent (Trb->Event);
+            SdMmcFreeTrb (Trb);
+          }
+        }
+        gBS->RestoreTPL (OldTpl);
+        //
+        // Notify the upper layer the connect state change through ReinstallProtocolInterface.
+        //
+        gBS->ReinstallProtocolInterface (
+              Private->ControllerHandle,
+              &gEfiSdMmcPassThruProtocolGuid,
+              &Private->PassThru,
+              &Private->PassThru
+              );
+      }
+      if ((Status == EFI_MEDIA_CHANGED) && MediaPresent) {
+        DEBUG ((DEBUG_INFO, "SdMmcPciHcEnumerateDevice: device connected at slot %d of pci %p\n", Slot, Private->PciIo));
+        //
+        // Reset the specified slot of the SD/MMC Pci Host Controller
+        //
+        Status = SdMmcHcReset (Private->PciIo, Slot);
+        if (EFI_ERROR (Status)) {
+          continue;
+        }
+        //
+        // Reinitialize slot and restart identification process for the new attached device
+        //
+        Status = SdMmcHcInitHost (Private->PciIo, Slot, Private->Capability[Slot]);
+        if (EFI_ERROR (Status)) {
+          continue;
+        }
+
+        Private->Slot[Slot].MediaPresent = TRUE;
+        Private->Slot[Slot].Initialized  = TRUE;
+        RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
+        for (Index = 0; Index < RoutineNum; Index++) {
+          Routine = &mCardTypeDetectRoutineTable[Index];
+          if (*Routine != NULL) {
+            Status = (*Routine) (Private, Slot);
+            if (!EFI_ERROR (Status)) {
+              break;
+            }
+          }
+        }
+        //
+        // This card doesn't get initialized correctly.
+        //
+        if (Index == RoutineNum) {
+          Private->Slot[Slot].Initialized = FALSE;
+        }
+
+        //
+        // Notify the upper layer the connect state change through ReinstallProtocolInterface.
+        //
+        gBS->ReinstallProtocolInterface (
+               Private->ControllerHandle,
+               &gEfiSdMmcPassThruProtocolGuid,
+               &Private->PassThru,
+               &Private->PassThru
+               );
+      }
+    }
+  }
+
+  return;
+}
+/**
+  Tests to see if this driver supports a given controller. If a child device is provided,
+  it further tests to see if this driver supports creating a handle for the specified child device.
+
+  This function checks to see if the driver specified by This supports the device specified by
+  ControllerHandle. Drivers will typically use the device path attached to
+  ControllerHandle and/or the services from the bus I/O abstraction attached to
+  ControllerHandle to determine if the driver supports ControllerHandle. This function
+  may be called many times during platform initialization. In order to reduce boot times, the tests
+  performed by this function must be very small, and take as little time as possible to execute. This
+  function must not change the state of any hardware devices, and this function must be aware that the
+  device specified by ControllerHandle may already be managed by the same driver or a
+  different driver. This function must match its calls to AllocatePages() with FreePages(),
+  AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+  Since ControllerHandle may have been previously started by the same driver, if a protocol is
+  already in the opened state, then it must not be closed with CloseProtocol(). This is required
+  to guarantee the state of ControllerHandle is not modified by this function.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to test. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For bus drivers, if this parameter is not NULL, then
+                                   the bus driver must determine if the bus controller specified
+                                   by ControllerHandle and the child controller specified
+                                   by RemainingDevicePath are both supported by this
+                                   bus driver.
+
+  @retval EFI_SUCCESS              The device specified by ControllerHandle and
+                                   RemainingDevicePath is supported by the driver specified by This.
+  @retval EFI_ALREADY_STARTED      The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by the driver
+                                   specified by This.
+  @retval EFI_ACCESS_DENIED        The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by a different
+                                   driver or an application that requires exclusive access.
+                                   Currently not implemented.
+  @retval EFI_UNSUPPORTED          The device specified by ControllerHandle and
+                                   RemainingDevicePath is not supported by the driver specified by This.
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL *This,
+  IN EFI_HANDLE                  Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL    *RemainingDevicePath
+  )
+{
+  EFI_STATUS                Status;
+  EFI_DEVICE_PATH_PROTOCOL  *ParentDevicePath;
+  EFI_PCI_IO_PROTOCOL       *PciIo;
+  PCI_TYPE00                PciData;
+
+  PciIo            = NULL;
+  ParentDevicePath = NULL;
+
+  //
+  // SdPciHcDxe is a device driver, and should ingore the
+  // "RemainingDevicePath" according to EFI spec.
+  //
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiDevicePathProtocolGuid,
+                  (VOID *) &ParentDevicePath,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    //
+    // EFI_ALREADY_STARTED is also an error.
+    //
+    return Status;
+  }
+  //
+  // Close the protocol because we don't use it here.
+  //
+  gBS->CloseProtocol (
+        Controller,
+        &gEfiDevicePathProtocolGuid,
+        This->DriverBindingHandle,
+        Controller
+        );
+
+  //
+  // Now test the EfiPciIoProtocol.
+  //
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiPciIoProtocolGuid,
+                  (VOID **) &PciIo,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Now further check the PCI header: Base class (offset 0x08) and
+  // Sub Class (offset 0x05). This controller should be an SD/MMC PCI
+  // Host Controller.
+  //
+  Status = PciIo->Pci.Read (
+                        PciIo,
+                        EfiPciIoWidthUint8,
+                        0,
+                        sizeof (PciData),
+                        &PciData
+                        );
+  if (EFI_ERROR (Status)) {
+    gBS->CloseProtocol (
+          Controller,
+          &gEfiPciIoProtocolGuid,
+          This->DriverBindingHandle,
+          Controller
+          );
+    return EFI_UNSUPPORTED;
+  }
+  //
+  // Since we already got the PciData, we can close protocol to avoid to carry it
+  // on for multiple exit points.
+  //
+  gBS->CloseProtocol (
+        Controller,
+        &gEfiPciIoProtocolGuid,
+        This->DriverBindingHandle,
+        Controller
+        );
+
+  //
+  // Examine SD PCI Host Controller PCI Configuration table fields.
+  //
+  if ((PciData.Hdr.ClassCode[2] == PCI_CLASS_SYSTEM_PERIPHERAL) &&
+      (PciData.Hdr.ClassCode[1] == PCI_SUBCLASS_SD_HOST_CONTROLLER) &&
+      ((PciData.Hdr.ClassCode[0] == 0x00) || (PciData.Hdr.ClassCode[0] == 0x01))) {
+    return EFI_SUCCESS;
+  }
+
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Starts a device controller or a bus controller.
+
+  The Start() function is designed to be invoked from the EFI boot service ConnectController().
+  As a result, much of the error checking on the parameters to Start() has been moved into this
+  common boot service. It is legal to call Start() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE.
+  2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
+     EFI_DEVICE_PATH_PROTOCOL.
+  3. Prior to calling Start(), the Supported() function for the driver specified by This must
+     have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to start. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For a bus driver, if this parameter is NULL, then handles
+                                   for all the children of Controller are created by this driver.
+                                   If this parameter is not NULL and the first Device Path Node is
+                                   not the End of Device Path Node, then only the handle for the
+                                   child device specified by the first Device Path Node of
+                                   RemainingDevicePath is created by this driver.
+                                   If the first Device Path Node of RemainingDevicePath is
+                                   the End of Device Path Node, no child handle is created by this
+                                   driver.
+
+  @retval EFI_SUCCESS              The device was started.
+  @retval EFI_DEVICE_ERROR         The device could not be started due to a device error.Currently not implemented.
+  @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+  @retval Others                   The driver failded to start the device.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN EFI_HANDLE                      Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath
+  )
+{
+  EFI_STATUS                      Status;
+  SD_MMC_HC_PRIVATE_DATA          *Private;
+  EFI_PCI_IO_PROTOCOL             *PciIo;
+  UINT64                          Supports;
+  UINT64                          PciAttributes;
+  UINT8                           Slot;
+  UINT8                           Index;
+  CARD_TYPE_DETECT_ROUTINE        *Routine;
+  UINT32                          RoutineNum;
+  BOOLEAN                         Support64BitDma;
+
+  DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
+
+  //
+  // Open PCI I/O Protocol and save pointer to open protocol
+  // in private data area.
+  //
+  PciIo  = NULL;
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiPciIoProtocolGuid,
+                  (VOID **) &PciIo,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Enable the SD Host Controller MMIO space
+  //
+  Private = NULL;
+  Status  = PciIo->Attributes (
+                     PciIo,
+                     EfiPciIoAttributeOperationGet,
+                     0,
+                     &PciAttributes
+                     );
+
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationSupported,
+                    0,
+                    &Supports
+                    );
+
+  if (!EFI_ERROR (Status)) {
+    Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
+    Status    = PciIo->Attributes (
+                         PciIo,
+                         EfiPciIoAttributeOperationEnable,
+                         Supports,
+                         NULL
+                         );
+  } else {
+    goto Done;
+  }
+
+  Private = AllocateCopyPool (sizeof (SD_MMC_HC_PRIVATE_DATA), &gSdMmcPciHcTemplate);
+  if (Private == NULL) {
+    Status = EFI_OUT_OF_RESOURCES;
+    goto Done;
+  }
+
+  Private->ControllerHandle = Controller;
+  Private->PciIo            = PciIo;
+  Private->PciAttributes    = PciAttributes;
+  InitializeListHead (&Private->Queue);
+
+  Support64BitDma = TRUE;
+
+  //
+  // There is only one slot 0 on Xenon
+  //
+  Slot = 0;
+  Private->Slot[Slot].Enable = TRUE;
+
+  Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Support64BitDma &= Private->Capability[Slot].SysBus64;
+
+  //
+  // Override capabilities structure - only 4 Bit width bus is supported
+  // by HW and also force using SDR25 mode
+  //
+  Private->Capability[Slot].Sdr104 = 0;
+  Private->Capability[Slot].Ddr50 = 0;
+  Private->Capability[Slot].Sdr50 = 0;
+  Private->Capability[Slot].BusWidth8 = 0;
+
+  if (Private->Capability[Slot].BaseClkFreq == 0) {
+    Private->Capability[Slot].BaseClkFreq = 0xff;
+  }
+
+  DumpCapabilityReg (Slot, &Private->Capability[Slot]);
+
+  Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Private->Slot[Slot].SlotType = Private->Capability[Slot].SlotType;
+  if ((Private->Slot[Slot].SlotType != RemovableSlot) && (Private->Slot[Slot].SlotType != EmbeddedSlot)) {
+    DEBUG ((DEBUG_INFO, "SdMmcPciHcDxe doesn't support the slot type [%d]!!!\n", Private->Slot[Slot].SlotType));
+    return EFI_D_ERROR;
+  }
+
+  //
+  // Perform Xenon-specific init sequence
+  //
+  XenonInit (Private);
+
+  //
+  // Initialize HC timeout control
+  //
+  Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Private->Slot[Slot].MediaPresent = TRUE;
+  Private->Slot[Slot].Initialized  = TRUE;
+  RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
+  for (Index = 0; Index < RoutineNum; Index++) {
+    Routine = &mCardTypeDetectRoutineTable[Index];
+    if (*Routine != NULL) {
+      Status = (*Routine) (Private, Slot);
+      if (!EFI_ERROR (Status)) {
+        break;
+      }
+    }
+  }
+  //
+  // This card doesn't get initialized correctly.
+  //
+  if (Index == RoutineNum) {
+    Private->Slot[Slot].Initialized = FALSE;
+  }
+
+  //
+  // Enable 64-bit DMA support in the PCI layer if this controller
+  // supports it.
+  //
+  if (Support64BitDma) {
+    Status = PciIo->Attributes (
+                      PciIo,
+                      EfiPciIoAttributeOperationEnable,
+                      EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
+                      NULL
+                      );
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_WARN, "SdMmcPciHcDriverBindingStart: failed to enable 64-bit DMA (%r)\n", Status));
+    }
+  }
+
+  //
+  // Start the asynchronous I/O monitor
+  //
+  Status = gBS->CreateEvent (
+                  EVT_TIMER | EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  ProcessAsyncTaskList,
+                  Private,
+                  &Private->TimerEvent
+                  );
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, SD_MMC_HC_ASYNC_TIMER);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  //
+  // Start the Sd removable device connection enumeration
+  //
+  Status = gBS->CreateEvent (
+                  EVT_TIMER | EVT_NOTIFY_SIGNAL,
+                  TPL_CALLBACK,
+                  SdMmcPciHcEnumerateDevice,
+                  Private,
+                  &Private->ConnectEvent
+                  );
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = gBS->SetTimer (Private->ConnectEvent, TimerPeriodic, SD_MMC_HC_ENUM_TIMER);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Controller,
+                  &gEfiSdMmcPassThruProtocolGuid,
+                  &(Private->PassThru),
+                  NULL
+                  );
+
+  DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: %r End on %x\n", Status, Controller));
+
+Done:
+  if (EFI_ERROR (Status)) {
+    if ((Private != NULL) && (Private->PciAttributes != 0)) {
+      //
+      // Restore original PCI attributes
+      //
+      PciIo->Attributes (
+               PciIo,
+               EfiPciIoAttributeOperationSet,
+               Private->PciAttributes,
+               NULL
+               );
+    }
+    gBS->CloseProtocol (
+          Controller,
+          &gEfiPciIoProtocolGuid,
+          This->DriverBindingHandle,
+          Controller
+          );
+
+    if ((Private != NULL) && (Private->TimerEvent != NULL)) {
+      gBS->CloseEvent (Private->TimerEvent);
+    }
+
+    if ((Private != NULL) && (Private->ConnectEvent != NULL)) {
+      gBS->CloseEvent (Private->ConnectEvent);
+    }
+
+    if (Private != NULL) {
+      FreePool (Private);
+    }
+  }
+
+  return Status;
+}
+
+/**
+  Stops a device controller or a bus controller.
+
+  The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+  As a result, much of the error checking on the parameters to Stop() has been moved
+  into this common boot service. It is legal to call Stop() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
+     same driver's Start() function.
+  2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
+     EFI_HANDLE. In addition, all of these handles must have been created in this driver's
+     Start() function, and the Start() function must have called OpenProtocol() on
+     ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+  @param[in]  This              A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle  A handle to the device being stopped. The handle must
+                                support a bus specific I/O protocol for the driver
+                                to use to stop the device.
+  @param[in]  NumberOfChildren  The number of child device handles in ChildHandleBuffer.
+  @param[in]  ChildHandleBuffer An array of child handles to be freed. May be NULL
+                                if NumberOfChildren is 0.
+
+  @retval EFI_SUCCESS           The device was stopped.
+  @retval EFI_DEVICE_ERROR      The device could not be stopped due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN  EFI_HANDLE                      Controller,
+  IN  UINTN                           NumberOfChildren,
+  IN  EFI_HANDLE                      *ChildHandleBuffer
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_PROTOCOL       *PassThru;
+  SD_MMC_HC_PRIVATE_DATA              *Private;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+  LIST_ENTRY                          *Link;
+  LIST_ENTRY                          *NextLink;
+  SD_MMC_HC_TRB                       *Trb;
+
+  DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStop: Start\n"));
+
+  Status = gBS->OpenProtocol (
+                  Controller,
+                  &gEfiSdMmcPassThruProtocolGuid,
+                  (VOID**) &PassThru,
+                  This->DriverBindingHandle,
+                  Controller,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  //
+  // Close Non-Blocking timer and free Task list.
+  //
+  if (Private->TimerEvent != NULL) {
+    gBS->CloseEvent (Private->TimerEvent);
+    Private->TimerEvent = NULL;
+  }
+  if (Private->ConnectEvent != NULL) {
+    gBS->CloseEvent (Private->ConnectEvent);
+    Private->ConnectEvent = NULL;
+  }
+  //
+  // As the timer is closed, there is no needs to use TPL lock to
+  // protect the critical region "queue".
+  //
+  for (Link = GetFirstNode (&Private->Queue);
+       !IsNull (&Private->Queue, Link);
+       Link = NextLink) {
+    NextLink = GetNextNode (&Private->Queue, Link);
+    RemoveEntryList (Link);
+    Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
+    Trb->Packet->TransactionStatus = EFI_ABORTED;
+    gBS->SignalEvent (Trb->Event);
+    SdMmcFreeTrb (Trb);
+  }
+
+  //
+  // Uninstall Block I/O protocol from the device handle
+  //
+  Status = gBS->UninstallProtocolInterface (
+                  Controller,
+                  &gEfiSdMmcPassThruProtocolGuid,
+                  &(Private->PassThru)
+                  );
+
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  gBS->CloseProtocol (
+         Controller,
+         &gEfiPciIoProtocolGuid,
+         This->DriverBindingHandle,
+         Controller
+         );
+  //
+  // Restore original PCI attributes
+  //
+  PciIo  = Private->PciIo;
+  Status = PciIo->Attributes (
+                    PciIo,
+                    EfiPciIoAttributeOperationSet,
+                    Private->PciAttributes,
+                    NULL
+                    );
+  ASSERT_EFI_ERROR (Status);
+
+  FreePool (Private);
+
+  DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStop: End with %r\n", Status));
+
+  return Status;
+}
+
+/**
+  Sends SD command to an SD card that is attached to the SD controller.
+
+  The PassThru() function sends the SD command specified by Packet to the SD card
+  specified by Slot.
+
+  If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.
+
+  If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
+
+  If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER
+  is returned.
+
+  If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
+  EFI_INVALID_PARAMETER is returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]     Slot           The slot number of the SD card to send the command to.
+  @param[in,out] Packet         A pointer to the SD command data structure.
+  @param[in]     Event          If Event is NULL, blocking I/O is performed. If Event is
+                                not NULL, then nonblocking I/O is performed, and Event
+                                will be signaled when the Packet completes.
+
+  @retval EFI_SUCCESS           The SD Command Packet was sent by the host.
+  @retval EFI_DEVICE_ERROR      A device error occurred while attempting to send the SD
+                                command Packet.
+  @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
+  @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
+                                OutDataBuffer are NULL.
+  @retval EFI_NO_MEDIA          SD Device not present in the Slot.
+  @retval EFI_UNSUPPORTED       The command described by the SD Command Packet is not
+                                supported by the host controller.
+  @retval EFI_BAD_BUFFER_SIZE   The InTransferLength or OutTransferLength exceeds the
+                                limit supported by SD card ( i.e. if the number of bytes
+                                exceed the Last LBA).
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruPassThru (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL         *This,
+  IN     UINT8                                 Slot,
+  IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   *Packet,
+  IN     EFI_EVENT                             Event    OPTIONAL
+  )
+{
+  EFI_STATUS                      Status;
+  SD_MMC_HC_PRIVATE_DATA          *Private;
+  SD_MMC_HC_TRB                   *Trb;
+  EFI_TPL                         OldTpl;
+
+  if ((This == NULL) || (Packet == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  if (!Private->Slot[Slot].Enable) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (!Private->Slot[Slot].MediaPresent) {
+    return EFI_NO_MEDIA;
+  }
+
+  if (!Private->Slot[Slot].Initialized) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  Trb = SdMmcCreateTrb (Private, Slot, Packet, Event);
+  if (Trb == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  //
+  // Immediately return for async I/O.
+  //
+  if (Event != NULL) {
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Wait async I/O list is empty before execute sync I/O operation.
+  //
+  while (TRUE) {
+    OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+    if (IsListEmpty (&Private->Queue)) {
+      gBS->RestoreTPL (OldTpl);
+      break;
+    }
+    gBS->RestoreTPL (OldTpl);
+  }
+
+  Status = SdMmcWaitTrbEnv (Private, Trb);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = SdMmcExecTrb (Private, Trb);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+  Status = SdMmcWaitTrbResult (Private, Trb);
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+
+Done:
+  if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
+    FreePages (Trb->AdmaDesc, Trb->AdmaPages);
+  }
+
+  if (Trb != NULL) {
+    FreePool (Trb);
+  }
+
+  return Status;
+}
+
+/**
+  Used to retrieve next slot numbers supported by the SD controller. The function
+  returns information about all available slots (populated or not-populated).
+
+  The GetNextSlot() function retrieves the next slot number on an SD controller.
+  If on input Slot is 0xFF, then the slot number of the first slot on the SD controller
+  is returned.
+
+  If Slot is a slot number that was returned on a previous call to GetNextSlot(), then
+  the slot number of the next slot on the SD controller is returned.
+
+  If Slot is not 0xFF and Slot was not returned on a previous call to GetNextSlot(),
+  EFI_INVALID_PARAMETER is returned.
+
+  If Slot is the slot number of the last slot on the SD controller, then EFI_NOT_FOUND
+  is returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
+  @param[in,out] Slot           On input, a pointer to a slot number on the SD controller.
+                                On output, a pointer to the next slot number on the SD controller.
+                                An input value of 0xFF retrieves the first slot number on the SD
+                                controller.
+
+  @retval EFI_SUCCESS           The next slot number on the SD controller was returned in Slot.
+  @retval EFI_NOT_FOUND         There are no more slots on this SD controller.
+  @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a previous call
+                                to GetNextSlot().
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruGetNextSlot (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL        *This,
+  IN OUT UINT8                                *Slot
+  )
+{
+  SD_MMC_HC_PRIVATE_DATA          *Private;
+  UINT8                           Index;
+
+  if ((This == NULL) || (Slot == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  if (*Slot == 0xFF) {
+    for (Index = 0; Index < SD_MMC_HC_MAX_SLOT; Index++) {
+      if (Private->Slot[Index].Enable) {
+        *Slot = Index;
+        Private->PreviousSlot = Index;
+        return EFI_SUCCESS;
+      }
+    }
+    return EFI_NOT_FOUND;
+  } else if (*Slot == Private->PreviousSlot) {
+    for (Index = *Slot + 1; Index < SD_MMC_HC_MAX_SLOT; Index++) {
+      if (Private->Slot[Index].Enable) {
+        *Slot = Index;
+        Private->PreviousSlot = Index;
+        return EFI_SUCCESS;
+      }
+    }
+    return EFI_NOT_FOUND;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+}
+
+/**
+  Used to allocate and build a device path node for an SD card on the SD controller.
+
+  The BuildDevicePath() function allocates and builds a single device node for the SD
+  card specified by Slot.
+
+  If the SD card specified by Slot is not present on the SD controller, then EFI_NOT_FOUND
+  is returned.
+
+  If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
+
+  If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES
+  is returned.
+
+  Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of
+  DevicePath are initialized to describe the SD card specified by Slot, and EFI_SUCCESS is
+  returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
+  @param[in]     Slot           Specifies the slot number of the SD card for which a device
+                                path node is to be allocated and built.
+  @param[in,out] DevicePath     A pointer to a single device path node that describes the SD
+                                card specified by Slot. This function is responsible for
+                                allocating the buffer DevicePath with the boot service
+                                AllocatePool(). It is the caller's responsibility to free
+                                DevicePath when the caller is finished with DevicePath.
+
+  @retval EFI_SUCCESS           The device path node that describes the SD card specified by
+                                Slot was allocated and returned in DevicePath.
+  @retval EFI_NOT_FOUND         The SD card specified by Slot does not exist on the SD controller.
+  @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to allocate DevicePath.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruBuildDevicePath (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL       *This,
+  IN     UINT8                               Slot,
+  IN OUT EFI_DEVICE_PATH_PROTOCOL            **DevicePath
+  )
+{
+  SD_MMC_HC_PRIVATE_DATA          *Private;
+  SD_DEVICE_PATH                  *SdNode;
+  EMMC_DEVICE_PATH                *EmmcNode;
+
+  if ((This == NULL) || (DevicePath == NULL) || (Slot >= SD_MMC_HC_MAX_SLOT)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  if ((!Private->Slot[Slot].Enable) || (!Private->Slot[Slot].MediaPresent)) {
+    return EFI_NOT_FOUND;
+  }
+
+  if (Private->Slot[Slot].CardType == SdCardType) {
+    SdNode = AllocateCopyPool (sizeof (SD_DEVICE_PATH), &mSdDpTemplate);
+    if (SdNode == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    SdNode->SlotNumber = Slot;
+
+    *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) SdNode;
+  } else if (Private->Slot[Slot].CardType == EmmcCardType) {
+    EmmcNode = AllocateCopyPool (sizeof (EMMC_DEVICE_PATH), &mEmmcDpTemplate);
+    if (EmmcNode == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+    EmmcNode->SlotNumber = Slot;
+
+    *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) EmmcNode;
+  } else {
+    //
+    // Currently we only support SD and EMMC two device nodes.
+    //
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function retrieves an SD card slot number based on the input device path.
+
+  The GetSlotNumber() function retrieves slot number for the SD card specified by
+  the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is returned.
+
+  If DevicePath is not a device path node type that the SD Pass Thru driver supports,
+  EFI_UNSUPPORTED is returned.
+
+  @param[in]  This              A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  DevicePath        A pointer to the device path node that describes a SD
+                                card on the SD controller.
+  @param[out] Slot              On return, points to the slot number of an SD card on
+                                the SD controller.
+
+  @retval EFI_SUCCESS           SD card slot number is returned in Slot.
+  @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL.
+  @retval EFI_UNSUPPORTED       DevicePath is not a device path node type that the SD
+                                Pass Thru driver supports.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruGetSlotNumber (
+  IN  EFI_SD_MMC_PASS_THRU_PROTOCOL          *This,
+  IN  EFI_DEVICE_PATH_PROTOCOL               *DevicePath,
+  OUT UINT8                                  *Slot
+  )
+{
+  SD_MMC_HC_PRIVATE_DATA          *Private;
+  SD_DEVICE_PATH                  *SdNode;
+  EMMC_DEVICE_PATH                *EmmcNode;
+  UINT8                           SlotNumber;
+
+  if ((This == NULL) || (DevicePath == NULL) || (Slot == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  //
+  // Check whether the DevicePath belongs to SD_DEVICE_PATH or EMMC_DEVICE_PATH
+  //
+  if ((DevicePath->Type != MESSAGING_DEVICE_PATH) ||
+      ((DevicePath->SubType != MSG_SD_DP) &&
+       (DevicePath->SubType != MSG_EMMC_DP)) ||
+      (DevicePathNodeLength(DevicePath) != sizeof(SD_DEVICE_PATH)) ||
+      (DevicePathNodeLength(DevicePath) != sizeof(EMMC_DEVICE_PATH))) {
+    return EFI_UNSUPPORTED;
+  }
+
+  if (DevicePath->SubType == MSG_SD_DP) {
+    SdNode = (SD_DEVICE_PATH *) DevicePath;
+    SlotNumber = SdNode->SlotNumber;
+  } else {
+    EmmcNode = (EMMC_DEVICE_PATH *) DevicePath;
+    SlotNumber = EmmcNode->SlotNumber;
+  }
+
+  if (SlotNumber >= SD_MMC_HC_MAX_SLOT) {
+    return EFI_NOT_FOUND;
+  }
+
+  if (Private->Slot[SlotNumber].Enable) {
+    *Slot = SlotNumber;
+    return EFI_SUCCESS;
+  } else {
+    return EFI_NOT_FOUND;
+  }
+}
+
+/**
+  Resets an SD card that is connected to the SD controller.
+
+  The ResetDevice() function resets the SD card specified by Slot.
+
+  If this SD controller does not support a device reset operation, EFI_UNSUPPORTED is
+  returned.
+
+  If Slot is not in a valid slot number for this SD controller, EFI_INVALID_PARAMETER
+  is returned.
+
+  If the device reset operation is completed, EFI_SUCCESS is returned.
+
+  @param[in]  This              A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot              Specifies the slot number of the SD card to be reset.
+
+  @retval EFI_SUCCESS           The SD card specified by Slot was reset.
+  @retval EFI_UNSUPPORTED       The SD controller does not support a device reset operation.
+  @retval EFI_INVALID_PARAMETER Slot number is invalid.
+  @retval EFI_NO_MEDIA          SD Device not present in the Slot.
+  @retval EFI_DEVICE_ERROR      The reset command failed due to a device error
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruResetDevice (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL           *This,
+  IN UINT8                                   Slot
+  )
+{
+  SD_MMC_HC_PRIVATE_DATA          *Private;
+  LIST_ENTRY                      *Link;
+  LIST_ENTRY                      *NextLink;
+  SD_MMC_HC_TRB                   *Trb;
+  EFI_TPL                         OldTpl;
+
+  if (This == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Private = SD_MMC_HC_PRIVATE_FROM_THIS (This);
+
+  if (!Private->Slot[Slot].Enable) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (!Private->Slot[Slot].MediaPresent) {
+    return EFI_NO_MEDIA;
+  }
+
+  if (!Private->Slot[Slot].Initialized) {
+    return EFI_DEVICE_ERROR;
+  }
+  //
+  // Free all async I/O requests in the queue
+  //
+  OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+
+  for (Link = GetFirstNode (&Private->Queue);
+       !IsNull (&Private->Queue, Link);
+       Link = NextLink) {
+    NextLink = GetNextNode (&Private->Queue, Link);
+    RemoveEntryList (Link);
+    Trb = SD_MMC_HC_TRB_FROM_THIS (Link);
+    Trb->Packet->TransactionStatus = EFI_ABORTED;
+    gBS->SignalEvent (Trb->Event);
+    SdMmcFreeTrb (Trb);
+  }
+
+  gBS->RestoreTPL (OldTpl);
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h
new file mode 100644
index 0000000..6a2a279
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h
@@ -0,0 +1,785 @@
+/** @file
+
+  Provides some data structure definitions used by the SD/MMC host controller driver.
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SD_MMC_PCI_HC_DXE_H_
+#define _SD_MMC_PCI_HC_DXE_H_
+
+#include <Uefi.h>
+
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/Emmc.h>
+#include <IndustryStandard/Sd.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DevicePathLib.h>
+
+#include <Protocol/DevicePath.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/DriverBinding.h>
+#include <Protocol/ComponentName.h>
+#include <Protocol/ComponentName2.h>
+#include <Protocol/SdMmcPassThru.h>
+
+#include "SdMmcPciHci.h"
+
+extern EFI_COMPONENT_NAME_PROTOCOL  gSdMmcPciHcComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gSdMmcPciHcComponentName2;
+extern EFI_DRIVER_BINDING_PROTOCOL  gSdMmcPciHcDriverBinding;
+
+#define SD_MMC_HC_PRIVATE_SIGNATURE  SIGNATURE_32 ('s', 'd', 't', 'f')
+
+#define SD_MMC_HC_PRIVATE_FROM_THIS(a) \
+    CR(a, SD_MMC_HC_PRIVATE_DATA, PassThru, SD_MMC_HC_PRIVATE_SIGNATURE)
+
+//
+// Generic time out value, 1 microsecond as unit.
+//
+#define SD_MMC_HC_GENERIC_TIMEOUT     1 * 1000 * 1000
+
+//
+// SD/MMC async transfer timer interval, set by experience.
+// The unit is 100us, takes 1ms as interval.
+//
+#define SD_MMC_HC_ASYNC_TIMER   EFI_TIMER_PERIOD_MILLISECONDS(1)
+//
+// SD/MMC removable device enumeration timer interval, set by experience.
+// The unit is 100us, takes 100ms as interval.
+//
+#define SD_MMC_HC_ENUM_TIMER    EFI_TIMER_PERIOD_MILLISECONDS(100)
+
+typedef enum {
+  UnknownCardType,
+  SdCardType,
+  SdioCardType,
+  MmcCardType,
+  EmmcCardType
+} SD_MMC_CARD_TYPE;
+
+typedef enum {
+  RemovableSlot,
+  EmbeddedSlot,
+  SharedBusSlot,
+  UnknownSlot
+} EFI_SD_MMC_SLOT_TYPE;
+
+typedef struct {
+  BOOLEAN                           Enable;
+  EFI_SD_MMC_SLOT_TYPE              SlotType;
+  BOOLEAN                           MediaPresent;
+  BOOLEAN                           Initialized;
+  SD_MMC_CARD_TYPE                  CardType;
+} SD_MMC_HC_SLOT;
+
+typedef struct {
+  UINTN                               Signature;
+
+  EFI_HANDLE                          ControllerHandle;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+
+  EFI_SD_MMC_PASS_THRU_PROTOCOL       PassThru;
+
+  UINT64                              PciAttributes;
+  //
+  // The field is used to record the previous slot in GetNextSlot().
+  //
+  UINT8                               PreviousSlot;
+  //
+  // For Non-blocking operation.
+  //
+  EFI_EVENT                           TimerEvent;
+  //
+  // For Sd removable device enumeration.
+  //
+  EFI_EVENT                           ConnectEvent;
+  LIST_ENTRY                          Queue;
+
+  SD_MMC_HC_SLOT                      Slot[SD_MMC_HC_MAX_SLOT];
+  SD_MMC_HC_SLOT_CAP                  Capability[SD_MMC_HC_MAX_SLOT];
+  UINT64                              MaxCurrent[SD_MMC_HC_MAX_SLOT];
+
+  UINT32                              ControllerVersion;
+} SD_MMC_HC_PRIVATE_DATA;
+
+#define SD_MMC_HC_TRB_SIG             SIGNATURE_32 ('T', 'R', 'B', 'T')
+
+//
+// TRB (Transfer Request Block) contains information for the cmd request.
+//
+typedef struct {
+  UINT32                              Signature;
+  LIST_ENTRY                          TrbList;
+
+  UINT8                               Slot;
+  UINT16                              BlockSize;
+
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  VOID                                *Data;
+  UINT32                              DataLen;
+  BOOLEAN                             Read;
+  EFI_PHYSICAL_ADDRESS                DataPhy;
+  VOID                                *DataMap;
+  SD_MMC_HC_TRANSFER_MODE             Mode;
+
+  EFI_EVENT                           Event;
+  BOOLEAN                             Started;
+  UINT64                              Timeout;
+
+  SD_MMC_HC_ADMA_DESC_LINE            *AdmaDesc;
+  EFI_PHYSICAL_ADDRESS                AdmaDescPhy;
+  VOID                                *AdmaMap;
+  UINT32                              AdmaPages;
+
+  SD_MMC_HC_PRIVATE_DATA              *Private;
+} SD_MMC_HC_TRB;
+
+#define SD_MMC_HC_TRB_FROM_THIS(a) \
+    CR(a, SD_MMC_HC_TRB, TrbList, SD_MMC_HC_TRB_SIG)
+
+//
+// Task for Non-blocking mode.
+//
+typedef struct {
+  UINT32                              Signature;
+  LIST_ENTRY                          Link;
+
+  UINT8                               Slot;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  BOOLEAN                             IsStart;
+  EFI_EVENT                           Event;
+  UINT64                              RetryTimes;
+  BOOLEAN                             InfiniteWait;
+  VOID                                *Map;
+  VOID                                *MapAddress;
+} SD_MMC_HC_QUEUE;
+
+//
+// Prototypes
+//
+/**
+  Execute card identification procedure.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The card is identified correctly.
+  @retval Others            The card can't be identified.
+
+**/
+typedef
+EFI_STATUS
+(*CARD_TYPE_DETECT_ROUTINE) (
+  IN SD_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  );
+
+/**
+  Sends SD command to an SD card that is attached to the SD controller.
+
+  The PassThru() function sends the SD command specified by Packet to the SD card
+  specified by Slot.
+
+  If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.
+
+  If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
+
+  If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER
+  is returned.
+
+  If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
+  EFI_INVALID_PARAMETER is returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]     Slot           The slot number of the SD card to send the command to.
+  @param[in,out] Packet         A pointer to the SD command data structure.
+  @param[in]     Event          If Event is NULL, blocking I/O is performed. If Event is
+                                not NULL, then nonblocking I/O is performed, and Event
+                                will be signaled when the Packet completes.
+
+  @retval EFI_SUCCESS           The SD Command Packet was sent by the host.
+  @retval EFI_DEVICE_ERROR      A device error occurred while attempting to send the SD
+                                command Packet.
+  @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
+  @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
+                                OutDataBuffer are NULL.
+  @retval EFI_NO_MEDIA          SD Device not present in the Slot.
+  @retval EFI_UNSUPPORTED       The command described by the SD Command Packet is not
+                                supported by the host controller.
+  @retval EFI_BAD_BUFFER_SIZE   The InTransferLength or OutTransferLength exceeds the
+                                limit supported by SD card ( i.e. if the number of bytes
+                                exceed the Last LBA).
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruPassThru (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL         *This,
+  IN     UINT8                                 Slot,
+  IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET   *Packet,
+  IN     EFI_EVENT                             Event    OPTIONAL
+  );
+
+/**
+  Used to retrieve next slot numbers supported by the SD controller. The function
+  returns information about all available slots (populated or not-populated).
+
+  The GetNextSlot() function retrieves the next slot number on an SD controller.
+  If on input Slot is 0xFF, then the slot number of the first slot on the SD controller
+  is returned.
+
+  If Slot is a slot number that was returned on a previous call to GetNextSlot(), then
+  the slot number of the next slot on the SD controller is returned.
+
+  If Slot is not 0xFF and Slot was not returned on a previous call to GetNextSlot(),
+  EFI_INVALID_PARAMETER is returned.
+
+  If Slot is the slot number of the last slot on the SD controller, then EFI_NOT_FOUND
+  is returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
+  @param[in,out] Slot           On input, a pointer to a slot number on the SD controller.
+                                On output, a pointer to the next slot number on the SD controller.
+                                An input value of 0xFF retrieves the first slot number on the SD
+                                controller.
+
+  @retval EFI_SUCCESS           The next slot number on the SD controller was returned in Slot.
+  @retval EFI_NOT_FOUND         There are no more slots on this SD controller.
+  @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a previous call
+                                to GetNextSlot().
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruGetNextSlot (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL        *This,
+  IN OUT UINT8                                *Slot
+  );
+
+/**
+  Used to allocate and build a device path node for an SD card on the SD controller.
+
+  The BuildDevicePath() function allocates and builds a single device node for the SD
+  card specified by Slot.
+
+  If the SD card specified by Slot is not present on the SD controller, then EFI_NOT_FOUND
+  is returned.
+
+  If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
+
+  If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES
+  is returned.
+
+  Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of
+  DevicePath are initialized to describe the SD card specified by Slot, and EFI_SUCCESS is
+  returned.
+
+  @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
+  @param[in]     Slot           Specifies the slot number of the SD card for which a device
+                                path node is to be allocated and built.
+  @param[in,out] DevicePath     A pointer to a single device path node that describes the SD
+                                card specified by Slot. This function is responsible for
+                                allocating the buffer DevicePath with the boot service
+                                AllocatePool(). It is the caller's responsibility to free
+                                DevicePath when the caller is finished with DevicePath.
+
+  @retval EFI_SUCCESS           The device path node that describes the SD card specified by
+                                Slot was allocated and returned in DevicePath.
+  @retval EFI_NOT_FOUND         The SD card specified by Slot does not exist on the SD controller.
+  @retval EFI_INVALID_PARAMETER DevicePath is NULL.
+  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to allocate DevicePath.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruBuildDevicePath (
+  IN     EFI_SD_MMC_PASS_THRU_PROTOCOL       *This,
+  IN     UINT8                               Slot,
+  IN OUT EFI_DEVICE_PATH_PROTOCOL            **DevicePath
+  );
+
+/**
+  This function retrieves an SD card slot number based on the input device path.
+
+  The GetSlotNumber() function retrieves slot number for the SD card specified by
+  the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is returned.
+
+  If DevicePath is not a device path node type that the SD Pass Thru driver supports,
+  EFI_UNSUPPORTED is returned.
+
+  @param[in]  This              A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  DevicePath        A pointer to the device path node that describes a SD
+                                card on the SD controller.
+  @param[out] Slot              On return, points to the slot number of an SD card on
+                                the SD controller.
+
+  @retval EFI_SUCCESS           SD card slot number is returned in Slot.
+  @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL.
+  @retval EFI_UNSUPPORTED       DevicePath is not a device path node type that the SD
+                                Pass Thru driver supports.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruGetSlotNumber (
+  IN  EFI_SD_MMC_PASS_THRU_PROTOCOL          *This,
+  IN  EFI_DEVICE_PATH_PROTOCOL               *DevicePath,
+  OUT UINT8                                  *Slot
+  );
+
+/**
+  Resets an SD card that is connected to the SD controller.
+
+  The ResetDevice() function resets the SD card specified by Slot.
+
+  If this SD controller does not support a device reset operation, EFI_UNSUPPORTED is
+  returned.
+
+  If Slot is not in a valid slot number for this SD controller, EFI_INVALID_PARAMETER
+  is returned.
+
+  If the device reset operation is completed, EFI_SUCCESS is returned.
+
+  @param[in]  This              A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in]  Slot              Specifies the slot number of the SD card to be reset.
+
+  @retval EFI_SUCCESS           The SD card specified by Slot was reset.
+  @retval EFI_UNSUPPORTED       The SD controller does not support a device reset operation.
+  @retval EFI_INVALID_PARAMETER Slot number is invalid.
+  @retval EFI_NO_MEDIA          SD Device not present in the Slot.
+  @retval EFI_DEVICE_ERROR      The reset command failed due to a device error
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPassThruResetDevice (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL           *This,
+  IN UINT8                                   Slot
+  );
+
+//
+// Driver model protocol interfaces
+//
+/**
+  Tests to see if this driver supports a given controller. If a child device is provided,
+  it further tests to see if this driver supports creating a handle for the specified child device.
+
+  This function checks to see if the driver specified by This supports the device specified by
+  ControllerHandle. Drivers will typically use the device path attached to
+  ControllerHandle and/or the services from the bus I/O abstraction attached to
+  ControllerHandle to determine if the driver supports ControllerHandle. This function
+  may be called many times during platform initialization. In order to reduce boot times, the tests
+  performed by this function must be very small, and take as little time as possible to execute. This
+  function must not change the state of any hardware devices, and this function must be aware that the
+  device specified by ControllerHandle may already be managed by the same driver or a
+  different driver. This function must match its calls to AllocatePages() with FreePages(),
+  AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+  Since ControllerHandle may have been previously started by the same driver, if a protocol is
+  already in the opened state, then it must not be closed with CloseProtocol(). This is required
+  to guarantee the state of ControllerHandle is not modified by this function.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to test. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For bus drivers, if this parameter is not NULL, then
+                                   the bus driver must determine if the bus controller specified
+                                   by ControllerHandle and the child controller specified
+                                   by RemainingDevicePath are both supported by this
+                                   bus driver.
+
+  @retval EFI_SUCCESS              The device specified by ControllerHandle and
+                                   RemainingDevicePath is supported by the driver specified by This.
+  @retval EFI_ALREADY_STARTED      The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by the driver
+                                   specified by This.
+  @retval EFI_ACCESS_DENIED        The device specified by ControllerHandle and
+                                   RemainingDevicePath is already being managed by a different
+                                   driver or an application that requires exclusive access.
+                                   Currently not implemented.
+  @retval EFI_UNSUPPORTED          The device specified by ControllerHandle and
+                                   RemainingDevicePath is not supported by the driver specified by This.
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcDriverBindingSupported (
+  IN EFI_DRIVER_BINDING_PROTOCOL *This,
+  IN EFI_HANDLE                  Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL    *RemainingDevicePath
+  );
+
+/**
+  Starts a device controller or a bus controller.
+
+  The Start() function is designed to be invoked from the EFI boot service ConnectController().
+  As a result, much of the error checking on the parameters to Start() has been moved into this
+  common boot service. It is legal to call Start() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE.
+  2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
+     EFI_DEVICE_PATH_PROTOCOL.
+  3. Prior to calling Start(), the Supported() function for the driver specified by This must
+     have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
+
+  @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle     The handle of the controller to start. This handle
+                                   must support a protocol interface that supplies
+                                   an I/O abstraction to the driver.
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For a bus driver, if this parameter is NULL, then handles
+                                   for all the children of Controller are created by this driver.
+                                   If this parameter is not NULL and the first Device Path Node is
+                                   not the End of Device Path Node, then only the handle for the
+                                   child device specified by the first Device Path Node of
+                                   RemainingDevicePath is created by this driver.
+                                   If the first Device Path Node of RemainingDevicePath is
+                                   the End of Device Path Node, no child handle is created by this
+                                   driver.
+
+  @retval EFI_SUCCESS              The device was started.
+  @retval EFI_DEVICE_ERROR         The device could not be started due to a device error.Currently not implemented.
+  @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.
+  @retval Others                   The driver failded to start the device.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcDriverBindingStart (
+  IN EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN EFI_HANDLE                      Controller,
+  IN EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath
+  );
+
+/**
+  Stops a device controller or a bus controller.
+
+  The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+  As a result, much of the error checking on the parameters to Stop() has been moved
+  into this common boot service. It is legal to call Stop() from other locations,
+  but the following calling restrictions must be followed or the system behavior will not be deterministic.
+  1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
+     same driver's Start() function.
+  2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid
+     EFI_HANDLE. In addition, all of these handles must have been created in this driver's
+     Start() function, and the Start() function must have called OpenProtocol() on
+     ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
+
+  @param[in]  This              A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
+  @param[in]  ControllerHandle  A handle to the device being stopped. The handle must
+                                support a bus specific I/O protocol for the driver
+                                to use to stop the device.
+  @param[in]  NumberOfChildren  The number of child device handles in ChildHandleBuffer.
+  @param[in]  ChildHandleBuffer An array of child handles to be freed. May be NULL
+                                if NumberOfChildren is 0.
+
+  @retval EFI_SUCCESS           The device was stopped.
+  @retval EFI_DEVICE_ERROR      The device could not be stopped due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcDriverBindingStop (
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,
+  IN  EFI_HANDLE                      Controller,
+  IN  UINTN                           NumberOfChildren,
+  IN  EFI_HANDLE                      *ChildHandleBuffer
+  );
+
+//
+// EFI Component Name Functions
+//
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language. This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified
+                                in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]       A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                driver specified by This in the language
+                                specified by Language.
+
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by
+                                This and the language specified by Language was
+                                returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL     *This,
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **DriverName
+  );
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified by
+  Language, then a pointer to the controller name is returned in ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+                                EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  ControllerHandle[in]  The handle of a controller that the driver
+                                specified by This is managing.  This handle
+                                specifies the controller whose name is to be
+                                returned.
+
+  @param  ChildHandle[in]       The handle of the child controller to retrieve
+                                the name of.  This is an optional parameter that
+                                may be NULL.  It will be NULL for device
+                                drivers.  It will also be NULL for a bus drivers
+                                that wish to retrieve the name of the bus
+                                controller.  It will not be NULL for a bus
+                                driver that wishes to retrieve the name of a
+                                child controller.
+
+  @param  Language[in]          A pointer to a Null-terminated ASCII string
+                                array indicating the language.  This is the
+                                language of the driver name that the caller is
+                                requesting, and it must match one of the
+                                languages specified in SupportedLanguages. The
+                                number of languages supported by a driver is up
+                                to the driver writer. Language is specified in
+                                RFC 4646 or ISO 639-2 language code format.
+
+  @param  ControllerName[out]   A pointer to the Unicode string to return.
+                                This Unicode string is the name of the
+                                controller specified by ControllerHandle and
+                                ChildHandle in the language specified by
+                                Language from the point of view of the driver
+                                specified by This.
+
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in
+                                the language specified by Language for the
+                                driver specified by This was returned in
+                                DriverName.
+
+  @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+                                EFI_HANDLE.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by
+                                ControllerHandle and ChildHandle.
+
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support
+                                the language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcPciHcComponentNameGetControllerName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL     *This,
+  IN  EFI_HANDLE                      ControllerHandle,
+  IN  EFI_HANDLE                      ChildHandle, OPTIONAL
+  IN  CHAR8                           *Language,
+  OUT CHAR16                          **ControllerName
+  );
+
+/**
+  Create a new TRB for the SD/MMC cmd request.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Packet         A pointer to the SD command data structure.
+  @param[in] Event          If Event is NULL, blocking I/O is performed. If Event is
+                            not NULL, then nonblocking I/O is performed, and Event
+                            will be signaled when the Packet completes.
+
+  @return Created Trb or NULL.
+
+**/
+SD_MMC_HC_TRB *
+SdMmcCreateTrb (
+  IN SD_MMC_HC_PRIVATE_DATA              *Private,
+  IN UINT8                               Slot,
+  IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
+  IN EFI_EVENT                           Event
+  );
+
+/**
+  Free the resource used by the TRB.
+
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+**/
+VOID
+SdMmcFreeTrb (
+  IN SD_MMC_HC_TRB           *Trb
+  );
+
+/**
+  Check if the env is ready for execute specified TRB.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The env is ready for TRB execution.
+  @retval EFI_NOT_READY     The env is not ready for TRB execution.
+  @retval Others            Some erros happen.
+
+**/
+EFI_STATUS
+SdMmcCheckTrbEnv (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Wait for the env to be ready for execute specified TRB.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The env is ready for TRB execution.
+  @retval EFI_TIMEOUT       The env is not ready for TRB execution in time.
+  @retval Others            Some erros happen.
+
+**/
+EFI_STATUS
+SdMmcWaitTrbEnv (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Execute the specified TRB.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is sent to host controller successfully.
+  @retval Others            Some erros happen when sending this request to the host controller.
+
+**/
+EFI_STATUS
+SdMmcExecTrb (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Check the TRB execution result.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is executed successfully.
+  @retval EFI_NOT_READY     The TRB is not completed for execution.
+  @retval Others            Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+SdMmcCheckTrbResult (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Wait for the TRB execution result.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is executed successfully.
+  @retval Others            Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+SdMmcWaitTrbResult (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  );
+
+/**
+  Execute EMMC device identification procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       There is a EMMC card.
+  @retval Others            There is not a EMMC card.
+
+**/
+EFI_STATUS
+EmmcIdentification (
+  IN SD_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  );
+
+/**
+  Execute EMMC device identification procedure.
+
+  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       There is a EMMC card.
+  @retval Others            There is not a EMMC card.
+
+**/
+EFI_STATUS
+SdCardIdentification (
+  IN SD_MMC_HC_PRIVATE_DATA             *Private,
+  IN UINT8                              Slot
+  );
+
+#endif
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf
new file mode 100644
index 0000000..fad9fc6
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf
@@ -0,0 +1,64 @@
+## @file
+#  SdMmcPciHcDxe driver is used to manage those host controllers which comply with SD
+#  Host Controller Simplified Specifiction version 3.0.
+#
+#  It will produce EFI_SD_MMC_PASS_THRU_PROTOCOL to allow sending SD/MMC/eMMC cmds
+#  to specified devices from upper layer.
+#
+#  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+#  Copyright (C) 2016 Marvell International Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = XenonDxe
+  MODULE_UNI_FILE                = SdMmcPciHcDxe.uni
+  FILE_GUID                      = 17f56b40-f7c1-435c-ab8d-404872da951e
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeSdMmcPciHcDxe
+
+[Sources]
+  ComponentName.c
+  EmmcDevice.c
+  SdDevice.c
+  SdMmcPciHcDxe.c
+  SdMmcPciHcDxe.h
+  SdMmcPciHci.c
+  SdMmcPciHci.h
+  XenonSdhci.c
+  XenonSdhci.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  DevicePathLib
+  MemoryAllocationLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+  UefiRuntimeServicesTableLib
+
+[Protocols]
+  gEfiDevicePathProtocolGuid                    ## TO_START
+  gEfiPciIoProtocolGuid                         ## TO_START
+  gEfiSdMmcPassThruProtocolGuid                 ## BY_START
+
+# [Event]
+# EVENT_TYPE_PERIODIC_TIMER ## SOMETIMES_CONSUMES
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  SdMmcPciHcDxeExtra.uni
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.uni b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.uni
new file mode 100644
index 0000000..57f9fa7
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.uni
@@ -0,0 +1,23 @@
+// /** @file
+// SdMmcPciHcDxe driver is used to manage those host controllers which comply with SD
+// Host Controller Simplified Specifiction version 3.0.
+//
+// It will produce EFI_SD_MMC_PASS_THRU_PROTOCOL to allow sending SD/MMC/eMMC cmds
+// to specified devices from upper layer.
+//
+// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "SD/MMC Pci Host Controller driver to manage SD/MMC host controllers"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "This driver follows the UEFI driver model and produces SD/MMC Pass Thru protocol for upper layer bus driver."
+
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxeExtra.uni b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxeExtra.uni
new file mode 100644
index 0000000..c7aedb4
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxeExtra.uni
@@ -0,0 +1,19 @@
+// /** @file
+// SdMmcPciHcDxe Localized Strings and Content
+//
+// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"SD/MMC Pci Host Controller Driver"
+
+
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c
new file mode 100644
index 0000000..ccbf355
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c
@@ -0,0 +1,1923 @@
+/** @file
+  This driver is used to manage SD/MMC PCI host controllers which are compliance
+  with SD Host Controller Simplified Specification version 3.00.
+
+  It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
+
+  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SdMmcPciHcDxe.h"
+
+/**
+  Dump the content of SD/MMC host controller's Capability Register.
+
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[in]  Capability      The buffer to store the capability data.
+
+**/
+VOID
+DumpCapabilityReg (
+  IN UINT8                Slot,
+  IN SD_MMC_HC_SLOT_CAP   *Capability
+  )
+{
+  //
+  // Dump Capability Data
+  //
+  DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
+  DEBUG ((DEBUG_INFO, "   Timeout Clk Freq  %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
+  DEBUG ((DEBUG_INFO, "   Base Clk Freq     %dMHz\n", Capability->BaseClkFreq));
+  DEBUG ((DEBUG_INFO, "   Max Blk Len       %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
+  DEBUG ((DEBUG_INFO, "   8-bit Support     %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   ADMA2 Support     %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   SDMA Support      %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Suspend/Resume    %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Voltage 3.3       %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Voltage 3.0       %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Voltage 1.8       %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   64-bit Sys Bus    %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Async Interrupt   %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   SlotType          "));
+  if (Capability->SlotType == 0x00) {
+    DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
+  } else if (Capability->SlotType == 0x01) {
+    DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
+  } else if (Capability->SlotType == 0x02) {
+    DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
+  } else {
+    DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
+  }
+  DEBUG ((DEBUG_INFO, "   SDR50  Support    %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   SDR104 Support    %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   DDR50  Support    %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Driver Type A     %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Driver Type C     %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Driver Type D     %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Driver Type 4     %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
+  if (Capability->TimerCount == 0) {
+    DEBUG ((DEBUG_INFO, "   Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
+  } else {
+    DEBUG ((DEBUG_INFO, "   Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
+  }
+  DEBUG ((DEBUG_INFO, "   SDR50 Tuning      %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
+  DEBUG ((DEBUG_INFO, "   Retuning Mode     Mode %d\n", Capability->RetuningMod + 1));
+  DEBUG ((DEBUG_INFO, "   Clock Multiplier  M = %d\n", Capability->ClkMultiplier + 1));
+  DEBUG ((DEBUG_INFO, "   HS 400            %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
+  return;
+}
+
+/**
+  Read SlotInfo register from SD/MMC host controller pci config space.
+
+  @param[in]  PciIo        The PCI IO protocol instance.
+  @param[out] FirstBar     The buffer to store the first BAR value.
+  @param[out] SlotNum      The buffer to store the supported slot number.
+
+  @retval EFI_SUCCESS      The operation succeeds.
+  @retval Others           The operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcGetSlotInfo (
+  IN     EFI_PCI_IO_PROTOCOL   *PciIo,
+     OUT UINT8                 *FirstBar,
+     OUT UINT8                 *SlotNum
+  )
+{
+  EFI_STATUS                   Status;
+  SD_MMC_HC_SLOT_INFO          SlotInfo;
+
+  Status = PciIo->Pci.Read (
+                        PciIo,
+                        EfiPciIoWidthUint8,
+                        SD_MMC_HC_SLOT_OFFSET,
+                        sizeof (SlotInfo),
+                        &SlotInfo
+                        );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  *FirstBar = SlotInfo.FirstBar;
+  *SlotNum  = SlotInfo.SlotNum + 1;
+  ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
+  return EFI_SUCCESS;
+}
+
+/**
+  Read/Write specified SD/MMC host controller mmio register.
+
+  @param[in]      PciIo        The PCI IO protocol instance.
+  @param[in]      BarIndex     The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in]      Offset       The offset within the selected BAR to start the
+                               memory operation.
+  @param[in]      Read         A boolean to indicate it's read or write operation.
+  @param[in]      Count        The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in, out] Data         For read operations, the destination buffer to store
+                               the results. For write operations, the source buffer
+                               to write data from. The caller is responsible for
+                               having ownership of the data buffer and ensuring its
+                               size not less than Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The read/write operation succeeds.
+  @retval Others                The read/write operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcRwMmio (
+  IN     EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN     UINT8                 BarIndex,
+  IN     UINT32                Offset,
+  IN     BOOLEAN               Read,
+  IN     UINT8                 Count,
+  IN OUT VOID                  *Data
+  )
+{
+  EFI_STATUS                   Status;
+
+  if ((PciIo == NULL) || (Data == NULL))  {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (Read) {
+    Status = PciIo->Mem.Read (
+                          PciIo,
+                          EfiPciIoWidthUint8,
+                          BarIndex,
+                          (UINT64) Offset,
+                          Count,
+                          Data
+                          );
+  } else {
+    Status = PciIo->Mem.Write (
+                          PciIo,
+                          EfiPciIoWidthUint8,
+                          BarIndex,
+                          (UINT64) Offset,
+                          Count,
+                          Data
+                          );
+  }
+
+  return Status;
+}
+
+/**
+  Do OR operation with the value of the specified SD/MMC host controller mmio register.
+
+  @param[in] PciIo             The PCI IO protocol instance.
+  @param[in] BarIndex          The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in] Offset            The offset within the selected BAR to start the
+                               memory operation.
+  @param[in] Count             The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in] OrData            The pointer to the data used to do OR operation.
+                               The caller is responsible for having ownership of
+                               the data buffer and ensuring its size not less than
+                               Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The OR operation succeeds.
+  @retval Others                The OR operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcOrMmio (
+  IN  EFI_PCI_IO_PROTOCOL      *PciIo,
+  IN  UINT8                    BarIndex,
+  IN  UINT32                   Offset,
+  IN  UINT8                    Count,
+  IN  VOID                     *OrData
+  )
+{
+  EFI_STATUS                   Status;
+  UINT64                       Data;
+  UINT64                       Or;
+
+  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if (Count == 1) {
+    Or = *(UINT8*) OrData;
+  } else if (Count == 2) {
+    Or = *(UINT16*) OrData;
+  } else if (Count == 4) {
+    Or = *(UINT32*) OrData;
+  } else if (Count == 8) {
+    Or = *(UINT64*) OrData;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Data  |= Or;
+  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
+
+  return Status;
+}
+
+/**
+  Do AND operation with the value of the specified SD/MMC host controller mmio register.
+
+  @param[in] PciIo             The PCI IO protocol instance.
+  @param[in] BarIndex          The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in] Offset            The offset within the selected BAR to start the
+                               memory operation.
+  @param[in] Count             The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in] AndData           The pointer to the data used to do AND operation.
+                               The caller is responsible for having ownership of
+                               the data buffer and ensuring its size not less than
+                               Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The AND operation succeeds.
+  @retval Others                The AND operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcAndMmio (
+  IN  EFI_PCI_IO_PROTOCOL      *PciIo,
+  IN  UINT8                    BarIndex,
+  IN  UINT32                   Offset,
+  IN  UINT8                    Count,
+  IN  VOID                     *AndData
+  )
+{
+  EFI_STATUS                   Status;
+  UINT64                       Data;
+  UINT64                       And;
+
+  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if (Count == 1) {
+    And = *(UINT8*) AndData;
+  } else if (Count == 2) {
+    And = *(UINT16*) AndData;
+  } else if (Count == 4) {
+    And = *(UINT32*) AndData;
+  } else if (Count == 8) {
+    And = *(UINT64*) AndData;
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Data  &= And;
+  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
+
+  return Status;
+}
+
+/**
+  Wait for the value of the specified MMIO register set to the test value.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  BarIndex      The BAR index of the standard PCI Configuration
+                            header to use as the base address for the memory
+                            operation to perform.
+  @param[in]  Offset        The offset within the selected BAR to start the
+                            memory operation.
+  @param[in]  Count         The width of the mmio register in bytes.
+                            Must be 1, 2, 4 or 8 bytes.
+  @param[in]  MaskValue     The mask value of memory.
+  @param[in]  TestValue     The test value of memory.
+
+  @retval EFI_NOT_READY     The MMIO register hasn't set to the expected value.
+  @retval EFI_SUCCESS       The MMIO register has expected value.
+  @retval Others            The MMIO operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcCheckMmioSet (
+  IN  EFI_PCI_IO_PROTOCOL       *PciIo,
+  IN  UINT8                     BarIndex,
+  IN  UINT32                    Offset,
+  IN  UINT8                     Count,
+  IN  UINT64                    MaskValue,
+  IN  UINT64                    TestValue
+  )
+{
+  EFI_STATUS            Status;
+  UINT64                Value;
+
+  //
+  // Access PCI MMIO space to see if the value is the tested one.
+  //
+  Value  = 0;
+  Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Value &= MaskValue;
+
+  if (Value == TestValue) {
+    return EFI_SUCCESS;
+  }
+
+  return EFI_NOT_READY;
+}
+
+/**
+  Wait for the value of the specified MMIO register set to the test value.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  BarIndex      The BAR index of the standard PCI Configuration
+                            header to use as the base address for the memory
+                            operation to perform.
+  @param[in]  Offset        The offset within the selected BAR to start the
+                            memory operation.
+  @param[in]  Count         The width of the mmio register in bytes.
+                            Must be 1, 2, 4 or 8 bytes.
+  @param[in]  MaskValue     The mask value of memory.
+  @param[in]  TestValue     The test value of memory.
+  @param[in]  Timeout       The time out value for wait memory set, uses 1
+                            microsecond as a unit.
+
+  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
+                            range.
+  @retval EFI_SUCCESS       The MMIO register has expected value.
+  @retval Others            The MMIO operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcWaitMmioSet (
+  IN  EFI_PCI_IO_PROTOCOL       *PciIo,
+  IN  UINT8                     BarIndex,
+  IN  UINT32                    Offset,
+  IN  UINT8                     Count,
+  IN  UINT64                    MaskValue,
+  IN  UINT64                    TestValue,
+  IN  UINT64                    Timeout
+  )
+{
+  EFI_STATUS            Status;
+  BOOLEAN               InfiniteWait;
+
+  if (Timeout == 0) {
+    InfiniteWait = TRUE;
+  } else {
+    InfiniteWait = FALSE;
+  }
+
+  while (InfiniteWait || (Timeout > 0)) {
+    Status = SdMmcHcCheckMmioSet (
+               PciIo,
+               BarIndex,
+               Offset,
+               Count,
+               MaskValue,
+               TestValue
+               );
+    if (Status != EFI_NOT_READY) {
+      return Status;
+    }
+
+    //
+    // Stall for 1 microsecond.
+    //
+    gBS->Stall (1);
+
+    Timeout--;
+  }
+
+  return EFI_TIMEOUT;
+}
+
+/**
+  Software reset the specified SD/MMC host controller and enable all interrupts.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The software reset executes successfully.
+  @retval Others            The software reset fails.
+
+**/
+EFI_STATUS
+SdMmcHcReset (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  )
+{
+  EFI_STATUS                Status;
+  UINT8                     SwReset;
+
+  SwReset = 0xFF;
+  Status  = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);
+
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write full 1 fails: %r\n", Status));
+    return Status;
+  }
+
+  Status = SdMmcHcWaitMmioSet (
+             PciIo,
+             Slot,
+             SD_MMC_HC_SW_RST,
+             sizeof (SwReset),
+             0xFF,
+             0x00,
+             SD_MMC_HC_GENERIC_TIMEOUT
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
+    return Status;
+  }
+  //
+  // Enable all interrupt after reset all.
+  //
+  Status = SdMmcHcEnableInterrupt (PciIo, Slot);
+
+  return Status;
+}
+
+/**
+  Set all interrupt status bits in Normal and Error Interrupt Status Enable
+  register.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation executes successfully.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdMmcHcEnableInterrupt (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  )
+{
+  EFI_STATUS                Status;
+  UINT16                    IntStatus;
+
+  //
+  // Enable all bits in Error Interrupt Status Enable Register
+  //
+  IntStatus = 0xFFFF;
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Enable all bits in Normal Interrupt Status Enable Register
+  //
+  IntStatus = 0xFFFF;
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
+
+  return Status;
+}
+
+/**
+  Get the capability data from the specified slot.
+
+  @param[in]  PciIo           The PCI IO protocol instance.
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[out] Capability      The buffer to store the capability data.
+
+  @retval EFI_SUCCESS         The operation executes successfully.
+  @retval Others              The operation fails.
+
+**/
+EFI_STATUS
+SdMmcHcGetCapability (
+  IN     EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN     UINT8                Slot,
+     OUT SD_MMC_HC_SLOT_CAP   *Capability
+  )
+{
+  EFI_STATUS                Status;
+  UINT64                    Cap;
+
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  CopyMem (Capability, &Cap, sizeof (Cap));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Get the maximum current capability data from the specified slot.
+
+  @param[in]  PciIo           The PCI IO protocol instance.
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[out] MaxCurrent      The buffer to store the maximum current capability data.
+
+  @retval EFI_SUCCESS         The operation executes successfully.
+  @retval Others              The operation fails.
+
+**/
+EFI_STATUS
+SdMmcHcGetMaxCurrent (
+  IN     EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN     UINT8                Slot,
+     OUT UINT64               *MaxCurrent
+  )
+{
+  EFI_STATUS          Status;
+
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
+
+  return Status;
+}
+
+/**
+  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
+  slot.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[out] MediaPresent  The pointer to the media present boolean value.
+
+  @retval EFI_SUCCESS       There is no media change happened.
+  @retval EFI_MEDIA_CHANGED There is media change happened.
+  @retval Others            The detection fails.
+
+**/
+EFI_STATUS
+SdMmcHcCardDetect (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+     OUT BOOLEAN            *MediaPresent
+  )
+{
+  EFI_STATUS                Status;
+  UINT16                    Data;
+  UINT32                    PresentState;
+
+  //
+  // Check Present State Register to see if there is a card presented.
+  //
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if ((PresentState & BIT16) != 0) {
+    *MediaPresent = TRUE;
+  } else {
+    *MediaPresent = FALSE;
+  }
+
+  //
+  // Check Normal Interrupt Status Register
+  //
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if ((Data & (BIT6 | BIT7)) != 0) {
+    //
+    // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
+    //
+    Data  &= BIT6 | BIT7;
+    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+
+    return EFI_MEDIA_CHANGED;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Stop SD/MMC card clock.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
+  @retval Others            Fail to stop SD/MMC clock.
+
+**/
+EFI_STATUS
+SdMmcHcStopClock (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    PresentState;
+  UINT16                    ClockCtrl;
+
+  //
+  // Ensure no SD transactions are occurring on the SD Bus by
+  // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
+  // in the Present State register to be 0.
+  //
+  Status = SdMmcHcWaitMmioSet (
+             PciIo,
+             Slot,
+             SD_MMC_HC_PRESENT_STATE,
+             sizeof (PresentState),
+             BIT0 | BIT1,
+             0,
+             SD_MMC_HC_GENERIC_TIMEOUT
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Set SD Clock Enable in the Clock Control register to 0
+  //
+  ClockCtrl = (UINT16)~BIT2;
+  Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
+
+  return Status;
+}
+
+/**
+  SD/MMC card clock supply.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The clock is supplied successfully.
+  @retval Others            The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+SdMmcHcClockSupply (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT64                 ClockFreq,
+  IN SD_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    BaseClkFreq;
+  UINT32                    SettingFreq;
+  UINT32                    Divisor;
+  UINT32                    Remainder;
+  UINT16                    ControllerVer;
+  UINT16                    ClockCtrl;
+
+  //
+  // Calculate a divisor for SD clock frequency
+  //
+  ASSERT (Capability.BaseClkFreq != 0);
+
+  BaseClkFreq = Capability.BaseClkFreq;
+  if (ClockFreq == 0) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (ClockFreq > (BaseClkFreq * 1000)) {
+    ClockFreq = BaseClkFreq * 1000;
+  }
+
+  //
+  // Calculate the divisor of base frequency.
+  //
+  Divisor     = 0;
+  SettingFreq = BaseClkFreq * 1000;
+  while (ClockFreq < SettingFreq) {
+    Divisor++;
+
+    SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
+    Remainder   = (BaseClkFreq * 1000) % (2 * Divisor);
+    if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
+      break;
+    }
+    if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
+      SettingFreq ++;
+    }
+  }
+
+  DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
+
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
+  //
+  if ((ControllerVer & 0xFF) == 2) {
+    ASSERT (Divisor <= 0x3FF);
+    ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
+  } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
+    //
+    // Only the most significant bit can be used as divisor.
+    //
+    if (((Divisor - 1) & Divisor) != 0) {
+      Divisor = 1 << (HighBitSet32 (Divisor) + 1);
+    }
+    ASSERT (Divisor <= 0x80);
+    ClockCtrl = (Divisor & 0xFF) << 8;
+  } else {
+    DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Stop bus clock at first
+  //
+  Status = SdMmcHcStopClock (PciIo, Slot);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Supply clock frequency with specified divisor
+  //
+  ClockCtrl |= BIT0;
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
+    return Status;
+  }
+
+  //
+  // Wait Internal Clock Stable in the Clock Control register to be 1
+  //
+  Status = SdMmcHcWaitMmioSet (
+             PciIo,
+             Slot,
+             SD_MMC_HC_CLOCK_CTRL,
+             sizeof (ClockCtrl),
+             BIT1,
+             BIT1,
+             SD_MMC_HC_GENERIC_TIMEOUT
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Set SD Clock Enable in the Clock Control register to 1
+  //
+  ClockCtrl = BIT2;
+  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
+
+  return Status;
+}
+
+/**
+  SD/MMC bus power control.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] PowerCtrl      The value setting to the power control register.
+
+  @retval TRUE              There is a SD/MMC card attached.
+  @retval FALSE             There is no a SD/MMC card attached.
+
+**/
+EFI_STATUS
+SdMmcHcPowerControl (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT8                  PowerCtrl
+  )
+{
+  EFI_STATUS                Status;
+
+  //
+  // Clr SD Bus Power
+  //
+  PowerCtrl &= (UINT8)~BIT0;
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
+  //
+  PowerCtrl |= BIT0;
+  Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
+
+  return Status;
+}
+
+/**
+  Set the SD/MMC bus width.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
+
+  @retval EFI_SUCCESS       The bus width is set successfully.
+  @retval Others            The bus width isn't set successfully.
+
+**/
+EFI_STATUS
+SdMmcHcSetBusWidth (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT16                 BusWidth
+  )
+{
+  EFI_STATUS                Status;
+  UINT8                     HostCtrl1;
+
+  if (BusWidth == 1) {
+    HostCtrl1 = (UINT8)~(BIT5 | BIT1);
+    Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+  } else if (BusWidth == 4) {
+    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    HostCtrl1 |= BIT1;
+    HostCtrl1 &= (UINT8)~BIT5;
+    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
+  } else if (BusWidth == 8) {
+    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    HostCtrl1 &= (UINT8)~BIT1;
+    HostCtrl1 |= BIT5;
+    Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
+  } else {
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return Status;
+}
+
+/**
+  Supply SD/MMC card with lowest clock frequency at initialization.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The clock is supplied successfully.
+  @retval Others            The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+SdMmcHcInitClockFreq (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN SD_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS                Status;
+  UINT32                    InitFreq;
+
+  //
+  // Calculate a divisor for SD clock frequency
+  //
+  if (Capability.BaseClkFreq == 0) {
+    //
+    // Don't support get Base Clock Frequency information via another method
+    //
+    return EFI_UNSUPPORTED;
+  }
+  //
+  // Supply 400KHz clock frequency at initialization phase.
+  //
+  InitFreq = 400;
+  Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
+  return Status;
+}
+
+/**
+  Supply SD/MMC card with maximum voltage at initialization.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The voltage is supplied successfully.
+  @retval Others            The voltage isn't supplied successfully.
+
+**/
+EFI_STATUS
+SdMmcHcInitPowerVoltage (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN SD_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS                Status;
+  UINT8                     MaxVoltage;
+  UINT8                     HostCtrl2;
+
+  //
+  // Calculate supported maximum voltage according to SD Bus Voltage Select
+  //
+  if (Capability.Voltage33 != 0) {
+    //
+    // Support 3.3V
+    //
+    MaxVoltage = 0x0E;
+  } else if (Capability.Voltage30 != 0) {
+    //
+    // Support 3.0V
+    //
+    MaxVoltage = 0x0C;
+  } else if (Capability.Voltage18 != 0) {
+    //
+    // Support 1.8V
+    //
+    MaxVoltage = 0x0A;
+    HostCtrl2  = BIT3;
+    Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+    gBS->Stall (5000);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  } else {
+    ASSERT (FALSE);
+    return EFI_DEVICE_ERROR;
+  }
+
+  //
+  // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
+  //
+  Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
+
+  return Status;
+}
+
+/**
+  Initialize the Timeout Control register with most conservative value at initialization.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The timeout control register is configured successfully.
+  @retval Others            The timeout control register isn't configured successfully.
+
+**/
+EFI_STATUS
+SdMmcHcInitTimeoutCtrl (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  )
+{
+  EFI_STATUS                Status;
+  UINT8                     Timeout;
+
+  Timeout = 0x0E;
+  Status  = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
+
+  return Status;
+}
+
+/**
+  Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
+  at initialization.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The host controller is initialized successfully.
+  @retval Others            The host controller isn't initialized successfully.
+
+**/
+EFI_STATUS
+SdMmcHcInitHost (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN SD_MMC_HC_SLOT_CAP     Capability
+  )
+{
+  EFI_STATUS       Status;
+
+  Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
+  return Status;
+}
+
+/**
+  Turn on/off LED.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] On             The boolean to turn on/off LED.
+
+  @retval EFI_SUCCESS       The LED is turned on/off successfully.
+  @retval Others            The LED isn't turned on/off successfully.
+
+**/
+EFI_STATUS
+SdMmcHcLedOnOff (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN BOOLEAN                On
+  )
+{
+  EFI_STATUS                Status;
+  UINT8                     HostCtrl1;
+
+  if (On) {
+    HostCtrl1 = BIT0;
+    Status    = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+  } else {
+    HostCtrl1 = (UINT8)~BIT0;
+    Status    = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+  }
+
+  return Status;
+}
+
+/**
+  Build ADMA descriptor table for transfer.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
+
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The ADMA descriptor table is created successfully.
+  @retval Others            The ADMA descriptor table isn't created successfully.
+
+**/
+EFI_STATUS
+BuildAdmaDescTable (
+  IN SD_MMC_HC_TRB          *Trb
+  )
+{
+  EFI_PHYSICAL_ADDRESS      Data;
+  UINT64                    DataLen;
+  UINT64                    Entries;
+  UINT32                    Index;
+  UINT64                    Remaining;
+  UINT32                    Address;
+  UINTN                     TableSize;
+  EFI_PCI_IO_PROTOCOL       *PciIo;
+  EFI_STATUS                Status;
+  UINTN                     Bytes;
+
+  Data    = Trb->DataPhy;
+  DataLen = Trb->DataLen;
+  PciIo   = Trb->Private->PciIo;
+  //
+  // Only support 32bit ADMA Descriptor Table
+  //
+  if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  //
+  // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
+  // for 32-bit address descriptor table.
+  //
+  if ((Data & (BIT0 | BIT1)) != 0) {
+    DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
+  }
+
+  Entries   = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
+  TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));
+  Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
+  Status = PciIo->AllocateBuffer (
+                    PciIo,
+                    AllocateAnyPages,
+                    EfiBootServicesData,
+                    EFI_SIZE_TO_PAGES (TableSize),
+                    (VOID **)&Trb->AdmaDesc,
+                    0
+                    );
+  if (EFI_ERROR (Status)) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  ZeroMem (Trb->AdmaDesc, TableSize);
+  Bytes  = TableSize;
+  Status = PciIo->Map (
+                    PciIo,
+                    EfiPciIoOperationBusMasterCommonBuffer,
+                    Trb->AdmaDesc,
+                    &Bytes,
+                    &Trb->AdmaDescPhy,
+                    &Trb->AdmaMap
+                    );
+
+  if (EFI_ERROR (Status) || (Bytes != TableSize)) {
+    //
+    // Map error or unable to map the whole RFis buffer into a contiguous region.
+    //
+    PciIo->FreeBuffer (
+             PciIo,
+             EFI_SIZE_TO_PAGES (TableSize),
+             Trb->AdmaDesc
+             );
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
+    //
+    // The ADMA doesn't support 64bit addressing.
+    //
+    PciIo->Unmap (
+      PciIo,
+      Trb->AdmaMap
+    );
+    PciIo->FreeBuffer (
+      PciIo,
+      EFI_SIZE_TO_PAGES (TableSize),
+      Trb->AdmaDesc
+    );
+    return EFI_DEVICE_ERROR;
+  }
+
+  Remaining = DataLen;
+  Address   = (UINT32)Data;
+  for (Index = 0; Index < Entries; Index++) {
+    if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
+      Trb->AdmaDesc[Index].Valid = 1;
+      Trb->AdmaDesc[Index].Act   = 2;
+      Trb->AdmaDesc[Index].Length  = (UINT16)Remaining;
+      Trb->AdmaDesc[Index].Address = Address;
+      break;
+    } else {
+      Trb->AdmaDesc[Index].Valid = 1;
+      Trb->AdmaDesc[Index].Act   = 2;
+      Trb->AdmaDesc[Index].Length  = 0;
+      Trb->AdmaDesc[Index].Address = Address;
+    }
+
+    Remaining -= ADMA_MAX_DATA_PER_LINE;
+    Address   += ADMA_MAX_DATA_PER_LINE;
+  }
+
+  //
+  // Set the last descriptor line as end of descriptor table
+  //
+  Trb->AdmaDesc[Index].End = 1;
+  return EFI_SUCCESS;
+}
+
+/**
+  Create a new TRB for the SD/MMC cmd request.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Packet         A pointer to the SD command data structure.
+  @param[in] Event          If Event is NULL, blocking I/O is performed. If Event is
+                            not NULL, then nonblocking I/O is performed, and Event
+                            will be signaled when the Packet completes.
+
+  @return Created Trb or NULL.
+
+**/
+SD_MMC_HC_TRB *
+SdMmcCreateTrb (
+  IN SD_MMC_HC_PRIVATE_DATA              *Private,
+  IN UINT8                               Slot,
+  IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
+  IN EFI_EVENT                           Event
+  )
+{
+  SD_MMC_HC_TRB                 *Trb;
+  EFI_STATUS                    Status;
+  EFI_TPL                       OldTpl;
+  EFI_PCI_IO_PROTOCOL_OPERATION Flag;
+  EFI_PCI_IO_PROTOCOL           *PciIo;
+  UINTN                         MapLength;
+
+  Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
+  if (Trb == NULL) {
+    return NULL;
+  }
+
+  Trb->Signature = SD_MMC_HC_TRB_SIG;
+  Trb->Slot      = Slot;
+  Trb->BlockSize = 0x200;
+  Trb->Packet    = Packet;
+  Trb->Event     = Event;
+  Trb->Started   = FALSE;
+  Trb->Timeout   = Packet->Timeout;
+  Trb->Private   = Private;
+
+  if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
+    Trb->Data    = Packet->InDataBuffer;
+    Trb->DataLen = Packet->InTransferLength;
+    Trb->Read    = TRUE;
+  } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
+    Trb->Data    = Packet->OutDataBuffer;
+    Trb->DataLen = Packet->OutTransferLength;
+    Trb->Read    = FALSE;
+  } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
+    Trb->Data    = NULL;
+    Trb->DataLen = 0;
+  } else {
+    goto Error;
+  }
+
+  if (Trb->DataLen < Trb->BlockSize) {
+    Trb->BlockSize = (UINT16)Trb->DataLen;
+  }
+
+  if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
+       (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
+      ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
+       (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
+    Trb->Mode = SdMmcPioMode;
+  } else {
+    if (Trb->Read) {
+      Flag = EfiPciIoOperationBusMasterWrite;
+    } else {
+      Flag = EfiPciIoOperationBusMasterRead;
+    }
+
+    PciIo = Private->PciIo;
+    if (Trb->DataLen != 0) {
+      MapLength = Trb->DataLen;
+      Status = PciIo->Map (
+                        PciIo,
+                        Flag,
+                        Trb->Data,
+                        &MapLength,
+                        &Trb->DataPhy,
+                        &Trb->DataMap
+                        );
+      if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
+        Status = EFI_BAD_BUFFER_SIZE;
+        goto Error;
+      }
+    }
+
+    if (Trb->DataLen == 0) {
+      Trb->Mode = SdMmcNoData;
+    } else if (Private->Capability[Slot].Adma2 != 0) {
+      Trb->Mode = SdMmcAdmaMode;
+      Status = BuildAdmaDescTable (Trb);
+      if (EFI_ERROR (Status)) {
+        PciIo->Unmap (PciIo, Trb->DataMap);
+        goto Error;
+      }
+    } else if (Private->Capability[Slot].Sdma != 0) {
+      Trb->Mode = SdMmcSdmaMode;
+    } else {
+      Trb->Mode = SdMmcPioMode;
+    }
+  }
+
+  if (Event != NULL) {
+    OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+    InsertTailList (&Private->Queue, &Trb->TrbList);
+    gBS->RestoreTPL (OldTpl);
+  }
+
+  return Trb;
+
+Error:
+  SdMmcFreeTrb (Trb);
+  return NULL;
+}
+
+/**
+  Free the resource used by the TRB.
+
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+**/
+VOID
+SdMmcFreeTrb (
+  IN SD_MMC_HC_TRB           *Trb
+  )
+{
+  EFI_PCI_IO_PROTOCOL        *PciIo;
+
+  PciIo = Trb->Private->PciIo;
+
+  if (Trb->AdmaMap != NULL) {
+    PciIo->Unmap (
+      PciIo,
+      Trb->AdmaMap
+    );
+  }
+  if (Trb->AdmaDesc != NULL) {
+    PciIo->FreeBuffer (
+      PciIo,
+      Trb->AdmaPages,
+      Trb->AdmaDesc
+    );
+  }
+  if (Trb->DataMap != NULL) {
+    PciIo->Unmap (
+      PciIo,
+      Trb->DataMap
+    );
+  }
+  FreePool (Trb);
+  return;
+}
+
+/**
+  Check if the env is ready for execute specified TRB.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The env is ready for TRB execution.
+  @retval EFI_NOT_READY     The env is not ready for TRB execution.
+  @retval Others            Some erros happen.
+
+**/
+EFI_STATUS
+SdMmcCheckTrbEnv (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+  UINT32                              PresentState;
+
+  Packet = Trb->Packet;
+
+  if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
+      (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
+      (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
+    //
+    // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
+    // the Present State register to be 0
+    //
+    PresentState = BIT0 | BIT1;
+  } else {
+    //
+    // Wait Command Inhibit (CMD) in the Present State register
+    // to be 0
+    //
+    PresentState = BIT0;
+  }
+
+  PciIo  = Private->PciIo;
+  Status = SdMmcHcCheckMmioSet (
+             PciIo,
+             Trb->Slot,
+             SD_MMC_HC_PRESENT_STATE,
+             sizeof (PresentState),
+             PresentState,
+             0
+             );
+
+  return Status;
+}
+
+/**
+  Wait for the env to be ready for execute specified TRB.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The env is ready for TRB execution.
+  @retval EFI_TIMEOUT       The env is not ready for TRB execution in time.
+  @retval Others            Some erros happen.
+
+**/
+EFI_STATUS
+SdMmcWaitTrbEnv (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  UINT64                              Timeout;
+  BOOLEAN                             InfiniteWait;
+
+  //
+  // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
+  //
+  Packet  = Trb->Packet;
+  Timeout = Packet->Timeout;
+  if (Timeout == 0) {
+    InfiniteWait = TRUE;
+  } else {
+    InfiniteWait = FALSE;
+  }
+
+  while (InfiniteWait || (Timeout > 0)) {
+    //
+    // Check Trb execution result by reading Normal Interrupt Status register.
+    //
+    Status = SdMmcCheckTrbEnv (Private, Trb);
+    if (Status != EFI_NOT_READY) {
+      return Status;
+    }
+    //
+    // Stall for 1 microsecond.
+    //
+    gBS->Stall (1);
+
+    Timeout--;
+  }
+
+  return EFI_TIMEOUT;
+}
+
+/**
+  Execute the specified TRB.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is sent to host controller successfully.
+  @retval Others            Some erros happen when sending this request to the host controller.
+
+**/
+EFI_STATUS
+SdMmcExecTrb (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  EFI_PCI_IO_PROTOCOL                 *PciIo;
+  UINT16                              Cmd;
+  UINT16                              IntStatus;
+  UINT32                              Argument;
+  UINT16                              BlkCount;
+  UINT16                              BlkSize;
+  UINT16                              TransMode;
+  UINT8                               HostCtrl1;
+  UINT32                              SdmaAddr;
+  UINT64                              AdmaAddr;
+
+  Packet = Trb->Packet;
+  PciIo  = Trb->Private->PciIo;
+  //
+  // Clear all bits in Error Interrupt Status Register
+  //
+  IntStatus = 0xFFFF;
+  Status    = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
+  //
+  IntStatus = 0xFF3F;
+  Status    = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  //
+  // Set Host Control 1 register DMA Select field
+  //
+  if (Trb->Mode == SdMmcAdmaMode) {
+    HostCtrl1 = BIT4;
+    Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+
+  SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
+
+  if (Trb->Mode == SdMmcSdmaMode) {
+    if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
+    Status   = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  } else if (Trb->Mode == SdMmcAdmaMode) {
+    AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
+    Status   = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+  }
+
+  BlkSize = Trb->BlockSize;
+  if (Trb->Mode == SdMmcSdmaMode) {
+    //
+    // Set SDMA boundary to be 512K bytes.
+    //
+    BlkSize |= 0x7000;
+  }
+
+  Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  BlkCount = 0;
+  if (Trb->Mode != SdMmcNoData) {
+    //
+    // Calcuate Block Count.
+    //
+    BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
+  }
+  Status   = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Argument = Packet->SdMmcCmdBlk->CommandArgument;
+  Status   = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  TransMode = 0;
+  if (Trb->Mode != SdMmcNoData) {
+    if (Trb->Mode != SdMmcPioMode) {
+      TransMode |= BIT0;
+    }
+    if (Trb->Read) {
+      TransMode |= BIT4;
+    }
+    if (BlkCount > 1) {
+      TransMode |= BIT5 | BIT1;
+    }
+    //
+    // Only SD memory card needs to use AUTO CMD12 feature.
+    //
+    if (Private->Slot[Trb->Slot].CardType == SdCardType) {
+      if (BlkCount > 1) {
+        TransMode |= BIT2;
+      }
+    }
+  }
+
+  Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
+  if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
+    Cmd |= BIT5;
+  }
+  //
+  // Convert ResponseType to value
+  //
+  if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
+    switch (Packet->SdMmcCmdBlk->ResponseType) {
+      case SdMmcResponseTypeR1:
+      case SdMmcResponseTypeR5:
+      case SdMmcResponseTypeR6:
+      case SdMmcResponseTypeR7:
+        Cmd |= (BIT1 | BIT3 | BIT4);
+        break;
+      case SdMmcResponseTypeR2:
+        Cmd |= (BIT0 | BIT3);
+       break;
+      case SdMmcResponseTypeR3:
+      case SdMmcResponseTypeR4:
+        Cmd |= BIT1;
+        break;
+      case SdMmcResponseTypeR1b:
+      case SdMmcResponseTypeR5b:
+        Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
+        break;
+      default:
+        ASSERT (FALSE);
+        break;
+    }
+  }
+  //
+  // Execute cmd
+  //
+  Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
+  return Status;
+}
+
+/**
+  Check the TRB execution result.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is executed successfully.
+  @retval EFI_NOT_READY     The TRB is not completed for execution.
+  @retval Others            Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+SdMmcCheckTrbResult (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  UINT16                              IntStatus;
+  UINT32                              Response[4];
+  UINT32                              SdmaAddr;
+  UINT8                               Index;
+  UINT8                               SwReset;
+  UINT32                              PioLength;
+
+  SwReset = 0;
+  Packet  = Trb->Packet;
+  //
+  // Check Trb execution result by reading Normal Interrupt Status register.
+  //
+  Status = SdMmcHcRwMmio (
+             Private->PciIo,
+             Trb->Slot,
+             SD_MMC_HC_NOR_INT_STS,
+             TRUE,
+             sizeof (IntStatus),
+             &IntStatus
+             );
+  if (EFI_ERROR (Status)) {
+    goto Done;
+  }
+  //
+  // Check Transfer Complete bit is set or not.
+  //
+  if ((IntStatus & BIT1) == BIT1) {
+    if ((IntStatus & BIT15) == BIT15) {
+      //
+      // Read Error Interrupt Status register to check if the error is
+      // Data Timeout Error.
+      // If yes, treat it as success as Transfer Complete has higher
+      // priority than Data Timeout Error.
+      //
+      Status = SdMmcHcRwMmio (
+                 Private->PciIo,
+                 Trb->Slot,
+                 SD_MMC_HC_ERR_INT_STS,
+                 TRUE,
+                 sizeof (IntStatus),
+                 &IntStatus
+                 );
+      if (!EFI_ERROR (Status)) {
+        if ((IntStatus & BIT4) == BIT4) {
+          Status = EFI_SUCCESS;
+        } else {
+          Status = EFI_DEVICE_ERROR;
+        }
+      }
+    }
+
+    goto Done;
+  }
+  //
+  // Check if there is a error happened during cmd execution.
+  // If yes, then do error recovery procedure to follow SD Host Controller
+  // Simplified Spec 3.0 section 3.10.1.
+  //
+  if ((IntStatus & BIT15) == BIT15) {
+    Status = SdMmcHcRwMmio (
+               Private->PciIo,
+               Trb->Slot,
+               SD_MMC_HC_ERR_INT_STS,
+               TRUE,
+               sizeof (IntStatus),
+               &IntStatus
+               );
+    if (EFI_ERROR (Status)) {
+      goto Done;
+    }
+    if ((IntStatus & 0x0F) != 0) {
+      SwReset |= BIT1;
+    }
+    if ((IntStatus & 0xF0) != 0) {
+      SwReset |= BIT2;
+    }
+
+    Status  = SdMmcHcRwMmio (
+                Private->PciIo,
+                Trb->Slot,
+                SD_MMC_HC_SW_RST,
+                FALSE,
+                sizeof (SwReset),
+                &SwReset
+                );
+    if (EFI_ERROR (Status)) {
+      goto Done;
+    }
+    Status = SdMmcHcWaitMmioSet (
+               Private->PciIo,
+               Trb->Slot,
+               SD_MMC_HC_SW_RST,
+               sizeof (SwReset),
+               0xFF,
+               0,
+               SD_MMC_HC_GENERIC_TIMEOUT
+               );
+    if (EFI_ERROR (Status)) {
+      goto Done;
+    }
+
+    Status = EFI_DEVICE_ERROR;
+    goto Done;
+  }
+  //
+  // Check if DMA interrupt is signalled for the SDMA transfer.
+  //
+  if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
+    //
+    // Clear DMA interrupt bit.
+    //
+    IntStatus = BIT3;
+    Status    = SdMmcHcRwMmio (
+                  Private->PciIo,
+                  Trb->Slot,
+                  SD_MMC_HC_NOR_INT_STS,
+                  FALSE,
+                  sizeof (IntStatus),
+                  &IntStatus
+                  );
+    if (EFI_ERROR (Status)) {
+      goto Done;
+    }
+    //
+    // Update SDMA Address register.
+    //
+    SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
+    Status   = SdMmcHcRwMmio (
+                 Private->PciIo,
+                 Trb->Slot,
+                 SD_MMC_HC_SDMA_ADDR,
+                 FALSE,
+                 sizeof (UINT32),
+                 &SdmaAddr
+                 );
+    if (EFI_ERROR (Status)) {
+      goto Done;
+    }
+    Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
+  }
+
+  if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
+      (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
+      (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
+    if ((IntStatus & BIT0) == BIT0) {
+      Status = EFI_SUCCESS;
+      goto Done;
+    }
+  }
+
+  if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
+       (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
+      ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
+       (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
+    //
+    // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
+    // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
+    // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
+    //
+    if ((IntStatus & BIT5) == BIT5) {
+      //
+      // Clear Buffer Read Ready interrupt at first.
+      //
+      IntStatus = BIT5;
+      SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
+      //
+      // Read data out from Buffer Port register
+      //
+      for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
+        SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
+      }
+      Status = EFI_SUCCESS;
+      goto Done;
+    }
+  }
+
+  Status = EFI_NOT_READY;
+Done:
+  //
+  // Get response data when the cmd is executed successfully.
+  //
+  if (!EFI_ERROR (Status)) {
+    if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
+      for (Index = 0; Index < 4; Index++) {
+        Status = SdMmcHcRwMmio (
+                   Private->PciIo,
+                   Trb->Slot,
+                   SD_MMC_HC_RESPONSE + Index * 4,
+                   TRUE,
+                   sizeof (UINT32),
+                   &Response[Index]
+                   );
+        if (EFI_ERROR (Status)) {
+          SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
+          return Status;
+        }
+      }
+      CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
+    }
+  }
+
+  if (Status != EFI_NOT_READY) {
+    SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
+  }
+
+  return Status;
+}
+
+/**
+  Wait for the TRB execution result.
+
+  @param[in] Private        A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb            The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS       The TRB is executed successfully.
+  @retval Others            Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+SdMmcWaitTrbResult (
+  IN SD_MMC_HC_PRIVATE_DATA           *Private,
+  IN SD_MMC_HC_TRB                    *Trb
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
+  UINT64                              Timeout;
+  BOOLEAN                             InfiniteWait;
+
+  Packet = Trb->Packet;
+  //
+  // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
+  //
+  Timeout = Packet->Timeout;
+  if (Timeout == 0) {
+    InfiniteWait = TRUE;
+  } else {
+    InfiniteWait = FALSE;
+  }
+
+  while (InfiniteWait || (Timeout > 0)) {
+    //
+    // Check Trb execution result by reading Normal Interrupt Status register.
+    //
+    Status = SdMmcCheckTrbResult (Private, Trb);
+    if (Status != EFI_NOT_READY) {
+      return Status;
+    }
+    //
+    // Stall for 1 microsecond.
+    //
+    gBS->Stall (1);
+
+    Timeout--;
+  }
+
+  return EFI_TIMEOUT;
+}
+
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h b/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h
new file mode 100644
index 0000000..fb62758
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h
@@ -0,0 +1,546 @@
+/** @file
+
+  Provides some data structure definitions used by the SD/MMC host controller driver.
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SD_MMC_PCI_HCI_H_
+#define _SD_MMC_PCI_HCI_H_
+
+//
+// SD Host Controller SlotInfo Register Offset
+//
+#define SD_MMC_HC_SLOT_OFFSET         0x40
+
+#define SD_MMC_HC_MAX_SLOT            6
+
+//
+// SD Host Controller MMIO Register Offset
+//
+#define SD_MMC_HC_SDMA_ADDR           0x00
+#define SD_MMC_HC_ARG2                0x00
+#define SD_MMC_HC_BLK_SIZE            0x04
+#define SD_MMC_HC_BLK_COUNT           0x06
+#define SD_MMC_HC_ARG1                0x08
+#define SD_MMC_HC_TRANS_MOD           0x0C
+#define SD_MMC_HC_COMMAND             0x0E
+#define SD_MMC_HC_RESPONSE            0x10
+#define SD_MMC_HC_BUF_DAT_PORT        0x20
+#define SD_MMC_HC_PRESENT_STATE       0x24
+#define SD_MMC_HC_HOST_CTRL1          0x28
+#define SD_MMC_HC_POWER_CTRL          0x29
+#define SD_MMC_HC_BLK_GAP_CTRL        0x2A
+#define SD_MMC_HC_WAKEUP_CTRL         0x2B
+#define SD_MMC_HC_CLOCK_CTRL          0x2C
+#define SD_MMC_HC_TIMEOUT_CTRL        0x2E
+#define SD_MMC_HC_SW_RST              0x2F
+#define SD_MMC_HC_NOR_INT_STS         0x30
+#define SD_MMC_HC_ERR_INT_STS         0x32
+#define SD_MMC_HC_NOR_INT_STS_EN      0x34
+#define SD_MMC_HC_ERR_INT_STS_EN      0x36
+#define SD_MMC_HC_NOR_INT_SIG_EN      0x38
+#define SD_MMC_HC_ERR_INT_SIG_EN      0x3A
+#define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C
+#define SD_MMC_HC_HOST_CTRL2          0x3E
+#define SD_MMC_HC_CAP                 0x40
+#define SD_MMC_HC_MAX_CURRENT_CAP     0x48
+#define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50
+#define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52
+#define SD_MMC_HC_ADMA_ERR_STS        0x54
+#define SD_MMC_HC_ADMA_SYS_ADDR       0x58
+#define SD_MMC_HC_PRESET_VAL          0x60
+#define SD_MMC_HC_SHARED_BUS_CTRL     0xE0
+#define SD_MMC_HC_SLOT_INT_STS        0xFC
+#define SD_MMC_HC_CTRL_VER            0xFE
+
+//
+// The transfer modes supported by SD Host Controller
+// Simplified Spec 3.0 Table 1-2
+//
+typedef enum {
+  SdMmcNoData,
+  SdMmcPioMode,
+  SdMmcSdmaMode,
+  SdMmcAdmaMode
+} SD_MMC_HC_TRANSFER_MODE;
+
+//
+// The maximum data length of each descriptor line
+//
+#define ADMA_MAX_DATA_PER_LINE     0x10000
+
+typedef struct {
+  UINT32 Valid:1;
+  UINT32 End:1;
+  UINT32 Int:1;
+  UINT32 Reserved:1;
+  UINT32 Act:2;
+  UINT32 Reserved1:10;
+  UINT32 Length:16;
+  UINT32 Address;
+} SD_MMC_HC_ADMA_DESC_LINE;
+
+#define SD_MMC_SDMA_BOUNDARY          512 * 1024
+#define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
+
+typedef struct {
+  UINT8    FirstBar:3;        // bit 0:2
+  UINT8    Reserved:1;        // bit 3
+  UINT8    SlotNum:3;         // bit 4:6
+  UINT8    Reserved1:1;       // bit 7
+} SD_MMC_HC_SLOT_INFO;
+
+typedef struct {
+  UINT32   TimeoutFreq:6;     // bit 0:5
+  UINT32   Reserved:1;        // bit 6
+  UINT32   TimeoutUnit:1;     // bit 7
+  UINT32   BaseClkFreq:8;     // bit 8:15
+  UINT32   MaxBlkLen:2;       // bit 16:17
+  UINT32   BusWidth8:1;       // bit 18
+  UINT32   Adma2:1;           // bit 19
+  UINT32   Reserved2:1;       // bit 20
+  UINT32   HighSpeed:1;       // bit 21
+  UINT32   Sdma:1;            // bit 22
+  UINT32   SuspRes:1;         // bit 23
+  UINT32   Voltage33:1;       // bit 24
+  UINT32   Voltage30:1;       // bit 25
+  UINT32   Voltage18:1;       // bit 26
+  UINT32   Reserved3:1;       // bit 27
+  UINT32   SysBus64:1;        // bit 28
+  UINT32   AsyncInt:1;        // bit 29
+  UINT32   SlotType:2;        // bit 30:31
+  UINT32   Sdr50:1;           // bit 32
+  UINT32   Sdr104:1;          // bit 33
+  UINT32   Ddr50:1;           // bit 34
+  UINT32   Reserved4:1;       // bit 35
+  UINT32   DriverTypeA:1;     // bit 36
+  UINT32   DriverTypeC:1;     // bit 37
+  UINT32   DriverTypeD:1;     // bit 38
+  UINT32   DriverType4:1;     // bit 39
+  UINT32   TimerCount:4;      // bit 40:43
+  UINT32   Reserved5:1;       // bit 44
+  UINT32   TuningSDR50:1;     // bit 45
+  UINT32   RetuningMod:2;     // bit 46:47
+  UINT32   ClkMultiplier:8;   // bit 48:55
+  UINT32   Reserved6:7;       // bit 56:62
+  UINT32   Hs400:1;           // bit 63
+} SD_MMC_HC_SLOT_CAP;
+
+/**
+  Dump the content of SD/MMC host controller's Capability Register.
+
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[in]  Capability      The buffer to store the capability data.
+
+**/
+VOID
+DumpCapabilityReg (
+  IN UINT8                Slot,
+  IN SD_MMC_HC_SLOT_CAP   *Capability
+  );
+
+/**
+  Read SlotInfo register from SD/MMC host controller pci config space.
+
+  @param[in]  PciIo        The PCI IO protocol instance.
+  @param[out] FirstBar     The buffer to store the first BAR value.
+  @param[out] SlotNum      The buffer to store the supported slot number.
+
+  @retval EFI_SUCCESS      The operation succeeds.
+  @retval Others           The operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcGetSlotInfo (
+  IN     EFI_PCI_IO_PROTOCOL   *PciIo,
+     OUT UINT8                 *FirstBar,
+     OUT UINT8                 *SlotNum
+  );
+
+/**
+  Read/Write specified SD/MMC host controller mmio register.
+
+  @param[in]      PciIo        The PCI IO protocol instance.
+  @param[in]      BarIndex     The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in]      Offset       The offset within the selected BAR to start the
+                               memory operation.
+  @param[in]      Read         A boolean to indicate it's read or write operation.
+  @param[in]      Count        The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in, out] Data         For read operations, the destination buffer to store
+                               the results. For write operations, the source buffer
+                               to write data from. The caller is responsible for
+                               having ownership of the data buffer and ensuring its
+                               size not less than Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The read/write operation succeeds.
+  @retval Others                The read/write operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcRwMmio (
+  IN     EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN     UINT8                 BarIndex,
+  IN     UINT32                Offset,
+  IN     BOOLEAN               Read,
+  IN     UINT8                 Count,
+  IN OUT VOID                  *Data
+  );
+
+/**
+  Do OR operation with the value of the specified SD/MMC host controller mmio register.
+
+  @param[in] PciIo             The PCI IO protocol instance.
+  @param[in] BarIndex          The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in] Offset            The offset within the selected BAR to start the
+                               memory operation.
+  @param[in] Count             The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in] OrData            The pointer to the data used to do OR operation.
+                               The caller is responsible for having ownership of
+                               the data buffer and ensuring its size not less than
+                               Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The OR operation succeeds.
+  @retval Others                The OR operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcOrMmio (
+  IN  EFI_PCI_IO_PROTOCOL      *PciIo,
+  IN  UINT8                    BarIndex,
+  IN  UINT32                   Offset,
+  IN  UINT8                    Count,
+  IN  VOID                     *OrData
+  );
+
+/**
+  Do AND operation with the value of the specified SD/MMC host controller mmio register.
+
+  @param[in] PciIo             The PCI IO protocol instance.
+  @param[in] BarIndex          The BAR index of the standard PCI Configuration
+                               header to use as the base address for the memory
+                               operation to perform.
+  @param[in] Offset            The offset within the selected BAR to start the
+                               memory operation.
+  @param[in] Count             The width of the mmio register in bytes.
+                               Must be 1, 2 , 4 or 8 bytes.
+  @param[in] AndData           The pointer to the data used to do AND operation.
+                               The caller is responsible for having ownership of
+                               the data buffer and ensuring its size not less than
+                               Count bytes.
+
+  @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
+  @retval EFI_SUCCESS           The AND operation succeeds.
+  @retval Others                The AND operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcAndMmio (
+  IN  EFI_PCI_IO_PROTOCOL      *PciIo,
+  IN  UINT8                    BarIndex,
+  IN  UINT32                   Offset,
+  IN  UINT8                    Count,
+  IN  VOID                     *AndData
+  );
+
+/**
+  Wait for the value of the specified MMIO register set to the test value.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  BarIndex      The BAR index of the standard PCI Configuration
+                            header to use as the base address for the memory
+                            operation to perform.
+  @param[in]  Offset        The offset within the selected BAR to start the
+                            memory operation.
+  @param[in]  Count         The width of the mmio register in bytes.
+                            Must be 1, 2, 4 or 8 bytes.
+  @param[in]  MaskValue     The mask value of memory.
+  @param[in]  TestValue     The test value of memory.
+  @param[in]  Timeout       The time out value for wait memory set, uses 1
+                            microsecond as a unit.
+
+  @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
+                            range.
+  @retval EFI_SUCCESS       The MMIO register has expected value.
+  @retval Others            The MMIO operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+SdMmcHcWaitMmioSet (
+  IN  EFI_PCI_IO_PROTOCOL       *PciIo,
+  IN  UINT8                     BarIndex,
+  IN  UINT32                    Offset,
+  IN  UINT8                     Count,
+  IN  UINT64                    MaskValue,
+  IN  UINT64                    TestValue,
+  IN  UINT64                    Timeout
+  );
+
+/**
+  Software reset the specified SD/MMC host controller.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The software reset executes successfully.
+  @retval Others            The software reset fails.
+
+**/
+EFI_STATUS
+SdMmcHcReset (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  );
+
+/**
+  Set all interrupt status bits in Normal and Error Interrupt Status Enable
+  register.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The operation executes successfully.
+  @retval Others            The operation fails.
+
+**/
+EFI_STATUS
+SdMmcHcEnableInterrupt (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  );
+
+/**
+  Get the capability data from the specified slot.
+
+  @param[in]  PciIo           The PCI IO protocol instance.
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[out] Capability      The buffer to store the capability data.
+
+  @retval EFI_SUCCESS         The operation executes successfully.
+  @retval Others              The operation fails.
+
+**/
+EFI_STATUS
+SdMmcHcGetCapability (
+  IN     EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN     UINT8                Slot,
+     OUT SD_MMC_HC_SLOT_CAP   *Capability
+  );
+
+/**
+  Get the maximum current capability data from the specified slot.
+
+  @param[in]  PciIo           The PCI IO protocol instance.
+  @param[in]  Slot            The slot number of the SD card to send the command to.
+  @param[out] MaxCurrent      The buffer to store the maximum current capability data.
+
+  @retval EFI_SUCCESS         The operation executes successfully.
+  @retval Others              The operation fails.
+
+**/
+EFI_STATUS
+SdMmcHcGetMaxCurrent (
+  IN     EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN     UINT8                Slot,
+     OUT UINT64               *MaxCurrent
+  );
+
+/**
+  Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
+  slot.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
+
+  @param[in]  PciIo         The PCI IO protocol instance.
+  @param[in]  Slot          The slot number of the SD card to send the command to.
+  @param[out] MediaPresent  The pointer to the media present boolean value.
+
+  @retval EFI_SUCCESS       There is no media change happened.
+  @retval EFI_MEDIA_CHANGED There is media change happened.
+  @retval Others            The detection fails.
+
+**/
+EFI_STATUS
+SdMmcHcCardDetect (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+     OUT BOOLEAN            *MediaPresent
+  );
+
+/**
+  Stop SD/MMC card clock.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
+  @retval Others            Fail to stop SD/MMC clock.
+
+**/
+EFI_STATUS
+SdMmcHcStopClock (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  );
+
+/**
+  SD/MMC card clock supply.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The clock is supplied successfully.
+  @retval Others            The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+SdMmcHcClockSupply (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT64                 ClockFreq,
+  IN SD_MMC_HC_SLOT_CAP     Capability
+  );
+
+/**
+  SD/MMC bus power control.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] PowerCtrl      The value setting to the power control register.
+
+  @retval TRUE              There is a SD/MMC card attached.
+  @retval FALSE             There is no a SD/MMC card attached.
+
+**/
+EFI_STATUS
+SdMmcHcPowerControl (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT8                  PowerCtrl
+  );
+
+/**
+  Set the SD/MMC bus width.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
+
+  @retval EFI_SUCCESS       The bus width is set successfully.
+  @retval Others            The bus width isn't set successfully.
+
+**/
+EFI_STATUS
+SdMmcHcSetBusWidth (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN UINT16                 BusWidth
+  );
+
+/**
+  Supply SD/MMC card with lowest clock frequency at initialization.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The clock is supplied successfully.
+  @retval Others            The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+SdMmcHcInitClockFreq (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN SD_MMC_HC_SLOT_CAP     Capability
+  );
+
+/**
+  Supply SD/MMC card with maximum voltage at initialization.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The voltage is supplied successfully.
+  @retval Others            The voltage isn't supplied successfully.
+
+**/
+EFI_STATUS
+SdMmcHcInitPowerVoltage (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN SD_MMC_HC_SLOT_CAP     Capability
+  );
+
+/**
+  Initialize the Timeout Control register with most conservative value at initialization.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+
+  @retval EFI_SUCCESS       The timeout control register is configured successfully.
+  @retval Others            The timeout control register isn't configured successfully.
+
+**/
+EFI_STATUS
+SdMmcHcInitTimeoutCtrl (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot
+  );
+
+/**
+  Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
+  at initialization.
+
+  @param[in] PciIo          The PCI IO protocol instance.
+  @param[in] Slot           The slot number of the SD card to send the command to.
+  @param[in] Capability     The capability of the slot.
+
+  @retval EFI_SUCCESS       The host controller is initialized successfully.
+  @retval Others            The host controller isn't initialized successfully.
+
+**/
+EFI_STATUS
+SdMmcHcInitHost (
+  IN EFI_PCI_IO_PROTOCOL    *PciIo,
+  IN UINT8                  Slot,
+  IN SD_MMC_HC_SLOT_CAP     Capability
+  );
+
+#endif
diff --git a/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Drivers/SdMmc/XenonDxe/XenonSdhci.c
new file mode 100755
index 0000000..31f207e
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/XenonSdhci.c
@@ -0,0 +1,665 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "XenonSdhci.h"
+
+STATIC
+VOID
+XenonReadVersion (
+  IN  EFI_PCI_IO_PROTOCOL   *PciIo,
+  OUT UINT32 *ControllerVersion
+  )
+{
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CTRL_VER, TRUE, SDHC_REG_SIZE_2B, ControllerVersion);
+}
+
+STATIC
+VOID
+XenonSetFifo (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo
+  )
+{
+  UINTN Data;
+
+  // Set FIFO_RTC, FIFO_WTC, FIFO_CS and FIFO_PDLVMC
+  Data = SDHC_SLOT_FIFO_DEFAULT_CONFIG;
+
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, SDHC_REG_SIZE_4B, &Data);
+}
+
+// Auto Clock Gating
+STATIC
+VOID
+XenonSetAcg (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN BOOLEAN Enable
+  )
+{
+  UINT32 Var;
+
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, SDHC_REG_SIZE_4B, &Var);
+
+  if (Enable) {
+    Var &= ~AUTO_CLKGATE_DISABLE_MASK;
+  } else {
+    Var |= AUTO_CLKGATE_DISABLE_MASK;
+  }
+
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, SDHC_REG_SIZE_4B, &Var);
+}
+
+STATIC
+VOID
+XenonSetSlot (
+  IN EFI_PCI_IO_PROTOCOL *PciIo,
+  IN UINT8 Slot,
+  IN BOOLEAN Enable
+  )
+{
+  UINT32 Var;
+
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, TRUE, SDHC_REG_SIZE_4B, &Var);
+  if (Enable) {
+    Var |= ((0x1 << Slot) << SLOT_ENABLE_SHIFT);
+  } else {
+    Var &= ~((0x1 << Slot) << SLOT_ENABLE_SHIFT);
+  }
+
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SYS_OP_CTRL, FALSE, SDHC_REG_SIZE_4B, &Var);
+}
+
+//
+// Stub function, which will in future be responsible for
+// setting SDIO controller in either HIGH (if Voltage parameter
+// is equal 1) or LOW (if Voltage is equal 0)
+//
+STATIC
+VOID
+XenonSetSdio (
+  IN EFI_PCI_IO_PROTOCOL *PciIo,
+  IN UINTN Voltage
+  )
+{
+  // Currently SDIO isn't supported
+  return;
+}
+
+STATIC
+VOID
+XenonSetPower (
+  IN EFI_PCI_IO_PROTOCOL *PciIo,
+  IN UINT32 Vcc,
+  IN UINT32 Vccq,
+  IN UINT8 Mode
+  )
+{
+  UINT8 Pwr = 0;
+  UINT32 Ctrl = 0;
+
+  // Below statement calls routine to set voltage for SDIO devices in either HIGH (1) or LOW (0) mode
+  switch (Vcc) {
+  case MMC_VDD_165_195:
+    Pwr = SDHCI_POWER_180;
+    if (Mode == XENON_MMC_MODE_SD_SDIO) {
+      XenonSetSdio (PciIo, 0);
+    }
+    break;
+  case MMC_VDD_29_30:
+  case MMC_VDD_30_31:
+    Pwr = SDHCI_POWER_300;
+    if (Mode == XENON_MMC_MODE_SD_SDIO) {
+      XenonSetSdio (PciIo, 1);
+    }
+    break;
+  case MMC_VDD_32_33:
+  case MMC_VDD_33_34:
+    Pwr = SDHCI_POWER_330;
+    if (Mode == XENON_MMC_MODE_SD_SDIO) {
+      XenonSetSdio (PciIo, 1);
+    }
+    break;
+  default:
+    DEBUG((DEBUG_ERROR, "SD/MMC: Does not support power mode(0x%X)\n", Vcc));
+    break;
+  }
+
+  if (Pwr == 0) {
+    SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_POWER_CTRL, FALSE, SDHC_REG_SIZE_1B, &Pwr);
+    return;
+  }
+
+  Pwr |= SDHCI_POWER_ON;
+
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX,SD_MMC_HC_POWER_CTRL, FALSE, SDHC_REG_SIZE_1B, &Pwr);
+
+  // Set VCCQ
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, TRUE, SDHC_REG_SIZE_4B, &Ctrl);
+  Ctrl |= Vccq;
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_eMMC_CTRL, FALSE, SDHC_REG_SIZE_4B, &Ctrl);
+}
+
+UINTN
+XenonSetClk (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN SD_MMC_HC_PRIVATE_DATA *Private,
+  IN UINT32 Clock
+  )
+{
+  UINT32 Div;
+  UINT32 Clk;
+  UINT32 Retry;
+  UINT16 Value = 0;
+
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &Value);
+
+  if (Clock == 0) {
+    return 0;
+  }
+
+  if (Private->ControllerVersion >= SDHCI_SPEC_300) {
+    // Version 3.00 Divisors must be a multiple of 2
+    if (XENON_MMC_MAX_CLK <= Clock) {
+      Div = 1;
+    } else {
+      for (Div = 2; Div < SDHCI_MAX_DIV_SPEC_300; Div += 2) {
+        if ((XENON_MMC_MAX_CLK / Div) <= Clock)
+          break;
+      }
+    }
+  } else {
+    // Version 2.00 Divisors must be a power of 2
+    for (Div = 1; Div < SDHCI_MAX_DIV_SPEC_200; Div *= 2) {
+      if ((XENON_MMC_MAX_CLK / Div) <= Clock)
+        break;
+    }
+  }
+  Div >>= 1;
+
+  Clk = (Div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
+  Clk |= ((Div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT;
+  Clk |= SDHCI_CLOCK_INT_EN;
+
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &Clk);
+
+  //
+  // Poll for internal controller clock to be stabilised
+  // Wait up to 200us for this to occur
+  //
+  Retry = 200;
+
+  do {
+    SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &Clk);
+    if (Retry == 0) {
+      DEBUG((DEBUG_ERROR, "SD/MMC: Internal Clock never stabilised\n"));
+      return -1;
+    }
+
+    Retry--;
+
+    // Wait for internal clock to be stabilised
+    gBS->Stall (1);
+
+  } while (!(Clk & SDHCI_CLOCK_INT_STABLE));
+
+  Clk |= SDHCI_CLOCK_CARD_EN;
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &Clk);
+
+  return 0;
+}
+
+VOID
+XenonPhyInit (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo
+  )
+{
+  UINT32 Var, Wait, Time;
+  UINT32 Clock = XENON_MMC_MAX_CLK;
+  UINT16 ClkCtrl;
+
+  // Need to disable the clock to set EMMC_PHY_TIMING_ADJUST register
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &ClkCtrl);
+  ClkCtrl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &ClkCtrl);
+
+  // Enable QSP PHASE SELECT
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var);
+  Var |= SAMPL_INV_QSP_PHASE_SELECT;
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var);
+
+  // Enable internal clock
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &ClkCtrl);
+  ClkCtrl |= SDHCI_CLOCK_INT_EN;
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &ClkCtrl);
+
+  //
+  // Poll for host MMC PHY clock init to be stable
+  // Wait up to 100us
+  //
+  Time = 100;
+  while (Time--) {
+    SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var);
+    if (Var & SDHCI_CLOCK_INT_STABLE) {
+      break;
+    }
+
+    // Poll interval for MMC PHY clock to be stable is 1us
+    gBS->Stall (1);
+  }
+  if (Time <= 0) {
+    DEBUG((DEBUG_ERROR, "SD/MMC: Failed to enable MMC internal clock in Time\n"));
+    return;
+  }
+
+  // Enable bus clock
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, TRUE, SDHC_REG_SIZE_2B, &ClkCtrl);
+  ClkCtrl |= SDHCI_CLOCK_CARD_EN;
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CLOCK_CTRL, FALSE, SDHC_REG_SIZE_2B, &ClkCtrl);
+
+  // Delay 200us to wait for the completion of bus clock
+  gBS->Stall (200);
+
+  // Init PHY
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var);
+  Var |= PHY_INITIALIZAION;
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var);
+
+  // Add duration of FC_SYNC_RST
+  Wait = ((Var >> FC_SYNC_RST_DURATION_SHIFT) & FC_SYNC_RST_DURATION_MASK);
+
+  // Add interval between FC_SYNC_EN and FC_SYNC_RST
+  Wait += ((Var >> FC_SYNC_RST_EN_DURATION_SHIFT) & FC_SYNC_RST_EN_DURATION_MASK);
+
+  // Add duration of asserting FC_SYNC_EN
+  Wait += ((Var >> FC_SYNC_EN_DURATION_SHIFT) & FC_SYNC_EN_DURATION_MASK);
+
+  // Add duration of Waiting for PHY
+  Wait += ((Var >> WAIT_CYCLE_BEFORE_USING_SHIFT) & WAIT_CYCLE_BEFORE_USING_MASK);
+
+  // 4 addtional bus clock and 4 AXI bus clock are required left shift 20 bits
+  Wait += 8;
+  Wait <<= 20;
+
+  // Use the possibly slowest bus frequency value
+  if (Clock == 0) {
+    Clock = XENON_MMC_MIN_CLK;
+  }
+
+  // Get the Wait Time in unit of ms
+  Wait = Wait / Clock;
+  Wait++;
+
+  // Poll for host eMMC PHY init to complete, wait up to 100us
+  Time = 100;
+  while (Time--) {
+    Var = SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var);
+    Var &= PHY_INITIALIZAION;
+    if (!Var) {
+      break;
+    }
+
+    // Wait for host eMMC PHY init to complete
+    gBS->Stall (1);
+  }
+
+  if (Time <= 0) {
+    DEBUG((DEBUG_ERROR, "SD/MMC: Failed to init MMC PHY in Time\n"));
+    return;
+  }
+
+  return;
+}
+
+STATIC
+VOID
+XenonSetPhy (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo,
+  UINT8 Timing
+  )
+{
+  UINT32 Var = 0;
+
+  // Setup pad, set bit[30], bit[28] and bits[26:24]
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, TRUE, SDHC_REG_SIZE_4B, &Var);
+  Var |= (AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | FC_CMD_RECEN | FC_DQ_RECEN);
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL, FALSE, SDHC_REG_SIZE_4B, &Var);
+
+  //
+  // If Timing belongs to high speed, set bit[17] of
+  // EMMC_PHY_TIMING_ADJUST register
+  //
+  if ((Timing == MMC_TIMING_MMC_HS400) ||
+      (Timing == MMC_TIMING_MMC_HS200) ||
+      (Timing == MMC_TIMING_UHS_SDR50) ||
+      (Timing == MMC_TIMING_UHS_SDR104) ||
+      (Timing == MMC_TIMING_UHS_DDR50) ||
+      (Timing == MMC_TIMING_UHS_SDR25)) {
+
+    SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var);
+
+    // Set SLOW_MODE for PHY
+    Var |= OUTPUT_QSN_PHASE_SELECT | QSN_PHASE_SLOW_MODE_BIT;
+    SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var);
+  }
+
+  SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, SDHC_REG_SIZE_4B, &Var);
+  Var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
+  SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, SDHC_REG_SIZE_4B, &Var);
+
+  if (Timing == MMC_TIMING_MMC_HS400) {
+    SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, TRUE, SDHC_REG_SIZE_4B, &Var);
+    Var &= ~DQ_ASYNC_MODE;
+    SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_FUNC_CONTROL, FALSE, SDHC_REG_SIZE_4B, &Var);
+
+    Var = LOGIC_TIMING_VALUE;
+    SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_LOGIC_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var);
+  }
+
+  XenonPhyInit (PciIo);
+}
+
+STATIC
+VOID
+XenonConfigureInterrupts (
+  IN EFI_PCI_IO_PROTOCOL *PciIo
+  )
+{
+  UINT32 Var;
+
+  // Clear interrupt status
+  Var = SDHC_CLR_ALL_IRQ_MASK;
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, SDHC_REG_SIZE_4B, &Var);
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS, FALSE, SDHC_REG_SIZE_4B, &Var);
+
+  // Enable only interrupts served by the SD controller
+  Var = SDHC_CLR_ALL_IRQ_MASK & ~(NOR_INT_STS_CARD_INS | NOR_INT_STS_CARD_INT);
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_STS_EN, FALSE, SDHC_REG_SIZE_4B, &Var);
+
+  // Mask all sdhci interrupt sources
+  Var = SDHC_CLR_ALL_IRQ_MASK & ~NOR_INT_SIG_EN_CARD_INT;
+  SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_NOR_INT_SIG_EN, FALSE, SDHC_REG_SIZE_4B, &Var);
+}
+
+// Enable Parallel Transfer Mode
+STATIC
+VOID
+XenonSetParallelTransfer (
+  IN EFI_PCI_IO_PROTOCOL *PciIo,
+  IN UINT8 Slot,
+  IN BOOLEAN Enable
+  )
+{
+  UINT32 Var;
+
+  SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, TRUE, SDHC_REG_SIZE_4B, &Var);
+
+  if (Enable) {
+    Var |= (0x1 << Slot);
+  } else {
+    Var &= ~(0x1 << Slot);
+  }
+
+  SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SYS_EXT_OP_CTRL, FALSE, SDHC_REG_SIZE_4B, &Var);
+}
+
+STATIC
+VOID
+XenonSetTuning (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN UINT8 Slot,
+  IN BOOLEAN Enable
+  )
+{
+  UINT32 Var;
+
+  // Set the Re-Tuning Request functionality
+  SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, TRUE, SDHC_REG_SIZE_4B, &Var);
+
+  if (Enable) {
+    Var |= RETUNING_COMPATIBLE;
+  } else {
+    Var &= ~RETUNING_COMPATIBLE;
+  }
+
+  SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHC_SLOT_RETUNING_REQ_CTRL, FALSE, SDHC_REG_SIZE_4B, &Var);
+
+  // Set the Re-tuning Event Signal Enable
+  SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, TRUE, SDHC_REG_SIZE_4B, &Var);
+
+  if (Enable) {
+    Var |= SDHCI_RETUNE_EVT_INTSIG;
+  } else {
+    Var &= ~SDHCI_RETUNE_EVT_INTSIG;
+  }
+
+  SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, SDHCI_SIGNAL_ENABLE, FALSE, SDHC_REG_SIZE_4B, &Var);
+}
+
+VOID
+XenonReset (
+  IN SD_MMC_HC_PRIVATE_DATA *Private,
+  IN UINT8 Slot,
+  IN UINT8 Mask
+  )
+{
+  UINT32 Retry = 1000;
+  UINT8 SwReset;
+
+  SwReset = Mask;
+
+  SdMmcHcRwMmio (
+          Private->PciIo,
+          Slot,
+          SD_MMC_HC_SW_RST,
+          FALSE,
+          sizeof (SwReset),
+          &SwReset
+        );
+
+  SdMmcHcRwMmio (
+          Private->PciIo,
+          Slot,
+          SD_MMC_HC_SW_RST,
+          TRUE,
+          sizeof (SwReset),
+          &SwReset
+        );
+
+  while (SwReset & Mask) {
+    if (Retry == 0) {
+      DEBUG((DEBUG_ERROR, "SD/MMC: Reset never completed\n"));
+      return;
+    }
+
+    Retry--;
+
+    // Poll interval for SwReset is 100us according to SDHCI spec
+    gBS-> Stall (100);
+    SdMmcHcRwMmio (
+            Private->PciIo,
+            Slot,
+            SD_MMC_HC_SW_RST,
+            TRUE,
+            sizeof (SwReset),
+            &SwReset
+          );
+  }
+}
+
+STATIC
+VOID
+XenonTransferPio (
+  IN SD_MMC_HC_PRIVATE_DATA *Private,
+  IN UINT8 Slot,
+  IN OUT VOID *Buffer,
+  IN UINT16 BlockSize,
+  IN BOOLEAN Read
+  )
+{
+  UINTN Index;
+  UINT8 *Offs;
+
+  //
+  // SD stack's intrinsic functions cannot perform properly reading/writing from
+  // buffer register, that is why MmioRead/MmioWrite are used. It is temporary
+  // solution.
+  //
+  for (Index = 0; Index < BlockSize; Index += 4) {
+    Offs = Buffer + Index;
+    if (Read) {
+      *(UINT32 *)Offs = MmioRead32 (SDHC_DAT_BUF_PORT_ADDR);
+    } else {
+      MmioWrite32 (SDHC_DAT_BUF_PORT_ADDR, *(UINT32 *)Offs);
+    }
+  }
+}
+
+EFI_STATUS
+XenonTransferData (
+  IN SD_MMC_HC_PRIVATE_DATA *Private,
+  IN UINT8 Slot,
+  IN OUT VOID *Buffer,
+  IN UINT32 DataLen,
+  IN UINT16 BlockSize,
+  IN UINT16 Blocks,
+  IN BOOLEAN Read
+  )
+{
+  UINT32 IntStatus, PresentState, Rdy, Mask, Retry, Block = 0;
+
+  if (Buffer == NULL) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  Retry = SDHC_INT_STATUS_POLL_RETRY_DATA_TRAN;
+  Rdy = NOR_INT_STS_TX_RDY | NOR_INT_STS_RX_RDY;
+  Mask = PRESENT_STATE_BUFFER_RD_EN | PRESENT_STATE_BUFFER_WR_EN;
+
+  do {
+    SdMmcHcRwMmio (
+            Private->PciIo,
+            Slot,
+            SD_MMC_HC_NOR_INT_STS,
+            TRUE,
+            sizeof (IntStatus),
+            &IntStatus
+          );
+
+    if (IntStatus & NOR_INT_STS_ERR_INT) {
+      DEBUG((DEBUG_INFO, "SD/MMC: Error detected in status %0x\n", IntStatus));
+      return EFI_DEVICE_ERROR;
+    }
+
+    if (IntStatus & Rdy) {
+      SdMmcHcRwMmio (
+              Private->PciIo,
+              Slot,
+              SD_MMC_HC_PRESENT_STATE,
+              TRUE,
+              sizeof (PresentState),
+              &PresentState
+            );
+
+      if (!(PresentState & Mask)) {
+        continue;
+      }
+
+      SdMmcHcRwMmio (
+              Private->PciIo,
+              Slot,
+              SD_MMC_HC_NOR_INT_STS,
+              FALSE,
+              sizeof (Rdy),
+              &Rdy
+            );
+
+      XenonTransferPio (Private, Slot, Buffer, BlockSize, Read);
+
+      Buffer += BlockSize;
+      if (++Block >= Blocks) {
+        break;
+      }
+    }
+
+    if (Retry-- > 0) {
+
+      // Poll interval for data transfer complete bit in NOR_INT_STS register is 10us
+      gBS->Stall (10);
+    } else {
+      DEBUG((DEBUG_INFO, "SD/MMC: Transfer data timeout\n"));
+      return EFI_TIMEOUT;
+    }
+  } while (!(IntStatus & NOR_INT_STS_XFER_COMPLETE));
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+XenonInit (
+  IN SD_MMC_HC_PRIVATE_DATA *Private
+  )
+{
+  EFI_PCI_IO_PROTOCOL *PciIo = Private->PciIo;
+
+  // Read XENON version
+  XenonReadVersion (PciIo, &Private->ControllerVersion);
+
+  XenonSetFifo (PciIo);
+
+  // Disable auto clock generator
+  XenonSetAcg (PciIo, FALSE);
+
+  // XENON has only one port
+  XenonSetSlot (PciIo, XENON_MMC_SLOT_ID, TRUE);
+
+  XenonSetPower (PciIo, MMC_VDD_165_195, eMMC_VCCQ_1_8V, XENON_MMC_MODE_SD_SDIO);
+
+  // Set MAX_CLOCK for configuring PHY
+  XenonSetClk (PciIo, Private, XENON_MMC_MAX_CLK);
+  XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50);
+
+  XenonConfigureInterrupts (PciIo);
+
+  // Enable parallel transfer
+  XenonSetParallelTransfer (PciIo, XENON_MMC_SLOT_ID, TRUE);
+  XenonSetTuning (PciIo, XENON_MMC_SLOT_ID, FALSE);
+
+  // Enable auto clock generator
+  XenonSetAcg (PciIo, TRUE);
+
+  // Set proper clock for PHY configuration
+  XenonSetClk (PciIo, Private, XENON_MMC_BASE_CLK);
+  XenonPhyInit (PciIo);
+
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Drivers/SdMmc/XenonDxe/XenonSdhci.h
new file mode 100644
index 0000000..2be0ee6
--- /dev/null
+++ b/Drivers/SdMmc/XenonDxe/XenonSdhci.h
@@ -0,0 +1,346 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "SdMmcPciHcDxe.h"
+
+#include <Library/IoLib.h>
+
+#define SD_BAR_INDEX 0
+
+#define SIZE_512B    0x200
+
+/* Register Offset of SD Host Controller SOCP self-defined register */
+
+#define SDHC_IPID                     0x0100
+#define SDHC_SYS_CFG_INFO             0x0104
+#define SLOT_TYPE_SDIO_SHIFT          24
+#define SLOT_TYPE_EMMC_MASK           0xff
+#define SLOT_TYPE_EMMC_SHIFT          16
+#define SLOT_TYPE_SD_SDIO_MMC_MASK    0xff
+#define SLOT_TYPE_SD_SDIO_MMC_SHIFT   8
+
+#define SDHC_SYS_OP_CTRL              0x0108
+#define AUTO_CLKGATE_DISABLE_MASK     (0x1<<20)
+#define SDCLK_IDLEOFF_ENABLE_SHIFT    8
+#define SLOT_ENABLE_SHIFT             0
+
+#define SDHC_SYS_EXT_OP_CTRL          0x010c
+#define SDHC_TEST_OUT                 0x0110
+#define SDHC_TESTOUT_MUXSEL           0x0114
+
+#define SDHC_SLOT_EXT_INT_STATUS      0x0120
+#define SDHC_SLOT_EXT_ERR_STATUS      0x0122
+#define SDHC_SLOT_EXT_INT_STATUS_EN   0x0124
+#define SDHC_SLOT_EXT_ERR_STATUS_EN   0x0126
+
+#define SDHC_SLOT_OP_STATUS_CTRL      0x0128
+#define TUNING_PROG_FIXED_DELAY_MASK  0x7ff
+#define FORCE_SEL_INVERSE_CLK_SHIFT   11
+
+#define SDHC_SLOT_FIFO_CTRL           0x012c
+#define SDHC_SLOT_FIFO_DEFAULT_CONFIG 0x315
+
+#define SDHC_SLOT_eMMC_CTRL           0x0130
+#define ENABLE_DATA_STROBE_SHIFT      24
+#define SET_EMMC_RSTN_SHIFT           16
+#define eMMC_VCCQ_MASK                0x3
+#define eMMC_VCCQ_1_8V                0x1
+#define eMMC_VCCQ_1_2V                0x2
+#define eMMC_VCCQ_3_3V                0x3
+
+#define SDHC_SLOT_OUTPUT_DLY_CTRL     0x0134
+#define SDHC_SLOT_DCM_CTRL            0x0137
+
+#define SDHC_SLOT_DLL_CTRL            0x0138
+#define SELECT_DEF_DLL                0x1
+
+#define SDHC_SLOT_DLL_PHASE_SEL       0x013c
+#define DLL_UPDATE_STROBE             7
+
+#define SDHC_SLOT_STROBE_DLY_CTRL     0x0140
+#define STROBE_DELAY_FIXED_MASK       0xffff
+
+#define SDHC_SLOT_RETUNING_REQ_CTRL   0x0144
+#define RETUNING_COMPATIBLE           0x1
+
+#define SDHC_SLOT_AUTO_RETUNING_CTRL  0x0148
+#define ENABLE_AUTO_RETUNING          0x1
+
+#define SDHC_SLOT_EXT_PRESENT_STATE   0x014c
+#define SDHC_SLOT_DLL_CUR_DLY_VAL     0x0150
+#define SDHC_SLOT_TUNING_CUR_DLY_VAL  0x0154
+#define SDHC_SLOT_STROBE_CUR_DLY_VAL  0x0158
+#define SDHC_SLOT_SUB_CMD_STRL        0x015c
+
+#define SDHC_SLOT_CQ_TASK_INFO        0x0160
+
+#define SDHC_SLOT_TUNING_DEBUG_INFO   0x01f0
+#define SDHC_SLOT_DATAIN_DEBUG_INFO   0x01f4
+
+#define SDHC_CMD_RESET_BIT            (1 << 1)
+#define SDHC_DATA_RESET_BIT           (1 << 2)
+
+#define SDHC_CMD_INHIBIT              (1 << 0)
+#define SDHC_DATA_INHIBIT             (1 << 1)
+
+#define SDHC_REG_SIZE_1B              1
+#define SDHC_REG_SIZE_2B              2
+#define SDHC_REG_SIZE_4B              4
+
+#define SDHC_DAT_BUF_PORT_ADDR        0xF06E0020
+
+/* Command register bits description */
+#define RESP_TYPE_136_BITS            (1 << 0)
+#define RESP_TYPE_48_BITS             (1 << 1)
+#define RESP_TYPE_48_BITS_NO_CRC      ((1 << 0) | (1 << 1))
+#define CMD_CRC_CHK_EN                (1 << 3)
+#define CMD_INDEX_CHK_EN              (1 << 4)
+#define DATA_PRESENT                  (1 << 5)
+
+/* Transfer mode register bits description */
+#define SDHC_TRNS_BLK_CNT_EN          (1 << 1)
+#define SDHC_TRNS_MULTI_BLK_SEL       (1 << 5)
+#define SDHC_TRNS_TO_HOST_DIR         (1 << 4)
+
+/* Block size register bits description */
+#define BLK_SIZE_HOST_DMA_BDRY_OFFSET 12
+#define BLK_SIZE_512KB                0x7
+
+/* Int status register bits description */
+#define NOR_INT_STS_CMD_COMPLETE      (1 << 0)
+#define NOR_INT_STS_XFER_COMPLETE     (1 << 1)
+#define NOR_INT_STS_TX_RDY            (1 << 4)
+#define NOR_INT_STS_RX_RDY            (1 << 5)
+#define NOR_INT_STS_CARD_INS          (1 << 6)
+#define NOR_INT_STS_CARD_INT          (1 << 8)
+#define NOR_INT_STS_ERR_INT           (1 << 15)
+#define ERR_INT_STS_CMD_TIMEOUT_ERR   (1 << 16)
+#define ERR_INT_STS_DATA_TIMEOUT_ERR  (1 << 20)
+
+#define NOR_INT_SIG_EN_CARD_INT       (1 << 8)
+
+#define PRESENT_STATE_BUFFER_RD_EN    (1 << 11)
+#define PRESENT_STATE_BUFFER_WR_EN    (1 << 10)
+
+#define SDHC_CLR_IRQ_STS_MASK         0xFFFF
+#define SDHC_CLR_ALL_IRQ_MASK         0xFFFFFFFFUL
+
+/* Max clock in Hz */
+#define XENON_MMC_MAX_CLK             400000000
+#define XENON_MMC_CLK_RATIO           2046
+#define XENON_MMC_BASE_CLK            XENON_MMC_MAX_CLK / XENON_MMC_CLK_RATIO
+#define XENON_MMC_MIN_CLK             100000
+
+#define XENON_MMC_CMD_MAX_TIMEOUT     3200
+#define XENON_MMC_CMD_DEFAULT_TIMEOUT 100
+
+/* Tuning Parameter */
+#define TMR_RETUN_NO_PRESENT          0xf
+#define XENON_MAX_TUN_COUNT           0xb
+
+#define EMMC_PHY_REG_BASE                 0x170
+#define EMMC_PHY_TIMING_ADJUST            EMMC_PHY_REG_BASE
+#define OUTPUT_QSN_PHASE_SELECT           (1 << 17)
+#define SAMPL_INV_QSP_PHASE_SELECT        (1 << 18)
+#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT  18
+#define PHY_INITIALIZAION                 (1 << 31)
+#define WAIT_CYCLE_BEFORE_USING_MASK      0xf
+#define WAIT_CYCLE_BEFORE_USING_SHIFT     12
+#define FC_SYNC_EN_DURATION_MASK          0xf
+#define FC_SYNC_EN_DURATION_SHIFT         8
+#define FC_SYNC_RST_EN_DURATION_MASK      0xf
+#define FC_SYNC_RST_EN_DURATION_SHIFT     4
+#define FC_SYNC_RST_DURATION_MASK         0xf
+#define FC_SYNC_RST_DURATION_SHIFT        0
+
+#define EMMC_PHY_FUNC_CONTROL     (EMMC_PHY_REG_BASE + 0x4)
+#define DQ_ASYNC_MODE             (1 << 4)
+#define DQ_DDR_MODE_SHIFT         8
+#define DQ_DDR_MODE_MASK          0xff
+#define CMD_DDR_MODE              (1 << 16)
+
+#define EMMC_PHY_PAD_CONTROL      (EMMC_PHY_REG_BASE + 0x8)
+#define REC_EN_SHIFT              24
+#define REC_EN_MASK               0xf
+#define FC_DQ_RECEN               (1 << 24)
+#define FC_CMD_RECEN              (1 << 25)
+#define FC_QSP_RECEN              (1 << 26)
+#define FC_QSN_RECEN              (1 << 27)
+#define OEN_QSN                   (1 << 28)
+#define AUTO_RECEN_CTRL           (1 << 30)
+
+#define EMMC_PHY_PAD_CONTROL1        (EMMC_PHY_REG_BASE + 0xc)
+#define EMMC_PHY_PAD_CONTROL2        (EMMC_PHY_REG_BASE + 0x10)
+#define EMMC_PHY_DLL_CONTROL         (EMMC_PHY_REG_BASE + 0x14)
+#define DLL_DELAY_TEST_LOWER_SHIFT   8
+#define DLL_DELAY_TEST_LOWER_MASK    0xff
+#define DLL_BYPASS_EN                0x1
+
+#define EMMC_LOGIC_TIMING_ADJUST       (EMMC_PHY_REG_BASE + 0x18)
+#define EMMC_LOGIC_TIMING_ADJUST_LOW   (EMMC_PHY_REG_BASE + 0x1c)
+
+#define LOGIC_TIMING_VALUE             0x5a54 /* Recommend by HW team */
+
+#define QSN_PHASE_SLOW_MODE_BIT        (1 << 29)
+
+/* XENON only have one slot 0 */
+#define XENON_MMC_SLOT_ID              (0)
+
+#define MMC_TIMING_LEGACY     0
+#define MMC_TIMING_MMC_HS     1
+#define MMC_TIMING_SD_HS      2
+#define MMC_TIMING_UHS_SDR12  3
+#define MMC_TIMING_UHS_SDR25  4
+#define MMC_TIMING_UHS_SDR50  5
+#define MMC_TIMING_UHS_SDR104 6
+#define MMC_TIMING_UHS_DDR50  7
+#define MMC_TIMING_MMC_HS200  8
+#define MMC_TIMING_MMC_HS400  10
+
+/* Data time out default value 0xE: TMCLK x 227 */
+#define DATA_TIMEOUT_DEF_VAL          0xE
+
+/* Max retry count for INT status ready */
+#define SDHC_INT_STATUS_POLL_RETRY              1000
+#define SDHC_INT_STATUS_POLL_RETRY_DATA_TRAN    100000
+
+/* Take 2.5 seconds as generic time out value, 1 microsecond as unit */
+#define SD_GENERIC_TIMEOUT            2500 * 1000
+
+/* SDMA start address should allign with 0x8, align mask 0x7 */
+#define DMA_START_ADDR_ALIGN_MASK 0x7
+
+#define  SDHCI_RETUNE_EVT_INTSIG  0x00001000
+
+/* MMC modes */
+#define XENON_MMC_MODE_EMMC     0
+#define XENON_MMC_MODE_SD_SDIO  1
+
+/* MMC Voltage */
+#define MMC_VDD_165_195   0x00000080  /* VDD voltage 1.65 - 1.95 */
+#define MMC_VDD_20_21     0x00000100  /* VDD voltage 2.0 ~ 2.1 */
+#define MMC_VDD_21_22     0x00000200  /* VDD voltage 2.1 ~ 2.2 */
+#define MMC_VDD_22_23     0x00000400  /* VDD voltage 2.2 ~ 2.3 */
+#define MMC_VDD_23_24     0x00000800  /* VDD voltage 2.3 ~ 2.4 */
+#define MMC_VDD_24_25     0x00001000  /* VDD voltage 2.4 ~ 2.5 */
+#define MMC_VDD_25_26     0x00002000  /* VDD voltage 2.5 ~ 2.6 */
+#define MMC_VDD_26_27     0x00004000  /* VDD voltage 2.6 ~ 2.7 */
+#define MMC_VDD_27_28     0x00008000  /* VDD voltage 2.7 ~ 2.8 */
+#define MMC_VDD_28_29     0x00010000  /* VDD voltage 2.8 ~ 2.9 */
+#define MMC_VDD_29_30     0x00020000  /* VDD voltage 2.9 ~ 3.0 */
+#define MMC_VDD_30_31     0x00040000  /* VDD voltage 3.0 ~ 3.1 */
+#define MMC_VDD_31_32     0x00080000  /* VDD voltage 3.1 ~ 3.2 */
+#define MMC_VDD_32_33     0x00100000  /* VDD voltage 3.2 ~ 3.3 */
+#define MMC_VDD_33_34     0x00200000  /* VDD voltage 3.3 ~ 3.4 */
+#define MMC_VDD_34_35     0x00400000  /* VDD voltage 3.4 ~ 3.5 */
+#define MMC_VDD_35_36     0x00800000  /* VDD voltage 3.5 ~ 3.6 */
+
+/* SDHCI FLAGS */
+#define SDHCI_POWER_ON   0x01
+#define SDHCI_POWER_180  0x0A
+#define SDHCI_POWER_300  0x0C
+#define SDHCI_POWER_330  0x0E
+
+#define SDHCI_DIVIDER_SHIFT     8
+#define SDHCI_DIVIDER_HI_SHIFT  6
+#define SDHCI_DIV_MASK          0xFF
+#define SDHCI_DIV_MASK_LEN      8
+#define SDHCI_DIV_HI_MASK       0x300
+#define SDHCI_CLOCK_CARD_EN     0x0004
+#define SDHCI_CLOCK_INT_STABLE  0x0002
+#define SDHCI_CLOCK_INT_EN      0x0001
+
+#define SDHCI_VENDOR_VER_MASK   0xFF00
+#define SDHCI_VENDOR_VER_SHIFT  8
+#define SDHCI_SPEC_VER_MASK     0x00FF
+#define SDHCI_SPEC_VER_SHIFT    0
+#define SDHCI_SPEC_100          0
+#define SDHCI_SPEC_200          1
+#define SDHCI_SPEC_300          2
+
+#define SDHCI_SIGNAL_ENABLE     0x38
+
+#define SDHCI_MAX_DIV_SPEC_200  256
+#define SDHCI_MAX_DIV_SPEC_300  2046
+
+/* SD DEVICE STATUS FLAGS */
+#define CURRENT_STATE_MASK           (0xF << 9)
+#define CURRENT_STATE_N_READY_MASK   (7 << 9)
+#define READY_FOR_DATA               (1 << 8)
+#define CARD_STATUS_ERROR_MASK       (~0x0206BF7F)
+
+#define RCA_BITS_OFFSET              16
+
+UINTN
+XenonSetClk (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN SD_MMC_HC_PRIVATE_DATA *Private,
+  IN UINT32 Clock
+  );
+
+VOID
+XenonPhyInit (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo
+  );
+
+VOID
+XenonReset (
+  IN SD_MMC_HC_PRIVATE_DATA *Private,
+  IN UINT8 Slot,
+  IN UINT8 Mask
+  );
+
+EFI_STATUS
+XenonTransferData (
+  IN SD_MMC_HC_PRIVATE_DATA *Private,
+  IN UINT8 Slot,
+  IN OUT VOID *Buffer,
+  IN UINT32 DataLen,
+  IN UINT16 BlockSize,
+  IN UINT16 Blocks,
+  IN BOOLEAN Read
+  );
+
+EFI_STATUS
+XenonInit (
+  IN SD_MMC_HC_PRIVATE_DATA *Private
+  );
+
+EFI_STATUS
+SdCardSendStatus (
+  IN  EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN  UINT8                          Slot,
+  IN  UINT16                         Rca,
+  OUT UINT32                         *DevStatus
+  );
diff --git a/Drivers/Spi/Devices/MvSpiFlash.c b/Drivers/Spi/Devices/MvSpiFlash.c
new file mode 100755
index 0000000..9a04493
--- /dev/null
+++ b/Drivers/Spi/Devices/MvSpiFlash.c
@@ -0,0 +1,531 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include "MvSpiFlash.h"
+
+MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol;
+SPI_FLASH_INSTANCE  *mSpiFlashInstance;
+
+STATIC
+VOID
+SpiFlashFormatAddress (
+  IN      UINT32  Address,
+  IN      UINT8   AddrSize,
+  IN OUT  UINT8   *Cmd
+  )
+{
+  if (AddrSize == 4) {
+      Cmd[1] = Address >> 24;
+      Cmd[2] = Address >> 16;
+      Cmd[3] = Address >> 8;
+      Cmd[4] = Address;
+  } else {
+      Cmd[1] = Address >> 16;
+      Cmd[2] = Address >> 8;
+      Cmd[3] = Address;
+  }
+}
+
+STATIC
+EFI_STATUS
+MvSpiFlashReadCmd (
+  IN  SPI_DEVICE *Slave,
+  IN  UINT8 *Cmd,
+  IN  UINTN CmdSize,
+  OUT UINT8 *DataIn,
+  IN  UINTN DataSize
+  )
+{
+  EFI_STATUS Status;
+
+  // Send command and gather response
+  Status = SpiMasterProtocol->ReadWrite (SpiMasterProtocol, Slave, Cmd,
+    CmdSize, NULL, DataIn, DataSize);
+
+  return Status;
+}
+
+STATIC
+EFI_STATUS
+MvSpiFlashWriteEnableCmd (
+  IN  SPI_DEVICE   *Slave
+  )
+{
+  EFI_STATUS Status;
+  UINT8 CmdEn = CMD_WRITE_ENABLE;
+
+  // Send write_enable command
+  Status = SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1,
+    &CmdEn, NULL, SPI_TRANSFER_BEGIN | SPI_TRANSFER_END);
+
+  return Status;
+}
+
+STATIC
+EFI_STATUS
+MvSpiFlashWriteCommon (
+  IN SPI_DEVICE *Slave,
+  IN UINT8 *Cmd,
+  IN UINT32 Length,
+  IN UINT8* Buffer,
+  IN UINT32 BufferLength
+  )
+{
+  UINT8 CmdStatus = CMD_READ_STATUS;
+  UINT8 State;
+  UINT32 Counter = 0xFFFFF;
+  UINT8 poll_bit = STATUS_REG_POLL_WIP;
+  UINT8 check_status = 0x0;
+
+  CmdStatus = (UINT8)PcdGet32 (PcdSpiFlashPollCmd);
+  if (CmdStatus == CMD_FLAG_STATUS) {
+    poll_bit = STATUS_REG_POLL_PEC;
+    check_status = poll_bit;
+  }
+
+  // Send command
+  MvSpiFlashWriteEnableCmd (Slave);
+
+  // Write data
+  SpiMasterProtocol->ReadWrite (SpiMasterProtocol, Slave, Cmd, Length,
+    Buffer, NULL, BufferLength);
+
+  // Poll status register
+  SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, &CmdStatus,
+    NULL, SPI_TRANSFER_BEGIN);
+  do {
+    SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, NULL, &State,
+      0);
+    Counter--;
+    if ((State & poll_bit) == check_status)
+      break;
+  } while (Counter > 0);
+  if (Counter == 0) {
+    DEBUG((DEBUG_ERROR, "SpiFlash: Timeout while writing to spi flash\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  // Deactivate CS
+  SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 0, NULL, NULL, SPI_TRANSFER_END);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+SpiFlashCmdBankaddrWrite (
+  IN SPI_DEVICE *Slave,
+  IN UINT8 BankSel
+  )
+{
+  UINT8 Cmd = CMD_BANK_WRITE;
+
+  MvSpiFlashWriteCommon (Slave, &Cmd, 1, &BankSel, 1);
+}
+
+STATIC
+UINT8
+SpiFlashBank (
+  IN SPI_DEVICE *Slave,
+  IN UINT32 Offset
+  )
+{
+  UINT8 BankSel;
+
+  BankSel = Offset / SPI_FLASH_16MB_BOUN;
+
+  SpiFlashCmdBankaddrWrite (Slave, BankSel);
+
+  return BankSel;
+}
+
+EFI_STATUS
+MvSpiFlashErase (
+  IN SPI_DEVICE *Slave,
+  IN UINTN Offset,
+  IN UINTN Length
+  )
+{
+  EFI_STATUS Status;
+  UINT32 AddrSize, EraseAddr;
+  UINTN EraseSize;
+  UINT8 Cmd[5];
+
+  AddrSize  = PcdGet32 (PcdSpiFlashAddressCycles);
+  EraseSize = PcdGet64 (PcdSpiFlashEraseSize);
+
+  // Check input parameters
+  if (Offset % EraseSize || Length % EraseSize) {
+    DEBUG((DEBUG_ERROR, "SpiFlash: Either erase offset or length "
+      "is not multiple of erase size\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  Cmd[0] = CMD_ERASE_64K;
+  while (Length) {
+    EraseAddr = Offset;
+
+    SpiFlashBank (Slave, EraseAddr);
+
+    SpiFlashFormatAddress (EraseAddr, AddrSize, Cmd);
+
+    // Programm proper erase address
+    Status = MvSpiFlashWriteCommon (Slave, Cmd, AddrSize + 1, NULL, 0);
+      if (EFI_ERROR (Status)) {
+        DEBUG((DEBUG_ERROR, "SpiFlash: Error while programming target address\n"));
+        return Status;
+      }
+
+    Offset += EraseSize;
+    Length -= EraseSize;
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MvSpiFlashRead (
+  IN SPI_DEVICE   *Slave,
+  IN UINT32       Offset,
+  IN UINTN        Length,
+  IN VOID         *Buf
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  UINT8 Cmd[6];
+  UINT32 AddrSize, ReadAddr, ReadLength, RemainLength;
+  UINTN BankSel = 0;
+
+  AddrSize = PcdGet32 (PcdSpiFlashAddressCycles);
+
+  Cmd[0] = CMD_READ_ARRAY_FAST;
+
+  // Sign end of address with 0 byte
+  Cmd[5] = 0;
+
+  while (Length) {
+    ReadAddr = Offset;
+
+    BankSel = SpiFlashBank (Slave, ReadAddr);
+
+    RemainLength = (SPI_FLASH_16MB_BOUN * (BankSel + 1)) - Offset;
+    if (Length < RemainLength) {
+      ReadLength = Length;
+    } else {
+      ReadLength = RemainLength;
+    }
+    SpiFlashFormatAddress (ReadAddr, AddrSize, Cmd);
+    // Program proper read address and read data
+    Status = MvSpiFlashReadCmd (Slave, Cmd, AddrSize + 2, Buf, Length);
+
+    Offset += ReadLength;
+    Length -= ReadLength;
+    Buf += ReadLength;
+  }
+
+  return Status;
+}
+
+EFI_STATUS
+MvSpiFlashWrite (
+  IN SPI_DEVICE *Slave,
+  IN UINT32     Offset,
+  IN UINTN      Length,
+  IN VOID       *Buf
+  )
+{
+  EFI_STATUS Status;
+  UINTN ByteAddr, ChunkLength, ActualIndex, PageSize;
+  UINT32 WriteAddr;
+  UINT8 Cmd[5], AddrSize;
+
+  AddrSize = PcdGet32 (PcdSpiFlashAddressCycles);
+  PageSize = PcdGet32 (PcdSpiFlashPageSize);
+
+  Cmd[0] = CMD_PAGE_PROGRAM;
+
+  for (ActualIndex = 0; ActualIndex < Length; ActualIndex += ChunkLength) {
+    WriteAddr = Offset;
+
+    SpiFlashBank (Slave, WriteAddr);
+
+    ByteAddr = Offset % PageSize;
+
+    ChunkLength = MIN(Length - ActualIndex, (UINT64) (PageSize - ByteAddr));
+
+    SpiFlashFormatAddress (WriteAddr, AddrSize, Cmd);
+
+    // Program proper write address and write data
+    Status = MvSpiFlashWriteCommon (Slave, Cmd, AddrSize + 1, Buf + ActualIndex,
+      ChunkLength);
+    if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR, "SpiFlash: Error while programming write address\n"));
+      return Status;
+    }
+
+    Offset += ChunkLength;
+  }
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+MvSpiFlashUpdateBlock (
+  IN SPI_DEVICE *Slave,
+  IN UINT32 Offset,
+  IN UINTN ToUpdate,
+  IN UINT8 *Buf,
+  IN UINT8 *TmpBuf,
+  IN UINTN EraseSize
+  )
+{
+  EFI_STATUS Status;
+
+  // Read backup
+  Status = MvSpiFlashRead (Slave, Offset, EraseSize, TmpBuf);
+    if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while reading old data\n"));
+      return Status;
+    }
+
+  // Erase entire sector
+  Status = MvSpiFlashErase (Slave, Offset, EraseSize);
+  if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while erasing block\n"));
+      return Status;
+    }
+
+  // Write new data
+  MvSpiFlashWrite (Slave, Offset, ToUpdate, Buf);
+  if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while writing new data\n"));
+      return Status;
+    }
+
+  // Write backup
+  if (ToUpdate != EraseSize) {
+    Status = MvSpiFlashWrite (Slave, Offset + ToUpdate, EraseSize - ToUpdate,
+      &TmpBuf[ToUpdate]);
+    if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while writing backup\n"));
+      return Status;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MvSpiFlashUpdate (
+  IN SPI_DEVICE *Slave,
+  IN UINT32 Offset,
+  IN UINTN ByteCount,
+  IN UINT8 *Buf
+  )
+{
+  EFI_STATUS Status;
+  UINT64 EraseSize, ToUpdate, Scale = 1;
+  UINT8 *TmpBuf, *End;
+
+  EraseSize = PcdGet64 (PcdSpiFlashEraseSize);
+
+  End = Buf + ByteCount;
+
+  TmpBuf = (UINT8 *)AllocateZeroPool (EraseSize);
+  if (TmpBuf == NULL) {
+    DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  if (End - Buf >= 200)
+    Scale = (End - Buf) / 100;
+
+  for (; Buf < End; Buf += ToUpdate, Offset += ToUpdate) {
+    ToUpdate = MIN((UINT64)(End - Buf), EraseSize);
+    Print (L"   \rUpdating, %d%%", 100 - (End - Buf) / Scale);
+    Status = MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf, EraseSize);
+
+    if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR, "SpiFlash: Error while updating\n"));
+      return Status;
+    }
+  }
+
+  Print(L"\n");
+  FreePool (TmpBuf);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiFlashReadId (
+  IN     SPI_DEVICE *SpiDev,
+  IN     UINT32     DataByteCount,
+  IN OUT UINT8      *Buffer
+  )
+{
+  EFI_STATUS Status;
+  UINT8 *DataOut;
+
+  DataOut = (UINT8 *) AllocateZeroPool (DataByteCount);
+  if (DataOut == NULL) {
+    DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+  Status = SpiMasterProtocol->Transfer (SpiMasterProtocol, SpiDev,
+    DataByteCount, Buffer, DataOut, SPI_TRANSFER_BEGIN | SPI_TRANSFER_END);
+  if (EFI_ERROR(Status)) {
+    FreePool (DataOut);
+    DEBUG((DEBUG_ERROR, "SpiFlash: Spi transfer error\n"));
+    return Status;
+  }
+
+  // Bytes 1,2 and 3 contain SPI flash ID
+  Buffer[0] = DataOut[1];
+  Buffer[1] = DataOut[2];
+  Buffer[2] = DataOut[3];
+
+  FreePool (DataOut);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiFlashInit (
+  IN MARVELL_SPI_FLASH_PROTOCOL *This,
+  IN SPI_DEVICE *Slave
+  )
+{
+  EFI_STATUS Status;
+  UINT8 Cmd, StatusRegister;
+  UINT32 AddrSize;
+
+  AddrSize = PcdGet32 (PcdSpiFlashAddressCycles);
+
+  if (AddrSize == 4) {
+    // Set 4 byte address mode
+    Status = MvSpiFlashWriteEnableCmd (Slave);
+    if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR, "SpiFlash: Error while setting write_enable\n"));
+      return Status;
+    }
+
+    Cmd = CMD_4B_ADDR_ENABLE;
+    Status = SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, &Cmd, NULL,
+      SPI_TRANSFER_BEGIN | SPI_TRANSFER_END);
+    if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR, "SpiFlash: Error while setting 4B address\n"));
+      return Status;
+    }
+  }
+
+  // Write flash status register
+  Status = MvSpiFlashWriteEnableCmd (Slave);
+  if (EFI_ERROR (Status)) {
+    DEBUG((DEBUG_ERROR, "SpiFlash: Error while setting write_enable\n"));
+    return Status;
+  }
+
+  Cmd = CMD_WRITE_STATUS_REG;
+  StatusRegister = 0x0;
+  Status = SpiMasterProtocol->ReadWrite (SpiMasterProtocol, Slave, &Cmd, 1,
+    &StatusRegister, NULL, 1);
+  if (EFI_ERROR (Status)) {
+    DEBUG((DEBUG_ERROR, "SpiFlash: Error with spi transfer\n"));
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MvSpiFlashInitProtocol (
+  IN MARVELL_SPI_FLASH_PROTOCOL *SpiFlashProtocol
+  )
+{
+
+  SpiFlashProtocol->Init = MvSpiFlashInit;
+  SpiFlashProtocol->ReadId = MvSpiFlashReadId;
+  SpiFlashProtocol->Read = MvSpiFlashRead;
+  SpiFlashProtocol->Write = MvSpiFlashWrite;
+  SpiFlashProtocol->Erase = MvSpiFlashErase;
+  SpiFlashProtocol->Update = MvSpiFlashUpdate;
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiFlashEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = gBS->LocateProtocol (
+    &gMarvellSpiMasterProtocolGuid,
+    NULL,
+    (VOID **)&SpiMasterProtocol
+  );
+  if (EFI_ERROR (Status)) {
+    DEBUG((DEBUG_ERROR, "SpiFlash: Cannot locate SPI Master protocol\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  mSpiFlashInstance = AllocateZeroPool (sizeof (SPI_FLASH_INSTANCE));
+
+  if (mSpiFlashInstance == NULL) {
+    DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n"));
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  MvSpiFlashInitProtocol (&mSpiFlashInstance->SpiFlashProtocol);
+
+  mSpiFlashInstance->Signature = SPI_FLASH_SIGNATURE;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &(mSpiFlashInstance->Handle),
+                  &gMarvellSpiFlashProtocolGuid,
+                  &(mSpiFlashInstance->SpiFlashProtocol),
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    FreePool (mSpiFlashInstance);
+    DEBUG((DEBUG_ERROR, "SpiFlash: Cannot install SPI flash protocol\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/Spi/Devices/MvSpiFlash.h b/Drivers/Spi/Devices/MvSpiFlash.h
new file mode 100755
index 0000000..3889643
--- /dev/null
+++ b/Drivers/Spi/Devices/MvSpiFlash.h
@@ -0,0 +1,132 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __MV_SPI_FLASH_H__
+#define __MV_SPI_FLASH_H__
+
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Spi.h>
+#include <Protocol/SpiFlash.h>
+
+#define SPI_FLASH_SIGNATURE             SIGNATURE_32 ('F', 'S', 'P', 'I')
+
+#define CMD_READ_ID                     0x9f
+#define READ_STATUS_REG_CMD             0x0b
+#define CMD_WRITE_ENABLE                0x06
+#define CMD_READ_STATUS                 0x05
+#define CMD_FLAG_STATUS                 0x70
+#define CMD_WRITE_STATUS_REG            0x01
+#define CMD_READ_ARRAY_FAST             0x0b
+#define CMD_PAGE_PROGRAM                0x02
+#define CMD_BANK_WRITE                  0xc5
+#define CMD_ERASE_64K                   0xd8
+#define CMD_4B_ADDR_ENABLE              0xb7
+
+#define STATUS_REG_POLL_WIP             (1 << 0)
+#define STATUS_REG_POLL_PEC             (1 << 7)
+
+#define SPI_TRANSFER_BEGIN              0x01  // Assert CS before transfer
+#define SPI_TRANSFER_END                0x02  // Deassert CS after transfers
+
+#define SPI_FLASH_16MB_BOUN             0x1000000
+
+typedef enum {
+  SPI_FLASH_READ_ID,
+  SPI_FLASH_READ, // Read from SPI flash with address
+  SPI_FLASH_WRITE, // Write to SPI flash with address
+  SPI_FLASH_ERASE,
+  SPI_FLASH_UPDATE,
+  SPI_COMMAND_MAX
+} SPI_COMMAND;
+
+typedef struct {
+  MARVELL_SPI_FLASH_PROTOCOL  SpiFlashProtocol;
+  UINTN                   Signature;
+  EFI_HANDLE              Handle;
+} SPI_FLASH_INSTANCE;
+
+EFI_STATUS
+EFIAPI
+SpiFlashReadId (
+  IN     SPI_DEVICE *SpiDev,
+  IN     UINT32     DataByteCount,
+  IN OUT UINT8      *Buffer
+  );
+
+EFI_STATUS
+SpiFlashRead (
+  IN SPI_DEVICE   *Slave,
+  IN UINT32       Offset,
+  IN UINTN        Length,
+  IN VOID         *Buf
+  );
+
+EFI_STATUS
+SpiFlashWrite (
+  IN SPI_DEVICE *Slave,
+  IN UINT32     Offset,
+  IN UINTN      Length,
+  IN VOID       *Buf
+  );
+
+EFI_STATUS
+SpiFlashUpdate (
+  IN SPI_DEVICE *Slave,
+  IN UINT32 Offset,
+  IN UINTN ByteCount,
+  IN UINT8 *Buf
+  );
+
+EFI_STATUS
+SpiFlashErase (
+  IN SPI_DEVICE *SpiDev,
+  IN UINTN      Offset,
+  IN UINTN      Length
+  );
+
+EFI_STATUS
+EFIAPI
+EfiSpiFlashInit (
+  IN MARVELL_SPI_FLASH_PROTOCOL *This,
+  IN SPI_DEVICE *Slave
+  );
+
+#endif // __MV_SPI_FLASH_H__
diff --git a/Drivers/Spi/Devices/MvSpiFlash.inf b/Drivers/Spi/Devices/MvSpiFlash.inf
new file mode 100644
index 0000000..85b1728
--- /dev/null
+++ b/Drivers/Spi/Devices/MvSpiFlash.inf
@@ -0,0 +1,67 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SpiFlashDxe
+  FILE_GUID                      = 49d7fb74-306d-42bd-94c8-c0c54b181dd7
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = MvSpiFlashEntryPoint
+
+[Sources]
+  MvSpiFlash.c
+  MvSpiFlash.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  TimerLib
+  UefiLib
+  DebugLib
+  MemoryAllocationLib
+
+[FixedPcd]
+  gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles
+  gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize
+  gMarvellTokenSpaceGuid.PcdSpiFlashPageSize
+  gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd
+
+[Protocols]
+  gMarvellSpiMasterProtocolGuid
+  gMarvellSpiFlashProtocolGuid
+
+[Depex]
+  TRUE
diff --git a/Drivers/Spi/MvSpiDxe.c b/Drivers/Spi/MvSpiDxe.c
new file mode 100755
index 0000000..aab20fc
--- /dev/null
+++ b/Drivers/Spi/MvSpiDxe.c
@@ -0,0 +1,379 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#include "MvSpiDxe.h"
+
+SPI_MASTER *mSpiMasterInstance;
+
+STATIC
+EFI_STATUS
+SpiSetBaudRate (
+  IN UINT32 CpuClock,
+  IN UINT32 MaxFreq
+  )
+{
+  UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff;
+  UINTN SpiRegBase = PcdGet32 (PcdSpiRegBase);
+
+  MinBaudDiff = 0xFFFFFFFF;
+  BestSppr = 0;
+
+  //Spr is in range 1-15 and Sppr in range 0-8
+  for (Spr = 1; Spr <= 15; Spr++) {
+    for (Sppr = 0; Sppr <= 7; Sppr++) {
+      ClockDivider = Spr * (1 << Sppr);
+
+      if ((CpuClock / ClockDivider) > MaxFreq) {
+        continue;
+      }
+
+      if ((CpuClock / ClockDivider) == MaxFreq) {
+        BestSpr = Spr;
+        BestSppr = Sppr;
+        Match = 1;
+        break;
+        }
+
+      if ((MaxFreq - (CpuClock / ClockDivider)) < MinBaudDiff) {
+        MinBaudDiff = (MaxFreq - (CpuClock / ClockDivider));
+        BestSpr = Spr;
+        BestSppr = Sppr;
+      }
+    }
+
+    if (Match == 1) {
+      break;
+    }
+  }
+
+  if (BestSpr == 0) {
+    return (EFI_INVALID_PARAMETER);
+  }
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
+  Reg &= ~(SPI_SPR_MASK | SPI_SPPR_0_MASK | SPI_SPPR_HI_MASK);
+  Reg |= (BestSpr << SPI_SPR_OFFSET) |
+         ((BestSppr & 0x1) << SPI_SPPR_0_OFFSET) |
+         ((BestSppr >> 1) << SPI_SPPR_HI_OFFSET);
+  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+SpiSetCs (
+  UINT8 CsId
+  )
+{
+  UINT32 Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase);
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
+  Reg &= ~SPI_CS_NUM_MASK;
+  Reg |= (CsId << SPI_CS_NUM_OFFSET);
+  MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg);
+}
+
+STATIC
+VOID
+SpiActivateCs (
+  UINT8 IN CsId
+  )
+{
+  UINT32  Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase);
+
+  SpiSetCs(CsId);
+  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
+  Reg |= SPI_CS_EN_MASK;
+  MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
+}
+
+STATIC
+VOID
+SpiDeactivateCs (
+  VOID
+  )
+{
+  UINT32  Reg, SpiRegBase = PcdGet32 (PcdSpiRegBase);
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
+  Reg &= ~SPI_CS_EN_MASK;
+  MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
+}
+
+STATIC
+VOID
+SpiSetupTransfer (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN SPI_DEVICE *Slave
+  )
+{
+  SPI_MASTER *SpiMaster;
+  UINT32 Reg, SpiRegBase, CoreClock, SpiMaxFreq;
+
+  SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
+
+  // Initialize values from PCDs
+  SpiRegBase  = PcdGet32 (PcdSpiRegBase);
+  CoreClock   = PcdGet32 (PcdSpiClockFrequency);
+  SpiMaxFreq  = PcdGet32 (PcdSpiMaxFrequency);
+
+  EfiAcquireLock (&SpiMaster->Lock);
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
+  Reg |= SPI_BYTE_LENGTH;
+  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
+
+  SpiSetCs(Slave->Cs);
+
+  SpiSetBaudRate (CoreClock, SpiMaxFreq);
+
+  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
+  Reg &= ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_MASK);
+
+  switch (Slave->Mode) {
+  case SPI_MODE0:
+    break;
+  case SPI_MODE1:
+    Reg |= SPI_CPHA_MASK;
+    break;
+  case SPI_MODE2:
+    Reg |= SPI_CPOL_MASK;
+    break;
+  case SPI_MODE3:
+    Reg |= SPI_CPOL_MASK;
+    Reg |= SPI_CPHA_MASK;
+    break;
+  }
+
+  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
+
+  EfiReleaseLock (&SpiMaster->Lock);
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiTransfer (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN SPI_DEVICE *Slave,
+  IN UINTN DataByteCount,
+  IN VOID *DataOut,
+  IN VOID *DataIn,
+  IN UINTN Flag
+  )
+{
+  SPI_MASTER *SpiMaster;
+  UINT64  Length;
+  UINT32  Iterator, Reg, SpiRegBase;
+  UINT8   *DataOutPtr = (UINT8 *)DataOut;
+  UINT8   *DataInPtr  = (UINT8 *)DataIn;
+  UINT8   DataToSend  = 0;
+
+  SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);
+
+  SpiRegBase = PcdGet32 (PcdSpiRegBase);
+
+  Length = 8 * DataByteCount;
+
+  EfiAcquireLock (&SpiMaster->Lock);
+
+  if (Flag & SPI_TRANSFER_BEGIN) {
+    SpiActivateCs (Slave->Cs);
+  }
+
+  // Set 8-bit mode
+  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
+  Reg &= ~SPI_BYTE_LENGTH;
+  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);
+
+  while (Length > 0) {
+    if (DataOut != NULL) {
+      DataToSend = *DataOutPtr & 0xFF;
+    }
+    // Transmit Data
+    MmioWrite32 (SpiRegBase + SPI_INT_CAUSE_REG, 0x0);
+    MmioWrite32 (SpiRegBase + SPI_DATA_OUT_REG, DataToSend);
+    // Wait for memory ready
+    for (Iterator = 0; Iterator < SPI_TIMEOUT; Iterator++) {
+      if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) {
+        *DataInPtr = MmioRead32 (SpiRegBase + SPI_DATA_IN_REG);
+
+        if (DataInPtr != NULL) {
+          DataInPtr++;
+        }
+        if (DataOutPtr != NULL) {
+          DataOutPtr++;
+        }
+        Length -= 8;
+        break;
+      }
+    }
+
+    if (Iterator >= SPI_TIMEOUT) {
+      DEBUG ((DEBUG_ERROR, "Timeout\n"));
+    }
+  }
+
+  if (Flag & SPI_TRANSFER_END) {
+    SpiDeactivateCs ();
+  }
+
+  EfiReleaseLock (&SpiMaster->Lock);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiReadWrite (
+  IN  MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN  SPI_DEVICE *Slave,
+  IN  UINT8 *Cmd,
+  IN  UINTN CmdSize,
+  IN  UINT8 *DataOut,
+  OUT UINT8 *DataIn,
+  IN  UINTN DataSize
+  )
+{
+  EFI_STATUS Status;
+
+  Status = MvSpiTransfer (This, Slave, CmdSize, Cmd, NULL, SPI_TRANSFER_BEGIN);
+  if (EFI_ERROR (Status)) {
+    Print (L"Spi Transfer Error\n");
+    return EFI_DEVICE_ERROR;
+  }
+
+  Status = MvSpiTransfer (This, Slave, DataSize, DataOut, DataIn, SPI_TRANSFER_END);
+  if (EFI_ERROR (Status)) {
+    Print (L"Spi Transfer Error\n");
+    return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiInit (
+  IN MARVELL_SPI_MASTER_PROTOCOL * This
+  )
+{
+
+  return EFI_SUCCESS;
+}
+
+SPI_DEVICE *
+EFIAPI
+MvSpiSetupSlave (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN UINTN Cs,
+  IN SPI_MODE Mode
+  )
+{
+  SPI_DEVICE  *Slave;
+
+  Slave = AllocateZeroPool (sizeof(SPI_DEVICE));
+  if (Slave == NULL) {
+    DEBUG((DEBUG_ERROR, "Cannot allocate memory\n"));
+    return NULL;
+  }
+
+  Slave->Cs   = Cs;
+  Slave->Mode = Mode;
+
+  SpiSetupTransfer (This, Slave);
+
+  return Slave;
+}
+
+EFI_STATUS
+EFIAPI
+MvSpiFreeSlave (
+  IN SPI_DEVICE *Slave
+  )
+{
+  FreePool (Slave);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+SpiMasterInitProtocol (
+  IN MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol
+  )
+{
+
+  SpiMasterProtocol->Init        = MvSpiInit;
+  SpiMasterProtocol->SetupDevice = MvSpiSetupSlave;
+  SpiMasterProtocol->FreeDevice  = MvSpiFreeSlave;
+  SpiMasterProtocol->Transfer    = MvSpiTransfer;
+  SpiMasterProtocol->ReadWrite   = MvSpiReadWrite;
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SpiMasterEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+
+  mSpiMasterInstance = AllocateZeroPool (sizeof (SPI_MASTER));
+
+  if (mSpiMasterInstance == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  EfiInitializeLock (&mSpiMasterInstance->Lock, TPL_NOTIFY);
+
+  SpiMasterInitProtocol (&mSpiMasterInstance->SpiMasterProtocol);
+
+  mSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &(mSpiMasterInstance->Handle),
+                  &gMarvellSpiMasterProtocolGuid,
+                  &(mSpiMasterInstance->SpiMasterProtocol),
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    FreePool (mSpiMasterInstance);
+    return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Drivers/Spi/MvSpiDxe.h b/Drivers/Spi/MvSpiDxe.h
new file mode 100644
index 0000000..1401f62
--- /dev/null
+++ b/Drivers/Spi/MvSpiDxe.h
@@ -0,0 +1,145 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __SPI_MASTER_H__
+#define __SPI_MASTER_H__
+
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Spi.h>
+
+#define SPI_MASTER_SIGNATURE                      SIGNATURE_32 ('M', 'S', 'P', 'I')
+#define SPI_MASTER_FROM_SPI_MASTER_PROTOCOL(a)  CR (a, SPI_MASTER, SpiMasterProtocol, SPI_MASTER_SIGNATURE)
+
+// Marvell Flash Device Controller Registers
+#define SPI_CTRL_REG                    (0x00)
+#define SPI_CONF_REG                    (0x04)
+#define SPI_DATA_OUT_REG                (0x08)
+#define SPI_DATA_IN_REG                 (0x0c)
+#define SPI_INT_CAUSE_REG               (0x10)
+
+// Serial Memory Interface Control Register Masks
+#define SPI_CS_NUM_OFFSET               2
+#define SPI_CS_NUM_MASK                 (0x7 << SPI_CS_NUM_OFFSET)
+#define SPI_MEM_READY_MASK              (0x1 << 1)
+#define SPI_CS_EN_MASK                  (0x1 << 0)
+
+// Serial Memory Interface Configuration Register Masks
+#define SPI_BYTE_LENGTH_OFFSET          5
+#define SPI_BYTE_LENGTH                 (0x1  << SPI_BYTE_LENGTH_OFFSET)
+#define SPI_CPOL_OFFSET                 11
+#define SPI_CPOL_MASK                   (0x1 << SPI_CPOL_OFFSET)
+#define SPI_CPHA_OFFSET                 12
+#define SPI_CPHA_MASK                  (0x1 << SPI_CPHA_OFFSET)
+#define SPI_TXLSBF_OFFSET               13
+#define SPI_TXLSBF_MASK                 (0x1 << SPI_TXLSBF_OFFSET)
+#define SPI_RXLSBF_OFFSET               14
+#define SPI_RXLSBF_MASK                 (0x1 << SPI_RXLSBF_OFFSET)
+
+#define SPI_SPR_OFFSET                  0
+#define SPI_SPR_MASK                    (0xf << SPI_SPR_OFFSET)
+#define SPI_SPPR_0_OFFSET               4
+#define SPI_SPPR_0_MASK                 (0x1 << SPI_SPPR_0_OFFSET)
+#define SPI_SPPR_HI_OFFSET              6
+#define SPI_SPPR_HI_MASK                (0x3 << SPI_SPPR_HI_OFFSET)
+
+#define SPI_TRANSFER_BEGIN              0x01  // Assert CS before transfer
+#define SPI_TRANSFER_END                0x02  // Deassert CS after transfers
+
+#define SPI_TIMEOUT                     100000
+
+typedef struct {
+  MARVELL_SPI_MASTER_PROTOCOL SpiMasterProtocol;
+  UINTN                   Signature;
+  EFI_HANDLE              Handle;
+  EFI_LOCK                Lock;
+} SPI_MASTER;
+
+EFI_STATUS
+EFIAPI
+MvSpiTransfer (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN SPI_DEVICE *Slave,
+  IN UINTN DataByteCount,
+  IN VOID *DataOut,
+  IN VOID *DataIn,
+  IN UINTN Flag
+  );
+
+EFI_STATUS
+EFIAPI
+MvSpiReadWrite (
+  IN  MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN  SPI_DEVICE *Slave,
+  IN  UINT8 *Cmd,
+  IN  UINTN CmdSize,
+  IN  UINT8 *DataOut,
+  OUT UINT8 *DataIn,
+  IN  UINTN DataSize
+  );
+
+EFI_STATUS
+EFIAPI
+MvSpiInit (
+  IN MARVELL_SPI_MASTER_PROTOCOL     * This
+  );
+
+SPI_DEVICE *
+EFIAPI
+MvSpiSetupSlave (
+  IN MARVELL_SPI_MASTER_PROTOCOL     * This,
+  IN UINTN Cs,
+  IN SPI_MODE Mode
+  );
+
+EFI_STATUS
+EFIAPI
+MvSpiFreeSlave (
+  IN SPI_DEVICE *Slave
+  );
+
+EFI_STATUS
+EFIAPI
+SpiMasterEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  );
+
+#endif // __SPI_MASTER_H__
diff --git a/Drivers/Spi/MvSpiDxe.inf b/Drivers/Spi/MvSpiDxe.inf
new file mode 100644
index 0000000..1dd3029
--- /dev/null
+++ b/Drivers/Spi/MvSpiDxe.inf
@@ -0,0 +1,66 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SpiMasterDxe
+  FILE_GUID                      = c19dbc8a-f4f9-43b0-aee5-802e3ed03d15
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = SpiMasterEntryPoint
+
+[Sources]
+  MvSpiDxe.c
+  MvSpiDxe.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  TimerLib
+  UefiLib
+  DebugLib
+  MemoryAllocationLib
+  IoLib
+
+[FixedPcd]
+  gMarvellTokenSpaceGuid.PcdSpiRegBase
+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency
+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
+
+[Protocols]
+  gMarvellSpiMasterProtocolGuid
+
+[Depex]
+  TRUE
diff --git a/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.c b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.c
new file mode 100644
index 0000000..5ed3dd4
--- /dev/null
+++ b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.c
@@ -0,0 +1,2347 @@
+/** @file
+
+  Copyright (c) 2017, Linaro Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Usb.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UncachedMemoryAllocationLib.h>
+#include <Protocol/DwUsb.h>
+#include <Protocol/UsbDevice.h>
+
+#include "DwUsb3Dxe.h"
+
+#define FIFO_DIR_TX                  0
+#define FIFO_DIR_RX                  1
+
+#define TX_FIFO_ADDR                 0
+#define RX_FIFO_ADDR                 0
+
+#define RAM_WIDTH                    8
+#define RAM_TX0_DEPTH                2048
+#define RAM_TX1_DEPTH                4096
+#define RAM_RX_DEPTH                 8192
+
+#define USB_TYPE_LENGTH              16
+#define USB_BLOCK_HIGH_SPEED_SIZE    512
+#define DATA_SIZE                    131072
+#define CMD_SIZE                     512
+#define MATCH_CMD_LITERAL(Cmd, Buf) !AsciiStrnCmp (Cmd, Buf, sizeof (Cmd) - 1)
+
+// The time between interrupt polls, in units of 100 nanoseconds
+// 10 Microseconds
+#define DW_INTERRUPT_POLL_PERIOD     100
+
+#define DWUSB3_EVENT_BUF_SIZE        256
+
+// Maxpacket size for EP0, defined by USB3 spec
+#define USB3_MAX_EP0_SIZE            512
+
+// Maxpacket size for any EP, defined by USB3 spec
+#define USB3_MAX_PACKET_SIZE         1024
+#define USB2_HS_MAX_PACKET_SIZE      512
+#define USB2_FS_MAX_PACKET_SIZE      64
+
+#define USB3_STATE_UNCONNECTED       0
+#define USB3_STATE_DEFAULT           1
+#define USB3_STATE_ADDRESSED         2
+#define USB3_STATE_CONFIGURED        3
+
+#define GET_EVENTBUF_COUNT()       (GEVNTCOUNT_EVNTCOUNT (MmioRead32 (GEVNTCOUNT (0))))
+#define UPDATE_EVENTBUF_COUNT(x)   (MmioWrite32 (GEVNTCOUNT (0), GEVNTCOUNT_EVNTCOUNT (x)))
+#define CLEAR_EVENTBUF()           do {                                                \
+                                     MmioOr32 (GEVNTSIZ (0), GEVNTSIZ_EVNTINTMASK);    \
+                                     MmioOr32 (GEVNTCOUNT (0), 0);                     \
+                                   } while (0)
+
+#define SET_DEVADDR(x)             (MmioAndThenOr32 (DCFG, ~DCFG_DEVADDR_MASK, DCFG_DEVADDR (x)))
+
+EFI_GUID  gDwUsbProtocolGuid = DW_USB_PROTOCOL_GUID;
+
+STATIC DW_USB_PROTOCOL          *DwUsb;
+
+STATIC usb3_pcd_t               gPcd;
+STATIC UINT32                   *gEventBuf, *gEventPtr;
+STATIC struct usb_device_descriptor   gDwUsb3DevDesc;
+STATIC VOID                     *gRxBuf;
+
+STATIC usb_setup_pkt_t                *gEndPoint0SetupPacket;
+#define USB3_STATUS_BUF_SIZE    512
+STATIC UINT8                          *gEndPoint0StatusBuf;
+STATIC USB_DEVICE_RX_CALLBACK         mDataReceivedCallback;
+/*
+	UINT8 ep0_status_buf[USB3_STATUS_BUF_SIZE];
+*/
+
+struct usb_interface_descriptor intf = {
+  sizeof (struct usb_interface_descriptor),
+  UDESC_INTERFACE,
+  0,
+  0,
+  2,
+  USB_CLASS_VENDOR_SPEC,
+  0x42,
+  0x03,
+  0
+};
+
+const struct usb_ss_ep_comp_descriptor ep_comp = {
+  sizeof (struct usb_ss_ep_comp_descriptor),
+  UDESC_SS_USB_COMPANION,
+  0,
+  0,
+  0
+};
+
+const struct usb_endpoint_descriptor hs_bulk_in = {
+  sizeof (struct usb_endpoint_descriptor),
+  UDESC_ENDPOINT,
+  UE_DIR_IN | USB3_BULK_IN_EP,
+  USB_ENDPOINT_XFER_BULK,
+  0x200,
+  0
+};
+
+const struct usb_endpoint_descriptor
+hs_bulk_out = {
+	sizeof(struct usb_endpoint_descriptor), /* bLength */
+	UDESC_ENDPOINT, /* bDescriptorType */
+
+	UE_DIR_OUT | USB3_BULK_OUT_EP, /* bEndpointAddress */
+	USB_ENDPOINT_XFER_BULK, /* bmAttributes */
+	0x200, /* wMaxPacketSize: 512 of high-speed */
+	1, /* bInterval */
+};
+
+const struct usb_endpoint_descriptor ss_bulk_in = {
+	sizeof(struct usb_endpoint_descriptor), /* bLength */
+	UDESC_ENDPOINT, /* bDescriptorType */
+
+	UE_DIR_IN | USB3_BULK_IN_EP, /* bEndpointAddress */
+	USB_ENDPOINT_XFER_BULK, /* bmAttributes */
+	0x400, /* wMaxPacketSize: 1024 of super-speed */
+	0, /* bInterval */
+};
+
+const struct usb_endpoint_descriptor ss_bulk_out = {
+	sizeof(struct usb_endpoint_descriptor), /* bLength */
+	UDESC_ENDPOINT, /* bDescriptorType */
+
+	UE_DIR_OUT | USB3_BULK_OUT_EP, /* bEndpointAddress */
+	USB_ENDPOINT_XFER_BULK, /* bmAttributes */
+	0x400, /* wMaxPacketSize: 1024 of super-speed */
+	0, /* bInterval */
+};
+
+/** The BOS Descriptor */
+
+const struct usb_dev_cap_20_ext_desc cap1 = {
+	sizeof(struct usb_dev_cap_20_ext_desc),	/* bLength */
+	UDESC_DEVICE_CAPABILITY,		/* bDescriptorType */
+	USB_DEVICE_CAPABILITY_20_EXTENSION,	/* bDevCapabilityType */
+	0x2,				/* bmAttributes */
+};
+
+const struct usb_dev_cap_ss_usb
+cap2 = {
+	sizeof(struct usb_dev_cap_ss_usb),	/* bLength */
+	UDESC_DEVICE_CAPABILITY,		/* bDescriptorType */
+	USB_DEVICE_CAPABILITY_SS_USB,		/* bDevCapabilityType */
+	0x0,					/* bmAttributes */
+	(USB_DC_SS_USB_SPEED_SUPPORT_SS |
+	    USB_DC_SS_USB_SPEED_SUPPORT_HIGH),   /* wSpeedsSupported */
+	0x2,					/* bFunctionalitySupport */
+	/* @todo set these to correct value */
+	0xa,					/* bU1DevExitLat */
+	0x100,				/* wU2DevExitLat */
+};
+
+const struct usb_dev_cap_container_id
+cap3 = {
+	sizeof(struct usb_dev_cap_container_id),/* bLength */
+	UDESC_DEVICE_CAPABILITY,		/* bDescriptorType */
+	USB_DEVICE_CAPABILITY_CONTAINER_ID,	/* bDevCapabilityType */
+	0,					/* bReserved */
+	/* @todo Create UUID */
+	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* containerID */
+};
+
+const struct wusb_bos_desc
+bos = {
+	sizeof(struct wusb_bos_desc),		/* bLength */
+	UDESC_BOS,				/* bDescriptorType */
+	(sizeof(struct wusb_bos_desc)	/* wTotalLength */
+	    + sizeof(cap1) + sizeof(cap2) + sizeof(cap3)),
+	3,					/* bNumDeviceCaps */
+};
+
+STATIC struct usb_enum_port_param usb_port_activity_config = {
+  .idVendor           = USB_ENUM_ADB_PORT_VID,
+  .idProduct          = USB_ENUM_ADB_PORT_PID,
+  .bInterfaceSubClass = USB_ENUM_INTERFACE_ADB_SUBCLASS,
+  .bInterfaceProtocol = USB_ENUM_INTERFACE_ADB_PROTOCOL
+};
+
+STATIC
+UINT32
+DwUsb3GetEventBufEvent (
+  IN UINTN               Size
+  )
+{
+  UINT32                 Event;
+
+  Event = *gEventPtr++;
+  if ((UINT32)(UINTN)gEventPtr >= (UINT32)(UINTN)gEventBuf + Size) {
+    gEventPtr = gEventBuf;
+  }
+  return Event;
+}
+
+STATIC
+VOID
+DwUsb3SetFifoSize (
+  IN UINT32              Addr,
+  IN UINT32              Depth,
+  IN UINT32              Dir,
+  IN UINT32              FifoNum
+  )
+{
+  UINT32                 Reg;
+
+  if (Dir == FIFO_DIR_TX) {
+    Reg = GTXFIFOSIZ (FifoNum);
+  } else if (Dir == FIFO_DIR_RX) {
+    Reg = GRXFIFOSIZ (FifoNum);
+  } else {
+    ASSERT (0);
+  }
+  MmioWrite32 (Reg, FIFOSIZ_DEP (Depth) | FIFOSIZ_ADDR (Addr));
+}
+
+STATIC
+UINT32
+Handshake (
+  IN UINT32              Reg,
+  IN UINT32              Mask,
+  IN UINT32              Done
+  )
+{
+  UINT32                 Timeout = 100000;
+
+  do {
+    if ((MmioRead32 (Reg) & Mask) == Done) {
+      return 1;
+    }
+    MicroSecondDelay (1);
+  } while (Timeout-- > 0);
+  return 0;
+}
+
+STATIC
+VOID
+DwUsb3FillDesc (
+  IN usb3_dma_desc_t     *desc,
+  IN UINT64              dma_addr,
+  IN UINT32              dma_len,
+  IN UINT32              stream,
+  IN UINT32              type,
+  IN UINT32              ctrlbits,
+  IN UINT32              own
+  )
+{
+  desc->bptl = (UINT32)(dma_addr & 0xFFFFFFFF);
+  desc->bpth = (UINT32)(dma_addr >> 32);
+  desc->status = DSCSTS_XFERCNT (dma_len);
+  if (type) {
+    desc->control = DSCCTL_TRBCTL (type);
+  }
+  desc->control |= DSCCTL_STRMID_SOFN (stream) | ctrlbits;
+  ArmDataSynchronizationBarrier ();
+  /* must execute this operation at last */
+  if (own) {
+    desc->control |= DSCCTL_HWO;
+  }
+  ArmDataSynchronizationBarrier ();
+}
+
+STATIC
+VOID
+DwUsb3DepStartNewCfg (
+  IN UINT32              EpIdx,
+  IN UINT32              RsrcIdx
+  )
+{
+  /* start the command */
+  MmioWrite32 (
+    DEPCMD (EpIdx),
+    DEPCMD_XFER_RSRC_IDX (RsrcIdx) | DEPCMD_CMDTYPE (CMDTYPE_START_NEW_CFG) | DEPCMD_CMDACT
+    );
+  Handshake (DEPCMD (EpIdx), DEPCMD_CMDACT, 0);
+}
+
+STATIC
+VOID
+DwUsb3DepCfg (
+  IN UINT32              EpIdx,
+  IN UINT32              DepCfg0,
+  IN UINT32              DepCfg1,
+  IN UINT32              DepCfg2
+  )
+{
+  MmioWrite32 (DEPCMDPAR2 (EpIdx), DepCfg2);
+  MmioWrite32 (DEPCMDPAR1 (EpIdx), DepCfg1);
+  MmioWrite32 (DEPCMDPAR0 (EpIdx), DepCfg0);
+  MmioWrite32 (DEPCMD (EpIdx), DEPCMD_CMDTYPE (CMDTYPE_SET_EP_CFG) | DEPCMD_CMDACT);
+  Handshake (DEPCMD (EpIdx), DEPCMD_CMDACT, 0);
+}
+
+STATIC
+VOID
+DwUsb3DepXferCfg (
+  IN UINT32              EpIdx,
+  IN UINT32              DepStrmCfg
+  )
+{
+  MmioWrite32 (DEPCMDPAR0 (EpIdx), DepStrmCfg);
+  MmioWrite32 (DEPCMD (EpIdx), DEPCMD_CMDTYPE (CMDTYPE_SET_XFER_CFG) | DEPCMD_CMDACT);
+  Handshake (DEPCMD (EpIdx), DEPCMD_CMDACT, 0);
+}
+
+STATIC
+UINT8
+DwUsb3DepStartXfer (
+  IN UINT32              EpIdx,
+  IN UINT64              DmaAddr,
+  IN UINT32              StreamOrUf
+  )
+{
+  UINT32                 Data;
+
+  MmioWrite32 (DEPCMDPAR1 (EpIdx), (UINT32)DmaAddr);
+  MmioWrite32 (DEPCMDPAR0 (EpIdx), (UINT32)(DmaAddr >> 32));
+  MmioWrite32 (
+    DEPCMD (EpIdx),
+    DEPCMD_STR_NUM_OR_UF (StreamOrUf) | DEPCMD_CMDTYPE (CMDTYPE_START_XFER) | DEPCMD_CMDACT
+    );
+  Handshake (DEPCMD (EpIdx), DEPCMD_CMDACT, 0);
+  Data = MmioRead32 (DEPCMD (EpIdx));
+  return GET_DEPCMD_XFER_RSRC_IDX(Data);
+}
+
+STATIC
+VOID
+DwUsb3DepStopXfer (
+  IN UINT32               EpIdx,
+  IN UINT32               Tri
+  )
+{
+  MmioWrite32 (DEPCMDPAR2 (EpIdx), 0);
+  MmioWrite32 (DEPCMDPAR1 (EpIdx), 0);
+  MmioWrite32 (DEPCMDPAR0 (EpIdx), 0);
+  MmioWrite32 (
+    DEPCMD (EpIdx),
+    DEPCMD_XFER_RSRC_IDX (Tri) | DEPCMD_CMDTYPE (CMDTYPE_END_XFER) | DEPCMD_CMDACT
+    );
+  Handshake (DEPCMD (EpIdx), DEPCMD_CMDACT, 0);
+}
+
+VOID
+DwUsb3DepUpdateXfer (
+  IN UINT32               EpIdx,
+  IN UINT32               Tri
+  )
+{
+  MmioWrite32 (
+    DEPCMD (EpIdx),
+    DEPCMD_XFER_RSRC_IDX (Tri) | DEPCMD_CMDTYPE (CMDTYPE_UPDATE_XFER) | DEPCMD_CMDACT
+    );
+  Handshake (DEPCMD (EpIdx), DEPCMD_CMDACT, 0);
+}
+
+STATIC
+VOID
+DwUsb3DepClearStall (
+  IN UINTN            EpIdx
+  )
+{
+  MmioWrite32 (DEPCMD (EpIdx), DEPCMD_CMDTYPE (CMDTYPE_CLR_STALL) | DEPCMD_CMDACT);
+  Handshake (DEPCMD (EpIdx), DEPCMD_CMDACT, 0);
+}
+
+
+STATIC
+VOID
+DwUsb3DepSetStall (
+  IN UINTN            EpIdx
+  )
+{
+  MmioWrite32 (DEPCMD (EpIdx), DEPCMD_CMDTYPE (CMDTYPE_SET_STALL) | DEPCMD_CMDACT);
+  Handshake (DEPCMD (EpIdx), DEPCMD_CMDACT, 0);
+}
+
+STATIC
+VOID
+DwUsb3EnableEp (
+  IN UINT32                EpIdx,
+  IN usb3_pcd_ep_t         *ep
+  )
+{
+  UINT32                   Dalepena;
+
+  Dalepena = MmioRead32 (DALEPENA);
+  /* If the EP is already enabled, skip to set it again. */
+  if (Dalepena & (1 << EpIdx)) {
+    return;
+  }
+  Dalepena |= 1 << EpIdx;
+  MmioWrite32 (DALEPENA, Dalepena);
+}
+
+STATIC
+VOID
+DwUsb3Ep0Activate (
+  IN OUT usb3_pcd_t         *pcd
+  )
+{
+  /* issue DEPCFG command to EP0 OUT */
+  DwUsb3DepStartNewCfg (EP_OUT_IDX (0), 0);
+  DwUsb3DepCfg (
+    EP_OUT_IDX (0),
+    EPCFG0_EPTYPE (EPTYPE_CONTROL) | EPCFG0_MPS (512),
+    EPCFG1_XFER_CMPL | EPCFG1_XFER_NRDY,
+    0
+    );
+  /* issue DEPSTRMCFG command to EP0 OUT */
+  DwUsb3DepXferCfg (EP_OUT_IDX (0), 1);  // one stream
+  /* issue DEPCFG command to EP0 IN */
+  DwUsb3DepCfg (
+    EP_IN_IDX (0),
+    EPCFG0_EPTYPE (EPTYPE_CONTROL)  | EPCFG0_MPS (512) | EPCFG0_TXFNUM (pcd->ep0.tx_fifo_num),
+    EPCFG1_XFER_NRDY | EPCFG1_XFER_CMPL | EPCFG1_EP_DIR_IN,
+    0
+    );
+  /* issue DEPSTRMCFG command to EP0 IN */
+  DwUsb3DepXferCfg (EP_IN_IDX (0), 1);  // one stream
+  pcd->ep0.active = 1;
+}
+
+STATIC
+VOID
+DwUsb3EpActivate (
+  IN OUT usb3_pcd_t         *pcd,
+  IN OUT usb3_pcd_ep_t      *ep
+  )
+{
+  UINT32                    EpIdx, DepCfg0, DepCfg1;
+  if (ep->is_in) {
+    EpIdx = EP_IN_IDX (ep->num);
+  } else {
+    EpIdx = EP_OUT_IDX (ep->num);
+  }
+
+  /* Start a new configurate when enable the first EP. */
+  if (!pcd->eps_enabled) {
+    pcd->eps_enabled = 1;
+    /* Issue DEPCFG command to physical EP1 (logical EP0 IN) first.
+     * It resets the core's Tx FIFO mapping table.
+     */
+    DepCfg0 = EPCFG0_EPTYPE (EPTYPE_CONTROL);
+    DepCfg0 |= EPCFG0_CFG_ACTION (CFG_ACTION_MODIFY);
+    DepCfg1 = EPCFG1_XFER_CMPL | EPCFG1_XFER_NRDY | EPCFG1_EP_DIR_IN;
+
+    switch (pcd->speed) {
+    case USB_SPEED_SUPER:
+      DepCfg0 |= EPCFG0_MPS (512);
+      break;
+    case USB_SPEED_HIGH:
+    case USB_SPEED_FULL:
+      DepCfg0 |= EPCFG0_MPS (64);
+      break;
+    case USB_SPEED_LOW:
+      DepCfg0 |= EPCFG0_MPS (8);
+      break;
+    default:
+      ASSERT (0);
+      break;
+    }
+    DwUsb3DepCfg (EP_IN_IDX (0), DepCfg0, DepCfg1, 0);
+    DwUsb3DepStartNewCfg (EP_OUT_IDX (0), 2);
+  }
+  /* issue DEPCFG command to EP */
+  DepCfg0 = EPCFG0_EPTYPE (ep->type);
+  DepCfg0 |= EPCFG0_MPS (ep->maxpacket);
+  if (ep->is_in) {
+    DepCfg0 |= EPCFG0_TXFNUM (ep->tx_fifo_num);
+  }
+  DepCfg0 |= EPCFG0_BRSTSIZ (ep->maxburst);
+  DepCfg1 = EPCFG1_EP_NUM (ep->num);
+  if (ep->is_in) {
+    DepCfg1 |= EPCFG1_EP_DIR_IN;
+  } else {
+    DepCfg1 |= EPCFG1_XFER_CMPL;
+  }
+  DwUsb3DepCfg (EpIdx, DepCfg0, DepCfg1, 0);
+  /* issue DEPSTRMCFG command to EP */
+  DwUsb3DepXferCfg (EpIdx, 1);
+  DwUsb3EnableEp (EpIdx, ep);
+  ep->active = 1;
+}
+
+STATIC
+VOID
+DwUsb3Ep0OutStart (
+  IN usb3_pcd_t          *pcd
+  )
+{
+  usb3_dma_desc_t        *desc;
+
+  /* Get the SETUP packet DMA Descriptor (TRB) */
+  desc = pcd->ep0_setup_desc;
+
+  /* DMA Descriptor setup */
+  DwUsb3FillDesc (
+    desc,
+    (UINT64)gEndPoint0SetupPacket,
+    pcd->ep0.maxpacket,
+    0,
+    TRBCTL_SETUP,
+    DSCCTL_IOC | DSCCTL_ISP | DSCCTL_LST,
+    1
+    );
+
+  /* issue DEPSTRTXFER command to EP0 OUT */
+  pcd->ep0.tri_out = DwUsb3DepStartXfer (EP_OUT_IDX (0), (UINT64)desc, 0);
+}
+
+STATIC
+VOID
+DwUsb3Init (
+  VOID
+  )
+{
+  UINT32                 Data, Addr;
+  usb3_pcd_t             *pcd = &gPcd;
+
+  /* soft reset the usb core */
+  do {
+    MmioAndThenOr32 (DCTL, ~DCTL_RUN_STOP, DCTL_CSFTRST);
+
+    do {
+      MicroSecondDelay (1000);
+      Data = MmioRead32 (DCTL);
+    } while (Data & DCTL_CSFTRST);
+    // wait for at least 3 PHY clocks
+    MicroSecondDelay (1000);
+  } while (0);
+
+  pcd->link_state = 0;
+
+  /* TI PHY: Set Turnaround Time = 9 (8-bit UTMI+ / ULPI) */
+  MmioAndThenOr32 (GUSB2PHYCFG (0), ~GUSB2PHYCFG_USBTRDTIM_MASK, GUSB2PHYCFG_USBTRDTIM (9));
+
+  /* set TX FIFO size */
+  Addr = TX_FIFO_ADDR;
+  DwUsb3SetFifoSize (Addr, RAM_TX0_DEPTH / RAM_WIDTH, FIFO_DIR_TX, 0);
+  Addr += RAM_TX0_DEPTH / RAM_WIDTH;
+  DwUsb3SetFifoSize (Addr, RAM_TX1_DEPTH / RAM_WIDTH, FIFO_DIR_TX, 1);
+  /* set RX FIFO size */
+  DwUsb3SetFifoSize (RX_FIFO_ADDR, RAM_RX_DEPTH / RAM_WIDTH, FIFO_DIR_RX, 0);
+
+  /* set LFPS filter delay1trans */
+  MmioAndThenOr32 (
+    GUSB3PIPECTL (0),
+    ~PIPECTL_DELAYP1TRANS,
+    PIPECTL_LFPS_FILTER | PIPECTL_TX_DEMPH (1)
+    );
+
+  /* set GCTL */
+  Data = GCTL_U2EXIT_LFPS | GCTL_PRTCAPDIR_DEVICE | GCTL_U2RSTECN |
+         GCTL_PWRDNSCALE(2);
+  MmioWrite32 (GCTL, Data);
+
+  /* init event buf */
+  MmioWrite32 (GEVNTADRL(0), (UINT32)(UINTN)gEventBuf);
+  MmioWrite32 (GEVNTADRH(0), (UINTN)gEventBuf >> 32);
+  MmioWrite32 (GEVNTSIZ(0), DWUSB3_EVENT_BUF_SIZE << 2);
+  MmioWrite32 (GEVNTCOUNT(0), 0);
+
+  /* set max speed to super speed */
+  MmioAndThenOr32 (
+    DCFG,
+    ~DCFG_DEVSPD_MASK,
+    DCFG_DEVSPD (DEVSPD_SS_PHY_125MHZ_OR_250MHZ)
+    );
+
+  /* set nump */
+  MmioAndThenOr32 (DCFG, ~DCFG_NUMP_MASK, DCFG_NUMP (16));
+
+  /* init address */
+  SET_DEVADDR (0);
+
+  /* disable phy suspend */
+  MmioAnd32 (GUSB3PIPECTL (0), ~PIPECTL_SUSPEND_EN);
+  MmioAnd32 (GUSB2PHYCFG (0), ~GUSB2PHYCFG_SUSPHY);
+
+  /* clear any pending interrupts */
+#if 0
+  CLEAR_EVENTBUF ();
+#else
+  Data = MmioRead32 (GEVNTCOUNT (0));
+  MmioWrite32 (GEVNTCOUNT (0), Data);
+#endif
+  /* enable device interrupts */
+  MmioWrite32 (DEVTEN, DEVTEN_CONNECTDONEEN | DEVTEN_USBRSTEN);
+  /* activate EP0 */
+  DwUsb3Ep0Activate (pcd);
+  /* start EP0 to receive SETUP packets */
+  DwUsb3Ep0OutStart (pcd);
+
+  /* enable EP0 OUT/IN in DALEPENA */
+  MmioWrite32 (DALEPENA, (1 << EP_OUT_IDX (0)) | (1 << EP_IN_IDX (0)));
+
+  /* set RUN/STOP bit */
+  MmioOr32 (DCTL, DCTL_RUN_STOP);
+}
+
+#define ALIGN(x, a)     (((x) + ((a) - 1)) & ~((a) - 1))
+
+STATIC
+VOID
+DriverInit (
+  VOID
+  )
+{
+  usb3_pcd_t          *pcd = &gPcd;
+  usb3_pcd_ep_t       *ep;
+
+  pcd->speed = USB_SPEED_UNKNOWN;
+
+  // init EP0
+  ep = &pcd->ep0;
+  ep->pcd = pcd;
+  ep->stopped = 1;
+  ep->is_in = 0;
+  ep->active = 0;
+  ep->phys = 0;
+  ep->num = 0;
+  ep->tx_fifo_num = 0;
+  ep->type = EPTYPE_CONTROL;
+  ep->maxburst = 0;
+  ep->maxpacket = USB3_MAX_EP0_SIZE;
+  ep->send_zlp = 0;
+  ep->req.length = 0;
+  ep->req.actual = 0;
+  pcd->ep0_req.length = 0;
+  pcd->ep0_req.actual = 0;
+
+  // init EP1 OUT
+  ep = &pcd->out_ep;
+  ep->pcd = pcd;
+  ep->stopped = 1;
+  ep->is_in = 0;
+  ep->active = 0;
+  ep->phys = USB3_BULK_OUT_EP << 1;
+  ep->num = 1;
+  ep->tx_fifo_num = 0;
+  // bulk ep is activated
+  ep->type = EPTYPE_BULK;
+  ep->maxburst = 0;
+  ep->maxpacket = USB3_MAX_PACKET_SIZE;
+  ep->send_zlp = 0;
+  ep->req.length = 0;
+  ep->req.actual = 0;
+
+  // init EP1 IN
+  ep = &pcd->in_ep;
+  ep->stopped = 1;
+  ep->is_in = 1;
+  ep->active = 0;
+  ep->phys = (USB3_BULK_IN_EP << 1) | 1;
+  ep->num = 1;
+  ep->tx_fifo_num = USB3_BULK_IN_EP;
+  // bulk ep is activated
+  ep->type = EPTYPE_BULK;
+  ep->maxburst = 0;
+  ep->maxpacket = USB3_MAX_PACKET_SIZE;
+  ep->send_zlp = 0;
+  ep->req.length = 0;
+  ep->req.actual = 0;
+
+  pcd->ep0state = EP0_IDLE;
+  pcd->ep0.maxpacket = USB3_MAX_EP0_SIZE;
+  pcd->ep0.type = EPTYPE_CONTROL;
+
+#if 0
+  pcd->ep0_setup_desc = (usb3_dma_desc_t *)ALIGN ((UINTN)pcd->ep0_setup, 16);
+  pcd->ep0_in_desc = (usb3_dma_desc_t *)ALIGN ((UINTN)pcd->ep0_in, 16);
+  pcd->ep0_out_desc = (usb3_dma_desc_t *)ALIGN ((UINTN)pcd->ep0_out, 16);
+  pcd->in_ep.ep_desc = (usb3_dma_desc_t *)ALIGN ((UINTN)pcd->in_ep.epx_desc, 16);
+  pcd->out_ep.ep_desc = (usb3_dma_desc_t *)ALIGN ((UINTN)pcd->out_ep.epx_desc, 16);
+#else
+  pcd->ep0_setup_desc = (usb3_dma_desc_t *)UncachedAllocateAlignedZeroPool (64, 64);
+  pcd->ep0_in_desc = (usb3_dma_desc_t *)UncachedAllocateAlignedZeroPool (64, 64);
+  pcd->ep0_out_desc = (usb3_dma_desc_t *)UncachedAllocateAlignedZeroPool (64, 64);
+  pcd->in_ep.ep_desc = (usb3_dma_desc_t *)UncachedAllocateAlignedZeroPool (64, 64);
+  pcd->out_ep.ep_desc = (usb3_dma_desc_t *)UncachedAllocateAlignedZeroPool (64, 64);
+#endif
+}
+
+STATIC
+VOID
+DwUsb3HandleUsbResetInterrupt (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb3_pcd_ep_t        *ep;
+
+  // clear stall on each EP
+  ep = &pcd->in_ep;
+  if (ep->xfer_started) {
+    if (ep->is_in) {
+      DwUsb3DepStopXfer (EP_IN_IDX (ep->num), ep->tri_in);
+    } else {
+      DwUsb3DepStopXfer (EP_OUT_IDX (ep->num), ep->tri_out);
+    }
+  }
+  if (ep->stopped) {
+    if (ep->is_in) {
+      DwUsb3DepClearStall (EP_IN_IDX (ep->num));
+    } else {
+      DwUsb3DepClearStall (EP_OUT_IDX (ep->num));
+    }
+  }
+
+  ep = &pcd->out_ep;
+  if (ep->xfer_started) {
+    if (ep->is_in) {
+      DwUsb3DepStopXfer (EP_IN_IDX (ep->num), ep->tri_in);
+    } else {
+      DwUsb3DepStopXfer (EP_OUT_IDX (ep->num), ep->tri_out);
+    }
+  }
+  if (ep->stopped) {
+    if (ep->is_in) {
+      DwUsb3DepClearStall (EP_IN_IDX (ep->num));
+    } else {
+      DwUsb3DepClearStall (EP_OUT_IDX (ep->num));
+    }
+  }
+
+  // set device address to 0
+  SET_DEVADDR (0);
+
+  pcd->ltm_enable = 0;
+  DEBUG ((DEBUG_INFO, "usb reset\n"));
+}
+
+STATIC
+UINT32
+DwUsb3GetDeviceSpeed (
+  IN usb3_pcd_t         *pcd
+  )
+{
+  UINT32                Data, Speed;
+
+  Data = MmioRead32 (DSTS);
+  switch (DSTS_GET_DEVSPD (Data)) {
+  case DEVSPD_HS_PHY_30MHZ_OR_60MHZ:
+    Speed = USB_SPEED_HIGH;
+    break;
+  case DEVSPD_FS_PHY_30MHZ_OR_60MHZ:
+  case DEVSPD_FS_PHY_48MHZ:
+    Speed = USB_SPEED_FULL;
+    break;
+  case DEVSPD_LS_PHY_6MHZ:
+    Speed = USB_SPEED_LOW;
+    break;
+  case DEVSPD_SS_PHY_125MHZ_OR_250MHZ:
+    Speed = USB_SPEED_SUPER;
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR, "DwUsb3GetDeviceSpeed: invalid DSTS:0x%x\n", Data));
+    Speed = USB_SPEED_UNKNOWN;
+    break;
+  }
+  return Speed;
+}
+
+STATIC
+VOID
+DwUsb3PcdSetSpeed (
+  IN usb3_pcd_t         *pcd,
+  IN UINTN              speed
+  )
+{
+  // set the MPS of EP0 based on the connection speed
+  switch (speed) {
+  case USB_SPEED_SUPER:
+    pcd->ep0.maxpacket = 512;
+    pcd->in_ep.maxpacket = USB3_MAX_PACKET_SIZE;
+    pcd->out_ep.maxpacket = USB3_MAX_PACKET_SIZE;
+    break;
+  case USB_SPEED_HIGH:
+    pcd->ep0.maxpacket = 64;
+    pcd->in_ep.maxpacket = USB2_HS_MAX_PACKET_SIZE;
+    pcd->out_ep.maxpacket = USB2_HS_MAX_PACKET_SIZE;
+    break;
+  case USB_SPEED_FULL:
+    pcd->ep0.maxpacket = 64;
+    pcd->in_ep.maxpacket = USB2_FS_MAX_PACKET_SIZE;
+    pcd->out_ep.maxpacket = USB2_FS_MAX_PACKET_SIZE;
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR, "invalid speed: %d\n", speed));
+    break;
+  }
+}
+
+STATIC
+VOID
+DwUsb3HandleConnectDoneInterrupt (
+  IN usb3_pcd_t         *pcd
+  )
+{
+  usb3_pcd_ep_t         *ep0 = &pcd->ep0;
+  UINT32                DiepCfg0, DoepCfg0, DiepCfg1, DoepCfg1;
+  UINT32                Speed;
+
+  ep0->stopped = 0;
+  Speed = (UINT32)DwUsb3GetDeviceSpeed (pcd);
+  pcd->speed = (UINT8)Speed;
+
+  DwUsb3PcdSetSpeed (pcd, Speed);
+  // set the MPS of EP0 based on the connection speed
+  DiepCfg0 = EPCFG0_EPTYPE (EPTYPE_CONTROL) | EPCFG0_CFG_ACTION (CFG_ACTION_MODIFY);
+  DiepCfg1 = EPCFG1_XFER_CMPL | EPCFG1_XFER_NRDY | EPCFG1_EP_DIR_IN;
+  DoepCfg0 = EPCFG0_EPTYPE (EPTYPE_CONTROL) | EPCFG0_CFG_ACTION (CFG_ACTION_MODIFY);
+  DoepCfg1 = EPCFG1_XFER_CMPL | EPCFG1_XFER_NRDY;
+
+  switch (Speed) {
+  case USB_SPEED_SUPER:
+    DiepCfg0 |= EPCFG0_MPS (512);
+    DoepCfg0 |= EPCFG0_MPS (512);
+    break;
+  case USB_SPEED_HIGH:
+  case USB_SPEED_FULL:
+    DiepCfg0 |= EPCFG0_MPS (64);
+    DoepCfg0 |= EPCFG0_MPS (64);
+    break;
+  case USB_SPEED_LOW:
+    DiepCfg0 |= EPCFG0_MPS (8);
+    DoepCfg0 |= EPCFG0_MPS (8);
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR, "DwUsb3HandleConnectDoneInterrupt: invalid speed %d\n", Speed));
+    break;
+  }
+  DiepCfg0 |= EPCFG0_TXFNUM (ep0->tx_fifo_num);
+  // issue DEPCFG command to EP0 OUT
+  DwUsb3DepCfg (EP_OUT_IDX (0), DoepCfg0, DoepCfg1, 0);
+  // issue DEPCFG command to EP0 IN
+  DwUsb3DepCfg (EP_IN_IDX (0), DiepCfg0, DiepCfg1, 0);
+  pcd->state = USB3_STATE_DEFAULT;
+}
+
+STATIC
+VOID
+DwUsb3HandleDeviceInterrupt (
+  IN usb3_pcd_t       *pcd,
+  IN UINT32           Event
+  )
+{
+  switch (Event & GEVNT_DEVT_MASK) {
+  case GEVNT_DEVT_USBRESET:
+    DwUsb3HandleUsbResetInterrupt (pcd);
+    break;
+  case GEVNT_DEVT_CONNDONE:
+    DwUsb3HandleConnectDoneInterrupt (pcd);
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR, "DwUsb3HandleDeviceInterrupt: invalid event\n"));
+    break;
+  }
+}
+
+STATIC
+usb3_pcd_ep_t *
+DwUsb3GetOutEndPoint (
+  IN usb3_pcd_t       *pcd,
+  IN UINT32           EndPointNum
+  )
+{
+  if (EndPointNum == 0) {
+    return &pcd->ep0;
+  }
+  return &pcd->out_ep;
+}
+
+STATIC
+usb3_pcd_ep_t *
+DwUsb3GetInEndPoint (
+  IN usb3_pcd_t       *pcd,
+  IN UINT32           EndPointNum
+  )
+{
+  if (EndPointNum == 0) {
+    return &pcd->ep0;
+  }
+  return &pcd->in_ep;
+}
+
+STATIC
+VOID
+EndPoint0DoStall (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb3_pcd_ep_t       *ep0 = &pcd->ep0;
+
+  // stall EP0 IN & OUT simultanelusly
+  ep0->is_in = 1;
+  DwUsb3DepSetStall (EP_IN_IDX (0));
+  ep0->is_in = 0;
+  DwUsb3DepSetStall (EP_OUT_IDX (0));
+  // prepare for the next setup transfer
+  ep0->stopped = 1;
+  pcd->ep0state = EP0_IDLE;
+  DwUsb3Ep0OutStart (pcd);
+}
+
+STATIC
+VOID
+EndPoint0ContinueTransfer (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_req_t   *req
+  )
+{
+  usb3_pcd_ep_t       *ep0 = &pcd->ep0;
+  usb3_dma_desc_t     *desc;
+  UINT64              desc_dma;
+  UINT8               tri;
+
+  // send a 0-byte length packet after the end of transfer
+  if (ep0->is_in) {
+    desc = pcd->ep0_in_desc;
+    desc_dma = (UINT64)pcd->ep0_in_desc;
+    // DMA descriptor setup
+    DwUsb3FillDesc (
+      desc,
+      (UINT64)req->bufdma,
+      0,
+      0,
+      TRBCTL_NORMAL,
+      DSCCTL_IOC | DSCCTL_ISP | DSCCTL_LST,
+      1
+      );
+    tri = DwUsb3DepStartXfer (EP_IN_IDX (0), desc_dma, 0);
+    ep0->tri_in = tri;
+  }
+}
+
+STATIC
+VOID
+EndPoint0CompleteRequest (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_req_t   *req,
+  IN usb3_dma_desc_t  *desc
+  )
+{
+  usb3_pcd_ep_t      *ep = &pcd->ep0;
+
+  if (req == NULL) {
+    return;
+  }
+
+  if ((pcd->ep0state == EP0_OUT_DATA_PHASE) ||
+      (pcd->ep0state == EP0_IN_DATA_PHASE)) {
+    if (ep->is_in) {
+      if (GET_DSCSTS_XFERCNT (desc->status) == 0) {
+        pcd->ep0.is_in = 0;
+        pcd->ep0state = EP0_OUT_WAIT_NRDY;
+      }
+    } else {
+      pcd->ep0.is_in = 1;
+      pcd->ep0state = EP0_IN_WAIT_NRDY;
+    }
+  }
+}
+
+STATIC
+VOID
+DwUsb3OsGetTrb (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_ep_t    *ep,
+  IN usb3_pcd_req_t   *req
+  )
+{
+  // If EP0, fill request with EP0 IN/OUT data TRB
+  if (ep == &pcd->ep0) {
+    if (ep->is_in) {
+      req->trb = pcd->ep0_in_desc;
+      req->trbdma = (UINT64)pcd->ep0_in_desc;
+    } else {
+      req->trb = pcd->ep0_out_desc;
+      req->trbdma = (UINT64)pcd->ep0_out_desc;
+    }
+  } else {
+    // fill request with TRB from the non-EP0 allocation
+    req->trb = ep->ep_desc;
+    req->trbdma = (UINT64)ep->ep_desc;
+  }
+}
+
+STATIC
+VOID
+DwUsb3EndPoint0StartTransfer (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_req_t   *req
+  )
+{
+  usb3_pcd_ep_t       *ep0 = &pcd->ep0;
+  usb3_dma_desc_t     *desc;
+  UINT64              desc_dma;
+  UINT32              desc_type, len;
+
+  // get the DMA descriptor (TRB) for this request
+  DwUsb3OsGetTrb (pcd, ep0, req);
+  desc = req->trb;
+  desc_dma = req->trbdma;
+
+  if (ep0->is_in) {
+    // start DMA on EP0 IN
+    // DMA Descriptor (TRB) setup
+    len = req->length;
+    if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
+      if (ep0->three_stage) {
+        desc_type = TRBCTL_STATUS_3;
+      } else {
+        desc_type = TRBCTL_STATUS_2;
+      }
+    } else {
+      desc_type = TRBCTL_CTLDATA_1ST;
+    }
+    DwUsb3FillDesc (
+      desc,
+      (UINT64)req->bufdma,
+      len,
+      0,
+      desc_type,
+      DSCCTL_IOC | DSCCTL_ISP | DSCCTL_LST,
+      1
+      );
+    // issue DEPSTRTXFER command to EP0 IN
+    ep0->tri_in = DwUsb3DepStartXfer (EP_IN_IDX (0), desc_dma, 0);
+  } else {
+    // start DMA on EP0 OUT
+    // DMA Descriptor (TRB) setup
+    len = ALIGN (req->length, ep0->maxpacket);
+    if (pcd->ep0state == EP0_OUT_STATUS_PHASE) {
+      if (ep0->three_stage) {
+        desc_type = TRBCTL_STATUS_3;
+      } else {
+        desc_type = TRBCTL_STATUS_2;
+      }
+    } else {
+      desc_type = TRBCTL_CTLDATA_1ST;
+    }
+    DwUsb3FillDesc (
+      desc,
+      (UINT64)req->bufdma,
+      len,
+      0,
+      desc_type,
+      DSCCTL_IOC | DSCCTL_ISP | DSCCTL_LST,
+      1
+      );
+    // issue DEPSTRTXFER command to EP0 OUT
+    ep0->tri_out = DwUsb3DepStartXfer (EP_OUT_IDX (0), desc_dma, 0);
+  }
+}
+
+STATIC
+INTN
+DwUsb3EndPointXStartTransfer (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_ep_t    *ep
+  )
+{
+  usb3_pcd_req_t      *req = &ep->req;
+  usb3_dma_desc_t     *desc;
+  UINT64              desc_dma;
+  UINT32              len;
+
+  // get the TRB for this request
+  DwUsb3OsGetTrb (pcd, ep, req);
+  desc = req->trb;
+  desc_dma = req->trbdma;
+
+  if (ep->is_in) {
+    // For IN, TRB length is just xfer length
+    len = req->length;
+    if (ep->xfer_started && !(desc->control & DSCCTL_HWO)) {
+      DEBUG ((DEBUG_INFO, "[%a] last tx succ, but not in 10s!\n", __func__));
+      ep->xfer_started = 0;
+    }
+  } else {
+    // For OUT, TRB length must be multiple of maxpacket
+    // must be power of 2, use cheap AND
+    len = (req->length + ep->maxpacket - 1) & ~(ep->maxpacket - 1);
+    req->length = len;
+  }
+  // DMA descriptor setup
+  DwUsb3FillDesc (
+    desc,
+    (UINT64)req->bufdma,
+    len,
+    0,
+    TRBCTL_NORMAL,
+    DSCCTL_IOC | DSCCTL_ISP | DSCCTL_LST,
+    1
+    );
+  if (ep->is_in) {
+    // start DMA on EPn IN
+    if (ep->xfer_started) {
+      // issue DEPUPDTXFER command to EP
+      DwUsb3DepUpdateXfer (EP_IN_IDX (ep->num), ep->tri_in);
+    } else {
+      ep->tri_in = DwUsb3DepStartXfer (EP_IN_IDX (ep->num), desc_dma, 0);
+      ep->xfer_started = 1;
+    }
+  } else {
+    // start DMA on EPn OUT
+    if (ep->xfer_started) {
+      // issue DEPUPDTXFER command to EP
+      DwUsb3DepUpdateXfer (EP_OUT_IDX (ep->num), ep->tri_out);
+    } else {
+      ep->tri_out = DwUsb3DepStartXfer (EP_OUT_IDX (ep->num), desc_dma, 0);
+      ep->xfer_started = 1;
+    }
+  }
+  if (ep->is_in) {
+    UINT32       count = 0;
+    // wait until send complete
+    while ((desc->control & DSCCTL_HWO) && (count < 1000000)) {
+      MicroSecondDelay (10);
+      count++;
+    }
+    if (count >= 1000000) {
+      DEBUG ((DEBUG_INFO, "[%a]: ep%d transfer timeout!\n", __func__, ep->num));
+      DEBUG ((DEBUG_INFO, "please disconnect then connect USB cable again to recovery!\n"));
+      return -1;
+    }
+    ep->xfer_started = 0;
+  }
+  return 0;
+}
+
+#if 0
+STATIC
+VOID
+DwUsb3EndPointXStopTransfer (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_ep_t    *ep
+  )
+{
+  if (ep->is_in) {
+    DwUsb3DepStopXfer (EP_IN_IDX (ep->num), ep->tri_in);
+  } else {
+    DwUsb3DepStopXfer (EP_OUT_IDX (ep->num), ep->tri_out);
+  }
+}
+#endif
+
+STATIC
+VOID
+SetupInStatusPhase (
+  IN usb3_pcd_t       *pcd,
+  IN VOID             *buf
+  )
+{
+  usb3_pcd_ep_t       *ep0 = &pcd->ep0;
+
+  if (pcd->ep0state == EP0_STALL)
+    return;
+
+  ep0->is_in = 1;
+  pcd->ep0state = EP0_IN_STATUS_PHASE;
+  pcd->ep0_req.bufdma = buf;
+  pcd->ep0_req.length = 0;
+  pcd->ep0_req.actual = 0;
+  DwUsb3EndPoint0StartTransfer (pcd, &pcd->ep0_req);
+}
+
+STATIC
+VOID
+SetupOutStatusPhase (
+  IN usb3_pcd_t       *pcd,
+  IN VOID             *buf
+  )
+{
+  usb3_pcd_ep_t       *ep0 = &pcd->ep0;
+
+  if (pcd->ep0state == EP0_STALL)
+    return;
+
+  ep0->is_in = 0;
+  pcd->ep0state = EP0_OUT_STATUS_PHASE;
+  pcd->ep0_req.bufdma = buf;
+  pcd->ep0_req.length = 0;
+  pcd->ep0_req.actual = 0;
+  DwUsb3EndPoint0StartTransfer (pcd, &pcd->ep0_req);
+}
+
+STATIC
+VOID
+DwUsb3HandleEndPoint0 (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_req_t   *req,
+  IN UINT32           event
+  )
+{
+  usb3_pcd_ep_t       *ep0 = &pcd->ep0;
+  usb3_dma_desc_t     *desc;
+  UINT32              byte_count, len;
+
+  switch (pcd->ep0state) {
+  case EP0_IN_DATA_PHASE:
+    if (req == NULL) {
+      req = &pcd->ep0_req;
+    }
+    desc = pcd->ep0_in_desc;
+
+    if (desc->control & DSCCTL_HWO) {
+      goto out;
+    }
+
+    if (GET_DSCSTS_TRBRSP (desc->status) == TRBRSP_SETUP_PEND) {
+      // start of a new control transfer
+      desc->status = 0;
+    }
+    byte_count = req->length - GET_DSCSTS_XFERCNT (desc->status);
+    req->actual += byte_count;
+    req->bufdma += byte_count;
+
+    if (req->actual < req->length) {
+      // IN CONTINUE, stall EP0
+      EndPoint0DoStall (pcd);
+    } else if (ep0->send_zlp) {
+      // CONTINUE TRANSFER IN ZLP
+      EndPoint0ContinueTransfer (pcd, req);
+      ep0->send_zlp = 0;
+    } else {
+      // COMPLETE IN TRANSFER
+      EndPoint0CompleteRequest (pcd, req, desc);
+    }
+    break;
+  case EP0_OUT_DATA_PHASE:
+    if (req == NULL) {
+      req = &pcd->ep0_req;
+    }
+    desc = pcd->ep0_out_desc;
+
+    if (desc->control & DSCCTL_HWO) {
+      goto out;
+    }
+
+    if (GET_DSCSTS_TRBRSP (desc->status) == TRBRSP_SETUP_PEND) {
+      // start of a new control transfer
+      desc->status = 0;
+    }
+    len = (req->length + ep0->maxpacket - 1) & ~(ep0->maxpacket - 1);
+    byte_count = len - GET_DSCSTS_XFERCNT (desc->status);
+    req->actual += byte_count;
+    req->bufdma += byte_count;
+
+    if (req->actual < req->length) {
+      // IN CONTINUE, stall EP0
+      EndPoint0DoStall (pcd);
+    } else if (ep0->send_zlp) {
+      // CONTINUE TRANSFER IN ZLP
+      EndPoint0ContinueTransfer (pcd, req);
+      ep0->send_zlp = 0;
+    } else {
+      // COMPLETE IN TRANSFER
+      EndPoint0CompleteRequest (pcd, req, desc);
+    }
+    break;
+#if 0
+  case EP0_IN_WAIT_NRDY:
+  case EP0_OUT_WAIT_NRDY:
+    if (ep0->is_in) {
+      SetupInStatusPhase (pcd, gEndPoint0SetupPacket);
+    } else {
+      SetupOutStatusPhase (pcd, gEndPoint0SetupPacket);
+    }
+    break;
+  case EP0_IN_STATUS_PHASE:
+  case EP0_OUT_STATUS_PHASE:
+    if (ep0->is_in) {
+      desc = pcd->ep0_in_desc;
+    } else {
+      desc = pcd->ep0_out_desc;
+    }
+//ASSERT (0);
+    EndPoint0CompleteRequest (pcd, req, desc);
+    // skip test mode
+    pcd->ep0state = EP0_IDLE;
+    ep0->stopped = 1;
+    ep0->is_in = 0;  // OUT for next SETUP
+    // prepare for more SETUP packets
+    DwUsb3Ep0OutStart (pcd);
+    break;
+#else
+  case EP0_IN_WAIT_NRDY:
+    if (ep0->is_in) {
+      SetupInStatusPhase (pcd, gEndPoint0SetupPacket);
+    } else {
+      ASSERT (0);
+    }
+    break;
+  case EP0_OUT_WAIT_NRDY:
+    if (!ep0->is_in) {
+      SetupOutStatusPhase (pcd, gEndPoint0SetupPacket);
+    } else {
+      ASSERT (0);
+    }
+    break;
+  case EP0_IN_STATUS_PHASE:
+    if (ep0->is_in) {
+      desc = pcd->ep0_in_desc;
+    } else {
+      ASSERT (0);
+    }
+    EndPoint0CompleteRequest (pcd, req, desc);
+    pcd->ep0state = EP0_IDLE;
+    ep0->stopped = 1;
+    ep0->is_in = 0;  // OUT for next SETUP
+    // prepare for more SETUP packets
+    DwUsb3Ep0OutStart (pcd);
+    break;
+  case EP0_OUT_STATUS_PHASE:
+    if (!ep0->is_in) {
+      desc = pcd->ep0_out_desc;
+    } else {
+      ASSERT (0);
+    }
+    EndPoint0CompleteRequest (pcd, req, desc);
+    pcd->ep0state = EP0_IDLE;
+    ep0->stopped = 1;
+    ep0->is_in = 0;  // OUT for next SETUP
+    // prepare for more SETUP packets
+    DwUsb3Ep0OutStart (pcd);
+    break;
+#endif
+  case EP0_STALL:
+    break;
+  case EP0_IDLE:
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR, "%a: invalid state %d\n", __func__, pcd->ep0state));
+    break;
+  }
+out:
+  return;
+}
+
+STATIC
+usb3_pcd_ep_t *
+Addr2EndPoint (
+  IN usb3_pcd_t       *pcd,
+  IN UINT16           index
+  )
+{
+  UINT32              ep_num;
+
+  ep_num = UE_GET_ADDR (index);
+  if (ep_num == 0) {
+    return &pcd->ep0;
+  } else {
+    if (UE_GET_DIR (index) == UE_DIR_IN) {
+      return &pcd->in_ep;
+    }
+    return &pcd->out_ep;
+  }
+}
+
+STATIC
+VOID
+DwUsb3DoGetStatus (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb_device_request_t   *ctrl = &gEndPoint0SetupPacket->req;
+  UINT8                  *status = gEndPoint0StatusBuf;
+  usb3_pcd_ep_t          *ep;
+
+  if (ctrl->wLength != 2) {
+    EndPoint0DoStall (pcd);
+    return;
+  }
+
+  switch (UT_GET_RECIPIENT (ctrl->bmRequestType)) {
+  case UT_DEVICE:
+    *status = 0;   // bus powered
+    if (pcd->speed == USB_SPEED_SUPER) {
+      if (pcd->state == USB3_STATE_CONFIGURED) {
+        if (MmioRead32 (DCTL) & DCTL_INIT_U1_EN) {
+          *status |= 1 << 2;
+        }
+        if (MmioRead32 (DCTL) & DCTL_INIT_U2_EN) {
+          *status |= 1 << 3;
+        }
+        *status |= (UINT8)(pcd->ltm_enable << 4);
+      }
+    }
+    *(status + 1) = 0;
+    break;
+  case UT_INTERFACE:
+    *status = 0;
+    *(status + 1) = 0;
+    break;
+  case UT_ENDPOINT:
+    ep = Addr2EndPoint (pcd, ctrl->wIndex);
+    *status = ep->stopped;
+    *(status + 1) = 0;
+    break;
+  default:
+    EndPoint0DoStall (pcd);
+    return;
+  }
+  pcd->ep0_req.bufdma = (UINT64 *)status;
+  pcd->ep0_req.length = 2;
+  pcd->ep0_req.actual = 0;
+  DwUsb3EndPoint0StartTransfer (pcd, &pcd->ep0_req);
+}
+
+STATIC
+VOID
+DoClearHalt (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_ep_t    *ep
+  )
+{
+  if (ep->is_in) {
+    DwUsb3DepClearStall (EP_IN_IDX (ep->num));
+  } else {
+    DwUsb3DepClearStall (EP_OUT_IDX (ep->num));
+  }
+  if (ep->stopped) {
+    ep->stopped = 0;
+  }
+}
+
+STATIC
+VOID
+Usb3PcdEpEnable (
+  IN usb3_pcd_t        *pcd,
+  IN usb3_pcd_ep_t     *ep
+  )
+{
+  // activate the EP
+  ep->stopped = 0;
+  ep->xfer_started = 0;
+  ep->ep_desc->control = 0;
+  ep->ep_desc->status = 0;
+  // set initial data pid.
+  if (ep->type == EPTYPE_BULK) {
+    ep->data_pid_start = 0;
+  }
+  DwUsb3EpActivate (pcd, ep);
+}
+
+STATIC
+VOID
+DwUsb3DoClearFeature (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb_device_request_t  *ctrl = &gEndPoint0SetupPacket->req;
+  usb3_pcd_ep_t  *ep;
+
+  switch (UT_GET_RECIPIENT (ctrl->bmRequestType)) {
+  case UT_DEVICE:
+    switch (ctrl->wValue) {
+    case UF_U1_ENABLE:
+      if ((pcd->speed != USB_SPEED_SUPER) ||
+          (pcd->state != USB3_STATE_CONFIGURED)) {
+        EndPoint0DoStall (pcd);
+        return;
+      }
+      MmioAnd32 (DCTL, ~DCTL_INIT_U1_EN);
+      break;
+    case UF_U2_ENABLE:
+      if ((pcd->speed != USB_SPEED_SUPER) ||
+          (pcd->state != USB3_STATE_CONFIGURED)) {
+        EndPoint0DoStall (pcd);
+        return;
+      }
+      MmioAnd32 (DCTL, ~DCTL_INIT_U2_EN);
+      break;
+    case UF_LTM_ENABLE:
+      if ((pcd->speed != USB_SPEED_SUPER) ||
+          (pcd->state != USB3_STATE_CONFIGURED) ||
+          (ctrl->wIndex != 0)) {
+        EndPoint0DoStall (pcd);
+        return;
+      }
+      pcd->ltm_enable = 0;
+      break;
+    default:
+      EndPoint0DoStall (pcd);
+      return;
+    }
+    break;
+  case UT_INTERFACE:
+    // if FUNCTION_SUSPEND
+    if (ctrl->wValue) {
+      EndPoint0DoStall (pcd);
+      return;
+    }
+    break;
+  case UT_ENDPOINT:
+    ep = Addr2EndPoint (pcd, ctrl->wIndex);
+    if (ctrl->wValue != UF_ENDPOINT_HALT) {
+      EndPoint0DoStall (pcd);
+      return;
+    }
+    DoClearHalt (pcd, ep);
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR, "invalid bmRequestType :%d\n", UT_GET_RECIPIENT (ctrl->bmRequestType)));
+    break;
+  }
+  pcd->ep0.is_in = 1;
+  pcd->ep0state = EP0_IN_WAIT_NRDY;
+}
+
+STATIC
+VOID
+DwUsb3DoSetFeature (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb_device_request_t  *ctrl = &gEndPoint0SetupPacket->req;
+  usb3_pcd_ep_t  *ep;
+
+  switch (UT_GET_RECIPIENT (ctrl->bmRequestType)) {
+  case UT_DEVICE:
+    switch (ctrl->wValue) {
+    case UF_DEVICE_REMOTE_WAKEUP:
+      break;
+    case UF_TEST_MODE:
+      pcd->test_mode_nr = ctrl->wIndex >> 8;
+      pcd->test_mode = 1;
+      break;
+    case UF_U1_ENABLE:
+      if ((pcd->speed != USB_SPEED_SUPER) ||
+          (pcd->state != USB3_STATE_CONFIGURED)) {
+        EndPoint0DoStall (pcd);
+        return;
+      }
+      MmioOr32 (DCTL, DCTL_INIT_U1_EN);
+      break;
+    case UF_U2_ENABLE:
+      if ((pcd->speed != USB_SPEED_SUPER) ||
+          (pcd->state != USB3_STATE_CONFIGURED)) {
+        EndPoint0DoStall (pcd);
+        return;
+      }
+      MmioOr32 (DCTL, DCTL_INIT_U2_EN);
+      break;
+    case UF_LTM_ENABLE:
+      if ((pcd->speed != USB_SPEED_SUPER) ||
+          (pcd->state != USB3_STATE_CONFIGURED) ||
+          (ctrl->wIndex != 0)) {
+        EndPoint0DoStall (pcd);
+        return;
+      }
+      pcd->ltm_enable = 1;
+      break;
+    default:
+      EndPoint0DoStall (pcd);
+      return;
+    }
+    break;
+  case UT_INTERFACE:
+    // if FUNCTION_SUSPEND
+    if (ctrl->wValue) {
+      EndPoint0DoStall (pcd);
+      return;
+    }
+    break;
+  case UT_ENDPOINT:
+    ep = Addr2EndPoint (pcd, ctrl->wIndex);
+    if (ctrl->wValue != UF_ENDPOINT_HALT) {
+      EndPoint0DoStall (pcd);
+      return;
+    }
+    ep->stopped = 1;
+    if (ep->is_in) {
+      DwUsb3DepClearStall (EP_IN_IDX (ep->num));
+    } else {
+      DwUsb3DepClearStall (EP_OUT_IDX (ep->num));
+    }
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR, "invalid bmRequestType %d\n", UT_GET_RECIPIENT (ctrl->bmRequestType)));
+    break;
+  }
+  pcd->ep0.is_in = 1;
+  pcd->ep0state = EP0_IN_WAIT_NRDY;
+}
+
+STATIC
+VOID
+DwUsb3DoSetAddress (
+  IN usb3_pcd_t          *pcd
+  )
+{
+  usb_device_request_t *ctrl = &gEndPoint0SetupPacket->req;
+
+  if (ctrl->bmRequestType == UT_DEVICE) {
+    SET_DEVADDR (ctrl->wValue);
+    pcd->ep0.is_in = 1;
+    pcd->ep0state = EP0_IN_WAIT_NRDY;
+    if (ctrl->wValue) {
+      pcd->state = USB3_STATE_ADDRESSED;
+    } else {
+      pcd->state = USB3_STATE_DEFAULT;
+    }
+  }
+}
+
+#if 0
+STATIC
+UINTN
+UsbStatus (
+  IN UINTN                        online,
+  IN UINTN                        speed
+  )
+{
+  if (online) {
+}
+
+VOID
+DwUsb3SetConfig (
+  IN usb3_pcd_t           *pcd
+  )
+{
+  usb_device_request_t   *ctrl = &gEndPoint0SetupPacket->req;
+  UINT16         wvalue = ctrl->wValue;
+  usb3_pcd_ep_t     *ep;
+
+DEBUG ((DEBUG_ERROR, "#%a, %d, wvalue:0x%x\n", __func__, __LINE__, wvalue));
+  if (ctrl->bmRequestType != (UT_WRITE | UT_STANDARD | UT_DEVICE)) {
+    EndPoint0DoStall (pcd);
+    return;
+  }
+
+  if (!wvalue || (wvalue == CONFIG_VALUE)) {
+    UINT32         speed;
+    pcd->new_config = (UINT8)wvalue;
+    // set new configuration
+    if (wvalue) {
+      // activate bulk in endpoint
+      ep = &pcd->in_ep;
+      Usb3PcdEpEnable (pcd, ep);
+      // activate bulk out endpoint
+      ep = &pcd->out_ep;
+      Usb3PcdEpEnable (pcd, ep);
+      // prepare for next bulk transfer
+      speed = DwUsb3GetDeviceSpeed (pcd);
+      (VOID)speed;
+
+#if 0
+      if (g_usb_ops->status) {
+        g_usb_ops->status (ctrl->wValue ? 1 : 0,
+                           speed == USB_SPEED_SUPER ? USB_SS : speed == USB_SPEED_HIGH ? USB_HS : USB_FS);
+      }
+      usb_status ();
+#endif
+      pcd->state = USB3_STATE_CONFIGURED;
+    } else {
+      pcd->state = USB3_STATE_ADDRESSED;
+    }
+DEBUG ((DEBUG_ERROR, "#%a, %d, state:%d\n", __func__, __LINE__, pcd->state));
+    pcd->ep0.is_in = 1;
+    pcd->ep0state = EP0_IN_WAIT_NRDY;
+  } else {
+    EndPoint0DoStall (pcd);
+  }
+}
+#endif
+
+STATIC
+VOID
+DwUsb3DoGetConfig (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb_device_request_t  *ctrl = &gEndPoint0SetupPacket->req;
+  UINT8  *status = gEndPoint0StatusBuf;
+
+  if (ctrl->bmRequestType != (UT_READ | UT_STANDARD | UT_DEVICE)) {
+    EndPoint0DoStall (pcd);
+    return;
+  }
+  // Notify host the current config value
+  *status = pcd->new_config;
+  pcd->ep0_req.bufdma = (UINT64 *)status;
+  pcd->ep0_req.length = 1;
+  pcd->ep0_req.actual = 0;
+  DwUsb3EndPoint0StartTransfer (pcd, &pcd->ep0_req);
+}
+
+STATIC
+VOID
+DwUsb3DoSetConfig (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb_device_request_t  *ctrl = &gEndPoint0SetupPacket->req;
+  UINT16  wvalue = ctrl->wValue;
+  usb3_pcd_ep_t  *ep;
+
+  if (ctrl->bmRequestType != (UT_WRITE | UT_STANDARD | UT_DEVICE)) {
+    EndPoint0DoStall (pcd);
+    return;
+  }
+
+  if (!wvalue || (wvalue == CONFIG_VALUE)) {
+    //UINT32 speed;
+
+    pcd->new_config = (UINT8)wvalue;
+    // set new configuration
+    if (wvalue) {
+      // activate bulk in endpoint
+      ep = &pcd->in_ep;
+      Usb3PcdEpEnable (pcd, ep);
+      // activate bulk out endpoint
+      ep = &pcd->out_ep;
+      Usb3PcdEpEnable (pcd, ep);
+#if 0
+      // prepare for next bulk transfer
+      speed = DwUsb3GetDeviceSpeed (pcd);
+      (VOID)speed;
+      g_usb_ops->status
+#endif
+      pcd->state = USB3_STATE_CONFIGURED;
+      {
+        // prepare for EP1 OUT
+        usb3_pcd_ep_t                 *ep = &pcd->out_ep;
+        usb3_pcd_req_t                *req = &ep->req;
+
+        // AndroidFast App will free the rx buffer.
+        gRxBuf = AllocatePool (DATA_SIZE);
+        ASSERT (gRxBuf != NULL);
+        WriteBackDataCacheRange (gRxBuf, DATA_SIZE);
+        req->bufdma = (UINT64 *)gRxBuf;
+        req->length = DATA_SIZE;
+        DwUsb3EndPointXStartTransfer (pcd, ep);
+      }
+    } else {
+      pcd->state = USB3_STATE_ADDRESSED;
+    }
+    pcd->ep0.is_in = 1;
+    pcd->ep0state = EP0_IN_WAIT_NRDY;
+  } else {
+    EndPoint0DoStall (pcd);
+  }
+}
+
+STATIC
+VOID
+DwUsb3DoGetDescriptor (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb_device_request_t  *ctrl = &gEndPoint0SetupPacket->req;
+  UINT8                 dt = ctrl->wValue >> 8;
+  UINT8                 index = (UINT8)ctrl->wValue;
+  UINT16                len = ctrl->wLength;
+  UINT8                 *buf = gEndPoint0StatusBuf;
+  UINT16                value = 0;
+  EFI_USB_STRING_DESCRIPTOR        *Descriptor = NULL;
+
+  if (ctrl->bmRequestType != (UT_READ | UT_STANDARD | UT_DEVICE)) {
+    EndPoint0DoStall (pcd);
+    return;
+  }
+
+  switch (dt) {
+  case UDESC_DEVICE:
+    {
+      struct usb_device_descriptor  *dev = &gDwUsb3DevDesc;
+      dev->bLength = sizeof (struct usb_device_descriptor);
+      dev->bDescriptorType = UDESC_DEVICE;
+      dev->bDeviceClass = 0;
+      dev->bDeviceSubClass = 0;
+      dev->bDeviceProtocol = 0;
+      if (pcd->speed == USB_SPEED_SUPER) {
+        dev->bcdUSB = 0x300;
+        // 2^9 = 512
+        dev->bMaxPacketSize0 = 9;
+      } else {
+        dev->bcdUSB = 0x0200;
+        dev->bMaxPacketSize0 = 0x40;
+      }
+      dev->idVendor = usb_port_activity_config.idVendor;
+      dev->idProduct = usb_port_activity_config.idProduct;
+      dev->bcdDevice = 0x0100;
+      dev->iManufacturer = STRING_MANUFACTURER;
+      dev->iProduct = STRING_PRODUCT;
+      dev->iSerialNumber = STRING_SERIAL;
+      dev->bNumConfigurations = 1;
+      value = sizeof (struct usb_device_descriptor);
+      CopyMem ((void *)buf, (void *)dev, value);
+    }
+    break;
+  case UDESC_DEVICE_QUALIFIER:
+    {
+      struct usb_qualifier_descriptor   *qual = (struct usb_qualifier_descriptor *)buf;
+      struct usb_device_descriptor *dev = &gDwUsb3DevDesc;
+
+      qual->bLength = sizeof (*qual);
+      qual->bDescriptorType = UDESC_DEVICE_QUALIFIER;
+      qual->bcdUSB = dev->bcdUSB;
+      qual->bDeviceClass = dev->bDeviceClass;
+      qual->bDeviceSubClass = dev->bDeviceSubClass;
+      qual->bDeviceProtocol = dev->bDeviceProtocol;
+      qual->bMaxPacketSize0 = dev->bMaxPacketSize0;
+      qual->bNumConfigurations = 1;
+      qual->bRESERVED = 0;
+      value = sizeof (struct usb_qualifier_descriptor);
+    }
+    break;
+
+  case UDESC_CONFIG:
+    {
+      struct usb_config_descriptor    *config = (struct usb_config_descriptor *)buf;
+
+      config->bLength = sizeof (*config);
+      config->bDescriptorType = UDESC_CONFIG;
+      config->bNumInterfaces = 1;
+      config->bConfigurationValue = 1;
+      config->iConfiguration = 0;
+      config->bmAttributes = USB_CONFIG_ATT_ONE;
+
+      if (pcd->speed == USB_SPEED_SUPER) {
+        config->bMaxPower = 0x50;
+      } else {
+        config->bMaxPower = 0x80;
+      }
+      buf += sizeof (*config);
+
+      intf.bInterfaceSubClass = usb_port_activity_config.bInterfaceSubClass;
+      intf.bInterfaceProtocol = usb_port_activity_config.bInterfaceProtocol;
+      CopyMem ((void *)buf, (void *)&intf, sizeof (intf));
+      buf += sizeof (intf);
+
+      switch (pcd->speed) {
+      case USB_SPEED_SUPER:
+        CopyMem (buf, &ss_bulk_in, sizeof (ss_bulk_in));
+        buf += sizeof (ss_bulk_in);
+        CopyMem (buf, &ep_comp, sizeof (ep_comp));
+        buf += sizeof (ep_comp);
+        CopyMem (buf, &ss_bulk_out, sizeof (ss_bulk_out));
+        buf += sizeof (ss_bulk_out);
+        CopyMem (buf, &ep_comp, sizeof (ep_comp));
+
+        config->wTotalLength = sizeof (*config) + sizeof (intf) + sizeof (ss_bulk_in) +
+                               sizeof (ep_comp) + sizeof (ss_bulk_out) + sizeof (ep_comp);
+        break;
+
+      default: // HS/FS
+        {
+          struct usb_endpoint_descriptor  *endp = (struct usb_endpoint_descriptor *)buf;
+
+          CopyMem (buf, &hs_bulk_in, sizeof (hs_bulk_in));
+          (endp++)->wMaxPacketSize = pcd->in_ep.maxpacket;
+          buf += sizeof (hs_bulk_in);
+          CopyMem (buf, &hs_bulk_out, sizeof (hs_bulk_out));
+          endp->wMaxPacketSize = pcd->out_ep.maxpacket;
+          config->wTotalLength = sizeof (*config) + sizeof (intf) + sizeof (hs_bulk_in) +
+                                 sizeof (hs_bulk_out);
+          break;
+        }
+      }
+      value = config->wTotalLength;
+    }
+    break;
+
+  case UDESC_STRING:
+    {
+      switch (index) {
+      case STRING_LANGUAGE:
+        Descriptor = (EFI_USB_STRING_DESCRIPTOR *)(UINTN)gEndPoint0StatusBuf;
+        ASSERT (Descriptor != NULL);
+        Descriptor->Length = LANG_LENGTH * sizeof (CHAR16);
+        Descriptor->DescriptorType = USB_DESC_TYPE_STRING;
+        DwUsb->GetLang (Descriptor->String, &Descriptor->Length);
+        value = Descriptor->Length;
+        break;
+      case STRING_MANUFACTURER:
+        Descriptor = (EFI_USB_STRING_DESCRIPTOR *)(UINTN)gEndPoint0StatusBuf;
+        ASSERT (Descriptor != NULL);
+        Descriptor->Length = MANU_FACTURER_STRING_LENGTH * sizeof (CHAR16);
+        Descriptor->DescriptorType = USB_DESC_TYPE_STRING;
+        DwUsb->GetManuFacturer (Descriptor->String, &Descriptor->Length);
+        value = Descriptor->Length;
+        break;
+      case STRING_PRODUCT:
+        Descriptor = (EFI_USB_STRING_DESCRIPTOR *)(UINTN)gEndPoint0StatusBuf;
+        ASSERT (Descriptor != NULL);
+        Descriptor->Length = PRODUCT_STRING_LENGTH * sizeof (CHAR16);
+        Descriptor->DescriptorType = USB_DESC_TYPE_STRING;
+        DwUsb->GetProduct (Descriptor->String, &Descriptor->Length);
+        value = Descriptor->Length;
+        break;
+      case STRING_SERIAL:
+        Descriptor = (EFI_USB_STRING_DESCRIPTOR *)(UINTN)gEndPoint0StatusBuf;
+        ASSERT (Descriptor != NULL);
+        Descriptor->Length = SERIAL_STRING_LENGTH * sizeof (CHAR16);
+        Descriptor->DescriptorType = USB_DESC_TYPE_STRING;
+        DwUsb->GetSerialNo (Descriptor->String, &Descriptor->Length);
+        value = Descriptor->Length;
+        break;
+      default:
+        EndPoint0DoStall (pcd);
+        break;
+      }
+    }
+    break;
+
+  case UDESC_BOS:
+    if (pcd->speed != USB_SPEED_SUPER) {
+      EndPoint0DoStall (pcd);
+      return;
+    }
+    value = bos.wTotalLength;
+    CopyMem (buf, &bos, sizeof (bos));
+    buf += sizeof (bos);
+    CopyMem (buf, &cap1, sizeof (cap1));
+    buf += sizeof (cap1);
+    CopyMem (buf, &cap2, sizeof (cap2));
+    buf += sizeof (cap2);
+    CopyMem (buf, &cap3, sizeof (cap3));
+    break;
+  default:
+    EndPoint0DoStall (pcd);
+    return;
+  }
+  pcd->ep0_req.bufdma = (UINT64 *)gEndPoint0StatusBuf;
+  pcd->ep0_req.length = value < len ? value : len;
+  pcd->ep0_req.actual = 0;
+  DwUsb3EndPoint0StartTransfer (pcd, &pcd->ep0_req);
+}
+
+STATIC
+VOID
+DwUsb3DoSetup (
+  IN usb3_pcd_t       *pcd
+  )
+{
+  usb_device_request_t  *ctrl = &gEndPoint0SetupPacket->req;
+  usb3_pcd_ep_t         *ep0 = &pcd->ep0;
+  UINT16                wLength;
+
+  wLength = ctrl->wLength;
+  ep0->stopped = 0;
+  ep0->three_stage = 1;
+  if (ctrl->bmRequestType & UE_DIR_IN) {
+    ep0->is_in = 1;
+    pcd->ep0state = EP0_IN_DATA_PHASE;
+  } else {
+    ep0->is_in = 0;
+    pcd->ep0state = EP0_OUT_DATA_PHASE;
+  }
+
+  if (wLength == 0) {
+    ep0->is_in = 1;
+    pcd->ep0state = EP0_IN_WAIT_NRDY;
+    ep0->three_stage = 0;
+  }
+  if (UT_GET_TYPE (ctrl->bmRequestType) != UT_STANDARD) {
+    EndPoint0DoStall (pcd);
+    return;
+  }
+
+  switch (ctrl->bRequest) {
+  case UR_GET_STATUS:
+    DwUsb3DoGetStatus (pcd);
+    break;
+  case UR_CLEAR_FEATURE:
+    DwUsb3DoClearFeature (pcd);
+    break;
+  case UR_SET_FEATURE:
+    DwUsb3DoSetFeature (pcd);
+    break;
+  case UR_SET_ADDRESS:
+    DwUsb3DoSetAddress (pcd);
+    break;
+  case UR_SET_CONFIG:
+    DwUsb3DoSetConfig (pcd);
+    MmioOr32 (DCTL, DCTL_ACCEPT_U1_EN);
+    MmioOr32 (DCTL, DCTL_ACCEPT_U2_EN);
+    DEBUG ((DEBUG_INFO, "enum done"));
+    pcd->ltm_enable = 0;
+    break;
+  case UR_GET_CONFIG:
+    DwUsb3DoGetConfig (pcd);
+    break;
+  case UR_GET_DESCRIPTOR:
+    DwUsb3DoGetDescriptor (pcd);
+    break;
+  case UR_SET_SEL:
+    // for now this is a no-op
+    pcd->ep0_req.bufdma = (UINT64 *)gEndPoint0StatusBuf;
+    pcd->ep0_req.length = USB3_STATUS_BUF_SIZE;
+    pcd->ep0_req.actual = 0;
+    ep0->send_zlp = 0;
+    DwUsb3EndPoint0StartTransfer (pcd, &pcd->ep0_req);
+    break;
+  default:
+    EndPoint0DoStall (pcd);
+    break;
+  }
+}
+
+STATIC
+VOID
+DwUsb3OsHandleEndPoint0 (
+  IN usb3_pcd_t       *pcd,
+  IN UINT32           event
+  )
+{
+  if (pcd->ep0state == EP0_IDLE) {
+    DwUsb3DoSetup (pcd);
+  } else {
+    DwUsb3HandleEndPoint0 (pcd, NULL, event);
+  }
+}
+
+STATIC
+VOID
+DwUsb3RequestDone (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_ep_t    *ep,
+  IN usb3_pcd_req_t   *req,
+  IN UINTN            status
+  )
+{
+  if (ep != &pcd->ep0) {
+    req->trb = NULL;
+  }
+  if (req->complete) {
+    req->complete (req->actual, status);
+  } else {
+    if (!ep->is_in) {
+      ASSERT (req->actual <= req->length);
+      InvalidateDataCacheRange (gRxBuf, req->actual);
+      mDataReceivedCallback (req->actual, gRxBuf);
+    }
+  }
+  req->actual = 0;
+}
+
+STATIC
+VOID
+DwUsb3EndPointcompleteRequest (
+  IN usb3_pcd_t       *pcd,
+  IN usb3_pcd_ep_t    *ep,
+  IN UINT32           event
+  )
+{
+  usb3_pcd_req_t           *req = &ep->req;
+  usb3_dma_desc_t          *desc = req->trb;
+  UINT32 byte_count;
+
+  ep->send_zlp = 0;
+  if (!desc) {
+    return;
+  }
+
+  if (desc->control & DSCCTL_HWO) {
+    return;
+  }
+
+  if (ep->is_in) {
+    // IN ep
+    if (GET_DSCSTS_XFERCNT (desc->status) == 0) {
+      req->actual += req->length;
+    }
+    // reset IN tri
+    ep->tri_in = 0;
+    // complete the IN request
+    // flush for dma?
+    DwUsb3RequestDone (pcd, ep, req, 0);
+  } else {
+    // OUT ep
+    byte_count = req->length - GET_DSCSTS_XFERCNT (desc->status);
+    req->actual += byte_count;
+    //req->bufdma += byte_count;
+    // reset OUT tri
+    ep->tri_out = 0;
+    // OUT transfer complete or not
+    // complete the OUT request
+    // FIXME flush dma?
+    DwUsb3RequestDone (pcd, ep, req, 0);
+    {
+      // prepare for EP1 OUT
+      usb3_pcd_ep_t                 *ep = &pcd->out_ep;
+      usb3_pcd_req_t                *req = &ep->req;
+
+      ZeroMem (req, sizeof (usb3_pcd_req_t));
+      gRxBuf = AllocatePool (DATA_SIZE);
+      ASSERT (gRxBuf != NULL);
+      WriteBackDataCacheRange (gRxBuf, DATA_SIZE);
+      req->bufdma = (UINT64 *)gRxBuf;
+      req->length = DATA_SIZE;
+      DwUsb3EndPointXStartTransfer (pcd, ep);
+    }
+  }
+}
+
+STATIC
+VOID
+DwUsb3HandleEndPointInterrupt (
+  IN usb3_pcd_t       *pcd,
+  IN UINTN            PhySep,
+  IN UINT32           event
+  )
+{
+  usb3_pcd_ep_t       *ep;
+  UINT32              epnum, is_in;
+
+  // Physical Out EPs are even, physical In EPs are odd
+  is_in = (UINT32)PhySep & 1;
+  epnum = ((UINT32)PhySep >> 1) & 0xF;
+
+  // Get the EP pointer
+  if (is_in) {
+    ep = DwUsb3GetInEndPoint (pcd, epnum);
+  } else {
+    ep = DwUsb3GetOutEndPoint (pcd, epnum);
+  }
+
+  switch (event & GEVNT_DEPEVT_INTTYPE_MASK) {
+  case GEVNT_DEPEVT_INTTYPE_XFER_CMPL:
+    ep->xfer_started = 0;
+    // complete the transfer
+    if (epnum == 0) {
+      DwUsb3OsHandleEndPoint0 (pcd, event);
+    } else {
+      DwUsb3EndPointcompleteRequest (pcd, ep, event);
+    }
+    break;
+  case GEVNT_DEPEVT_INTTYPE_XFER_IN_PROG:
+    break;
+  case GEVNT_DEPEVT_INTTYPE_XFER_NRDY:
+    if (epnum == 0) {
+      switch (pcd->ep0state) {
+#if 1
+      case EP0_IN_WAIT_NRDY:
+        if (is_in) {
+          DwUsb3OsHandleEndPoint0 (pcd, event);
+        } else {
+        }
+        break;
+      case EP0_OUT_WAIT_NRDY:
+        if (!is_in) {
+          DwUsb3OsHandleEndPoint0 (pcd, event);
+        } else {
+        }
+        break;
+#else
+      case EP0_IN_WAIT_NRDY:
+      case EP0_OUT_WAIT_NRDY:
+        DwUsb3OsHandleEndPoint0 (pcd, event);
+        break;
+#endif
+      default:
+        break;
+      }
+    } else {
+    }
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR, "invalid event %d\n", event & GEVNT_DEPEVT_INTTYPE_MASK));
+    break;
+  }
+}
+
+STATIC
+UINTN
+DwUsb3HandleEvent (
+  VOID
+  )
+{
+  usb3_pcd_t          *pcd = &gPcd;
+  UINT32              Count, Index, Event, Intr;
+  UINT32              PhySep;
+
+  Count = GET_EVENTBUF_COUNT ();
+  // reset event buffer when it's full
+  if ((GEVNTCOUNT_EVNTCOUNT (Count) == GEVNTCOUNT_EVNTCOUNT_MASK) ||
+      (Count >= DWUSB3_EVENT_BUF_SIZE * sizeof (UINT32))) {
+    UPDATE_EVENTBUF_COUNT (Count);
+    Count = 0;
+  }
+
+  for (Index = 0; Index < Count; Index += sizeof (UINT32)) {
+    Event = DwUsb3GetEventBufEvent (DWUSB3_EVENT_BUF_SIZE << 2);
+    UPDATE_EVENTBUF_COUNT (sizeof (UINT32));
+    if (Event == 0) {
+      // ignore null events
+      continue;
+    }
+    if (Event & GEVNT_NON_EP) {
+      Intr = Event & GEVNT_INTTYPE_MASK;
+      if (Intr == GEVNT_INTTYPE (EVENT_DEV_INT)) {
+        DwUsb3HandleDeviceInterrupt (pcd, Event);
+      }
+    } else {
+      PhySep = (Event & GEVNT_DEPEVT_EPNUM_MASK) >> GEVNT_DEPEVT_EPNUM_SHIFT;
+      DwUsb3HandleEndPointInterrupt (pcd, PhySep, Event);
+    }
+  }
+  return 0;
+}
+
+STATIC
+VOID
+DwUsb3Poll (
+  IN EFI_EVENT        Event,
+  IN VOID            *Context
+  )
+{
+  if (DwUsb3HandleEvent ()) {
+    DEBUG ((DEBUG_ERROR, "error: exit from usb_poll\n"));
+    return;
+  }
+}
+
+EFI_STATUS
+EFIAPI
+DwUsb3Start (
+  IN USB_DEVICE_DESCRIPTOR   *DeviceDescriptor,
+  IN VOID                   **Descriptors,
+  IN USB_DEVICE_RX_CALLBACK   RxCallback,
+  IN USB_DEVICE_TX_CALLBACK   TxCallback
+  )
+{
+  EFI_STATUS             Status;
+  EFI_EVENT              TimerEvent;
+
+  //gEventBuf = UncachedAllocateAlignedZeroPool (DWUSB3_EVENT_BUF_SIZE << 2, 256);
+  gEventBuf = UncachedAllocatePages (EFI_SIZE_TO_PAGES (DWUSB3_EVENT_BUF_SIZE << 2));
+  if (gEventBuf == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  ZeroMem (gEventBuf, EFI_SIZE_TO_PAGES (DWUSB3_EVENT_BUF_SIZE << 2));
+  gEventPtr = gEventBuf;
+  DriverInit ();
+  DwUsb3Init ();
+  Status = gBS->CreateEvent (
+                  EVT_TIMER | EVT_NOTIFY_SIGNAL,
+                  TPL_CALLBACK,
+                  DwUsb3Poll,
+                  NULL,
+                  &TimerEvent
+                  );
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = gBS->SetTimer (
+                  TimerEvent,
+                  TimerPeriodic,
+                  DW_INTERRUPT_POLL_PERIOD
+                  );
+  ASSERT_EFI_ERROR (Status);
+  mDataReceivedCallback = RxCallback;
+  return Status;
+}
+
+EFI_STATUS
+DwUsb3Send (
+  IN        UINT8  EndpointIndex,
+  IN        UINTN  Size,
+  IN  CONST VOID  *Buffer
+  )
+{
+  usb3_pcd_t                    *pcd = &gPcd;
+  usb3_pcd_ep_t                 *ep = &pcd->in_ep;
+  usb3_pcd_req_t                *req = &ep->req;
+
+  WriteBackDataCacheRange ((VOID *)Buffer, Size);
+  req->bufdma = (UINT64 *)Buffer;
+  req->length = Size;
+  DwUsb3EndPointXStartTransfer (pcd, ep);
+  return EFI_SUCCESS;
+}
+
+USB_DEVICE_PROTOCOL mUsbDevice = {
+  DwUsb3Start,
+  DwUsb3Send
+};
+
+EFI_STATUS
+EFIAPI
+DwUsb3EntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS      Status;
+
+  gEndPoint0SetupPacket = UncachedAllocatePages (EFI_SIZE_TO_PAGES (sizeof (usb_setup_pkt_t) * 5));
+  if (gEndPoint0SetupPacket == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  gEndPoint0StatusBuf = UncachedAllocatePages (EFI_SIZE_TO_PAGES (USB3_STATUS_BUF_SIZE * sizeof (UINT8)));
+  if (gEndPoint0StatusBuf == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+#if 0
+  gRxBuf = UncachedAllocatePages (1);
+  if (gRxBuf == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+#endif
+  Status = gBS->LocateProtocol (&gDwUsbProtocolGuid, NULL, (VOID **) &DwUsb);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = DwUsb->PhyInit(USB_DEVICE_MODE);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return gBS->InstallProtocolInterface (
+		  &ImageHandle,
+		  &gUsbDeviceProtocolGuid,
+		  EFI_NATIVE_INTERFACE,
+		  &mUsbDevice
+		  );
+}
diff --git a/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.dec b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.dec
index 7ebd6db..a55915d 100644
--- a/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.dec
+++ b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.dec
@@ -4,7 +4,7 @@
 # This Package provides headers and libraries that conform to EFI/PI Industry standards.
 # Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
 # Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
-# Copyright (c) 2015-2016, Linaro. All rights reserved.<BR>
+# Copyright (c) 2015-2017, Linaro. All rights reserved.<BR>
 #
 #    This program and the accompanying materials are licensed and made available under
 #    the terms and conditions of the BSD License which accompanies this distribution.
@@ -17,9 +17,9 @@
 #**/
 
 [Defines]
-  DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = OpenPlatformDriversVariableBlockVariableDxePkg
-  PACKAGE_GUID                   = 591a584f-3c3c-4e06-b1f8-2ad61f10f6c7
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = OpenPlatformDriversUsbDwUsb3DxePkg
+  PACKAGE_GUID                   = 9b7aa6fe-405b-4955-af1f-5faf183aedec
   PACKAGE_VERSION                = 0.1
 
 
@@ -34,12 +34,12 @@
 ################################################################################
 
 [Guids.common]
-  gBlockVariableDxeTokenSpaceGuid	= { 0x0c5d52e4, 0xadca, 0x48a8,  { 0xb9, 0xf5, 0x53, 0x15, 0x96, 0x81, 0xff, 0x25 }}
-  gVariableRuntimeGuid                  = { 0xcbd2e4d5, 0x7068, 0x4ff5,  { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 }}
+  gAndroidFastbootUsbGuid       = { 0xf6bec3fe, 0x88fb, 0x11e3, { 0xae, 0x84, 0xe7, 0x3b, 0x77, 0x56, 0x1c, 0x35 }}
+  gDwUsb3DxeTokenSpaceGuid      = { 0x098a50d3, 0x92e2, 0x461a, { 0xb6, 0xba, 0xf8, 0x5d, 0x9d, 0x89, 0x49, 0xf5 }}
+
+[Protocols.common]
+  gDwUsbProtocolGuid            = { 0x109fa264, 0x7811, 0x4862, { 0xa9, 0x73, 0x4a, 0xb2, 0xef, 0x2e, 0xe2, 0xff }}
 
 [PcdsFixedAtBuild.common]
-  # BlockVariable Driver PCDs
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockCount|0x0|UINT32|0x00000001
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockSize|0x0|UINT32|0x00000002
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockLba|0|UINT32|0x00000003
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockDevicePath|L""|VOID*|0x00000004
+  # DwUsb Driver PCDs
+  gDwUsb3DxeTokenSpaceGuid.PcdDwUsb3DxeBaseAddress|0x0|UINT32|0x00000001
diff --git a/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.h b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.h
new file mode 100644
index 0000000..2f3dfed
--- /dev/null
+++ b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.h
@@ -0,0 +1,632 @@
+/** @file
+
+  Copyright (c) 2017, Linaro Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __DW_USB3_DXE_H__
+#define __DW_USB3_DXE_H__
+
+#define DW_USB3_BASE                     FixedPcdGet32 (PcdDwUsb3DxeBaseAddress)
+
+#define GSBUCFG0                         (DW_USB3_BASE + 0xC100)
+#define GCTL                             (DW_USB3_BASE + 0xC110)
+
+#define GCTL_PWRDNSCALE_MASK             (0x1FFF << 19)
+#define GCTL_PWRDNSCALE(x)               (((x) & 0x1FFF) << 19)
+#define GCTL_U2RSTECN                    BIT16
+#define GCTL_PRTCAPDIR_MASK              (BIT13 | BIT12)
+#define GCTL_PRTCAPDIR_HOST              BIT12
+#define GCTL_PRTCAPDIR_DEVICE            BIT13
+#define GCTL_PRTCAPDIR_OTG               (BIT13 | BIT12)
+#define GCTL_U2EXIT_LFPS                 BIT2
+
+#define GUSB2PHYCFG(x)                   (DW_USB3_BASE + 0xC200 + (((x) & 0xF) << 2))
+
+#define GUSB2PHYCFG_USBTRDTIM_MASK       (0xF << 10)
+#define GUSB2PHYCFG_USBTRDTIM(x)         (((x) & 0xF) << 10)
+#define GUSB2PHYCFG_SUSPHY               BIT6
+
+#define GUSB3PIPECTL(x)                  (DW_USB3_BASE + 0xC2C0 + (((x) & 0x3) << 2))
+
+#define PIPECTL_DELAYP1TRANS             BIT18
+#define PIPECTL_SUSPEND_EN               BIT17
+#define PIPECTL_LFPS_FILTER              BIT9
+#define PIPECTL_TX_DEMPH_MASK            (0x3 << 1)
+#define PIPECTL_TX_DEMPH(x)              (((x) & 0x3) << 1)
+
+#define GTXFIFOSIZ(x)                    (DW_USB3_BASE + 0xC300 + (((x) & 0x1F) << 2))
+#define GRXFIFOSIZ(x)                    (DW_USB3_BASE + 0xC380 + (((x) & 0x1F) << 2))
+
+#define FIFOSIZ_ADDR(x)                  (((x) & 0xFFFF) << 16)
+#define FIFOSIZ_DEP(x)                   ((x) & 0xFFFF)
+
+#define GEVNTADRL(x)                     (DW_USB3_BASE + 0xC400 + (((x) & 0x1F) << 2))
+#define GEVNTADRH(x)                     (DW_USB3_BASE + 0xC404 + (((x) & 0x1F) << 2))
+#define GEVNTSIZ(x)                      (DW_USB3_BASE + 0xC408 + (((x) & 0x1F) << 2))
+
+#define GEVNTSIZ_EVNTINTMASK             BIT31
+#define GEVNTSIZ_EVNTSIZ_MASK            (0xFFFF)
+#define GEVNTSIZ_EVNTSIZ(x)              ((x) & 0xFFFF)
+
+#define GEVNTCOUNT(x)                    (DW_USB3_BASE + 0xC40C + (((x) & 0x1F) << 2))
+#define GEVNTCOUNT_EVNTCOUNT_MASK        (0xFFFF)
+#define GEVNTCOUNT_EVNTCOUNT(x)          ((x) & 0xFFFF)
+
+// Non-Endpoint specific event flag
+#define GEVNT_INTTYPE_MASK               (0x7F << 1)
+#define GEVNT_INTTYPE(x)                 (((x) & 0x7F) << 1)
+#define EVENT_I2C_INT                    4
+#define EVENT_CARKIT_INT                 3
+#define EVENT_OTG_INT                    1
+#define EVENT_DEV_INT                    0
+
+#define GEVNT_NON_EP                     BIT0
+// Endpoint specific event flag
+#define GEVNT_DEPEVT_INTTYPE_MASK        (0xF << 6)
+#define GEVNT_DEPEVT_INTTYPE(x)          (((x) & 0xF) << 6)
+#define GEVNT_DEPEVT_INTTYPE_EPCMD_CMPL          (7 << 6)
+#define GEVNT_DEPEVT_INTTYPE_STRM_EVT            (6 << 6)
+#define GEVNT_DEPEVT_INTTYPE_FIFOXRUN            (4 << 6)
+#define GEVNT_DEPEVT_INTTYPE_XFER_NRDY           (3 << 6)
+#define GEVNT_DEPEVT_INTTYPE_XFER_IN_PROG        (2 << 6)
+#define GEVNT_DEPEVT_INTTYPE_XFER_CMPL           (1 << 6)
+#define GEVNT_DEPEVT_EPNUM_MASK          (0x1F << 1)
+#define GEVNT_DEPEVT_EPNUM_SHIFT         1
+#define GEVNT_DEPEVT_EPNUM(x)            (((x) & 0x1F) << 1)
+// Devices specific event flag
+#define GEVNT_DEVT_MASK                  (0xF << 8)
+#define GEVNT_DEVT_SHIFT                 8
+#define GEVNT_DEVT(x)                    (((x) & 0xF) << 8)
+#define GEVNT_DEVT_INACT_TIMEOUT_RCVD    (0x15 << 8)
+#define GEVNT_DEVT_VNDR_DEV_TST_RCVD     (0x14 << 8)
+#define GEVNT_DEVT_OVERFLOW              (0x13 << 8)
+#define GEVNT_DEVT_CMD_CMPL              (0x12 << 8)
+#define GEVNT_DEVT_ERRATICERR            (0x11 << 8)
+#define GEVNT_DEVT_SOF                   (0x7 << 8)
+#define GEVNT_DEVT_EOPF                  (0x6 << 8)
+#define GEVNT_DEVT_HIBER_REQ             (0x5 << 8)
+#define GEVNT_DEVT_WKUP                  (0x4 << 8)
+#define GEVNT_DEVT_ULST_CHNG             (0x3 << 8)
+#define GEVNT_DEVT_CONNDONE              (0x2 << 8)
+#define GEVNT_DEVT_USBRESET              (0x1 << 8)
+#define GEVNT_DEVT_DISCONN               (0x0 << 8)
+
+#define DCFG                             (DW_USB3_BASE + 0xC700)
+
+#define DCFG_NUMP_MASK                   (0x1F << 17)
+#define DCFG_NUMP(x)                     (((x) & 0x1F) << 17)
+#define DCFG_DEVADDR_MASK                (0x7F << 3)
+#define DCFG_DEVADDR(x)                  (((x) & 0x7F) << 3)
+#define DCFG_DEVSPD_MASK                 (0x7)
+#define DCFG_DEVSPD(x)                   ((x) & 0x7)
+#define DEVSPD_HS_PHY_30MHZ_OR_60MHZ     0
+#define DEVSPD_FS_PHY_30MHZ_OR_60MHZ     1
+#define DEVSPD_LS_PHY_6MHZ               2
+#define DEVSPD_FS_PHY_48MHZ              3
+#define DEVSPD_SS_PHY_125MHZ_OR_250MHZ   4
+
+#define DCTL                             (DW_USB3_BASE + 0xC704)
+
+#define DCTL_RUN_STOP                    BIT31
+#define DCTL_CSFTRST                     BIT30
+#define DCTL_INIT_U2_EN                  BIT12
+#define DCTL_ACCEPT_U2_EN                BIT11
+#define DCTL_INIT_U1_EN                  BIT10
+#define DCTL_ACCEPT_U1_EN                BIT9
+
+#define DEVTEN                           (DW_USB3_BASE + 0xC708)
+#define DEVTEN_CONNECTDONEEN             BIT2
+#define DEVTEN_USBRSTEN                  BIT1
+#define DEVTEN_DISCONNEN                 BIT0
+
+#define DSTS                             (DW_USB3_BASE + 0xC70C)
+#define DSTS_GET_DEVSPD(x)               ((x) & 0x7)
+
+#define DALEPENA                         (DW_USB3_BASE + 0xC720)
+
+#define DEPCMDPAR2(x)                    (DW_USB3_BASE + 0xC800 + ((x) & 0x1F) * 0x10)
+#define DEPCMDPAR1(x)                    (DW_USB3_BASE + 0xC804 + ((x) & 0x1F) * 0x10)
+#define DEPCMDPAR0(x)                    (DW_USB3_BASE + 0xC808 + ((x) & 0x1F) * 0x10)
+#define DEPCMD(x)                        (DW_USB3_BASE + 0xc80C + ((x) & 0x1F) * 0x10)
+
+#define DEPCMD_COMMANDPARAM_MASK         (0xFFFF << 16)
+#define DEPCMD_COMMANDPARAM(x)           (((x) & 0xFFFF) << 16)
+/* Stream Number or uFrame (input) */
+#define DEPCMD_STR_NUM_OR_UF_MASK        (0xFFFF << 16)
+#define DEPCMD_STR_NUM_OR_UF(x)          (((x) & 0xFFFF) << 16)
+/* Transfer Resource Index (output) */
+#define DEPCMD_XFER_RSRC_IDX_SHIFT       16
+#define DEPCMD_XFER_RSRC_IDX_MASK        (0x7F << 16)
+#define DEPCMD_XFER_RSRC_IDX(x)          (((x) & 0x7F) << 16)
+#define GET_DEPCMD_XFER_RSRC_IDX(x)      (((x) >> 16) & 0x7F)
+#define DEPCMD_CMDACT                    BIT10
+#define DEPCMD_CMDTYPE_MASK              0xFF
+#define DEPCMD_CMDTYPE(x)                ((x) & 0xFF)
+
+/* EP registers range as: OUT0, IN0, OUT1, IN1, ... */
+#define EP_OUT_IDX(x)                    ((x) * 2)
+#define EP_IN_IDX(x)                     (((x) * 2) + 1)
+
+#define CMDTYPE_SET_EP_CFG               1
+#define CMDTYPE_SET_XFER_CFG             2
+#define CMDTYPE_GET_EP_STATE             3
+#define CMDTYPE_SET_STALL                4
+#define CMDTYPE_CLR_STALL                5
+#define CMDTYPE_START_XFER               6
+#define CMDTYPE_UPDATE_XFER              7
+#define CMDTYPE_END_XFER                 8
+#define CMDTYPE_START_NEW_CFG            9
+
+#define EPTYPE_CONTROL                   0
+#define EPTYPE_ISOC                      1
+#define EPTYPE_BULK                      2
+#define EPTYPE_INTR                      3
+
+#define CFG_ACTION_INIT                  0
+#define CFG_ACTION_RESTORE               1
+#define CFG_ACTION_MODIFY                2
+
+#define EPCFG0_CFG_ACTION_MASK           (0x3 << 30)
+#define EPCFG0_CFG_ACTION(x)             (((x) & 0x3) << 30)
+#define EPCFG0_BRSTSIZ_MASK              (0xF << 22)
+#define EPCFG0_BRSTSIZ(x)                (((x) & 0xF) << 22)
+#define EPCFG0_TXFNUM_MASK               (0x1F << 17)
+#define EPCFG0_TXFNUM(x)                 (((x) & 0x1F) << 17)
+#define EPCFG0_MPS_MASK                  (0x7FF << 3)
+#define EPCFG0_MPS(x)                    (((x) & 0x7FF) << 3)
+#define EPCFG0_EPTYPE_MASK               (0x3 << 1)
+#define EPCFG0_EPTYPE_SHIFT              1
+#define EPCFG0_EPTYPE(x)                 (((x) & 0x3) << 1)
+
+/* Endpoint Number */
+#define EPCFG1_EP_NUM_MASK               (0xF << 26)
+#define EPCFG1_EP_NUM(x)                 (((x) & 0xF) << 26)
+/* Endpoint Direction */
+#define EPCFG1_EP_DIR_IN                 BIT25
+/* Stream Not Ready */
+#define EPCFG1_XFER_NRDY                 BIT10
+/* XferInProgress Enable */
+#define EPCFG1_XFER_IN_PROG              BIT9
+/* Stream Completed */
+#define EPCFG1_XFER_CMPL                 BIT8
+
+#define USB_SPEED_UNKNOWN                0
+#define USB_SPEED_LOW                    1
+#define USB_SPEED_FULL                   2
+#define USB_SPEED_HIGH                   3
+#define USB_SPEED_VARIABLE               4
+#define USB_SPEED_SUPER                  5
+
+// DMA registers
+#define DSCSTS_TRBRSP_MASK               (0xF << 28)
+#define DSCSTS_TRBRSP(x)                 (((x) & 0xF) << 28)
+#define GET_DSCSTS_TRBRSP(x)             (((x) >> 28) & 0xF)
+#define TRBRSP_MISSED_ISOC_IN            1
+#define TRBRSP_SETUP_PEND                2
+#define TRBRSP_XFER_IN_PROG              4
+#define DSCSTS_PCM1_MASK                 (0x3 << 24)
+#define DSCSTS_PCM1(x)                   (((x) & 0x3) << 24)
+#define DSCSTS_XFERCNT_MASK              0xFFFFFF
+#define DSCSTS_XFERCNT(x)                ((x) & 0xFFFFFF)
+#define GET_DSCSTS_XFERCNT(x)            ((x) & 0xFFFFFF)
+
+#define DSCCTL_STRMID_SOFN(x)            (((x) & 0xFFFF) << 14)
+#define DSCCTL_IOC                       BIT11
+#define DSCCTL_ISP                       BIT10
+#define DSCCTL_TRBCTL_MASK               (0x3F << 4)
+#define DSCCTL_TRBCTL(x)                 (((x) & 0x3F) << 4)
+#define DSCCTL_LST                       BIT1
+#define DSCCTL_HWO                       BIT0
+#define TRBCTL_NORMAL                    1
+#define TRBCTL_SETUP                     2
+#define TRBCTL_STATUS_2                  3
+#define TRBCTL_STATUS_3                  4
+#define TRBCTL_CTLDATA_1ST               5
+#define TRBCTL_ISOC_1ST                  6
+#define TRBCTL_ISOC                      7
+#define TRBCTL_LINK                      8
+#define TRBCTL_NORMAL_ZLP                9
+
+
+#define UE_DIR_IN                        0x80
+#define UE_DIR_OUT                       0
+#define UE_SET_DIR(a, d)                 ((a) | (((d) & 1) << 7))
+#define UE_GET_DIR(a)                    ((a) & 0x80)
+#define UE_ADDR                          0x0F
+#define UE_GET_ADDR(a)                   ((a) & UE_ADDR)
+
+#define UT_GET_DIR(a) ((a) & 0x80)
+#define UT_WRITE		0x00
+#define UT_READ			0x80
+
+#define UT_GET_TYPE(a)                   ((a) & 0x60)
+#define UT_STANDARD                      0x00
+#define UT_CLASS                         0x20
+#define UT_VENDOR                        0x40
+
+#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
+#define UT_DEVICE		0x00
+#define UT_INTERFACE    0x01
+#define UT_ENDPOINT		0x02
+#define UT_OTHER		0x03
+
+#define UR_GET_STATUS                    0x00
+#define UR_CLEAR_FEATURE                 0x01
+#define UR_SET_FEATURE                   0x03
+#define UR_SET_ADDRESS                   0x05
+#define UR_GET_DESCRIPTOR                0x06
+#define UR_SET_DESCRIPTOR                0x07
+#define UR_GET_CONFIG                    0x08
+#define UR_SET_CONFIG                    0x09
+#define UR_GET_INTERFACE                 0x0A
+#define UR_SET_INTERFACE                 0x0B
+#define UR_SYNCH_FRAME                   0x0C
+#define UR_SET_SEL                       0x30
+#define UR_SET_ISOC_DELAY                0x31
+
+/* Feature numbers */
+#define UF_ENDPOINT_HALT	        0
+#define UF_DEVICE_REMOTE_WAKEUP	    1
+#define UF_TEST_MODE		        2
+#define UF_DEVICE_B_HNP_ENABLE	    3
+#define UF_DEVICE_A_HNP_SUPPORT	    4
+#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
+#define UF_FUNCTION_SUSPEND	0
+#define UF_U1_ENABLE		48
+#define UF_U2_ENABLE		49
+#define UF_LTM_ENABLE		50
+
+#define  UDESC_DEVICE		    0x01
+#define  UDESC_CONFIG		    0x02
+#define  UDESC_STRING		    0x03
+#define  UDESC_INTERFACE	    0x04
+#define  UDESC_ENDPOINT		    0x05
+#define  UDESC_SS_USB_COMPANION	0x30
+#define  UDESC_DEVICE_QUALIFIER	0x06
+#define  UDESC_BOS		        0x0f
+#define  UDESC_DEVICE_CAPABILITY 0x10
+
+#define STRING_LANGUAGE         0
+#define STRING_MANUFACTURER     1
+#define STRING_PRODUCT          2
+#define STRING_SERIAL           3
+
+#define CONFIG_VALUE    1
+
+#define USB3_BULK_IN_EP                  1
+#define USB3_BULK_OUT_EP                 1
+
+#define USB_ENUM_ADB_PORT_VID             0x18D1
+#define USB_ENUM_ADB_PORT_PID             0xD00D
+#define USB_ENUM_INTERFACE_ADB_SUBCLASS   0x42
+#define USB_ENUM_INTERFACE_ADB_PROTOCOL   0x03
+
+struct usb3_pcd;
+
+typedef enum pcd_state {
+	USB3_STATE_UNCONNECTED,	/* no host */
+	USB3_STATE_DEFAULT,
+	USB3_STATE_ADDRESSED,
+	USB3_STATE_CONFIGURED,
+} pcdstate_e;
+
+typedef enum ep0_state {
+	EP0_IDLE,
+	EP0_IN_DATA_PHASE,
+	EP0_OUT_DATA_PHASE,
+	EP0_IN_WAIT_NRDY,
+	EP0_OUT_WAIT_NRDY,
+	EP0_IN_STATUS_PHASE,
+	EP0_OUT_STATUS_PHASE,
+	EP0_STALL,
+} ep0state_e;
+
+typedef struct usb3_dma_desc {
+	/** Buffer Pointer - Low address quadlet */
+	UINT32	bptl;
+
+	/** Buffer Pointer - High address quadlet */
+	UINT32	bpth;
+
+	/** Status quadlet. Fields defined in enum @ref desc_sts_data. */
+	UINT32	status;
+
+	/** Control quadlet. Fields defined in enum @ref desc_ctl_data. */
+	UINT32	control;
+} usb3_dma_desc_t;
+
+typedef struct usb3_pcd_req {
+	usb3_dma_desc_t *trb;
+	UINT64 trbdma;
+
+	UINT32 length;
+	UINT32 actual;
+
+	UINT64 *bufdma;
+	int (*complete)(unsigned actual, int status);
+} usb3_pcd_req_t;
+
+typedef struct usb_device_request {
+	UINT8 bmRequestType;
+	UINT8 bRequest;
+	UINT16 wValue;
+	UINT16 wIndex;
+	UINT16 wLength;
+} usb_device_request_t;
+
+#pragma pack(1)
+/** USB_DT_DEVICE: Device descriptor */
+typedef struct usb_device_descriptor {
+	UINT8  bLength;
+	UINT8  bDescriptorType;
+
+	UINT16 bcdUSB;
+#define USB_CLASS_COMM          0x02
+#define USB_CLASS_VENDOR_SPEC   0xFF
+#define USB_SC_VENDOR_SPEC      0xFF
+#define USB_PR_VENDOR_SPEC      0xFF
+	UINT8  bDeviceClass;
+	UINT8  bDeviceSubClass;
+	UINT8  bDeviceProtocol;
+	UINT8  bMaxPacketSize0;
+	UINT16 idVendor;
+	UINT16 idProduct;
+	UINT16 bcdDevice;
+	UINT8  iManufacturer;
+	UINT8  iProduct;
+	UINT8  iSerialNumber;
+	UINT8  bNumConfigurations;
+} usb_device_descriptor_t;
+
+/* USB_DT_CONFIG: Config descriptor */
+typedef struct usb_config_descriptor {
+	UINT8  bLength;
+	UINT8  bDescriptorType;
+
+	UINT16 wTotalLength;
+	UINT8  bNumInterfaces;
+#define CONFIG_VALUE    1
+	UINT8  bConfigurationValue;
+	UINT8  iConfiguration;
+#define USB_CONFIG_ATT_ONE      (1 << 7)
+	UINT8  bmAttributes;
+#define USB_CONFIG_VBUS_DRAW    (0xFA)
+	UINT8  bMaxPower;
+} usb_config_descriptor_t;
+
+/* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */
+typedef struct usb_qualifier_descriptor {
+	UINT8  bLength;
+	UINT8  bDescriptorType;
+
+	UINT16 bcdUSB;
+	UINT8  bDeviceClass;
+	UINT8  bDeviceSubClass;
+	UINT8  bDeviceProtocol;
+	UINT8  bMaxPacketSize0;
+	UINT8  bNumConfigurations;
+	UINT8  bRESERVED;
+} usb_qualifier_descriptor_t;
+
+/* USB_DT_INTERFACE: Interface descriptor */
+typedef struct usb_interface_descriptor {
+	UINT8  bLength;
+	UINT8  bDescriptorType;
+
+	UINT8  bInterfaceNumber;
+	UINT8  bAlternateSetting;
+	UINT8  bNumEndpoints;
+	UINT8  bInterfaceClass;
+	UINT8  bInterfaceSubClass;
+	UINT8  bInterfaceProtocol;
+	UINT8  iInterface;
+} usb_interface_descriptor_t;
+
+/* USB_DT_ENDPOINT: Endpoint descriptor */
+typedef struct usb_endpoint_descriptor {
+	UINT8  bLength;
+	UINT8  bDescriptorType;
+
+	UINT8  bEndpointAddress;
+	UINT8  bmAttributes;
+#define USB_ENDPOINT_XFER_CONTROL	0x00
+#define USB_ENDPOINT_XFER_ISOC		0x01
+#define USB_ENDPOINT_XFER_BULK		0x02
+#define USB_ENDPOINT_XFER_INT		0x03
+	UINT16 wMaxPacketSize;
+	UINT8  bInterval;
+} usb_endpoint_descriptor_t;
+
+/* USB_DT_SS_ENDPOINT_COMP: SuperSpeed Endpoint Companion descriptor */
+typedef struct usb_ss_ep_comp_descriptor {
+	UINT8  bLength;
+	UINT8  bDescriptorType;
+
+	UINT8  bMaxBurst;
+	UINT8  bmAttributes;
+	UINT16 wBytesPerInterval;
+} usb_ss_ep_comp_descriptor_t;
+
+/* WUSB BOS Descriptor (Binary device Object Store) */
+typedef struct wusb_bos_desc {
+	UINT8 bLength;
+	UINT8 bDescriptorType;
+	UINT16 wTotalLength;
+	UINT8 bNumDeviceCaps;
+} wusb_bos_desc_t;
+
+#define USB_DEVICE_CAPABILITY_20_EXTENSION	0x02
+typedef struct usb_dev_cap_20_ext_desc {
+	UINT8 bLength;
+	UINT8 bDescriptorType;
+	UINT8 bDevCapabilityType;
+#define USB_20_EXT_LPM				0x02
+	UINT32 bmAttributes;
+} usb_dev_cap_20_ext_desc_t;
+
+#define USB_DEVICE_CAPABILITY_SS_USB		0x03
+typedef struct usb_dev_cap_ss_usb {
+	UINT8 bLength;
+	UINT8 bDescriptorType;
+	UINT8 bDevCapabilityType;
+#define USB_DC_SS_USB_LTM_CAPABLE		0x02
+	UINT8 bmAttributes;
+#define USB_DC_SS_USB_SPEED_SUPPORT_LOW		0x01
+#define USB_DC_SS_USB_SPEED_SUPPORT_FULL	0x02
+#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH	0x04
+#define USB_DC_SS_USB_SPEED_SUPPORT_SS		0x08
+	UINT32 wSpeedsSupported;
+	UINT8 bFunctionalitySupport;
+	UINT8 bU1DevExitLat;
+	UINT32 wU2DevExitLat;
+} usb_dev_cap_ss_usb_t;
+
+#define USB_DEVICE_CAPABILITY_CONTAINER_ID	0x04
+typedef struct usb_dev_cap_container_id {
+	UINT8 bLength;
+	UINT8 bDescriptorType;
+	UINT8 bDevCapabilityType;
+	UINT8 bReserved;
+	UINT8 containerID[16];
+} usb_dev_cap_container_id_t;
+#pragma pack()
+
+typedef union usb_setup_pkt {
+	usb_device_request_t req;
+	UINT32 d32[2];
+	UINT8 d8[8];
+} usb_setup_pkt_t;
+
+typedef struct usb3_pcd_ep {
+	struct usb3_pcd *pcd;
+
+  UINT8          EpInIdx;
+  UINT8          EpOutIdx;
+  UINT8          phys;
+
+	//UINT8 phys;
+	UINT8 num;
+	UINT8 type;
+	UINT8 maxburst;
+	UINT16 maxpacket;
+	/* Tx FIFO # for IN EPs */
+	UINT8 tx_fifo_num;
+
+	/* The Transfer Resource Index from the Start Transfer command */
+	UINT8 tri_out;
+	UINT8 tri_in;
+
+	UINT8 stopped;
+	/* Send ZLP */
+	UINT8 send_zlp;
+	/* True if 3-stage control transfer */
+	UINT8 three_stage;
+	/* True if transfer has been started on EP */
+	UINT8 xfer_started;
+	/* EP direction 0 = OUT */
+	UINT8 is_in;
+	/* True if endpoint is active */
+	UINT8 active;
+	/* Initial data pid of bulk endpoint */
+	UINT8 data_pid_start;
+
+	/* ep_desc (excluding ep0) */
+	usb3_dma_desc_t *ep_desc;
+
+#if 0
+	/* TRB descriptor must be aligned to 16 bytes */
+	UINT8 epx_desc[32];
+#endif
+
+	/* request (excluding ep0) */
+	usb3_pcd_req_t req;
+} usb3_pcd_ep_t;
+
+typedef struct usb3_pcd {
+	//struct usb3_device *usb3_dev;
+
+	INT32 link_state;
+	pcdstate_e state;
+	UINT8 new_config;
+	ep0state_e ep0state;
+
+	UINT32 eps_enabled;
+	UINT32 ltm_enable;
+
+	usb3_pcd_ep_t ep0;
+	usb3_pcd_ep_t out_ep;
+	usb3_pcd_ep_t in_ep;
+
+	/*
+	usb3_dev_global_regs_t *dev_global_regs;
+	usb3_dev_ep_regs_t *out_ep_regs;
+	usb3_dev_ep_regs_t *in_ep_regs;
+	*/
+
+	usb3_pcd_req_t ep0_req;
+
+	UINT8 speed;
+
+	usb3_dma_desc_t *ep0_setup_desc;
+	usb3_dma_desc_t *ep0_in_desc;
+	usb3_dma_desc_t *ep0_out_desc;
+
+	/* TRB descriptor must be aligned to 16 bytes */
+#if 0
+	UINT8 ep0_setup[32];
+	UINT8 ep0_in[32];
+	UINT8 ep0_out[32];
+
+	usb_setup_pkt_t ep0_setup_pkt[5];
+
+#define USB3_STATUS_BUF_SIZE    512
+	UINT8 ep0_status_buf[USB3_STATUS_BUF_SIZE];
+
+#define USB3_BULK_BUF_SIZE      2048
+	UINT8 ss_bulk_buf[USB3_BULK_BUF_SIZE];
+#endif
+
+	UINT32 file_type;
+	UINT32 file_address;
+	UINT32 file_capacity;
+	UINT32 file_total_frame;
+	UINT32 file_curr_frame;
+	UINT32 file_next_frame;
+	UINT32 file_received;
+	UINT32 file_complete;
+
+	UINT16 test_mode_nr;
+	UINT16 test_mode;
+} usb3_pcd_t;
+
+struct usb_enum_port_param {
+  UINT16     idVendor;
+  UINT16     idProduct;
+  UINT8      bInterfaceSubClass;
+  UINT8      bInterfaceProtocol;
+};
+
+#if 0
+typedef struct usb3_pcd_req {
+	usb3_dma_desc_t *trb;
+	UINT64 trbdma;
+
+	UINT32 length;
+	UINT32 actual;
+
+	UINT64 *bufdma;
+	int (*complete)(unsigned actual, int status);
+} usb3_pcd_req_t;
+
+#endif
+
+#endif /* __DW_USB3_DXE_H__ */
diff --git a/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.inf b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.inf
new file mode 100644
index 0000000..85c75fa
--- /dev/null
+++ b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+#  Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = DwUsb3Dxe
+  FILE_GUID                      = 0879cd34-c399-4315-9891-56024072e711
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = DwUsb3EntryPoint
+
+[Sources.common]
+  DwUsb3Dxe.c
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  MemoryAllocationLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UncachedMemoryAllocationLib
+  CacheMaintenanceLib
+
+[Protocols]
+  gEfiDriverBindingProtocolGuid
+  gUsbDeviceProtocolGuid
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.dec
+
+[Pcd]
+  gDwUsb3DxeTokenSpaceGuid.PcdDwUsb3DxeBaseAddress
+
+[Depex]
+  BEFORE gAndroidFastbootUsbGuid
diff --git a/Drivers/Usb/DwUsbDxe/DwUsbDxe.c b/Drivers/Usb/DwUsbDxe/DwUsbDxe.c
index f4d927b..ee67624 100644
--- a/Drivers/Usb/DwUsbDxe/DwUsbDxe.c
+++ b/Drivers/Usb/DwUsbDxe/DwUsbDxe.c
@@ -1,793 +1,796 @@
-/** @file
-
-  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <IndustryStandard/Usb.h>
-#include <Library/TimerLib.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiDriverEntryPoint.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UncachedMemoryAllocationLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/BaseLib.h>
-#include <Protocol/DwUsb.h>
-#include <Protocol/UsbDevice.h>
-
-#include "DwUsbDxe.h"
-
-EFI_GUID  gDwUsbProtocolGuid = DW_USB_PROTOCOL_GUID;
-
-STATIC dwc_otg_dev_dma_desc_t *g_dma_desc,*g_dma_desc_ep0,*g_dma_desc_in;
-STATIC USB_DEVICE_REQUEST *p_ctrlreq;
-STATIC VOID *rx_buf;
-STATIC UINTN rx_desc_bytes = 0;
-STATIC UINTN mNumDataBytes;
-
-STATIC DW_USB_PROTOCOL          *DwUsb;
-
-#define USB_TYPE_LENGTH              16
-#define USB_BLOCK_HIGH_SPEED_SIZE    512
-#define DATA_SIZE 32768
-#define CMD_SIZE 512
-#define MATCH_CMD_LITERAL(Cmd, Buf) !AsciiStrnCmp (Cmd, Buf, sizeof (Cmd) - 1)
-
-STATIC USB_DEVICE_DESCRIPTOR    *mDeviceDescriptor;
-
-// The config descriptor, interface descriptor, and endpoint descriptors in a
-// buffer (in that order)
-STATIC VOID                     *mDescriptors;
-// Convenience pointers to those descriptors inside the buffer:
-STATIC USB_INTERFACE_DESCRIPTOR *mInterfaceDescriptor;
-STATIC USB_CONFIG_DESCRIPTOR    *mConfigDescriptor;
-STATIC USB_ENDPOINT_DESCRIPTOR  *mEndpointDescriptors;
-
-STATIC USB_DEVICE_RX_CALLBACK   mDataReceivedCallback;
-STATIC USB_DEVICE_TX_CALLBACK   mDataSentCallback;
-
-STATIC EFI_USB_STRING_DESCRIPTOR *mLangStringDescriptor;
-STATIC EFI_USB_STRING_DESCRIPTOR *mManufacturerStringDescriptor;
-STATIC EFI_USB_STRING_DESCRIPTOR *mProductStringDescriptor;
-STATIC EFI_USB_STRING_DESCRIPTOR *mSerialStringDescriptor;
-
-STATIC CHAR16 mLangString[] = { 0x409 };
-
-STATIC CHAR16 mManufacturerString[] = {
-  '9', '6', 'B', 'o', 'a', 'r', 'd', 's'
-};
-
-STATIC CHAR16 mProductString[] = {
-  'H', 'i', 'K', 'e', 'y'
-};
-
-STATIC CHAR16 mSerialString[] = {
-  '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'
-};
-
-// The time between interrupt polls, in units of 100 nanoseconds
-// 10 Microseconds
-#define DW_INTERRUPT_POLL_PERIOD 10000
-STATIC int usb_drv_port_speed(void) /*To detect which mode was run, high speed or full speed*/
-{
-    /*
-    * 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
-    */
-    UINT32 val = READ_REG32(DSTS) & 2;
-    return (!val);
-}
-
-STATIC VOID reset_endpoints(void)
-{
-  /* EP0 IN ACTIVE NEXT=1 */
-  WRITE_REG32(DIEPCTL0, 0x8800);
-
-  /* EP0 OUT ACTIVE */
-  WRITE_REG32(DOEPCTL0, 0x8000);
-
-  /* Clear any pending OTG Interrupts */
-  WRITE_REG32(GOTGINT, 0xFFFFFFFF);
-
-  /* Clear any pending interrupts */
-  WRITE_REG32(GINTSTS, 0xFFFFFFFF);
-  WRITE_REG32(DIEPINT0, 0xFFFFFFFF);
-  WRITE_REG32(DOEPINT0, 0xFFFFFFFF);
-  WRITE_REG32(DIEPINT1, 0xFFFFFFFF);
-  WRITE_REG32(DOEPINT1, 0xFFFFFFFF);
-
-  /* IN EP interrupt mask */
-  WRITE_REG32(DIEPMSK, 0x0D);
-  /* OUT EP interrupt mask */
-  WRITE_REG32(DOEPMSK, 0x0D);
-  /* Enable interrupts on Ep0 */
-  WRITE_REG32(DAINTMSK, 0x00010001);
-
-  /* EP0 OUT Transfer Size:64 Bytes, 1 Packet, 3 Setup Packet, Read to receive setup packet*/
-  WRITE_REG32(DOEPTSIZ0, 0x60080040);
-
-  //notes that:the compulsive conversion is expectable.
-  g_dma_desc_ep0->status.b.bs = 0x3;
-  g_dma_desc_ep0->status.b.mtrf = 0;
-  g_dma_desc_ep0->status.b.sr = 0;
-  g_dma_desc_ep0->status.b.l = 1;
-  g_dma_desc_ep0->status.b.ioc = 1;
-  g_dma_desc_ep0->status.b.sp = 0;
-  g_dma_desc_ep0->status.b.bytes = 64;
-  g_dma_desc_ep0->buf = (UINT32)(UINTN)(p_ctrlreq);
-  g_dma_desc_ep0->status.b.sts = 0;
-  g_dma_desc_ep0->status.b.bs = 0x0;
-  WRITE_REG32(DOEPDMA0, (unsigned long)(g_dma_desc_ep0));
-  /* EP0 OUT ENABLE CLEARNAK */
-  WRITE_REG32(DOEPCTL0, (READ_REG32(DOEPCTL0) | 0x84000000));
-}
-
-STATIC VOID ep_tx(IN UINT8 ep, CONST VOID *ptr, UINTN len)
-{
-    UINT32 blocksize;
-    UINT32 packets;
-
-    /* EPx OUT ACTIVE */
-    WRITE_REG32(DIEPCTL(ep), (READ_REG32(DIEPCTL(ep))) | 0x8000);
-    if(!ep) {
-        blocksize = 64;
-    } else {
-        blocksize = usb_drv_port_speed() ? USB_BLOCK_HIGH_SPEED_SIZE : 64;
-    }
-    packets = (len + blocksize - 1) / blocksize;
-
-    if (!len) { //send a null packet
-        /* one empty packet */
-        g_dma_desc_in->status.b.bs = 0x3;
-        g_dma_desc_in->status.b.l = 1;
-        g_dma_desc_in->status.b.ioc = 1;
-        g_dma_desc_in->status.b.sp = 1;
-        g_dma_desc_in->status.b.bytes = 0;
-        g_dma_desc_in->buf = 0;
-        g_dma_desc_in->status.b.sts = 0;
-        g_dma_desc_in->status.b.bs = 0x0;
-
-        WRITE_REG32(DIEPDMA(ep), (UINT32)(UINTN)(g_dma_desc_in));             // DMA Address (DMAAddr) is zero
-    } else { //prepare to send a packet
-        /*WRITE_REG32((len | (packets << 19)), DIEPTSIZ(ep));*/  // packets+transfer size
-	WRITE_REG32(DIEPTSIZ(ep), len | (packets << 19));
-
-	//flush cache
-	WriteBackDataCacheRange ((void*)ptr, len);
-
-        g_dma_desc_in->status.b.bs = 0x3;
-        g_dma_desc_in->status.b.l = 1;
-        g_dma_desc_in->status.b.ioc = 1;
-        g_dma_desc_in->status.b.sp = 1;
-        g_dma_desc_in->status.b.bytes = len;
-        g_dma_desc_in->buf = (UINT32)((UINTN)ptr);
-        g_dma_desc_in->status.b.sts = 0;
-        g_dma_desc_in->status.b.bs = 0x0;
-        WRITE_REG32(DIEPDMA(ep), (UINT32)(UINTN)(g_dma_desc_in));         // ptr is DMA address
-    }
-    asm("dsb  sy");
-    asm("isb  sy");
-    /* epena & cnak*/
-    WRITE_REG32(DIEPCTL(ep), READ_REG32(DIEPCTL(ep)) | 0x84000800);
-    return;
-}
-
-STATIC VOID ep_rx(unsigned ep, UINTN len)
-{
-    /* EPx UNSTALL */
-    WRITE_REG32(DOEPCTL(ep), ((READ_REG32(DOEPCTL(ep))) & (~0x00200000)));
-    /* EPx OUT ACTIVE */
-    WRITE_REG32(DOEPCTL(ep), (READ_REG32(DOEPCTL(ep)) | 0x8000));
-
-    if (len >= DATA_SIZE)
-	    rx_desc_bytes = DATA_SIZE;
-    else
-	    rx_desc_bytes = len;
-
-    rx_buf = AllocatePool (DATA_SIZE);
-    ASSERT (rx_buf != NULL);
-
-    InvalidateDataCacheRange (rx_buf, len);
-
-    g_dma_desc->status.b.bs = 0x3;
-    g_dma_desc->status.b.mtrf = 0;
-    g_dma_desc->status.b.sr = 0;
-    g_dma_desc->status.b.l = 1;
-    g_dma_desc->status.b.ioc = 1;
-    g_dma_desc->status.b.sp = 0;
-    g_dma_desc->status.b.bytes = (UINT32)rx_desc_bytes;
-    g_dma_desc->buf = (UINT32)((UINTN)rx_buf);
-    g_dma_desc->status.b.sts = 0;
-    g_dma_desc->status.b.bs = 0x0;
-
-    asm("dsb  sy");
-    asm("isb  sy");
-    WRITE_REG32(DOEPDMA(ep), (UINT32)((UINTN)g_dma_desc));
-    /* EPx OUT ENABLE CLEARNAK */
-    WRITE_REG32(DOEPCTL(ep), (READ_REG32(DOEPCTL(ep)) | 0x84000000));
-}
-
-STATIC
-EFI_STATUS
-HandleGetDescriptor (
-  IN USB_DEVICE_REQUEST  *Request
-  )
-{
-  UINT8       DescriptorType;
-  UINTN       ResponseSize;
-  VOID       *ResponseData;
-
-  ResponseSize = 0;
-  ResponseData = NULL;
-
-  // Pretty confused if bmRequestType is anything but this:
-  ASSERT (Request->RequestType == USB_DEV_GET_DESCRIPTOR_REQ_TYPE);
-
-  // Choose the response
-  DescriptorType = Request->Value >> 8;
-  switch (DescriptorType) {
-  case USB_DESC_TYPE_DEVICE:
-    DEBUG ((EFI_D_INFO, "USB: Got a request for device descriptor\n"));
-    ResponseSize = sizeof (USB_DEVICE_DESCRIPTOR);
-    ResponseData = mDeviceDescriptor;
-    break;
-  case USB_DESC_TYPE_CONFIG:
-    DEBUG ((EFI_D_INFO, "USB: Got a request for config descriptor\n"));
-    ResponseSize = mConfigDescriptor->TotalLength;
-    ResponseData = mDescriptors;
-    break;
-  case USB_DESC_TYPE_STRING:
-    DEBUG ((EFI_D_INFO, "USB: Got a request for String descriptor %d\n", Request->Value & 0xFF));
-    switch (Request->Value & 0xff) {
-    case 0:
-      ResponseSize = mLangStringDescriptor->Length;
-      ResponseData = mLangStringDescriptor;
-      break;
-    case 1:
-      ResponseSize = mManufacturerStringDescriptor->Length;
-      ResponseData = mManufacturerStringDescriptor;
-      break;
-    case 2:
-      ResponseSize = mProductStringDescriptor->Length;
-      ResponseData = mProductStringDescriptor;
-      break;
-    case 3:
-      DwUsb->Get (mSerialStringDescriptor->String, &mSerialStringDescriptor->Length);
-      ResponseSize = mSerialStringDescriptor->Length;
-      ResponseData = mSerialStringDescriptor;
-      break;
-    }
-    break;
-  default:
-    DEBUG ((EFI_D_INFO, "USB: Didn't understand request for descriptor 0x%04x\n", Request->Value));
-    break;
-  }
-
-  // Send the response
-  if (ResponseData) {
-    ASSERT (ResponseSize != 0);
-
-    if (Request->Length < ResponseSize) {
-      // Truncate response
-      ResponseSize = Request->Length;
-    } else if (Request->Length > ResponseSize) {
-      DEBUG ((EFI_D_INFO, "USB: Info: ResponseSize < wLength\n"));
-    }
-
-    ep_tx(0, ResponseData, ResponseSize);
-  }
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-EFI_STATUS
-HandleSetAddress (
-  IN USB_DEVICE_REQUEST  *Request
-  )
-{
-  // Pretty confused if bmRequestType is anything but this:
-  ASSERT (Request->RequestType == USB_DEV_SET_ADDRESS_REQ_TYPE);
-  DEBUG ((EFI_D_INFO, "USB: Setting address to %d\n", Request->Value));
-  reset_endpoints();
-
-  WRITE_REG32(DCFG, (READ_REG32(DCFG) & ~0x7F0) | (Request->Value << 4));
-  ep_tx(0, 0, 0);
-
-  return EFI_SUCCESS;
-}
-
-int usb_drv_request_endpoint(unsigned int type, int dir)
-{
-  unsigned int ep = 1;    /*FIXME*/
-  int ret;
-  unsigned long newbits;
-
-  ret = (int)ep | dir;
-  newbits = (type << 18) | 0x10000000;
-
-  /*
-   * (type << 18):Endpoint Type (EPType)
-   * 0x10000000:Endpoint Enable (EPEna)
-   * 0x000C000:Endpoint Type (EPType);Hardcoded to 00 for control.
-   * (ep<<22):TxFIFO Number (TxFNum)
-   * 0x20000:NAK Status (NAKSts);The core is transmitting NAK handshakes on this endpoint.
-   */
-  if (dir) {  // IN: to host
-    WRITE_REG32(DIEPCTL(ep), ((READ_REG32(DIEPCTL(ep)))& ~0x000C0000) | newbits | (ep<<22)|0x20000);
-  } else {    // OUT: to device
-    WRITE_REG32(DOEPCTL(ep), ((READ_REG32(DOEPCTL(ep))) & ~0x000C0000) | newbits);
-  }
-
-  return ret;
-}
-
-STATIC
-EFI_STATUS
-HandleSetConfiguration (
-  IN USB_DEVICE_REQUEST  *Request
-  )
-{
-  ASSERT (Request->RequestType == USB_DEV_SET_CONFIGURATION_REQ_TYPE);
-
-  // Cancel all transfers
-  reset_endpoints();
-
-  usb_drv_request_endpoint(2, 0);
-  usb_drv_request_endpoint(2, 0x80);
-
-  WRITE_REG32(DIEPCTL1, (READ_REG32(DIEPCTL1)) | 0x10088800);
-
-  /* Enable interrupts on all endpoints */
-  WRITE_REG32(DAINTMSK, 0xFFFFFFFF);
-
-  ep_rx(1, CMD_SIZE);
-  ep_tx(0, 0, 0);
-  return EFI_SUCCESS;
-}
-
-
-STATIC
-EFI_STATUS
-HandleDeviceRequest (
-  IN USB_DEVICE_REQUEST  *Request
-  )
-{
-  EFI_STATUS  Status;
-
-  switch (Request->Request) {
-  case USB_DEV_GET_DESCRIPTOR:
-    Status = HandleGetDescriptor (Request);
-    break;
-  case USB_DEV_SET_ADDRESS:
-    Status = HandleSetAddress (Request);
-    break;
-  case USB_DEV_SET_CONFIGURATION:
-    Status = HandleSetConfiguration (Request);
-    break;
-  default:
-    DEBUG ((EFI_D_ERROR,
-      "Didn't understand RequestType 0x%x Request 0x%x\n",
-      Request->RequestType, Request->Request));
-      Status = EFI_INVALID_PARAMETER;
-    break;
-  }
-
-  return Status;
-}
-
-
-// Instead of actually registering interrupt handlers, we poll the controller's
-//  interrupt source register in this function.
-STATIC
-VOID
-CheckInterrupts (
-  IN EFI_EVENT  Event,
-  IN VOID      *Context
-  )
-{
-  UINT32 ints = READ_REG32(GINTSTS);    // interrupt register
-  UINT32 epints;
-
-  /*
-   * bus reset
-   * The core sets this bit to indicate that a reset is detected on the USB.
-   */
-  if (ints & 0x1000) {
-	  WRITE_REG32(DCFG, 0x800004);
-	  reset_endpoints();
-  }
-
-  /*
-   * enumeration done, we now know the speed
-   * The core sets this bit to indicate that speed enumeration is complete. The
-   * application must read the Device Status (DSTS) register to obtain the
-   * enumerated speed.
-   */
-  if (ints & 0x2000) {
-	  /* Set up the maximum packet sizes accordingly */
-	  unsigned long maxpacket = usb_drv_port_speed() ? USB_BLOCK_HIGH_SPEED_SIZE : 64;
-	  //Set Maximum In Packet Size (MPS)
-	  WRITE_REG32(DIEPCTL1, ((READ_REG32(DIEPCTL1)) & ~0x000003FF) | maxpacket);
-	  //Set Maximum Out Packet Size (MPS)
-	  WRITE_REG32(DOEPCTL1, ((READ_REG32(DOEPCTL1)) & ~0x000003FF) | maxpacket);
-  }
-
-  /*
-   * IN EP event
-   * The core sets this bit to indicate that an interrupt is pending on one of the IN
-   * endpoints of the core (in Device mode). The application must read the
-   * Device All Endpoints Interrupt (DAINT) register to determine the exact
-   * number of the IN endpoint on which the interrupt occurred, and then read
-   * the corresponding Device IN Endpoint-n Interrupt (DIEPINTn) register to
-   * determine the exact cause of the interrupt. The application must clear the
-   * appropriate status bit in the corresponding DIEPINTn register to clear this bit.
-   */
-  if (ints & 0x40000) {
-	  epints = READ_REG32(DIEPINT0);
-	  WRITE_REG32(DIEPINT0, epints);
-	  if (epints & 0x1) /* Transfer Completed Interrupt (XferCompl) */
-		  DEBUG ((EFI_D_INFO, "INT: IN TX completed.DIEPTSIZ(0) = 0x%x.\n", READ_REG32(DIEPTSIZ0)));
-
-	  epints = READ_REG32(DIEPINT1);
-	  WRITE_REG32(DIEPINT1, epints);
-	  if (epints & 0x1)
-		  DEBUG ((EFI_D_INFO, "ep1: IN TX completed\n"));
-  }
-
-  /*
-   * OUT EP event
-   * The core sets this bit to indicate that an interrupt is pending on one of the
-   * OUT endpoints of the core (in Device mode). The application must read the
-   * Device All Endpoints Interrupt (DAINT) register to determine the exact
-   * number of the OUT endpoint on which the interrupt occurred, and then read
-   * the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register
-   * to determine the exact cause of the interrupt. The application must clear the
-   * appropriate status bit in the corresponding DOEPINTn register to clear this bit.
-   */
-  if (ints & 0x80000) {
-	  /* indicates the status of an endpoint
-	   * with respect to USB- and AHB-related events. */
-	  epints = READ_REG32(DOEPINT0);
-	  if(epints) {
-		  WRITE_REG32(DOEPINT0, epints);
-		  if (epints & 0x1)
-			  DEBUG ((EFI_D_INFO,"INT: EP0 RX completed. DOEPTSIZ(0) = 0x%x.\n", READ_REG32(DOEPTSIZ0)));
-		  /*
-		   *
-		   IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-		   * Indicates that an IN token was received when the associated TxFIFO (periodic/nonperiodic)
-		   * was empty. This interrupt is asserted on the endpoint for which the IN token
-		   * was received.
-		   */
-		  if (epints & 0x8) { /* SETUP phase done */
-			  // PRINT_DEBUG("Setup phase \n");
-			  WRITE_REG32(DIEPCTL0, READ_REG32(DIEPCTL0) | 0x08000000);
-			  WRITE_REG32(DOEPCTL0, READ_REG32(DOEPCTL0) | 0x08000000);
-			  /*clear IN EP intr*/
-			  WRITE_REG32(DIEPINT0, 0xffffffff);
-			  HandleDeviceRequest((USB_DEVICE_REQUEST *)p_ctrlreq);
-		  }
-
-		  /* Make sure EP0 OUT is set up to accept the next request */
-		  /* memset(p_ctrlreq, 0, NUM_ENDPOINTS*8); */
-		  WRITE_REG32(DOEPTSIZ0, 0x60080040);
-		  /*
-		   * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
-		   * Indicates that an IN token was received when the associated TxFIFO (periodic/nonperiodic)
-		   * was empty. This interrupt is asserted on the endpoint for which the IN token
-		   * was received.
-		   */
-		  g_dma_desc_ep0->status.b.bs = 0x3;
-		  g_dma_desc_ep0->status.b.mtrf = 0;
-		  g_dma_desc_ep0->status.b.sr = 0;
-		  g_dma_desc_ep0->status.b.l = 1;
-		  g_dma_desc_ep0->status.b.ioc = 1;
-		  g_dma_desc_ep0->status.b.sp = 0;
-		  g_dma_desc_ep0->status.b.bytes = 64;
-		  g_dma_desc_ep0->buf = (UINT32)(UINTN)(p_ctrlreq);
-		  g_dma_desc_ep0->status.b.sts = 0;
-		  g_dma_desc_ep0->status.b.bs = 0x0;
-		  WRITE_REG32(DOEPDMA0, (unsigned long)(g_dma_desc_ep0));
-		  // endpoint enable; clear NAK
-		  WRITE_REG32(DOEPCTL0, 0x84000000);
-	  }
-
-	  epints = (READ_REG32(DOEPINT1));
-	  if(epints) {
-		  WRITE_REG32(DOEPINT1, epints);
-		  /* Transfer Completed Interrupt (XferCompl);Transfer completed */
-		  if (epints & 0x1) {
-			  asm("dsb  sy");
-			  asm("isb  sy");
-
-			  UINTN bytes = rx_desc_bytes - g_dma_desc->status.b.bytes;
-			  UINTN len = 0;
-
-			  if (MATCH_CMD_LITERAL ("download:", rx_buf)) {
-				  mNumDataBytes = AsciiStrHexToUint64 (rx_buf + sizeof ("download"));
-			  } else {
-				if (mNumDataBytes != 0)
-					mNumDataBytes -= bytes;
-			  }
-
-			  mDataReceivedCallback (bytes, rx_buf);
-
-			  if (mNumDataBytes == 0)
-				  len = CMD_SIZE;
-			  else if (mNumDataBytes > DATA_SIZE)
-				  len = DATA_SIZE;
-			  else
-				  len = mNumDataBytes;
-
-			  ep_rx(1, len);
-		  }
-	  }
-  }
-
-  //WRITE_REG32 clear ints
-  WRITE_REG32(GINTSTS, ints);
-}
-
-EFI_STATUS
-DwUsbSend (
-  IN        UINT8  EndpointIndex,
-  IN        UINTN  Size,
-  IN  CONST VOID  *Buffer
-  )
-{
-    ep_tx(EndpointIndex, Buffer, Size);
-    return 0;
-}
-
-STATIC VOID usb_init()
-{
-  VOID     *buf;
-  UINT32   data;
-
-  buf = UncachedAllocatePages (16);
-  g_dma_desc = buf;
-  g_dma_desc_ep0 = g_dma_desc + sizeof(struct dwc_otg_dev_dma_desc);
-  g_dma_desc_in = g_dma_desc_ep0 + sizeof(struct dwc_otg_dev_dma_desc);
-  p_ctrlreq = (USB_DEVICE_REQUEST *)g_dma_desc_in + sizeof(struct dwc_otg_dev_dma_desc);
-
-  SetMem(g_dma_desc, sizeof(struct dwc_otg_dev_dma_desc), 0);
-  SetMem(g_dma_desc_ep0, sizeof(struct dwc_otg_dev_dma_desc), 0);
-  SetMem(g_dma_desc_in, sizeof(struct dwc_otg_dev_dma_desc), 0);
-
-  /*Reset usb controller.*/
-  /* Wait for OTG AHB master idle */
-  do {
-    data = READ_REG32 (GRSTCTL) & GRSTCTL_AHBIDLE;
-  } while (data == 0);
-
-  /* OTG: Assert Software Reset */
-  WRITE_REG32 (GRSTCTL, GRSTCTL_CSFTRST);
-
-  /* Wait for OTG to ack reset */
-  while (READ_REG32 (GRSTCTL) & GRSTCTL_CSFTRST);
-
-  /* Wait for OTG AHB master idle */
-  while ((READ_REG32 (GRSTCTL) & GRSTCTL_AHBIDLE) == 0);
-
-  WRITE_REG32 (GDFIFOCFG, DATA_FIFO_CONFIG);
-  WRITE_REG32 (GRXFSIZ, RX_SIZE);
-  WRITE_REG32 (GNPTXFSIZ, ENDPOINT_TX_SIZE);
-  WRITE_REG32 (DIEPTXF1, DATA_IN_ENDPOINT_TX_FIFO1);
-  WRITE_REG32 (DIEPTXF2, DATA_IN_ENDPOINT_TX_FIFO2);
-  WRITE_REG32 (DIEPTXF3, DATA_IN_ENDPOINT_TX_FIFO3);
-  WRITE_REG32 (DIEPTXF4, DATA_IN_ENDPOINT_TX_FIFO4);
-  WRITE_REG32 (DIEPTXF5, DATA_IN_ENDPOINT_TX_FIFO5);
-  WRITE_REG32 (DIEPTXF6, DATA_IN_ENDPOINT_TX_FIFO6);
-  WRITE_REG32 (DIEPTXF7, DATA_IN_ENDPOINT_TX_FIFO7);
-  WRITE_REG32 (DIEPTXF8, DATA_IN_ENDPOINT_TX_FIFO8);
-  WRITE_REG32 (DIEPTXF9, DATA_IN_ENDPOINT_TX_FIFO9);
-  WRITE_REG32 (DIEPTXF10, DATA_IN_ENDPOINT_TX_FIFO10);
-  WRITE_REG32 (DIEPTXF11, DATA_IN_ENDPOINT_TX_FIFO11);
-  WRITE_REG32 (DIEPTXF12, DATA_IN_ENDPOINT_TX_FIFO12);
-  WRITE_REG32 (DIEPTXF13, DATA_IN_ENDPOINT_TX_FIFO13);
-  WRITE_REG32 (DIEPTXF14, DATA_IN_ENDPOINT_TX_FIFO14);
-  WRITE_REG32 (DIEPTXF15, DATA_IN_ENDPOINT_TX_FIFO15);
-
-  /*
-   * set Periodic TxFIFO Empty Level,
-   * Non-Periodic TxFIFO Empty Level,
-   * Enable DMA, Unmask Global Intr
-   */
-  WRITE_REG32 (GAHBCFG, GAHBCFG_CTRL_MASK);
-
-  /*select 8bit UTMI+, ULPI Inerface*/
-  WRITE_REG32 (GUSBCFG, 0x2400);
-
-  /* Detect usb work mode,host or device? */
-  do {
-    data = READ_REG32 (GINTSTS);
-  } while (data & GINTSTS_CURMODE_HOST);
-  MicroSecondDelay(3);
-
-  /*Init global and device mode csr register.*/
-  /*set Non-Zero-Length status out handshake */
-  data = (0x20 << DCFG_EPMISCNT_SHIFT) | DCFG_NZ_STS_OUT_HSHK;
-  WRITE_REG32 (DCFG, data);
-
-  /* Interrupt unmask: IN event, OUT event, bus reset */
-  data = GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_ENUMDONE | GINTSTS_USBRST;
-  WRITE_REG32 (GINTMSK, data);
-
-  do {
-    data = READ_REG32 (GINTSTS) & GINTSTS_ENUMDONE;
-  } while (data);
-
-  /* Clear any pending OTG Interrupts */
-  WRITE_REG32 (GOTGINT, ~0);
-  /* Clear any pending interrupts */
-  WRITE_REG32 (GINTSTS, ~0);
-  WRITE_REG32 (GINTMSK, ~0);
-  data = READ_REG32 (GOTGINT);
-  data &= ~0x3000;
-  WRITE_REG32 (GOTGINT, data);
-
-  /*endpoint settings cfg*/
-  reset_endpoints();
-  MicroSecondDelay (1);
-
-  /*init finish. and ready to transfer data*/
-
-  /* Soft Disconnect */
-  WRITE_REG32(DCTL, 0x802);
-  MicroSecondDelay(10000);
-
-  /* Soft Reconnect */
-  WRITE_REG32(DCTL, 0x800);
-}
-
-EFI_STATUS
-EFIAPI
-DwUsbStart (
-  IN USB_DEVICE_DESCRIPTOR   *DeviceDescriptor,
-  IN VOID                   **Descriptors,
-  IN USB_DEVICE_RX_CALLBACK   RxCallback,
-  IN USB_DEVICE_TX_CALLBACK   TxCallback
-  )
-{
-  UINT8                    *Ptr;
-  EFI_STATUS                Status;
-  EFI_EVENT                 TimerEvent;
-  UINTN                     StringDescriptorSize;
-
-  ASSERT (DeviceDescriptor != NULL);
-  ASSERT (Descriptors[0] != NULL);
-  ASSERT (RxCallback != NULL);
-  ASSERT (TxCallback != NULL);
-
-  StringDescriptorSize = sizeof (EFI_USB_STRING_DESCRIPTOR) +
-	                 sizeof (mLangString) + 1;
-  mLangStringDescriptor = AllocateZeroPool (StringDescriptorSize);
-  ASSERT (mLangStringDescriptor != NULL);
-  mLangStringDescriptor->Length = sizeof (mLangString);
-  mLangStringDescriptor->DescriptorType = USB_DESC_TYPE_STRING;
-  CopyMem (mLangStringDescriptor->String, mLangString,
-	   mLangStringDescriptor->Length);
-
-  StringDescriptorSize = sizeof (EFI_USB_STRING_DESCRIPTOR) +
-	                 sizeof (mManufacturerString) + 1;
-  mManufacturerStringDescriptor = AllocateZeroPool (StringDescriptorSize);
-  ASSERT (mManufacturerStringDescriptor != NULL);
-  mManufacturerStringDescriptor->Length = sizeof (mManufacturerString);
-  mManufacturerStringDescriptor->DescriptorType = USB_DESC_TYPE_STRING;
-  CopyMem (mManufacturerStringDescriptor->String, mManufacturerString,
-	   mManufacturerStringDescriptor->Length);
-
-  StringDescriptorSize = sizeof (EFI_USB_STRING_DESCRIPTOR) +
-	                 sizeof (mProductString) + 1;
-  mProductStringDescriptor = AllocateZeroPool (StringDescriptorSize);
-  ASSERT (mProductStringDescriptor != NULL);
-  mProductStringDescriptor->Length = sizeof (mProductString);
-  mProductStringDescriptor->DescriptorType = USB_DESC_TYPE_STRING;
-  CopyMem (mProductStringDescriptor->String, mProductString,
-	   mProductStringDescriptor->Length);
-
-  StringDescriptorSize = sizeof (EFI_USB_STRING_DESCRIPTOR) +
-	                 sizeof (mSerialString) + 1;
-  mSerialStringDescriptor = AllocateZeroPool (StringDescriptorSize);
-  ASSERT (mSerialStringDescriptor != NULL);
-  mSerialStringDescriptor->Length = sizeof (mSerialString);
-  mSerialStringDescriptor->DescriptorType = USB_DESC_TYPE_STRING;
-  CopyMem (mSerialStringDescriptor->String, mSerialString,
-	   mSerialStringDescriptor->Length);
-
-  usb_init();
-
-  mDeviceDescriptor = DeviceDescriptor;
-  mDescriptors = Descriptors[0];
-
-  // Right now we just support one configuration
-  ASSERT (mDeviceDescriptor->NumConfigurations == 1);
-  mDeviceDescriptor->StrManufacturer = 1;
-  mDeviceDescriptor->StrProduct = 2;
-  mDeviceDescriptor->StrSerialNumber = 3;
-  // ... and one interface
-  mConfigDescriptor = (USB_CONFIG_DESCRIPTOR *)mDescriptors;
-  ASSERT (mConfigDescriptor->NumInterfaces == 1);
-
-  Ptr = ((UINT8 *) mDescriptors) + sizeof (USB_CONFIG_DESCRIPTOR);
-  mInterfaceDescriptor = (USB_INTERFACE_DESCRIPTOR *) Ptr;
-  Ptr += sizeof (USB_INTERFACE_DESCRIPTOR);
-
-  mEndpointDescriptors = (USB_ENDPOINT_DESCRIPTOR *) Ptr;
-
-  mDataReceivedCallback = RxCallback;
-  mDataSentCallback = TxCallback;
-
-  // Register a timer event so CheckInterupts gets called periodically
-  Status = gBS->CreateEvent (
-                  EVT_TIMER | EVT_NOTIFY_SIGNAL,
-                  TPL_CALLBACK,
-                  CheckInterrupts,
-                  NULL,
-                  &TimerEvent
-                  );
-  ASSERT_EFI_ERROR (Status);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Status = gBS->SetTimer (
-                  TimerEvent,
-                  TimerPeriodic,
-                  DW_INTERRUPT_POLL_PERIOD
-                  );
-  ASSERT_EFI_ERROR (Status);
-
-  return Status;
-}
-
-USB_DEVICE_PROTOCOL mUsbDevice = {
-  DwUsbStart,
-  DwUsbSend
-};
-
-
-EFI_STATUS
-EFIAPI
-DwUsbEntryPoint (
-  IN EFI_HANDLE                            ImageHandle,
-  IN EFI_SYSTEM_TABLE                      *SystemTable
-  )
-{
-  EFI_STATUS      Status;
-  UINT8                     UsbMode;
-
-  Status = gBS->LocateProtocol (&gDwUsbProtocolGuid, NULL, (VOID **) &DwUsb);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "DwUsbEntryPoint: fail to locate DwUsbProtocolGuid, Status:%r\n", Status));
-    return Status;
-  }
-
-  //Mode: 1 for device, 0 for Host
-  UsbMode = USB_DEVICE_MODE;
-  Status = DwUsb->PhyInit(UsbMode);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "DwUsbEntryPoint: fail to init USB Phy, Status:%r\n", Status));
-    return Status;
-  }
-
-  return gBS->InstallProtocolInterface (
-		  &ImageHandle,
-		  &gUsbDeviceProtocolGuid,
-		  EFI_NATIVE_INTERFACE,
-		  &mUsbDevice
-		  );
-}
+/** @file
+
+  Copyright (c) 2015-2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Usb.h>
+#include <Library/ArmLib.h>
+#include <Library/TimerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UncachedMemoryAllocationLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BaseLib.h>
+#include <Protocol/DwUsb.h>
+#include <Protocol/UsbDevice.h>
+
+#include "DwUsbDxe.h"
+
+#define USB_TYPE_LENGTH               16
+#define USB_BLOCK_HIGH_SPEED_SIZE     512
+#define DATA_SIZE                     32768
+#define CMD_SIZE                      512
+#define MATCH_CMD_LITERAL(Cmd, Buf)   !AsciiStrnCmp (Cmd, Buf, sizeof (Cmd) - 1)
+
+// The time between interrupt polls, in units of 100 nanoseconds
+// 10 Microseconds
+#define DW_INTERRUPT_POLL_PERIOD      10000
+
+EFI_GUID  gDwUsbProtocolGuid = DW_USB_PROTOCOL_GUID;
+
+STATIC dwc_otg_dev_dma_desc_t *gDmaDesc,*gDmaDescEp0,*gDmaDescIn;
+STATIC USB_DEVICE_REQUEST *gCtrlReq;
+STATIC VOID *RxBuf;
+STATIC UINTN RxDescBytes = 0;
+STATIC UINTN mNumDataBytes;
+
+STATIC DW_USB_PROTOCOL          *DwUsb;
+
+STATIC USB_DEVICE_DESCRIPTOR    *mDeviceDescriptor;
+
+// The config descriptor, interface descriptor, and endpoint descriptors in a
+// buffer (in that order)
+STATIC VOID                     *mDescriptors;
+// Convenience pointers to those descriptors inside the buffer:
+STATIC USB_INTERFACE_DESCRIPTOR *mInterfaceDescriptor;
+STATIC USB_CONFIG_DESCRIPTOR    *mConfigDescriptor;
+STATIC USB_ENDPOINT_DESCRIPTOR  *mEndpointDescriptors;
+
+STATIC USB_DEVICE_RX_CALLBACK   mDataReceivedCallback;
+STATIC USB_DEVICE_TX_CALLBACK   mDataSentCallback;
+
+
+/* To detect which mode was run, high speed or full speed */
+STATIC
+UINTN
+UsbDrvPortSpeed (
+  VOID
+  )
+{
+  /*
+  * 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
+  */
+  UINT32          Val = READ_REG32 (DSTS) & 2;
+  return (!Val);
+}
+
+STATIC
+VOID
+ResetEndpoints (
+  VOID
+  )
+{
+  /* EP0 IN ACTIVE NEXT=1 */
+  WRITE_REG32 (DIEPCTL0, DXEPCTL_USBACTEP | BIT11);
+
+  /* EP0 OUT ACTIVE */
+  WRITE_REG32 (DOEPCTL0, DXEPCTL_USBACTEP);
+
+  /* Clear any pending OTG Interrupts */
+  WRITE_REG32 (GOTGINT, ~0);
+
+  /* Clear any pending interrupts */
+  WRITE_REG32 (GINTSTS, ~0);
+  WRITE_REG32 (DIEPINT0, ~0);
+  WRITE_REG32 (DOEPINT0, ~0);
+  WRITE_REG32 (DIEPINT1, ~0);
+  WRITE_REG32 (DOEPINT1, ~0);
+
+  /* IN EP interrupt mask */
+  WRITE_REG32 (DIEPMSK, DXEPMSK_TIMEOUTMSK | DXEPMSK_AHBERMSK | DXEPMSK_XFERCOMPLMSK);
+  /* OUT EP interrupt mask */
+  WRITE_REG32 (DOEPMSK, DXEPMSK_TIMEOUTMSK | DXEPMSK_AHBERMSK | DXEPMSK_XFERCOMPLMSK);
+  /* Enable interrupts on Ep0 */
+  WRITE_REG32 (DAINTMSK, (1 << DAINTMSK_OUTEPMSK_SHIFT) | (1 << DAINTMSK_INEPMSK_SHIFT));
+
+  /* EP0 OUT Transfer Size:64 Bytes, 1 Packet, 3 Setup Packet, Read to receive setup packet*/
+  WRITE_REG32 (DOEPTSIZ0, DXEPTSIZ_SUPCNT(3) | DXEPTSIZ_PKTCNT(1) | DXEPTSIZ_XFERSIZE(64));
+
+  //notes that:the compulsive conversion is expectable.
+  gDmaDescEp0->status.b.bs = 0x3;
+  gDmaDescEp0->status.b.mtrf = 0;
+  gDmaDescEp0->status.b.sr = 0;
+  gDmaDescEp0->status.b.l = 1;
+  gDmaDescEp0->status.b.ioc = 1;
+  gDmaDescEp0->status.b.sp = 0;
+  gDmaDescEp0->status.b.bytes = 64;
+  gDmaDescEp0->buf = (UINT32)(UINTN)(gCtrlReq);
+  gDmaDescEp0->status.b.sts = 0;
+  gDmaDescEp0->status.b.bs = 0x0;
+  WRITE_REG32 (DOEPDMA0, (UINT32)(UINTN)(gDmaDescEp0));
+  /* EP0 OUT ENABLE CLEARNAK */
+  WRITE_REG32 (DOEPCTL0, (READ_REG32 (DOEPCTL0) | DXEPCTL_EPENA | DXEPCTL_CNAK));
+}
+
+STATIC
+VOID
+EpTx (
+  IN UINT8          Ep,
+  IN CONST VOID    *Ptr,
+  IN UINTN          Len
+  )
+{
+    UINT32          BlockSize;
+    UINT32          Packets;
+
+    /* EPx OUT ACTIVE */
+    WRITE_REG32 (DIEPCTL (Ep), (READ_REG32 (DIEPCTL (Ep))) | DXEPCTL_USBACTEP);
+    if (!Ep) {
+        BlockSize = 64;
+    } else {
+        BlockSize = UsbDrvPortSpeed () ? USB_BLOCK_HIGH_SPEED_SIZE : 64;
+    }
+    Packets = (Len + BlockSize - 1) / BlockSize;
+
+    if (!Len) {
+      /* send one empty packet */
+      gDmaDescIn->status.b.bs = 0x3;
+      gDmaDescIn->status.b.l = 1;
+      gDmaDescIn->status.b.ioc = 1;
+      gDmaDescIn->status.b.sp = 1;
+      gDmaDescIn->status.b.bytes = 0;
+      gDmaDescIn->buf = 0;
+      gDmaDescIn->status.b.sts = 0;
+      gDmaDescIn->status.b.bs = 0x0;
+
+      WRITE_REG32 (DIEPDMA (Ep), (UINT32)(UINTN)(gDmaDescIn));             // DMA Address (DMAAddr) is zero
+    } else {
+      WRITE_REG32 (DIEPTSIZ (Ep), Len | (Packets << 19));
+
+      //flush cache
+      WriteBackDataCacheRange ((VOID *)Ptr, Len);
+
+      gDmaDescIn->status.b.bs = 0x3;
+      gDmaDescIn->status.b.l = 1;
+      gDmaDescIn->status.b.ioc = 1;
+      gDmaDescIn->status.b.sp = 1;
+      gDmaDescIn->status.b.bytes = Len;
+      gDmaDescIn->buf = (UINT32)((UINTN)Ptr);
+      gDmaDescIn->status.b.sts = 0;
+      gDmaDescIn->status.b.bs = 0x0;
+      WRITE_REG32 (DIEPDMA (Ep), (UINT32)(UINTN)(gDmaDescIn));         // Ptr is DMA address
+    }
+    ArmDataSynchronizationBarrier ();
+    /* epena & cnak */
+    WRITE_REG32 (DIEPCTL (Ep), READ_REG32 (DIEPCTL (Ep)) | DXEPCTL_EPENA | DXEPCTL_CNAK | BIT11);
+}
+
+STATIC
+VOID
+EpRx (
+  IN UINTN            Ep,
+  IN UINTN            Len
+  )
+{
+  /* EPx UNSTALL */
+  WRITE_REG32 (DOEPCTL (Ep), ((READ_REG32 (DOEPCTL (Ep))) & (~DXEPCTL_STALL)));
+  /* EPx OUT ACTIVE */
+  WRITE_REG32 (DOEPCTL (Ep), (READ_REG32 (DOEPCTL (Ep)) | DXEPCTL_USBACTEP));
+
+  if (Len >= DATA_SIZE) {
+    RxDescBytes = DATA_SIZE;
+  } else {
+    RxDescBytes = Len;
+  }
+
+  RxBuf = AllocatePool (DATA_SIZE);
+  ASSERT (RxBuf != NULL);
+
+  InvalidateDataCacheRange (RxBuf, Len);
+
+  gDmaDesc->status.b.bs = 0x3;
+  gDmaDesc->status.b.mtrf = 0;
+  gDmaDesc->status.b.sr = 0;
+  gDmaDesc->status.b.l = 1;
+  gDmaDesc->status.b.ioc = 1;
+  gDmaDesc->status.b.sp = 0;
+  gDmaDesc->status.b.bytes = (UINT32)RxDescBytes;
+  gDmaDesc->buf = (UINT32)((UINTN)RxBuf);
+  gDmaDesc->status.b.sts = 0;
+  gDmaDesc->status.b.bs = 0x0;
+
+  ArmDataSynchronizationBarrier ();
+  WRITE_REG32 (DOEPDMA (Ep), (UINT32)((UINTN)gDmaDesc));
+  /* EPx OUT ENABLE CLEARNAK */
+  WRITE_REG32 (DOEPCTL (Ep), (READ_REG32 (DOEPCTL (Ep)) | DXEPCTL_EPENA | DXEPCTL_CNAK));
+}
+
+STATIC
+EFI_STATUS
+HandleGetDescriptor (
+  IN USB_DEVICE_REQUEST  *Request
+  )
+{
+  UINT8       DescriptorType;
+  UINTN       ResponseSize;
+  VOID       *ResponseData;
+  EFI_USB_STRING_DESCRIPTOR        *Descriptor = NULL;
+  UINTN                             DescriptorSize;
+
+  ResponseSize = 0;
+  ResponseData = NULL;
+
+  // Pretty confused if bmRequestType is anything but this:
+  ASSERT (Request->RequestType == USB_DEV_GET_DESCRIPTOR_REQ_TYPE);
+
+  // Choose the response
+  DescriptorType = Request->Value >> 8;
+  switch (DescriptorType) {
+  case USB_DESC_TYPE_DEVICE:
+    DEBUG ((DEBUG_INFO, "USB: Got a request for device descriptor\n"));
+    ResponseSize = sizeof (USB_DEVICE_DESCRIPTOR);
+    ResponseData = mDeviceDescriptor;
+    break;
+  case USB_DESC_TYPE_CONFIG:
+    DEBUG ((DEBUG_INFO, "USB: Got a request for config descriptor\n"));
+    ResponseSize = mConfigDescriptor->TotalLength;
+    ResponseData = mDescriptors;
+    break;
+  case USB_DESC_TYPE_STRING:
+    DEBUG ((DEBUG_INFO, "USB: Got a request for String descriptor %d\n", Request->Value & 0xFF));
+    switch (Request->Value & 0xff) {
+    case 0:
+      DescriptorSize = sizeof (EFI_USB_STRING_DESCRIPTOR) +
+                       LANG_LENGTH * sizeof (CHAR16) + 1;
+      Descriptor = (EFI_USB_STRING_DESCRIPTOR *)AllocateZeroPool (DescriptorSize);
+      ASSERT (Descriptor != NULL);
+      Descriptor->Length = LANG_LENGTH * sizeof (CHAR16);
+      Descriptor->DescriptorType = USB_DESC_TYPE_STRING;
+      DwUsb->GetLang (Descriptor->String, &Descriptor->Length);
+      ResponseSize = Descriptor->Length;
+      ResponseData = Descriptor;
+      break;
+    case 1:
+      DescriptorSize = sizeof (EFI_USB_STRING_DESCRIPTOR) +
+                       MANU_FACTURER_STRING_LENGTH * sizeof (CHAR16) + 1;
+      Descriptor = (EFI_USB_STRING_DESCRIPTOR *)AllocateZeroPool (DescriptorSize);
+      ASSERT (Descriptor != NULL);
+      Descriptor->Length = MANU_FACTURER_STRING_LENGTH * sizeof (CHAR16);
+      Descriptor->DescriptorType = USB_DESC_TYPE_STRING;
+      DwUsb->GetManuFacturer (Descriptor->String, &Descriptor->Length);
+      ResponseSize = Descriptor->Length;
+      ResponseData = Descriptor;
+      break;
+    case 2:
+      DescriptorSize = sizeof (EFI_USB_STRING_DESCRIPTOR) +
+                       PRODUCT_STRING_LENGTH * sizeof (CHAR16) + 1;
+      Descriptor = (EFI_USB_STRING_DESCRIPTOR *)AllocateZeroPool (DescriptorSize);
+      ASSERT (Descriptor != NULL);
+      Descriptor->Length = PRODUCT_STRING_LENGTH * sizeof (CHAR16);
+      Descriptor->DescriptorType = USB_DESC_TYPE_STRING;
+      DwUsb->GetProduct (Descriptor->String, &Descriptor->Length);
+      ResponseSize = Descriptor->Length;
+      ResponseData = Descriptor;
+      break;
+    case 3:
+      DescriptorSize = sizeof (EFI_USB_STRING_DESCRIPTOR) +
+                       SERIAL_STRING_LENGTH * sizeof (CHAR16) + 1;
+      Descriptor = (EFI_USB_STRING_DESCRIPTOR *)AllocateZeroPool (DescriptorSize);
+      ASSERT (Descriptor != NULL);
+      Descriptor->Length = SERIAL_STRING_LENGTH * sizeof (CHAR16);
+      Descriptor->DescriptorType = USB_DESC_TYPE_STRING;
+      DwUsb->GetSerialNo (Descriptor->String, &Descriptor->Length);
+      ResponseSize = Descriptor->Length;
+      ResponseData = Descriptor;
+      break;
+    }
+    break;
+  default:
+    DEBUG ((DEBUG_INFO, "USB: Didn't understand request for descriptor 0x%04x\n", Request->Value));
+    break;
+  }
+
+  // Send the response
+  if (ResponseData) {
+    ASSERT (ResponseSize != 0);
+
+    if (Request->Length < ResponseSize) {
+      // Truncate response
+      ResponseSize = Request->Length;
+    } else if (Request->Length > ResponseSize) {
+      DEBUG ((DEBUG_INFO, "USB: Info: ResponseSize < wLength\n"));
+    }
+
+    EpTx (0, ResponseData, ResponseSize);
+  }
+  if (Descriptor) {
+    FreePool (Descriptor);
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+HandleSetAddress (
+  IN USB_DEVICE_REQUEST  *Request
+  )
+{
+  // Pretty confused if bmRequestType is anything but this:
+  ASSERT (Request->RequestType == USB_DEV_SET_ADDRESS_REQ_TYPE);
+  DEBUG ((DEBUG_INFO, "USB: Setting address to %d\n", Request->Value));
+  ResetEndpoints ();
+
+  WRITE_REG32 (DCFG, (READ_REG32 (DCFG) & ~DCFG_DEVADDR_MASK) | DCFG_DEVADDR(Request->Value));
+  EpTx (0, 0, 0);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+UINTN
+UsbDrvRequestEndpoint (
+  IN UINTN           Type,
+  IN UINTN           Dir
+  )
+{
+  UINTN              Ep = 1;
+  UINTN              Ret, NewBits;
+
+  Ret = Ep | Dir;
+  NewBits = (Type << 18) | 0x10000000;
+
+  /*
+   * (Type << 18):Endpoint Type (EPType)
+   * 0x10000000:Endpoint Enable (EPEna)
+   * 0x000C000:Endpoint Type (EPType);Hardcoded to 00 for control.
+   * (ep<<22):TxFIFO Number (TxFNum)
+   * 0x20000:NAK Status (NAKSts);The core is transmitting NAK handshakes on this endpoint.
+   */
+  if (Dir) {  // IN: to host
+    WRITE_REG32 (DIEPCTL (Ep), ((READ_REG32 (DIEPCTL (Ep))) & ~DXEPCTL_EPTYPE_MASK) | NewBits | (Ep << 22) | DXEPCTL_NAKSTS);
+  } else {    // OUT: to device
+    WRITE_REG32 (DOEPCTL (Ep), ((READ_REG32 (DOEPCTL (Ep))) & ~DXEPCTL_EPTYPE_MASK) | NewBits);
+  }
+
+  return Ret;
+}
+
+STATIC
+EFI_STATUS
+HandleSetConfiguration (
+  IN USB_DEVICE_REQUEST  *Request
+  )
+{
+  ASSERT (Request->RequestType == USB_DEV_SET_CONFIGURATION_REQ_TYPE);
+
+  // Cancel all transfers
+  ResetEndpoints ();
+
+  UsbDrvRequestEndpoint (2, 0);
+  UsbDrvRequestEndpoint (2, 0x80);
+
+  WRITE_REG32 (DIEPCTL1, (READ_REG32 (DIEPCTL1)) | BIT28 | BIT19 | DXEPCTL_USBACTEP | BIT11);
+
+  /* Enable interrupts on all endpoints */
+  WRITE_REG32 (DAINTMSK, ~0);
+
+  EpRx (1, CMD_SIZE);
+  EpTx (0, 0, 0);
+  return EFI_SUCCESS;
+}
+
+
+STATIC
+EFI_STATUS
+HandleDeviceRequest (
+  IN USB_DEVICE_REQUEST  *Request
+  )
+{
+  EFI_STATUS  Status;
+
+  switch (Request->Request) {
+  case USB_DEV_GET_DESCRIPTOR:
+    Status = HandleGetDescriptor (Request);
+    break;
+  case USB_DEV_SET_ADDRESS:
+    Status = HandleSetAddress (Request);
+    break;
+  case USB_DEV_SET_CONFIGURATION:
+    Status = HandleSetConfiguration (Request);
+    break;
+  default:
+    DEBUG ((DEBUG_ERROR,
+      "Didn't understand RequestType 0x%x Request 0x%x\n",
+      Request->RequestType, Request->Request));
+      Status = EFI_INVALID_PARAMETER;
+    break;
+  }
+
+  return Status;
+}
+
+
+// Instead of actually registering interrupt handlers, we poll the controller's
+//  interrupt source register in this function.
+STATIC
+VOID
+CheckInterrupts (
+  IN EFI_EVENT        Event,
+  IN VOID            *Context
+  )
+{
+  UINT32              Ints, EpInts;
+
+
+  // interrupt register
+  Ints = READ_REG32 (GINTSTS);
+
+  /*
+   * bus reset
+   * The core sets this bit to indicate that a reset is detected on the USB.
+   */
+  if (Ints & GINTSTS_USBRST) {
+    WRITE_REG32 (DCFG, DCFG_DESCDMA | DCFG_NZ_STS_OUT_HSHK);
+    ResetEndpoints ();
+  }
+
+  /*
+   * enumeration done, we now know the speed
+   * The core sets this bit to indicate that speed enumeration is complete. The
+   * application must read the Device Status (DSTS) register to obtain the
+   * enumerated speed.
+   */
+  if (Ints & GINTSTS_ENUMDONE) {
+    /* Set up the maximum packet sizes accordingly */
+    UINTN MaxPacket = UsbDrvPortSpeed () ? USB_BLOCK_HIGH_SPEED_SIZE : 64;
+    //Set Maximum In Packet Size (MPS)
+    WRITE_REG32 (DIEPCTL1, ((READ_REG32 (DIEPCTL1)) & ~DXEPCTL_MPS_MASK) | MaxPacket);
+    //Set Maximum Out Packet Size (MPS)
+    WRITE_REG32 (DOEPCTL1, ((READ_REG32 (DOEPCTL1)) & ~DXEPCTL_MPS_MASK) | MaxPacket);
+  }
+
+  /*
+   * IN EP event
+   * The core sets this bit to indicate that an interrupt is pending on one of the IN
+   * endpoInts of the core (in Device mode). The application must read the
+   * Device All EndpoInts Interrupt (DAINT) register to determine the exact
+   * number of the IN endpoint on which the interrupt occurred, and then read
+   * the corresponding Device IN Endpoint-n Interrupt (DIEPINTn) register to
+   * determine the exact cause of the interrupt. The application must clear the
+   * appropriate status bit in the corresponding DIEPINTn register to clear this bit.
+   */
+  if (Ints & GINTSTS_IEPINT) {
+    EpInts = READ_REG32 (DIEPINT0);
+    WRITE_REG32 (DIEPINT0, EpInts);
+    if (EpInts & DXEPINT_XFERCOMPL) {
+      DEBUG ((DEBUG_INFO, "INT: IN TX completed.DIEPTSIZ (0) = 0x%x.\n", READ_REG32 (DIEPTSIZ0)));
+    }
+
+    EpInts = READ_REG32 (DIEPINT1);
+    WRITE_REG32 (DIEPINT1, EpInts);
+    if (EpInts & DXEPINT_XFERCOMPL) {
+      DEBUG ((DEBUG_INFO, "ep1: IN TX completed\n"));
+    }
+  }
+
+  /*
+   * OUT EP event
+   * The core sets this bit to indicate that an interrupt is pending on one of the
+   * OUT endpoints of the core (in Device mode). The application must read the
+   * Device All EndpoInts Interrupt (DAINT) register to determine the exact
+   * number of the OUT endpoint on which the interrupt occurred, and then read
+   * the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register
+   * to determine the exact cause of the interrupt. The application must clear the
+   * appropriate status bit in the corresponding DOEPINTn register to clear this bit.
+   */
+  if (Ints & GINTSTS_OEPINT) {
+    /* indicates the status of an endpoint
+     * with respect to USB- and AHB-related events. */
+    EpInts = READ_REG32 (DOEPINT0);
+    if (EpInts) {
+      WRITE_REG32 (DOEPINT0, EpInts);
+      if (EpInts & DXEPINT_XFERCOMPL) {
+        DEBUG ((DEBUG_INFO, "INT: EP0 RX completed. DOEPTSIZ(0) = 0x%x.\n", READ_REG32 (DOEPTSIZ0)));
+      }
+      /*
+       *
+       IN Token Received When TxFIFO is Empty (INTknTXFEmp)
+       * Indicates that an IN token was received when the associated TxFIFO (periodic/nonperiodic)
+       * was empty. This interrupt is asserted on the endpoint for which the IN token
+       * was received.
+       */
+      if (EpInts & BIT3) { /* SETUP phase done */
+        WRITE_REG32 (DIEPCTL0, READ_REG32 (DIEPCTL0) | DXEPCTL_SNAK);
+        WRITE_REG32 (DOEPCTL0, READ_REG32 (DOEPCTL0) | DXEPCTL_SNAK);
+        /*clear IN EP intr*/
+        WRITE_REG32 (DIEPINT0, ~0);
+        HandleDeviceRequest((USB_DEVICE_REQUEST *)gCtrlReq);
+      }
+
+      /* Make sure EP0 OUT is set up to accept the next request */
+      WRITE_REG32 (DOEPTSIZ0, DXEPTSIZ_SUPCNT(3) | DXEPTSIZ_PKTCNT(1) | DXEPTSIZ_XFERSIZE(64));
+      /*
+       * IN Token Received When TxFIFO is Empty (INTknTXFEmp)
+       * Indicates that an IN token was received when the associated TxFIFO (periodic/nonperiodic)
+       * was empty. This interrupt is asserted on the endpoint for which the IN token
+       * was received.
+       */
+      gDmaDescEp0->status.b.bs = 0x3;
+      gDmaDescEp0->status.b.mtrf = 0;
+      gDmaDescEp0->status.b.sr = 0;
+      gDmaDescEp0->status.b.l = 1;
+      gDmaDescEp0->status.b.ioc = 1;
+      gDmaDescEp0->status.b.sp = 0;
+      gDmaDescEp0->status.b.bytes = 64;
+      gDmaDescEp0->buf = (UINT32)(UINTN)(gCtrlReq);
+      gDmaDescEp0->status.b.sts = 0;
+      gDmaDescEp0->status.b.bs = 0x0;
+      WRITE_REG32 (DOEPDMA0, (UINT32)(UINTN)(gDmaDescEp0));
+      // endpoint enable; clear NAK
+      WRITE_REG32 (DOEPCTL0, DXEPCTL_EPENA | DXEPCTL_CNAK);
+    }
+
+    EpInts = (READ_REG32 (DOEPINT1));
+    if (EpInts) {
+      WRITE_REG32 (DOEPINT1, EpInts);
+      /* Transfer Completed Interrupt (XferCompl);Transfer completed */
+      if (EpInts & DXEPINT_XFERCOMPL) {
+
+        UINTN Bytes = RxDescBytes - gDmaDesc->status.b.bytes;
+        UINTN Len = 0;
+
+        ArmDataSynchronizationBarrier ();
+        if (MATCH_CMD_LITERAL ("download:", RxBuf)) {
+          mNumDataBytes = AsciiStrHexToUint64 (RxBuf + sizeof ("download:"));
+        } else {
+          if (mNumDataBytes != 0) {
+            mNumDataBytes -= Bytes;
+          }
+        }
+
+        mDataReceivedCallback (Bytes, RxBuf);
+
+        if (mNumDataBytes == 0) {
+          Len = CMD_SIZE;
+        } else if (mNumDataBytes > DATA_SIZE) {
+          Len = DATA_SIZE;
+        } else {
+          Len = mNumDataBytes;
+        }
+
+        EpRx (1, Len);
+      }
+    }
+  }
+
+  //WRITE_REG32 clear ints
+  WRITE_REG32 (GINTSTS, Ints);
+}
+
+EFI_STATUS
+DwUsbSend (
+  IN        UINT8  EndpointIndex,
+  IN        UINTN  Size,
+  IN  CONST VOID  *Buffer
+  )
+{
+    EpTx (EndpointIndex, Buffer, Size);
+    return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+DwUsbInit (
+  VOID
+  )
+{
+  VOID     *Buf;
+  UINT32   Data;
+
+  Buf = UncachedAllocatePages (16);
+  gDmaDesc = Buf;
+  gDmaDescEp0 = gDmaDesc + sizeof (dwc_otg_dev_dma_desc_t);
+  gDmaDescIn = gDmaDescEp0 + sizeof (dwc_otg_dev_dma_desc_t);
+  gCtrlReq = (USB_DEVICE_REQUEST *)gDmaDescIn + sizeof (dwc_otg_dev_dma_desc_t);
+
+  ZeroMem (gDmaDesc, sizeof (dwc_otg_dev_dma_desc_t));
+  ZeroMem (gDmaDescEp0, sizeof (dwc_otg_dev_dma_desc_t));
+  ZeroMem (gDmaDescIn, sizeof (dwc_otg_dev_dma_desc_t));
+
+  /*Reset usb controller.*/
+  /* Wait for OTG AHB master idle */
+  do {
+    Data = READ_REG32 (GRSTCTL) & GRSTCTL_AHBIDLE;
+  } while (Data == 0);
+
+  /* OTG: Assert Software Reset */
+  WRITE_REG32 (GRSTCTL, GRSTCTL_CSFTRST);
+
+  /* Wait for OTG to ack reset */
+  while (READ_REG32 (GRSTCTL) & GRSTCTL_CSFTRST);
+
+  /* Wait for OTG AHB master idle */
+  while ((READ_REG32 (GRSTCTL) & GRSTCTL_AHBIDLE) == 0);
+
+  WRITE_REG32 (GDFIFOCFG, DATA_FIFO_CONFIG);
+  WRITE_REG32 (GRXFSIZ, RX_SIZE);
+  WRITE_REG32 (GNPTXFSIZ, ENDPOINT_TX_SIZE);
+  WRITE_REG32 (DIEPTXF1, DATA_IN_ENDPOINT_TX_FIFO1);
+  WRITE_REG32 (DIEPTXF2, DATA_IN_ENDPOINT_TX_FIFO2);
+  WRITE_REG32 (DIEPTXF3, DATA_IN_ENDPOINT_TX_FIFO3);
+  WRITE_REG32 (DIEPTXF4, DATA_IN_ENDPOINT_TX_FIFO4);
+  WRITE_REG32 (DIEPTXF5, DATA_IN_ENDPOINT_TX_FIFO5);
+  WRITE_REG32 (DIEPTXF6, DATA_IN_ENDPOINT_TX_FIFO6);
+  WRITE_REG32 (DIEPTXF7, DATA_IN_ENDPOINT_TX_FIFO7);
+  WRITE_REG32 (DIEPTXF8, DATA_IN_ENDPOINT_TX_FIFO8);
+  WRITE_REG32 (DIEPTXF9, DATA_IN_ENDPOINT_TX_FIFO9);
+  WRITE_REG32 (DIEPTXF10, DATA_IN_ENDPOINT_TX_FIFO10);
+  WRITE_REG32 (DIEPTXF11, DATA_IN_ENDPOINT_TX_FIFO11);
+  WRITE_REG32 (DIEPTXF12, DATA_IN_ENDPOINT_TX_FIFO12);
+  WRITE_REG32 (DIEPTXF13, DATA_IN_ENDPOINT_TX_FIFO13);
+  WRITE_REG32 (DIEPTXF14, DATA_IN_ENDPOINT_TX_FIFO14);
+  WRITE_REG32 (DIEPTXF15, DATA_IN_ENDPOINT_TX_FIFO15);
+
+  /*
+   * set Periodic TxFIFO Empty Level,
+   * Non-Periodic TxFIFO Empty Level,
+   * Enable DMA, Unmask Global Intr
+   */
+  WRITE_REG32 (GAHBCFG, GAHBCFG_CTRL_MASK);
+
+  /*select 8bit UTMI+, ULPI Inerface*/
+  WRITE_REG32 (GUSBCFG, 0x2400);
+
+  /* Detect usb work mode,host or device? */
+  do {
+    Data = READ_REG32 (GINTSTS);
+  } while (Data & GINTSTS_CURMODE_HOST);
+  MicroSecondDelay (3);
+
+  /*Init global and device mode csr register.*/
+  /*set Non-Zero-Length status out handshake */
+  Data = (0x20 << DCFG_EPMISCNT_SHIFT) | DCFG_NZ_STS_OUT_HSHK;
+  WRITE_REG32 (DCFG, Data);
+
+  /* Interrupt unmask: IN event, OUT event, bus reset */
+  Data = GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_ENUMDONE | GINTSTS_USBRST;
+  WRITE_REG32 (GINTMSK, Data);
+
+  do {
+    Data = READ_REG32 (GINTSTS) & GINTSTS_ENUMDONE;
+  } while (Data);
+
+  /* Clear any pending OTG Interrupts */
+  WRITE_REG32 (GOTGINT, ~0);
+  /* Clear any pending interrupts */
+  WRITE_REG32 (GINTSTS, ~0);
+  WRITE_REG32 (GINTMSK, ~0);
+  Data = READ_REG32 (GOTGINT);
+  Data &= ~0x3000;
+  WRITE_REG32 (GOTGINT, Data);
+
+  /* endpoint settings cfg */
+  ResetEndpoints ();
+  MicroSecondDelay (1);
+
+  /* init finish. and ready to transfer data */
+
+  /* Soft Disconnect */
+  WRITE_REG32 (DCTL, DCTL_PWRONPRGDONE | DCTL_SFTDISCON);
+  MicroSecondDelay (10000);
+
+  /* Soft Reconnect */
+  WRITE_REG32 (DCTL, DCTL_PWRONPRGDONE);
+}
+
+EFI_STATUS
+EFIAPI
+DwUsbStart (
+  IN USB_DEVICE_DESCRIPTOR   *DeviceDescriptor,
+  IN VOID                   **Descriptors,
+  IN USB_DEVICE_RX_CALLBACK   RxCallback,
+  IN USB_DEVICE_TX_CALLBACK   TxCallback
+  )
+{
+  UINT8                    *Ptr;
+  EFI_STATUS                Status;
+  EFI_EVENT                 TimerEvent;
+
+  ASSERT (DeviceDescriptor != NULL);
+  ASSERT (Descriptors[0] != NULL);
+  ASSERT (RxCallback != NULL);
+  ASSERT (TxCallback != NULL);
+
+  DwUsbInit();
+
+  mDeviceDescriptor = DeviceDescriptor;
+  mDescriptors = Descriptors[0];
+
+  // Right now we just support one configuration
+  ASSERT (mDeviceDescriptor->NumConfigurations == 1);
+  mDeviceDescriptor->StrManufacturer = 1;
+  mDeviceDescriptor->StrProduct = 2;
+  mDeviceDescriptor->StrSerialNumber = 3;
+  // ... and one interface
+  mConfigDescriptor = (USB_CONFIG_DESCRIPTOR *)mDescriptors;
+  ASSERT (mConfigDescriptor->NumInterfaces == 1);
+
+  Ptr = ((UINT8 *) mDescriptors) + sizeof (USB_CONFIG_DESCRIPTOR);
+  mInterfaceDescriptor = (USB_INTERFACE_DESCRIPTOR *) Ptr;
+  Ptr += sizeof (USB_INTERFACE_DESCRIPTOR);
+
+  mEndpointDescriptors = (USB_ENDPOINT_DESCRIPTOR *) Ptr;
+
+  mDataReceivedCallback = RxCallback;
+  mDataSentCallback = TxCallback;
+
+  // Register a timer event so CheckInterupts gets called periodically
+  Status = gBS->CreateEvent (
+                  EVT_TIMER | EVT_NOTIFY_SIGNAL,
+                  TPL_CALLBACK,
+                  CheckInterrupts,
+                  NULL,
+                  &TimerEvent
+                  );
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = gBS->SetTimer (
+                  TimerEvent,
+                  TimerPeriodic,
+                  DW_INTERRUPT_POLL_PERIOD
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+USB_DEVICE_PROTOCOL mUsbDevice = {
+  DwUsbStart,
+  DwUsbSend
+};
+
+
+EFI_STATUS
+EFIAPI
+DwUsbEntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS      Status;
+
+  Status = gBS->LocateProtocol (&gDwUsbProtocolGuid, NULL, (VOID **) &DwUsb);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = DwUsb->PhyInit(USB_DEVICE_MODE);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  return gBS->InstallProtocolInterface (
+                &ImageHandle,
+                &gUsbDeviceProtocolGuid,
+                EFI_NATIVE_INTERFACE,
+                &mUsbDevice
+                );
+}
diff --git a/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec b/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec
index eb6a667..f991492 100644
--- a/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec
+++ b/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec
@@ -1,46 +1,46 @@
-#/** @file
-# Framework Module Development Environment Industry Standards
-#
-# This Package provides headers and libraries that conform to EFI/PI Industry standards.
-# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
-# Copyright (c) 2015-2016, Linaro. All rights reserved.<BR>
-#
-#    This program and the accompanying materials are licensed and made available under
-#    the terms and conditions of the BSD License which accompanies this distribution.
-#    The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
-#
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = OpenPlatformDriversUsbDwUsbDxePkg
-  PACKAGE_GUID                   = 114a3be9-10f7-4bf1-81ca-09ac52d4c3d5
-  PACKAGE_VERSION                = 0.1
-
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-#                   Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-
-[Guids.common]
-  gAndroidFastbootUsbGuid       = { 0xf6bec3fe, 0x88fb, 0x11e3, { 0xae, 0x84, 0xe7, 0x3b, 0x77, 0x56, 0x1c, 0x35 }}
-  gDwUsbDxeTokenSpaceGuid	= { 0x131c4d02, 0x9449, 0x4ee9, { 0xba, 0x3d, 0x69, 0x50, 0x21, 0x89, 0x26, 0x0b }}
-
-[Protocols.common]
-  gDwUsbProtocolGuid            = { 0x109fa264, 0x7811, 0x4862, { 0xa9, 0x73, 0x4a, 0xb2, 0xef, 0x2e, 0xe2, 0xff }}
-
-[PcdsFixedAtBuild.common]
-  # DwUsb Driver PCDs
-  gDwUsbDxeTokenSpaceGuid.PcdDwUsbDxeBaseAddress|0x0|UINT32|0x00000001
-  gDwUsbDxeTokenSpaceGuid.PcdSysCtrlBaseAddress|0x0|UINT32|0x00000002
+#/** @file
+# Framework Module Development Environment Industry Standards
+#
+# This Package provides headers and libraries that conform to EFI/PI Industry standards.
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2015-2017, Linaro. All rights reserved.<BR>
+#
+#    This program and the accompanying materials are licensed and made available under
+#    the terms and conditions of the BSD License which accompanies this distribution.
+#    The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = OpenPlatformDriversUsbDwUsbDxePkg
+  PACKAGE_GUID                   = 114a3be9-10f7-4bf1-81ca-09ac52d4c3d5
+  PACKAGE_VERSION                = 0.1
+
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+  gAndroidFastbootUsbGuid       = { 0xf6bec3fe, 0x88fb, 0x11e3, { 0xae, 0x84, 0xe7, 0x3b, 0x77, 0x56, 0x1c, 0x35 }}
+  gDwUsbDxeTokenSpaceGuid       = { 0x131c4d02, 0x9449, 0x4ee9, { 0xba, 0x3d, 0x69, 0x50, 0x21, 0x89, 0x26, 0x0b }}
+
+[Protocols.common]
+  gDwUsbProtocolGuid            = { 0x109fa264, 0x7811, 0x4862, { 0xa9, 0x73, 0x4a, 0xb2, 0xef, 0x2e, 0xe2, 0xff }}
+
+[PcdsFixedAtBuild.common]
+  # DwUsb Driver PCDs
+  gDwUsbDxeTokenSpaceGuid.PcdDwUsbDxeBaseAddress|0x0|UINT32|0x00000001
+  gDwUsbDxeTokenSpaceGuid.PcdSysCtrlBaseAddress|0x0|UINT32|0x00000002
diff --git a/Drivers/Usb/DwUsbDxe/DwUsbDxe.h b/Drivers/Usb/DwUsbDxe/DwUsbDxe.h
index cd47798..7f909c3 100644
--- a/Drivers/Usb/DwUsbDxe/DwUsbDxe.h
+++ b/Drivers/Usb/DwUsbDxe/DwUsbDxe.h
@@ -1,594 +1,627 @@
-/** @file
-
-  Copyright (c) 2015, Linaro Limited. All rights reserved.
-  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __DW_USB_DXE_H__
-#define __DW_USB_DXE_H__
-
-#define DW_USB_BASE                     FixedPcdGet32 (PcdDwUsbDxeBaseAddress)
-
-#define READ_REG32(Offset)		MmioRead32 (DW_USB_BASE + Offset)
-#define READ_REG16(Offset)		(UINT16)READ_REG32 (Offset)
-#define WRITE_REG32(Offset, Val)  	MmioWrite32 (DW_USB_BASE + Offset, Val)
-#define WRITE_REG16(Offset, Val)  	MmioWrite32 (DW_USB_BASE + Offset, (UINT32) Val)
-#define WRITE_REG8(Offset, Val)   	MmioWrite32 (DW_USB_BASE + Offset, (UINT32) Val)
-
-// Max packet size in bytes (For Full Speed USB 64 is the only valid value)
-#define MAX_PACKET_SIZE_CONTROL     64
-
-#define MAX_PACKET_SIZE_BULK        512
-
-// 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer
-#define DW_NUM_ENDPOINTS               16
-
-// Endpoint Indexes
-#define DW_EP0SETUP                    0x20
-#define DW_EP0RX                       0x00
-#define DW_EP0TX                       0x01
-#define DW_EP1RX                       0x02
-#define DW_EP1TX                       0x03
-
-// DcInterrupt bits
-#define DW_DC_INTERRUPT_BRESET         BIT0
-#define DW_DC_INTERRUPT_SOF            BIT1
-#define DW_DC_INTERRUPT_PSOF           BIT2
-#define DW_DC_INTERRUPT_SUSP           BIT3
-#define DW_DC_INTERRUPT_RESUME         BIT4
-#define DW_DC_INTERRUPT_HS_STAT        BIT5
-#define DW_DC_INTERRUPT_DMA            BIT6
-#define DW_DC_INTERRUPT_VBUS           BIT7
-#define DW_DC_INTERRUPT_EP0SETUP       BIT8
-#define DW_DC_INTERRUPT_EP0RX          BIT10
-#define DW_DC_INTERRUPT_EP0TX          BIT11
-#define DW_DC_INTERRUPT_EP1RX          BIT12
-#define DW_DC_INTERRUPT_EP1TX          BIT13
-// All valid peripheral controller interrupts
-#define DW_DC_INTERRUPT_MASK           0x003FFFDFF
-
-#define DW_ADDRESS                     0x200
-#define DW_ADDRESS_DEVEN               BIT7
-
-#define DW_MODE                        0x20C
-#define DW_MODE_DATA_BUS_WIDTH         BIT8
-#define DW_MODE_CLKAON                 BIT7
-#define DW_MODE_SFRESET                BIT4
-#define DW_MODE_WKUPCS                 BIT2
-
-#define DW_ENDPOINT_MAX_PACKET_SIZE    0x204
-
-#define DW_ENDPOINT_TYPE               0x208
-#define DW_ENDPOINT_TYPE_NOEMPKT       BIT4
-#define DW_ENDPOINT_TYPE_ENABLE        BIT3
-
-#define DW_INTERRUPT_CONFIG            0x210
-// Interrupt config value to only interrupt on ACK of IN and OUT tokens
-#define DW_INTERRUPT_CONFIG_ACK_ONLY   BIT2 | BIT5 | BIT6
-
-#define DW_DC_INTERRUPT                0x218
-#define DW_DC_INTERRUPT_ENABLE         0x214
-
-#define DW_CTRL_FUNCTION               0x228
-#define DW_CTRL_FUNCTION_VENDP         BIT3
-#define DW_CTRL_FUNCTION_DSEN          BIT2
-#define DW_CTRL_FUNCTION_STATUS        BIT1
-
-#define DW_DEVICE_UNLOCK               0x27C
-#define DW_DEVICE_UNLOCK_MAGIC         0xAA37
-
-#define DW_SW_RESET_REG                0x30C
-#define DW_SW_RESET_ALL                BIT0
-
-#define DW_DEVICE_ID                   0x370
-
-#define DW_OTG_CTRL_SET                0x374
-#define DW_OTG_CTRL_CLR                OTG_CTRL_SET + 2
-#define DW_OTG_CTRL_OTG_DISABLE        BIT10
-#define DW_OTG_CTRL_VBUS_CHRG          BIT6
-#define DW_OTG_CTRL_VBUS_DISCHRG       BIT5
-#define DW_OTG_CTRL_DM_PULLDOWN        BIT2
-#define DW_OTG_CTRL_DP_PULLDOWN        BIT1
-#define DW_OTG_CTRL_DP_PULLUP          BIT0
-
-#define DW_OTG_STATUS                  0x378
-#define DW_OTG_STATUS_B_SESS_END       BIT7
-#define DW_OTG_STATUS_A_B_SESS_VLD     BIT1
-
-#define DW_OTG_INTERRUPT_LATCH_SET     0x37C
-#define DW_OTG_INTERRUPT_LATCH_CLR     0x37E
-#define DW_OTG_INTERRUPT_ENABLE_RISE   0x384
-
-#define DW_DMA_ENDPOINT_INDEX          0x258
-
-#define DW_ENDPOINT_INDEX              0x22c
-#define DW_DATA_PORT                   0x220
-#define DW_BUFFER_LENGTH               0x21c
-
-// Device ID Values
-#define PHILLIPS_VENDOR_ID_VAL 0x04cc
-#define DW_PRODUCT_ID_VAL 0x1761
-#define DW_DEVICE_ID_VAL ((ISP1761_PRODUCT_ID_VAL << 16) |\
-                               PHILLIPS_VENDOR_ID_VAL)
-
-#define DWC_OTG_BASE		           DW_USB_BASE
-
-#define USB_NUM_ENDPOINTS                  2
-#define MAX_EPS_CHANNELS 		   16
-
-#define BULK_OUT_EP 			   1
-#define BULK_IN_EP			   1
-
-#define RX_REQ_LEN 			   512
-#define MAX_PACKET_LEN 			   512
-
-#define DATA_FIFO_CONFIG 		   0x0F801000
-/* RX FIFO: 2048 bytes */
-#define RX_SIZE          		   0x00000200
-/* Non-periodic TX FIFO: 128 bytes. start address: 0x200 * 4. */
-#define ENDPOINT_TX_SIZE 		   0x01000200
-
-/* EP1  TX FIFO: 1024 bytes. start address: 0x220 * 4. */
-/* EP2  TX FIFO: 1024 bytes. start address: 0x320 * 4. */
-/* EP3  TX FIFO: 1024 bytes. start address: 0x420 * 4. */
-/* EP4  TX FIFO: 1024 bytes. start address: 0x520 * 4. */
-/* EP5  TX FIFO: 128 bytes. start address: 0x620 * 4. */
-/* EP6  TX FIFO: 128 bytes. start address: 0x640 * 4. */
-/* EP7  TX FIFO: 128 bytes. start address: 0x660 * 4. */
-/* EP8  TX FIFO: 128 bytes. start address: 0x680 * 4. */
-/* EP9  TX FIFO: 128 bytes. start address: 0x6A0 * 4. */
-/* EP10 TX FIFO: 128 bytes. start address: 0x6C0 * 4. */
-/* EP11 TX FIFO: 128  bytes. start address: 0x6E0 * 4. */
-/* EP12 TX FIFO: 128  bytes. start address: 0x700 * 4. */
-/* EP13 TX FIFO: 128  bytes. start address: 0x720 * 4. */
-/* EP14 TX FIFO: 128  bytes. start address: 0x740 * 4. */
-/* EP15 TX FIFO: 128  bytes. start address: 0x760 * 4. */
-
-#define DATA_IN_ENDPOINT_TX_FIFO1  0x01000220
-#define DATA_IN_ENDPOINT_TX_FIFO2  0x01000320
-#define DATA_IN_ENDPOINT_TX_FIFO3  0x01000420
-#define DATA_IN_ENDPOINT_TX_FIFO4  0x01000520
-#define DATA_IN_ENDPOINT_TX_FIFO5  0x00200620
-#define DATA_IN_ENDPOINT_TX_FIFO6  0x00200640
-#define DATA_IN_ENDPOINT_TX_FIFO7  0x00200680
-#define DATA_IN_ENDPOINT_TX_FIFO8  0x002006A0
-#define DATA_IN_ENDPOINT_TX_FIFO9  0x002006C0
-#define DATA_IN_ENDPOINT_TX_FIFO10 0x002006E0
-#define DATA_IN_ENDPOINT_TX_FIFO11 0x00200700
-#define DATA_IN_ENDPOINT_TX_FIFO12 0x00200720
-#define DATA_IN_ENDPOINT_TX_FIFO13 0x00200740
-#define DATA_IN_ENDPOINT_TX_FIFO14 0x00200760
-#define DATA_IN_ENDPOINT_TX_FIFO15 0x00200F00
-
-/*DWC_OTG regsiter descriptor*/
-/*Device mode CSR MAP*/
-#define DEVICE_CSR_BASE			(0x800)
-/*Device mode CSR MAP*/
-#define DEVICE_INEP_BASE		(0x900)
-/*Device mode CSR MAP*/
-#define DEVICE_OUTEP_BASE		(0xB00)
-
-/*** OTG LINK CORE REGISTERS ***/
-/* Core Global Registers */
-#define GOTGCTL     			(0x000)
-#define GOTGINT     			(0x004)
-#define GAHBCFG     			(0x008)
-#define GAHBCFG_P_TXF_EMP_LVL           (1 << 8)
-#define GAHBCFG_NP_TXF_EMP_LVL          (1 << 7)
-#define GAHBCFG_DMA_EN                  (1 << 5)
-#define GAHBCFG_GLBL_INTR_EN            (1 << 0)
-#define GAHBCFG_CTRL_MASK               (GAHBCFG_P_TXF_EMP_LVL | \
-                                         GAHBCFG_NP_TXF_EMP_LVL | \
-                                         GAHBCFG_DMA_EN | \
-                                         GAHBCFG_GLBL_INTR_EN)
-
-#define GUSBCFG     			(0x00C)
-#define GRSTCTL     			(0x010)
-#define GRSTCTL_AHBIDLE                 (1 << 31)
-#define GRSTCTL_CSFTRST                 (1 << 0)
-
-#define GINTSTS				(0x014)
-#define GINTSTS_WKUPINT                 (1 << 31)
-#define GINTSTS_SESSREGINT              (1 << 30)
-#define GINTSTS_DISCONNINT              (1 << 29)
-#define GINTSTS_CONIDSTSCHNG            (1 << 28)
-#define GINTSTS_LPMTRANRCVD             (1 << 27)
-#define GINTSTS_PTXFEMP                 (1 << 26)
-#define GINTSTS_HCHINT                  (1 << 25)
-#define GINTSTS_PRTINT                  (1 << 24)
-#define GINTSTS_RESETDET                (1 << 23)
-#define GINTSTS_FET_SUSP                (1 << 22)
-#define GINTSTS_INCOMPL_IP              (1 << 21)
-#define GINTSTS_INCOMPL_SOIN            (1 << 20)
-#define GINTSTS_OEPINT                  (1 << 19)
-#define GINTSTS_IEPINT                  (1 << 18)
-#define GINTSTS_EPMIS                   (1 << 17)
-#define GINTSTS_RESTOREDONE             (1 << 16)
-#define GINTSTS_EOPF                    (1 << 15)
-#define GINTSTS_ISOUTDROP               (1 << 14)
-#define GINTSTS_ENUMDONE                (1 << 13)
-#define GINTSTS_USBRST                  (1 << 12)
-#define GINTSTS_USBSUSP                 (1 << 11)
-#define GINTSTS_ERLYSUSP                (1 << 10)
-#define GINTSTS_I2CINT                  (1 << 9)
-#define GINTSTS_ULPI_CK_INT             (1 << 8)
-#define GINTSTS_GOUTNAKEFF              (1 << 7)
-#define GINTSTS_GINNAKEFF               (1 << 6)
-#define GINTSTS_NPTXFEMP                (1 << 5)
-#define GINTSTS_RXFLVL                  (1 << 4)
-#define GINTSTS_SOF                     (1 << 3)
-#define GINTSTS_OTGINT                  (1 << 2)
-#define GINTSTS_MODEMIS                 (1 << 1)
-#define GINTSTS_CURMODE_HOST            (1 << 0)
-
-#define GINTMSK     			(0x018)
-#define GRXSTSR     			(0x01C)
-#define GRXSTSP     			(0x020)
-#define GRXFSIZ     			(0x024)
-#define GNPTXFSIZ   			(0x028)
-#define GNPTXSTS    			(0x02C)
-
-#define GHWCFG1     			(0x044)
-#define GHWCFG2     			(0x048)
-#define GHWCFG3     			(0x04c)
-#define GHWCFG4     			(0x050)
-#define GLPMCFG     			(0x054)
-
-#define GDFIFOCFG     			(0x05c)
-
-#define HPTXFSIZ    			(0x100)
-#define DIEPTXF(x) 			(0x100 + 4 * (x))
-#define DIEPTXF1   			(0x104)
-#define DIEPTXF2   			(0x108)
-#define DIEPTXF3   			(0x10C)
-#define DIEPTXF4   			(0x110)
-#define DIEPTXF5   			(0x114)
-#define DIEPTXF6   			(0x118)
-#define DIEPTXF7   			(0x11C)
-#define DIEPTXF8   			(0x120)
-#define DIEPTXF9   			(0x124)
-#define DIEPTXF10  			(0x128)
-#define DIEPTXF11  			(0x12C)
-#define DIEPTXF12  			(0x130)
-#define DIEPTXF13  			(0x134)
-#define DIEPTXF14  			(0x138)
-#define DIEPTXF15  			(0x13C)
-
-/*** HOST MODE REGISTERS ***/
-/* Host Global Registers */
-#define HCFG       			(0x400)
-#define HFIR       			(0x404)
-#define HFNUM      			(0x408)
-#define HPTXSTS    			(0x410)
-#define HAINT      			(0x414)
-#define HAINTMSK   			(0x418)
-
-/* Host Port Control and Status Registers */
-#define HPRT        			(0x440)
-
-/* Host Channel-Specific Registers */
-#define HCCHAR(x)   			(0x500 + 0x20 * (x))
-#define HCSPLT(x)   			(0x504 + 0x20 * (x))
-#define HCINT(x)    			(0x508 + 0x20 * (x))
-#define HCINTMSK(x) 			(0x50C + 0x20 * (x))
-#define HCTSIZ(x)   			(0x510 + 0x20 * (x))
-#define HCDMA(x)    			(0x514 + 0x20 * (x))
-#define HCCHAR0     			(0x500)
-#define HCSPLT0     			(0x504)
-#define HCINT0      			(0x508)
-#define HCINTMSK0   			(0x50C)
-#define HCTSIZ0     			(0x510)
-#define HCDMA0      			(0x514)
-#define HCCHAR1     			(0x520)
-#define HCSPLT1     			(0x524)
-#define HCINT1      			(0x528)
-#define HCINTMSK1   			(0x52C)
-#define HCTSIZ1     			(0x530)
-#define HCDMA1      			(0x534)
-#define HCCHAR2     			(0x540)
-#define HCSPLT2     			(0x544)
-#define HCINT2      			(0x548)
-#define HCINTMSK2   			(0x54C)
-#define HCTSIZ2     			(0x550)
-#define HCDMA2      			(0x554)
-#define HCCHAR3     			(0x560)
-#define HCSPLT3     			(0x564)
-#define HCINT3      			(0x568)
-#define HCINTMSK3   			(0x56C)
-#define HCTSIZ3     			(0x570)
-#define HCDMA3      			(0x574)
-#define HCCHAR4     			(0x580)
-#define HCSPLT4     			(0x584)
-#define HCINT4      			(0x588)
-#define HCINTMSK4   			(0x58C)
-#define HCTSIZ4     			(0x590)
-#define HCDMA4      			(0x594)
-#define HCCHAR5     			(0x5A0)
-#define HCSPLT5     			(0x5A4)
-#define HCINT5      			(0x5A8)
-#define HCINTMSK5   			(0x5AC)
-#define HCTSIZ5     			(0x5B0)
-#define HCDMA5      			(0x5B4)
-#define HCCHAR6     			(0x5C0)
-#define HCSPLT6     			(0x5C4)
-#define HCINT6      			(0x5C8)
-#define HCINTMSK6   			(0x5CC)
-#define HCTSIZ6     			(0x5D0)
-#define HCDMA6      			(0x5D4)
-#define HCCHAR7     			(0x5E0)
-#define HCSPLT7     			(0x5E4)
-#define HCINT7      			(0x5E8)
-#define HCINTMSK7   			(0x5EC)
-#define HCTSIZ7     			(0x5F0)
-#define HCDMA7      			(0x5F4)
-#define HCCHAR8     			(0x600)
-#define HCSPLT8     			(0x604)
-#define HCINT8      			(0x608)
-#define HCINTMSK8   			(0x60C)
-#define HCTSIZ8     			(0x610)
-#define HCDMA8      			(0x614)
-#define HCCHAR9     			(0x620)
-#define HCSPLT9     			(0x624)
-#define HCINT9      			(0x628)
-#define HCINTMSK9   			(0x62C)
-#define HCTSIZ9     			(0x630)
-#define HCDMA9      			(0x634)
-#define HCCHAR10    			(0x640)
-#define HCSPLT10    			(0x644)
-#define HCINT10     			(0x648)
-#define HCINTMSK10  			(0x64C)
-#define HCTSIZ10    			(0x650)
-#define HCDMA10     			(0x654)
-#define HCCHAR11    			(0x660)
-#define HCSPLT11    			(0x664)
-#define HCINT11     			(0x668)
-#define HCINTMSK11  			(0x66C)
-#define HCTSIZ11    			(0x670)
-#define HCDMA11     			(0x674)
-#define HCCHAR12    			(0x680)
-#define HCSPLT12    			(0x684)
-#define HCINT12     			(0x688)
-#define HCINTMSK12  			(0x68C)
-#define HCTSIZ12    			(0x690)
-#define HCDMA12     			(0x694)
-#define HCCHAR13    			(0x6A0)
-#define HCSPLT13    			(0x6A4)
-#define HCINT13     			(0x6A8)
-#define HCINTMSK13  			(0x6AC)
-#define HCTSIZ13    			(0x6B0)
-#define HCDMA13     			(0x6B4)
-#define HCCHAR14    			(0x6C0)
-#define HCSPLT14    			(0x6C4)
-#define HCINT14     			(0x6C8)
-#define HCINTMSK14  			(0x6CC)
-#define HCTSIZ14    			(0x6D0)
-#define HCDMA14     			(0x6D4)
-#define HCCHAR15    			(0x6E0)
-#define HCSPLT15    			(0x6E4)
-#define HCINT15     			(0x6E8)
-#define HCINTMSK15  			(0x6EC)
-#define HCTSIZ15    			(0x6F0)
-#define HCDMA15     			(0x6F4)
-
-/*** DEVICE MODE REGISTERS ***/
-/* Device Global Registers */
-#define DCFG        			(0x800)
-#define DCFG_EPMISCNT_MASK              (0x1F << 18)
-#define DCFG_EPMISCNT_SHIFT             (18)
-#define DCFG_NZ_STS_OUT_HSHK            (1 << 2)
-
-#define DCTL        			(0x804)
-#define DSTS        			(0x808)
-#define DIEPMSK     			(0x810)
-#define DOEPMSK     			(0x814)
-#define DAINT       			(0x818)
-#define DAINTMSK    			(0x81C)
-#define DTKNQR1     			(0x820)
-#define DTKNQR2     			(0x824)
-#define DVBUSDIS    			(0x828)
-#define DVBUSPULSE  			(0x82C)
-#define DTHRCTL     			(0x830)
-
-/* Device Logical IN Endpoint-Specific Registers */
-#define DIEPCTL(x)  			(0x900 + 0x20 * (x))
-#define DIEPINT(x)  			(0x908 + 0x20 * (x))
-#define DIEPTSIZ(x) 			(0x910 + 0x20 * (x))
-#define DIEPDMA(x)  			(0x914 + 0x20 * (x))
-#define DTXFSTS(x)  			(0x918 + 0x20 * (x))
-
-#define DIEPCTL0    			(0x900)
-#define DIEPINT0    			(0x908)
-#define DIEPTSIZ0   			(0x910)
-#define DIEPDMA0    			(0x914)
-#define DIEPCTL1    			(0x920)
-#define DIEPINT1    			(0x928)
-#define DIEPTSIZ1   			(0x930)
-#define DIEPDMA1    			(0x934)
-#define DIEPCTL2    			(0x940)
-#define DIEPINT2    			(0x948)
-#define DIEPTSIZ2  			(0x950)
-#define DIEPDMA2    			(0x954)
-#define DIEPCTL3    			(0x960)
-#define DIEPINT3    			(0x968)
-#define DIEPTSIZ3   			(0x970)
-#define DIEPDMA3    			(0x974)
-#define DIEPCTL4    			(0x980)
-#define DIEPINT4    			(0x988)
-#define DIEPTSIZ4   			(0x990)
-#define DIEPDMA4    			(0x994)
-#define DIEPCTL5    			(0x9A0)
-#define DIEPINT5    			(0x9A8)
-#define DIEPTSIZ5   			(0x9B0)
-#define DIEPDMA5    			(0x9B4)
-#define DIEPCTL6    			(0x9C0)
-#define DIEPINT6    			(0x9C8)
-#define DIEPTSIZ6   			(0x9D0)
-#define DIEPDMA6    			(0x9D4)
-#define DIEPCTL7    			(0x9E0)
-#define DIEPINT7    			(0x9E8)
-#define DIEPTSIZ7   			(0x9F0)
-#define DIEPDMA7    			(0x9F4)
-#define DIEPCTL8    			(0xA00)
-#define DIEPINT8    			(0xA08)
-#define DIEPTSIZ8   			(0xA10)
-#define DIEPDMA8    			(0xA14)
-#define DIEPCTL9    			(0xA20)
-#define DIEPINT9    			(0xA28)
-#define DIEPTSIZ9   			(0xA30)
-#define DIEPDMA9    			(0xA34)
-#define DIEPCTL10   			(0xA40)
-#define DIEPINT10   			(0xA48)
-#define DIEPTSIZ10  			(0xA50)
-#define DIEPDMA10   			(0xA54)
-#define DIEPCTL11   			(0xA60)
-#define DIEPINT11   			(0xA68)
-#define DIEPTSIZ11  			(0xA70)
-#define DIEPDMA11   			(0xA74)
-#define DIEPCTL12   			(0xA80)
-#define DIEPINT12   			(0xA88)
-#define DIEPTSIZ12  			(0xA90)
-#define DIEPDMA12   			(0xA94)
-#define DIEPCTL13   			(0xAA0)
-#define DIEPINT13   			(0xAA8)
-#define DIEPTSIZ13  			(0xAB0)
-#define DIEPDMA13   			(0xAB4)
-#define DIEPCTL14   			(0xAC0)
-#define DIEPINT14   			(0xAC8)
-#define DIEPTSIZ14  			(0xAD0)
-#define DIEPDMA14   			(0xAD4)
-#define DIEPCTL15   			(0xAE0)
-#define DIEPINT15   			(0xAE8)
-#define DIEPTSIZ15  			(0xAF0)
-#define DIEPDMA15   			(0xAF4)
-
-/* Device Logical OUT Endpoint-Specific Registers */
-#define DOEPCTL(x)  			(0xB00 + 0x20 * (x))
-#define DOEPINT(x)  			(0xB08 + 0x20 * (x))
-#define DOEPTSIZ(x) 			(0xB10 + 0x20 * (x))
-#define DOEPDMA(x)  			(0xB14 + 0x20 * (x))
-#define DOEPCTL0    			(0xB00)
-#define DOEPINT0    			(0xB08)
-#define DOEPTSIZ0   			(0xB10)
-#define DOEPDMA0    			(0xB14)
-#define DOEPCTL1    			(0xB20)
-#define DOEPINT1    			(0xB28)
-#define DOEPTSIZ1   			(0xB30)
-#define DOEPDMA1    			(0xB34)
-#define DOEPCTL2    			(0xB40)
-#define DOEPINT2    			(0xB48)
-#define DOEPTSIZ2   			(0xB50)
-#define DOEPDMA2    			(0xB54)
-#define DOEPCTL3    			(0xB60)
-#define DOEPINT3    			(0xB68)
-#define DOEPTSIZ3   			(0xB70)
-#define DOEPDMA3    			(0xB74)
-#define DOEPCTL4    			(0xB80)
-#define DOEPINT4    			(0xB88)
-#define DOEPTSIZ4   			(0xB90)
-#define DOEPDMA4    			(0xB94)
-#define DOEPCTL5    			(0xBA0)
-#define DOEPINT5    			(0xBA8)
-#define DOEPTSIZ5   			(0xBB0)
-#define DOEPDMA5    			(0xBB4)
-#define DOEPCTL6    			(0xBC0)
-#define DOEPINT6    			(0xBC8)
-#define DOEPTSIZ6   			(0xBD0)
-#define DOEPDMA6    			(0xBD4)
-#define DOEPCTL7    			(0xBE0)
-#define DOEPINT7    			(0xBE8)
-#define DOEPTSIZ7   			(0xBF0)
-#define DOEPDMA7    			(0xBF4)
-#define DOEPCTL8    			(0xC00)
-#define DOEPINT8    			(0xC08)
-#define DOEPTSIZ8   			(0xC10)
-#define DOEPDMA8    			(0xC14)
-#define DOEPCTL9    			(0xC20)
-#define DOEPINT9    			(0xC28)
-#define DOEPTSIZ9   			(0xC30)
-#define DOEPDMA9    			(0xC34)
-#define DOEPCTL10   			(0xC40)
-#define DOEPINT10   			(0xC48)
-#define DOEPTSIZ10  			(0xC50)
-#define DOEPDMA10   			(0xC54)
-#define DOEPCTL11   			(0xC60)
-#define DOEPINT11   			(0xC68)
-#define DOEPTSIZ11  			(0xC70)
-#define DOEPDMA11   			(0xC74)
-#define DOEPCTL12   			(0xC80)
-#define DOEPINT12   			(0xC88)
-#define DOEPTSIZ12  			(0xC90)
-#define DOEPDMA12   			(0xC94)
-#define DOEPCTL13   			(0xCA0)
-#define DOEPINT13   			(0xCA8)
-#define DOEPTSIZ13  			(0xCB0)
-#define DOEPDMA13   			(0xCB4)
-#define DOEPCTL14   			(0xCC0)
-#define DOEPINT14   			(0xCC8)
-#define DOEPTSIZ14  			(0xCD0)
-#define DOEPDMA14   			(0xCD4)
-#define DOEPCTL15   			(0xCE0)
-#define DOEPINT15   			(0xCE8)
-#define DOEPTSIZ15  			(0xCF0)
-#define DOEPDMA15   			(0xCF4)
-
-/* Power and Clock Gating Register */
-#define PCGCCTL				(0xE00)
-
-#define EP0FIFO				(0x1000)
-
-/**
- * This union represents the bit fields in the DMA Descriptor
- * status quadlet. Read the quadlet into the <i>d32</i> member then
- * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
- * <i>b_iso_in</i> elements.
- */
-typedef union dev_dma_desc_sts {
-		/** raw register data */
-	unsigned int d32;
-		/** quadlet bits */
-	struct {
-		/** Received number of bytes */
-		unsigned bytes:16;
-		/** NAK bit - only for OUT EPs */
-		unsigned nak:1;
-		unsigned reserved17_22:6;
-		/** Multiple Transfer - only for OUT EPs */
-		unsigned mtrf:1;
-		/** Setup Packet received - only for OUT EPs */
-		unsigned sr:1;
-		/** Interrupt On Complete */
-		unsigned ioc:1;
-		/** Short Packet */
-		unsigned sp:1;
-		/** Last */
-		unsigned l:1;
-		/** Receive Status */
-		unsigned sts:2;
-		/** Buffer Status */
-		unsigned bs:2;
-	} b;
-} dev_dma_desc_sts_t;
-
-/**
- * DMA Descriptor structure
- *
- * DMA Descriptor structure contains two quadlets:
- * Status quadlet and Data buffer pointer.
- */
-typedef struct dwc_otg_dev_dma_desc {
-	/** DMA Descriptor status quadlet */
-	dev_dma_desc_sts_t status;
-	/** DMA Descriptor data buffer pointer */
-	UINT32 buf;
-} dwc_otg_dev_dma_desc_t;
-
-#endif //ifndef __DW_USB_DXE_H__
+/** @file
+
+  Copyright (c) 2015-2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __DW_USB_DXE_H__
+#define __DW_USB_DXE_H__
+
+#define DW_USB_BASE                     FixedPcdGet32 (PcdDwUsbDxeBaseAddress)
+
+#define READ_REG32(Offset)              MmioRead32 (DW_USB_BASE + Offset)
+#define READ_REG16(Offset)              (UINT16)READ_REG32 (Offset)
+#define WRITE_REG32(Offset, Val)        MmioWrite32 (DW_USB_BASE + Offset, Val)
+#define WRITE_REG16(Offset, Val)        MmioWrite32 (DW_USB_BASE + Offset, (UINT32) Val)
+#define WRITE_REG8(Offset, Val)         MmioWrite32 (DW_USB_BASE + Offset, (UINT32) Val)
+
+// Max packet size in bytes (For Full Speed USB 64 is the only valid value)
+#define MAX_PACKET_SIZE_CONTROL         64
+
+#define MAX_PACKET_SIZE_BULK            512
+
+// 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer
+#define DW_NUM_ENDPOINTS                16
+
+// Endpoint Indexes
+#define DW_EP0SETUP                     0x20
+#define DW_EP0RX                        0x00
+#define DW_EP0TX                        0x01
+#define DW_EP1RX                        0x02
+#define DW_EP1TX                        0x03
+
+// DcInterrupt bits
+#define DW_DC_INTERRUPT_EP1TX           BIT13
+#define DW_DC_INTERRUPT_EP1RX           BIT12
+#define DW_DC_INTERRUPT_EP0TX           BIT11
+#define DW_DC_INTERRUPT_EP0RX           BIT10
+#define DW_DC_INTERRUPT_EP0SETUP        BIT8
+#define DW_DC_INTERRUPT_VBUS            BIT7
+#define DW_DC_INTERRUPT_DMA             BIT6
+#define DW_DC_INTERRUPT_HS_STAT         BIT5
+#define DW_DC_INTERRUPT_RESUME          BIT4
+#define DW_DC_INTERRUPT_SUSP            BIT3
+#define DW_DC_INTERRUPT_PSOF            BIT2
+#define DW_DC_INTERRUPT_SOF             BIT1
+#define DW_DC_INTERRUPT_BRESET          BIT0
+// All valid peripheral controller int  rrupts
+#define DW_DC_INTERRUPT_MASK            0x003FFFDFF
+
+#define DW_ADDRESS                      0x200
+#define DW_ADDRESS_DEVEN                BIT7
+
+#define DW_MODE                         0x20C
+#define DW_MODE_DATA_BUS_WIDTH          BIT8
+#define DW_MODE_CLKAON                  BIT7
+#define DW_MODE_SFRESET                 BIT4
+#define DW_MODE_WKUPCS                  BIT2
+
+#define DW_ENDPOINT_MAX_PACKET_SIZE     0x204
+
+#define DW_ENDPOINT_TYPE                0x208
+#define DW_ENDPOINT_TYPE_NOEMPKT        BIT4
+#define DW_ENDPOINT_TYPE_ENABLE         BIT3
+
+#define DW_INTERRUPT_CONFIG             0x210
+// Interrupt config value to only interrupt on ACK of IN and OUT tokens
+#define DW_INTERRUPT_CONFIG_ACK_ONLY    (BIT2 | BIT5 | BIT6)
+
+#define DW_DC_INTERRUPT                 0x218
+#define DW_DC_INTERRUPT_ENABLE          0x214
+
+#define DW_CTRL_FUNCTION                0x228
+#define DW_CTRL_FUNCTION_VENDP          BIT3
+#define DW_CTRL_FUNCTION_DSEN           BIT2
+#define DW_CTRL_FUNCTION_STATUS         BIT1
+
+#define DW_DEVICE_UNLOCK                0x27C
+#define DW_DEVICE_UNLOCK_MAGIC          0xAA37
+
+#define DW_SW_RESET_REG                 0x30C
+#define DW_SW_RESET_ALL                 BIT0
+
+#define DW_DEVICE_ID                    0x370
+
+#define DW_OTG_CTRL_SET                 0x374
+#define DW_OTG_CTRL_CLR                 (OTG_CTRL_SET + 2)
+#define DW_OTG_CTRL_OTG_DISABLE         BIT10
+#define DW_OTG_CTRL_VBUS_CHRG           BIT6
+#define DW_OTG_CTRL_VBUS_DISCHRG        BIT5
+#define DW_OTG_CTRL_DM_PULLDOWN         BIT2
+#define DW_OTG_CTRL_DP_PULLDOWN         BIT1
+#define DW_OTG_CTRL_DP_PULLUP           BIT0
+
+#define DW_OTG_STATUS                   0x378
+#define DW_OTG_STATUS_B_SESS_END        BIT7
+#define DW_OTG_STATUS_A_B_SESS_VLD      BIT1
+
+#define DW_OTG_INTERRUPT_LATCH_SET      0x37C
+#define DW_OTG_INTERRUPT_LATCH_CLR      0x37E
+#define DW_OTG_INTERRUPT_ENABLE_RISE    0x384
+
+#define DW_DMA_ENDPOINT_INDEX           0x258
+
+#define DW_ENDPOINT_INDEX               0x22c
+#define DW_DATA_PORT                    0x220
+#define DW_BUFFER_LENGTH                0x21c
+
+// Device ID Values
+#define PHILLIPS_VENDOR_ID_VAL          0x04cc
+#define DW_PRODUCT_ID_VAL               0x1761
+#define DW_DEVICE_ID_VAL                ((ISP1761_PRODUCT_ID_VAL << 16) | \
+                                         PHILLIPS_VENDOR_ID_VAL)
+
+#define DWC_OTG_BASE                    DW_USB_BASE
+
+#define USB_NUM_ENDPOINTS               2
+#define MAX_EPS_CHANNELS                16
+
+#define BULK_OUT_EP                     1
+#define BULK_IN_EP                      1
+
+#define RX_REQ_LEN                      512
+#define MAX_PACKET_LEN                  512
+
+#define DATA_FIFO_CONFIG                0x0F801000
+/* RX FIFO: 2048 bytes */
+#define RX_SIZE                         0x00000200
+/* Non-periodic TX FIFO: 128 bytes. start address: 0x200 * 4. */
+#define ENDPOINT_TX_SIZE                0x01000200
+
+/* EP1  TX FIFO: 1024 bytes. start address: 0x220 * 4. */
+/* EP2  TX FIFO: 1024 bytes. start address: 0x320 * 4. */
+/* EP3  TX FIFO: 1024 bytes. start address: 0x420 * 4. */
+/* EP4  TX FIFO: 1024 bytes. start address: 0x520 * 4. */
+/* EP5  TX FIFO: 128 bytes. start address: 0x620 * 4. */
+/* EP6  TX FIFO: 128 bytes. start address: 0x640 * 4. */
+/* EP7  TX FIFO: 128 bytes. start address: 0x660 * 4. */
+/* EP8  TX FIFO: 128 bytes. start address: 0x680 * 4. */
+/* EP9  TX FIFO: 128 bytes. start address: 0x6A0 * 4. */
+/* EP10 TX FIFO: 128 bytes. start address: 0x6C0 * 4. */
+/* EP11 TX FIFO: 128  bytes. start address: 0x6E0 * 4. */
+/* EP12 TX FIFO: 128  bytes. start address: 0x700 * 4. */
+/* EP13 TX FIFO: 128  bytes. start address: 0x720 * 4. */
+/* EP14 TX FIFO: 128  bytes. start address: 0x740 * 4. */
+/* EP15 TX FIFO: 128  bytes. start address: 0x760 * 4. */
+
+#define DATA_IN_ENDPOINT_TX_FIFO1       0x01000220
+#define DATA_IN_ENDPOINT_TX_FIFO2       0x01000320
+#define DATA_IN_ENDPOINT_TX_FIFO3       0x01000420
+#define DATA_IN_ENDPOINT_TX_FIFO4       0x01000520
+#define DATA_IN_ENDPOINT_TX_FIFO5       0x00200620
+#define DATA_IN_ENDPOINT_TX_FIFO6       0x00200640
+#define DATA_IN_ENDPOINT_TX_FIFO7       0x00200680
+#define DATA_IN_ENDPOINT_TX_FIFO8       0x002006A0
+#define DATA_IN_ENDPOINT_TX_FIFO9       0x002006C0
+#define DATA_IN_ENDPOINT_TX_FIFO10      0x002006E0
+#define DATA_IN_ENDPOINT_TX_FIFO11      0x00200700
+#define DATA_IN_ENDPOINT_TX_FIFO12      0x00200720
+#define DATA_IN_ENDPOINT_TX_FIFO13      0x00200740
+#define DATA_IN_ENDPOINT_TX_FIFO14      0x00200760
+#define DATA_IN_ENDPOINT_TX_FIFO15      0x00200F00
+
+/*DWC_OTG regsiter descriptor*/
+/*Device mode CSR MAP*/
+#define DEVICE_CSR_BASE                 0x800
+/*Device mode CSR MAP*/
+#define DEVICE_INEP_BASE                0x900
+/*Device mode CSR MAP*/
+#define DEVICE_OUTEP_BASE               0xB00
+
+/*** OTG LINK CORE REGISTERS ***/
+/* Core Global Registers */
+#define GOTGCTL                         0x000
+#define GOTGINT                         0x004
+#define GAHBCFG                         0x008
+#define GAHBCFG_P_TXF_EMP_LVL           (1 << 8)
+#define GAHBCFG_NP_TXF_EMP_LVL          (1 << 7)
+#define GAHBCFG_DMA_EN                  (1 << 5)
+#define GAHBCFG_GLBL_INTR_EN            (1 << 0)
+#define GAHBCFG_CTRL_MASK               (GAHBCFG_P_TXF_EMP_LVL | \
+                                         GAHBCFG_NP_TXF_EMP_LVL | \
+                                         GAHBCFG_DMA_EN | \
+                                         GAHBCFG_GLBL_INTR_EN)
+
+#define GUSBCFG                         0x00C
+#define GRSTCTL                         0x010
+#define GRSTCTL_AHBIDLE                 (1 << 31)
+#define GRSTCTL_CSFTRST                 (1 << 0)
+
+#define GINTSTS                         0x014
+#define GINTSTS_WKUPINT                 BIT31
+#define GINTSTS_SESSREGINT              BIT30
+#define GINTSTS_DISCONNINT              BIT29
+#define GINTSTS_CONIDSTSCHNG            BIT28
+#define GINTSTS_LPMTRANRCVD             BIT27
+#define GINTSTS_PTXFEMP                 BIT26
+#define GINTSTS_HCHINT                  BIT25
+#define GINTSTS_PRTINT                  BIT24
+#define GINTSTS_RESETDET                BIT23
+#define GINTSTS_FET_SUSP                BIT22
+#define GINTSTS_INCOMPL_IP              BIT21
+#define GINTSTS_INCOMPL_SOIN            BIT20
+#define GINTSTS_OEPINT                  BIT19
+#define GINTSTS_IEPINT                  BIT18
+#define GINTSTS_EPMIS                   BIT17
+#define GINTSTS_RESTOREDONE             BIT16
+#define GINTSTS_EOPF                    BIT15
+#define GINTSTS_ISOUTDROP               BIT14
+#define GINTSTS_ENUMDONE                BIT13
+#define GINTSTS_USBRST                  BIT12
+#define GINTSTS_USBSUSP                 BIT11
+#define GINTSTS_ERLYSUSP                BIT10
+#define GINTSTS_I2CINT                  BIT9
+#define GINTSTS_ULPI_CK_INT             BIT8
+#define GINTSTS_GOUTNAKEFF              BIT7
+#define GINTSTS_GINNAKEFF               BIT6
+#define GINTSTS_NPTXFEMP                BIT5
+#define GINTSTS_RXFLVL                  BIT4
+#define GINTSTS_SOF                     BIT3
+#define GINTSTS_OTGINT                  BIT2
+#define GINTSTS_MODEMIS                 BIT1
+#define GINTSTS_CURMODE_HOST            BIT0
+
+#define GINTMSK                         0x018
+#define GRXSTSR                         0x01C
+#define GRXSTSP                         0x020
+#define GRXFSIZ                         0x024
+#define GNPTXFSIZ                       0x028
+#define GNPTXSTS                        0x02C
+
+#define GHWCFG1                         0x044
+#define GHWCFG2                         0x048
+#define GHWCFG3                         0x04c
+#define GHWCFG4                         0x050
+#define GLPMCFG                         0x054
+
+#define GDFIFOCFG                       0x05c
+
+#define HPTXFSIZ                        0x100
+#define DIEPTXF(x)                      (0x100 + 4 * (x))
+#define DIEPTXF1                        0x104
+#define DIEPTXF2                        0x108
+#define DIEPTXF3                        0x10C
+#define DIEPTXF4                        0x110
+#define DIEPTXF5                        0x114
+#define DIEPTXF6                        0x118
+#define DIEPTXF7                        0x11C
+#define DIEPTXF8                        0x120
+#define DIEPTXF9                        0x124
+#define DIEPTXF10                       0x128
+#define DIEPTXF11                       0x12C
+#define DIEPTXF12                       0x130
+#define DIEPTXF13                       0x134
+#define DIEPTXF14                       0x138
+#define DIEPTXF15                       0x13C
+
+/*** HOST MODE REGISTERS ***/
+/* Host Global Registers */
+#define HCFG                            0x400
+#define HFIR                            0x404
+#define HFNUM                           0x408
+#define HPTXSTS                         0x410
+#define HAINT                           0x414
+#define HAINTMSK                        0x418
+
+/* Host Port Control and Status Registers */
+#define HPRT                            0x440
+
+/* Host Channel-Specific Registers */
+#define HCCHAR(x)                       (0x500 + 0x20 * (x))
+#define HCSPLT(x)                       (0x504 + 0x20 * (x))
+#define HCINT(x)                        (0x508 + 0x20 * (x))
+#define HCINTMSK(x)                     (0x50C + 0x20 * (x))
+#define HCTSIZ(x)                       (0x510 + 0x20 * (x))
+#define HCDMA(x)                        (0x514 + 0x20 * (x))
+#define HCCHAR0                         0x500
+#define HCSPLT0                         0x504
+#define HCINT0                          0x508
+#define HCINTMSK0                       0x50C
+#define HCTSIZ0                         0x510
+#define HCDMA0                          0x514
+#define HCCHAR1                         0x520
+#define HCSPLT1                         0x524
+#define HCINT1                          0x528
+#define HCINTMSK1                       0x52C
+#define HCTSIZ1                         0x530
+#define HCDMA1                          0x534
+#define HCCHAR2                         0x540
+#define HCSPLT2                         0x544
+#define HCINT2                          0x548
+#define HCINTMSK2                       0x54C
+#define HCTSIZ2                         0x550
+#define HCDMA2                          0x554
+#define HCCHAR3                         0x560
+#define HCSPLT3                         0x564
+#define HCINT3                          0x568
+#define HCINTMSK3                       0x56C
+#define HCTSIZ3                         0x570
+#define HCDMA3                          0x574
+#define HCCHAR4                         0x580
+#define HCSPLT4                         0x584
+#define HCINT4                          0x588
+#define HCINTMSK4                       0x58C
+#define HCTSIZ4                         0x590
+#define HCDMA4                          0x594
+#define HCCHAR5                         0x5A0
+#define HCSPLT5                         0x5A4
+#define HCINT5                          0x5A8
+#define HCINTMSK5                       0x5AC
+#define HCTSIZ5                         0x5B0
+#define HCDMA5                          0x5B4
+#define HCCHAR6                         0x5C0
+#define HCSPLT6                         0x5C4
+#define HCINT6                          0x5C8
+#define HCINTMSK6                       0x5CC
+#define HCTSIZ6                         0x5D0
+#define HCDMA6                          0x5D4
+#define HCCHAR7                         0x5E0
+#define HCSPLT7                         0x5E4
+#define HCINT7                          0x5E8
+#define HCINTMSK7                       0x5EC
+#define HCTSIZ7                         0x5F0
+#define HCDMA7                          0x5F4
+#define HCCHAR8                         0x600
+#define HCSPLT8                         0x604
+#define HCINT8                          0x608
+#define HCINTMSK8                       0x60C
+#define HCTSIZ8                         0x610
+#define HCDMA8                          0x614
+#define HCCHAR9                         0x620
+#define HCSPLT9                         0x624
+#define HCINT9                          0x628
+#define HCINTMSK9                       0x62C
+#define HCTSIZ9                         0x630
+#define HCDMA9                          0x634
+#define HCCHAR10                        0x640
+#define HCSPLT10                        0x644
+#define HCINT10                         0x648
+#define HCINTMSK10                      0x64C
+#define HCTSIZ10                        0x650
+#define HCDMA10                         0x654
+#define HCCHAR11                        0x660
+#define HCSPLT11                        0x664
+#define HCINT11                         0x668
+#define HCINTMSK11                      0x66C
+#define HCTSIZ11                        0x670
+#define HCDMA11                         0x674
+#define HCCHAR12                        0x680
+#define HCSPLT12                        0x684
+#define HCINT12                         0x688
+#define HCINTMSK12                      0x68C
+#define HCTSIZ12                        0x690
+#define HCDMA12                         0x694
+#define HCCHAR13                        0x6A0
+#define HCSPLT13                        0x6A4
+#define HCINT13                         0x6A8
+#define HCINTMSK13                      0x6AC
+#define HCTSIZ13                        0x6B0
+#define HCDMA13                         0x6B4
+#define HCCHAR14                        0x6C0
+#define HCSPLT14                        0x6C4
+#define HCINT14                         0x6C8
+#define HCINTMSK14                      0x6CC
+#define HCTSIZ14                        0x6D0
+#define HCDMA14                         0x6D4
+#define HCCHAR15                        0x6E0
+#define HCSPLT15                        0x6E4
+#define HCINT15                         0x6E8
+#define HCINTMSK15                      0x6EC
+#define HCTSIZ15                        0x6F0
+#define HCDMA15                         0x6F4
+
+/*** DEVICE MODE REGISTERS ***/
+/* Device Global Registers */
+#define DCFG                            0x800
+#define DCFG_DESCDMA                    BIT23
+#define DCFG_EPMISCNT_MASK              (0x1F << 18)
+#define DCFG_EPMISCNT_SHIFT             18
+#define DCFG_DEVADDR_MASK               (0x7F << 4)
+#define DCFG_DEVADDR_SHIFT              4
+#define DCFG_DEVADDR(x)                 (((x) << DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK)
+#define DCFG_NZ_STS_OUT_HSHK            BIT2
+
+#define DCTL                            0x804
+#define DCTL_PWRONPRGDONE               BIT11
+#define DCTL_GNPINNAKSTS                BIT2
+#define DCTL_SFTDISCON                  BIT1
+
+#define DSTS                            0x808
+#define DIEPMSK                         0x810
+#define DOEPMSK                         0x814
+
+#define DXEPMSK_TIMEOUTMSK              BIT3
+#define DXEPMSK_AHBERMSK                BIT2
+#define DXEPMSK_XFERCOMPLMSK            BIT0
+
+#define DAINT                           0x818
+#define DAINTMSK                        0x81C
+
+#define DAINTMSK_OUTEPMSK_SHIFT         16
+#define DAINTMSK_INEPMSK_SHIFT          0
+
+#define DTKNQR1                         0x820
+#define DTKNQR2                         0x824
+#define DVBUSDIS                        0x828
+#define DVBUSPULSE                      0x82C
+#define DTHRCTL                         0x830
+
+/* Device Logical IN Endpoint-Specific Registers */
+#define DIEPCTL(x)                      (0x900 + 0x20 * (x))
+#define DIEPINT(x)                      (0x908 + 0x20 * (x))
+#define DIEPTSIZ(x)                     (0x910 + 0x20 * (x))
+#define DIEPDMA(x)                      (0x914 + 0x20 * (x))
+#define DTXFSTS(x)                      (0x918 + 0x20 * (x))
+
+#define DIEPCTL0                        0x900
+#define DIEPINT0                        0x908
+#define DIEPTSIZ0                       0x910
+#define DIEPDMA0                        0x914
+#define DIEPCTL1                        0x920
+#define DIEPINT1                        0x928
+#define DIEPTSIZ1                       0x930
+#define DIEPDMA1                        0x934
+#define DIEPCTL2                        0x940
+#define DIEPINT2                        0x948
+#define DIEPTSIZ2                       0x950
+#define DIEPDMA2                        0x954
+#define DIEPCTL3                        0x960
+#define DIEPINT3                        0x968
+#define DIEPTSIZ3                       0x970
+#define DIEPDMA3                        0x974
+#define DIEPCTL4                        0x980
+#define DIEPINT4                        0x988
+#define DIEPTSIZ4                       0x990
+#define DIEPDMA4                        0x994
+#define DIEPCTL5                        0x9A0
+#define DIEPINT5                        0x9A8
+#define DIEPTSIZ5                       0x9B0
+#define DIEPDMA5                        0x9B4
+#define DIEPCTL6                        0x9C0
+#define DIEPINT6                        0x9C8
+#define DIEPTSIZ6                       0x9D0
+#define DIEPDMA6                        0x9D4
+#define DIEPCTL7                        0x9E0
+#define DIEPINT7                        0x9E8
+#define DIEPTSIZ7                       0x9F0
+#define DIEPDMA7                        0x9F4
+#define DIEPCTL8                        0xA00
+#define DIEPINT8                        0xA08
+#define DIEPTSIZ8                       0xA10
+#define DIEPDMA8                        0xA14
+#define DIEPCTL9                        0xA20
+#define DIEPINT9                        0xA28
+#define DIEPTSIZ9                       0xA30
+#define DIEPDMA9                        0xA34
+#define DIEPCTL10                       0xA40
+#define DIEPINT10                       0xA48
+#define DIEPTSIZ10                      0xA50
+#define DIEPDMA10                       0xA54
+#define DIEPCTL11                       0xA60
+#define DIEPINT11                       0xA68
+#define DIEPTSIZ11                      0xA70
+#define DIEPDMA11                       0xA74
+#define DIEPCTL12                       0xA80
+#define DIEPINT12                       0xA88
+#define DIEPTSIZ12                      0xA90
+#define DIEPDMA12                       0xA94
+#define DIEPCTL13                       0xAA0
+#define DIEPINT13                       0xAA8
+#define DIEPTSIZ13                      0xAB0
+#define DIEPDMA13                       0xAB4
+#define DIEPCTL14                       0xAC0
+#define DIEPINT14                       0xAC8
+#define DIEPTSIZ14                      0xAD0
+#define DIEPDMA14                       0xAD4
+#define DIEPCTL15                       0xAE0
+#define DIEPINT15                       0xAE8
+#define DIEPTSIZ15                      0xAF0
+#define DIEPDMA15                       0xAF4
+
+/* Device Logical OUT Endpoint-Specific Registers */
+#define DOEPCTL(x)                      (0xB00 + 0x20 * (x))
+#define DOEPINT(x)                      (0xB08 + 0x20 * (x))
+#define DOEPTSIZ(x)                     (0xB10 + 0x20 * (x))
+
+#define DXEPINT_EPDISBLD                BIT1
+#define DXEPINT_XFERCOMPL               BIT0
+
+#define DXEPTSIZ_SUPCNT(x)              (((x) & 0x3) << 29)
+#define DXEPTSIZ_PKTCNT(x)              (((x) & 0x3) << 19)
+#define DXEPTSIZ_XFERSIZE(x)            ((x) & 0x7F)
+
+#define DOEPDMA(x)                      (0xB14 + 0x20 * (x))
+#define DOEPCTL0                        0xB00
+#define DOEPINT0                        0xB08
+#define DOEPTSIZ0                       0xB10
+#define DOEPDMA0                        0xB14
+#define DOEPCTL1                        0xB20
+#define DOEPINT1                        0xB28
+#define DOEPTSIZ1                       0xB30
+#define DOEPDMA1                        0xB34
+#define DOEPCTL2                        0xB40
+#define DOEPINT2                        0xB48
+#define DOEPTSIZ2                       0xB50
+#define DOEPDMA2                        0xB54
+#define DOEPCTL3                        0xB60
+#define DOEPINT3                        0xB68
+#define DOEPTSIZ3                       0xB70
+#define DOEPDMA3                        0xB74
+#define DOEPCTL4                        0xB80
+#define DOEPINT4                        0xB88
+#define DOEPTSIZ4                       0xB90
+#define DOEPDMA4                        0xB94
+#define DOEPCTL5                        0xBA0
+#define DOEPINT5                        0xBA8
+#define DOEPTSIZ5                       0xBB0
+#define DOEPDMA5                        0xBB4
+#define DOEPCTL6                        0xBC0
+#define DOEPINT6                        0xBC8
+#define DOEPTSIZ6                       0xBD0
+#define DOEPDMA6                        0xBD4
+#define DOEPCTL7                        0xBE0
+#define DOEPINT7                        0xBE8
+#define DOEPTSIZ7                       0xBF0
+#define DOEPDMA7                        0xBF4
+#define DOEPCTL8                        0xC00
+#define DOEPINT8                        0xC08
+#define DOEPTSIZ8                       0xC10
+#define DOEPDMA8                        0xC14
+#define DOEPCTL9                        0xC20
+#define DOEPINT9                        0xC28
+#define DOEPTSIZ9                       0xC30
+#define DOEPDMA9                        0xC34
+#define DOEPCTL10                       0xC40
+#define DOEPINT10                       0xC48
+#define DOEPTSIZ10                      0xC50
+#define DOEPDMA10                       0xC54
+#define DOEPCTL11                       0xC60
+#define DOEPINT11                       0xC68
+#define DOEPTSIZ11                      0xC70
+#define DOEPDMA11                       0xC74
+#define DOEPCTL12                       0xC80
+#define DOEPINT12                       0xC88
+#define DOEPTSIZ12                      0xC90
+#define DOEPDMA12                       0xC94
+#define DOEPCTL13                       0xCA0
+#define DOEPINT13                       0xCA8
+#define DOEPTSIZ13                      0xCB0
+#define DOEPDMA13                       0xCB4
+#define DOEPCTL14                       0xCC0
+#define DOEPINT14                       0xCC8
+#define DOEPTSIZ14                      0xCD0
+#define DOEPDMA14                       0xCD4
+#define DOEPCTL15                       0xCE0
+#define DOEPINT15                       0xCE8
+#define DOEPTSIZ15                      0xCF0
+#define DOEPDMA15                       0xCF4
+
+#define DXEPCTL_EPENA                   BIT31
+#define DXEPCTL_SNAK                    BIT27
+#define DXEPCTL_CNAK                    BIT26
+#define DXEPCTL_STALL                   BIT21
+#define DXEPCTL_EPTYPE_MASK             (BIT19 | BIT18)
+#define DXEPCTL_NAKSTS                  BIT17
+#define DXEPCTL_USBACTEP                BIT15
+#define DXEPCTL_MPS_MASK                0x7FF
+
+/* Power and Clock Gating Register */
+#define PCGCCTL                         0xE00
+
+#define EP0FIFO                         0x1000
+
+/**
+ * This union represents the bit fields in the DMA Descriptor
+ * status quadlet. Read the quadlet into the <i>d32</i> member then
+ * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
+ * <i>b_iso_in</i> elements.
+ */
+typedef union {
+  /** raw register data */
+  UINT32 d32;
+    /** quadlet bits */
+  struct {
+    /** Received number of bytes */
+    unsigned bytes:16;
+    /** NAK bit - only for OUT EPs */
+    unsigned nak:1;
+    unsigned reserved17_22:6;
+    /** Multiple Transfer - only for OUT EPs */
+    unsigned mtrf:1;
+    /** Setup Packet received - only for OUT EPs */
+    unsigned sr:1;
+    /** Interrupt On Complete */
+    unsigned ioc:1;
+    /** Short Packet */
+    unsigned sp:1;
+    /** Last */
+    unsigned l:1;
+    /** Receive Status */
+    unsigned sts:2;
+    /** Buffer Status */
+    unsigned bs:2;
+  } b;
+} dev_dma_desc_sts_t;
+
+/**
+ * DMA Descriptor structure
+ *
+ * DMA Descriptor structure contains two quadlets:
+ * Status quadlet and Data buffer pointer.
+ */
+typedef struct {
+  /** DMA Descriptor status quadlet */
+  dev_dma_desc_sts_t status;
+  /** DMA Descriptor data buffer pointer */
+  UINT32 buf;
+} dwc_otg_dev_dma_desc_t;
+
+#endif //ifndef __DW_USB_DXE_H__
diff --git a/Drivers/Usb/DwUsbDxe/DwUsbDxe.inf b/Drivers/Usb/DwUsbDxe/DwUsbDxe.inf
index 6659aef..fc1e988 100644
--- a/Drivers/Usb/DwUsbDxe/DwUsbDxe.inf
+++ b/Drivers/Usb/DwUsbDxe/DwUsbDxe.inf
@@ -1,52 +1,52 @@
-#/** @file
-#
-#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = DwUsbDxe
-  FILE_GUID                      = 72d78ea6-4dee-11e3-8100-f3842a48d0a0
-  MODULE_TYPE                    = UEFI_DRIVER
-  VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = DwUsbEntryPoint
-
-[Sources.common]
-  DwUsbDxe.c
-
-[LibraryClasses]
-  DebugLib
-  IoLib
-  MemoryAllocationLib
-  TimerLib
-  UefiBootServicesTableLib
-  UefiDriverEntryPoint
-  UncachedMemoryAllocationLib
-  CacheMaintenanceLib
-
-[Protocols]
-  gEfiDriverBindingProtocolGuid
-  gUsbDeviceProtocolGuid
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec
-
-[Pcd]
-  gDwUsbDxeTokenSpaceGuid.PcdDwUsbDxeBaseAddress
-
-[Depex]
-  BEFORE gAndroidFastbootUsbGuid
+#/** @file
+#
+#  Copyright (c) 2015-2017, Linaro. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = DwUsbDxe
+  FILE_GUID                      = 72d78ea6-4dee-11e3-8100-f3842a48d0a0
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = DwUsbEntryPoint
+
+[Sources.common]
+  DwUsbDxe.c
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+  IoLib
+  MemoryAllocationLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UncachedMemoryAllocationLib
+  CacheMaintenanceLib
+
+[Protocols]
+  gEfiDriverBindingProtocolGuid
+  gUsbDeviceProtocolGuid
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec
+
+[Pcd]
+  gDwUsbDxeTokenSpaceGuid.PcdDwUsbDxeBaseAddress
+
+[Depex]
+  BEFORE gAndroidFastbootUsbGuid
diff --git a/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.c b/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.c
deleted file mode 100644
index 80abdcf..0000000
--- a/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.c
+++ /dev/null
@@ -1,1158 +0,0 @@
-/** @file
-
-  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "DwUsbHostDxe.h"
-#include "DwcHw.h"
-
-EFI_USB_PCIIO_DEVICE_PATH DwHcDevicePath =
-{
-  {
-    { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },
-    EISA_PNP_ID(0x0A03),  // HID
-    0                     // UID
-  },
-  {
-    { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },
-    0,
-    0
-  },
-  { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }
-};
-
-VOID DwHcInit (IN DWUSB_OTGHC_DEV *DwHc);
-VOID DwCoreInit (IN DWUSB_OTGHC_DEV *DwHc);
-
-STATIC DW_USB_PROTOCOL          *DwUsb;
-
-UINT32
-Wait4Bit (
-  IN UINT32     Reg,
-  IN UINT32     Mask,
-  IN BOOLEAN    Set
-  )
-{
-        UINT32  Timeout = 1000000;
-        UINT32  Value;
-
-        while (--Timeout) {
-                Value = MmioRead32 (Reg);
-                if (!Set)
-                        Value = ~Value;
-
-                if ((Value & Mask) == Mask)
-                        return 0;
-
-                MicroSecondDelay (1);
-        }
-
-        DEBUG ((EFI_D_ERROR, "Wait4Bit: Timeout (Reg:0x%x, mask:0x%x, wait_set:%d)\n", Reg, Mask, Set));
-
-        return 1;
-}
-
-UINT32
-Wait4Chhltd (
-  IN DWUSB_OTGHC_DEV	*DwHc,
-  IN UINT32		*Sub,
-  IN UINT32		*Toggle,
-  IN BOOLEAN		IgnoreAck
-  )
-{
-	UINT32	HcintCompHltAck = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
-	INT32	Ret;
-	UINT32	Hcint, Hctsiz;
-
-	MicroSecondDelay (100);
-	Ret = Wait4Bit (DwHc->DwUsbBase + HCINT(DWC2_HC_CHANNEL), DWC2_HCINT_CHHLTD, 1);
-	if (Ret)
-		return Ret;
-
-	MicroSecondDelay (100);
-	Hcint = MmioRead32 (DwHc->DwUsbBase + HCINT(DWC2_HC_CHANNEL));
-	if (Hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) {
-		DEBUG ((EFI_D_INFO, "Wait4Chhltd: ERROR\n"));
-		return 1;
-	}
-
-	if (IgnoreAck)
-		Hcint &= ~DWC2_HCINT_ACK;
-	else
-		HcintCompHltAck |= DWC2_HCINT_ACK;
-
-	if (Hcint != HcintCompHltAck) {
-		DEBUG ((EFI_D_ERROR, "Wait4Chhltd: HCINT Error 0x%x\n", Hcint));
-		return 1;
-	}
-
-	Hctsiz = MmioRead32 (DwHc->DwUsbBase + HCTSIZ(DWC2_HC_CHANNEL));
-	*Sub = (Hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> DWC2_HCTSIZ_XFERSIZE_OFFSET;
-	*Toggle = (Hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
-
-	return 0;
-}
-
-VOID
-DwOtgHcInit (
-  IN DWUSB_OTGHC_DEV	*DwHc,
-  IN UINT8		HcNum,
-  IN UINT8		DevAddr,
-  IN UINT8		Endpoint,
-  IN UINT8		EpDir,
-  IN UINT8		EpType,
-  IN UINT16		MaxPacket
-  )
-{
-	UINT32	Hcchar = (DevAddr << DWC2_HCCHAR_DEVADDR_OFFSET) |
-			(Endpoint << DWC2_HCCHAR_EPNUM_OFFSET) |
-			(EpDir << DWC2_HCCHAR_EPDIR_OFFSET) |
-			(EpType << DWC2_HCCHAR_EPTYPE_OFFSET) |
-			(MaxPacket << DWC2_HCCHAR_MPS_OFFSET);
-
-	MmioWrite32 (DwHc->DwUsbBase + HCINT(HcNum), 0x3FFF);
-
-	MmioWrite32 (DwHc->DwUsbBase + HCCHAR(HcNum), Hcchar);
-
-	MmioWrite32 (DwHc->DwUsbBase + HCSPLT(HcNum), 0);
-}
-
-VOID
-DwCoreReset (
-  IN DWUSB_OTGHC_DEV *DwHc
-  )
-{
-        UINT32  Status;
-
-        Status = Wait4Bit (DwHc->DwUsbBase + GRSTCTL, DWC2_GRSTCTL_AHBIDLE, 1);
-        if (Status)
-                DEBUG ((EFI_D_ERROR, "DwCoreReset: Timeout!\n"));
-
-        MmioWrite32 (DwHc->DwUsbBase + GRSTCTL, DWC2_GRSTCTL_CSFTRST);
-
-        Status = Wait4Bit (DwHc->DwUsbBase + GRSTCTL, DWC2_GRSTCTL_CSFTRST, 0);
-        if (Status)
-                DEBUG ((EFI_D_ERROR, "DwCoreReset: Timeout!\n"));
-
-        MicroSecondDelay (100000);
-}
-
-EFI_STATUS
-DwHcTransfer (
-  IN     DWUSB_OTGHC_DEV	*DwHc,
-  IN     UINT8			DeviceAddress,
-  IN     UINTN			MaximumPacketLength,
-  IN OUT UINT32			*Pid,
-  IN     UINT32			TransferDirection,
-  IN OUT VOID			*Data,
-  IN OUT UINTN			*DataLength,
-  IN     UINT32			EpAddress,
-  IN     UINT32			EpType,
-  OUT    UINT32			*TransferResult,
-  IN     BOOLEAN		IgnoreAck
-  )
-{
-        UINT32                          TxferLen;
-        UINT32                          Done = 0;
-        UINT32                          NumPackets;
-        UINT32                          Sub;
-        UINT32                          Ret = 0;
-        UINT32                          StopTransfer = 0;
-        EFI_STATUS                      Status = EFI_SUCCESS;
-
-        do {
-                DwOtgHcInit (DwHc, DWC2_HC_CHANNEL, DeviceAddress, EpAddress, TransferDirection, EpType, MaximumPacketLength);
-
-                TxferLen = *DataLength - Done;
-                if (TxferLen > DWC2_MAX_TRANSFER_SIZE)
-                        TxferLen = DWC2_MAX_TRANSFER_SIZE - MaximumPacketLength + 1;
-                if (TxferLen > DWC2_DATA_BUF_SIZE)
-                        TxferLen = DWC2_DATA_BUF_SIZE - MaximumPacketLength + 1;
-
-                if (TxferLen > 0) {
-                        NumPackets = (TxferLen + MaximumPacketLength - 1) / MaximumPacketLength;
-                        if (NumPackets > DWC2_MAX_PACKET_COUNT) {
-                                NumPackets = DWC2_MAX_PACKET_COUNT;
-                                TxferLen = NumPackets * MaximumPacketLength;
-                        }
-                } else {
-                        NumPackets = 1;
-                }
-
-                if (TransferDirection)
-	                TxferLen = NumPackets * MaximumPacketLength;
-
-                MmioWrite32 (DwHc->DwUsbBase + HCTSIZ(DWC2_HC_CHANNEL), (TxferLen << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
-                                                        (NumPackets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
-                                                        (*Pid << DWC2_HCTSIZ_PID_OFFSET));
-
-		if (!TransferDirection) {
-			CopyMem (DwHc->AlignedBuffer, Data+Done, *DataLength);
-		}
-
-                MmioWrite32 (DwHc->DwUsbBase + HCDMA(DWC2_HC_CHANNEL), (UINTN)DwHc->AlignedBuffer);
-
-                MmioAndThenOr32 (DwHc->DwUsbBase + HCCHAR(DWC2_HC_CHANNEL), ~(DWC2_HCCHAR_MULTICNT_MASK |
-                                                                                DWC2_HCCHAR_CHEN |
-										DWC2_HCCHAR_CHDIS),
-									     ((1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
-										DWC2_HCCHAR_CHEN));
-
-                Ret = Wait4Chhltd (DwHc, &Sub, Pid, IgnoreAck);
-                if (Ret) {
-                        *TransferResult = EFI_USB_ERR_STALL;
-                        Status = EFI_DEVICE_ERROR;
-                        break;
-                }
-
-		if (TransferDirection) {
-	                TxferLen -= Sub;
-	                CopyMem (Data+Done, DwHc->AlignedBuffer, TxferLen);
-	                if (Sub)
-		                StopTransfer = 1;
-		}
-
-                Done += TxferLen;
-        } while (Done < *DataLength && !StopTransfer);
-
-        MmioWrite32 (DwHc->DwUsbBase + HCINTMSK(DWC2_HC_CHANNEL), 0);
-        MmioWrite32 (DwHc->DwUsbBase + HCINT(DWC2_HC_CHANNEL), 0xFFFFFFFF);
-
-	*DataLength = Done;
-
-        return Status;
-}
-
-/**
-EFI_USB2_HC_PROTOCOL APIs
-**/
-
-EFI_STATUS
-EFIAPI
-DwHcGetCapability (
-  IN  EFI_USB2_HC_PROTOCOL  *This,
-  OUT UINT8                 *MaxSpeed,
-  OUT UINT8                 *PortNumber,
-  OUT UINT8                 *Is64BitCapable
-  )
-{
-	if ((MaxSpeed == NULL) || (PortNumber == NULL) || (Is64BitCapable == NULL)) {
-		return EFI_INVALID_PARAMETER;
-	}
-
-	*MaxSpeed = EFI_USB_SPEED_HIGH;
-	*PortNumber = 1;
-	*Is64BitCapable = 1;
-
-	return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcReset (
-  IN EFI_USB2_HC_PROTOCOL *This,
-  IN UINT16               Attributes
-  )
-{
-	DWUSB_OTGHC_DEV	*DwHc;
-        EFI_STATUS       Status;
-        UINT8            UsbMode;
-
-	DwHc = DWHC_FROM_THIS (This);
-
-        //Mode: 1 for device, 0 for Host
-        UsbMode = USB_HOST_MODE;
-        Status = DwUsb->PhyInit(UsbMode);
-        if (EFI_ERROR(Status)) {
-           return Status;
-        }
-
-        DwCoreInit(DwHc);
-        DwHcInit(DwHc);
-
-        MmioAndThenOr32 (DwHc->DwUsbBase + HPRT0,
-                                ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-                                  DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG),
-                                  DWC2_HPRT0_PRTRST);
-
-        MicroSecondDelay (50000);
-
-        MmioAnd32 (DwHc->DwUsbBase + HPRT0, ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-                                                DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
-                                                DWC2_HPRT0_PRTRST));
-
-	return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcGetState (
-  IN   EFI_USB2_HC_PROTOCOL  *This,
-  OUT  EFI_USB_HC_STATE      *State
-  )
-{
-	DWUSB_OTGHC_DEV	*DwHc;
-
-	DwHc = DWHC_FROM_THIS (This);
-
-	*State = DwHc->DwHcState;
-
-	return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcSetState (
-  IN EFI_USB2_HC_PROTOCOL *This,
-  IN EFI_USB_HC_STATE     State
-  )
-{
-	DWUSB_OTGHC_DEV *DwHc;
-
-	DwHc = DWHC_FROM_THIS (This);
-
-	DwHc->DwHcState = State;
-
-	return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcGetRootHubPortStatus (
-  IN   EFI_USB2_HC_PROTOCOL  *This,
-  IN   UINT8                 PortNumber,
-  OUT  EFI_USB_PORT_STATUS   *PortStatus
-  )
-{
-	DWUSB_OTGHC_DEV	*DwHc;
-	UINT32		Hprt0;
-
-        if (PortNumber > DWC2_HC_CHANNEL)
-                return EFI_INVALID_PARAMETER;
-
-	if (PortStatus == NULL)
-		return EFI_INVALID_PARAMETER;
-
-	DwHc = DWHC_FROM_THIS (This);
-
-	PortStatus->PortStatus = 0;
-	PortStatus->PortChangeStatus = 0;
-	Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-
-	if (Hprt0 & DWC2_HPRT0_PRTCONNSTS) {
-		PortStatus->PortStatus |= USB_PORT_STAT_CONNECTION;
-	}
-
-	if (Hprt0 & DWC2_HPRT0_PRTENA) {
-		PortStatus->PortStatus |= USB_PORT_STAT_ENABLE;
-	}
-
-	if (Hprt0 & DWC2_HPRT0_PRTSUSP) {
-		PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND;
-	}
-
-	if (Hprt0 & DWC2_HPRT0_PRTOVRCURRACT) {
-		PortStatus->PortStatus |= USB_PORT_STAT_OVERCURRENT;
-	}
-
-	if (Hprt0 & DWC2_HPRT0_PRTRST) {
-		PortStatus->PortStatus |= USB_PORT_STAT_RESET;
-	}
-
-	if (Hprt0 & DWC2_HPRT0_PRTPWR) {
-		PortStatus->PortStatus |= USB_PORT_STAT_POWER;
-	}
-
-	PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
-
-	if (Hprt0 & DWC2_HPRT0_PRTENCHNG) {
-//		PortStatus->PortChangeStatus |= USB_PORT_STAT_C_ENABLE;
-	}
-
-	if (Hprt0 & DWC2_HPRT0_PRTCONNDET) {
-		PortStatus->PortChangeStatus |= USB_PORT_STAT_C_CONNECTION;
-	}
-
-	if (Hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) {
-		PortStatus->PortChangeStatus |= USB_PORT_STAT_C_OVERCURRENT;
-	}
-
-	return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcSetRootHubPortFeature (
-  IN  EFI_USB2_HC_PROTOCOL  *This,
-  IN  UINT8                 PortNumber,
-  IN  EFI_USB_PORT_FEATURE  PortFeature
-  )
-{
-	DWUSB_OTGHC_DEV		*DwHc;
-	UINT32			Hprt0;
-	EFI_STATUS		Status = EFI_SUCCESS;
-
-        if (PortNumber > DWC2_HC_CHANNEL) {
-                Status = EFI_INVALID_PARAMETER;
-                goto End;
-        }
-
-	DwHc = DWHC_FROM_THIS (This);
-
-	switch (PortFeature) {
-		case EfiUsbPortEnable:
-			break;
-		case EfiUsbPortSuspend:
-			Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-			Hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-					DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
-			Hprt0 |= DWC2_HPRT0_PRTSUSP;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			break;
-		case EfiUsbPortReset:
-                        MmioAndThenOr32 (DwHc->DwUsbBase + HPRT0,
-                                                ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-                                                DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG),
-                                                DWC2_HPRT0_PRTRST);
-                        MicroSecondDelay (50000);
-                        MmioAnd32 (DwHc->DwUsbBase + HPRT0, ~DWC2_HPRT0_PRTRST);
-			break;
-		case EfiUsbPortPower:
-			Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-			Hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-					DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
-			Hprt0 |= DWC2_HPRT0_PRTPWR;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			break;
-		case EfiUsbPortOwner:
-			break;
-		default:
-			Status = EFI_INVALID_PARAMETER;
-			break;
-	}
-
-End:
-	return Status;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcClearRootHubPortFeature (
-  IN  EFI_USB2_HC_PROTOCOL  *This,
-  IN  UINT8                 PortNumber,
-  IN  EFI_USB_PORT_FEATURE  PortFeature
-  )
-{
-	DWUSB_OTGHC_DEV		*DwHc;
-	UINT32			Hprt0;
-	EFI_STATUS		Status = EFI_SUCCESS;
-
-	if (PortNumber > DWC2_HC_CHANNEL) {
-		Status = EFI_INVALID_PARAMETER;
-		goto End;
-	}
-
-	DwHc = DWHC_FROM_THIS (This);
-
-	switch (PortFeature) {
-		case EfiUsbPortEnable:
-			Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-			Hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-					DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
-			Hprt0 |= DWC2_HPRT0_PRTENA;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			break;
-		case EfiUsbPortReset:
-			MmioAndThenOr32 (DwHc->DwUsbBase + HPRT0,
-						~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-						DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG),
-						DWC2_HPRT0_PRTRST);
-			MicroSecondDelay (50000);
-			MmioAnd32 (DwHc->DwUsbBase + HPRT0, ~DWC2_HPRT0_PRTRST);
-			break;
-		case EfiUsbPortSuspend:
-			MmioWrite32 (DwHc->DwUsbBase + PCGCCTL, 0);
-			MicroSecondDelay (40000);
-			Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-			Hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-					DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
-			Hprt0 |= DWC2_HPRT0_PRTRES;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			Hprt0 &= ~DWC2_HPRT0_PRTSUSP;
-			MicroSecondDelay (150000);
-			Hprt0 &= ~DWC2_HPRT0_PRTRES;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			break;
-		case EfiUsbPortPower:
-			Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-			Hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-					DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
-			Hprt0 &= ~DWC2_HPRT0_PRTPWR;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			break;
-		case EfiUsbPortOwner:
-			break;
-		case EfiUsbPortConnectChange:
-			Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-			Hprt0 &= ~DWC2_HPRT0_PRTCONNDET;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			break;
-		case EfiUsbPortResetChange:
-			break;
-		case EfiUsbPortEnableChange:
-			Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-			Hprt0 &= ~DWC2_HPRT0_PRTENCHNG;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			break;
-		case EfiUsbPortSuspendChange:
-			break;
-		case EfiUsbPortOverCurrentChange:
-			Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-			Hprt0 &= ~DWC2_HPRT0_PRTOVRCURRCHNG;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-			break;
-		default:
-			Status = EFI_INVALID_PARAMETER;
-			break;
-	}
-
-End:
-	return Status;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcControlTransfer (
-  IN  EFI_USB2_HC_PROTOCOL                *This,
-  IN  UINT8                               DeviceAddress,
-  IN  UINT8                               DeviceSpeed,
-  IN  UINTN                               MaximumPacketLength,
-  IN  EFI_USB_DEVICE_REQUEST              *Request,
-  IN  EFI_USB_DATA_DIRECTION              TransferDirection,
-  IN  OUT VOID                            *Data,
-  IN  OUT UINTN                           *DataLength,
-  IN  UINTN                               TimeOut,
-  IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
-  OUT UINT32                              *TransferResult
-  )
-{
-	DWUSB_OTGHC_DEV		*DwHc;
-	EFI_STATUS		Status;
-	UINT32			Pid;
-	UINTN			Length;
-	EFI_USB_DATA_DIRECTION	StatusDirection;
-	UINT32			Direction;
-
-	if ((Request == NULL) || (TransferResult == NULL)) {
-		return EFI_INVALID_PARAMETER;
-	}
-
-	if ((TransferDirection != EfiUsbDataIn) &&
-	    (TransferDirection != EfiUsbDataOut) &&
-	    (TransferDirection != EfiUsbNoData)) {
-		return EFI_INVALID_PARAMETER;
-	}
-
-	if ((TransferDirection == EfiUsbNoData) &&
-	    ((Data != NULL) || (*DataLength != 0))) {
-		return EFI_INVALID_PARAMETER;
-	}
-
-        if ((TransferDirection != EfiUsbNoData) &&
-            ((Data == NULL) || (*DataLength == 0))) {
-                return EFI_INVALID_PARAMETER;
-        }
-
-	if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
-	    (MaximumPacketLength != 32) && (MaximumPacketLength != 64)) {
-		return EFI_INVALID_PARAMETER;
-	}
-
-	if ((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) {
-		return EFI_INVALID_PARAMETER;
-	}
-
-	DwHc  = DWHC_FROM_THIS(This);
-
-	*TransferResult = EFI_USB_ERR_SYSTEM;
-	Status		= EFI_DEVICE_ERROR;
-
-	Pid = DWC2_HC_PID_SETUP;
-	Length = 8;
-	Status = DwHcTransfer (DwHc, DeviceAddress, MaximumPacketLength, &Pid, 0, Request, &Length,
-					0, DWC2_HCCHAR_EPTYPE_CONTROL, TransferResult, 1);
-
-	if (EFI_ERROR(Status)) {
-		DEBUG ((EFI_D_ERROR, "DwHcControlTransfer: Setup Stage Error\n"));
-		goto EXIT;
-	}
-
-	if (Data) {
-		Pid = DWC2_HC_PID_DATA1;
-
-		if (TransferDirection == EfiUsbDataIn)
-			Direction = 1;
-		else
-			Direction = 0;
-
-		Status = DwHcTransfer (DwHc, DeviceAddress, MaximumPacketLength, &Pid, Direction,
-					Data, DataLength, 0, DWC2_HCCHAR_EPTYPE_CONTROL, TransferResult, 0);
-
-		if (EFI_ERROR(Status)) {
-			DEBUG ((EFI_D_ERROR, "DwHcControlTransfer: Data Stage Error\n"));
-			goto EXIT;
-		}
-	}
-
-	if ((TransferDirection == EfiUsbDataOut) || (TransferDirection == EfiUsbNoData))
-		StatusDirection = 1;
-	else
-		StatusDirection = 0;
-
-	Pid = DWC2_HC_PID_DATA1;
-	Length = 0;
-	Status = DwHcTransfer (DwHc, DeviceAddress, MaximumPacketLength, &Pid, StatusDirection, DwHc->StatusBuffer,
-				&Length, 0, DWC2_HCCHAR_EPTYPE_CONTROL, TransferResult, 0);
-
-	if (EFI_ERROR(Status)) {
-		DEBUG ((EFI_D_ERROR, "DwHcControlTransfer: Status Stage Error\n"));
-		goto EXIT;
-	}
-
-EXIT:
-	return Status;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcBulkTransfer (
-  IN  EFI_USB2_HC_PROTOCOL                *This,
-  IN  UINT8                               DeviceAddress,
-  IN  UINT8                               EndPointAddress,
-  IN  UINT8                               DeviceSpeed,
-  IN  UINTN                               MaximumPacketLength,
-  IN  UINT8                               DataBuffersNumber,
-  IN  OUT VOID                            *Data[EFI_USB_MAX_BULK_BUFFER_NUM],
-  IN  OUT UINTN                           *DataLength,
-  IN  OUT UINT8                           *DataToggle,
-  IN  UINTN                               TimeOut,
-  IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
-  OUT UINT32                              *TransferResult
-  )
-{
-	DWUSB_OTGHC_DEV		*DwHc;
-	EFI_STATUS		Status;
-	UINT8			TransferDirection;
-	UINT8			EpAddress;
-	UINT32			Pid;
-
-	if ((Data == NULL) || (Data[0] == NULL) ||
-		(DataLength == NULL) || (*DataLength == 0) ||
-		(TransferResult == NULL)) {
-			return EFI_INVALID_PARAMETER;
-	}
-
-	if ((*DataToggle != 0) && (*DataToggle != 1))
-		return EFI_INVALID_PARAMETER;
-
-	if ((DeviceSpeed == EFI_USB_SPEED_LOW) || (DeviceSpeed == EFI_USB_SPEED_SUPER))
-		return EFI_INVALID_PARAMETER;
-
-	if (((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
-		((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 512)))
-			return EFI_INVALID_PARAMETER;
-
-	DwHc = DWHC_FROM_THIS (This);
-
-	*TransferResult		= EFI_USB_ERR_SYSTEM;
-	Status			= EFI_DEVICE_ERROR;
-	TransferDirection	= (EndPointAddress >> 7) & 0x01;
-	EpAddress		= EndPointAddress & 0x0F;
-	Pid			= (*DataToggle << 1);
-
-	Status = DwHcTransfer (DwHc, DeviceAddress, MaximumPacketLength, &Pid, TransferDirection, Data[0], DataLength,
-				EpAddress, DWC2_HCCHAR_EPTYPE_BULK, TransferResult, 1);
-
-	*DataToggle = (Pid >> 1);
-
-	return Status;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcAsyncInterruptTransfer (
-  IN  EFI_USB2_HC_PROTOCOL                  *This,
-  IN  UINT8                                 DeviceAddress,
-  IN  UINT8                                 EndPointAddress,
-  IN  UINT8                                 DeviceSpeed,
-  IN  UINTN                                 MaximumPacketLength,
-  IN  BOOLEAN                               IsNewTransfer,
-  IN  OUT UINT8                             *DataToggle,
-  IN  UINTN                                 PollingInterval,
-  IN  UINTN                                 DataLength,
-  IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR    *Translator,
-  IN  EFI_ASYNC_USB_TRANSFER_CALLBACK       CallBackFunction,
-  IN  VOID                                  *Context OPTIONAL
-  )
-{
-        DWUSB_OTGHC_DEV                 *DwHc;
-        VOID                            *Data;
-	EFI_STATUS			Status;
-	UINT32				TransferResult;
-	UINT32				Pid;
-	UINT8				TransferDirection;
-	UINT8				EpAddress;
-
-	if (!(EndPointAddress & USB_ENDPOINT_DIR_IN))
-		return EFI_INVALID_PARAMETER;
-
-	if (IsNewTransfer) {
-		if (DataLength == 0)
-			return EFI_INVALID_PARAMETER;
-
-		if ((*DataToggle != 1) && (*DataToggle != 0))
-			return EFI_INVALID_PARAMETER;
-
-		if ((PollingInterval > 255) || (PollingInterval < 1))
-			return EFI_INVALID_PARAMETER;
-	}
-
-	DwHc = DWHC_FROM_THIS (This);
-
-	if (!IsNewTransfer)
-		return EFI_SUCCESS;
-
-        Data = AllocateZeroPool (DataLength);
-        if (Data == NULL) {
-                DEBUG ((EFI_D_ERROR, "DwHcAsyncInterruptTransfer: failed to allocate buffer\n"));
-                Status = EFI_OUT_OF_RESOURCES;
-                goto EXIT;
-        }
-
-	Status			= EFI_SUCCESS;
-	TransferResult		= EFI_USB_NOERROR;
-	EpAddress		= EndPointAddress & 0x0F;
-	TransferDirection	= (EndPointAddress >> 7) & 0x01;
-	Pid			= (*DataToggle << 1);
-
-
-	Status = DwHcTransfer (DwHc, DeviceAddress, MaximumPacketLength, &Pid, TransferDirection, Data, &DataLength,
-				EpAddress, DWC2_HCCHAR_EPTYPE_INTR, &TransferResult, 1);
-
-	*DataToggle = (Pid >> 1);
-
-	if (CallBackFunction != NULL)
-		CallBackFunction (Data, DataLength, Context, TransferResult);
-
-EXIT:
-	return Status;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcSyncInterruptTransfer (
-  IN  EFI_USB2_HC_PROTOCOL                *This,
-  IN  UINT8                               DeviceAddress,
-  IN  UINT8                               EndPointAddress,
-  IN  UINT8                               DeviceSpeed,
-  IN  UINTN                               MaximumPacketLength,
-  IN  OUT VOID                            *Data,
-  IN  OUT UINTN                           *DataLength,
-  IN  OUT UINT8                           *DataToggle,
-  IN  UINTN                               TimeOut,
-  IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
-  OUT UINT32                              *TransferResult
-  )
-{
-	return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcIsochronousTransfer (
-  IN  EFI_USB2_HC_PROTOCOL                *This,
-  IN  UINT8                               DeviceAddress,
-  IN  UINT8                               EndPointAddress,
-  IN  UINT8                               DeviceSpeed,
-  IN  UINTN                               MaximumPacketLength,
-  IN  UINT8                               DataBuffersNumber,
-  IN  OUT VOID                            *Data[EFI_USB_MAX_ISO_BUFFER_NUM],
-  IN  UINTN                               DataLength,
-  IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
-  OUT UINT32                              *TransferResult
-  )
-{
-	return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-EFIAPI
-DwHcAsyncIsochronousTransfer (
-  IN  EFI_USB2_HC_PROTOCOL                *This,
-  IN  UINT8                               DeviceAddress,
-  IN  UINT8                               EndPointAddress,
-  IN  UINT8                               DeviceSpeed,
-  IN  UINTN                               MaximumPacketLength,
-  IN  UINT8                               DataBuffersNumber,
-  IN  OUT VOID                            *Data[EFI_USB_MAX_ISO_BUFFER_NUM],
-  IN  UINTN                               DataLength,
-  IN  EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
-  IN  EFI_ASYNC_USB_TRANSFER_CALLBACK     IsochronousCallBack,
-  IN  VOID                                *Context
-  )
-{
-	return EFI_UNSUPPORTED;
-}
-
-/**
-Supported Functions
-**/
-
-VOID
-InitFslspClkSel (
-  IN DWUSB_OTGHC_DEV *DwHc
-  )
-{
-	UINT32	PhyClk;
-
-	PhyClk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
-
-	MmioAndThenOr32 (DwHc->DwUsbBase + HCFG,
-				~DWC2_HCFG_FSLSPCLKSEL_MASK,
-				PhyClk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
-}
-
-VOID
-DwFlushTxFifo (
-  IN DWUSB_OTGHC_DEV *DwHc,
-  IN INT32 Num
-  )
-{
-	UINT32 Status;
-
-	MmioWrite32 (DwHc->DwUsbBase + GRSTCTL, DWC2_GRSTCTL_TXFFLSH | (Num << DWC2_GRSTCTL_TXFNUM_OFFSET));
-
-	Status = Wait4Bit (DwHc->DwUsbBase + GRSTCTL, DWC2_GRSTCTL_TXFFLSH, 0);
-	if (Status)
-		DEBUG ((EFI_D_ERROR, "DwFlushTxFifo: Timeout!\n"));
-
-	MicroSecondDelay (1);
-}
-
-VOID
-DwFlushRxFifo (
-  IN DWUSB_OTGHC_DEV *DwHc
-  )
-{
-	UINT32 Status;
-
-	MmioWrite32 (DwHc->DwUsbBase + GRSTCTL, DWC2_GRSTCTL_RXFFLSH);
-
-	Status = Wait4Bit (DwHc->DwUsbBase + GRSTCTL, DWC2_GRSTCTL_RXFFLSH, 0);
-	if (Status)
-		DEBUG ((EFI_D_ERROR, "DwFlushRxFifo: Timeout!\n"));
-
-	MicroSecondDelay (1);
-}
-
-VOID
-DwHcInit (
-  IN DWUSB_OTGHC_DEV *DwHc
-  )
-{
-	UINT32 NpTxFifoSz = 0;
-	UINT32 pTxFifoSz = 0;
-	UINT32 Hprt0 = 0;
-	INT32  i, Status, NumChannels;
-
-	MmioWrite32 (DwHc->DwUsbBase + PCGCCTL, 0);
-
-	InitFslspClkSel (DwHc);
-
-	MmioWrite32 (DwHc->DwUsbBase + GRXFSIZ, DWC2_HOST_RX_FIFO_SIZE);
-
-	NpTxFifoSz |= DWC2_HOST_NPERIO_TX_FIFO_SIZE << DWC2_FIFOSIZE_DEPTH_OFFSET;
-	NpTxFifoSz |= DWC2_HOST_RX_FIFO_SIZE << DWC2_FIFOSIZE_STARTADDR_OFFSET;
-	MmioWrite32 (DwHc->DwUsbBase + GNPTXFSIZ, NpTxFifoSz);
-
-	pTxFifoSz |= DWC2_HOST_PERIO_TX_FIFO_SIZE << DWC2_FIFOSIZE_DEPTH_OFFSET;
-	pTxFifoSz |= (DWC2_HOST_RX_FIFO_SIZE + DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
-									DWC2_FIFOSIZE_STARTADDR_OFFSET;
-	MmioWrite32 (DwHc->DwUsbBase + HPTXFSIZ, pTxFifoSz);
-
-	MmioAnd32 (DwHc->DwUsbBase + GOTGCTL, ~(DWC2_GOTGCTL_HSTSETHNPEN));
-
-	DwFlushTxFifo (DwHc, 0x10);
-	DwFlushRxFifo (DwHc);
-
-	NumChannels = MmioRead32 (DwHc->DwUsbBase + GHWCFG2);
-	NumChannels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
-	NumChannels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
-	NumChannels += 1;
-
-	for (i=0; i<NumChannels; i++)
-		MmioAndThenOr32 (DwHc->DwUsbBase + HCCHAR(i),
-					~(DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR),
-					DWC2_HCCHAR_CHDIS);
-
-	for (i=0; i<NumChannels; i++) {
-		MmioAndThenOr32 (DwHc->DwUsbBase + HCCHAR(i),
-					~DWC2_HCCHAR_EPDIR,
-					(DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS));
-		Status = Wait4Bit (DwHc->DwUsbBase + HCCHAR(i), DWC2_HCCHAR_CHEN, 0);
-		if (Status)
-			DEBUG ((EFI_D_ERROR, "DwHcInit: Timeout!\n"));
-	}
-
-	if (MmioRead32 (DwHc->DwUsbBase + GINTSTS) & DWC2_GINTSTS_CURMODE_HOST) {
-		Hprt0 = MmioRead32 (DwHc->DwUsbBase + HPRT0);
-		Hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
-		Hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
-
-		if (!(Hprt0 & DWC2_HPRT0_PRTPWR)) {
-			Hprt0 |= DWC2_HPRT0_PRTPWR;
-			MmioWrite32 (DwHc->DwUsbBase + HPRT0, Hprt0);
-		}
-	}
-}
-
-VOID
-DwCoreInit (
-  IN DWUSB_OTGHC_DEV *DwHc
-  )
-{
-	UINT32		AhbCfg = 0;
-	UINT32		UsbCfg = 0;
-
-	UsbCfg = MmioRead32 (DwHc->DwUsbBase + GUSBCFG);
-
-	UsbCfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
-	UsbCfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
-
-	MmioWrite32 (DwHc->DwUsbBase + GUSBCFG, UsbCfg);
-
-	DwCoreReset (DwHc);
-
-	UsbCfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
-	UsbCfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
-
-	UsbCfg &= ~DWC2_GUSBCFG_DDRSEL;
-
-	MmioWrite32 (DwHc->DwUsbBase + GUSBCFG, UsbCfg);
-
-	DwCoreReset (DwHc);
-
-	UsbCfg = MmioRead32 (DwHc->DwUsbBase + GUSBCFG);
-	UsbCfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
-	MmioWrite32 (DwHc->DwUsbBase + GUSBCFG, UsbCfg);
-
-	AhbCfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
-	AhbCfg |= DWC2_GAHBCFG_DMAENABLE;
-
-	MmioWrite32 (DwHc->DwUsbBase + GAHBCFG, AhbCfg);
-	MmioOr32 (DwHc->DwUsbBase + GUSBCFG, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
-}
-
-DWUSB_OTGHC_DEV *
-CreateDwUsbHc (
-  VOID
-  )
-{
-        DWUSB_OTGHC_DEV	*DwHc;
-	UINT32		Pages;
-
-        DwHc = AllocateZeroPool (sizeof(DWUSB_OTGHC_DEV));
-
-        if (DwHc == NULL) {
-                return NULL;
-        }
-
-        DwHc->Signature                                 = DWUSB_OTGHC_DEV_SIGNATURE;
-        DwHc->DwUsbOtgHc.GetCapability                  = DwHcGetCapability;
-        DwHc->DwUsbOtgHc.Reset                          = DwHcReset;
-        DwHc->DwUsbOtgHc.GetState                       = DwHcGetState;
-        DwHc->DwUsbOtgHc.SetState                       = DwHcSetState;
-        DwHc->DwUsbOtgHc.ControlTransfer                = DwHcControlTransfer;
-        DwHc->DwUsbOtgHc.BulkTransfer                   = DwHcBulkTransfer;
-        DwHc->DwUsbOtgHc.AsyncInterruptTransfer         = DwHcAsyncInterruptTransfer;
-        DwHc->DwUsbOtgHc.SyncInterruptTransfer          = DwHcSyncInterruptTransfer;
-        DwHc->DwUsbOtgHc.IsochronousTransfer            = DwHcIsochronousTransfer;
-        DwHc->DwUsbOtgHc.AsyncIsochronousTransfer       = DwHcAsyncIsochronousTransfer;
-        DwHc->DwUsbOtgHc.GetRootHubPortStatus           = DwHcGetRootHubPortStatus;
-        DwHc->DwUsbOtgHc.SetRootHubPortFeature          = DwHcSetRootHubPortFeature;
-        DwHc->DwUsbOtgHc.ClearRootHubPortFeature        = DwHcClearRootHubPortFeature;
-        DwHc->DwUsbOtgHc.MajorRevision                  = 0x02;
-        DwHc->DwUsbOtgHc.MinorRevision                  = 0x00;
-	DwHc->DwUsbBase					= FixedPcdGet32 (PcdDwUsbDxeBaseAddress);
-
-	CopyMem (&DwHc->DevicePath, &DwHcDevicePath, sizeof(DwHcDevicePath));
-
-	Pages = EFI_SIZE_TO_PAGES (DWC2_STATUS_BUF_SIZE);
-	DwHc->StatusBuffer = UncachedAllocatePages (Pages);
-	if (DwHc->StatusBuffer == NULL) {
-		DEBUG ((EFI_D_ERROR, "CreateDwUsbHc: No page availablefor StatusBuffer\n"));
-		return NULL;
-	}
-
-	Pages = EFI_SIZE_TO_PAGES (DWC2_DATA_BUF_SIZE);
-	DwHc->AlignedBuffer = UncachedAllocatePages (Pages);
-        if (DwHc->AlignedBuffer == NULL) {
-                DEBUG ((EFI_D_ERROR, "CreateDwUsbHc: No page availablefor AlignedBuffer\n"));
-                return NULL;
-        }
-
-        return DwHc;
-}
-
-VOID
-EFIAPI
-DwUsbHcExitBootService (
-  EFI_EVENT	Event,
-  VOID		*Context
-  )
-{
-	DWUSB_OTGHC_DEV		*DwHc;
-
-	DwHc = (DWUSB_OTGHC_DEV *) Context;
-
-        MmioAndThenOr32 (DwHc->DwUsbBase + HPRT0,
-                                ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
-                                  DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG),
-                                  DWC2_HPRT0_PRTRST);
-
-        MicroSecondDelay (50000);
-
-	DwCoreReset (DwHc);
-}
-
-/**
-  UEFI Driver Entry Point API
-
-  @param  ImageHandle       EFI_HANDLE.
-  @param  SystemTable       EFI_SYSTEM_TABLE.
-
-  @return EFI_SUCCESS       Success.
-          EFI_DEVICE_ERROR  Fail.
-**/
-
-EFI_STATUS
-EFIAPI
-DwUsbHostEntryPoint (
-  IN EFI_HANDLE           ImageHandle,
-  IN EFI_SYSTEM_TABLE     *SystemTable
-  )
-{
-	EFI_STATUS                      Status;
-	DWUSB_OTGHC_DEV                 *DwHc;
-	UINT32				Pages;
-
-	Status = EFI_SUCCESS;
-
-	DwHc = CreateDwUsbHc ();
-
-        if (DwHc == NULL) {
-                Status = EFI_OUT_OF_RESOURCES;
-                goto EXIT;
-        }
-
-        Status = gBS->LocateProtocol (&gDwUsbProtocolGuid, NULL, (VOID **) &DwUsb);
-        if (EFI_ERROR (Status)) {
-           return Status;
-        }
-
-        Status = gBS->InstallMultipleProtocolInterfaces (
-                        &DwHc->DeviceHandle,
-                        &gEfiUsb2HcProtocolGuid,	&DwHc->DwUsbOtgHc,
-			&gEfiDevicePathProtocolGuid,	&DwHc->DevicePath,
-			NULL
-                        );
-
-        if (EFI_ERROR (Status)) {
-                goto FREE_DWUSBHC;
-        }
-
-        Status = gBS->CreateEventEx (
-                        EVT_NOTIFY_SIGNAL,
-                        TPL_NOTIFY,
-                        DwUsbHcExitBootService,
-                        DwHc,
-                        &gEfiEventExitBootServicesGuid,
-                        &DwHc->ExitBootServiceEvent
-                        );
-
-        if (EFI_ERROR (Status)) {
-                goto UNINSTALL_PROTOCOL;
-        }
-
-	return Status;
-
-UNINSTALL_PROTOCOL:
-	gBS->UninstallMultipleProtocolInterfaces (
-		&DwHc->DeviceHandle,
-		&gEfiUsb2HcProtocolGuid,	&DwHc->DwUsbOtgHc,
-		&gEfiDevicePathProtocolGuid,	&DwHc->DevicePath,
-		NULL
-		);
-FREE_DWUSBHC:
-        Pages = EFI_SIZE_TO_PAGES (DWC2_STATUS_BUF_SIZE);
-	UncachedFreePages (DwHc->StatusBuffer, Pages);
-        Pages = EFI_SIZE_TO_PAGES (DWC2_DATA_BUF_SIZE);
-	UncachedFreePages (DwHc->AlignedBuffer, Pages);
-	gBS->FreePool (DwHc);
-EXIT:
-	return Status;
-}
-
-EFI_STATUS
-EFIAPI
-DwUsbHostExitPoint (
-  IN EFI_HANDLE	ImageHandle
-  )
-{
-        EFI_STATUS              Status;
-        EFI_USB2_HC_PROTOCOL    *DwUsbHc;
-        DWUSB_OTGHC_DEV         *DwHc;
-	UINT32			Pages;
-
-	Status = EFI_SUCCESS;
-
-        Status = gBS->LocateProtocol (&gEfiUsb2HcProtocolGuid, NULL, (VOID **) &DwUsbHc);
-
-        if (EFI_ERROR (Status)) {
-                return Status;
-        }
-
-        DwHc  = DWHC_FROM_THIS(DwUsbHc);
-
-	if (DwHc->ExitBootServiceEvent != NULL) {
-		gBS->CloseEvent (DwHc->ExitBootServiceEvent);
-	}
-
-        gBS->UninstallMultipleProtocolInterfaces (
-                &DwHc->DeviceHandle,
-                &gEfiUsb2HcProtocolGuid,        &DwHc->DwUsbOtgHc,
-                &gEfiDevicePathProtocolGuid,    &DwHc->DevicePath,
-                NULL
-                );
-
-        if (EFI_ERROR (Status)) {
-                return Status;
-        }
-
-        Pages = EFI_SIZE_TO_PAGES (DWC2_STATUS_BUF_SIZE);
-        UncachedFreePages (DwHc->StatusBuffer, Pages);
-        Pages = EFI_SIZE_TO_PAGES (DWC2_DATA_BUF_SIZE);
-        UncachedFreePages (DwHc->AlignedBuffer, Pages);
-	FreePool (DwHc);
-
-	return Status;
-}
diff --git a/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.h b/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.h
deleted file mode 100644
index bcc11e9..0000000
--- a/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/** @file
-
-  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _DWUSBHOSTDXE_H_
-#define _DWUSBHOSTDXE_H_
-
-#include <Uefi.h>
-
-#include <Protocol/DwUsb.h>
-#include <Protocol/Usb2HostController.h>
-
-#include <Guid/EventGroup.h>
-
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiDriverEntryPoint.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/BaseLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UncachedMemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Library/ReportStatusCodeLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/TimerLib.h>
-
-#define MAX_DEVICE                      16
-#define MAX_ENDPOINT                    16
-
-typedef struct _DWUSB_OTGHC_DEV DWUSB_OTGHC_DEV;
-
-#define DWUSB_OTGHC_DEV_SIGNATURE	SIGNATURE_32 ('d', 'w', 'h', 'c')
-#define DWHC_FROM_THIS(a)		CR(a, DWUSB_OTGHC_DEV, DwUsbOtgHc, DWUSB_OTGHC_DEV_SIGNATURE)
-
-//
-// The RequestType in EFI_USB_DEVICE_REQUEST is composed of
-// three fields: One bit direction, 2 bit type, and 5 bit
-// target.
-//
-#define USB_REQUEST_TYPE(Dir, Type, Target) \
-          ((UINT8)((((Dir) == EfiUsbDataIn ? 0x01 : 0) << 7) | (Type) | (Target)))
-
-typedef struct {
-	ACPI_HID_DEVICE_PATH		AcpiDevicePath;
-	PCI_DEVICE_PATH			PciDevicePath;
-	EFI_DEVICE_PATH_PROTOCOL	EndDevicePath;
-} EFI_USB_PCIIO_DEVICE_PATH;
-
-struct _DWUSB_OTGHC_DEV {
-	UINTN				Signature;
-	EFI_HANDLE			DeviceHandle;
-
-	EFI_USB2_HC_PROTOCOL		DwUsbOtgHc;
-
-	EFI_USB_HC_STATE		DwHcState;
-
-	EFI_USB_PCIIO_DEVICE_PATH	DevicePath;
-
-	EFI_EVENT			ExitBootServiceEvent;
-
-	UINT64				DwUsbBase;
-	UINT8				*StatusBuffer;
-	UINT8				*AlignedBuffer;
-
-	UINT16				PortStatus;
-	UINT16				PortChangeStatus;
-
-	UINT32				RhDevNum;
-};
-
-#endif //_DWUSBHOSTDXE_H_
diff --git a/Drivers/Usb/DwUsbHostDxe/DwcHw.h b/Drivers/Usb/DwUsbHostDxe/DwcHw.h
deleted file mode 100644
index 5a56817..0000000
--- a/Drivers/Usb/DwUsbHostDxe/DwcHw.h
+++ /dev/null
@@ -1,786 +0,0 @@
-/** @file
-
-  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __DWCHW_H__
-#define __DWCHW_H__
-
-#define HSOTG_REG(x)    (x)
-
-#define HCCHAR(_ch)                     HSOTG_REG(0x0500 + 0x20 * (_ch))
-#define HCSPLT(_ch)                     HSOTG_REG(0x0504 + 0x20 * (_ch))
-#define HCINT(_ch)                      HSOTG_REG(0x0508 + 0x20 * (_ch))
-#define HCINTMSK(_ch)                   HSOTG_REG(0x050c + 0x20 * (_ch))
-#define HCTSIZ(_ch)                     HSOTG_REG(0x0510 + 0x20 * (_ch))
-#define HCDMA(_ch)                      HSOTG_REG(0x0514 + 0x20 * (_ch))
-#define HCDMAB(_ch)                     HSOTG_REG(0x051c + 0x20 * (_ch))
-
-#define HCFG                            HSOTG_REG(0x0400)
-#define HFIR                            HSOTG_REG(0x0404)
-#define HFNUM                           HSOTG_REG(0x0408)
-#define HPTXSTS                         HSOTG_REG(0x0410)
-#define HAINT                           HSOTG_REG(0x0414)
-#define HAINTMSK                        HSOTG_REG(0x0418)
-#define HFLBADDR                        HSOTG_REG(0x041c)
-
-#define GOTGCTL                         HSOTG_REG(0x000)
-#define GOTGINT                         HSOTG_REG(0x004)
-#define GAHBCFG                         HSOTG_REG(0x008)
-#define GUSBCFG                         HSOTG_REG(0x00C)
-#define GRSTCTL                         HSOTG_REG(0x010)
-#define GINTSTS                         HSOTG_REG(0x014)
-#define GINTMSK                         HSOTG_REG(0x018)
-#define GRXSTSR                         HSOTG_REG(0x01C)
-#define GRXSTSP                         HSOTG_REG(0x020)
-#define GRXFSIZ                         HSOTG_REG(0x024)
-#define GNPTXFSIZ                       HSOTG_REG(0x028)
-#define GNPTXSTS                        HSOTG_REG(0x02C)
-#define GI2CCTL                         HSOTG_REG(0x0030)
-#define GPVNDCTL                        HSOTG_REG(0x0034)
-#define GGPIO                           HSOTG_REG(0x0038)
-#define GUID                            HSOTG_REG(0x003c)
-#define GSNPSID                         HSOTG_REG(0x0040)
-#define GHWCFG1                         HSOTG_REG(0x0044)
-#define GHWCFG2                         HSOTG_REG(0x0048)
-#define GHWCFG3                         HSOTG_REG(0x004c)
-#define GHWCFG4                         HSOTG_REG(0x0050)
-#define GLPMCFG                         HSOTG_REG(0x0054)
-#define HPTXFSIZ                        HSOTG_REG(0x100)
-#define DPTXFSIZN(_a)                   HSOTG_REG(0x104 + (((_a) - 1) * 4))
-#define HPRT0                           HSOTG_REG(0x0440)
-#define PCGCCTL				HSOTG_REG(0xE00)
-
-#define DWC2_GOTGCTL_SESREQSCS				(1 << 0)
-#define DWC2_GOTGCTL_SESREQSCS_OFFSET			0
-#define DWC2_GOTGCTL_SESREQ				(1 << 1)
-#define DWC2_GOTGCTL_SESREQ_OFFSET			1
-#define DWC2_GOTGCTL_HSTNEGSCS				(1 << 8)
-#define DWC2_GOTGCTL_HSTNEGSCS_OFFSET			8
-#define DWC2_GOTGCTL_HNPREQ				(1 << 9)
-#define DWC2_GOTGCTL_HNPREQ_OFFSET			9
-#define DWC2_GOTGCTL_HSTSETHNPEN			(1 << 10)
-#define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET			10
-#define DWC2_GOTGCTL_DEVHNPEN				(1 << 11)
-#define DWC2_GOTGCTL_DEVHNPEN_OFFSET			11
-#define DWC2_GOTGCTL_CONIDSTS				(1 << 16)
-#define DWC2_GOTGCTL_CONIDSTS_OFFSET			16
-#define DWC2_GOTGCTL_DBNCTIME				(1 << 17)
-#define DWC2_GOTGCTL_DBNCTIME_OFFSET			17
-#define DWC2_GOTGCTL_ASESVLD				(1 << 18)
-#define DWC2_GOTGCTL_ASESVLD_OFFSET			18
-#define DWC2_GOTGCTL_BSESVLD				(1 << 19)
-#define DWC2_GOTGCTL_BSESVLD_OFFSET			19
-#define DWC2_GOTGCTL_OTGVER				(1 << 20)
-#define DWC2_GOTGCTL_OTGVER_OFFSET			20
-#define DWC2_GOTGINT_SESENDDET				(1 << 2)
-#define DWC2_GOTGINT_SESENDDET_OFFSET			2
-#define DWC2_GOTGINT_SESREQSUCSTSCHNG			(1 << 8)
-#define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET		8
-#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG			(1 << 9)
-#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET		9
-#define DWC2_GOTGINT_RESERVER10_16_MASK			(0x7F << 10)
-#define DWC2_GOTGINT_RESERVER10_16_OFFSET		10
-#define DWC2_GOTGINT_HSTNEGDET				(1 << 17)
-#define DWC2_GOTGINT_HSTNEGDET_OFFSET			17
-#define DWC2_GOTGINT_ADEVTOUTCHNG			(1 << 18)
-#define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET		18
-#define DWC2_GOTGINT_DEBDONE				(1 << 19)
-#define DWC2_GOTGINT_DEBDONE_OFFSET			19
-#define DWC2_GAHBCFG_GLBLINTRMSK			(1 << 0)
-#define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET			0
-#define DWC2_GAHBCFG_HBURSTLEN_SINGLE			(0 << 1)
-#define DWC2_GAHBCFG_HBURSTLEN_INCR			(1 << 1)
-#define DWC2_GAHBCFG_HBURSTLEN_INCR4			(3 << 1)
-#define DWC2_GAHBCFG_HBURSTLEN_INCR8			(5 << 1)
-#define DWC2_GAHBCFG_HBURSTLEN_INCR16			(7 << 1)
-#define DWC2_GAHBCFG_HBURSTLEN_MASK			(0xF << 1)
-#define DWC2_GAHBCFG_HBURSTLEN_OFFSET			1
-#define DWC2_GAHBCFG_DMAENABLE				(1 << 5)
-#define DWC2_GAHBCFG_DMAENABLE_OFFSET			5
-#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL		(1 << 7)
-#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET	7
-#define DWC2_GAHBCFG_PTXFEMPLVL				(1 << 8)
-#define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET			8
-#define DWC2_GUSBCFG_TOUTCAL_MASK			(0x7 << 0)
-#define DWC2_GUSBCFG_TOUTCAL_OFFSET			0
-#define DWC2_GUSBCFG_PHYIF				(1 << 3)
-#define DWC2_GUSBCFG_PHYIF_OFFSET			3
-#define DWC2_GUSBCFG_ULPI_UTMI_SEL			(1 << 4)
-#define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET		4
-#define DWC2_GUSBCFG_FSINTF				(1 << 5)
-#define DWC2_GUSBCFG_FSINTF_OFFSET			5
-#define DWC2_GUSBCFG_PHYSEL				(1 << 6)
-#define DWC2_GUSBCFG_PHYSEL_OFFSET			6
-#define DWC2_GUSBCFG_DDRSEL				(1 << 7)
-#define DWC2_GUSBCFG_DDRSEL_OFFSET			7
-#define DWC2_GUSBCFG_SRPCAP				(1 << 8)
-#define DWC2_GUSBCFG_SRPCAP_OFFSET			8
-#define DWC2_GUSBCFG_HNPCAP				(1 << 9)
-#define DWC2_GUSBCFG_HNPCAP_OFFSET			9
-#define DWC2_GUSBCFG_USBTRDTIM_MASK			(0xF << 10)
-#define DWC2_GUSBCFG_USBTRDTIM_OFFSET			10
-#define DWC2_GUSBCFG_NPTXFRWNDEN			(1 << 14)
-#define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET			14
-#define DWC2_GUSBCFG_PHYLPWRCLKSEL			(1 << 15)
-#define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET		15
-#define DWC2_GUSBCFG_OTGUTMIFSSEL			(1 << 16)
-#define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET		16
-#define DWC2_GUSBCFG_ULPI_FSLS				(1 << 17)
-#define DWC2_GUSBCFG_ULPI_FSLS_OFFSET			17
-#define DWC2_GUSBCFG_ULPI_AUTO_RES			(1 << 18)
-#define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET		18
-#define DWC2_GUSBCFG_ULPI_CLK_SUS_M			(1 << 19)
-#define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET		19
-#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV			(1 << 20)
-#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET		20
-#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR		(1 << 21)
-#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET	21
-#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE			(1 << 22)
-#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET		22
-#define DWC2_GUSBCFG_IC_USB_CAP				(1 << 26)
-#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET			26
-#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE		(1 << 27)
-#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET	27
-#define DWC2_GUSBCFG_TX_END_DELAY			(1 << 28)
-#define DWC2_GUSBCFG_TX_END_DELAY_OFFSET		28
-#define DWC2_GUSBCFG_FORCEHOSTMODE			(1 << 29)
-#define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET		29
-#define DWC2_GUSBCFG_FORCEDEVMODE			(1 << 30)
-#define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET		30
-#define DWC2_GLPMCTL_LPM_CAP_EN				(1 << 0)
-#define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET			0
-#define DWC2_GLPMCTL_APPL_RESP				(1 << 1)
-#define DWC2_GLPMCTL_APPL_RESP_OFFSET			1
-#define DWC2_GLPMCTL_HIRD_MASK				(0xF << 2)
-#define DWC2_GLPMCTL_HIRD_OFFSET			2
-#define DWC2_GLPMCTL_REM_WKUP_EN			(1 << 6)
-#define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET			6
-#define DWC2_GLPMCTL_EN_UTMI_SLEEP			(1 << 7)
-#define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET		7
-#define DWC2_GLPMCTL_HIRD_THRES_MASK			(0x1F << 8)
-#define DWC2_GLPMCTL_HIRD_THRES_OFFSET			8
-#define DWC2_GLPMCTL_LPM_RESP_MASK			(0x3 << 13)
-#define DWC2_GLPMCTL_LPM_RESP_OFFSET			13
-#define DWC2_GLPMCTL_PRT_SLEEP_STS			(1 << 15)
-#define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET		15
-#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK		(1 << 16)
-#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET	16
-#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK		(0xF << 17)
-#define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET		17
-#define DWC2_GLPMCTL_RETRY_COUNT_MASK			(0x7 << 21)
-#define DWC2_GLPMCTL_RETRY_COUNT_OFFSET			21
-#define DWC2_GLPMCTL_SEND_LPM				(1 << 24)
-#define DWC2_GLPMCTL_SEND_LPM_OFFSET			24
-#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK		(0x7 << 25)
-#define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET		25
-#define DWC2_GLPMCTL_HSIC_CONNECT			(1 << 30)
-#define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET		30
-#define DWC2_GLPMCTL_INV_SEL_HSIC			(1 << 31)
-#define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET		31
-#define DWC2_GRSTCTL_CSFTRST				(1 << 0)
-#define DWC2_GRSTCTL_CSFTRST_OFFSET			0
-#define DWC2_GRSTCTL_HSFTRST				(1 << 1)
-#define DWC2_GRSTCTL_HSFTRST_OFFSET			1
-#define DWC2_GRSTCTL_HSTFRM				(1 << 2)
-#define DWC2_GRSTCTL_HSTFRM_OFFSET			2
-#define DWC2_GRSTCTL_INTKNQFLSH				(1 << 3)
-#define DWC2_GRSTCTL_INTKNQFLSH_OFFSET			3
-#define DWC2_GRSTCTL_RXFFLSH				(1 << 4)
-#define DWC2_GRSTCTL_RXFFLSH_OFFSET			4
-#define DWC2_GRSTCTL_TXFFLSH				(1 << 5)
-#define DWC2_GRSTCTL_TXFFLSH_OFFSET			5
-#define DWC2_GRSTCTL_TXFNUM_MASK			(0x1F << 6)
-#define DWC2_GRSTCTL_TXFNUM_OFFSET			6
-#define DWC2_GRSTCTL_DMAREQ				(1 << 30)
-#define DWC2_GRSTCTL_DMAREQ_OFFSET			30
-#define DWC2_GRSTCTL_AHBIDLE				(1 << 31)
-#define DWC2_GRSTCTL_AHBIDLE_OFFSET			31
-#define DWC2_GINTMSK_MODEMISMATCH			(1 << 1)
-#define DWC2_GINTMSK_MODEMISMATCH_OFFSET		1
-#define DWC2_GINTMSK_OTGINTR				(1 << 2)
-#define DWC2_GINTMSK_OTGINTR_OFFSET			2
-#define DWC2_GINTMSK_SOFINTR				(1 << 3)
-#define DWC2_GINTMSK_SOFINTR_OFFSET			3
-#define DWC2_GINTMSK_RXSTSQLVL				(1 << 4)
-#define DWC2_GINTMSK_RXSTSQLVL_OFFSET			4
-#define DWC2_GINTMSK_NPTXFEMPTY				(1 << 5)
-#define DWC2_GINTMSK_NPTXFEMPTY_OFFSET			5
-#define DWC2_GINTMSK_GINNAKEFF				(1 << 6)
-#define DWC2_GINTMSK_GINNAKEFF_OFFSET			6
-#define DWC2_GINTMSK_GOUTNAKEFF				(1 << 7)
-#define DWC2_GINTMSK_GOUTNAKEFF_OFFSET			7
-#define DWC2_GINTMSK_I2CINTR				(1 << 9)
-#define DWC2_GINTMSK_I2CINTR_OFFSET			9
-#define DWC2_GINTMSK_ERLYSUSPEND			(1 << 10)
-#define DWC2_GINTMSK_ERLYSUSPEND_OFFSET			10
-#define DWC2_GINTMSK_USBSUSPEND				(1 << 11)
-#define DWC2_GINTMSK_USBSUSPEND_OFFSET			11
-#define DWC2_GINTMSK_USBRESET				(1 << 12)
-#define DWC2_GINTMSK_USBRESET_OFFSET			12
-#define DWC2_GINTMSK_ENUMDONE				(1 << 13)
-#define DWC2_GINTMSK_ENUMDONE_OFFSET			13
-#define DWC2_GINTMSK_ISOOUTDROP				(1 << 14)
-#define DWC2_GINTMSK_ISOOUTDROP_OFFSET			14
-#define DWC2_GINTMSK_EOPFRAME				(1 << 15)
-#define DWC2_GINTMSK_EOPFRAME_OFFSET			15
-#define DWC2_GINTMSK_EPMISMATCH				(1 << 17)
-#define DWC2_GINTMSK_EPMISMATCH_OFFSET			17
-#define DWC2_GINTMSK_INEPINTR				(1 << 18)
-#define DWC2_GINTMSK_INEPINTR_OFFSET			18
-#define DWC2_GINTMSK_OUTEPINTR				(1 << 19)
-#define DWC2_GINTMSK_OUTEPINTR_OFFSET			19
-#define DWC2_GINTMSK_INCOMPLISOIN			(1 << 20)
-#define DWC2_GINTMSK_INCOMPLISOIN_OFFSET		20
-#define DWC2_GINTMSK_INCOMPLISOOUT			(1 << 21)
-#define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET		21
-#define DWC2_GINTMSK_PORTINTR				(1 << 24)
-#define DWC2_GINTMSK_PORTINTR_OFFSET			24
-#define DWC2_GINTMSK_HCINTR				(1 << 25)
-#define DWC2_GINTMSK_HCINTR_OFFSET			25
-#define DWC2_GINTMSK_PTXFEMPTY				(1 << 26)
-#define DWC2_GINTMSK_PTXFEMPTY_OFFSET			26
-#define DWC2_GINTMSK_LPMTRANRCVD			(1 << 27)
-#define DWC2_GINTMSK_LPMTRANRCVD_OFFSET			27
-#define DWC2_GINTMSK_CONIDSTSCHNG			(1 << 28)
-#define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET		28
-#define DWC2_GINTMSK_DISCONNECT				(1 << 29)
-#define DWC2_GINTMSK_DISCONNECT_OFFSET			29
-#define DWC2_GINTMSK_SESSREQINTR			(1 << 30)
-#define DWC2_GINTMSK_SESSREQINTR_OFFSET			30
-#define DWC2_GINTMSK_WKUPINTR				(1 << 31)
-#define DWC2_GINTMSK_WKUPINTR_OFFSET			31
-#define DWC2_GINTSTS_CURMODE_DEVICE			(0 << 0)
-#define DWC2_GINTSTS_CURMODE_HOST			(1 << 0)
-#define DWC2_GINTSTS_CURMODE				(1 << 0)
-#define DWC2_GINTSTS_CURMODE_OFFSET			0
-#define DWC2_GINTSTS_MODEMISMATCH			(1 << 1)
-#define DWC2_GINTSTS_MODEMISMATCH_OFFSET		1
-#define DWC2_GINTSTS_OTGINTR				(1 << 2)
-#define DWC2_GINTSTS_OTGINTR_OFFSET			2
-#define DWC2_GINTSTS_SOFINTR				(1 << 3)
-#define DWC2_GINTSTS_SOFINTR_OFFSET			3
-#define DWC2_GINTSTS_RXSTSQLVL				(1 << 4)
-#define DWC2_GINTSTS_RXSTSQLVL_OFFSET			4
-#define DWC2_GINTSTS_NPTXFEMPTY				(1 << 5)
-#define DWC2_GINTSTS_NPTXFEMPTY_OFFSET			5
-#define DWC2_GINTSTS_GINNAKEFF				(1 << 6)
-#define DWC2_GINTSTS_GINNAKEFF_OFFSET			6
-#define DWC2_GINTSTS_GOUTNAKEFF				(1 << 7)
-#define DWC2_GINTSTS_GOUTNAKEFF_OFFSET			7
-#define DWC2_GINTSTS_I2CINTR				(1 << 9)
-#define DWC2_GINTSTS_I2CINTR_OFFSET			9
-#define DWC2_GINTSTS_ERLYSUSPEND			(1 << 10)
-#define DWC2_GINTSTS_ERLYSUSPEND_OFFSET			10
-#define DWC2_GINTSTS_USBSUSPEND				(1 << 11)
-#define DWC2_GINTSTS_USBSUSPEND_OFFSET			11
-#define DWC2_GINTSTS_USBRESET				(1 << 12)
-#define DWC2_GINTSTS_USBRESET_OFFSET			12
-#define DWC2_GINTSTS_ENUMDONE				(1 << 13)
-#define DWC2_GINTSTS_ENUMDONE_OFFSET			13
-#define DWC2_GINTSTS_ISOOUTDROP				(1 << 14)
-#define DWC2_GINTSTS_ISOOUTDROP_OFFSET			14
-#define DWC2_GINTSTS_EOPFRAME				(1 << 15)
-#define DWC2_GINTSTS_EOPFRAME_OFFSET			15
-#define DWC2_GINTSTS_INTOKENRX				(1 << 16)
-#define DWC2_GINTSTS_INTOKENRX_OFFSET			16
-#define DWC2_GINTSTS_EPMISMATCH				(1 << 17)
-#define DWC2_GINTSTS_EPMISMATCH_OFFSET			17
-#define DWC2_GINTSTS_INEPINT				(1 << 18)
-#define DWC2_GINTSTS_INEPINT_OFFSET			18
-#define DWC2_GINTSTS_OUTEPINTR				(1 << 19)
-#define DWC2_GINTSTS_OUTEPINTR_OFFSET			19
-#define DWC2_GINTSTS_INCOMPLISOIN			(1 << 20)
-#define DWC2_GINTSTS_INCOMPLISOIN_OFFSET		20
-#define DWC2_GINTSTS_INCOMPLISOOUT			(1 << 21)
-#define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET		21
-#define DWC2_GINTSTS_PORTINTR				(1 << 24)
-#define DWC2_GINTSTS_PORTINTR_OFFSET			24
-#define DWC2_GINTSTS_HCINTR				(1 << 25)
-#define DWC2_GINTSTS_HCINTR_OFFSET			25
-#define DWC2_GINTSTS_PTXFEMPTY				(1 << 26)
-#define DWC2_GINTSTS_PTXFEMPTY_OFFSET			26
-#define DWC2_GINTSTS_LPMTRANRCVD			(1 << 27)
-#define DWC2_GINTSTS_LPMTRANRCVD_OFFSET			27
-#define DWC2_GINTSTS_CONIDSTSCHNG			(1 << 28)
-#define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET		28
-#define DWC2_GINTSTS_DISCONNECT				(1 << 29)
-#define DWC2_GINTSTS_DISCONNECT_OFFSET			29
-#define DWC2_GINTSTS_SESSREQINTR			(1 << 30)
-#define DWC2_GINTSTS_SESSREQINTR_OFFSET			30
-#define DWC2_GINTSTS_WKUPINTR				(1 << 31)
-#define DWC2_GINTSTS_WKUPINTR_OFFSET			31
-#define DWC2_GRXSTS_EPNUM_MASK				(0xF << 0)
-#define DWC2_GRXSTS_EPNUM_OFFSET			0
-#define DWC2_GRXSTS_BCNT_MASK				(0x7FF << 4)
-#define DWC2_GRXSTS_BCNT_OFFSET				4
-#define DWC2_GRXSTS_DPID_MASK				(0x3 << 15)
-#define DWC2_GRXSTS_DPID_OFFSET				15
-#define DWC2_GRXSTS_PKTSTS_MASK				(0xF << 17)
-#define DWC2_GRXSTS_PKTSTS_OFFSET			17
-#define DWC2_GRXSTS_FN_MASK				(0xF << 21)
-#define DWC2_GRXSTS_FN_OFFSET				21
-#define DWC2_FIFOSIZE_STARTADDR_MASK			(0xFFFF << 0)
-#define DWC2_FIFOSIZE_STARTADDR_OFFSET			0
-#define DWC2_FIFOSIZE_DEPTH_MASK			(0xFFFF << 16)
-#define DWC2_FIFOSIZE_DEPTH_OFFSET			16
-#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK		(0xFFFF << 0)
-#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET		0
-#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK		(0xFF << 16)
-#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET		16
-#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE		(1 << 24)
-#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET		24
-#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK		(0x3 << 25)
-#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET		25
-#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK		(0xF << 27)
-#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET		27
-#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK			(0xFFFF << 0)
-#define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET			0
-#define DWC2_GI2CCTL_RWDATA_MASK			(0xFF << 0)
-#define DWC2_GI2CCTL_RWDATA_OFFSET			0
-#define DWC2_GI2CCTL_REGADDR_MASK			(0xFF << 8)
-#define DWC2_GI2CCTL_REGADDR_OFFSET			8
-#define DWC2_GI2CCTL_ADDR_MASK				(0x7F << 16)
-#define DWC2_GI2CCTL_ADDR_OFFSET			16
-#define DWC2_GI2CCTL_I2CEN				(1 << 23)
-#define DWC2_GI2CCTL_I2CEN_OFFSET			23
-#define DWC2_GI2CCTL_ACK				(1 << 24)
-#define DWC2_GI2CCTL_ACK_OFFSET				24
-#define DWC2_GI2CCTL_I2CSUSPCTL				(1 << 25)
-#define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET			25
-#define DWC2_GI2CCTL_I2CDEVADDR_MASK			(0x3 << 26)
-#define DWC2_GI2CCTL_I2CDEVADDR_OFFSET			26
-#define DWC2_GI2CCTL_RW					(1 << 30)
-#define DWC2_GI2CCTL_RW_OFFSET				30
-#define DWC2_GI2CCTL_BSYDNE				(1 << 31)
-#define DWC2_GI2CCTL_BSYDNE_OFFSET			31
-#define DWC2_HWCFG1_EP_DIR0_MASK			(0x3 << 0)
-#define DWC2_HWCFG1_EP_DIR0_OFFSET			0
-#define DWC2_HWCFG1_EP_DIR1_MASK			(0x3 << 2)
-#define DWC2_HWCFG1_EP_DIR1_OFFSET			2
-#define DWC2_HWCFG1_EP_DIR2_MASK			(0x3 << 4)
-#define DWC2_HWCFG1_EP_DIR2_OFFSET			4
-#define DWC2_HWCFG1_EP_DIR3_MASK			(0x3 << 6)
-#define DWC2_HWCFG1_EP_DIR3_OFFSET			6
-#define DWC2_HWCFG1_EP_DIR4_MASK			(0x3 << 8)
-#define DWC2_HWCFG1_EP_DIR4_OFFSET			8
-#define DWC2_HWCFG1_EP_DIR5_MASK			(0x3 << 10)
-#define DWC2_HWCFG1_EP_DIR5_OFFSET			10
-#define DWC2_HWCFG1_EP_DIR6_MASK			(0x3 << 12)
-#define DWC2_HWCFG1_EP_DIR6_OFFSET			12
-#define DWC2_HWCFG1_EP_DIR7_MASK			(0x3 << 14)
-#define DWC2_HWCFG1_EP_DIR7_OFFSET			14
-#define DWC2_HWCFG1_EP_DIR8_MASK			(0x3 << 16)
-#define DWC2_HWCFG1_EP_DIR8_OFFSET			16
-#define DWC2_HWCFG1_EP_DIR9_MASK			(0x3 << 18)
-#define DWC2_HWCFG1_EP_DIR9_OFFSET			18
-#define DWC2_HWCFG1_EP_DIR10_MASK			(0x3 << 20)
-#define DWC2_HWCFG1_EP_DIR10_OFFSET			20
-#define DWC2_HWCFG1_EP_DIR11_MASK			(0x3 << 22)
-#define DWC2_HWCFG1_EP_DIR11_OFFSET			22
-#define DWC2_HWCFG1_EP_DIR12_MASK			(0x3 << 24)
-#define DWC2_HWCFG1_EP_DIR12_OFFSET			24
-#define DWC2_HWCFG1_EP_DIR13_MASK			(0x3 << 26)
-#define DWC2_HWCFG1_EP_DIR13_OFFSET			26
-#define DWC2_HWCFG1_EP_DIR14_MASK			(0x3 << 28)
-#define DWC2_HWCFG1_EP_DIR14_OFFSET			28
-#define DWC2_HWCFG1_EP_DIR15_MASK			(0x3 << 30)
-#define DWC2_HWCFG1_EP_DIR15_OFFSET			30
-#define DWC2_HWCFG2_OP_MODE_MASK			(0x7 << 0)
-#define DWC2_HWCFG2_OP_MODE_OFFSET			0
-#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY		(0x0 << 3)
-#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA		(0x1 << 3)
-#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA		(0x2 << 3)
-#define DWC2_HWCFG2_ARCHITECTURE_MASK			(0x3 << 3)
-#define DWC2_HWCFG2_ARCHITECTURE_OFFSET			3
-#define DWC2_HWCFG2_POINT2POINT				(1 << 5)
-#define DWC2_HWCFG2_POINT2POINT_OFFSET			5
-#define DWC2_HWCFG2_HS_PHY_TYPE_MASK			(0x3 << 6)
-#define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET			6
-#define DWC2_HWCFG2_FS_PHY_TYPE_MASK			(0x3 << 8)
-#define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET			8
-#define DWC2_HWCFG2_NUM_DEV_EP_MASK			(0xF << 10)
-#define DWC2_HWCFG2_NUM_DEV_EP_OFFSET			10
-#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK			(0xF << 14)
-#define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET		14
-#define DWC2_HWCFG2_PERIO_EP_SUPPORTED			(1 << 18)
-#define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET		18
-#define DWC2_HWCFG2_DYNAMIC_FIFO			(1 << 19)
-#define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET			19
-#define DWC2_HWCFG2_MULTI_PROC_INT			(1 << 20)
-#define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET		20
-#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK		(0x3 << 22)
-#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET		22
-#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK		(0x3 << 24)
-#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET	24
-#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1F << 26)
-#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET		26
-#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK		(0xF << 0)
-#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET		0
-#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK		(0x7 << 4)
-#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET	4
-#define DWC2_HWCFG3_OTG_FUNC				(1 << 7)
-#define DWC2_HWCFG3_OTG_FUNC_OFFSET			7
-#define DWC2_HWCFG3_I2C					(1 << 8)
-#define DWC2_HWCFG3_I2C_OFFSET				8
-#define DWC2_HWCFG3_VENDOR_CTRL_IF			(1 << 9)
-#define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET		9
-#define DWC2_HWCFG3_OPTIONAL_FEATURES			(1 << 10)
-#define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET		10
-#define DWC2_HWCFG3_SYNCH_RESET_TYPE			(1 << 11)
-#define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET		11
-#define DWC2_HWCFG3_OTG_ENABLE_IC_USB			(1 << 12)
-#define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET		12
-#define DWC2_HWCFG3_OTG_ENABLE_HSIC			(1 << 13)
-#define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET		13
-#define DWC2_HWCFG3_OTG_LPM_EN				(1 << 15)
-#define DWC2_HWCFG3_OTG_LPM_EN_OFFSET			15
-#define DWC2_HWCFG3_DFIFO_DEPTH_MASK			(0xFFFF << 16)
-#define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET			16
-#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK		(0xF << 0)
-#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET		0
-#define DWC2_HWCFG4_POWER_OPTIMIZ			(1 << 4)
-#define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET		4
-#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK			(0x1FF << 5)
-#define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET			5
-#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK		(0x3 << 14)
-#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET		14
-#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK		(0xF << 16)
-#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET		16
-#define DWC2_HWCFG4_IDDIG_FILT_EN			(1 << 20)
-#define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET		20
-#define DWC2_HWCFG4_VBUS_VALID_FILT_EN			(1 << 21)
-#define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET		21
-#define DWC2_HWCFG4_A_VALID_FILT_EN			(1 << 22)
-#define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET		22
-#define DWC2_HWCFG4_B_VALID_FILT_EN			(1 << 23)
-#define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET		23
-#define DWC2_HWCFG4_SESSION_END_FILT_EN			(1 << 24)
-#define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET		24
-#define DWC2_HWCFG4_DED_FIFO_EN				(1 << 25)
-#define DWC2_HWCFG4_DED_FIFO_EN_OFFSET			25
-#define DWC2_HWCFG4_NUM_IN_EPS_MASK			(0xF << 26)
-#define DWC2_HWCFG4_NUM_IN_EPS_OFFSET			26
-#define DWC2_HWCFG4_DESC_DMA				(1 << 30)
-#define DWC2_HWCFG4_DESC_DMA_OFFSET			30
-#define DWC2_HWCFG4_DESC_DMA_DYN			(1 << 31)
-#define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET			31
-#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ			0
-#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ			1
-#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ			2
-#define DWC2_HCFG_FSLSPCLKSEL_MASK			(0x3 << 0)
-#define DWC2_HCFG_FSLSPCLKSEL_OFFSET			0
-#define DWC2_HCFG_FSLSSUPP				(1 << 2)
-#define DWC2_HCFG_FSLSSUPP_OFFSET			2
-#define DWC2_HCFG_DESCDMA				(1 << 23)
-#define DWC2_HCFG_DESCDMA_OFFSET			23
-#define DWC2_HCFG_FRLISTEN_MASK				(0x3 << 24)
-#define DWC2_HCFG_FRLISTEN_OFFSET			24
-#define DWC2_HCFG_PERSCHEDENA				(1 << 26)
-#define DWC2_HCFG_PERSCHEDENA_OFFSET			26
-#define DWC2_HCFG_PERSCHEDSTAT				(1 << 27)
-#define DWC2_HCFG_PERSCHEDSTAT_OFFSET			27
-#define DWC2_HFIR_FRINT_MASK				(0xFFFF << 0)
-#define DWC2_HFIR_FRINT_OFFSET				0
-#define DWC2_HFNUM_FRNUM_MASK				(0xFFFF << 0)
-#define DWC2_HFNUM_FRNUM_OFFSET				0
-#define DWC2_HFNUM_FRREM_MASK				(0xFFFF << 16)
-#define DWC2_HFNUM_FRREM_OFFSET				16
-#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK			(0xFFFF << 0)
-#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET		0
-#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK			(0xFF << 16)
-#define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET		16
-#define DWC2_HPTXSTS_PTXQTOP_TERMINATE			(1 << 24)
-#define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET		24
-#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK			(0x3 << 25)
-#define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET		25
-#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK			(0xF << 27)
-#define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET		27
-#define DWC2_HPTXSTS_PTXQTOP_ODD			(1 << 31)
-#define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET			31
-#define DWC2_HPRT0_PRTCONNSTS				(1 << 0)
-#define DWC2_HPRT0_PRTCONNSTS_OFFSET			0
-#define DWC2_HPRT0_PRTCONNDET				(1 << 1)
-#define DWC2_HPRT0_PRTCONNDET_OFFSET			1
-#define DWC2_HPRT0_PRTENA				(1 << 2)
-#define DWC2_HPRT0_PRTENA_OFFSET			2
-#define DWC2_HPRT0_PRTENCHNG				(1 << 3)
-#define DWC2_HPRT0_PRTENCHNG_OFFSET			3
-#define DWC2_HPRT0_PRTOVRCURRACT			(1 << 4)
-#define DWC2_HPRT0_PRTOVRCURRACT_OFFSET			4
-#define DWC2_HPRT0_PRTOVRCURRCHNG			(1 << 5)
-#define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET		5
-#define DWC2_HPRT0_PRTRES				(1 << 6)
-#define DWC2_HPRT0_PRTRES_OFFSET			6
-#define DWC2_HPRT0_PRTSUSP				(1 << 7)
-#define DWC2_HPRT0_PRTSUSP_OFFSET			7
-#define DWC2_HPRT0_PRTRST				(1 << 8)
-#define DWC2_HPRT0_PRTRST_OFFSET			8
-#define DWC2_HPRT0_PRTLNSTS_MASK			(0x3 << 10)
-#define DWC2_HPRT0_PRTLNSTS_OFFSET			10
-#define DWC2_HPRT0_PRTPWR				(1 << 12)
-#define DWC2_HPRT0_PRTPWR_OFFSET			12
-#define DWC2_HPRT0_PRTTSTCTL_MASK			(0xF << 13)
-#define DWC2_HPRT0_PRTTSTCTL_OFFSET			13
-#define DWC2_HPRT0_PRTSPD_MASK				(0x3 << 17)
-#define DWC2_HPRT0_PRTSPD_OFFSET			17
-#define DWC2_HAINT_CH0					(1 << 0)
-#define DWC2_HAINT_CH0_OFFSET				0
-#define DWC2_HAINT_CH1					(1 << 1)
-#define DWC2_HAINT_CH1_OFFSET				1
-#define DWC2_HAINT_CH2					(1 << 2)
-#define DWC2_HAINT_CH2_OFFSET				2
-#define DWC2_HAINT_CH3					(1 << 3)
-#define DWC2_HAINT_CH3_OFFSET				3
-#define DWC2_HAINT_CH4					(1 << 4)
-#define DWC2_HAINT_CH4_OFFSET				4
-#define DWC2_HAINT_CH5					(1 << 5)
-#define DWC2_HAINT_CH5_OFFSET				5
-#define DWC2_HAINT_CH6					(1 << 6)
-#define DWC2_HAINT_CH6_OFFSET				6
-#define DWC2_HAINT_CH7					(1 << 7)
-#define DWC2_HAINT_CH7_OFFSET				7
-#define DWC2_HAINT_CH8					(1 << 8)
-#define DWC2_HAINT_CH8_OFFSET				8
-#define DWC2_HAINT_CH9					(1 << 9)
-#define DWC2_HAINT_CH9_OFFSET				9
-#define DWC2_HAINT_CH10					(1 << 10)
-#define DWC2_HAINT_CH10_OFFSET				10
-#define DWC2_HAINT_CH11					(1 << 11)
-#define DWC2_HAINT_CH11_OFFSET				11
-#define DWC2_HAINT_CH12					(1 << 12)
-#define DWC2_HAINT_CH12_OFFSET				12
-#define DWC2_HAINT_CH13					(1 << 13)
-#define DWC2_HAINT_CH13_OFFSET				13
-#define DWC2_HAINT_CH14					(1 << 14)
-#define DWC2_HAINT_CH14_OFFSET				14
-#define DWC2_HAINT_CH15					(1 << 15)
-#define DWC2_HAINT_CH15_OFFSET				15
-#define DWC2_HAINT_CHINT_MASK				0xffff
-#define DWC2_HAINT_CHINT_OFFSET				0
-#define DWC2_HAINTMSK_CH0				(1 << 0)
-#define DWC2_HAINTMSK_CH0_OFFSET			0
-#define DWC2_HAINTMSK_CH1				(1 << 1)
-#define DWC2_HAINTMSK_CH1_OFFSET			1
-#define DWC2_HAINTMSK_CH2				(1 << 2)
-#define DWC2_HAINTMSK_CH2_OFFSET			2
-#define DWC2_HAINTMSK_CH3				(1 << 3)
-#define DWC2_HAINTMSK_CH3_OFFSET			3
-#define DWC2_HAINTMSK_CH4				(1 << 4)
-#define DWC2_HAINTMSK_CH4_OFFSET			4
-#define DWC2_HAINTMSK_CH5				(1 << 5)
-#define DWC2_HAINTMSK_CH5_OFFSET			5
-#define DWC2_HAINTMSK_CH6				(1 << 6)
-#define DWC2_HAINTMSK_CH6_OFFSET			6
-#define DWC2_HAINTMSK_CH7				(1 << 7)
-#define DWC2_HAINTMSK_CH7_OFFSET			7
-#define DWC2_HAINTMSK_CH8				(1 << 8)
-#define DWC2_HAINTMSK_CH8_OFFSET			8
-#define DWC2_HAINTMSK_CH9				(1 << 9)
-#define DWC2_HAINTMSK_CH9_OFFSET			9
-#define DWC2_HAINTMSK_CH10				(1 << 10)
-#define DWC2_HAINTMSK_CH10_OFFSET			10
-#define DWC2_HAINTMSK_CH11				(1 << 11)
-#define DWC2_HAINTMSK_CH11_OFFSET			11
-#define DWC2_HAINTMSK_CH12				(1 << 12)
-#define DWC2_HAINTMSK_CH12_OFFSET			12
-#define DWC2_HAINTMSK_CH13				(1 << 13)
-#define DWC2_HAINTMSK_CH13_OFFSET			13
-#define DWC2_HAINTMSK_CH14				(1 << 14)
-#define DWC2_HAINTMSK_CH14_OFFSET			14
-#define DWC2_HAINTMSK_CH15				(1 << 15)
-#define DWC2_HAINTMSK_CH15_OFFSET			15
-#define DWC2_HAINTMSK_CHINT_MASK			0xffff
-#define DWC2_HAINTMSK_CHINT_OFFSET			0
-#define DWC2_HCCHAR_MPS_MASK				(0x7FF << 0)
-#define DWC2_HCCHAR_MPS_OFFSET				0
-#define DWC2_HCCHAR_EPNUM_MASK				(0xF << 11)
-#define DWC2_HCCHAR_EPNUM_OFFSET			11
-#define DWC2_HCCHAR_EPDIR				(1 << 15)
-#define DWC2_HCCHAR_EPDIR_OFFSET			15
-#define DWC2_HCCHAR_LSPDDEV				(1 << 17)
-#define DWC2_HCCHAR_LSPDDEV_OFFSET			17
-#define DWC2_HCCHAR_EPTYPE_CONTROL			0
-#define DWC2_HCCHAR_EPTYPE_ISOC				1
-#define DWC2_HCCHAR_EPTYPE_BULK				2
-#define DWC2_HCCHAR_EPTYPE_INTR				3
-#define DWC2_HCCHAR_EPTYPE_MASK				(0x3 << 18)
-#define DWC2_HCCHAR_EPTYPE_OFFSET			18
-#define DWC2_HCCHAR_MULTICNT_MASK			(0x3 << 20)
-#define DWC2_HCCHAR_MULTICNT_OFFSET			20
-#define DWC2_HCCHAR_DEVADDR_MASK			(0x7F << 22)
-#define DWC2_HCCHAR_DEVADDR_OFFSET			22
-#define DWC2_HCCHAR_ODDFRM				(1 << 29)
-#define DWC2_HCCHAR_ODDFRM_OFFSET			29
-#define DWC2_HCCHAR_CHDIS				(1 << 30)
-#define DWC2_HCCHAR_CHDIS_OFFSET			30
-#define DWC2_HCCHAR_CHEN				(1 << 31)
-#define DWC2_HCCHAR_CHEN_OFFSET				31
-#define DWC2_HCSPLT_PRTADDR_MASK			(0x7F << 0)
-#define DWC2_HCSPLT_PRTADDR_OFFSET			0
-#define DWC2_HCSPLT_HUBADDR_MASK			(0x7F << 7)
-#define DWC2_HCSPLT_HUBADDR_OFFSET			7
-#define DWC2_HCSPLT_XACTPOS_MASK			(0x3 << 14)
-#define DWC2_HCSPLT_XACTPOS_OFFSET			14
-#define DWC2_HCSPLT_COMPSPLT				(1 << 16)
-#define DWC2_HCSPLT_COMPSPLT_OFFSET			16
-#define DWC2_HCSPLT_SPLTENA				(1 << 31)
-#define DWC2_HCSPLT_SPLTENA_OFFSET			31
-#define DWC2_HCINT_XFERCOMP				(1 << 0)
-#define DWC2_HCINT_XFERCOMP_OFFSET			0
-#define DWC2_HCINT_CHHLTD				(1 << 1)
-#define DWC2_HCINT_CHHLTD_OFFSET			1
-#define DWC2_HCINT_AHBERR				(1 << 2)
-#define DWC2_HCINT_AHBERR_OFFSET			2
-#define DWC2_HCINT_STALL				(1 << 3)
-#define DWC2_HCINT_STALL_OFFSET				3
-#define DWC2_HCINT_NAK					(1 << 4)
-#define DWC2_HCINT_NAK_OFFSET				4
-#define DWC2_HCINT_ACK					(1 << 5)
-#define DWC2_HCINT_ACK_OFFSET				5
-#define DWC2_HCINT_NYET					(1 << 6)
-#define DWC2_HCINT_NYET_OFFSET				6
-#define DWC2_HCINT_XACTERR				(1 << 7)
-#define DWC2_HCINT_XACTERR_OFFSET			7
-#define DWC2_HCINT_BBLERR				(1 << 8)
-#define DWC2_HCINT_BBLERR_OFFSET			8
-#define DWC2_HCINT_FRMOVRUN				(1 << 9)
-#define DWC2_HCINT_FRMOVRUN_OFFSET			9
-#define DWC2_HCINT_DATATGLERR				(1 << 10)
-#define DWC2_HCINT_DATATGLERR_OFFSET			10
-#define DWC2_HCINT_BNA					(1 << 11)
-#define DWC2_HCINT_BNA_OFFSET				11
-#define DWC2_HCINT_XCS_XACT				(1 << 12)
-#define DWC2_HCINT_XCS_XACT_OFFSET			12
-#define DWC2_HCINT_FRM_LIST_ROLL			(1 << 13)
-#define DWC2_HCINT_FRM_LIST_ROLL_OFFSET			13
-#define DWC2_HCINTMSK_XFERCOMPL				(1 << 0)
-#define DWC2_HCINTMSK_XFERCOMPL_OFFSET			0
-#define DWC2_HCINTMSK_CHHLTD				(1 << 1)
-#define DWC2_HCINTMSK_CHHLTD_OFFSET			1
-#define DWC2_HCINTMSK_AHBERR				(1 << 2)
-#define DWC2_HCINTMSK_AHBERR_OFFSET			2
-#define DWC2_HCINTMSK_STALL				(1 << 3)
-#define DWC2_HCINTMSK_STALL_OFFSET			3
-#define DWC2_HCINTMSK_NAK				(1 << 4)
-#define DWC2_HCINTMSK_NAK_OFFSET			4
-#define DWC2_HCINTMSK_ACK				(1 << 5)
-#define DWC2_HCINTMSK_ACK_OFFSET			5
-#define DWC2_HCINTMSK_NYET				(1 << 6)
-#define DWC2_HCINTMSK_NYET_OFFSET			6
-#define DWC2_HCINTMSK_XACTERR				(1 << 7)
-#define DWC2_HCINTMSK_XACTERR_OFFSET			7
-#define DWC2_HCINTMSK_BBLERR				(1 << 8)
-#define DWC2_HCINTMSK_BBLERR_OFFSET			8
-#define DWC2_HCINTMSK_FRMOVRUN				(1 << 9)
-#define DWC2_HCINTMSK_FRMOVRUN_OFFSET			9
-#define DWC2_HCINTMSK_DATATGLERR			(1 << 10)
-#define DWC2_HCINTMSK_DATATGLERR_OFFSET			10
-#define DWC2_HCINTMSK_BNA				(1 << 11)
-#define DWC2_HCINTMSK_BNA_OFFSET			11
-#define DWC2_HCINTMSK_XCS_XACT				(1 << 12)
-#define DWC2_HCINTMSK_XCS_XACT_OFFSET			12
-#define DWC2_HCINTMSK_FRM_LIST_ROLL			(1 << 13)
-#define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET		13
-#define DWC2_HCTSIZ_XFERSIZE_MASK			0x7ffff
-#define DWC2_HCTSIZ_XFERSIZE_OFFSET			0
-#define DWC2_HCTSIZ_SCHINFO_MASK			0xff
-#define DWC2_HCTSIZ_SCHINFO_OFFSET			0
-#define DWC2_HCTSIZ_NTD_MASK				(0xff << 8)
-#define DWC2_HCTSIZ_NTD_OFFSET				8
-#define DWC2_HCTSIZ_PKTCNT_MASK				(0x3ff << 19)
-#define DWC2_HCTSIZ_PKTCNT_OFFSET			19
-#define DWC2_HCTSIZ_PID_MASK				(0x3 << 29)
-#define DWC2_HCTSIZ_PID_OFFSET				29
-#define DWC2_HCTSIZ_DOPNG				(1 << 31)
-#define DWC2_HCTSIZ_DOPNG_OFFSET			31
-#define DWC2_HCDMA_CTD_MASK				(0xFF << 3)
-#define DWC2_HCDMA_CTD_OFFSET				3
-#define DWC2_HCDMA_DMA_ADDR_MASK			(0x1FFFFF << 11)
-#define DWC2_HCDMA_DMA_ADDR_OFFSET			11
-#define DWC2_PCGCCTL_STOPPCLK				(1 << 0)
-#define DWC2_PCGCCTL_STOPPCLK_OFFSET			0
-#define DWC2_PCGCCTL_GATEHCLK				(1 << 1)
-#define DWC2_PCGCCTL_GATEHCLK_OFFSET			1
-#define DWC2_PCGCCTL_PWRCLMP				(1 << 2)
-#define DWC2_PCGCCTL_PWRCLMP_OFFSET			2
-#define DWC2_PCGCCTL_RSTPDWNMODULE			(1 << 3)
-#define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET		3
-#define DWC2_PCGCCTL_PHYSUSPENDED			(1 << 4)
-#define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET		4
-#define DWC2_PCGCCTL_ENBL_SLEEP_GATING			(1 << 5)
-#define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET		5
-#define DWC2_PCGCCTL_PHY_IN_SLEEP			(1 << 6)
-#define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET		6
-#define DWC2_PCGCCTL_DEEP_SLEEP				(1 << 7)
-#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET			7
-#define DWC2_SNPSID_DEVID_VER_2xx			(0x4f542 << 12)
-#define DWC2_SNPSID_DEVID_VER_3xx			(0x4f543 << 12)
-#define DWC2_SNPSID_DEVID_MASK				(0xfffff << 12)
-#define DWC2_SNPSID_DEVID_OFFSET			12
-
-/* Host controller specific */
-#define DWC2_HC_PID_DATA0		0
-#define DWC2_HC_PID_DATA2		1
-#define DWC2_HC_PID_DATA1		2
-#define DWC2_HC_PID_MDATA		3
-#define DWC2_HC_PID_SETUP		3
-
-/* roothub.a masks */
-#define RH_A_NDP	(0xff << 0)	/* number of downstream ports */
-#define RH_A_PSM	(1 << 8)	/* power switching mode */
-#define RH_A_NPS	(1 << 9)	/* no power switching */
-#define RH_A_DT		(1 << 10)	/* device type (mbz) */
-#define RH_A_OCPM	(1 << 11)	/* over current protection mode */
-#define RH_A_NOCP	(1 << 12)	/* no over current protection */
-#define RH_A_POTPGT	(0xff << 24)	/* power on to power good time */
-
-/* roothub.b masks */
-#define RH_B_DR		0x0000ffff	/* device removable flags */
-#define RH_B_PPCM	0xffff0000	/* port power control mask */
-
-#define DWC2_PHY_TYPE_FS		0
-#define DWC2_PHY_TYPE_UTMI		1
-#define DWC2_PHY_TYPE_ULPI		2
-#define CONFIG_DWC2_PHY_TYPE		DWC2_PHY_TYPE_UTMI	/* PHY type */
-#define CONFIG_DWC2_UTMI_WIDTH		8	/* UTMI bus width (8/16) */
-
-#define DWC2_DMA_BURST_SIZE              32      /* DMA burst len */
-#define DWC2_MAX_CHANNELS                16      /* Max # of EPs */
-#define DWC2_HOST_RX_FIFO_SIZE           (516 + DWC2_MAX_CHANNELS)
-#define DWC2_HOST_NPERIO_TX_FIFO_SIZE    0x100   /* nPeriodic TX FIFO */
-#define DWC2_HOST_PERIO_TX_FIFO_SIZE     0x200   /* Periodic TX FIFO */
-#define DWC2_MAX_TRANSFER_SIZE           65535
-#define DWC2_MAX_PACKET_COUNT            511
-
-#define DWC2_HC_CHANNEL                 0
-
-#define DWC2_STATUS_BUF_SIZE            64
-#define DWC2_DATA_BUF_SIZE              (64 * 1024)
-
-
-#define USB_PORT_FEAT_CONNECTION     0
-#define USB_PORT_FEAT_ENABLE         1
-#define USB_PORT_FEAT_SUSPEND        2
-#define USB_PORT_FEAT_OVER_CURRENT   3
-#define USB_PORT_FEAT_RESET          4
-#define USB_PORT_FEAT_POWER          8
-#define USB_PORT_FEAT_LOWSPEED       9
-#define USB_PORT_FEAT_HIGHSPEED      10
-#define USB_PORT_FEAT_C_CONNECTION   16
-#define USB_PORT_FEAT_C_ENABLE       17
-#define USB_PORT_FEAT_C_SUSPEND      18
-#define USB_PORT_FEAT_C_OVER_CURRENT 19
-#define USB_PORT_FEAT_C_RESET        20
-#define USB_PORT_FEAT_TEST           21
-
-#endif	/* __DWCHW_H__ */
diff --git a/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.c b/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.c
deleted file mode 100644
index cb09566..0000000
--- a/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/** @file
-  This file implement the Variable Protocol for the block device.
-
-  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Guid/VariableFormat.h>
-#include <Guid/SystemNvDataGuid.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-
-#include "BlockVariableDxe.h"
-
-
-STATIC EFI_PHYSICAL_ADDRESS      mMapNvStorageVariableBase;
-
-EFI_STATUS
-EFIAPI
-FvbGetAttributes (
-  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL    *This,
-  OUT       EFI_FVB_ATTRIBUTES_2                   *Attributes
-  )
-{
-  EFI_FVB_ATTRIBUTES_2 FvbAttributes;
-  FvbAttributes = (EFI_FVB_ATTRIBUTES_2) (
-
-      EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
-      EFI_FVB2_READ_STATUS      | // Reads are currently enabled
-      EFI_FVB2_STICKY_WRITE     | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
-      EFI_FVB2_MEMORY_MAPPED    | // It is memory mapped
-      EFI_FVB2_ERASE_POLARITY     // After erasure all bits take this value (i.e. '1')
-
-      );
-  FvbAttributes |= EFI_FVB2_WRITE_STATUS      | // Writes are currently enabled
-                   EFI_FVB2_WRITE_ENABLED_CAP;  // Writes may be enabled
-
-  *Attributes = FvbAttributes;
-
-  DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes));
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-FvbSetAttributes(
-  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL  *This,
-  IN OUT    EFI_FVB_ATTRIBUTES_2                 *Attributes
-  )
-{
-  DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attributes));
-  return EFI_UNSUPPORTED;
-}
-
-EFI_STATUS
-EFIAPI
-FvbGetPhysicalAddress (
-  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL  *This,
-  OUT       EFI_PHYSICAL_ADDRESS                 *Address
-  )
-{
-  *Address = mMapNvStorageVariableBase;
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-FvbGetBlockSize (
-  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL  *This,
-  IN        EFI_LBA                              Lba,
-  OUT       UINTN                                *BlockSize,
-  OUT       UINTN                                *NumberOfBlocks
-  )
-{
-  BLOCK_VARIABLE_INSTANCE       *Instance;
-
-  Instance = CR (This, BLOCK_VARIABLE_INSTANCE, FvbProtocol, BLOCK_VARIABLE_SIGNATURE);
-  *BlockSize = (UINTN) Instance->Media.BlockSize;
-  *NumberOfBlocks = PcdGet32 (PcdNvStorageVariableBlockCount);
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-FvbRead (
-  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL   *This,
-  IN        EFI_LBA                               Lba,
-  IN        UINTN                                 Offset,
-  IN OUT    UINTN                                 *NumBytes,
-  IN OUT    UINT8                                 *Buffer
-  )
-{
-  BLOCK_VARIABLE_INSTANCE       *Instance;
-  EFI_BLOCK_IO_PROTOCOL         *BlockIo;
-  EFI_STATUS                    Status;
-  UINTN                         Bytes;
-  VOID                          *DataPtr;
-
-  Instance = CR (This, BLOCK_VARIABLE_INSTANCE, FvbProtocol, BLOCK_VARIABLE_SIGNATURE);
-  BlockIo = Instance->BlockIoProtocol;
-  Bytes = (Offset + *NumBytes + Instance->Media.BlockSize - 1) / Instance->Media.BlockSize * Instance->Media.BlockSize;
-  DataPtr = AllocateZeroPool (Bytes);
-  if (DataPtr == NULL) {
-    DEBUG ((EFI_D_ERROR, "FvbWrite: failed to allocate buffer.\n"));
-    return EFI_BUFFER_TOO_SMALL;
-  }
-  WriteBackDataCacheRange (DataPtr, Bytes);
-  InvalidateDataCacheRange (Buffer, *NumBytes);
-  Status = BlockIo->ReadBlocks (BlockIo, BlockIo->Media->MediaId, Instance->StartLba + Lba,
-		                Bytes, DataPtr);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "FvbRead StartLba:%x, Lba:%x, Offset:%x, Status:%x\n",
-	    Instance->StartLba, Lba, Offset, Status));
-    goto exit;
-  }
-  CopyMem (Buffer, DataPtr + Offset, *NumBytes);
-  WriteBackDataCacheRange (Buffer, *NumBytes);
-exit:
-  FreePool (DataPtr);
-  return Status;
-}
-
-EFI_STATUS
-EFIAPI
-FvbWrite (
-  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL   *This,
-  IN        EFI_LBA                               Lba,
-  IN        UINTN                                 Offset,
-  IN OUT    UINTN                                 *NumBytes,
-  IN        UINT8                                 *Buffer
-  )
-{
-  BLOCK_VARIABLE_INSTANCE       *Instance;
-  EFI_BLOCK_IO_PROTOCOL         *BlockIo;
-  EFI_STATUS                    Status;
-  UINTN                         Bytes;
-  VOID                          *DataPtr;
-
-  Instance = CR (This, BLOCK_VARIABLE_INSTANCE, FvbProtocol, BLOCK_VARIABLE_SIGNATURE);
-  BlockIo = Instance->BlockIoProtocol;
-  Bytes = (Offset + *NumBytes + Instance->Media.BlockSize - 1) / Instance->Media.BlockSize * Instance->Media.BlockSize;
-  DataPtr = AllocateZeroPool (Bytes);
-  if (DataPtr == NULL) {
-    DEBUG ((EFI_D_ERROR, "FvbWrite: failed to allocate buffer.\n"));
-    return EFI_BUFFER_TOO_SMALL;
-  }
-  WriteBackDataCacheRange (DataPtr, Bytes);
-  Status = BlockIo->ReadBlocks (BlockIo, BlockIo->Media->MediaId, Instance->StartLba + Lba,
-                                Bytes, DataPtr);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "FvbWrite: failed on reading blocks.\n"));
-    goto exit;
-  }
-  CopyMem (DataPtr + Offset, Buffer, *NumBytes);
-  WriteBackDataCacheRange (DataPtr, Bytes);
-  Status = BlockIo->WriteBlocks (BlockIo, BlockIo->Media->MediaId, Instance->StartLba + Lba,
-                                 Bytes, DataPtr);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "FvbWrite StartLba:%x, Lba:%x, Offset:%x, Status:%x\n",
-            Instance->StartLba, Lba, Offset, Status));
-  }
-  // Sometimes the variable isn't flushed into block device if it's the last flush operation.
-  // So flush it again.
-  Status = BlockIo->WriteBlocks (BlockIo, BlockIo->Media->MediaId, Instance->StartLba + Lba,
-                                 Bytes, DataPtr);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "FvbWrite StartLba:%x, Lba:%x, Offset:%x, Status:%x\n",
-            Instance->StartLba, Lba, Offset, Status));
-  }
-exit:
-  FreePool (DataPtr);
-  return Status;
-}
-
-EFI_STATUS
-EFIAPI
-FvbEraseBlocks (
-  IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
-  ...
-  )
-{
-  return EFI_SUCCESS;
-}
-
-STATIC BLOCK_VARIABLE_INSTANCE   mBlockVariableInstance = {
-  .Signature      = BLOCK_VARIABLE_SIGNATURE,
-  .Media          = {
-    .MediaId                       = 0,
-    .RemovableMedia                = FALSE,
-    .MediaPresent                  = TRUE,
-    .LogicalPartition              = TRUE,
-    .ReadOnly                      = FALSE,
-    .WriteCaching                  = FALSE,
-    .BlockSize                     = 0,
-    .IoAlign                       = 4,
-    .LastBlock                     = 0,
-    .LowestAlignedLba              = 0,
-    .LogicalBlocksPerPhysicalBlock = 0,
-  },
-  .FvbProtocol    = {
-    .GetAttributes        = FvbGetAttributes,
-    .SetAttributes        = FvbSetAttributes,
-    .GetPhysicalAddress   = FvbGetPhysicalAddress,
-    .GetBlockSize         = FvbGetBlockSize,
-    .Read                 = FvbRead,
-    .Write                = FvbWrite,
-    .EraseBlocks          = FvbEraseBlocks,
-  }
-};
-
-EFI_STATUS
-ValidateFvHeader (
-  IN EFI_FIRMWARE_VOLUME_HEADER  *FwVolHeader
-  )
-{
-  UINT16                      Checksum, TempChecksum;
-  VARIABLE_STORE_HEADER       *VariableStoreHeader;
-  UINTN                       VariableStoreLength;
-  UINTN                       FvLength;
-
-  FvLength = (UINTN) (PcdGet32(PcdFlashNvStorageVariableSize) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
-      PcdGet32(PcdFlashNvStorageFtwSpareSize));
-
-  //
-  // Verify the header revision, header signature, length
-  // Length of FvBlock cannot be 2**64-1
-  // HeaderLength cannot be an odd number
-  //
-  if (   (FwVolHeader->Revision  != EFI_FVH_REVISION)
-      || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
-      || (FwVolHeader->FvLength  != FvLength)
-      )
-  {
-    DEBUG ((EFI_D_ERROR, "ValidateFvHeader: No Firmware Volume header present\n"));
-    return EFI_NOT_FOUND;
-  }
-
-  // Check the Firmware Volume Guid
-  if( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) {
-    DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Firmware Volume Guid non-compatible\n"));
-    return EFI_NOT_FOUND;
-  }
-
-  // Verify the header checksum
-  TempChecksum = FwVolHeader->Checksum;
-  FwVolHeader->Checksum = 0;
-  Checksum = CalculateSum16((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
-  if (Checksum != TempChecksum) {
-    DEBUG ((EFI_D_ERROR, "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n",Checksum));
-    return EFI_NOT_FOUND;
-  }
-  FwVolHeader->Checksum = Checksum;
-
-  VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + FwVolHeader->HeaderLength);
-
-  // Check the Variable Store Guid
-  if( CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) == FALSE ) {
-    DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Variable Store Guid non-compatible\n"));
-    return EFI_NOT_FOUND;
-  }
-
-  VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
-  if (VariableStoreHeader->Size != VariableStoreLength) {
-    DEBUG ((EFI_D_ERROR, "ValidateFvHeader: Variable Store Length does not match\n"));
-    return EFI_NOT_FOUND;
-  }
-
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-InitNonVolatileVariableStore (
-  IN BLOCK_VARIABLE_INSTANCE      *Instance,
-  IN VOID                         *Headers,
-  IN UINTN                        HeadersLength
-  )
-{
-  EFI_FIRMWARE_VOLUME_HEADER            *FirmwareVolumeHeader;
-  EFI_STATUS                            Status;
-  VARIABLE_STORE_HEADER                 *VariableStoreHeader;
-
-  // Check if the size of the area is at least one block size
-  ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && (PcdGet32(PcdFlashNvStorageVariableSize) / Instance->BlockIoProtocol->Media->BlockSize > 0));
-  ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingSize) > 0) && (PcdGet32(PcdFlashNvStorageFtwWorkingSize) / Instance->BlockIoProtocol->Media->BlockSize > 0));
-  ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32(PcdFlashNvStorageFtwSpareSize) / Instance->BlockIoProtocol->Media->BlockSize > 0));
-
-  //
-  // EFI_FIRMWARE_VOLUME_HEADER
-  //
-  FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Headers;
-  CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
-  FirmwareVolumeHeader->FvLength =
-      PcdGet32(PcdFlashNvStorageVariableSize) +
-      PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
-      PcdGet32(PcdFlashNvStorageFtwSpareSize);
-  FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
-  FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) (
-                                            EFI_FVB2_READ_ENABLED_CAP   | // Reads may be enabled
-                                            EFI_FVB2_READ_STATUS        | // Reads are currently enabled
-                                            EFI_FVB2_STICKY_WRITE       | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
-                                            EFI_FVB2_MEMORY_MAPPED      | // It is memory mapped
-                                            EFI_FVB2_ERASE_POLARITY     | // After erasure all bits take this value (i.e. '1')
-                                            EFI_FVB2_WRITE_STATUS       | // Writes are currently enabled
-                                            EFI_FVB2_WRITE_ENABLED_CAP    // Writes may be enabled
-                                        );
-  FirmwareVolumeHeader->HeaderLength          = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY);
-  FirmwareVolumeHeader->Revision              = EFI_FVH_REVISION;
-  FirmwareVolumeHeader->BlockMap[0].NumBlocks = PcdGet32 (PcdNvStorageVariableBlockCount);
-  FirmwareVolumeHeader->BlockMap[0].Length    = Instance->BlockIoProtocol->Media->BlockSize;
-  // BlockMap Terminator
-  FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
-  FirmwareVolumeHeader->BlockMap[1].Length    = 0;
-  FirmwareVolumeHeader->Checksum = 0;
-  FirmwareVolumeHeader->Checksum = CalculateSum16 ((UINT16*)FirmwareVolumeHeader, FirmwareVolumeHeader->HeaderLength);
-
-  //
-  // VARIABLE_STORE_HEADER
-  //
-  VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FirmwareVolumeHeader + FirmwareVolumeHeader->HeaderLength);
-  CopyGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid);
-  VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
-  VariableStoreHeader->Format            = VARIABLE_STORE_FORMATTED;
-  VariableStoreHeader->State             = VARIABLE_STORE_HEALTHY;
-
-  Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
-  return Status;
-}
-
-EFI_STATUS
-BlockVariableDxeInitialize (
-  IN EFI_HANDLE                   ImageHandle,
-  IN EFI_SYSTEM_TABLE             *SystemTable
-  )
-{
-  EFI_HANDLE                      Handle;
-  EFI_STATUS                      Status;
-  BLOCK_VARIABLE_INSTANCE         *Instance = &mBlockVariableInstance;
-  UINT32                          Count;
-  EFI_LBA                         Lba;
-  UINTN                           NvStorageSize;
-  EFI_DEVICE_PATH_PROTOCOL        *NvBlockDevicePath;
-  UINT8                           *NvStorageData;
-  VOID                            *Headers;
-  UINTN                           HeadersLength;
-
-  Instance->Signature = BLOCK_VARIABLE_SIGNATURE;
-
-  HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER);
-  Headers = AllocateZeroPool(HeadersLength);
-  if (Headers == NULL) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to allocate memory of Headers\n", __func__));
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  Lba = (EFI_LBA) PcdGet32 (PcdNvStorageVariableBlockLba);
-  Count = PcdGet32 (PcdNvStorageVariableBlockCount);
-  Instance->Media.BlockSize = PcdGet32 (PcdNvStorageVariableBlockSize);
-  NvStorageSize = Count * Instance->Media.BlockSize;
-  Instance->StartLba = Lba;
-  HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER);
-  if (NvStorageSize < HeadersLength) {
-    return EFI_BAD_BUFFER_SIZE;
-  }
-  NvStorageData = (UINT8 *) (UINTN) PcdGet32(PcdFlashNvStorageVariableBase);
-  mMapNvStorageVariableBase = PcdGet32(PcdFlashNvStorageVariableBase);
-  NvBlockDevicePath = &Instance->DevicePath;
-  NvBlockDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdNvStorageVariableBlockDevicePath));
-  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &NvBlockDevicePath,
-                                  &Instance->Handle);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Couldn't locate NVM device (status: %r)\n", Status));
-    return EFI_INVALID_PARAMETER;
-  }
-  Status = gBS->OpenProtocol (
-		      Instance->Handle,
-                      &gEfiBlockIoProtocolGuid,
-		      (VOID **) &Instance->BlockIoProtocol,
-                      gImageHandle,
-                      NULL,
-                      EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                      );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Couldn't open NVM device (status: %r)\n", Status));
-    return EFI_DEVICE_ERROR;
-  }
-  WriteBackDataCacheRange (Instance, sizeof(BLOCK_VARIABLE_INSTANCE));
-
-  Handle = NULL;
-  Status = gBS->InstallMultipleProtocolInterfaces (
-		  &Handle,
-		  &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
-		  NULL
-		  );
-  if (EFI_ERROR (Status)) {
-    goto exit;
-  }
-
-  Status = FvbRead (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  Status = ValidateFvHeader (Headers);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a, Found invalid Fv Header\n", __func__));
-
-    // Erase all the block device that is reserved for variable storage
-    Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, Count, EFI_LBA_LIST_TERMINATOR);
-    if (EFI_ERROR (Status)) {
-      goto exit;
-    }
-
-    Status = InitNonVolatileVariableStore (Instance, Headers, HeadersLength);
-    if (EFI_ERROR (Status)) {
-      goto exit;
-    }
-  }
-
-  if (NvStorageSize > ((EFI_FIRMWARE_VOLUME_HEADER*)Headers)->FvLength) {
-    NvStorageSize = ((EFI_FIRMWARE_VOLUME_HEADER*)Headers)->FvLength;
-    NvStorageSize = ((NvStorageSize + Instance->Media.BlockSize - 1) / Instance->Media.BlockSize) * Instance->Media.BlockSize;
-  }
-  Status = FvbRead (&Instance->FvbProtocol, 0, 0, &NvStorageSize, NvStorageData);
-
-exit:
-  return Status;
-}
diff --git a/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.h b/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.h
deleted file mode 100644
index a8f95e8..0000000
--- a/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file  NorFlashDxe.h
-
-  Copyright (c) 2015, Linaro Ltd. All rights reserved.
-  Copyright (c) 2015, Hisilicon Ltd. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __VARIABLE_DXE_H__
-#define __VARIABLE_DXE_H__
-
-#include <Protocol/BlockIo.h>
-#include <Protocol/DiskIo.h>
-#include <Protocol/FirmwareVolumeBlock.h>
-
-#define BLOCK_VARIABLE_SIGNATURE                       SIGNATURE_32('b', 'l', 'k', '0')
-
-typedef struct _BLOCK_VARIABLE_INSTANCE                BLOCK_VARIABLE_INSTANCE;
-
-typedef struct {
-  VENDOR_DEVICE_PATH                  Vendor;
-  EFI_DEVICE_PATH_PROTOCOL            End;
-} BLOCK_DEVICE_PATH;
-
-struct _BLOCK_VARIABLE_INSTANCE {
-  UINT32                              Signature;
-  EFI_HANDLE                          Handle;
-
-  BOOLEAN                             Initialized;
-
-  UINTN                               Size;
-  EFI_LBA                             StartLba;
-
-  EFI_BLOCK_IO_MEDIA                  Media;
-  EFI_BLOCK_IO_PROTOCOL               *BlockIoProtocol;
-  EFI_DISK_IO_PROTOCOL                DiskIoProtocol;
-  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
-  EFI_DEVICE_PATH_PROTOCOL            DevicePath;
-
-  VOID*                               ShadowBuffer;
-};
-
-
-#endif /* __VARIABLE_DXE_H__ */
diff --git a/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.inf b/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.inf
deleted file mode 100644
index a9b28d6..0000000
--- a/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.inf
+++ /dev/null
@@ -1,64 +0,0 @@
-#/** @file
-#  INF file for the Variable Protocol implementation for the block device.
-#
-#  Copyright (c) 2015-2016, Linaro. All rights reserved.
-#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BlockVariableDxe
-  FILE_GUID                      = 522fc4a8-46d8-403e-a415-e2dbb1e0ebc0
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = BlockVariableDxeInitialize
-
-[Sources.common]
-  BlockVariableDxe.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  OpenPlatformPkg/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.dec
-
-[LibraryClasses]
-  ArmLib
-  BaseLib
-  BaseMemoryLib
-  CacheMaintenanceLib
-  IoLib
-  UefiDriverEntryPoint
-  UefiLib
-
-[Guids]
-  gEfiSystemNvDataFvGuid
-  gEfiVariableGuid
-  gEfiEventVirtualAddressChangeGuid
-
-[Protocols]
-  gEfiDevicePathProtocolGuid
-  gEfiBlockIoProtocolGuid			                                  ## CONSUMES
-  gEfiFirmwareVolumeBlockProtocolGuid
-
-[Pcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase                    ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize                    ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize                  ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize                    ## CONSUMES
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockCount                  ## CONSUMES
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockSize                   ## CONSUMES
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockLba                    ## CONSUMES
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockDevicePath             ## CONSUMES
-
-[Depex]
-  BEFORE gVariableRuntimeGuid
diff --git a/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.c b/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.c
new file mode 100644
index 0000000..cf82ea3
--- /dev/null
+++ b/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.c
@@ -0,0 +1,372 @@
+/**  @file
+  Implementation of driver entry point and driver binding protocol.
+
+Copyright (c) 2016, Linaro Limited. All rights reserved.
+
+This program and the accompanying materials are licensed
+and made available under the terms and conditions of the BSD License which
+accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <IndustryStandard/Pci22.h>
+
+#include <Protocol/PciIo.h>
+
+#define PCI_VENDOR_ID_RENESAS               0x1912
+#define PCI_DEVICE_ID_PD720201              0x14
+#define PCI_DEVICE_ID_PD720202              0x15
+
+#define PCI_FW_CTL_STAT_REG                 0xF4
+#define PCI_FW_CTL_DATA_REG                 0xF5
+#define PCI_EXT_ROM_CTL_REG                 0xF6
+#define PCI_FW_DATA0                        0xF8
+#define PCI_FW_DATA1                        0xFC
+
+#define PCI_FW_CTL_STAT_REG_FW_DL_ENABLE    (1U << 0)
+#define PCI_FW_CTL_STAT_REG_RESULT_CODE     (7U << 4)
+#define PCI_FW_CTL_STAT_REG_RESULT_INVALID  (0)
+#define PCI_FW_CTL_STAT_REG_RESULT_OK       (1U << 4)
+#define PCI_FW_CTL_STAT_REG_SET_DATA0       (1U << 0)
+#define PCI_FW_CTL_STAT_REG_SET_DATA1       (1U << 1)
+
+#define PCI_EXT_ROM_CTL_REG_ROM_EXISTS      (1U << 15)
+
+STATIC CONST UINT32   *mFirmwareImage;
+STATIC UINTN          mFirmwareImageSize;
+
+STATIC
+UINT8
+ReadCtlStatVal (
+  IN EFI_PCI_IO_PROTOCOL     *PciIo,
+  IN UINTN                   Offset
+  )
+{
+  UINT8       CtlStatVal;
+  EFI_STATUS  Status;
+
+  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, Offset, 1, &CtlStatVal);
+  ASSERT_EFI_ERROR (Status);
+
+  return CtlStatVal;
+}
+
+STATIC
+VOID
+WriteCtlStatVal (
+  IN EFI_PCI_IO_PROTOCOL     *PciIo,
+  IN UINTN                   Offset,
+  IN UINT8                   CtlStatVal
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, Offset, 1, &CtlStatVal);
+  ASSERT_EFI_ERROR (Status);
+}
+
+STATIC
+VOID
+WriteDataVal (
+  IN EFI_PCI_IO_PROTOCOL     *PciIo,
+  IN UINTN                   Offset,
+  IN UINT32                  DataVal
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &DataVal);
+  ASSERT_EFI_ERROR (Status);
+}
+
+STATIC
+BOOLEAN
+WaitReadCtlStatVal (
+  IN EFI_PCI_IO_PROTOCOL     *PciIo,
+  IN UINTN                   Offset,
+  IN UINT8                   Mask,
+  IN UINT8                   Val
+  )
+{
+  UINTN Timeout;
+
+  for (Timeout = 0; (ReadCtlStatVal (PciIo, Offset) & Mask) != Val; Timeout++) {
+    if (Timeout > 1000) {
+      DEBUG ((EFI_D_ERROR,
+        "%a: Timeout waiting for reg [+0x%x] & 0x%x to become 0x%x\n",
+        __FUNCTION__, Offset, Mask, Val));
+      return FALSE;
+    }
+    gBS->Stall (10);
+  }
+  return TRUE;
+}
+
+STATIC
+VOID
+DownloadPD720202Firmware (
+  IN EFI_PCI_IO_PROTOCOL     *PciIo
+  )
+{
+  UINTN   Idx;
+
+  Idx = 0;
+
+  // 1. Set "FW Download Enable" to '1b'.
+  WriteCtlStatVal (PciIo, PCI_FW_CTL_STAT_REG,
+    PCI_FW_CTL_STAT_REG_FW_DL_ENABLE);
+
+  // 2. Read "Set DATA0" and confirm it is '0b'.
+  if (!WaitReadCtlStatVal (PciIo, PCI_FW_CTL_DATA_REG,
+         PCI_FW_CTL_STAT_REG_SET_DATA0, 0)) {
+    return;
+  }
+
+  // 3. Write FW data to "DATA0".
+  WriteDataVal (PciIo, PCI_FW_DATA0, mFirmwareImage[Idx++]);
+
+  // 4. Read "Set DATA1" and confirm it is '0b'.
+  if (!WaitReadCtlStatVal (PciIo, PCI_FW_CTL_DATA_REG,
+         PCI_FW_CTL_STAT_REG_SET_DATA1, 0)) {
+    return;
+  }
+
+  // 5. Write FW data to "DATA1".
+  WriteDataVal (PciIo, PCI_FW_DATA1, mFirmwareImage[Idx++]);
+
+  // 6. Set "Set DATA0" & "Set DATA1" to '1b'.
+  WriteCtlStatVal (PciIo, PCI_FW_CTL_DATA_REG,
+    PCI_FW_CTL_STAT_REG_SET_DATA0 | PCI_FW_CTL_STAT_REG_SET_DATA1);
+
+  while (Idx < mFirmwareImageSize / sizeof(UINT32)) {
+
+    // 7. Read "Set DATA0" and confirm it is '0b'.
+    if (!WaitReadCtlStatVal (PciIo, PCI_FW_CTL_DATA_REG,
+           PCI_FW_CTL_STAT_REG_SET_DATA0, 0)) {
+      return;
+    }
+
+    // 8. Write FW data to"DATA0". Set "Set DATA0" to '1b'.
+    WriteDataVal (PciIo, PCI_FW_DATA0, mFirmwareImage[Idx++]);
+    WriteCtlStatVal (PciIo, PCI_FW_CTL_DATA_REG, PCI_FW_CTL_STAT_REG_SET_DATA0);
+
+    // 9. Read "Set DATA1" and confirm it is '0b'.
+    if (!WaitReadCtlStatVal (PciIo, PCI_FW_CTL_DATA_REG,
+           PCI_FW_CTL_STAT_REG_SET_DATA1, 0)) {
+      return;
+    }
+
+    // 10. Write FW data to"DATA1". Set "Set DATA1" to '1b'.
+    WriteDataVal (PciIo, PCI_FW_DATA1, mFirmwareImage[Idx++]);
+    WriteCtlStatVal (PciIo, PCI_FW_CTL_DATA_REG, PCI_FW_CTL_STAT_REG_SET_DATA1);
+
+    // 11. Return to step 7 and repeat the sequence from step 7 to step 10.
+  }
+
+  // 12. After writing the last data of FW, the System Software must set "FW Download Enable" to '0b'.
+  WriteCtlStatVal (PciIo, PCI_FW_CTL_STAT_REG, 0);
+
+  // 13. Read "Result Code" and confirm it is '001b'.
+  if (WaitReadCtlStatVal (PciIo, PCI_FW_CTL_STAT_REG,
+        PCI_FW_CTL_STAT_REG_RESULT_CODE, PCI_FW_CTL_STAT_REG_RESULT_OK)) {
+    DEBUG ((EFI_D_INFO, "%a: Renesas PD720202 firmware download successful\n",
+      __FUNCTION__));
+  } else {
+    DEBUG ((EFI_D_ERROR, "%a: Renesas PD720202 firmware download FAILED\n",
+      __FUNCTION__));
+  }
+}
+
+/**
+  Test to see if this driver supports ControllerHandle. This service
+  is called by the EFI boot service ConnectController(). In
+  order to make drivers as small as possible, there are a few calling
+  restrictions for this service. ConnectController() must
+  follow these calling restrictions. If any other agent wishes to call
+  Supported() it must also follow these calling restrictions.
+
+   @param  This                   Protocol instance pointer.
+   @param  ControllerHandle       Handle of device to test.
+   @param  RemainingDevicePath    Optional parameter use to pick a specific child
+                                                         device to start.
+
+   @retval EFI_SUCCESS            This driver supports this device.
+   @retval EFI_ALREADY_STARTED    This driver is already running on this device.
+   @retval other                  This driver does not support this device.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+RenesasPD720202DriverSupported (
+    IN EFI_DRIVER_BINDING_PROTOCOL    *This,
+    IN EFI_HANDLE                     Controller,
+    IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
+    )
+{
+  EFI_STATUS              Status;
+  EFI_PCI_IO_PROTOCOL     *PciIo;
+  UINT32                  PciID;
+  UINT8                   CtlStatVal;
+
+  //
+  // Check for the PCI IO Protocol
+  //
+  Status = gBS->OpenProtocol (Controller, &gEfiPciIoProtocolGuid,
+                  (VOID **)&PciIo, This->DriverBindingHandle, Controller,
+                  EFI_OPEN_PROTOCOL_BY_DRIVER);
+
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, PCI_VENDOR_ID_OFFSET,
+                        1, &PciID);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR,
+      "%a: Pci->Pci.Read() of vendor/device id failed (Status == %r)\n",
+      __FUNCTION__, Status));
+    goto CloseProtocol;
+  }
+
+  if ((PciID & 0xffff) != PCI_VENDOR_ID_RENESAS ||
+      ((PciID >> 16) != PCI_DEVICE_ID_PD720201 &&
+       (PciID >> 16) != PCI_DEVICE_ID_PD720202)) {
+    DEBUG ((EFI_D_INFO, "%a: ignoring unsupported PCI device 0x%04x:0x%04x\n",
+      __FUNCTION__, PciID & 0xffff, PciID >> 16));
+    goto CloseProtocol;
+  }
+
+  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_FW_CTL_STAT_REG,
+                        1, &CtlStatVal);
+  if (!EFI_ERROR (Status) &&
+      (CtlStatVal & PCI_FW_CTL_STAT_REG_RESULT_CODE) == PCI_FW_CTL_STAT_REG_RESULT_INVALID) {
+    //
+    // Firmware download required
+    //
+    DEBUG ((EFI_D_INFO, "%a: downloading firmware\n", __FUNCTION__));
+    DownloadPD720202Firmware (PciIo);
+  }
+
+CloseProtocol:
+  gBS->CloseProtocol (Controller, &gEfiPciIoProtocolGuid,
+         This->DriverBindingHandle, Controller);
+
+  //
+  // Always return unsupported: we are not interested in driving the device,
+  // only in having the opportunity to install the firmware before the real
+  // driver attaches to it.
+  //
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Start this driver on Controller. Not used.
+
+  @param [in] This                    Protocol instance pointer.
+  @param [in] Controller              Handle of device to work with.
+  @param [in] RemainingDevicePath     Not used, always produce all possible children.
+
+  @retval EFI_SUCCESS                 This driver is added to Controller.
+  @retval other                       This driver does not support this device.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+RenesasPD720202DriverStart (
+    IN EFI_DRIVER_BINDING_PROTOCOL  *This,
+    IN EFI_HANDLE                   Controller,
+    IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath
+    )
+{
+  //
+  // We are not interested in driving the device, we only poke the firmware
+  // in the .Supported() callback.
+  //
+  ASSERT (FALSE);
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+  Stop this driver on Controller. Not used.
+
+  @param [in] This                    Protocol instance pointer.
+  @param [in] Controller              Handle of device to stop driver on.
+  @param [in] NumberOfChildren        How many children need to be stopped.
+  @param [in] ChildHandleBuffer       Not used.
+
+  @retval EFI_SUCCESS                 This driver is removed Controller.
+  @retval EFI_DEVICE_ERROR            The device could not be stopped due to a device error.
+  @retval other                       This driver was not removed from this device.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+RenesasPD720202DriverStop (
+    IN  EFI_DRIVER_BINDING_PROTOCOL *This,
+    IN  EFI_HANDLE                  Controller,
+    IN  UINTN                       NumberOfChildren,
+    IN  EFI_HANDLE                  *ChildHandleBuffer
+    )
+{
+  ASSERT (FALSE);
+  return EFI_SUCCESS;
+}
+
+//
+// UEFI Driver Model entry point
+//
+STATIC EFI_DRIVER_BINDING_PROTOCOL RenesasPD720202DriverBinding = {
+  RenesasPD720202DriverSupported,
+  RenesasPD720202DriverStart,
+  RenesasPD720202DriverStop,
+
+  // Version values of 0xfffffff0-0xffffffff are reserved for platform/OEM
+  // specific drivers. Protocol instances with higher 'Version' properties
+  // will be used before lower 'Version' ones. XhciDxe uses version 0x30,
+  // so this driver will be called in preference, and XhciDxe will be invoked
+  // after RenesasPD720202DriverSupported returns EFI_UNSUPPORTED.
+  0xfffffff0,
+  NULL,
+  NULL
+};
+
+EFI_STATUS
+EFIAPI
+InitializeRenesasPD720202Driver (
+    IN EFI_HANDLE       ImageHandle,
+    IN EFI_SYSTEM_TABLE *SystemTable
+    )
+{
+  EFI_STATUS    Status;
+
+  //
+  // First, try to locate the firmware image. If it is missing, there is no
+  // point in proceeding.
+  //
+  Status = GetSectionFromAnyFv (&gRenesasFirmwarePD720202ImageId,
+    EFI_SECTION_RAW, 0, (VOID **) (VOID **)&mFirmwareImage,
+    &mFirmwareImageSize);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "%a: could not locate PD720202 firmware image\n",
+      __FUNCTION__));
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  return EfiLibInstallDriverBinding (ImageHandle, SystemTable,
+        &RenesasPD720202DriverBinding, NULL);
+}
diff --git a/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf b/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
new file mode 100644
index 0000000..f999bf7
--- /dev/null
+++ b/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
@@ -0,0 +1,43 @@
+##  <at> file
+# Component description file for Reneses PD720202 firmware download driver
+#
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed
+# and made available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = RenesasFirmwarePD720202
+  FILE_GUID                      = 5979ebfe-d53c-4150-a972-568231583969
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeRenesasPD720202Driver
+
+[Sources]
+  RenesasFirmwarePD720202.c
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/OpenPlatformPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  DxeServicesLib
+  UefiBootServicesTableLib
+  UefiLib
+  UefiDriverEntryPoint
+
+[Protocols]
+  gEfiPciIoProtocolGuid
+
+[Guids]
+  gRenesasFirmwarePD720202ImageId
diff --git a/Include/Guid/RamDiskGuid.h b/Include/Guid/RamDiskGuid.h
new file mode 100644
index 0000000..6d304ae
--- /dev/null
+++ b/Include/Guid/RamDiskGuid.h
@@ -0,0 +1,26 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#ifndef _RAM_DISK_GUID_H_
+#define _RAM_DISK_GUID_H_
+
+// {06ED4DD0-FF78-11d3-BDC4-00A0C94053D1}
+#define RAM_DISK_GUID \
+  {0x6ed4dd0, 0xff78, 0x11d3, {0xbd, 0xc4, 0x0, 0xa0, 0xc9, 0x40, 0x53, 0xd1}}
+
+extern EFI_GUID gRamDiskGuid;
+
+#endif
diff --git a/Include/Library/EfiTimeBaseLib.h b/Include/Library/EfiTimeBaseLib.h
new file mode 100644
index 0000000..75dd864
--- /dev/null
+++ b/Include/Library/EfiTimeBaseLib.h
@@ -0,0 +1,62 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _EFI_TIME_BASE_LIB_H_
+#define _EFI_TIME_BASE_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+
+// Seconds per unit
+#define SEC_PER_MIN                                     ((UINTN)    60)
+#define SEC_PER_HOUR                                    ((UINTN)  3600)
+#define SEC_PER_DAY                                     ((UINTN) 86400)
+
+BOOLEAN
+EFIAPI
+IsLeapYear (
+  IN  EFI_TIME  *Time
+  );
+
+BOOLEAN
+EFIAPI
+IsDayValid (
+  IN  EFI_TIME  *Time
+  );
+
+BOOLEAN
+EFIAPI
+IsTimeValid (
+  IN  EFI_TIME  *Time
+  );
+
+/**
+  Converts Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 UTC) to EFI_TIME
+ **/
+VOID
+EFIAPI
+EpochToEfiTime (
+  IN  UINTN     EpochSeconds,
+  OUT EFI_TIME  *Time
+  );
+
+/**
+  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 UTC)
+ **/
+UINTN
+EfiTimeToEpoch (
+  IN  EFI_TIME  *Time
+  );
+
+#endif
diff --git a/Include/Library/UsbSerialNumberLib.h b/Include/Library/UsbSerialNumberLib.h
new file mode 100644
index 0000000..3ae594b
--- /dev/null
+++ b/Include/Library/UsbSerialNumberLib.h
@@ -0,0 +1,53 @@
+/** @file
+
+  Copyright (c) 2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __USB_SERIAL_NUMBER_LIB_H__
+#define __USB_SERIAL_NUMBER_LIB_H__
+
+#include <Uefi.h>
+
+#define SERIAL_NUMBER_SIZE                      17
+
+typedef struct {
+  UINT64        Magic;
+  UINT64        Data;
+  CHAR16        UnicodeSN[SERIAL_NUMBER_SIZE];
+} RANDOM_SERIAL_NUMBER;
+
+EFI_STATUS
+GenerateUsbSNBySeed (
+  IN  UINT32                  Seed,
+  OUT RANDOM_SERIAL_NUMBER   *RandomSN
+  );
+
+EFI_STATUS
+GenerateUsbSN (
+  OUT CHAR16                 *UnicodeSN
+  );
+
+EFI_STATUS
+LoadSNFromBlock (
+  IN  EFI_HANDLE              FlashHandle,
+  IN  EFI_LBA                 Lba,
+  OUT CHAR16                 *UnicodeSN
+  );
+
+EFI_STATUS
+StoreSNToBlock (
+  IN EFI_HANDLE               FlashHandle,
+  IN EFI_LBA                  Lba,
+  IN CHAR16                  *UnicodeSN
+  );
+
+#endif /* __USB_SERIAL_NUMBER_LIB_H__ */
diff --git a/Include/Protocol/DwUsb.h b/Include/Protocol/DwUsb.h
index 868d956..040e126 100644
--- a/Include/Protocol/DwUsb.h
+++ b/Include/Protocol/DwUsb.h
@@ -1,53 +1,81 @@
-/** @file
-
-  Copyright (c) 2015-2016, Linaro. All rights reserved.
-  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __DW_USB_H__
-#define __DW_USB_H__
-
-//
-// Protocol GUID
-//
-#define DW_USB_PROTOCOL_GUID { 0x109fa264, 0x7811, 0x4862, { 0xa9, 0x73, 0x4a, 0xb2, 0xef, 0x2e, 0xe2, 0xff }}
-
-//
-// Protocol interface structure
-//
-typedef struct _DW_USB_PROTOCOL  DW_USB_PROTOCOL;
-
-#define USB_HOST_MODE    0
-#define USB_DEVICE_MODE  1
-#define USB_CABLE_NOT_ATTACHED  2
-
-typedef
-EFI_STATUS
-(EFIAPI *DW_USB_GET_SERIAL_NO) (
-  OUT CHAR16                           *SerialNo,
-  OUT UINT8                            *Length
-  );
-
-typedef
-EFI_STATUS
-(EFIAPI *DW_USB_PHY_INIT) (
-  IN UINT8                           Mode
-  );
-
-struct _DW_USB_PROTOCOL {
-  DW_USB_GET_SERIAL_NO                 Get;
-  DW_USB_PHY_INIT                      PhyInit;
-};
-
-extern EFI_GUID gDwUsbProtocolGuid;
-
-#endif
+/** @file
+
+  Copyright (c) 2015-2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __DW_USB_H__
+#define __DW_USB_H__
+
+//
+// Protocol GUID
+//
+#define DW_USB_PROTOCOL_GUID { 0x109fa264, 0x7811, 0x4862, { 0xa9, 0x73, 0x4a, 0xb2, 0xef, 0x2e, 0xe2, 0xff }}
+
+//
+// Protocol interface structure
+//
+typedef struct _DW_USB_PROTOCOL  DW_USB_PROTOCOL;
+
+#define USB_HOST_MODE                 0
+#define USB_DEVICE_MODE               1
+#define USB_CABLE_NOT_ATTACHED        2
+
+#define LANG_LENGTH                   8
+#define MANU_FACTURER_STRING_LENGTH   32
+#define PRODUCT_STRING_LENGTH         32
+#define SERIAL_STRING_LENGTH          17
+
+typedef
+EFI_STATUS
+(EFIAPI *DW_USB_GET_LANG) (
+  OUT CHAR16                           *Lang,
+  OUT UINT8                            *Length
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *DW_USB_GET_MANU_FACTURER) (
+  OUT CHAR16                           *ManuFacturer,
+  OUT UINT8                            *Length
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *DW_USB_GET_PRODUCT) (
+  OUT CHAR16                           *Product,
+  OUT UINT8                            *Length
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *DW_USB_GET_SERIAL_NO) (
+  OUT CHAR16                           *SerialNo,
+  OUT UINT8                            *Length
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *DW_USB_PHY_INIT) (
+  IN UINT8                             Mode
+  );
+
+struct _DW_USB_PROTOCOL {
+  DW_USB_GET_LANG                      GetLang;
+  DW_USB_GET_MANU_FACTURER             GetManuFacturer;
+  DW_USB_GET_PRODUCT                   GetProduct;
+  DW_USB_GET_SERIAL_NO                 GetSerialNo;
+  DW_USB_PHY_INIT                      PhyInit;
+};
+
+extern EFI_GUID gDwUsbProtocolGuid;
+
+#endif
diff --git a/Include/Protocol/PlatformDwMmc.h b/Include/Protocol/PlatformDwMmc.h
new file mode 100644
index 0000000..fe2259b
--- /dev/null
+++ b/Include/Protocol/PlatformDwMmc.h
@@ -0,0 +1,78 @@
+/** @file
+
+  Copyright (c) 2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PLATFORM_DW_MMC_H__
+#define __PLATFORM_DW_MMC_H__
+
+typedef enum {
+  RemovableSlot,
+  EmbeddedSlot,
+  SharedBusSlot,
+  UnknownSlot
+} EFI_SD_MMC_SLOT_TYPE;
+
+typedef enum {
+  UnknownCardType,
+  SdCardType,
+  SdioCardType,
+  MmcCardType,
+  EmmcCardType
+} SD_MMC_CARD_TYPE;
+
+typedef struct {
+  UINT32        DefaultSpeed:1;    // bit 0
+  UINT32        HighSpeed:1;       // bit 1
+  UINT32        Sdr12:1;           // bit 2
+  UINT32        Sdr25:1;           // bit 3
+  UINT32        Sdr50:1;           // bit 4
+  UINT32        Sdr104:1;          // bit 5
+  UINT32        Ddr50:1;           // bit 6
+  UINT32        SysBus64:1;        // bit 7
+  UINT32        BusWidth:4;        // bit 11:8
+  UINT32        SlotType:2;        // bit 13:12
+  UINT32        CardType:3;        // bit 16:14
+  UINT32        Voltage18:1;       // bit 17
+  UINT32        Voltage30:1;       // bit 18
+  UINT32        Voltage33:1;       // bit 19
+  UINT32        BaseClkFreq;
+  EFI_HANDLE    Controller;
+} DW_MMC_HC_SLOT_CAP;
+
+//
+// Protocol interface structure
+//
+typedef struct _PLATFORM_DW_MMC_PROTOCOL       PLATFORM_DW_MMC_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_DW_MMC_GET_CAPABILITY) (
+  IN     EFI_HANDLE             Controller,
+  IN     UINT8                  Slot,
+     OUT DW_MMC_HC_SLOT_CAP     *Capability
+  );
+
+typedef
+BOOLEAN
+(EFIAPI *PLATFORM_DW_MMC_CARD_DETECT) (
+  IN UINT8                      Slot
+  );
+
+struct _PLATFORM_DW_MMC_PROTOCOL {
+  PLATFORM_DW_MMC_GET_CAPABILITY               GetCapability;
+  PLATFORM_DW_MMC_CARD_DETECT                  CardDetect;
+};
+
+extern EFI_GUID gPlatformDwMmcProtocolGuid;
+
+#endif /* __PLATFORM_DW_MMC_H__ */
diff --git a/Include/Protocol/PlatformVirtualKeyboard.h b/Include/Protocol/PlatformVirtualKeyboard.h
new file mode 100644
index 0000000..8231798
--- /dev/null
+++ b/Include/Protocol/PlatformVirtualKeyboard.h
@@ -0,0 +1,65 @@
+/** @file
+
+  Copyright (c) 2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PLATFORM_VIRTUAL_KEYBOARD_H__
+#define __PLATFORM_VIRTUAL_KEYBOARD_H__
+
+//
+// Protocol interface structure
+//
+typedef struct _PLATFORM_VIRTUAL_KBD_PROTOCOL  PLATFORM_VIRTUAL_KBD_PROTOCOL;
+
+typedef struct _VIRTUAL_KBD_KEY                VIRTUAL_KBD_KEY;
+
+#define VIRTUAL_KEYBOARD_KEY_SIGNATURE         SIGNATURE_32 ('v', 'k', 'b', 'd')
+
+struct _VIRTUAL_KBD_KEY {
+  UINTN                    Signature;
+  EFI_INPUT_KEY            Key;
+};
+
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_VIRTUAL_KBD_REGISTER) (
+  IN VOID
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_VIRTUAL_KBD_RESET) (
+  IN VOID
+  );
+
+typedef
+BOOLEAN
+(EFIAPI *PLATFORM_VIRTUAL_KBD_QUERY) (
+  IN VIRTUAL_KBD_KEY                           *VirtualKey
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_VIRTUAL_KBD_CLEAR) (
+  IN VIRTUAL_KBD_KEY                           *VirtualKey
+  );
+
+struct _PLATFORM_VIRTUAL_KBD_PROTOCOL {
+  PLATFORM_VIRTUAL_KBD_REGISTER                Register;
+  PLATFORM_VIRTUAL_KBD_RESET                   Reset;
+  PLATFORM_VIRTUAL_KBD_QUERY                   Query;
+  PLATFORM_VIRTUAL_KBD_CLEAR                   Clear;
+};
+
+extern EFI_GUID gPlatformVirtualKeyboardProtocolGuid;
+
+#endif /* __PLATFORM_VIRTUAL_KEYBOARD_H__ */
diff --git a/Library/EfiTimeBaseLib/EfiTimeBaseLib.c b/Library/EfiTimeBaseLib/EfiTimeBaseLib.c
new file mode 100644
index 0000000..e06606b
--- /dev/null
+++ b/Library/EfiTimeBaseLib/EfiTimeBaseLib.c
@@ -0,0 +1,172 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiSpec.h>
+#include <Library/DebugLib.h>
+#include <Library/EfiTimeBaseLib.h>
+
+// Define EPOCH (1970-JANUARY-01) in the Julian Date representation
+#define EPOCH_JULIAN_DATE                               2440588
+
+BOOLEAN
+EFIAPI
+IsLeapYear (
+  IN EFI_TIME *Time
+  )
+{
+  if (Time->Year % 4 == 0) {
+    if (Time->Year % 100 == 0) {
+      if (Time->Year % 400 == 0) {
+        return TRUE;
+      } else {
+        return FALSE;
+      }
+    } else {
+      return TRUE;
+    }
+  } else {
+    return FALSE;
+  }
+}
+
+BOOLEAN
+EFIAPI
+IsDayValid (
+  IN EFI_TIME *Time
+  )
+{
+  INTN DayOfMonth[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+  if (Time->Day < 1 ||
+      Time->Day > DayOfMonth[Time->Month - 1] ||
+      (Time->Month == 2 && (!IsLeapYear (Time) && Time->Day > 28))
+     ) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+BOOLEAN
+EFIAPI
+IsTimeValid(
+  IN EFI_TIME *Time
+  )
+{
+  // Check the input parameters are within the range specified by UEFI
+  if ((Time->Year   < 2000) ||
+     (Time->Year   > 2099) ||
+     (Time->Month  < 1   ) ||
+     (Time->Month  > 12  ) ||
+     (!IsDayValid (Time)    ) ||
+     (Time->Hour   > 23  ) ||
+     (Time->Minute > 59  ) ||
+     (Time->Second > 59  ) ||
+     (Time->Nanosecond > 999999999) ||
+     (!((Time->TimeZone == EFI_UNSPECIFIED_TIMEZONE) || ((Time->TimeZone >= -1440) && (Time->TimeZone <= 1440)))) ||
+     (Time->Daylight & (~(EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT)))
+  ) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/**
+  Converts Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 UTC) to EFI_TIME
+ **/
+VOID
+EpochToEfiTime (
+  IN  UINTN     EpochSeconds,
+  OUT EFI_TIME  *Time
+  )
+{
+  UINTN         a;
+  UINTN         b;
+  UINTN         c;
+  UINTN         d;
+  UINTN         g;
+  UINTN         j;
+  UINTN         m;
+  UINTN         y;
+  UINTN         da;
+  UINTN         db;
+  UINTN         dc;
+  UINTN         dg;
+  UINTN         hh;
+  UINTN         mm;
+  UINTN         ss;
+  UINTN         J;
+
+  J  = (EpochSeconds / 86400) + 2440588;
+  j  = J + 32044;
+  g  = j / 146097;
+  dg = j % 146097;
+  c  = (((dg / 36524) + 1) * 3) / 4;
+  dc = dg - (c * 36524);
+  b  = dc / 1461;
+  db = dc % 1461;
+  a  = (((db / 365) + 1) * 3) / 4;
+  da = db - (a * 365);
+  y  = (g * 400) + (c * 100) + (b * 4) + a;
+  m  = (((da * 5) + 308) / 153) - 2;
+  d  = da - (((m + 4) * 153) / 5) + 122;
+
+  Time->Year  = y - 4800 + ((m + 2) / 12);
+  Time->Month = ((m + 2) % 12) + 1;
+  Time->Day   = d + 1;
+
+  ss = EpochSeconds % 60;
+  a  = (EpochSeconds - ss) / 60;
+  mm = a % 60;
+  b = (a - mm) / 60;
+  hh = b % 24;
+
+  Time->Hour        = hh;
+  Time->Minute      = mm;
+  Time->Second      = ss;
+  Time->Nanosecond  = 0;
+
+}
+
+/**
+  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 UTC)
+ **/
+UINTN
+EfiTimeToEpoch (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINTN a;
+  UINTN y;
+  UINTN m;
+  UINTN JulianDate;  // Absolute Julian Date representation of the supplied Time
+  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
+  UINTN EpochSeconds;
+
+  a = (14 - Time->Month) / 12 ;
+  y = Time->Year + 4800 - a;
+  m = Time->Month + (12*a) - 3;
+
+  JulianDate = Time->Day + ((153*m + 2)/5) + (365*y) + (y/4) - (y/100) + (y/400) - 32045;
+
+  ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
+  EpochDays = JulianDate - EPOCH_JULIAN_DATE;
+
+  EpochSeconds = (EpochDays * SEC_PER_DAY) + ((UINTN)Time->Hour * SEC_PER_HOUR) + (Time->Minute * SEC_PER_MIN) + Time->Second;
+
+  return EpochSeconds;
+}
diff --git a/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf b/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
new file mode 100644
index 0000000..18dce73
--- /dev/null
+++ b/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
@@ -0,0 +1,34 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = EfiTimeBaseLib
+  FILE_GUID                      = B1B07E01-6896-448C-8E75-F0E119ABDF49
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = EfiTimeBaseLib
+
+[Sources.common]
+  EfiTimeBaseLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/OpenPlatformPkg.dec
+
+[LibraryClasses]
+  DebugLib
+
+[Pcd]
diff --git a/Library/UsbSerialNumberLib/UsbSerialNumberLib.c b/Library/UsbSerialNumberLib/UsbSerialNumberLib.c
new file mode 100644
index 0000000..2727d5c
--- /dev/null
+++ b/Library/UsbSerialNumberLib/UsbSerialNumberLib.c
@@ -0,0 +1,261 @@
+/** @file
+
+  Copyright (c) 2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+
+#include <Library/ArmGenericTimerCounterLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UsbSerialNumberLib.h>
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/DevicePath.h>
+
+
+#define SERIAL_NUMBER_SIZE               17
+
+#define RANDOM_MAX                       0x7FFFFFFFFFFFFFFF
+#define RANDOM_MAGIC                     0x9A4DBEAF
+
+STATIC
+EFI_STATUS
+GenerateRandomData (
+  IN  UINT32              Seed,
+  OUT UINT64             *RandomData
+  )
+{
+  INT64                   Quotient, Remainder, Tmp;
+
+  if (RandomData == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Quotient = (INT64) Seed / 127773;
+  Remainder = (INT64) Seed % 127773;
+  Tmp = (16807 * Remainder) - (2836 * Quotient);
+  if (Tmp < 0) {
+    Tmp += RANDOM_MAX;
+  }
+  Tmp = Tmp % ((UINT64)RANDOM_MAX + 1);
+  *RandomData = (UINT64)Tmp;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GenerateUsbSNBySeed (
+  IN  UINT32                  Seed,
+  OUT RANDOM_SERIAL_NUMBER   *RandomSN
+  )
+{
+  EFI_STATUS               Status;
+  UINT64                   Tmp;
+
+  if (RandomSN == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ZeroMem (RandomSN, sizeof (RANDOM_SERIAL_NUMBER));
+  Status = GenerateRandomData (Seed, &Tmp);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  RandomSN->Data = (Tmp << 32) | Seed;
+  UnicodeSPrint (RandomSN->UnicodeSN, SERIAL_NUMBER_SIZE * sizeof (CHAR16), L"%lx", RandomSN->Data);
+  RandomSN->Magic = RANDOM_MAGIC;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GenerateUsbSN (
+  OUT CHAR16                  *UnicodeSN
+  )
+{
+  EFI_STATUS               Status;
+  UINT64                   Tmp;
+  UINT32                   Seed;
+  RANDOM_SERIAL_NUMBER     RandomSN;
+
+  if (UnicodeSN == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  ZeroMem (&RandomSN, sizeof (RANDOM_SERIAL_NUMBER));
+  Seed = ArmGenericTimerGetSystemCount ();
+  Status = GenerateRandomData (Seed, &Tmp);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  RandomSN.Data = (Tmp << 32) | Seed;
+  UnicodeSPrint (RandomSN.UnicodeSN, SERIAL_NUMBER_SIZE * sizeof (CHAR16), L"%lx", RandomSN.Data);
+  StrCpyS (UnicodeSN, SERIAL_NUMBER_SIZE * sizeof (CHAR16), RandomSN.UnicodeSN);
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+LoadSNFromBlock (
+  IN  EFI_HANDLE              FlashHandle,
+  IN  EFI_LBA                 Lba,
+  OUT CHAR16                 *UnicodeSN
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_BLOCK_IO_PROTOCOL      *BlockIoProtocol;
+  VOID                       *DataPtr;
+  BOOLEAN                     Found = FALSE;
+  UINT32                      Seed;
+  RANDOM_SERIAL_NUMBER       *RandomSN;
+  UINTN                       NumPages;
+  CHAR16                      UnicodeStr[SERIAL_NUMBER_SIZE];
+
+  if (UnicodeSN == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = gBS->OpenProtocol (
+                  FlashHandle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &BlockIoProtocol,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_WARN, "Warning: Couldn't open block device (status: %r)\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  NumPages = EFI_SIZE_TO_PAGES (BlockIoProtocol->Media->BlockSize);
+  DataPtr = AllocatePages (NumPages);
+  if (DataPtr == NULL) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+  Status = BlockIoProtocol->ReadBlocks (
+                              BlockIoProtocol,
+                              BlockIoProtocol->Media->MediaId,
+                              Lba,
+                              BlockIoProtocol->Media->BlockSize,
+                              DataPtr
+                              );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_WARN, "Warning: Failed on reading blocks\n"));
+    goto Exit;
+  }
+
+  Seed = ArmGenericTimerGetSystemCount ();
+  RandomSN = (RANDOM_SERIAL_NUMBER *)DataPtr;
+  if (RandomSN->Magic == RANDOM_MAGIC) {
+    Found = TRUE;
+    // Verify the unicode string.
+    ZeroMem (UnicodeStr, SERIAL_NUMBER_SIZE * sizeof (CHAR16));
+    UnicodeSPrint (UnicodeStr, SERIAL_NUMBER_SIZE * sizeof (CHAR16), L"%lx", RandomSN->Data);
+    if (StrLen (RandomSN->UnicodeSN) != StrLen (UnicodeStr)) {
+      Found = FALSE;
+    }
+    if (StrnCmp (RandomSN->UnicodeSN, UnicodeStr, StrLen (UnicodeStr)) != 0) {
+      Found = FALSE;
+    }
+  }
+  if (Found == FALSE) {
+    Status = GenerateUsbSNBySeed (Seed, RandomSN);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_WARN, "Warning: Failed to generate serial number\n"));
+      goto Exit;
+    }
+    // Update SN to block device
+    Status = BlockIoProtocol->WriteBlocks (
+                                BlockIoProtocol,
+                                BlockIoProtocol->Media->MediaId,
+                                Lba,
+                                BlockIoProtocol->Media->BlockSize,
+                                DataPtr
+                                );
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_WARN, "Warning: Failed on writing blocks\n"));
+      goto Exit;
+    }
+  }
+  CopyMem (UnicodeSN, RandomSN->UnicodeSN, SERIAL_NUMBER_SIZE * sizeof (CHAR16));
+Exit:
+  FreePages (DataPtr, NumPages);
+  return Status;
+}
+
+EFI_STATUS
+StoreSNToBlock (
+  IN EFI_HANDLE               FlashHandle,
+  IN EFI_LBA                  Lba,
+  IN CHAR16                  *UnicodeSN
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_BLOCK_IO_PROTOCOL      *BlockIoProtocol;
+  VOID                       *DataPtr;
+  UINTN                       NumPages;
+  RANDOM_SERIAL_NUMBER       *RandomSN;
+  CHAR16                      UnicodeStr[SERIAL_NUMBER_SIZE];
+
+  if (UnicodeSN == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = gBS->OpenProtocol (
+                  FlashHandle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &BlockIoProtocol,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_WARN, "Warning: Couldn't open block device (status: %r)\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+  NumPages = EFI_SIZE_TO_PAGES (BlockIoProtocol->Media->BlockSize);
+  DataPtr = AllocatePages (NumPages);
+  if (DataPtr == NULL) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+  ZeroMem (DataPtr, BlockIoProtocol->Media->BlockSize);
+  RandomSN = (RANDOM_SERIAL_NUMBER *)DataPtr;
+  RandomSN->Magic = RANDOM_MAGIC;
+  StrnCpyS (RandomSN->UnicodeSN, SERIAL_NUMBER_SIZE * sizeof (CHAR16), UnicodeSN, StrSize (UnicodeSN));
+  RandomSN->Data = StrHexToUint64 (RandomSN->UnicodeSN);
+
+  // Verify the unicode string.
+  ZeroMem (UnicodeStr, SERIAL_NUMBER_SIZE * sizeof (CHAR16));
+  UnicodeSPrint (UnicodeStr, SERIAL_NUMBER_SIZE * sizeof (CHAR16), L"%lx", RandomSN->Data);
+  if (StrLen (RandomSN->UnicodeSN) != StrLen (UnicodeStr)) {
+    Status = EFI_INVALID_PARAMETER;
+    goto Exit;
+  }
+  if (StrnCmp (RandomSN->UnicodeSN, UnicodeStr, StrLen (UnicodeStr)) != 0) {
+    Status = EFI_INVALID_PARAMETER;
+    goto Exit;
+  }
+
+  Status = BlockIoProtocol->WriteBlocks (
+                              BlockIoProtocol,
+                              BlockIoProtocol->Media->MediaId,
+                              Lba,
+                              BlockIoProtocol->Media->BlockSize,
+                              DataPtr
+                              );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_WARN, "Warning: Failed on writing blocks\n"));
+    goto Exit;
+  }
+Exit:
+  FreePages (DataPtr, NumPages);
+  return Status;
+}
diff --git a/Library/UsbSerialNumberLib/UsbSerialNumberLib.inf b/Library/UsbSerialNumberLib/UsbSerialNumberLib.inf
new file mode 100644
index 0000000..9129de9
--- /dev/null
+++ b/Library/UsbSerialNumberLib/UsbSerialNumberLib.inf
@@ -0,0 +1,44 @@
+#/** @file
+#
+#  Copyright (c) 2017, Linaro. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = UsbSerialNumberLib
+  FILE_GUID                      = 88709c56-2a76-4a13-8bcf-427970b7e32a
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = UsbSerialNumberLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = ARM AARCH64
+
+[Sources]
+  UsbSerialNumberLib.c
+
+[LibraryClasses]
+  ArmGenericTimerCounterLib
+  BaseMemoryLib
+  DebugLib
+  MemoryAllocationLib
+  UefiBootServicesTableLib
+  UefiLib
+
+[Protocols]
+  gEfiBlockIoProtocolGuid
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
diff --git a/OpenPlatformPkg.dec b/OpenPlatformPkg.dec
new file mode 100644
index 0000000..aa4fa20
--- /dev/null
+++ b/OpenPlatformPkg.dec
@@ -0,0 +1,45 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = OpenPlatformPkg
+  PACKAGE_GUID                   = a8f10bf6-2f6f-11e6-b84e-bfcd6876df82
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  Include
+
+[Ppis]
+
+[Protocols]
+
+[Guids]
+  gOpenPlatformTokenSpaceGuid = {0xCD7CC258, 0x31DB, 0x11E6, {0x9F, 0xD3, 0x63, 0xB0, 0xB8, 0xEF, 0xD7, 0xB6}}
+  ## Vendor GUID for RAM disk device path
+  gRamDiskGuid = {0x6ED4DD0, 0xFF78, 0x11D3, {0xBD, 0xC4, 0x00, 0xA0, 0xC9, 0x40, 0x53, 0xD1}}
+
+  ## GUID for RenesasFirmwarePD720202 firmware image
+  gRenesasFirmwarePD720202ImageId = {0xA059EBC4, 0xD73D, 0x4279, {0x81,0xBF,0xE4,0xA8,0x93,0x08,0xB9,0x23}}
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild]
+  ## Indicates the size in MB for RAM disk.
+  gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|0|UINT32|0x00000001
+  gOpenPlatformTokenSpaceGuid.PcdAndroidFastbootFile|{ 0x2a, 0x50, 0x88, 0x95, 0x70, 0x53, 0xe3, 0x11, 0x86, 0x31, 0xd7, 0xc5, 0x95, 0x13, 0x64, 0xc8 }|VOID*|0x00000002
+  gOpenPlatformTokenSpaceGuid.PcdAndroidBootFile|{ 0x36, 0x8b, 0x73, 0x3a, 0xc5, 0xb9, 0x63, 0x47, 0xab, 0xbd, 0x6c, 0xbd, 0x4b, 0x25, 0xf9, 0xff }|VOID*|0x00000003
+
+[PcdsFeatureFlag]
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf b/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
index ecb4ca6..34a2c63 100644
--- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
+++ b/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
@@ -1,34 +1,29 @@
-##
-#  Component description file for PlatformAcpiTables module.
-#
-#  ACPI table data and ASL sources required to boot the platform.
-#
-#  Copyright (c) 2013, Linaro Ltd.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = PlatformAcpiTables
-  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
-  MODULE_TYPE                    = USER_DEFINED
-  VERSION_STRING                 = 1.0
-
-[Sources]
-  apic.asl
-  dsdt.asl
-  facp.asl
-  gtdt.asl
-  dbg2.asl
-  spcr.asl
-
-[Packages]
-  MdePkg/MdePkg.dec
+#/** @file
+#
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AcpiAml
+  FILE_GUID                      = 2df2a2ee-5f34-4dea-b4b6-da724e455f33
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  Dsdt.asl
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
diff --git a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000..12e0444
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf
@@ -0,0 +1,89 @@
+#/** @file
+#  Sample ACPI Platform Driver
+#
+#  Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+#
+#  Derived from:
+#   MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AmdStyxAcpiLib
+  FILE_GUID                      = 74850e9e-371c-43af-b1fe-794d61505ad0
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = AmdStyxAcpiLib
+
+[Sources]
+  Gtdt.c
+  Fadt.c
+  Dbg2.c
+  Spcr.c
+  Madt.c
+  Mcfg.c
+  Csrt.c
+  Dsdt.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  PcdLib
+  DebugLib
+  UefiBootServicesTableLib
+
+[Protocols]
+  gAmdMpCoreInfoProtocolGuid         ## CONSUMED
+
+[Pcd]
+  gAmdStyxTokenSpaceGuid.PcdSocCoreCount
+  gAmdStyxTokenSpaceGuid.PcdSocCpuId
+  gAmdStyxTokenSpaceGuid.PcdEthMacA
+  gAmdStyxTokenSpaceGuid.PcdEthMacB
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase
+  gAmdStyxTokenSpaceGuid.PcdGicVersion
+  gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase
+  gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase
+  gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt
+  gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase
+  gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase
+  gAmdStyxTokenSpaceGuid.PcdCntControlBase
+  gAmdStyxTokenSpaceGuid.PcdCntReadBase
+  gAmdStyxTokenSpaceGuid.PcdCntCTLBase
+  gAmdStyxTokenSpaceGuid.PcdCntBase0
+  gAmdStyxTokenSpaceGuid.PcdCntEL0Base0
+  gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase
+  gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase
+  gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV
+  gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV
+  gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+  gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion
+  gAmdStyxTokenSpaceGuid.PcdSata1PortCount
+
+[Depex]
+  gAmdMpCoreInfoProtocolGuid
diff --git a/Platforms/AMD/Styx/AcpiTables/Csrt.c b/Platforms/AMD/Styx/AcpiTables/Csrt.c
new file mode 100644
index 0000000..f25f90d
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Csrt.c
@@ -0,0 +1,107 @@
+/** @file
+
+  ACPI Memory mapped configuration space base address Description Table (MCFG).
+  Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+  downloadable at http://www.pcisig.com/home
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+  This program and the accompanying materials are licensed and
+  made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the
+  license may be found at http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+//
+// CSRT for ARM_CCN504 (L3 CACHE)
+//
+#define AMD_ACPI_ARM_CCN504_CSRT_REVISION 0
+#define AMD_ACPI_ARM_CCN504_VENDOR_ID     SIGNATURE_32('A','R','M','H')
+#define AMD_ACPI_ARM_CCN504_DEVICE_ID     0x510
+#define AMD_ACPI_ARM_CCN504_RESOURCE_TYPE 0x04
+#define AMD_ACPI_ARM_CCN504_DESC_VERSION  1
+#define AMD_ACPI_ARM_CCN504_HNF_COUNT     8
+#define AMD_ACPI_ARM_CCN504_BASE_ADDR     0xE8000000ULL
+#define AMD_ACPI_ARM_CCN504_CACHE_SIZE    0x00800000ULL
+
+//
+// Ensure proper (byte-packed) structure formats
+//
+#pragma pack(push, 1)
+
+typedef struct {
+  UINT32  Version;
+  UINT8   HnfRegionCount;
+  UINT8   Reserved[3];
+  UINT64  BaseAddress;
+  UINT64  CacheSize;
+} AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR;
+
+typedef struct {
+  UINT32  Length;
+  UINT16  ResourceType;
+  UINT16  ResourceSubtype;
+  UINT32  UID;
+  AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR Ccn504Desc;
+} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR;
+
+typedef struct {
+  UINT32  Length;
+  UINT32  VendorId;
+  UINT32  SubvendorId;
+  UINT16  DeviceId;
+  UINT16  SubdeviceId;
+  UINT16  Revision;
+  UINT8   Reserved[2];
+  UINT32  SharedInfoLength;
+  AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR RsrcDesc;
+} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP;
+
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP RsrcGroup;
+} AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE;
+
+
+AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE AcpiCsrt = {
+   AMD_ACPI_HEADER (EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE,
+                    AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE,
+                    AMD_ACPI_ARM_CCN504_CSRT_REVISION),
+  { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP), // UINT32  RsrcGroup.Length
+    AMD_ACPI_ARM_CCN504_VENDOR_ID,                    // UINT32  RsrcGroup.VendorId
+    0,                                                // UINT32  RsrcGroup.SubvendorId
+    AMD_ACPI_ARM_CCN504_DEVICE_ID,                    // UINT16  RsrcGroup.DeviceId
+    0,                                                // UINT16  RsrcGroup.SubdeviceId
+    0,                                                // UINT16  RsrcGroup.Revision
+    { 0 },                                            // UINT8   RsrcGroup.Reserved[]
+    0,                                                // UINT32  RsrcGroup.SharedInfoLength
+    { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR),  // UINT32  RsrcDesc.Length
+      AMD_ACPI_ARM_CCN504_RESOURCE_TYPE,                      // UINT16  RsrcDesc.ResourceType
+      0,                                                      // UINT16  RsrcDesc.ResourceSubtype
+      0,                                                      // UINT32  RsrcDesc.UID
+      { AMD_ACPI_ARM_CCN504_DESC_VERSION,                     // UINT32  Ccn504Desc.Version
+        AMD_ACPI_ARM_CCN504_HNF_COUNT,                        // UINT8   Ccn504Desc.HnfRegionCount
+        { 0 },                                                // UINT8   Ccn504Desc.Reserved[]
+        AMD_ACPI_ARM_CCN504_BASE_ADDR,                        // UINT64  Ccn504Desc.BaseAddress
+        AMD_ACPI_ARM_CCN504_CACHE_SIZE,                       // UINT64  Ccn504Desc.CacheSize
+      },
+    },
+  },
+};
+
+#pragma pack(pop)
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+CsrtHeader (
+  VOID
+  )
+{
+  return &AcpiCsrt.Header;
+}
diff --git a/Platforms/AMD/Styx/AcpiTables/Dbg2.c b/Platforms/AMD/Styx/AcpiTables/Dbg2.c
new file mode 100644
index 0000000..5d6cf82
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Dbg2.c
@@ -0,0 +1,114 @@
+/** @file
+
+  Microsoft Debug Port Table 2 (DBG2)
+  © 2012 Microsoft. All rights reserved.<BR>
+  http://go.microsoft.com/fwlink/p/?linkid=403551
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/DebugPort2Table.h>
+
+#pragma pack(push, 1)
+
+#define EFI_ACPI_DBG2_REVISION                     0
+#define DBG2_NUM_DEBUG_PORTS                       1
+#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS   1
+#define DBG2_NAMESPACESTRING_FIELD_SIZE            8
+#define DBG2_OEM_DATA_FIELD_SIZE                   0
+#define DBG2_OEM_DATA_FIELD_OFFSET                 0
+
+#define DBG2_DEBUG_PORT_SUBTYPE_PL011              0x0003        // Sub type for Pl011
+#define DBG2_DEBUG_PORT_SUBTYPE_UEFI               0x0007        // Sub type for UEFI Debug Port
+#define PL011_UART_LENGTH                          0x1000
+
+#define NAME_STR_UART1     {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'}
+#define NAME_STR_UEFI      {'U', 'E', 'F', 'I', '\0', '\0', '\0', '\0'}
+
+
+typedef struct {
+  EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT     Dbg2Device;
+  EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE            BaseAddressRegister;
+  UINT32                                            AddressSize;
+  UINT8                                             NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+  EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE           Description;
+  DBG2_DEBUG_DEVICE_INFORMATION                     Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS];
+} DBG2_TABLE;
+
+
+#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) {                                           \
+    {                                                                                                                        \
+      EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,              /* UINT8     Revision; */                         \
+      sizeof (DBG2_DEBUG_DEVICE_INFORMATION),                              /* UINT16    Length; */                           \
+      NumReg,                                                              /* UINT8     NumberofGenericAddressRegisters; */  \
+      DBG2_NAMESPACESTRING_FIELD_SIZE,                                     /* UINT16    NameSpaceStringLength; */            \
+      OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),           /* UINT16    NameSpaceStringOffset; */            \
+      DBG2_OEM_DATA_FIELD_SIZE,                                            /* UINT16    OemDataLength; */                    \
+      DBG2_OEM_DATA_FIELD_OFFSET,                                          /* UINT16    OemDataOffset; */                    \
+      EFI_ACPI_DBG2_PORT_TYPE_SERIAL,                                      /* UINT16    Port Type; */                        \
+      SubType,                                                             /* UINT16    Port Subtype; */                     \
+      {EFI_ACPI_RESERVED_BYTE,  EFI_ACPI_RESERVED_BYTE},                   /* UINT8     Reserved[2]; */                      \
+      OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),       /* UINT16    BaseAddressRegister Offset; */       \
+      OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)                /* UINT16    AddressSize Offset; */               \
+    },                                                                                                                       \
+    AMD_GASN (UartBase),                              /* EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */       \
+    UartAddrLen,                                      /* UINT32  AddressSize */                                              \
+    UartNameStr                                       /* UINT8   NameSpaceString[MAX_DBG2_NAME_LEN] */                       \
+  }
+
+
+STATIC DBG2_TABLE AcpiDbg2 = {
+  {
+    AMD_ACPI_HEADER (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE,
+                     DBG2_TABLE,
+                     EFI_ACPI_DBG2_REVISION),
+    OFFSET_OF(DBG2_TABLE, Dbg2DeviceInfo),
+    DBG2_NUM_DEBUG_PORTS                                                    // UINT32  NumberDbgDeviceInfo
+  },
+  {
+    /*
+     * Kernel Debug Port
+     */
+#if (DBG2_NUM_DEBUG_PORTS > 0)
+    DBG2_DEBUG_PORT_DDI(DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS,
+                    DBG2_DEBUG_PORT_SUBTYPE_PL011,
+                    FixedPcdGet64(PcdSerialDbgRegisterBase),
+                    PL011_UART_LENGTH,
+                    NAME_STR_UART1),
+#endif
+    /*
+     * UEFI Debug Port
+    */
+#if (DBG2_NUM_DEBUG_PORTS > 1)
+    DBG2_DEBUG_PORT_DDI(0,
+                    DBG2_DEBUG_PORT_SUBTYPE_UEFI,
+                    0,
+                    0,
+                    NAME_STR_UEFI),
+#endif
+  }
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+Dbg2Header (
+  VOID
+  )
+{
+  return &AcpiDbg2.Description.Header;
+}
+
diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl
new file mode 100644
index 0000000..3bfa26a
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl
@@ -0,0 +1,812 @@
+/** @file
+
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+  Derived from:
+   ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl
+
+**/
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3)
+{
+    Scope (_SB)
+    {
+        Device (CPU0)
+        {
+            Name (_HID, "ACPI0007" /* Processor Device */)  // _HID: Hardware ID
+            Name (_UID, 0x000)  // _UID: Unique ID
+        }
+#if (NUM_CORES > 1)
+        Device (CPU1)
+        {
+            Name (_HID, "ACPI0007" /* Processor Device */)  // _HID: Hardware ID
+            Name (_UID, 0x001)  // _UID: Unique ID
+        }
+#endif
+#if (NUM_CORES > 2)
+        Device (CPU2)
+        {
+            Name (_HID, "ACPI0007" /* Processor Device */)  // _HID: Hardware ID
+            Name (_UID, 0x100)  // _UID: Unique ID
+        }
+#endif
+#if (NUM_CORES > 3)
+        Device (CPU3)
+        {
+            Name (_HID, "ACPI0007" /* Processor Device */)  // _HID: Hardware ID
+            Name (_UID, 0x101)  // _UID: Unique ID
+        }
+#endif
+#if (NUM_CORES > 4)
+        Device (CPU4)
+        {
+            Name (_HID, "ACPI0007" /* Processor Device */)  // _HID: Hardware ID
+            Name (_UID, 0x200)  // _UID: Unique ID
+        }
+#endif
+#if (NUM_CORES > 5)
+        Device (CPU5)
+        {
+            Name (_HID, "ACPI0007" /* Processor Device */)  // _HID: Hardware ID
+            Name (_UID, 0x201)  // _UID: Unique ID
+        }
+#endif
+#if (NUM_CORES > 6)
+        Device (CPU6)
+        {
+            Name (_HID, "ACPI0007" /* Processor Device */)  // _HID: Hardware ID
+            Name (_UID, 0x300)  // _UID: Unique ID
+        }
+#endif
+#if (NUM_CORES > 7)
+        Device (CPU7)
+        {
+            Name (_HID, "ACPI0007" /* Processor Device */)  // _HID: Hardware ID
+            Name (_UID, 0x301)  // _UID: Unique ID
+        }
+#endif
+
+        Device (AHC0)
+        {
+            Name (_HID, "AMDI0600")  // _HID: Hardware ID
+            Name (_UID, 0x00)  // _UID: Unique ID
+            Name (_CCA, 0x01)  // _CCA: Cache Coherency Attribute
+            Name (_CLS, Package (0x03)  // _CLS: Class Code
+            {
+                0x01,
+                0x06,
+                0x01
+            })
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0300000,         // Address Base (MMIO)
+                    0x00010000,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE0000078,         // Address Base (SGPIO)
+                    0x00000001,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000183, }
+            })
+        }
+
+        Device (AHC1)
+        {
+            Name (_HID, "AMDI0600")  // _HID: Hardware ID
+            Name (_UID, 0x01)  // _UID: Unique ID
+            Name (_CCA, 0x01)  // _CCA: Cache Coherency Attribute
+            Name (_CLS, Package (0x03)  // _CLS: Class Code
+            {
+                0x01,
+                0x06,
+                0x01
+            })
+            Method (_STA)
+            {
+                 Return (0x0F)
+            }
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0D00000,         // Address Base (MMIO)
+                    0x00010000,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE000007C,         // Address Base (SGPIO)
+                    0x00000001,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000182, }
+            })
+        }
+
+#if DO_XGBE
+        Device (ETH0)
+        {
+            Name (_HID, "AMDI8001")  // _HID: Hardware ID
+            Name (_UID, 0x00)  // _UID: Unique ID
+            Name (_CCA, 0x01)  // _CCA: Cache Coherency Attribute
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0700000,         // Address Base (XGMAC)
+                    0x00010000,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE0780000,         // Address Base (XPCS)
+                    0x00080000,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE1240800,         // Address Base (SERDES_RxTx)
+                    0x00000400,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE1250000,         // Address Base (SERDES_IR_1)
+                    0x00000060,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE12500F8,         // Address Base (SERDES_IR_2)
+                    0x00000004,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000165, } // XGMAC
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )  {0x0000017A, } // DMA0
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )  {0x0000017B, } // DMA1
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )  {0x0000017C, } // DMA2
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )  {0x0000017D, } // DMA3
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000163, } // XPCS
+            })
+            Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
+            {
+                ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                Package ()
+                {
+                    Package (0x02) {"mac-address", Package (0x06) {0x02, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}},
+                    Package (0x02) {"phy-mode", "xgmii"},
+                    Package (0x02) {"amd,speed-set", 0x00},
+                    Package (0x02) {"amd,dma-freq", 0x0EE6B280},
+                    Package (0x02) {"amd,ptp-freq",  0x0EE6B280},
+                    Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}},
+                    Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}},
+                    Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}},
+                    Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}},
+                    Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}},
+                    Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}},
+                    Package (0x02) {"amd,per-channel-interrupt", 0x01}
+                }
+            })
+        }
+
+        Device (ETH1)
+        {
+            Name (_HID, "AMDI8001")  // _HID: Hardware ID
+            Name (_UID, 0x01)  // _UID: Unique ID
+            Name (_CCA, 0x01)  // _CCA: Cache Coherency Attribute
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0900000,         // Address Base (XGMAC)
+                    0x00010000,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE0980000,         // Address Base (XPCS)
+                    0x00080000,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE1240C00,         // Address Base (SERDES_RxTx)
+                    0x00000400,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE1250080,         // Address Base (SERDES_IR_1)
+                    0x00000060,         // Address Length
+                    )
+                Memory32Fixed (ReadWrite,
+                    0xE12500FC,         // Address Base (SERDES_IR_2)
+                    0x00000004,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000164, } // XGMAC
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )  {0x00000175, } // DMA0
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )  {0x00000176, } // DMA1
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )  {0x00000177, } // DMA2
+                Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )  {0x00000178, } // DMA3
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000162, } // XPCS
+            })
+            Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
+            {
+                ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                Package ()
+                {
+                    Package (0x02) {"mac-address", Package (0x06) {0x02, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5}},
+                    Package (0x02) {"phy-mode", "xgmii"},
+                    Package (0x02) {"amd,speed-set", 0x00},
+                    Package (0x02) {"amd,dma-freq", 0x0EE6B280},
+                    Package (0x02) {"amd,ptp-freq",  0x0EE6B280},
+                    Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}},
+                    Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}},
+                    Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}},
+                    Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}},
+                    Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}},
+                    Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}},
+                    Package (0x02) {"amd,per-channel-interrupt", 0x01}
+                }
+            })
+        }
+#endif  // DO_XGBE
+
+        Device (SPI0)
+        {
+            Name (_HID, "AMDI0500")  // _HID: Hardware ID
+            Name (_UID, 0x00)  // _UID: Unique ID
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE1020000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000016A, }
+            })
+        }
+
+        Device (SPI1)
+        {
+            Name (_HID, "AMDI0500")  // _HID: Hardware ID
+            Name (_UID, 0x01)  // _UID: Unique ID
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE1030000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000169, }
+            })
+
+            Device(SDC0)
+            {
+                Name(_HID, "AMDI0501")  // SD Card/MMC slot
+                Name(_CRS, ResourceTemplate()
+                {
+                    SPISerialBus(1,             // DeviceSelection
+                       PolarityLow,             // DeviceSelectionPolarity
+                       FourWireMode,            // WireMode
+                       8,                       // DataBitLength
+                       ControllerInitiated,     // SlaveMode
+                       20000000,                // ConnectionSpeed
+                       ClockPolarityLow,        // ClockPolarity
+                       ClockPhaseFirst,         // ClockPhase
+                       "\\SB.SPI1",             // ResourceSource
+                       0,                       // ResourceSourceIndex
+                       ResourceConsumer,        // ResourceUsage
+                    ) // SPISerialBus()
+
+                    // SD Card “Detect” signal
+                    GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, , "\\_SB.GIO1") {6}
+                }) // ResourceTemplate()
+
+            } // Device()
+        }
+
+        Device (COM1)
+        {
+            Name (_HID, "AMDI0511")  // _HID: Hardware ID
+            Name (_CID, "ARMH0011")  // _CID: Compatible ID
+            Name (_ADR, 0xE1010000)  // _ADR: Address
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE1010000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000168, }
+            })
+        }
+
+        Device (GIO0)
+        {
+            Name (_HID, "AMDI0400")  // _HID: Hardware ID
+            Name (_CID, "ARMH0061")  // _CID: Compatible ID
+            Name (_UID, 0x00)  // _UID: Unique ID
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0080000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000189, }
+            })
+        }
+
+        Device (GIO1)
+        {
+            Name (_HID, "AMDI0400")  // _HID: Hardware ID
+            Name (_CID, "ARMH0061")  // _CID: Compatible ID
+            Name (_UID, 0x01)  // _UID: Unique ID
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE1050000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000186, }
+            })
+        }
+
+        Device (GIO2)
+        {
+            Name (_HID, "AMDI0400")  // _HID: Hardware ID
+            Name (_CID, "ARMH0061")  // _CID: Compatible ID
+            Name (_UID, 0x02)  // _UID: Unique ID
+            Method (_STA)
+            {
+                 Return (0x0F)
+            }
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0020000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, }
+            })
+        }
+
+        Device (GIO3)
+        {
+            Name (_HID, "AMDI0400")  // _HID: Hardware ID
+            Name (_CID, "ARMH0061")  // _CID: Compatible ID
+            Name (_UID, 0x03)  // _UID: Unique ID
+            Method (_STA)
+            {
+                 Return (0x0F)
+            }
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0030000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, }
+            })
+        }
+
+        Device (I2C0)
+        {
+            Name (_HID, "AMDI0510")  // _HID: Hardware ID
+            Name (_UID, 0x00)  // _UID: Unique ID
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE1000000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000185, }
+            })
+
+            Method (SSCN, 0, NotSerialized)
+            {
+                Return (Package (0x03)
+                {
+                    0x0430,
+                    0x04E1,
+                    0x00
+                })
+            }
+
+            Method (FMCN, 0, NotSerialized)
+            {
+                Return (Package (0x03)
+                {
+                    0x00DE,
+                    0x018F,
+                    0x00
+                })
+            }
+        }
+
+        Device (I2C1)
+        {
+            Name (_HID, "AMDI0510")  // _HID: Hardware ID
+            Name (_UID, 0x01)  // _UID: Unique ID
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0050000,         // Address Base
+                    0x00001000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000174, }
+            })
+
+            Method (SSCN, 0, NotSerialized)
+            {
+                Return (Package (0x03)
+                {
+                    0x0430,
+                    0x04E1,
+                    0x00
+                })
+            }
+
+            Method (FMCN, 0, NotSerialized)
+            {
+                Return (Package (0x03)
+                {
+                    0x00DE,
+                    0x018F,
+                    0x00
+                })
+            }
+        }
+
+        Device (CCP0)
+        {
+            Name (_HID, "AMDI0C00")  // _HID: Hardware ID
+            Name (_CCA, 0x01)  // _CCA: Cache Coherency Attribute
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xE0100000,         // Address Base
+                    0x00010000,         // Address Length
+                    )
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000023, }
+            })
+
+            Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
+            {
+                ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                Package ()
+                {
+                    Package (0x02) {"amd,zlib-support", 1}
+                }
+            })
+        }
+
+#if DO_KCS
+        //
+        // IPMI/KCS
+        //
+        Device (KCS0)
+        {
+            Name (_HID, "AMDI0300")
+            Name (_CID, "IPI0001")
+            Name (_STR, Unicode("IPMI_KCS"))
+            Name (_UID, 0)
+            Name (_CRS, ResourceTemplate() {
+                Memory32Fixed(ReadWrite, 0xE0010000, 0x1) // KCS Data In/Out
+                Memory32Fixed(ReadWrite, 0xE0010004, 0x1) // KCS Control/Status
+                Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 421 } // GSIV
+            })
+            Method (_IFT) {     // Interface Type
+                Return ( 0x01)   // IPMI KCS
+            }
+
+            Method (_SRV) {     // Spec Revision
+                Return (0x200)  // IPMI Spec v2.0
+            }
+        }
+#endif // DO_KCS
+
+        //
+        // PCIe Root Bus
+        //
+        Device (PCI0)
+        {
+            Name (_HID, "PNP0A08" /* PCI Express Bus */)  // _HID: Hardware ID
+            Name (_CID, "PNP0A03" /* PCI Bus */)  // _CID: Compatible ID
+            Name (_SEG, 0x00)  // _SEG: PCI Segment
+            Name (_BBN, 0x00)  // _BBN: BIOS Bus Number
+            Name (_CCA, 0x01)  // _CCA: Cache Coherency Attribute
+            Name (_PRT, Package (0x04)  // _PRT: PCI Routing Table
+            {
+                Package (0x04)
+                {
+                    0xFFFF,
+                    0x00,
+                    0x00,
+                    0x0140
+                },
+
+                Package (0x04)
+                {
+                    0xFFFF,
+                    0x01,
+                    0x00,
+                    0x0141
+                },
+
+                Package (0x04)
+                {
+                    0xFFFF,
+                    0x02,
+                    0x00,
+                    0x0142
+                },
+
+                Package (0x04)
+                {
+                    0xFFFF,
+                    0x03,
+                    0x00,
+                    0x0143
+                }
+            }) // _PRT
+
+            Method (_CRS, 0, Serialized)  // _CRS: Current Resource Settings
+            {
+                Name (RBUF, ResourceTemplate ()
+                {
+                    WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                        0x0000,             // Granularity
+                        0x0000,             // Range Minimum
+                        0x007F,             // Range Maximum
+                        0x0000,             // Translation Offset
+                        0x0080,             // Length
+                        )
+                    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x00000000,         // Granularity
+                        0x40000000,         // Range Minimum
+                        0x5FFFFFFF,         // Range Maximum
+                        0x00000000,         // Translation Offset
+                        0x20000000          // Length
+                        )
+                    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x00000000,         // Granularity
+                        0x60000000,         // Range Minimum
+                        0x7FFFFFFF,         // Range Maximum
+                        0x00000000,         // Translation Offset
+                        0x20000000          // Length
+                        )
+                    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x00000000,         // Granularity
+                        0x80000000,         // Range Minimum
+                        0x9FFFFFFF,         // Range Maximum
+                        0x00000000,         // Translation Offset
+                        0x20000000          // Length
+                        )
+                    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x00000000,         // Granularity
+                        0xA0000000,         // Range Minimum
+                        0xBFFFFFFF,         // Range Maximum
+                        0x00000000,         // Translation Offset
+                        0x20000000          // Length
+                        )
+                    QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x0000000000000000, // Granularity
+                        0x0000000100000000, // Range Minimum
+                        0x00000001FFFFFFFF, // Range Maximum
+                        0x0000000000000000, // Translation Offset
+                        0x0000000100000000  // Length
+                        )
+                    QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x0000000000000000, // Granularity
+                        0x0000000200000000, // Range Minimum
+                        0x00000003FFFFFFFF, // Range Maximum
+                        0x0000000000000000, // Translation Offset
+                        0x0000000200000000  // Length
+                        )
+                    QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x0000000000000000, // Granularity
+                        0x0000000400000000, // Range Minimum
+                        0x00000007FFFFFFFF, // Range Maximum
+                        0x0000000000000000, // Translation Offset
+                        0x0000000400000000  // Length
+                        )
+                    QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x0000000000000000, // Granularity
+                        0x0000000800000000, // Range Minimum
+                        0x0000000FFFFFFFFF, // Range Maximum
+                        0x0000000000000000, // Translation Offset
+                        0x0000000800000000  // Length
+                        )
+                    QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x0000000000000000, // Granularity
+                        0x0000001000000000, // Range Minimum
+                        0x0000001FFFFFFFFF, // Range Maximum
+                        0x0000000000000000, // Translation Offset
+                        0x0000001000000000  // Length
+                        )
+                    QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x0000000000000000, // Granularity
+                        0x0000002000000000, // Range Minimum
+                        0x0000003FFFFFFFFF, // Range Maximum
+                        0x0000000000000000, // Translation Offset
+                        0x0000002000000000  // Length
+                        )
+                    QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                        0x0000000000000000, // Granularity
+                        0x0000004000000000, // Range Minimum
+                        0x0000007FFFFFFFFF, // Range Maximum
+                        0x0000000000000000, // Translation Offset
+                        0x0000004000000000  // Length
+                        )
+                    DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                        0x00000000,         // Granularity
+                        0x00000000,         // Range Minimum
+                        0x0000FFFF,         // Range Maximum
+                        0xEFFF0000,         // Translation Address
+                        0x00010000,         // Length
+                        ,
+                        ,
+                        ,
+                        TypeTranslation
+                        )
+                })
+                Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
+            } // Method(_CRS)
+
+            Device (RES0)
+            {
+                Name (_HID, "PNP0C02")
+                Name (_CRS, ResourceTemplate ()
+                {
+                    Memory32Fixed (ReadWrite, 0xF0000000, 0x8000000)
+                })
+            }
+            Name (SUPP, 0x00)
+            Name (CTRL, 0x00)
+            Method (_OSC, 4, NotSerialized)  // _OSC: Operating System Capabilities
+            {
+                CreateDWordField (Arg3, 0x00, CDW1)
+                If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+                {
+                    CreateDWordField (Arg3, 0x04, CDW2)
+                    CreateDWordField (Arg3, 0x08, CDW3)
+                    Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
+                    Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
+                    If (LNotEqual (And (SUPP, 0x16), 0x16))
+                    {
+                        And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
+                    }
+
+                    And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
+                    If (LNotEqual (Arg1, One))
+                    {
+                        Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+                    }
+
+                    If (LNotEqual (CDW3, CTRL))
+                    {
+                        Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+                    }
+
+                    Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
+                    Return (Arg3)
+                }
+                Else
+                {
+                    Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+                    Return (Arg3)
+                }
+            } // Method(_OSC)
+
+            //
+            // Device-Specific Methods
+            //
+            Method(_DSM, 0x4, NotSerialized) {
+              If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
+                switch (ToInteger(Arg2)) {
+                  //
+                  // Function 0: Return supported functions
+                  //
+                  case(0) {
+                    Return (Buffer() {0xFF})
+                  }
+
+                  //
+                  // Function 1: Return PCIe Slot Information
+                  //
+                  case(1) {
+                    Return (Package(2) {
+                      One, // Success
+                      Package(3) {
+                        0x1,  // x1 PCIe link
+                        0x1,  // PCI express card slot
+                        0x1   // WAKE# signal supported
+                      }
+                    })
+                  }
+
+                  //
+                  // Function 2: Return PCIe Slot Number.
+                  //
+                  case(2) {
+                    Return (Package(1) {
+                      Package(4) {
+                        2,  // Source ID
+                        4,  // Token ID: ID refers to a slot
+                        0,  // Start bit of the field to use.
+                        7   // End bit of the field to use.
+                      }
+                    })
+                  }
+
+                  //
+                  // Function 3: Return Vendor-specific Token ID Strings.
+                  //
+                  case(3) {
+                    Return (Package(0) {})
+                  }
+
+                  //
+                  // Function 4: Return PCI Bus Capabilities
+                  //
+                  case(4) {
+                    Return (Package(2) {
+                      One, // Success
+                      Buffer() {
+                        1,0,            // Version
+                        0,0,            // Status, 0:Success
+                        24,0,0,0,       // Length
+                        1,0,            // PCI
+                        16,0,           // Length
+                        0,              // Attributes
+                        0x0D,           // Current Speed/Mode
+                        0x3F,0,         // Supported Speeds/Modes
+                        0,              // Voltage
+                        0,0,0,0,0,0,0   // Reserved
+                      }
+                    })
+                  }
+
+                  //
+                  // Function 5: Return Ignore PCI Boot Configuration
+                  //
+                  case(5) {
+                    Return (Package(1) {1})
+                  }
+
+                  //
+                  // Function 6: Return LTR Maximum Latency
+                  //
+                  case(6) {
+                    Return (Package(4) {
+                      Package(1){0},  // Maximum Snoop Latency Scale
+                      Package(1){0},  // Maximum Snoop Latency Value
+                      Package(1){0},  // Maximum No-Snoop Latency Scale
+                      Package(1){0}   // Maximum No-Snoop Latency Value
+                    })
+                  }
+
+                  //
+                  // Function 7: Return PCI Express Naming
+                  //
+                  case(7) {
+                    Return (Package(2) {
+                      Package(1) {0},
+                      Package(1) {Unicode("PCI0")}
+                    })
+                  }
+
+                  //
+                  // Not supported
+                  //
+                  default {
+                  }
+                }
+              }
+              Return (Buffer(){0})
+            } // Method(_DSM)
+
+            //
+            // Root-Complex 0
+            //
+            Device (RP0)
+            {
+                Name (_ADR, 0xF0000000)  // _ADR: Bus 0, Dev 0, Func 0
+            }
+        }
+    }
+}
+
diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.c b/Platforms/AMD/Styx/AcpiTables/Dsdt.c
new file mode 100644
index 0000000..360a446
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.c
@@ -0,0 +1,192 @@
+/** @file
+
+  C language wrapper to build DSDT generated data.
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Dsdt.hex>
+#include <Dsdt.offset.h>
+
+
+UINTN
+ShiftLeftByteToUlong (
+  IN UINT8 Byte,
+  IN UINTN Shift
+  )
+{
+  UINTN Data;
+
+  Data = (UINTN)Byte;
+  Data <<= Shift;
+  return Data;
+}
+
+UINTN
+AmlGetPkgLength (
+  IN UINT8 *Buffer,
+  OUT UINTN *PkgLength
+  )
+{
+  UINTN Bytes, Length;
+
+  Bytes = (UINTN)((Buffer[0] >> 6) & 0x3) + 1;
+  switch (Bytes) {
+    case 1:
+      Length = (UINTN)Buffer[0];
+      break;
+
+    case 2:
+      Length = ShiftLeftByteToUlong(Buffer[1], 4) +
+                (UINTN)(Buffer[0] & 0x0F);
+      break;
+
+    case 3:
+      Length = ShiftLeftByteToUlong(Buffer[2], 12) +
+                ShiftLeftByteToUlong(Buffer[1], 4) +
+                 (UINTN)(Buffer[0] & 0x0F);
+      break;
+
+    default: /* 4 bytes */
+      Length = ShiftLeftByteToUlong(Buffer[3], 20) +
+                ShiftLeftByteToUlong(Buffer[2], 12) +
+                 ShiftLeftByteToUlong(Buffer[1], 4) +
+                  (UINTN)(Buffer[0] & 0x0F);
+      break;
+  }
+
+  *PkgLength = Length;
+  return Bytes;
+}
+
+UINT8 *
+AmlSearchStringPackage (
+  IN UINT8 *Buffer,
+  IN UINTN Length,
+  IN CHAR8 *String
+  )
+{
+  UINTN StrLength;
+
+  StrLength = AsciiStrLen (String) + 1;
+  if (Length > StrLength ) {
+    Length -= StrLength;
+    while (AsciiStrCmp((CHAR8 *)Buffer, String) != 0 && Length) {
+      --Length;
+      ++Buffer;
+    }
+    if (Length) {
+      return &Buffer[StrLength];
+    }
+  }
+  return NULL;
+}
+
+VOID
+OverrideMacAddr (
+  IN UINT8 *DSD_Data,
+  IN UINT64 MacAddr
+  )
+{
+  UINT8 *MacAddrPkg;
+  UINTN Bytes, Length, Index = 0;
+
+  // AML encoding: PackageOp
+  if (DSD_Data[0] == 0x12) {
+    // AML encoding: PkgLength
+    Bytes = AmlGetPkgLength (&DSD_Data[1], &Length);
+
+    // Search for "mac-address" property
+    MacAddrPkg = AmlSearchStringPackage (&DSD_Data[Bytes + 1],
+                                        Length - Bytes,
+                                        "mac-address");
+    if (MacAddrPkg &&
+        MacAddrPkg[0] == 0x12 &&        // PackageOp
+        MacAddrPkg[1] == 0x0E &&        // PkgLength
+        MacAddrPkg[2] == 0x06) {        // NumElements (element must have a BytePrefix)
+
+      MacAddrPkg += 3;
+      do {
+        MacAddrPkg[0] = 0x0A;           // BytePrefix
+        MacAddrPkg[1] = (UINT8)(MacAddr & 0xFF);
+        MacAddrPkg += 2;
+        MacAddr >>= 8;
+      } while (++Index < 6);
+    }
+  }
+}
+
+VOID
+OverrideStatus (
+  IN UINT8 *DSD_Data,
+  IN BOOLEAN Enable
+  )
+{
+  if (Enable) {
+    // AML encoding: ReturnOp + BytePrefix
+    if (DSD_Data[1] == 0xA4 && DSD_Data[2] == 0x0A) {
+      DSD_Data[3] = 0x0F;
+    }
+  } else {
+    // AML encoding: ReturnOp
+    if (DSD_Data[1] == 0xA4) {
+      // AML encoding: BytePrefix?
+      if (DSD_Data[2] == 0x0A) {
+        DSD_Data[3] = 0x00;
+      } else {
+        DSD_Data[2] = 0x00;
+      }
+    }
+  }
+}
+
+EFI_ACPI_DESCRIPTION_HEADER *
+DsdtHeader (
+  VOID
+  )
+{
+  AML_OFFSET_TABLE_ENTRY *Table;
+  BOOLEAN                EnableOnB1;
+  UINT32                 CpuId = PcdGet32 (PcdSocCpuId);
+
+  // Enable features on Styx-B1 or later
+  EnableOnB1 = (CpuId & 0xFF0) && (CpuId & 0x00F);
+
+  Table = &DSDT_SEATTLE__OffsetTable[0];
+  while (Table->Pathname) {
+    if (AsciiStrCmp(Table->Pathname, "_SB_.ETH0._DSD") == 0) {
+      OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacA));
+    }
+    else if (AsciiStrCmp(Table->Pathname, "_SB_.ETH1._DSD") == 0) {
+      OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacB));
+    }
+    else if (AsciiStrCmp(Table->Pathname, "_SB_.AHC1._STA") == 0) {
+      OverrideStatus ((UINT8 *)&AmlCode[Table->Offset],
+        EnableOnB1 && FixedPcdGet8(PcdSata1PortCount) > 0);
+    }
+    else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO2._STA") == 0) {
+      OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+    }
+    else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO3._STA") == 0) {
+      OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+    }
+
+    ++Table;
+  }
+
+  return (EFI_ACPI_DESCRIPTION_HEADER *) &AmlCode[0];
+}
diff --git a/Platforms/AMD/Styx/AcpiTables/Fadt.c b/Platforms/AMD/Styx/AcpiTables/Fadt.c
new file mode 100644
index 0000000..bcbff37
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Fadt.c
@@ -0,0 +1,104 @@
+/** @file
+
+  Fixed ACPI Description Table (FADT)
+
+  Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+  Derived from:
+   ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+#define FADT_FLAGS          ( EFI_ACPI_5_1_HW_REDUCED_ACPI |           \
+                              EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE | \
+                              EFI_ACPI_5_1_HEADLESS )
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
+    AMD_ACPI_HEADER (EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+                     EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+                     EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION),
+  0,                                                                        // UINT32     FirmwareCtrl
+  0,                                                                        // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
+  EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER,                                // UINT8      PreferredPmProfile
+  0,                                                                        // UINT16     SciInt
+  0,                                                                        // UINT32     SmiCmd
+  0,                                                                        // UINT8      AcpiEnable
+  0,                                                                        // UINT8      AcpiDisable
+  0,                                                                        // UINT8      S4BiosReq
+  0,                                                                        // UINT8      PstateCnt
+  0,                                                                        // UINT32     Pm1aEvtBlk
+  0,                                                                        // UINT32     Pm1bEvtBlk
+  0,                                                                        // UINT32     Pm1aCntBlk
+  0,                                                                        // UINT32     Pm1bCntBlk
+  0,                                                                        // UINT32     Pm2CntBlk
+  0,                                                                        // UINT32     PmTmrBlk
+  0,                                                                        // UINT32     Gpe0Blk
+  0,                                                                        // UINT32     Gpe1Blk
+  0,                                                                        // UINT8      Pm1EvtLen
+  0,                                                                        // UINT8      Pm1CntLen
+  0,                                                                        // UINT8      Pm2CntLen
+  0,                                                                        // UINT8      PmTmrLen
+  0,                                                                        // UINT8      Gpe0BlkLen
+  0,                                                                        // UINT8      Gpe1BlkLen
+  0,                                                                        // UINT8      Gpe1Base
+  0,                                                                        // UINT8      CstCnt
+  0,                                                                        // UINT16     PLvl2Lat
+  0,                                                                        // UINT16     PLvl3Lat
+  0,                                                                        // UINT16     FlushSize
+  0,                                                                        // UINT16     FlushStride
+  0,                                                                        // UINT8      DutyOffset
+  0,                                                                        // UINT8      DutyWidth
+  0,                                                                        // UINT8      DayAlrm
+  0,                                                                        // UINT8      MonAlrm
+  0,                                                                        // UINT8      Century
+  0,                                                                        // UINT16     IaPcBootArch
+  0,                                                                        // UINT8      Reserved1
+  FADT_FLAGS,                                                               // UINT32     Flags
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  ResetReg
+  0,                                                                        // UINT8      ResetValue
+  0,                                                                        // UINT16     ArmBootArch
+  1,                                                                        // UINT8      MinorVersion
+  0,                                                                        // UINT64     XFirmwareCtrl
+  0,                                                                        // UINT64     XDsdt
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
+  NULL_GAS                                                                  // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+FadtTable (
+  VOID
+  )
+{
+  if (FixedPcdGetBool (PcdPsciOsSupport) && FixedPcdGetBool (PcdTrustedFWSupport)) {
+    AcpiFadt.ArmBootArch = EFI_ACPI_5_1_ARM_PSCI_COMPLIANT;
+  }
+  return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiFadt;
+}
+
diff --git a/Platforms/AMD/Styx/AcpiTables/Gtdt.c b/Platforms/AMD/Styx/AcpiTables/Gtdt.c
new file mode 100644
index 0000000..139c9ae
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Gtdt.c
@@ -0,0 +1,189 @@
+/** @file
+
+  Generic Timer Description Table (GTDT)
+
+  Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+  Derived from:
+   ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+#pragma pack(push, 1)
+
+#define CNT_CONTROL_BASE_ADDRESS      FixedPcdGet64(PcdCntControlBase)
+#define CNT_READ_BASE_ADDRESS         FixedPcdGet64(PcdCntReadBase)
+#define CNT_CTL_BASE_ADDRESS          FixedPcdGet64(PcdCntCTLBase)
+#define CNT_BASE0_ADDRESS             FixedPcdGet64(PcdCntBase0)
+#define CNT_EL0_BASE0_ADDRESS         FixedPcdGet64(PcdCntEL0Base0)
+#define SBSA_WATCHDOG_REFRESH_BASE    FixedPcdGet64(PcdSbsaWatchDogRefreshBase)
+#define SBSA_WATCHDOG_CONTROL_BASE    FixedPcdGet64(PcdSbsaWatchDogControlBase)
+#define SBSA_WAKEUP_GSIV              FixedPcdGet64(PcdSbsaWakeUpGSIV)
+#define SBSA_WATCHDOG_GSIV            FixedPcdGet64(PcdSbsaWatchDogGSIV)
+
+
+/*
+ * Section 8.2.3 of Cortex-A15 r2p1 TRM
+ */
+#define CP15_TIMER_SEC_INTR    29
+#define CP15_TIMER_NS_INTR     30
+#define CP15_TIMER_VIRT_INTR   27
+#define CP15_TIMER_NSHYP_INTR  26
+
+/* SBSA Timers */
+  #define PLATFORM_TIMER_COUNT          2
+  #define PLATFORM_TIMER_OFFSET         sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE)
+
+/*
+// GTDT Table timer flags.
+
+Bit 0: Timer interrupt Mode
+  This bit indicates the mode of the timer interrupt
+    1: Interrupt is Edge triggered
+    0: Interrupt is Level triggered
+Timer Interrupt polarity
+  This bit indicates the polarity of the timer interrupt
+    1: Interrupt is Active low
+    0: Interrupt is Active high
+Reserved 2 30 Reserved, must be zero.
+
+From A15 TRM:
+   9.2 Generic Timer functional description
+    ...
+    Each timer provides an active-LOW interrupt output that is an external pin to the SoC and is
+    sent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources on page 8-4 for
+    the ID and PPI allocation of the Timer interrupts.
+      PPI6 Virtual Maintenance Interrupt.
+      PPI5 Hypervisor timer event.
+      PPI4 Virtual timer event.
+      PPI3 nIRQ.
+      PPI2 Non-secure physical timer event.
+      PPI1 Secure physical timer event.
+      PPI0-5 Active-LOW level-sensitive.
+      PPI6 Active-HIGH level-sensitive.*/
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+#define GTDT_TIMER_SECURE           EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+#define GTDT_TIMER_NON_SECURE       0
+#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_EDGE_TRIGGERED    EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTX_TIMER_LEVEL_TRIGGERED   0
+#define GTX_TIMER_ACTIVE_LOW        EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTX_TIMER_ACTIVE_HIGH       0
+#define GTX_TIMER_FLAGS             (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_SECURE            EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_NON_SECURE        0
+#define GTX_TIMER_SAVE_CONTEXT      EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_LOSE_CONTEXT      0
+#define GTX_COMMON_FLAGS            (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE)
+
+#define SBSA_WATCHDOG_EDGE_TRIGGERED   EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
+#define SBSA_WATCHDOG_LEVEL_TRIGGERED  0
+#define SBSA_WATCHDOG_ACTIVE_LOW       EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
+#define SBSA_WATCHDOG_ACTIVE_HIGH      0
+#define SBSA_WATCHDOG_SECURE           EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+#define SBSA_WATCHDOG_NON_SECURE       0
+#define SBSA_WATCHDOG_FLAGS            (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED)
+
+
+#define AMD_SBSA_GTX {                                                                     \
+   EFI_ACPI_5_1_GTDT_GT_BLOCK,                           /* UINT8  Type */                 \
+   sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) +                                         \
+   sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE),  /* UINT16 Length */               \
+   EFI_ACPI_RESERVED_BYTE,                               /* UINT8  Reserved */             \
+   CNT_CTL_BASE_ADDRESS,                                 /* UINT64 CntCtlBase */           \
+   1,                                                    /* UINT32 GTBlockTimerCount */    \
+   sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE)         /* UINT32 GTBlockTimerOffset */   \
+  }
+
+#define AMD_SBSA_GTX_TIMER {                                                                  \
+   0,                                                    /* UINT8  GTFrameNumber */           \
+   {0, 0, 0},                                            /* UINT8  Reserved[3] */             \
+   CNT_BASE0_ADDRESS,                                    /* UINT64 CntBaseX */                \
+   CNT_EL0_BASE0_ADDRESS,                                /* UINT64 CntEL0BaseX */             \
+   SBSA_WAKEUP_GSIV,                                     /* UINT32 GTxPhysicalTimerGSIV */    \
+   GTX_TIMER_FLAGS,                                      /* UINT32 GTxPhysicalTimerFlags */   \
+   0,                                                    /* UINT32 GTxVirtualTimerGSIV */     \
+   GTX_TIMER_FLAGS,                                      /* UINT32 GTxVirtualTimerFlags */    \
+   GTX_COMMON_FLAGS                                      /* UINT32 GTxCommonFlags */          \
+  }
+
+#define AMD_SBSA_WATCHDOG {                                                                                        \
+   EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG,                     /* UINT8  Type */                                  \
+   sizeof (EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE),  /* UINT16 Length */                                \
+   EFI_ACPI_RESERVED_BYTE,                                      /* UINT8  Reserved */                              \
+   SBSA_WATCHDOG_REFRESH_BASE,                                  /* UINT64 RefreshFramePhysicalAddress */           \
+   SBSA_WATCHDOG_CONTROL_BASE,                                  /* UINT64 WatchdogControlFramePhysicalAddress */   \
+   SBSA_WATCHDOG_GSIV,                                          /* UINT32 WatchdogTimerGSIV */                     \
+   SBSA_WATCHDOG_FLAGS                                          /* UINT32 WatchdogTimerFlags */                    \
+  }
+
+typedef struct {
+  EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE      Gtdt;
+  EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE              GTxBlock;
+  EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE        GTxTimer;
+  EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE WatchDog;
+} AMD_ACPI_5_1_ARM_GTDT_STRUCTURE;
+
+STATIC AMD_ACPI_5_1_ARM_GTDT_STRUCTURE AcpiGtdt = {
+  {
+    AMD_ACPI_HEADER(EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+                    AMD_ACPI_5_1_ARM_GTDT_STRUCTURE,
+                    EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION),
+    CNT_CONTROL_BASE_ADDRESS,     // UINT64  PhysicalAddress
+    0,                            // UINT32  Reserved
+    CP15_TIMER_SEC_INTR,          // UINT32  SecureEL1TimerGSIV
+    GTDT_GTIMER_FLAGS,            // UINT32  SecureEL1TimerFlags
+    CP15_TIMER_NS_INTR,           // UINT32  NonSecureEL1TimerGSIV
+    GTDT_GTIMER_FLAGS,            // UINT32  NonSecureEL1TimerFlags
+    CP15_TIMER_VIRT_INTR,         // UINT32  VirtualTimerGSIV
+    GTDT_GTIMER_FLAGS,            // UINT32  VirtualTimerFlags
+    CP15_TIMER_NSHYP_INTR,        // UINT32  NonSecureEL2TimerGSIV
+    GTDT_GTIMER_FLAGS,            // UINT32  NonSecureEL2TimerFlags
+    CNT_READ_BASE_ADDRESS,        // UINT64  CntReadBaseAddress
+    PLATFORM_TIMER_COUNT,         // UINT32  PlatformTimerCount
+    PLATFORM_TIMER_OFFSET         // UINT32  PlatformTimerOffset
+  },
+  AMD_SBSA_GTX,
+  AMD_SBSA_GTX_TIMER,
+  AMD_SBSA_WATCHDOG,
+};
+
+#pragma pack(pop)
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+GtdtHeader (
+  VOID
+  )
+{
+  UINT32 CpuId = PcdGet32 (PcdSocCpuId);
+
+  // Check BaseModel and Stepping: Styx-B0 or prior?
+  if (((CpuId & 0xFF0) == 0) || ((CpuId & 0x00F) == 0)) {
+    AcpiGtdt.Gtdt.Header.Length = sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE);
+    AcpiGtdt.Gtdt.PlatformTimerCount = 0;
+    AcpiGtdt.Gtdt.PlatformTimerOffset = 0;
+  }
+
+  return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiGtdt.Gtdt.Header;
+}
diff --git a/Platforms/AMD/Styx/AcpiTables/Madt.c b/Platforms/AMD/Styx/AcpiTables/Madt.c
new file mode 100644
index 0000000..96182e7
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Madt.c
@@ -0,0 +1,336 @@
+/** @file
+
+  Multiple APIC Description Table (MADT)
+
+  Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+  Derived from:
+   ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc
+
+**/
+
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <AmdStyxAcpiLib.h>
+#include <Protocol/AmdMpCoreInfo.h>
+
+AMD_MP_CORE_INFO_PROTOCOL  *mAmdMpCoreInfoProtocol = NULL;
+
+
+// ARM PL390 General Interrupt Controller
+#define GIC_BASE                             (FixedPcdGet64 (PcdGicInterruptInterfaceBase))
+#define GICD_BASE                            (FixedPcdGet64 (PcdGicDistributorBase))
+#define GICV_BASE                            (FixedPcdGet64 (PcdGicVirtualInterruptInterfaceBase))
+#define GICH_BASE                            (FixedPcdGet64 (PcdGicHypervisorInterruptInterfaceBase))
+#define VGIC_MAINT_INT                       (FixedPcdGet32 (PcdGicVirtualMaintenanceInterrupt))
+#define GICVR_BASE                           (FixedPcdGet64 (PcdGicVirtualRegisterInterfaceBase))
+#define GIC_MSI_FRAME                        (FixedPcdGet64 (PcdGicMSIFrameBase))
+#define GIC_VERSION                          (FixedPcdGet8  (PcdGicVersion))
+
+#define GICD_ID                              ( 0 )
+#define GICD_VECTOR                          ( 0 )
+
+#define GICM_ID                              ( 0 )
+#define GICM_SPI_COUNT                       ( 0x100 )
+#define GICM_SPI_BASE                        ( 0x40 )
+#define GSIV_SPI_OFFSET                      ( 32 )
+
+#if STYX_A0
+  #define MSI_TYPER_FLAG                     ( 1 ) // Ignore TYPER register and use Count/Base fields
+#else
+  #define MSI_TYPER_FLAG                     ( 0 ) // Use TYPER register and ignore Count/Base fields
+#endif
+
+#define PARKING_PROTOCOL_VERSION             (FixedPcdGet32 (PcdParkingProtocolVersion))
+#define PARKED_OFFSET                        ( 4096 )
+
+#define CORES_PER_CLUSTER                    (FixedPcdGet32 (PcdSocCoresPerCluster))
+#define PARKED_ADDRESS(Base, ClusterId, CoreId) \
+        ((Base) + (CORES_PER_CLUSTER * ClusterId + CoreId) * PARKED_OFFSET)
+
+
+/* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */
+#define AMD_GIC(CpuNum, ClusterId, CoreId, PerfInt)  {                        \
+  EFI_ACPI_5_1_GIC,                     /* UINT8 Type */                      \
+  sizeof (EFI_ACPI_5_1_GIC_STRUCTURE),  /* UINT8 Length */                    \
+  EFI_ACPI_RESERVED_WORD,               /* UINT16 Reserved */                 \
+  CpuNum,                               /* UINT32 CPUInterfaceNumber */       \
+  (ClusterId << 8) | CoreId,            /* UINT32 AcpiProcessorUid */         \
+  EFI_ACPI_5_1_GIC_ENABLED,             /* UINT32 Flags */                    \
+  PARKING_PROTOCOL_VERSION,             /* UINT32 ParkingProtocolVersion */   \
+  PerfInt,                              /* UINT32 PerformanceInterruptGsiv */ \
+  0,                                    /* UINT64 ParkedAddress */            \
+  GIC_BASE,                             /* UINT64 PhysicalBaseAddress */      \
+  GICV_BASE,                            /* UINT64 GICV */                     \
+  GICH_BASE,                            /* UINT64 GICH */                     \
+  VGIC_MAINT_INT,                       /* UINT32 VGICMaintenanceInterrupt */ \
+  GICVR_BASE,                           /* UINT64 GICRBaseAddress */          \
+  (ClusterId << 8) | CoreId             /* UINT64 MPIDR */                    \
+  }
+
+/* Macro to initialise EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE */
+#define AMD_GICD(Id, Vec) {                                                             \
+  EFI_ACPI_5_1_GICD,                                /* UINT8 Type */                    \
+  sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE),  /* UINT8 Length */                  \
+  EFI_ACPI_RESERVED_WORD,                           /* UINT16 Reserved1 */              \
+  Id,                                               /* UINT32 GicId */                  \
+  GICD_BASE,                                        /* UINT64 PhysicalBaseAddress */    \
+  Vec,                                              /* UINT32 SystemVectorBase */       \
+  EFI_ACPI_RESERVED_DWORD                           /* UINT32 Reserved2 */              \
+  }
+
+/* Macro to initialise EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE */
+#define AMD_GICM(Id, SpiCount, SpiBase) {                                               \
+   EFI_ACPI_5_1_GIC_MSI_FRAME,                      /* UINT8 Type */                    \
+   sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE),    /* UINT8 Length */                  \
+   EFI_ACPI_RESERVED_WORD,                          /* UINT16 Reserved1 */              \
+   Id,                                              /* UINT32 GicMsiFrameId */          \
+   GIC_MSI_FRAME,                                   /* UINT64 PhysicalBaseAddress */    \
+   MSI_TYPER_FLAG,                                  /* UINT32 Flags */                  \
+   SpiCount,                                        /* UINT16 SPICount */               \
+   SpiBase                                          /* UINT16 SPIBase */                \
+   }
+
+
+//
+// NOTE: NUM_CORES is a pre-processor macro passed in with -D option
+//
+#pragma pack(push, 1)
+typedef struct {
+  EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+  EFI_ACPI_5_1_GIC_STRUCTURE                          GicC[NUM_CORES];
+  EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE              GicD;
+  EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE                GicM;
+} EFI_ACPI_5_1_ARM_MADT_STRUCTURE;
+#pragma pack(pop)
+
+
+STATIC EFI_ACPI_5_1_ARM_MADT_STRUCTURE AcpiMadt = {
+  {
+    AMD_ACPI_HEADER (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+                     EFI_ACPI_5_1_ARM_MADT_STRUCTURE,
+                     EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+    GIC_BASE,                                 // UINT32  LocalApicAddress
+    0                                         // UINT32  Flags
+  },
+  {
+    /*
+     * GIC Interface for Cluster 0 CPU 0
+     */
+    AMD_GIC(0, 0, 0, 39),                     // EFI_ACPI_5_1_GIC_STRUCTURE
+#if (NUM_CORES > 1)
+    /*
+     * GIC Interface for Cluster 0 CPU 1
+     */
+    AMD_GIC(1, 0, 1, 40),                     // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 2)
+    /*
+     * GIC Interface for Cluster 1 CPU 0
+     */
+    AMD_GIC(2, 1, 0, 41),                     // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 3)
+    /*
+     * GIC Interface for Cluster 1 CPU 1
+     */
+    AMD_GIC(3, 1, 1, 42),                     // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 4)
+    /*
+     * GIC Interface for Cluster 2 CPU 0
+     */
+    AMD_GIC(4, 2, 0, 43),                     // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 5)
+    /*
+     * GIC Interface for Cluster 2 CPU 1
+     */
+    AMD_GIC(5, 2, 1, 44),                     // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 6)
+    /*
+     * GIC Interface for Cluster 3 CPU 0
+     */
+    AMD_GIC(6, 3, 0, 45),                     // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 7)
+    /*
+     * GIC Interface for Cluster 3 CPU 1
+     */
+    AMD_GIC(7, 3, 1, 46),                     // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+  },
+  /*
+   * GIC Distributor
+   */
+    AMD_GICD(GICD_ID, GICD_VECTOR),           // EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE
+  /*
+   * GIC MSI Frame
+   */
+  AMD_GICM(GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE),
+};
+
+
+STATIC
+EFI_STATUS
+BuildGicC (
+  EFI_ACPI_5_1_GIC_STRUCTURE *GicC,
+  UINT32 CpuNum,
+  UINT32 ClusterId,
+  UINT32 CoreId,
+  EFI_PHYSICAL_ADDRESS MpParkingBase
+  )
+{
+  UINT32 MpId, PmuSpi;
+  EFI_STATUS Status;
+
+  MpId = (UINT32) GET_MPID (ClusterId, CoreId);
+  Status = mAmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuSpi);
+  if (EFI_ERROR (Status))
+    return Status;
+
+  GicC->Type = EFI_ACPI_5_1_GIC;
+  GicC->Length = sizeof (EFI_ACPI_5_1_GIC_STRUCTURE);
+  GicC->Reserved = EFI_ACPI_RESERVED_WORD;
+  GicC->CPUInterfaceNumber = CpuNum;
+  GicC->AcpiProcessorUid = MpId;
+  GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED;
+  GicC->ParkingProtocolVersion = PARKING_PROTOCOL_VERSION;
+  GicC->ParkedAddress = PARKED_ADDRESS(MpParkingBase, ClusterId, CoreId);
+  GicC->PhysicalBaseAddress = GIC_BASE;
+  GicC->GICV = GICV_BASE;
+  GicC->GICH = GICH_BASE;
+  GicC->VGICMaintenanceInterrupt = VGIC_MAINT_INT;
+  GicC->GICRBaseAddress = GICVR_BASE;
+  GicC->PerformanceInterruptGsiv = PmuSpi + GSIV_SPI_OFFSET;
+  GicC->MPIDR = MpId;
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+BuildGicD (
+  EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD,
+  UINT32 GicId,
+  UINT32 SystemVectorBase
+  )
+{
+  GicD->Type = EFI_ACPI_5_1_GICD;
+  GicD->Length = sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+  GicD->Reserved1 = EFI_ACPI_RESERVED_WORD;
+  GicD->GicId = GicId;
+  GicD->PhysicalBaseAddress = GICD_BASE;
+  GicD->SystemVectorBase = SystemVectorBase;
+#if 0
+  GicD->Reserved2 = EFI_ACPI_RESERVED_DWORD;
+#else
+  GicD->GicVersion = EFI_ACPI_RESERVED_BYTE;
+  GicD->Reserved2[0] = EFI_ACPI_RESERVED_BYTE;
+  GicD->Reserved2[1] = EFI_ACPI_RESERVED_BYTE;
+  GicD->Reserved2[2] = EFI_ACPI_RESERVED_BYTE;
+#endif
+}
+
+
+STATIC
+VOID
+BuildGicM (
+  EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM,
+  UINT32 MsiFrameId,
+  UINT16 SpiCount,
+  UINT16 SpiBase
+  )
+{
+  GicM->Type = EFI_ACPI_5_1_GIC_MSI_FRAME;
+  GicM->Length = sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE);
+  GicM->Reserved1 = EFI_ACPI_RESERVED_WORD;
+  GicM->GicMsiFrameId = MsiFrameId;
+  GicM->PhysicalBaseAddress = GIC_MSI_FRAME;
+  GicM->Flags = MSI_TYPER_FLAG;
+  GicM->SPICount = SpiCount;
+  GicM->SPIBase = SpiBase;
+}
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+MadtHeader (
+  VOID
+  )
+{
+  EFI_ACPI_5_1_GIC_STRUCTURE             *GicC;
+  EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD;
+  EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE   *GicM;
+  ARM_CORE_INFO                          *ArmCoreInfoTable;
+  UINTN                                  CoreCount, CpuNum;
+  EFI_STATUS                             Status;
+  EFI_PHYSICAL_ADDRESS                   MpParkingBase;
+  UINTN                                  MpParkingSize;
+
+  Status = gBS->LocateProtocol (
+               &gAmdMpCoreInfoProtocolGuid,
+               NULL,
+               (VOID **)&mAmdMpCoreInfoProtocol
+               );
+  ASSERT_EFI_ERROR (Status);
+
+  // Get pointer to ARM core info table
+  ArmCoreInfoTable = mAmdMpCoreInfoProtocol->GetArmCoreInfoTable (&CoreCount);
+  ASSERT (ArmCoreInfoTable != NULL);
+
+  // Make sure SoC's core count does not exceed what we want to build
+  ASSERT (CoreCount <= NUM_CORES);
+  ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount));
+
+  MpParkingSize = 0;
+  MpParkingBase =  mAmdMpCoreInfoProtocol->GetMpParkingBase(&MpParkingSize);
+  if (MpParkingBase && MpParkingSize < (CoreCount * SIZE_4KB)) {
+    DEBUG ((EFI_D_ERROR, "MADT: Parking Protocol not supported.\n"));
+    MpParkingBase = 0;
+  }
+
+  GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0];
+  AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
+
+  for (CpuNum = 0; CpuNum < CoreCount; ++CpuNum, ++GicC) {
+    DEBUG ((EFI_D_ERROR, "MADT: Core[%d]: ClusterId = %d   CoreId = %d\n",
+            CpuNum, ArmCoreInfoTable[CpuNum].ClusterId, ArmCoreInfoTable[CpuNum].CoreId));
+
+    Status = BuildGicC (GicC, CpuNum,
+                ArmCoreInfoTable[CpuNum].ClusterId,
+                ArmCoreInfoTable[CpuNum].CoreId,
+                MpParkingBase
+                );
+    ASSERT_EFI_ERROR (Status);
+
+    AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_STRUCTURE);
+  }
+
+  GicD = (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length);
+  BuildGicD (GicD, GICD_ID, GICD_VECTOR);
+  AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+
+  GicM = (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length);
+  BuildGicM (GicM, GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE);
+  AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE);
+
+  return &AcpiMadt.Header.Header;
+}
+
diff --git a/Platforms/AMD/Styx/AcpiTables/Mcfg.c b/Platforms/AMD/Styx/AcpiTables/Mcfg.c
new file mode 100644
index 0000000..4fc18e8
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Mcfg.c
@@ -0,0 +1,51 @@
+/** @file
+
+  ACPI Memory mapped configuration space base address Description Table (MCFG).
+  Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+  downloadable at http://www.pcisig.com/home
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+  This program and the accompanying materials are licensed and
+  made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the
+  license may be found at http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+#if STYX_A0
+#define END_PCI_BUS_NUMBER                15
+#else
+#define END_PCI_BUS_NUMBER                255
+#endif
+
+#pragma pack(push, 1)
+
+typedef struct {
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure;
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE AcpiMcfg = {
+  { AMD_ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+    EFI_ACPI_RESERVED_QWORD },
+  { 0xF0000000ULL, 0, 0, END_PCI_BUS_NUMBER, EFI_ACPI_RESERVED_DWORD }
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+McfgHeader (
+  VOID
+  )
+{
+  return &AcpiMcfg.Header.Header;
+}
diff --git a/Platforms/AMD/Styx/AcpiTables/Spcr.c b/Platforms/AMD/Styx/AcpiTables/Spcr.c
new file mode 100644
index 0000000..719c276
--- /dev/null
+++ b/Platforms/AMD/Styx/AcpiTables/Spcr.c
@@ -0,0 +1,124 @@
+/** @file
+
+  Serial Port Console Redirection Table
+  © 2000 - 2014 Microsoft Corporation. All rights reserved.
+  http://go.microsoft.com/fwlink/?linkid=403368
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#pragma pack(push, 1)
+
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011   3
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE AcpiSpcr = {
+  //
+  // Header
+  //
+  AMD_ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+                   EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+                   2), /* New MS definition for PL011 support */
+  //
+  // InterfaceType
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011,
+  //
+  // Reserved[3]
+  //
+  {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+  //
+  // BaseAddress
+  //
+  AMD_GASN(FixedPcdGet64(PcdSerialRegisterBase)),
+  //
+  // InterruptType
+  //
+  0,
+  //
+  // Irq
+  //
+  0,
+  //
+  // GlobalSystemInterrupt
+  //
+  0x148,
+  //
+  // BaudRate
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+  //
+  // Parity
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+  //
+  // StopBits
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+  //
+  // FlowControl
+  //
+  0,
+  //
+  // TerminalType
+  //
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+  //
+  // Language
+  //
+  EFI_ACPI_RESERVED_BYTE,
+  //
+  // PciDeviceId
+  //
+  0xFFFF,
+  //
+  // PciVendorId
+  //
+  0xFFFF,
+  //
+  // PciBusNumber
+  //
+  0x00,
+  //
+  // PciDeviceNumber
+  //
+  0x00,
+  //
+  // PciFunctionNumber
+  //
+  0x00,
+  //
+  // PciFlags
+  //
+  0,
+  //
+  // PciSegment
+  //
+  0,
+  //
+  // Reserved2
+  //
+  EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+SpcrHeader (
+  VOID
+  )
+{
+  return &AcpiSpcr.Header;
+}
+
diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec
new file mode 100644
index 0000000..6624f8c
--- /dev/null
+++ b/Platforms/AMD/Styx/AmdStyx.dec
@@ -0,0 +1,113 @@
+#/** @file
+# AmdStyx package.
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+#
+#    This program and the accompanying materials are licensed and made
+#    available under the terms and conditions of the BSD License which
+#    accompanies this distribution. The full text of the license may be
+#    found at http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = AmdStyx
+  PACKAGE_GUID                   = 58353cd1-61fb-4f9e-93f7-c43961d39b01
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  Common
+
+[LibraryClasses]
+
+[Ppis]
+  gAmdStyxPlatInitPpiGuid    = { 0xcbff429c, 0xd3e3, 0x4c50, { 0xac, 0x1a, 0x1c, 0xd2, 0xfe, 0x15, 0x1a, 0xd7 } }
+
+[Protocols]
+  gAmdMpBootProtocolGuid     = { 0xe21eac84, 0x9fbf, 0x4808, { 0x83, 0x93, 0xe1, 0x93, 0x97, 0x23, 0x48, 0xab } }
+  gAmdMpCoreInfoProtocolGuid = { 0x0dba25f8, 0x2da1, 0x4ec5, { 0x89, 0x5d, 0x32, 0x1e, 0xd6, 0x1e, 0x3f, 0x43 } }
+
+[Guids]
+  gAmdStyxTokenSpaceGuid     = { 0x220d9653, 0x4a0e, 0x40bc, { 0xb3, 0x65, 0x2f, 0xbb, 0xa2, 0xd9, 0x03, 0x45 } }
+  gAmdStyxMpCoreInfoGuid     = { 0x68efeabd, 0xcb77, 0x4aa5, { 0xbf, 0x0c, 0xa3, 0x31, 0xfc, 0xcf, 0x76, 0x66 } }
+
+[PcdsDynamic]
+  gAmdStyxTokenSpaceGuid.PcdSocCoreCount|1|UINT32|0x00000100
+  gAmdStyxTokenSpaceGuid.PcdSocCpuId|1|UINT32|0x00000101
+
+  gAmdStyxTokenSpaceGuid.PcdEthMacA|0|UINT64|0x000d0001
+  gAmdStyxTokenSpaceGuid.PcdEthMacB|0|UINT64|0x000d0002
+
+[PcdsFixedAtBuild]
+  # CPUID Register
+  gAmdStyxTokenSpaceGuid.PcdCpuIdRegister|0xE0000010|UINT32|0x00000200
+
+  # FDT support
+  gAmdStyxTokenSpaceGuid.PcdStyxFdt|{ 0xe4, 0x08, 0x0d, 0x04, 0x9a, 0x47, 0x4b, 0x42, 0x8c, 0x42, 0x36, 0x64, 0xdf, 0x79, 0x3f, 0x4b }|VOID*|0x00010000
+
+  # Synopsys SATA Controller
+  gAmdStyxTokenSpaceGuid.PcdSata0CtrlAxiSlvPort|0xE0300000|UINT32|0x00020000
+  gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8|UINT8|0x00020001
+  gAmdStyxTokenSpaceGuid.PcdSataPi|0xFF|UINT32|0x00020002
+  gAmdStyxTokenSpaceGuid.PcdSataPortMode|0|UINT16|0x00020003
+  gAmdStyxTokenSpaceGuid.PcdSataPortMpsp|TRUE|BOOLEAN|0x00020004
+  gAmdStyxTokenSpaceGuid.PcdSataSmpsSupport|FALSE|BOOLEAN|0x00020005
+  gAmdStyxTokenSpaceGuid.PcdSataSssSupport|TRUE|BOOLEAN|0x00020006
+  gAmdStyxTokenSpaceGuid.PcdSataPortCpd|TRUE|BOOLEAN|0x00020007
+  gAmdStyxTokenSpaceGuid.PcdSata1CtrlAxiSlvPort|0xE0D00000|UINT32|0x00020008
+  gAmdStyxTokenSpaceGuid.PcdSata1PortCount|8|UINT8|0x00020009
+
+  # UART
+  gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0xE1010000|UINT64|0x00030000
+  gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200|UINT32|0x00030001
+
+  # GIC
+  gAmdStyxTokenSpaceGuid.PcdGicVersion|0x2|UINT8|0x00040000
+  gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase|0xE1140000|UINT64|0x00040001
+  gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase|0xE116F000|UINT64|0x00040002
+  gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt|25|UINT32|0x00040003
+  gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase|0x00000000|UINT64|0x00040004
+  gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase|0xE1180000|UINT64|0x00040005
+
+  # Timers (GTDT)
+  gAmdStyxTokenSpaceGuid.PcdCntControlBase|0xFFFFFFFFFFFFFFFF|UINT64|0x00050000
+  gAmdStyxTokenSpaceGuid.PcdCntReadBase|0x00000000E0B90000|UINT64|0x00050001
+  gAmdStyxTokenSpaceGuid.PcdCntCTLBase|0x00000000E0BD0000|UINT64|0x00050002
+  gAmdStyxTokenSpaceGuid.PcdCntBase0|0x00000000E0BE0000|UINT64|0x00050003
+  gAmdStyxTokenSpaceGuid.PcdCntEL0Base0|0x00000000E0BF0000|UINT64|0x00050004
+  gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase|0x00000000E0BB0000|UINT64|0x00050005
+  gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase|0x00000000E0BC0000|UINT64|0x00050006
+  gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV|371|UINT32|0x00050007
+  gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV|369|UINT32|0x00050008
+
+  # Trusted-Firmware
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport|TRUE|BOOLEAN|0x00060000
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase|0x8000000000|UINT64|0x00060001
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize|0xE80000|UINT64|0x0006002
+
+  # ISCP
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE|BOOLEAN|0x00070000
+
+  # PSCI
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE|BOOLEAN|0x00080000
+  gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext|0|UINT64|0x00080001
+
+  # Cores Per cluster
+  gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster|2|UINT32|0x00090000
+
+  # UEFI entry point
+  gAmdStyxTokenSpaceGuid.PcdUefiEntryAddress|0x8000E80000|UINT64|0x000a0000
+
+  # Parking Protocol
+  gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion|1|UINT32|0x000b0000
+
+  # The original offset in memory of the NV store firmware volume, before
+  # relocating it to a dynamically allocated buffer. We need this to correlate
+  # flash accesses to the in-memory copy with LBAs in the actual SPI flash
+  gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|0|UINT64|0x000c0000
+  # block size to use when invoking the ISCP FV methods
+  gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize|0x1000|UINT32|0x000c0001
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/AmdModulePkg.dec b/Platforms/AMD/Styx/Binary/AmdModulePkg/AmdModulePkg.dec
new file mode 100644
index 0000000..15ee61b
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/AmdModulePkg.dec
@@ -0,0 +1,133 @@
+#**
+# @file
+#
+# AmdModulePkg.dec
+#
+# AMD-specific package declaration file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 337482 $ @e date: $Date: 2016-03-11 21:39:02 -0600 (Fri, 11 Mar 2016) $
+#
+#
+##*****************************************************************************
+#
+#  Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = AmdModulePkg
+  PACKAGE_GUID                   = E967965B-4447-4CBB-9521-898B5A329240
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER
+#
+################################################################################
+[Includes]
+  Common
+  Include
+  Include/Library
+  Include/Ppi
+  Include/Protocol
+
+
+[LibraryClasses]
+  ##  @libraryclass  Provides a library function to get a DXE driver name
+  ##
+
+[Protocols]
+  gAmdIscpDxeProtocolGuid = { 0x05c794c8, 0x6aef, 0x4450, { 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 } }
+  gAmdRasApeiProtocolGuid = { 0xe9dbcc60, 0x8f93, 0x47ed, { 0x84, 0x78, 0x46, 0x78, 0xf1, 0x9f, 0x73, 0x4a } }
+
+[Ppis]
+  gPeiIscpPpiGuid                    = { 0xca2c1ecd, 0xc702, 0x49b1, { 0xae, 0x24, 0x9b, 0x6f, 0xa8, 0x71, 0x3b, 0x23 } }
+  gPeiFusePpiGuid                    = { 0xe074fa9f, 0x1bc7, 0x4af9, { 0x8f, 0x0d, 0x90, 0x0b, 0x76, 0x50, 0x5f, 0xfe } }
+  gPeiGionbPpiGuid                   = { 0x24b8ebcc, 0x3871, 0x4b39, { 0xaa, 0x1a, 0x0f, 0x86, 0x7d, 0xbf, 0x97, 0xc6 } }
+
+[Guids]
+  gAmdModulePkgTokenSpaceGuid        = { 0x2f9003d7, 0xac98, 0x407d, { 0xae, 0x38, 0x9d, 0xbf, 0x81, 0x27, 0xe5, 0xb1 } }
+  gAmdModulePkgVariableGuid          = { 0xf3dd4189, 0xe1b7, 0x49da, { 0xa5, 0xd3, 0x34, 0x28, 0x6f, 0xae, 0x2f, 0x01 } }
+
+[PcdsFixedAtBuild]
+  gAmdModulePkgTokenSpaceGuid.PcdFdkVersionMajor|0x1|UINT8|0x00000026
+  gAmdModulePkgTokenSpaceGuid.PcdFdkVersionMinor|0x0|UINT8|0x00000027
+  gAmdModulePkgTokenSpaceGuid.PcdFdkVersionPoint|0x0|UINT8|0x00000028
+  gAmdModulePkgTokenSpaceGuid.PcdFdkVersionSubpoint|0x2|UINT8|0x00000029
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+  gAmdModulePkgTokenSpaceGuid.PcdCCPBase|0xE0100000|UINT64|0x00000001
+  gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes0|0xE0B00000|UINT64|0x00000002
+  gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes1|0xE0B20000|UINT64|0x00000003
+  gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes2|0xE0B40000|UINT64|0x00000004
+  gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes3|0xE0B60000|UINT64|0x00000005
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdes0|0xE1200000|UINT64|0x00000006
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdes1|0xE1210000|UINT64|0x00000007
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdes2|0xE1220000|UINT64|0x00000008
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdes3|0xE1230000|UINT64|0x00000009
+  gAmdModulePkgTokenSpaceGuid.PcdEthernetSerdes|0xE1240000|UINT64|0x0000000a
+  gAmdModulePkgTokenSpaceGuid.PcdSataMMU401|0xE0200000|UINT64|0x0000000b
+  gAmdModulePkgTokenSpaceGuid.PcdDMA330MMU401|0xE0400000|UINT64|0x0000000c
+  gAmdModulePkgTokenSpaceGuid.PcdCCN504Space|0xE8000000|UINT64|0x0000000d
+  gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2|UINT8|0x0000000e
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000|UINT32|0x0000000f
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000|UINT32|0x00000010
+
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp|FALSE|BOOLEAN|0x00000033
+
+#XGMAC ETH0 MAC
+  gAmdModulePkgTokenSpaceGuid.PcdEthMacA|0|UINT64|0x0000011
+#XGMAC ETH1 MAC
+  gAmdModulePkgTokenSpaceGuid.PcdEthMacB|0|UINT64|0x0000012
+
+  gAmdModulePkgTokenSpaceGuid.PcdPort0PhyMode|1|UINT8|0x0000013
+  gAmdModulePkgTokenSpaceGuid.PcdPort1PhyMode|1|UINT8|0x0000014
+  gAmdModulePkgTokenSpaceGuid.PcdPort0NetSpeed|1|UINT8|0x0000015
+  gAmdModulePkgTokenSpaceGuid.PcdPort1NetSpeed|1|UINT8|0x0000016
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeEnable|FALSE|BOOLEAN|0x0000017
+
+  gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|0|UINT8|0x00000018
+  gAmdModulePkgTokenSpaceGuid.PcdPcieGenMax|2|UINT8|0x00000019
+  gAmdModulePkgTokenSpaceGuid.PcdIocClockGating|1|UINT8|0x0000001a
+  gAmdModulePkgTokenSpaceGuid.PcdAifClockGating|1|UINT8|0x0000001b
+  gAmdModulePkgTokenSpaceGuid.PcdPcieFuseEnable|TRUE|BOOLEAN|0x000001c
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1|UINT8|0x000001d
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1|UINT8|0x000001e
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1|UINT8|0x000001f
+  gAmdModulePkgTokenSpaceGuid.PcdPcieGen3|0|UINT8|0x00000020
+  gAmdModulePkgTokenSpaceGuid.PcdPcieGen2|0|UINT8|0x00000021
+  gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|FALSE|BOOLEAN|0x0000022
+
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeRev|1|UINT8|0x0000002A
+
+  gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen1|31|UINT32|0x0000002B
+  gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen2|47|UINT32|0x0000002C
+  gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen3|63|UINT32|0x0000002D
+  gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen1|31|UINT32|0x0000002E
+  gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen2|47|UINT32|0x0000002F
+  gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen3|63|UINT32|0x00000030
+
+  gAmdModulePkgTokenSpaceGuid.PcdXgbePort0SwKrTrain|0|UINT8|0x00000031
+  gAmdModulePkgTokenSpaceGuid.PcdXgbePort1SwKrTrain|0|UINT8|0x00000032
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CoreState.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CoreState.h
new file mode 100644
index 0000000..7ce4998
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CoreState.h
@@ -0,0 +1,66 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * CoreState.h
+ *
+ * CPU Core State Structures and Definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+//#########################################################################
+//#########################################################################
+//#########################################################################
+//        NOTE: This file shared between SCP and UEFI, make sure all     //
+//              changes are reflected in both copies.                    //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef CORESTATUS_H_
+#define CORESTATUS_H_
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/// Core State Enumeration
+typedef enum {
+  CPU_CORE_UNDEFINED = 0,         ///< Core is undefined
+  CPU_CORE_DISABLED,              ///< Core is disabled
+  CPU_CORE_POWERUP,               ///< Core/cluster is powered up
+  CPU_CORE_POWERDOWN,             ///< Core/cluster is powered down
+  CPU_CORE_RESET,                 ///< Core is powered but in reset
+  CPU_CORE_RUN,                   ///< Core is running
+  CPU_CORE_SLEEP,                 ///< Core is powered and sleeping (TBD)
+} CPU_CORE_STATE;
+
+/// SOC Core Status Structure
+typedef struct {
+  UINT32            ClusterId;    ///< CPU Cluster ID
+  UINT32            CoreId;       ///< CPU Core ID
+  CPU_CORE_STATE    Status;       ///< Core State Enumeration
+  UINT64            ResetVector;  ///< CPU Core Reset Vector
+} SocCoreStatus;
+
+#endif /* CORESTATUS_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CpuIscp.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CpuIscp.h
new file mode 100644
index 0000000..ca86894
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CpuIscp.h
@@ -0,0 +1,492 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * MemIscp.h
+ *
+ * Contains common Memory Training ISCP-related structures and defines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+//        NOTE: This file shared between SCP and UEFI, make sure all     //
+//              changes are reflected in both copies.                    //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef CPUISCP_H_
+#define CPUISCP_H_
+
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+  #include <ProcessorBind.h>  // Included just so this file can be built into both the RTOS
+                              // and UEFI without needing separate copies for both build
+                              // environments.
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+  /// Processor ID
+  typedef struct {
+    UINT32                   ProcIDMsd;            ///< Processor ID Msd
+    UINT32                   ProcIDLsd;            ///< Processor ID Lsd
+  } ISCP_PROC_ID;
+
+  /// Processor Type
+  typedef enum {
+    ISCP_CPU_TYPE_OTHER = 1,                       ///< Other
+    ISCP_CPU_TYPE_UNKNOWN,                         ///< Unknown
+    ISCP_CPU_TYPE_CENTRAL_PROCESSOR,               ///< Central Processor
+    ISCP_CPU_TYPE_MATH_COPROCESSOR,                ///< Math Coprocessor
+    ISCP_CPU_TYPE_DSP_PROCESSOR,                   ///< DSP Processor
+    ISCP_CPU_TYPE_VIDEO_PROCESSOR                  ///< Video Processor
+  } ISCP_PROCESSOR_TYPE;
+
+  /// Processor Information - Processor Family.
+  typedef enum {
+    ISCP_ProcessorFamilyOther                  = 0x01,  ///< Processor Family - Other
+    ISCP_ProcessorFamilyUnknown                = 0x02,  ///< Processor Family - Unknown
+    ISCP_ProcessorFamily8086                   = 0x03,  ///< Processor Family - 8086
+    ISCP_ProcessorFamily80286                  = 0x04,  ///< Processor Family - 80286
+    ISCP_ProcessorFamilyIntel386               = 0x05,  ///< Processor Family - Intel 386
+    ISCP_ProcessorFamilyIntel486               = 0x06,  ///< Processor Family - Intel 486
+    ISCP_ProcessorFamily8087                   = 0x07,  ///< Processor Family - 8087
+    ISCP_ProcessorFamily80287                  = 0x08,  ///< Processor Family - 80287
+    ISCP_ProcessorFamily80387                  = 0x09,  ///< Processor Family - 80387
+    ISCP_ProcessorFamily80487                  = 0x0A,  ///< Processor Family - 80487
+    ISCP_ProcessorFamilyPentium                = 0x0B,  ///< Processor Family - Pentium
+    ISCP_ProcessorFamilyPentiumPro             = 0x0C,  ///< Processor Family - Pentium Pro
+    ISCP_ProcessorFamilyPentiumII              = 0x0D,  ///< Processor Family - Pentium II
+    ISCP_ProcessorFamilyPentiumMMX             = 0x0E,  ///< Processor Family - Pentium MMX
+    ISCP_ProcessorFamilyCeleron                = 0x0F,  ///< Processor Family - Celeron
+    ISCP_ProcessorFamilyPentiumIIXeon          = 0x10,  ///< Processor Family - Pentium II Xeon
+    ISCP_ProcessorFamilyPentiumIII             = 0x11,  ///< Processor Family - Pentium III
+    ISCP_ProcessorFamilyM1                     = 0x12,  ///< Processor Family - M1
+    ISCP_ProcessorFamilyM2                     = 0x13,  ///< Processor Family - M2
+    ISCP_ProcessorFamilyIntelCeleronM          = 0x14,  ///< Processor Family - Intel Celeron
+    ISCP_ProcessorFamilyIntelPentium4Ht        = 0x15,  ///< Processor Family - Intel Pentium 4Ht
+    ISCP_ProcessorFamilyAmdDuron               = 0x18,  ///< Processor Family - AMD Duron
+    ISCP_ProcessorFamilyK5                     = 0x19,  ///< Processor Family - K5
+    ISCP_ProcessorFamilyK6                     = 0x1A,  ///< Processor Family - K6
+    ISCP_ProcessorFamilyK6_2                   = 0x1B,  ///< Processor Family - K6-2
+    ISCP_ProcessorFamilyK6_3                   = 0x1C,  ///< Processor Family - K6-3
+    ISCP_ProcessorFamilyAmdAthlon              = 0x1D,  ///< Processor Family - AMD Athlon
+    ISCP_ProcessorFamilyAmd29000               = 0x1E,  ///< Processor Family - AMD 29000
+    ISCP_ProcessorFamilyK6_2Plus               = 0x1F,  ///< Processor Family - K6-2 Plus
+    ISCP_ProcessorFamilyPowerPC                = 0x20,  ///< Processor Family - Power PC
+    ISCP_ProcessorFamilyPowerPC601             = 0x21,  ///< Processor Family - Power PC 601
+    ISCP_ProcessorFamilyPowerPC603             = 0x22,  ///< Processor Family - Power PC 603
+    ISCP_ProcessorFamilyPowerPC603Plus         = 0x23,  ///< Processor Family - Power PC 603 Plus
+    ISCP_ProcessorFamilyPowerPC604             = 0x24,  ///< Processor Family - Power PC 604
+    ISCP_ProcessorFamilyPowerPC620             = 0x25,  ///< Processor Family - Power PC 620
+    ISCP_ProcessorFamilyPowerPCx704            = 0x26,  ///< Processor Family - Power PC x704
+    ISCP_ProcessorFamilyPowerPC750             = 0x27,  ///< Processor Family - Power PC 750
+    ISCP_ProcessorFamilyIntelCoreDuo           = 0x28,  ///< Processor Family - Intel Core Duo
+    ISCP_ProcessorFamilyIntelCoreDuoMobile     = 0x29,  ///< Processor Family - Intel core Duo Mobile
+    ISCP_ProcessorFamilyIntelCoreSoloMobile    = 0x2A,  ///< Processor Family - Intel Core Solo Mobile
+    ISCP_ProcessorFamilyIntelAtom              = 0x2B,  ///< Processor Family - Intel Atom
+    ISCP_ProcessorFamilyAlpha                  = 0x30,  ///< Processor Family - Alpha
+    ISCP_ProcessorFamilyAlpha21064             = 0x31,  ///< Processor Family - Alpha 21064
+    ISCP_ProcessorFamilyAlpha21066             = 0x32,  ///< Processor Family - Alpha 21166
+    ISCP_ProcessorFamilyAlpha21164             = 0x33,  ///< Processor Family - Alpha 21164
+    ISCP_ProcessorFamilyAlpha21164PC           = 0x34,  ///< Processor Family - Alpha 21164PC
+    ISCP_ProcessorFamilyAlpha21164a            = 0x35,  ///< Processor Family - Alpha 21164a
+    ISCP_ProcessorFamilyAlpha21264             = 0x36,  ///< Processor Family - Alpha 21264
+    ISCP_ProcessorFamilyAlpha21364             = 0x37,  ///< Processor Family - Alpha 21364
+    ISCP_ProcessorFamilyAmdTurionIIUltraDualCoreMobileM    = 0x38,  ///< Processor Family - AMD Turion II Ultra Dual Core Mobile M
+    ISCP_ProcessorFamilyAmdTurionIIDualCoreMobileM         = 0x39,  ///< Processor Family - AMD Turion II Dual Core Mobile M
+    ISCP_ProcessorFamilyAmdAthlonIIDualCoreM   = 0x3A,  ///< Processor Family - AMD Athlon II Dual Core M
+    ISCP_ProcessorFamilyAmdOpteron6100Series   = 0x3B,  ///< Processor Family - AMD Opteron 6100 Series
+    ISCP_ProcessorFamilyAmdOpteron4100Series   = 0x3C,  ///< Processor Family - AMD Opteron 4100 Series
+    ISCP_ProcessorFamilyAmdOpteron6200Series   = 0x3D,  ///< Processor Family - AMD Opteron 6200 Series
+    ISCP_ProcessorFamilyAmdOpteron4200Series   = 0x3E,  ///< Processor Family - AMD Opteron 4200 Series
+    ISCP_ProcessorFamilyAmdFxSeries            = 0x3F,  ///< Processor Family - AMD FX Series
+    ISCP_ProcessorFamilyMips                   = 0x40,  ///< Processor Family - MIPs
+    ISCP_ProcessorFamilyMIPSR4000              = 0x41,  ///< Processor Family - MIPs R4000
+    ISCP_ProcessorFamilyMIPSR4200              = 0x42,  ///< Processor Family - MIPs R4200
+    ISCP_ProcessorFamilyMIPSR4400              = 0x43,  ///< Processor Family - MIPs R4400
+    ISCP_ProcessorFamilyMIPSR4600              = 0x44,  ///< Processor Family - MIPs R4600
+    ISCP_ProcessorFamilyMIPSR10000             = 0x45,  ///< Processor Family - MIPs R10000
+    ISCP_ProcessorFamilyAmdCSeries             = 0x46,  ///< Processor Family - AMD C Series
+    ISCP_ProcessorFamilyAmdESeries             = 0x47,  ///< Processor Family - AMD E Series
+    ISCP_ProcessorFamilyAmdASeries             = 0x48,  ///< Processor Family - AMD A Series
+    ISCP_ProcessorFamilyAmdGSeries             = 0x49,  ///< Processor Family - AMD G Series
+    ISCP_ProcessorFamilyAmdZSeries             = 0x4A,  ///< Processor Family - AMD Z Series
+    ISCP_ProcessorFamilyAmdRSeries             = 0x4B,  ///< Processor Family - AMD R Series
+    ISCP_ProcessorFamilyAmdOpteron4300         = 0x4C,  ///< Processor Family - AMD Opteron 4300
+    ISCP_ProcessorFamilyAmdOpteron6300         = 0x4D,  ///< Processor Family - AMD Opteron 6300
+    ISCP_ProcessorFamilyAmdOpteron3300         = 0x4E,  ///< Processor Family - AMD Opteron 3300
+    ISCP_ProcessorFamilyAmdFireProSeries       = 0x4F,  ///< Processor Family - AMD Fire Pro Series
+    ISCP_ProcessorFamilySparc                  = 0x50,  ///< Processor Family - Sparc
+    ISCP_ProcessorFamilySuperSparc             = 0x51,  ///< Processor Family - Super Sparc
+    ISCP_ProcessorFamilymicroSparcII           = 0x52,  ///< Processor Family - Sparc II
+    ISCP_ProcessorFamilymicroSparcIIep         = 0x53,  ///< Processor Family - Sparc IIep
+    ISCP_ProcessorFamilyUltraSparc             = 0x54,  ///< Processor Family - Ultra Sparc
+    ISCP_ProcessorFamilyUltraSparcII           = 0x55,  ///< Processor Family - Ultra Sparc II
+    ISCP_ProcessorFamilyUltraSparcIii          = 0x56,  ///< Processor Family - Ultra Sparc Iii
+    ISCP_ProcessorFamilyUltraSparcIII          = 0x57,  ///< Processor Family - Ultra Sparc III
+    ISCP_ProcessorFamilyUltraSparcIIIi         = 0x58,  ///< Processor Family - Ultra Sparc IIIi
+    ISCP_ProcessorFamily68040                  = 0x60,  ///< Processor Family - 68040
+    ISCP_ProcessorFamily68xxx                  = 0x61,  ///< Processor Family - 68xxx
+    ISCP_ProcessorFamily68000                  = 0x62,  ///< Processor Family - 68000
+    ISCP_ProcessorFamily68010                  = 0x63,  ///< Processor Family - 68010
+    ISCP_ProcessorFamily68020                  = 0x64,  ///< Processor Family - 68020
+    ISCP_ProcessorFamily68030                  = 0x65,  ///< Processor Family - 68030
+    ISCP_ProcessorFamilyAmdOpteronASeries      = 0x69,  ///< Processor Family - AMD Opteron A Series
+    ISCP_ProcessorFamilyHobbit                 = 0x70,  ///< Processor Family - Hobbit
+    ISCP_ProcessorFamilyCrusoeTM5000           = 0x78,  ///< Processor Family - Crusoe TM5000
+    ISCP_ProcessorFamilyCrusoeTM3000           = 0x79,  ///< Processor Family - Crusoe TM3000
+    ISCP_ProcessorFamilyEfficeonTM8000         = 0x7A,  ///< Processor Family - Efficeon TM8000
+    ISCP_ProcessorFamilyWeitek                 = 0x80,  ///< Processor Family - Weitek
+    ISCP_ProcessorFamilyItanium                = 0x82,  ///< Processor Family - Itanium
+    ISCP_ProcessorFamilyAmdAthlon64            = 0x83,  ///< Processor Family - AMD Athlon64
+    ISCP_ProcessorFamilyAmdOpteron             = 0x84,  ///< Processor Family - AMD Opeteron
+    ISCP_ProcessorFamilyAmdSempron             = 0x85,  ///< Processor Family - AMD Sempron
+    ISCP_ProcessorFamilyAmdTurion64Mobile      = 0x86,  ///< Processor Family - AMD Turion 64 Modbile
+    ISCP_ProcessorFamilyDualCoreAmdOpteron     = 0x87,  ///< Processor Family - AMD Dual Core Opteron
+    ISCP_ProcessorFamilyAmdAthlon64X2DualCore  = 0x88,  ///< Processor Family - AMD Athlon 64 X2 Dual Core
+    ISCP_ProcessorFamilyAmdTurion64X2Mobile    = 0x89,  ///< Processor Family - AMD Turion 64 X2 Mobile
+    ISCP_ProcessorFamilyQuadCoreAmdOpteron     = 0x8A,  ///< Processor Family - AMD Quad Core Opteron
+    ISCP_ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,  ///< Processor Family - AMD 3rd Generation Opteron
+    ISCP_ProcessorFamilyAmdPhenomFxQuadCore    = 0x8C,  ///< Processor Family - AMD Phenom FX Quad Core
+    ISCP_ProcessorFamilyAmdPhenomX4QuadCore    = 0x8D,  ///< Processor Family - AMD Phenom X4 Quad Core
+    ISCP_ProcessorFamilyAmdPhenomX2DualCore    = 0x8E,  ///< Processor Family - AMD Phenom X2 Quad Core
+    ISCP_ProcessorFamilyAmdAthlonX2DualCore    = 0x8F,  ///< Processor Family - AMD Athlon X2 Dual Core
+    ISCP_ProcessorFamilyPARISC                 = 0x90,  ///< Processor Family - PARISC
+    ISCP_ProcessorFamilyPaRisc8500             = 0x91,  ///< Processor Family - PARISC 8500
+    ISCP_ProcessorFamilyPaRisc8000             = 0x92,  ///< Processor Family - PARISC 8000
+    ISCP_ProcessorFamilyPaRisc7300LC           = 0x93,  ///< Processor Family - PARISC 7300LC
+    ISCP_ProcessorFamilyPaRisc7200             = 0x94,  ///< Processor Family - PARISC 7200
+    ISCP_ProcessorFamilyPaRisc7100LC           = 0x95,  ///< Processor Family - PARISC 7100LC
+    ISCP_ProcessorFamilyPaRisc7100             = 0x96,  ///< Processor Family - PARISC 7100
+    ISCP_ProcessorFamilyV30                    = 0xA0,  ///< Processor Family - V30
+    ISCP_ProcessorFamilyQuadCoreIntelXeon3200Series  = 0xA1,  ///< Processor Family - Intel Quad Core Xeon 3200 Series
+    ISCP_ProcessorFamilyDualCoreIntelXeon3000Series  = 0xA2,  ///< Processor Family - Intel Dual Core Xeon 3000 Series
+    ISCP_ProcessorFamilyQuadCoreIntelXeon5300Series  = 0xA3,  ///< Processor Family - Intel Quad Core Xeon 5300 Series
+    ISCP_ProcessorFamilyDualCoreIntelXeon5100Series  = 0xA4,  ///< Processor Family - Intel Dual Core Xeon 5100 Series
+    ISCP_ProcessorFamilyDualCoreIntelXeon5000Series  = 0xA5,  ///< Processor Family - Intel Dual Core Xeon 5000 Series
+    ISCP_ProcessorFamilyDualCoreIntelXeonLV          = 0xA6,  ///< Processor Family - Intel Dual Core Xeon LV
+    ISCP_ProcessorFamilyDualCoreIntelXeonULV         = 0xA7,  ///< Processor Family - Intel Dual Core Xeon ULV
+    ISCP_ProcessorFamilyDualCoreIntelXeon7100Series  = 0xA8,  ///< Processor Family - Intel Quad Core Xeon 7100 Series
+    ISCP_ProcessorFamilyQuadCoreIntelXeon5400Series  = 0xA9,  ///< Processor Family - Intel Quad Core Xeon 5400 Series
+    ISCP_ProcessorFamilyQuadCoreIntelXeon            = 0xAA,  ///< Processor Family - Intel Quad Core Xeon
+    ISCP_ProcessorFamilyDualCoreIntelXeon5200Series  = 0xAB,  ///< Processor Family - Intel Dual Core Xeon 5200 Series
+    ISCP_ProcessorFamilyDualCoreIntelXeon7200Series  = 0xAC,  ///< Processor Family - Intel Dual Core Xeon 7200 Series
+    ISCP_ProcessorFamilyQuadCoreIntelXeon7300Series  = 0xAD,  ///< Processor Family - Intel Quad Core Xeon 7300 Series
+    ISCP_ProcessorFamilyQuadCoreIntelXeon7400Series  = 0xAE,  ///< Processor Family - Intel Quad Core Xeon 7400 Series
+    ISCP_ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,  ///< Processor Family - Intel Multi-Core Xeon 7400 Series
+    ISCP_ProcessorFamilyPentiumIIIXeon               = 0xB0,  ///< Processor Family - Intel Pentium III Xeon
+    ISCP_ProcessorFamilyPentiumIIISpeedStep          = 0xB1,  ///< Processor Family - Intel Pentium III Speed Step
+    ISCP_ProcessorFamilyPentium4                     = 0xB2,  ///< Processor Family - Pentium 4
+    ISCP_ProcessorFamilyIntelXeon                    = 0xB3,  ///< Processor Family - Intel Xeon
+    ISCP_ProcessorFamilyAS400                        = 0xB4,  ///< Processor Family - AS400
+    ISCP_ProcessorFamilyIntelXeonMP                  = 0xB5,  ///< Processor Family - Intel Xeon MP
+    ISCP_ProcessorFamilyAMDAthlonXP                  = 0xB6,  ///< Processor Family - AMD Athlon XP
+    ISCP_ProcessorFamilyAMDAthlonMP                  = 0xB7,  ///< Processor Family - AMD Athlon MP
+    ISCP_ProcessorFamilyIntelItanium2                = 0xB8,  ///< Processor Family - Intel Itanum2
+    ISCP_ProcessorFamilyIntelPentiumM                = 0xB9,  ///< Processor Family - Intel Pentium M
+    ISCP_ProcessorFamilyIntelCeleronD                = 0xBA,  ///< Processor Family - Intel Celeron D
+    ISCP_ProcessorFamilyIntelPentiumD                = 0xBB,  ///< Processor Family - Intel Pentium D
+    ISCP_ProcessorFamilyIntelPentiumEx               = 0xBC,  ///< Processor Family - Intel pentium Ex
+    ISCP_ProcessorFamilyIntelCoreSolo                = 0xBD,  ///< Processor Family - Intel Core Solo
+    ISCP_ProcessorFamilyReserved                     = 0xBE,  ///< Processor Family - Reserved
+    ISCP_ProcessorFamilyIntelCore2                   = 0xBF,  ///< Processor Family - Intel Core 2
+    ISCP_ProcessorFamilyIntelCore2Solo               = 0xC0,  ///< Processor Family - Intel Core 2 Solo
+    ISCP_ProcessorFamilyIntelCore2Extreme            = 0xC1,  ///< Processor Family - Intel Core 2 Extreme
+    ISCP_ProcessorFamilyIntelCore2Quad               = 0xC2,  ///< Processor Family - Intel Core 2 Quad
+    ISCP_ProcessorFamilyIntelCore2ExtremeMobile      = 0xC3,  ///< Processor Family - Intel Core 2 Extremem Mobile
+    ISCP_ProcessorFamilyIntelCore2DuoMobile          = 0xC4,  ///< Processor Family - Intel core 2 Duo Mobile
+    ISCP_ProcessorFamilyIntelCore2SoloMobile         = 0xC5,  ///< Processor Family - Intel Core 2 Solo Mobile
+    ISCP_ProcessorFamilyIntelCoreI7                  = 0xC6,  ///< Processor Family - Intel Core I7
+    ISCP_ProcessorFamilyDualCoreIntelCeleron         = 0xC7,  ///< Processor Family - Intel Dual Core Celeron
+    ISCP_ProcessorFamilyIBM390                       = 0xC8,  ///< Processor Family - IBM 390
+    ISCP_ProcessorFamilyG4                           = 0xC9,  ///< Processor Family - G4
+    ISCP_ProcessorFamilyG5                           = 0xCA,  ///< Processor Family - G5
+    ISCP_ProcessorFamilyG6                           = 0xCB,  ///< Processor Family - G6
+    ISCP_ProcessorFamilyzArchitecture                = 0xCC,  ///< Processor Family - zArchitecture
+    ISCP_ProcessorFamilyIntelCoreI5                  = 0xCD,  ///< Processor Family - Intel Core I5
+    ISCP_ProcessorFamilyIntelCoreI3                  = 0xCE,  ///< Processor Family - Intel Core I3
+    ISCP_ProcessorFamilyViaC7M                       = 0xD2,  ///< Processor Family - Via C7M
+    ISCP_ProcessorFamilyViaC7D                       = 0xD3,  ///< Processor Family - Via C7D
+    ISCP_ProcessorFamilyViaC7                        = 0xD4,  ///< Processor Family - Via C7
+    ISCP_ProcessorFamilyViaEden                      = 0xD5,  ///< Processor Family - Via Eden
+    ISCP_ProcessorFamilyMultiCoreIntelXeon           = 0xD6,  ///< Processor Family - Intel Multi-core Xeon
+    ISCP_ProcessorFamilyDualCoreIntelXeon3Series     = 0xD7,  ///< Processor Family - Intel Dual-core Xeon 3-Series
+    ISCP_ProcessorFamilyQuadCoreIntelXeon3Series     = 0xD8,  ///< Processor Family - Intel Quad-core Xeon 3-Series
+    ISCP_ProcessorFamilyViaNano                      = 0xD9,  ///< Processor Family - Via Nano
+    ISCP_ProcessorFamilyDualCoreIntelXeon5Series     = 0xDA,  ///< Processor Family - Intel Dual-core Xeon 5-Series
+    ISCP_ProcessorFamilyQuadCoreIntelXeon5Series     = 0xDB,  ///< Processor Family - Intel Quad-core Xeon 5-Series
+    ISCP_ProcessorFamilyDualCoreIntelXeon7Series     = 0xDD,  ///< Processor Family - Intel Dual-core Xeon 7-Series
+    ISCP_ProcessorFamilyQuadCoreIntelXeon7Series     = 0xDE,  ///< Processor Family - Intel Quad-core Xeon 7-Series
+    ISCP_ProcessorFamilyMultiCoreIntelXeon7Series    = 0xDF,  ///< Processor Family - Intel Multi-core Xeon 7-Series
+    ISCP_ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,  ///< Processor Family - Intel Multi-core Xeon 3400-Series
+    ISCP_ProcessorFamilyAmdOpteron3000Series         = 0xE4,  ///< Processor Family - AMD Opteron 3000 Series
+    ISCP_ProcessorFamilyAmdSempronII                 = 0xE5,  ///< Processor Family - AMD Sempron II
+    ISCP_ProcessorFamilyEmbeddedAmdOpteronQuadCore   = 0xE6,  ///< Processor Family - AMD Embedded Opteron Quad Core
+    ISCP_ProcessorFamilyAmdPhenomTripleCore          = 0xE7,  ///< Processor Family - AMD Phonon Triple Core
+    ISCP_ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,  ///< Processor Family - AMD Turion Ultra Dual Core Mobile
+    ISCP_ProcessorFamilyAmdTurionDualCoreMobile      = 0xE9,  ///< Processor Family - AMD Turion Dual Core Mobile
+    ISCP_ProcessorFamilyAmdAthlonDualCore            = 0xEA,  ///< Processor Family - AMD Turion Dual Core Mobile
+    ISCP_ProcessorFamilyAmdSempronSI                 = 0xEB,  ///< Processor Family - AMD Sempron SI
+    ISCP_ProcessorFamilyAmdPhenomII                  = 0xEC,  ///< Processor Family - AMD Phenon II
+    ISCP_ProcessorFamilyAmdAthlonII                  = 0xED,  ///< Processor Family - AMD Athlon II
+    ISCP_ProcessorFamilySixCoreAmdOpteron            = 0xEE,  ///< Processor Family - AMD 6-Core Opteron
+    ISCP_ProcessorFamilyAmdSempronM                  = 0xEF,  ///< Processor Family - AMD Sempon M
+    ISCP_ProcessorFamilyi860                         = 0xFA,  ///< Processor Family - i860
+    ISCP_ProcessorFamilyi960                         = 0xFB,  ///< Processor Family - i960
+    ISCP_ProcessorFamilyIndicatorFamily2             = 0xFE,  ///< Processor Family - Indicator Family 2
+    ISCP_ProcessorFamilyReserved1                    = 0xFF   ///< Processor Family - Reserved
+  } ISCP_PROCESSOR_FAMILY_DATA;
+
+  /// Processor Information2 - Processor Family2.
+  typedef enum {
+    ISCP_ProcessorFamilySH3                   = 0x0104,  ///< ProcessorFamily - SH3
+    ISCP_ProcessorFamilySH4                   = 0x0105,  ///< ProcessorFamily - SH4
+    ISCP_ProcessorFamilyARM                   = 0x0118,  ///< ProcessorFamily - ARM
+    ISCP_ProcessorFamilyStrongARM             = 0x0119,  ///< ProcessorFamily - Strong ARM
+    ISCP_ProcessorFamily6x86                  = 0x012C,  ///< ProcessorFamily - x86
+    ISCP_ProcessorFamilyMediaGX               = 0x012D,  ///< ProcessorFamily - Media GX
+    ISCP_ProcessorFamilyMII                   = 0x012E,  ///< ProcessorFamily - MII
+    ISCP_ProcessorFamilyWinChip               = 0x0140,  ///< ProcessorFamily - WinChip
+    ISCP_ProcessorFamilyDSP                   = 0x015E,  ///< ProcessorFamily - DSP
+    ISCP_ProcessorFamilyVideoProcessor        = 0x01F4   ///< ProcessorFamily - Video Processor
+  } ISCP_PROCESSOR_FAMILY2_DATA;
+
+  /// Processor Information - Processor Upgrade.
+  typedef enum {
+    ISCP_ProcessorUpgradeOther         = 0x01,          ///< Processor Upgrade - Other
+    ISCP_ProcessorUpgradeUnknown       = 0x02,          ///< Processor Upgrade - Unknown
+    ISCP_ProcessorUpgradeDaughterBoard = 0x03,          ///< Processor Upgrade - Daughter Board
+    ISCP_ProcessorUpgradeZIFSocket     = 0x04,          ///< Processor Upgrade - ZIF Socket
+    ISCP_ProcessorUpgradePiggyBack     = 0x05,          ///< Processor Upgrade - Piggyback
+    ISCP_ProcessorUpgradeNone          = 0x06,          ///< Processor Upgrade - None
+    ISCP_ProcessorUpgradeLIFSocket     = 0x07,          ///< Processor Upgrade - LIF Socket
+    ISCP_ProcessorUpgradeSlot1         = 0x08,          ///< Processor Upgrade - Slot 1
+    ISCP_ProcessorUpgradeSlot2         = 0x09,          ///< Processor Upgrade - Slot 2
+    ISCP_ProcessorUpgrade370PinSocket  = 0x0A,          ///< Processor Upgrade - 370 Pin Socket
+    ISCP_ProcessorUpgradeSlotA         = 0x0B,          ///< Processor Upgrade - Slot A
+    ISCP_ProcessorUpgradeSlotM         = 0x0C,          ///< Processor Upgrade - Slot M
+    ISCP_ProcessorUpgradeSocket423     = 0x0D,          ///< Processor Upgrade - Socket 423
+    ISCP_ProcessorUpgradeSocketA       = 0x0E,          ///< Processor Upgrade - Socket A
+    ISCP_ProcessorUpgradeSocket478     = 0x0F,          ///< Processor Upgrade - Socket 478
+    ISCP_ProcessorUpgradeSocket754     = 0x10,          ///< Processor Upgrade - Socket 754
+    ISCP_ProcessorUpgradeSocket940     = 0x11,          ///< Processor Upgrade - Socket 940
+    ISCP_ProcessorUpgradeSocket939     = 0x12,          ///< Processor Upgrade - Socket 939
+    ISCP_ProcessorUpgradeSocketmPGA604 = 0x13,          ///< Processor Upgrade - PGA 604
+    ISCP_ProcessorUpgradeSocketLGA771  = 0x14,          ///< Processor Upgrade - LGA 771
+    ISCP_ProcessorUpgradeSocketLGA775  = 0x15,          ///< Processor Upgrade - LGA 775
+    ISCP_ProcessorUpgradeSocketS1      = 0x16,          ///< Processor Upgrade - S1
+    ISCP_ProcessorUpgradeAM2           = 0x17,          ///< Processor Upgrade - AM2
+    ISCP_ProcessorUpgradeF1207         = 0x18,          ///< Processor Upgrade - F1207
+    ISCP_ProcessorSocketLGA1366        = 0x19,          ///< Processor Upgrade - LGA 1366
+    ISCP_ProcessorUpgradeSocketG34     = 0x1A,          ///< Processor Upgrade - G34
+    ISCP_ProcessorUpgradeSocketAM3     = 0x1B,          ///< Processor Upgrade - AM3
+    ISCP_ProcessorUpgradeSocketC32     = 0x1C,          ///< Processor Upgrade - C32
+    ISCP_ProcessorUpgradeSocketLGA1156 = 0x1D,          ///< Processor Upgrade - LGA 1156
+    ISCP_ProcessorUpgradeSocketLGA1567 = 0x1E,          ///< Processor Upgrade - LGA 1567
+    ISCP_ProcessorUpgradeSocketPGA988A = 0x1F,          ///< Processor Upgrade - PGA 988A
+    ISCP_ProcessorUpgradeSocketBGA1288 = 0x20,          ///< Processor Upgrade - PGA 1288
+    ISCP_ProcessorUpgradeSocketrPGA988B = 0x21,         ///< Processor Upgrade - PGA 988B
+    ISCP_ProcessorUpgradeSocketBGA1023 = 0x22,          ///< Processor Upgrade - BGA 1023
+    ISCP_ProcessorUpgradeSocketBGA1224 = 0x23,          ///< Processor Upgrade - BGA 1224
+    ISCP_ProcessorUpgradeSocketLGA1155 = 0x24,          ///< Processor Upgrade - LGA 1155
+    ISCP_ProcessorUpgradeSocketLGA1356 = 0x25,          ///< Processor Upgrade - LGA 1356
+    ISCP_ProcessorUpgradeSocketLGA2011 = 0x26,          ///< Processor Upgrade - LGA 2011
+    ISCP_ProcessorUpgradeSocketFS1     = 0x27,          ///< Processor Upgrade - FS1
+    ISCP_ProcessorUpgradeSocketFS2     = 0x28,          ///< Processor Upgrade - FS2
+    ISCP_ProcessorUpgradeSocketFM1     = 0x29,          ///< Processor Upgrade - FM1
+    ISCP_ProcessorUpgradeSocketFM2     = 0x2A,          ///< Processor Upgrade - FM2
+    ISCP_ProcessorUpgradeSocketLGA2011_3 = 0x2B,        ///< Processor Upgrade - LGA 2011-3
+    ISCP_ProcessorUpgradeSocketLGA1356_3 = 0x2C         ///< Processor Upgrade - LGA 1356-3
+  } ISCP_PROCESSOR_UPGRADE;
+
+  /// CPU Information - Characteristics.
+  typedef struct {
+    UINT16  Reserved0                 :1;          ///< CPU Information - Reserved
+    UINT16  Unknown                   :1;          ///< CPU Information - Unknown
+    UINT16  Capable64Bit              :1;          ///< CPU Information - Capable 64-Bit
+    UINT16  MultiCore                 :1;          ///< CPU Information - Multi-core
+    UINT16  HardwareThread            :1;          ///< CPU Information - Hardware Thread
+    UINT16  ExecuteProtection         :1;          ///< CPU Information - Execute Protection
+    UINT16  EnhancedVirtualization    :1;          ///< CPU Information - Enhanced Virtualization
+    UINT16  PowerPerformanceControl   :1;          ///< CPU Information - Power Performance Control
+    UINT16  Reserved8_15              :8;          ///< CPU Information - Reserved
+  } ISCP_PROCESSOR_CHARACTERISTICS;
+
+  /// CPU Information - CPU Status.
+  typedef enum {
+    ISCP_CPU_STATUS_UNKNOWN = 0,                     ///< CPU Status - Unknown
+    ISCP_CPU_STATUS_ENABLED,                         ///< CPU Status - Enabled
+    ISCP_CPU_STATUS_DISABLED_BY_USER,                ///< CPU Status - Disabled by user
+    ISCP_CPU_STATUS_DISABLED_BY_BIOS,                ///< CPU Status - Disabled by BIOS
+    ISCP_CPU_STATUS_IDLE,                            ///< CPU Status - Idle
+    ISCP_CPU_STATUS_RESERVED_5,                      ///< CPU Status - Reserved
+    ISCP_CPU_STATUS_RESERVED_6,                      ///< CPU Status - Reserved
+    ISCP_CPU_STATUS_OTHER                            ///< CPU Status - Other
+  } ISCP_CPU_STATUS;
+
+
+  /// CPU Information - Status.
+  typedef struct {
+    UINT16  CpuStatus                 :3;            ///< CPU Status
+    UINT16  Reserved3_5               :3;            ///< Reserved Bits[5:3]
+    UINT16  CpuSocketPopulated        :1;            ///< CPU Socket Populated
+    UINT16  Reserved7_15              :9;            ///< Reserved Bits[15:9]
+  } PROCESSOR_STATUS;
+
+  /// Cache Information - Operation Mode.
+  typedef enum {
+    ISCP_CACHE_OPERATION_MODE_WRITE_THROUGH = 0,          ///< Cache Operation Mode Write Through
+    ISCP_CACHE_OPERATION_MODE_WRITE_BACK,                 ///< Cache Operation Mode Write Back
+    ISCP_CACHE_OPERATION_MODE_VARIES_WITH_MEMORY_ADDRESS, ///< Cache Operation Mode Varies with Memory Address
+    ISCP_CACHE_OPERATION_MODE_UNKNOWN,                    ///< Cache Operation Mode Unknown
+  } ISCP_CACHE_OPERATION_MODE;
+
+  /// Cache Information - Location.
+  typedef enum {
+    ISCP_CACHE_LOCATION_INTERNAL = 0,               ///< Cache Location Internal
+    ISCP_CACHE_LOCATION_EXTERNAL,                   ///< Cache Location External
+    ISCP_CACHE_LOCATION_RESERVED,                   ///< Cache Location Reserved
+    ISCP_CACHE_LOCATION_UNKNOWN,                    ///< Cache Location Unknown
+  } ISCP_CACHE_LOCATION;
+
+  /// Cache Information - Level.
+  typedef enum {
+    ISCP_CACHE_LEVEL_1 = 0,                         ///< Cache Level 1
+    ISCP_CACHE_LEVEL_2,                             ///< Cache Level 2
+    ISCP_CACHE_LEVEL_3,                             ///< Cache Level 3
+    ISCP_CACHE_LEVEL_4,                             ///< Cache Level 4
+  } ISCP_CACHE_LEVEL;
+
+  /// Cache Information - Configuration.
+  typedef struct {
+    UINT16  CacheLevel                :3;            ///< Cache Level
+    UINT16  CacheSocketd              :1;            ///< Cache Socket ID
+    UINT16  Reserved_4                :1;            ///< Cache Reserved
+    UINT16  Location                  :2;            ///< Cache Location
+    UINT16  EnabledDisabled           :1;            ///< Cache Enabled / Disabled
+    UINT16  OperationMode             :2;            ///< Operation Mode
+    UINT16  Reserved10_15             :6;            ///< Cache Reserved
+  } ISCP_CACHE_CONFIGURATION;
+
+  /// Cache Information - SRAM Type.
+  typedef struct {
+    UINT16  Other                :1;                 ///< SRAM Type - Other
+    UINT16  Unknown              :1;                 ///< SRAM Type - Unknown
+    UINT16  NonBurst             :1;                 ///< SRAM Type - NonBurst
+    UINT16  Burst                :1;                 ///< SRAM Type - Burst
+    UINT16  PipelineBurst        :1;                 ///< SRAM Type - Pipeline Burst
+    UINT16  Synchronous          :1;                 ///< SRAM Type - Synchronous
+    UINT16  Asynchronous         :1;                 ///< SRAM Type - Asynchronous
+    UINT16  Reserved7_15         :9;                 ///< SRAM Type - Reserved
+  } ISCP_CACHE_SRAM_TYPE;
+
+  /// Cache Information - Error Correction Type.
+  typedef enum {
+    ISCP_ECC_TYPE_OTHER = 1,                         ///< ECC Type - Other
+    ISCP_ECC_TYPE_UNKNOWN,                           ///< ECC Type - Unknown
+    ISCP_ECC_TYPE_NONE,                              ///< ECC Type - None
+    ISCP_ECC_TYPE_PARITY,                            ///< ECC Type - Parity
+    ISCP_ECC_TYPE_SINGLE_BIT,                        ///< ECC Type - Single-Bit
+    ISCP_ECC_TYPE_MULTI_BIT                          ///< ECC Type - Multi-Bit
+  } ISCP_CACHE_ECC_TYPE;
+
+  /// Cache Information - System Cache Type.
+  typedef enum {
+    ISCP_SYSTEM_CACHE_TYPE_OTHER  = 1,               ///< System Cache Type - Other
+    ISCP_SYSTEM_CACHE_TYPE_UNKNOWN,                  ///< System Cache Type - Unknown
+    ISCP_SYSTEM_CACHE_TYPE_INSTRUCTION,              ///< System Cache Type - Instruction
+    ISCP_SYSTEM_CACHE_TYPE_DATA,                     ///< System Cache Type - Data
+    ISCP_SYSTEM_CACHE_TYPE_UNIFIED                   ///< System Cache Type - Unified
+  } ISCP_SYSTEM_CACHE_TYPE;
+
+  /// Cache Information - Associativity.
+  typedef enum {
+    ISCP_CACHE_ASSOCIATIVITY_OTHER = 1,                 ///< Cache Associativity - Other
+    ISCP_CACHE_ASSOCIATIVITY_UNKNOWN,                   ///< Cache Associativity - Unknown
+    ISCP_CACHE_ASSOCIATIVITY_DIRECT_MAPPED,             ///< Cache Associativity - Direct Mapped
+    ISCP_CACHE_ASSOCIATIVITY_2_WAY_SET_ASSOCIATIVE,     ///< Cache Associativity - 2-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_4_WAY_SET_ASSOCIATIVE,     ///< Cache Associativity - 4-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_FULLY_ASSOCIATIVE,         ///< Cache Associativity - Fully Assciative
+    ISCP_CACHE_ASSOCIATIVITY_8_WAY_SET_ASSOCIATIVE,     ///< Cache Associativity - 8-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_16_WAY_SET_ASSOCIATIVE,    ///< Cache Associativity - 16-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_12_WAY_SET_ASSOCIATIVE,    ///< Cache Associativity - 12-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_24_WAY_SET_ASSOCIATIVE,    ///< Cache Associativity - 24-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_32_WAY_SET_ASSOCIATIVE,    ///< Cache Associativity - 32-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_48_WAY_SET_ASSOCIATIVE,    ///< Cache Associativity - 48-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_64_WAY_SET_ASSOCIATIVE,    ///< Cache Associativity - 64-way Set Assciative
+    ISCP_CACHE_ASSOCIATIVITY_20_WAY_SET_ASSOCIATIVE     ///< Cache Associativity - 20-way Set Assciative
+  } ISCP_CACHE_ASSOCIATIVITY;
+
+  /// DMI TYPE 4 - CPU Information
+  typedef struct {
+    UINT16                    T4ProcType;               ///< Processor Type
+    UINT16                    T4ProcFamily;             ///< Processor Family
+    ISCP_PROC_ID              T4ProcId;                 ///< Processor Id
+    UINT16                    T4Voltage;                ///< Processor Voltage
+    UINT16                    T4ExternalClock;          ///< Processor External Clock
+    UINT16                    T4MaxSpeed;               ///< Processor Maximum Speed
+    UINT16                    T4CurrentSpeed;           ///< Processor Current Speed
+    UINT16                    T4Status;                 ///< Processor Status
+    UINT16                    T4ProcUpgrade;            ///< Processor Upgrade
+    UINT16                    T4CoreCount;              ///< Processor Core Count
+    UINT16                    T4CoreEnabled;            ///< Processor Core Enabled
+    UINT16                    T4ThreadCount;            ///< Processor Thread Count
+    UINT16                    T4ProcCharacteristics;    ///< Processor Characteristics
+    UINT16                    T4ProcFamily2;            ///< Processor Family 2
+    UINT16                    T4CoreCount2;             ///< Processor Core Count 2
+    UINT16                    T4CoreEnabled2;           ///< Processor Core Enabled 2
+    UINT16                    T4ThreadCount2;           ///< Processor Thread Count 2
+    UINT8                     T4SerialNumber[8];        ///< Processor Serial Number
+  } ISCP_TYPE4_SMBIOS_INFO;
+
+  /// DMI Type 7 - Cache Information
+  typedef struct {
+    UINT16                    T7CacheCfg;               ///< Cache Configuration
+    UINT16                    T7MaxCacheSize;           ///< Maximum Cache Size
+    UINT16                    T7InstallSize;            ///< Cache Install Size
+    UINT16                    T7SupportedSramType;      ///< Supported SRAM Type
+    UINT16                    T7CurrentSramType;        ///< Current SRAM Type
+    UINT16                    T7CacheSpeed;             ///< Cache Speed in nanoseconds
+    UINT16                    T7ErrorCorrectionType;    ///< Cache Error Correction Type
+    UINT16                    T7SystemCacheType;        ///< System Cache Type
+    UINT16                    T7Associativity;          ///< Cache Associativity
+  } ISCP_TYPE7_SMBIOS_INFO;
+
+  #ifdef __cplusplus
+  }
+#endif
+
+
+#endif /* CPUISCP_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Iscp.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Iscp.h
new file mode 100644
index 0000000..30f8c65
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Iscp.h
@@ -0,0 +1,400 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * Iscp.h
+ *
+ * Contains common ISCP-related structures and defines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 338015 $ @e date: $Date: 2016-04-04 10:40:16 -0500 (Mon, 04 Apr 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+//        NOTE: This file shared between SCP and UEFI, make sure all     //
+//              changes are reflected in both copies.                    //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef ISCP_H_
+#define ISCP_H_
+
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+  #include "SocConfiguration.h"
+  #include "IscpConfig.h"
+  #include "CoreState.h"
+  #include "MemSetup.h"
+  #include "MemIscp.h"
+  #include "UartLineSettings.h"
+  #include "CpuIscp.h"
+  #include "NetworkAddress.h"
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// *** NOTE: This controls the size of a queue in SRAM. This is the
+// maximum number of elements that will fit, without changing the
+// overall SRAM layout.
+#define ISCP_ECC_EVENT_QUEUE_SIZE    8
+
+  /// Types of ECC errors
+  typedef enum _ECC_FAIL_TYPE {
+    ECC_FAIL_NO_ERROR = 0,            ///< ECC No Error
+    ECC_FAIL_CORRECTABLE,             ///< ECC Multiple Correctable Error
+    ECC_FAIL_CORRECTABLE_MULTIPLE,    ///< ECC Correctable Multiple Error
+    ECC_FAIL_UNCORRECTABLE,           ///< ECC Correctable Error
+    ECC_FAIL_UNCORRECTABLE_MULTIPLE,  ///< ECC Uncorrectable Multiple Error
+    ECC_FAIL_PARITY,                  ///< ECC Parity Error
+    ECC_FAIL_END                      ///< End of ECC Fail Types
+  } ECC_FAIL_TYPE;
+
+  /// ISCP ECC error events
+  typedef struct _ISCP_ECC_EVENT_DETAILS {
+    UINT64 Address;            ///< Address
+    UINT64 PhysicalAddress;    ///< DRAM Physical Address
+    UINT64 Data;               ///< Data
+    UINT32 Channel;            ///< DRAM Channel
+    UINT32 SourceId;           ///< Scource ID
+    UINT32 Syndrome;           ///< ECC Syndrome
+    UINT32 Type;               ///< Restricted to ECC_FAIL_TYPE values
+    UINT32 Module;             ///< DRAM Module
+    UINT32 Bank;               ///< DRAM Bank
+    UINT32 Row;                ///< DRAM Row
+    UINT32 Column;             ///< DRAM Column
+  } ISCP_ECC_EVENT_DETAILS;
+
+  /// ISCP Block Transfer Memory Buffer
+  typedef struct {
+    UINT64  BuffAddress;                      ///< 64-Bit Communication Buffer Address
+    UINT64  BufferSize;                       ///< 64-Bit Communication Buffer Size
+  } BLOCK_TRANSFER_BUFFER;
+
+  /// ISCP Data Window
+  typedef struct {
+    union {
+      UINT8   szData[248];                       ///< 8-bit ISCP data array
+      BLOCK_TRANSFER_BUFFER BlockTransferBuffer; ///< ISCP Memory block Transfer Buffer structure
+    } Data;
+  } DATA_WINDOW;
+
+  /// ISCP Communication Block. This structure must fit within the 4K SRAM area.
+  typedef struct {
+    UINT32  Signature;                        ///< Command Signature
+    UINT8   BlockLength;                      ///< Block Length of the entire message
+    UINT8   RequestCode;                      ///< Request Code - Operation Requested by the recipient
+    UINT8   ResponseCode;                     ///< Response Code - Response Code from recipient
+    UINT8   DataLength;                       ///< Data Length - Length in bytes of data
+                                              ///< being transmitted, zero if MEMORY_BUFFER is used
+    DATA_WINDOW   DataWin;                    ///< Data Window Union (This completes the 256 byte header)
+    UINT8   ExtraPayload[3072];               ///< Reserved for large payloads (A maximum of 3K)
+    ISCP_ECC_EVENT_DETAILS FatalEccEvent;     ///< Only one fatal ECC error event needed (56 bytes)
+    ISCP_ECC_EVENT_DETAILS EccEventList[ISCP_ECC_EVENT_QUEUE_SIZE];   ///< List of ECC error events (448 bytes, which nearly finishes the 4K area)
+    UINT8   HeadIndex;                        ///< Index of first ECC event, when head == tail queue is empty
+    UINT8   TailIndex;                        ///< Index of empty queue entry, to be filled next.
+    UINT8   Overflow;                         ///< Indicates a queue overflow, saturates at 0xFF
+  } ISCP_COMM_BLOCK __attribute__ ((__aligned__ (64)));
+
+  /// Memory info HOB structure
+  typedef struct {
+    UINT32  Version;                          ///< Version of HOB structure
+    UINT32  NumberOfDescriptor;               ///< Number of memory range descriptor
+    AMD_MEMORY_RANGE_DESCRIPTOR  Ranges;      ///< Memory ranges
+  } ISCP_MEMORY_INFO;
+
+  /// SMBIOS Memory Buffer structure
+  typedef struct {
+    ISCP_TYPE16_SMBIOS_INFO      T16;         ///< SMBIOS Type 16 Record Data
+    ISCP_TYPE17_SMBIOS_INFO      T17[2][2];   ///< SMBIOS Type 17 Record Data
+    ISCP_TYPE19_SMBIOS_INFO      T19;         ///< SMBIOS Type 19 Record Data
+  } AMD_SMBIOS_MEM_BUFFER;
+
+  /// SMBIOS CPU Buffer structure
+  typedef struct {
+    ISCP_TYPE4_SMBIOS_INFO       T4[1];       ///< SMBIOS Type 4 Record Data
+    ISCP_TYPE7_SMBIOS_INFO       T7L1[1];     ///< SMBIOS Type 7 Level 1 Cache Record Data
+    ISCP_TYPE7_SMBIOS_INFO       T7L2[1];     ///< SMBIOS Type 7 Level 2 Cache Record Data
+    ISCP_TYPE7_SMBIOS_INFO       T7L3[1];     ///< SMBIOS Type 7 Level 3 Cache Record Data
+  } AMD_SMBIOS_CPU_BUFFER;
+
+  /// SMBIOS Buffer structure
+  typedef struct {
+    AMD_SMBIOS_MEM_BUFFER        SmbiosMemBuffer;  ///< SMBIOS Memory Buffer
+    AMD_SMBIOS_CPU_BUFFER        SmbiosCpuBuffer;  ///< SMBIOS CPU Buffer
+  } ISCP_SMBIOS_INFO;
+
+  /// NV Data structure
+  typedef struct {
+    UINT32  Version;                          ///< Version of NV data structure
+    UINT32  FvOffset;                         ///< Offset from the base of the UEFI image
+    UINT32  FvSize;                           ///< Firmware Volume Data Size to be written, read, or erased
+    UINT8   FvData[64*1024];                  ///< Firmware Volume Data block
+  } ISCP_OEM_NV_INFO;
+
+  /// Firmware Fuse Buffer structure
+  typedef struct {
+    UINT32              Version;              ///< Version of Fuse Info Buffer structure
+    SocConfiguration    SocConfiguration;     ///< Fuse Structure to be passed to UEFI
+  } ISCP_FUSE_INFO;
+
+  /// Firmware CPU Reset Buffer structure
+  typedef struct {
+    UINT32            Version;                ///< Version of CPU reset Buffer structure
+    UINT32            CoreNum;                ///< The core number we want data for, e.g. 0,1,2,..
+    SocCoreStatus     CoreStatus;             ///< Core Status Structure
+  } ISCP_CPU_RESET_INFO;
+
+  /// Firmware MAC Address structure
+  typedef struct {
+    UINT32    Version;                        ///< Version of MAC address Info Buffer structure
+    UINT8     MacAddress0[6];                 ///< MAC Address 0 10Gb Ethernet port 0
+    UINT8     MacAddress1[6];                 ///< MAC Address 1 10Gb Ethernet port 1
+    UINT8     MacAddress2[6];                 ///< MAC Address 2 1Gb Ethernet
+  } ISCP_MAC_INFO;
+
+  /// ISCP RTC Time structure (Based on subset of EFI_TIME structure)
+  typedef struct {
+    UINT32      Version;                      ///< Version of RTC Info Buffer structure
+    UINT16      Year;                         ///< Year: 2000 - 20XX
+    UINT8       Month;                        ///< Month:  1 - 12
+    UINT8       Day;                          ///< Day:  1 - 31
+    UINT8       Hour;                         ///< Hour: 0 - 23
+    UINT8       Minute;                       ///< Minute: 0 - 59
+    UINT8       Second;                       ///< Second: 0 - 59
+    UINT8       Pad;                          ///< Padding to made structure 32-bit aligned
+  } ISCP_RTC_INFO;
+
+  /// ISCP PCIE Reset structure
+  typedef struct {
+    UINT32      Version;                      ///< Version of PCIE reset Buffer structure
+    UINT8       ResetSeq;                     ///< Sequence of Reset
+    UINT16      SVID;                         ///< VRM value / Voltage
+  } ISCP_PCIE_RESET_INFO;
+
+  /// ISCP Ready To Boot structure
+  typedef struct {
+    UINT32         Version;                   ///< Version of Ready To Boot
+    UINT8          ReadyToBoot;               ///< Signal Ready To Boot Event
+  } ISCP_READY_TO_BOOT_INFO;
+
+  /// ISCP BMC IP Address structure
+  typedef struct {
+    UINT32         Version;                   ///< Version of BMC IP Address
+    ISCP_BMC_IPV4_ADDRESS  Ipv4Address;       ///< BMC IPv4 Address Structure
+    ISCP_BMC_IPV6_ADDRESS  Ipv6Address;       ///< BMC IPv6 Address Structure
+  } ISCP_BMC_IP_ADDRESS_INFO;
+
+  /// EEPROM info structure
+  typedef struct {
+    UINT32  Version;                          ///< Version of EEPROM Info structure
+    UINT32  EepromOffset;                     ///< EEPROM Offset from the base of the UEFI image
+    UINT32  EepromSize;                       ///< EEPROM Data Size to be written, read, or erased
+    UINT32  EepromArea;                       ///< EEPROM Area to be affected by read, write,erase commands
+    UINT8   EepromData[64*1024];              ///< EEPROm Data block [64K]
+  } ISCP_EEPROM_INFO;
+
+  /// UART info structure. The legal values for these fields are in UartLineSettings.h and are
+  /// shared between the SCP and UEFI.
+  typedef struct {
+    UINT32  Version;                          ///< Version of UART Info structure
+    UART_LINE_SETTINGS  A57UartConfig;        ///< A57 UART Config
+  } ISCP_UART_INFO;
+
+  /// Override Command structure
+  typedef struct {
+    UINT32         Version;                   ///< Version of Override Command structure
+    UINT8          Command;                   ///< Override command
+  } ISCP_OVERRIDE_CMD_INFO;
+
+  /// SATA1 reset structure
+  typedef struct {
+    UINT32         Version;                   ///< Version of SATA en/disable structure
+    UINT8          State;                     ///< Enable/Disable state
+  } ISCP_SATA1_RESET_INFO;
+
+  /// BMC presence structure
+  typedef struct {
+    UINT32         Version;                   ///< Version of BMC presence structure
+    UINT8          BmcPresent;                ///< BMC presence
+  } ISCP_BMC_PRESENCE_INFO;
+
+  /// BERT Region structure
+  typedef struct {
+    UINT32 IscpVersion;                       ///< Version of BERT Region structure
+    UINT64 RegionPhysAddr;                    ///< ACPI v6.0: Table 18-319 [Boot Error Region]
+    UINT32 RegionLength;                      ///< ACPI v6.0: Table 18-319 [Boot Error Region Length]
+  } ISCP_BERT_REGION_INFO;
+
+  /// SCP Doorbell Record structure
+  typedef struct {
+        UINT32 IscpVersion;                       ///< Version of Doorbell Info structure
+        UINT32 ToggleRateMilliSec;                ///< Doorbell Toggle Rate
+  } ISCP_SCP_DOORBELL_INFO;
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define ISCP_TIMEOUT                (1000000)
+
+// Request Codes
+#define ISCP_TRANSACTION_SUCCESS    (0x00)
+
+#define ISCP_REQ_MEMORY             (0x03)
+#define ISCP_RETRIEVE_SETUP         (0x04)
+#define ISCP_STORE_SETUP            (0x05)
+#define ISCP_FUSE_BLOB              (0x07)
+#define ISCP_CPU_RETRIEVE_ID        (0x09)
+#define ISCP_CPU_RESET              (0x0A)
+#define ISCP_REQ_OEM_NV             (0x0B)
+#define ISCP_STORE_OEM_NV           (0x0C)
+#define ISCP_ERASE_OEM_NV           (0x0D)
+#define ISCP_GET_MAC_ADDRESS        (0x0E)
+#define ISCP_SET_MAC_ADDRESS        (0x0F)
+#define ISCP_REQ_RTC                (0x10)
+#define ISCP_SET_RTC                (0x11)
+#define ISCP_GET_SMBIOS             (0x12)
+#define ISCP_RESET_PCIE             (0x13)
+#define ISCP_READY_TO_BOOT          (0x14)
+#define ISCP_GET_BMC_IP             (0x15)
+#define ISCP_RETRIEVE_VERSION       (0x16)
+#define ISCP_STORE_EEPROM           (0x17)
+#define ISCP_REQ_EEPROM             (0x18)
+#define ISCP_ERASE_EEPROM           (0x19)
+#define ISCP_MEM_SETUP              (0x1A)
+#define ISCP_SEND_UART_CONFIG       (0x1C)
+#define ISCP_OVERRIDE_CMD           (0x1D)
+#define ISCP_SATA1_GET              (0x1E)
+#define ISCP_SATA1_SET              (0x1F)
+#define ISCP_BMC_PRESENT            (0x20)
+#define ISCP_RETRIEVE_BERT_RECORD   (0x21)
+#define ISCP_SUBMIT_BERT_RECORD     (0x22)
+#define ISCP_POWER_OFF              (0xAA)
+#define ISCP_SYSTEM_RESET           (0xBB)
+
+// Response Codes
+#define ISCP_TRANSACTION_SUCCESS    (0x00)
+#define ISCP_UNSUCCESSFUL           (0x01)
+#define ISCP_INVALID                (0x02)
+#define ISCP_SIGNATURE_NOT_FOUND    (0x03)
+#define ISCP_NOT_SUPPORTED          (0x04)
+#define ISCP_INVALID_BLOCK_LENGTH   (0x05)
+#define ISCP_INVALID_REQUEST_CODE   (0x06)
+#define ISCP_INVALID_DATA_LENGTH    (0x07)
+#define ISCP_NV_WRITE_FAIL          (0x0A)
+#define ISCP_NV_READ_FAIL           (0x0B)
+#define ISCP_NV_ERASE_FAIL          (0x0C)
+#define ISCP_SETUP_READ_FAIL        (0x0D)
+#define ISCP_SETUP_WRITE_FAIL       (0x0E)
+#define ISCP_EE_WRITE_FAIL          (0x0F)
+#define ISCP_EE_READ_FAIL           (0x10)
+#define ISCP_EE_ERASE_FAIL          (0x11)
+#define ISCP_SMBIOS_FAIL            (0x12)
+#define ISCP_INVALID_RESPONSE_CODE  (0xFF)
+
+// ISCP Signatures
+#define BOOT_CORE_SIG               (0x524F4342)   //"BCOR" spelled backwards - Boot Core
+#define BERT_SIG                    (0x54524542)   //"BERT" spelled backwards - BERT Error Block Buffer Address
+#define BMC_PRESENT_SIG             (0x50434D42)   //"BMCP" spelled backwards - BMC Present
+#define BMC_IP_ADDR_SIG             (0x50494D42)   //"BMIP" spelled backwards - BMC IP Address
+#define CPU_MP_SIG                  (0x4D555043)   //"CPUM" spelled backwards - CPU Reset
+#define DOORBELL_SIG                (0x4C454244)   //"DBEL" spelled backwards - Doorbell
+#define EEPROM_SIG                  (0x52504545)   //"EEPR" spelled backwards - EEPROM
+#define FUSE_BLOB_SIG               (0x45535546)   //"FUSE" spelled backwards - Fuse blob
+#define HOBS_SIG                    (0x53424F48)   //"HOBS" spelled backwards - Memory HOBs buffer
+#define GET_MAC_ADDR_SIG            (0x4143414D)   //"MACA" spelled backwards - Get MAC Address
+#define OEM_NV_SIG                  (0x564E454F)   //"OENV" spelled backwards - OEM NV Storage save and retrieval actions
+#define OVERRIDE_CMD_SIG            (0x4452564F)   //"OVRD" spelled backwards - Override Command
+#define PCIE_SIG                    (0x45494350)   //"PCIE" spelled backwards - PCIE Reset
+#define READY2BOOT_SIG              (0x54425452)   //"RTBT" spelled backwards - Ready-To-Boot
+#define RTC_SIG                     (0x4B435452)   //"RTCK" spelled backwards - Real-Time-Clock
+#define SATA1_GET_SIG               (0x47544153)   //"SATG" spelled backwards - SATA 1 get state
+#define SATA1_SET_SIG               (0x53544153)   //"SATS" spelled backwards - SATA 1 set state
+#define SETUP_SIG                   (0x55544553)   //"SETU" spelled backwards - BIOS Setup
+#define SHUTDOWN_SIG                (0x4E444853)   //"SHDN" spelled backwards - System Shutdown
+#define SET_MAC_ADDR_SIG            (0x43414D53)   //"SMAC" spelled backwards - Set MAC Address
+#define SMBIOS_SIG                  (0x534D4253)   //"SMBS" spelled backwards - SMBIOS
+#define UART_SIG                    (0x54524155)   //"UART" spelled backwards - UART Config
+
+
+#define ISCP_BERT_REGION_INFO_VERSION               (0x00000001ul)    ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_BMC_PRESENT_INFO_VERSION               (0x00000001ul)    ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_BMC_IP_ADDR_INFO_VERSION               (0x00000001ul)    ///< Ver: 00.00.00.01
+#define ISCP_CPU_RESET_INFO_VERSION                 (0x00000001ul)    ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_DOORBELL_INFO_VERSION                  (0x00000001ul)    ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_EEPROM_VERSION                         (0x00000001ul)    ///< Ver: 00.00.00.01
+#define ISCP_FUSE_INFO_VERSION                      (0x00000001ul)    ///< Ver: 00.00.00.01
+#define ISCP_MEMORY_INFO_VERSION                    (0x00000001ul)    ///< Ver: 00.00.00.01
+#define ISCP_MAC_INFO_VERSION                       (0x00000002ul)    ///< Ver: 00.00.00.02
+#define ISCP_OEM_NV_VERSION                         (0x00000001ul)    ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_OVERRIDE_CMD_INFO_VERSION              (0x00000001ul)    ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_PCIE_RESET_INFO_VERSION                (0x00000001ul)    ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_READY2BOOT_INFO_VERSION                (0x00000001ul)    ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_RTC_INFO_VERSION                       (0x00000001ul)    ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_SATA1_RESET_INFO_VERSION               (0x00000001ul)    ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_UART_CONFIG_INFO_VERSION               (0x00000001ul)    ///< Ver: 00.00.00.01
+
+#define ISCP_COMM_BLK_MAX_SIZE                      (0x100)           ///< Max length of ISCP communication block, 256 bytes
+#define MAX_NUMBER_OF_EXTENDED_MEMORY_DESCRIPTOR    (2)
+#define MAX_SIZEOF_AMD_MEMORY_INFO_HOB_BUFFER       (sizeof (ISCP_MEM_HOB) +  \
+          (MAX_NUMBER_OF_EXTENDED_MEMORY_DESCRIPTOR * sizeof (AMD_MEMORY_RANGE_DESCRIPTOR)))
+#define MAX_SIZEOF_AMD_SETUP_BUFFER                 (sizeof (ISCP_SETUP_INFO))
+#define MAX_SIZEOF_AMD_SMBIOS_BUFFER                (sizeof (AMD_ISCP_SMBIOS_INFO))
+
+#define FOREVER                         for (;;)
+#define USE_DRAM_BUFFER                 (0x00)
+#define ISCP_BLOCK_LENGTH               (0x08)
+
+  #ifdef __cplusplus
+  }
+#endif
+
+#endif /* ISCP_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/IscpConfig.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/IscpConfig.h
new file mode 100644
index 0000000..cac451a
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/IscpConfig.h
@@ -0,0 +1,63 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * IscpConfig.h
+ *
+ * Contains Intra-SoC Communication Protocol configuration definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+#ifndef ISCP_CONFIG_H_
+#define ISCP_CONFIG_H_
+
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+  #include <ProcessorBind.h>  // Included just so this file can be built into both the RTOS
+                              // and UEFI without needing separate copies for both build
+                              // environments.
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Door Bell Flag Register
+#define ISCP_DRAM_BUFFER_ADDR_REG_LO    (0xE0000008UL)
+#define ISCP_DRAM_BUFFER_ADDR_REG_HI    (0xE000000CUL)
+#define ISCP_BUFFER_SIZE                (0x1000)
+#define DOORBELL_OFFSET_NS              (0x100)
+#define DOORBELL_BIT_NS                 (UINT32)              (1 << 7)    // Door Bell bit = [GPIO_1 (Line 14)]
+#define DOORBELL_BIT_SEC                (UINT32)              (1 << 7)    // Door Bell bit = [GPIO_1 (Line 15)]
+
+  #ifdef __cplusplus
+  }
+#endif
+
+
+#endif /* ISCP_CONFIG_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemIscp.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemIscp.h
new file mode 100644
index 0000000..68cd0ec
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemIscp.h
@@ -0,0 +1,174 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * MemIscp.h
+ *
+ * Contains common Memory Training ISCP-related structures and defines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+//        NOTE: This file shared between SCP and UEFI, make sure all     //
+//              changes are reflected in both copies.                    //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef MEMISCP_H_
+#define MEMISCP_H_
+
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+  /// Memory Attribute enum
+  typedef enum {
+    MEM_AVAILABLE = 1,                        ///< Memory Available
+    MEM_RESERVED,                             ///< Memory Reserved
+    MEM_ACPI,                                 ///< Memory ACPI
+    MEM_NVS,                                  ///< Memory NVS
+    MEM_UNUSABLE                              ///< Memory Unavailable
+  } MEMORY_ATTRIBUTE;
+
+  /// Memory descriptor structure for each memory range
+  typedef struct {
+    UINT64            Base0;                  ///< Base address of memory range 0
+    UINT64            Size0;                  ///< Size of memory range 0
+    MEMORY_ATTRIBUTE  Attribute0;             ///< Attribute of memory range 0
+    UINT32            Padding0;               ///< 4-byte Padding to get 8-byte alignment
+    UINT64            Base1;                  ///< Base address of memory range 1
+    UINT64            Size1;                  ///< Size of memory range 1
+    MEMORY_ATTRIBUTE  Attribute1;             ///< Attribute of memory range 1
+    UINT32            Padding1;               ///< 4-byte Padding to get 8-byte alignment
+    UINT64            Base2;                  ///< Base address of memory range 2
+    UINT64            Size2;                  ///< Size of memory range 2
+    MEMORY_ATTRIBUTE  Attribute2;             ///< Attribute of memory range 2
+    UINT32            Padding2;               ///< 4-byte Padding to get 8-byte alignment
+    UINT64            Base3;                  ///< Base address of memory range 3
+    UINT64            Size3;                  ///< Size of memory range 3
+    MEMORY_ATTRIBUTE  Attribute3;             ///< Attribute of memory range 3
+    UINT32            Padding3;               ///< 4-byte Padding to get 8-byte alignment
+  } AMD_MEMORY_RANGE_DESCRIPTOR;
+
+  /// SMBIOS Structure Header
+  typedef struct {
+    UINT8   Type;                             ///< TYPE
+    UINT8   Length;                           ///< Length of TYPE
+    UINT16  Handle;                           ///< structure handle, a unique 16-bit number in the range 0 to 0FEFFh
+  } ISCP_SMBIOS_STRUCTURE_HEADER;
+
+  /// DMI Type 16 - Physical Memory Array
+  typedef struct {
+    UINT16                    Location;               ///< The physical location of the Memory Array,
+                                                      ///< whether on the system board or an add-in board.
+    UINT16                    Use;                    ///< Identifies the function for which the array
+                                                      ///< is used.
+    UINT16                    MemoryErrorCorrection;  ///< The primary hardware error correction or
+                                                      ///< detection method supported by this memory array.
+                                                      ///< ..for memory devices in this array.
+    UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available..
+                                                      ///< ..for memory devices in this array.
+  } ISCP_TYPE16_SMBIOS_INFO;
+
+  /// DMI Type 17 offset 13h - Type Detail
+  typedef struct {
+    UINT16                    Reserved1:1;            ///< Reserved
+    UINT16                    Other:1;                ///< Other
+    UINT16                    Unknown:1;              ///< Unknown
+    UINT16                    FastPaged:1;            ///< Fast-Paged
+    UINT16                    StaticColumn:1;         ///< Static column
+    UINT16                    PseudoStatic:1;         ///< Pseudo-static
+    UINT16                    Rambus:1;               ///< RAMBUS
+    UINT16                    Synchronous:1;          ///< Synchronous
+    UINT16                    Cmos:1;                 ///< CMOS
+    UINT16                    Edo:1;                  ///< EDO
+    UINT16                    WindowDram:1;           ///< Window DRAM
+    UINT16                    CacheDram:1;            ///< Cache Dram
+    UINT16                    NonVolatile:1;          ///< Non-volatile
+    UINT16                    Registered:1;           ///< Registered (Buffered)
+    UINT16                    Unbuffered:1;           ///< Unbuffered (Unregistered)
+    UINT16                    Reserved2:1;            ///< Reserved
+  } SMBIOS_T17_TYPE_DETAIL;
+
+  /// DMI Type 17 - Memory Device
+  typedef struct {
+    UINT16                    Handle;                  ///< The temporary handle, or instance number, associated with the structure
+    UINT16                    TotalWidth;              ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+    UINT16                    DataWidth;               ///< Data Width, in bits, of this memory device.
+    UINT16                    MemorySize;              ///< The size of the memory device.
+    UINT16                    FormFactor;              ///< The implementation form factor for this memory device.
+    UINT16                    DeviceSet;               ///< Identifies when the Memory Device is one of a set of..
+                                                       ///< ..memory devices that must be populated with all devices of..
+                                                       ///< ..the same type and size, and the set to which this device belongs.
+    CHAR8                     DeviceLocator[8];        ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+    CHAR8                     BankLocator[16];         ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+    UINT16                    MemoryType;              ///< The type of memory used in this device.
+    SMBIOS_T17_TYPE_DETAIL    TypeDetail;              ///< Additional detail on the memory device type
+    UINT16                    Speed;                   ///< Identifies the speed of the device, in megahertz (MHz).
+    UINT8                     ManufacturerIdCode[8];   ///< Manufacturer ID code.
+    CHAR8                     SerialNumber[16];        ///< Serial Number.
+    CHAR8                     PartNumber[20];          ///< Part Number.
+    UINT16                    Attributes;              ///< Bits 7-4: Reserved, Bits 3-0: rank.
+    UINT32                    ExtSize;                 ///< Extended Size.
+    UINT16                    ConfigSpeed;             ///< Configured memory clock speed
+  } ISCP_TYPE17_SMBIOS_INFO;
+
+  /// DMI Type 19 - Memory Array Mapped Address
+  typedef struct {
+    UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
+                                                      ///< of a range of memory mapped to the
+                                                      ///< specified physical memory array.
+    UINT32                    EndingAddr;             ///< The physical ending address of the
+                                                      ///< last kilobyte of a range of addresses
+                                                      ///< mapped to the specified physical memory array.
+    UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
+                                                      ///< with the physical memory array to which this
+                                                      ///< address range is mapped.
+    UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
+                                                      ///< form a single row of memory for the address
+                                                      ///< partition defined by this structure.
+    UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                      ///< memory mapped to the specified Physical Memory Array.
+    UINT64                    ExtEndingAddr;          ///< The physical address, in bytes, of a range of
+                                                      ///< memory mapped to the specified Physical Memory Array.
+  } ISCP_TYPE19_SMBIOS_INFO;
+
+  #ifdef __cplusplus
+  }
+#endif
+
+
+#endif /* MEMISCP_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemSetup.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemSetup.h
new file mode 100644
index 0000000..ec7c3ce
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemSetup.h
@@ -0,0 +1,84 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * MemSetup.h
+ *
+ * Contains common MemSetup-related structures and defines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+//        NOTE: This file shared between SCP and UEFI, make sure all     //
+//              changes are reflected in both copies.                    //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef MEMSETUP_H_
+#define MEMSETUP_H_
+
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+  /// Memory Set up Structure for customer visibility
+  typedef struct {
+    UINT8  MemoryClockSpeed;                   ///< Memory clock speed
+    UINT8  DDR3RttWr;                          ///< DDR3 Rtt_Wr
+    UINT8  DDR3RttNom;                         ///< DDR3 Rtt_Nom
+    UINT8  DDR4RttWr;                          ///< DDR4 Rtt_Wr
+    UINT8  DDR4RttNom;                         ///< DDR4 Rtt_Nom
+    UINT8  AddCtrlDriveStrength;               ///< Address/Control Drive Strength
+    UINT8  ClockDriveStrengt;                  ///< Clock Drive Strength
+    UINT8  DataDMDriveStrength;                ///< Data/DM Drive Strength
+    UINT8  DQSDriveStrength;                   ///< DQS Drive Strength
+    UINT8  PowerdownEnable;                    ///< Power down Enable
+    UINT16 PowerdownIdleClocks;                ///< Power down Idle Clocks
+    UINT8  LongCountMask;                      ///< Long Count Mask
+    UINT8  ECCEnable;                          ///< ECC Enable/Disable
+    UINT16  tref;                              ///< tref
+    UINT16  tselseldq;                         ///< tsel_sel_dq
+    UINT16  tselseldqs;                        ///< tsel_sel_dqs
+    UINT16  trainingProgress;                  ///< training progress
+    UINT16  trainingRestore;                   ///< restore training results
+  } MEM_SETUP_VAR;
+
+  #ifdef __cplusplus
+  }
+#endif
+
+
+#endif /* MEMSETUP_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/NetworkAddress.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/NetworkAddress.h
new file mode 100644
index 0000000..9d1f77f
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/NetworkAddress.h
@@ -0,0 +1,55 @@
+/**
+ * @file
+ *
+ * Network Definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      STYX
+ * @e sub-project:  (TBD)
+ * @e \$Revision$        @e  \$Date$
+ *
+ **/
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+
+#ifndef __NETWORK_ADDRESS_H__
+#define __NETWORK_ADDRESS_H__
+
+/// Indicates the status of an IP address field within a structure
+  typedef enum {
+    DISABLED,                   ///< Disabled
+    ENABLED                     ///< Enabled
+  } IP_ADDRESS_STATUS;
+
+/// Structure for an IPv4 address
+  typedef struct {
+    UINT32      Status;         ///< Indicates if the address is valid
+    UINT8       IpAddress[4];   ///< IPv4 address data, if enabled (xxx.xxx.xxx.xxx)
+  } ISCP_BMC_IPV4_ADDRESS;
+
+/// Structure for an IPv6 address
+  typedef struct {
+    UINT32      Status;         ///< Indicates if the address is valid
+    UINT8       IpAddress[16];  ///< IPv6 address data, if enabled (xxxx:xxxx:xxxx:xxx:xxxx:xxxx:xxxx:xxxx)
+  } ISCP_BMC_IPV6_ADDRESS;
+
+/// Structure for any combination of an IPv4 and an IPv6 address
+  typedef struct {
+    ISCP_BMC_IPV4_ADDRESS       Ipv4Address;  ///< IPv4 Network Address Structure
+    ISCP_BMC_IPV6_ADDRESS       Ipv6Address;  ///< IPv6 Network Address Structure
+  } IP_ADDRESS_INFO;
+
+#endif /* __NETWORK_ADDRESS_H__ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/PostCode.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/PostCode.h
new file mode 100644
index 0000000..dabd58e
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/PostCode.h
@@ -0,0 +1,82 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * PostCode.h
+ *
+ * Contains Where's-The-Fimrware (WTF) POST code definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+#ifndef __POSTCODE__H_
+#define __POSTCODE__H_
+
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+// AMD UEFI WTF POST Codes
+#define POST_ENTER_SEC_CORE             0x200       ///< Enter SEC Phase Core
+#define POST_INIT_GIG_SEC               0x201       ///< Initialize GIC in Secure Mode
+#define POST_EXIT_SEC_CORE              0x202       ///< Exit SEC Phase Core
+#define POST_INIT_GIC_NON_SEC           0x203       ///< Initalize GIC in Non-Secure Mode
+#define POST_INIT_FV                    0x204       ///< Initialize Firmware Volume
+#define POST_RE_INIT_FV                 0x205       ///< Re-Initialize Firmware Volume
+#define POST_PROCESS_FV_FILE            0x206       ///< Process Firmware Volume File
+#define POST_PROCESS_FV_FILE_SECT       0x207       ///< Process Firmware Volume Sections
+#define POST_CSP_LIB_INIT_PEI           0x208       ///< Initialize CSP Library PEI Phase
+#define POST_BSP_CORE_MAIN_PRE_PEI      0x209       ///< BSP Core Main Pre-PEI
+#define POST_AP_CORE_MAIN_PRE_PEI       0x20A       ///< AP Core Main Pre-PEI
+#define POST_ENTER_PEI_CORE             0x20B       ///< Enter PEI Core
+#define POST_INIT_GIC_PEI               0x20C       ///< Initialize PEI GIC
+#define POST_UART_INIT                  0x20D       ///< Initialize UART
+#define POST_UART_INIT_PORT             0x20E       ///< Initiaize the UART port attributes
+#define POST_PEI_ISCP_INIT              0x20F       ///< Initialize PEI ISCP
+#define POST_EXIT_PEI_CORE              0x210       ///< Exit PEI Core
+#define POST_PRE_PI_MAIN                0x211       ///< Enter Pre-DXE Main
+#define POST_BSP_CORE_MAIN_PRE_PI       0x212       ///< Enter BSP Pre-DXE Core
+#define POST_AP_CORE_MAIN_PRE_PI        0x213       ///< Enter AP Core Main Pre-DXE
+#define POST_DXE_MAIN_UEFI_DECOMP       0x214       ///< Decompress DXE
+#define POST_ENTER_DXE_CORE             0x215       ///< Enter DXE Core
+#define POST_DXE_CORE_MEM_ADD_SPACE     0x216       ///< Add Memory Space in DXE Core
+#define POST_DXE_CORE_MEM_FREE_SPACE    0x217       ///< Free Memory Space in DXE Core
+#define POST_INIT_GIC_DXE               0x218       ///< Initialize GIC in DXE phase
+#define POST_INIT_ISCP_DXE              0x219       ///< Initialize ISCP DXE
+#define POST_EXIT_DXE_CORE              0x21A       ///< Exit DXE Core
+#define POST_EXIT_BOOT_SERV             0x21B       ///< Exit Boot Services
+#define POST_FINAL                      0x3FF       ///< Final POST code
+
+
+// AMD UEFI WTF Error Codes
+#define ERROR_ISCP_TIMEOUT              0x250       ///< ISCP Timeout (no response from SCP)
+#define ERROR_PXE_DHCP_FAIL             0x251       ///< PXE DHCP Fail
+#define ERROR_PXE_DHCP_PASS             0x252       ///< PXE DHCP Pass
+#define ERROR_PCIE_TRAIN_ERROR          0x261       ///< GIONB PCIE training error
+#define ERROR_PCIE_SPEED_ERROR          0x262       ///< GIONB PCIE data rate error
+#define ERROR_PCIE_PLL_ERROR            0x263       ///< GIONB PCIE PLL error
+#define ERROR_NO_HDD_DETECTED           0x2CF       ///< No HDD Detected from SATA ports
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+  #ifdef __cplusplus
+  }
+#endif
+#endif
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/SocConfiguration.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/SocConfiguration.h
new file mode 100644
index 0000000..4ca9785
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/SocConfiguration.h
@@ -0,0 +1,100 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * SocConfiguration.h
+ *
+ * Contains SoC Fuse Data structure definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+//        NOTE: This file shared between SCP and UEFI, make sure all     //
+//              changes are reflected in both copies.                    //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef __SOC_CONFIGURATION_H_
+#define __SOC_CONFIGURATION_H_
+
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+  #include "ProcessorBind.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define SOC_BRAND_NAME_SIZE     (48)
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+  /// SOC Security Modes Enumeration
+  typedef enum {
+    SOC_SECURITY_MODE_BLANK     = 0,        ///< Security Mode Blank
+    SOC_SECURITY_MODE_NOT_SECURE,           ///< Security Mode Non-secure
+    SOC_SECURITY_MODE_SECURE,               ///< Security Mode Secure
+    SOC_SECURITY_MODE_UNDEFINED,            ///< Security Mode Undefined
+  } SOC_SECURITY_MODES;
+
+  /// SOC Configuration, i.e. fusing structure
+  typedef struct {
+    UINT64   SerialNumber;                   ///< SOC Serial Number
+    SOC_SECURITY_MODES  SecurityState;       ///< Indicates what security mode the SOC is in.
+    INT32    CpuMap;                         ///< Map of CPU cores in SOC.
+    INT32    CpuDefaultAClock;               ///< Default fused core frequency
+    INT32    CpuClusterCount;                ///< Number of CPU clusters in SOC.
+    INT32    CpuCoreCount;                   ///< Number of CPU cores in SOC.
+    INT32    CpuClusterBoot;                 ///< Primary cluster used for boot.
+    INT32    CpuCoreBoot;                    ///< Primary core used for boot.
+    INT32    CcpEnabled;                     ///< Indicates CCP enabled state.  Zero if disabled; otherwise, enabled.
+    INT32    PcieEnabled;                    ///< Indicates PCIe enabled state.  Zero if disabled; otherwise, enabled.
+    INT32    SataEnabled;                    ///< Indicates SATA enabled state.  Zero if disabled; otherwise, enabled.
+    INT32    XgeEnabled;                     ///< Indicates 10 gigabit Ethernet port enabled state.  Zero if disabled; otherwise, enabled.
+    UINT32   BrandId;                        ///< Brand ID
+    UINT32   ConfigurationId;                ///< Configuration ID
+    UINT32   CpuIdModel;                     ///< CPU ID - Model
+    UINT32   CpuIdExtModel;                  ///< CPU ID - Extended Model
+    UINT32   CpuIdStepping;                  ///< CPU ID - Stepping
+    UINT32   FixedErrata;                    ///< Fixed Errata
+    UINT32   InternalRevision;               ///< Internal Revision
+    UINT32   ManufacturingSpecifiedId;       ///< Manufacturing Specified Field
+    CHAR8    BrandName[SOC_BRAND_NAME_SIZE]; ///< Null appended at end
+  } SocConfiguration;
+
+  #ifdef __cplusplus
+  }
+#endif
+
+#endif // __SOC_CONFIGURATION_H__
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/UartLineSettings.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/UartLineSettings.h
new file mode 100644
index 0000000..36df534
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/UartLineSettings.h
@@ -0,0 +1,97 @@
+/**
+ * @file
+ *
+ * Generic UART line setting values. These are shared between UEFI and the SCP.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      STYX
+ * @e sub-project:  (TBD)
+ * @e \$Revision$        @e  \$Date$
+ *
+ **/
+/*****************************************************************************
+ *
+ *  Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ *  This program and the accompanying materials are licensed and made available
+ *  under the terms and conditions of the BSD License which accompanies this
+ *  distribution. The full text of the license may be found at
+ *  http://opensource.org/licenses/bsd-license.php
+ *
+ *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ *  IMPLIED.
+ *
+ * ***************************************************************************
+ **/
+
+#ifndef _UART_LINE_SETTINGS_H_
+#define _UART_LINE_SETTINGS_H_
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+//        NOTE: This file shared between SCP and UEFI, make sure all     //
+//              changes are reflected in both copies.                    //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+
+/// UART Baudrate enum
+typedef enum {
+  /// This subset is defined/used in UEFI
+  UART_BAUDRATE_9600    = 9600,       ///< 9600 Baudrate
+  UART_BAUDRATE_19200   = 19200,      ///< 19200 Baudrate
+  UART_BAUDRATE_38400   = 38400,      ///< 38400 Baudrate
+  UART_BAUDRATE_57600   = 57600,      ///< 57600 Baudrate
+  UART_BAUDRATE_115200  = 115200,     ///< 115200 Baudrate
+
+  /// These could be used within the SCP.
+  UART_BAUDRATE_110     = 110,        ///< 110 Baudrate
+  UART_BAUDRATE_300     = 300,        ///< 300 Baudrate
+  UART_BAUDRATE_600     = 600,        ///< 600 Baudrate
+  UART_BAUDRATE_1200    = 1200,       ///< 1200 Baudrate
+  UART_BAUDRATE_2400    = 2400,       ///< 2400 Baudrate
+  UART_BAUDRATE_4800    = 4800,       ///< 4800 Baudrate
+  UART_BAUDRATE_14400   = 14400,      ///< 14400 Baudrate
+  UART_BAUDRATE_230400  = 230400,     ///< 230400 Baudrate
+  UART_BAUDRATE_460800  = 460800,     ///< 460800 Baudrate
+  UART_BAUDRATE_921600  = 921600,     ///< 921600 Baudrate
+} UART_BAUDRATE;
+
+/// UART Parity enum
+typedef enum {
+  DEFAULT_PARITY = 0,                 ///< Default Parity
+  NO_PARITY,                          ///< No Parity
+  EVEN_PARITY,                        ///< Even Parity
+  ODD_PARITY,                         ///< Odd Parity
+  MARK_PARITY,                        ///< Mark Parity
+  SPACE_PARITY                        ///< Space Parity
+} UART_PARITY;
+
+/// UART Stop Bit enum
+typedef enum {
+  UART_STOP_BIT_0 = 0,                 ///< No Stop Bits
+  UART_STOP_BIT_1,                     ///< One Stop Bit
+  UART_STOP_BIT_1_5,                   ///< One and One Half Stop bits
+  UART_STOP_BIT_2                      ///< Two Stop Bits
+} UART_STOP_BITS;
+
+/// UART Data Length enum
+typedef enum {
+  UART_DATA_BITS_5 = 5,                ///< Five Data Bits
+  UART_DATA_BITS_6,                    ///< Six Data Bits
+  UART_DATA_BITS_7,                    ///< Seven Data Bits
+  UART_DATA_BITS_8,                    ///< Eight Data Bits
+} UART_DATA_BITS;
+
+/// UART Line Settings structure
+typedef struct _UART_LINE_SETTINGS {
+  UART_BAUDRATE   BaudRate;            ///< UART Baudrate
+  UART_DATA_BITS  DataBits;            ///< UART Data Bits
+  UART_PARITY     Parity;              ///< UART Parity
+  UART_STOP_BITS  StopBits;            ///< UART Stop Bits
+} UART_LINE_SETTINGS;
+
+#endif /* _UART_LINE_SETTINGS_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Wtf_Reg.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Wtf_Reg.h
new file mode 100644
index 0000000..736edab
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Wtf_Reg.h
@@ -0,0 +1,133 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * Wtf_Reg.h
+ *
+ * Contains Where's-The-Firmware (WTF) definitions and Macros.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+#ifndef __WTF_REG__H_
+#define __WTF_REG__H_
+
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define WTF_STATUS_REG                  0xE0000000  // "Where's The Firmware" Register
+
+#define WTF_STATUS_REG_SIZE             32
+#define WTF_STATUS_ERROR_SIZE           12
+#define WTF_STATUS_POST_SIZE            10
+#define WTF_STATUS_FW_INDICATOR_SIZE    2
+#define WTF_STATUS_BT_CHKSUMFAIL_SIZE   1
+
+#define WTF_STATUS_ERROR_SHIFT          0
+#define WTF_STATUS_POST_SHIFT           12
+#define WTF_STATUS_FW_INDICATOR_SHIFT   22
+#define WTF_STATUS_BT_CHKSUMFAIL_SHIFT  31
+
+#define WTF_STATUS_ERROR_MASK           0x00000FFF
+#define WTF_STATUS_POST_MASK            0x003FF000
+#define WTF_STATUS_FW_INDICATOR_MASK    0x00C00000
+#define WTF_STATUS_BT_CHKSUMFAIL_MASK   0x80000000
+
+#define WTF_STATUS_MASK \
+        (WTF_STATUS_ERROR_MASK | \
+        WTF_STATUS_POST_MASK | \
+        WTF_STATUS_FW_INDICATOR_MASK | \
+        WTF_STATUS_BT_CHKSUMFAIL_MASK)
+
+#define WTF_STATUS_DEFAULT              0x00000000
+#define WTF_STATUS_FW_INDICATOR_UEFI    0x2
+
+#define WTF_STATUS_GET_ERROR(wtf_status) \
+        ((wtf_status & WTF_STATUS_ERROR_MASK) >> WTF_STATUS_ERROR_SHIFT)
+#define WTF_STATUS_GET_POST(wtf_status) \
+        ((wtf_status & WTF_STATUS_POST_MASK) >> WTF_STATUS_POST_SHIFT)
+#define WTF_STATUS_GET_FW_INDICATOR(wtf_status) \
+        ((wtf_status & WTF_STATUS_FW_INDICATOR_MASK) >> WTF_STATUS_FW_INDICATOR_SHIFT)
+#define WTF_STATUS_GET_BT_CHKSUMFAIL(wtf_status) \
+        ((wtf_status & WTF_STATUS_BT_CHECKSUMFAIL_MASK) >> WTF_STATUS_BT_CHECKSUMFAIL_SHIFT)
+
+#define WTF_STATUS_SET_ERROR(error) { \
+        UINT32 wtf_status_reg; \
+        wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
+        wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_ERROR_MASK) | (error << WTF_STATUS_ERROR_SHIFT); \
+        wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (WTF_STATUS_FW_INDICATOR_UEFI << WTF_STATUS_FW_INDICATOR_SHIFT); \
+        MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
+}
+
+#define WTF_STATUS_SET_POST(post) { \
+        UINT32 wtf_status_reg; \
+        wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
+        wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_POST_MASK) | (post << WTF_STATUS_POST_SHIFT); \
+        wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (WTF_STATUS_FW_INDICATOR_UEFI << WTF_STATUS_FW_INDICATOR_SHIFT); \
+        MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
+}
+
+#define WTF_STATUS_SET_FW_INDICATOR(fwindicator) { \
+        UINT32 wtf_status_reg; \
+        wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
+        wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (fwindicator << WTF_STATUS_FW_INDICATOR_SHIFT); \
+        MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
+}
+
+#define WTF_STATUS_SET_BT_CHKSUMFAIL(btchksmfail) { \
+        UINT32 wtf_status_reg; \
+        wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
+        wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_BT_CHKSUMFAIL_MASK) | (btchksmfail << WTF_STATUS_BT_CHKSUMFAIL_SHIFT); \
+        MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
+}
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// WTF Status Structure
+typedef
+struct _WTF_STATUS_T {
+  UINT64 error                   : WTF_STATUS_ERROR_SIZE;          ///< WTF Status Error Size
+  UINT64 post                    : WTF_STATUS_POST_SIZE;           ///< WTF Status Post Size
+  UINT64 fwindicator             : WTF_STATUS_FW_INDICATOR_SIZE;   ///< WTF Status Firmware Indicator Size
+  UINT64 reserved                : 7;                              ///< Reserved
+  UINT64 btchksmfail             : WTF_STATUS_BT_CHKSUMFAIL_SIZE;  ///< WTF Status Bit Checksum Fail Size
+} WTF_STATUS_T;
+
+/// WTF Status Union
+typedef
+union {
+  UINT32 val : 32;   ///< Value
+  WTF_STATUS_T f;    ///< WTF Status Structure
+} WTF_STATUS_U;
+
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.depex
new file mode 100644
index 0000000..81f1fd5
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.depex
@@ -0,0 +1 @@
+�,�ǱI�$�o�q;#
+\ No newline at end of file
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.efi
new file mode 100644
index 0000000..bbd2e1c
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.efi
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.inf
new file mode 100644
index 0000000..9b06cf6
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.inf
@@ -0,0 +1,51 @@
+#**
+# @file
+#
+# Gionb.inf
+#
+# AMD-specific Gionb module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 325775 $ @e date: $Date: 2015-08-31 17:45:22 -0500 (Mon, 31 Aug 2015) $
+#
+#
+#*****************************************************************************
+#
+#  Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+INF_VERSION = 0x00010015
+VERSION_STRING = 1.0
+BASE_NAME = Gionb
+MODULE_TYPE = PEIM
+FILE_GUID = 3D65D81A-6E60-436F-951A-C9878BF77390
+ENTRY_POINT = PeiInitGionb
+
+[Binaries.AARCH64]
+  PE32|Gionb.efi|*
+  PEI_DEPEX|Gionb.depex|*
+
+[Packages]
+  AmdModulePkg/AmdModulePkg.dec
+
+[PatchPcd]
+  gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2|0xa4d9
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1|0xa4c2
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1|0xa4ab
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1|0xa4d8
+  gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE|0xa4ac
+  gAmdModulePkgTokenSpaceGuid.PcdPcieGenMax|2|0xa4ad
+  gAmdModulePkgTokenSpaceGuid.PcdPcieGen3|0|0xa4c1
+  gAmdModulePkgTokenSpaceGuid.PcdPcieGen2|0|0xa4c0
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdNvLib.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdNvLib.h
new file mode 100644
index 0000000..20a234a
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdNvLib.h
@@ -0,0 +1,78 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * AmdNvLib.c
+ *
+ * Provides library calls for NV (SPI and EEPROM) access.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 306428 $ @e date: $Date: 2014-10-23 14:42:26 -0500 (Thu, 23 Oct 2014) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+#ifndef _AMD_NV_H_
+#define _AMD_NV_H_
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+  #pragma pack(1)
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define  EEPROM_PAGE_SIZE        0x2000        // 8K block size
+#define  EEPROM_ERASE_POLARITY   0x1           // Erase Polarity Positive (all bits ON)
+
+/*----------------------------------------------------------------------------------------
+ *                                 P R O T O T Y P E S
+ *----------------------------------------------------------------------------------------
+ */
+
+  VOID
+  AmdNvEepromRead (
+    volatile UINT8      *Address,
+    UINT8               *Data,
+    UINT32              *Size
+    );
+
+  VOID
+  AmdNvEepromWrite (
+    volatile UINT8      *Address,
+    UINT8               *Data,
+    UINT32              *Size
+    );
+
+  VOID
+  AmdNvEepromErase (
+    volatile UINT8      *Address,
+    UINT32              *Size
+    );
+
+  #pragma pack()
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+  #ifdef __cplusplus
+  }
+#endif
+#endif
+
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdSataInitLib.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdSataInitLib.h
new file mode 100644
index 0000000..a5a6039
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdSataInitLib.h
@@ -0,0 +1,150 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * AmdSataInitLib.h
+ *
+ * Public SATA PHY layer initilization and training routines for Serdes registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 338015 $ @e date: $Date: 2016-04-04 10:40:16 -0500 (Mon, 04 Apr 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+#ifndef _AMD_SATA_INIT_LIB_H_
+#define _AMD_SATA_INIT_LIB_H_
+#ifdef __cplusplus
+  extern "C" {
+  #endif
+
+  /**
+   *---------------------------------------------------------------------------------------
+   *
+   *  SataPhyInit
+   *
+   *  Description:
+   *    Library call that trains the SATA PHY.
+   *
+   *  Control flow:
+   *    1. Initialize variables
+   *    2. Continue to set Serdes bits while not locked
+   *
+   *  Parameters:
+   *    @param[in]      cmu_number           Cmu block number. Port 0,1 belongs to CMU 0
+   *    @param[in]      EvenPortGen           Port Gen value for even port in given CMU
+   *    @param[in]      OddPortGen            Port Gen Value for Odd Port in given CMU
+   *
+   *    @return         VOID
+   *
+   *------------------------------------------------------------------------------------
+   **/
+  VOID
+  EFIAPI
+  SataPhyInit (
+    IN       UINT32 cmu_number,
+    IN       UINT32 EvenPortGen,
+    IN       UINT32 OddPortGen
+    );
+
+  /**
+   *---------------------------------------------------------------------------------------
+   *
+   *  SetCwMinSata0
+   *
+   *  Description:
+   *
+   *  Parameters:
+   *    @param[in]      Portnum            Port number
+   *
+   *    @return         VOID
+   *
+   *------------------------------------------------------------------------------------
+   **/
+  VOID
+  EFIAPI
+  SetCwMinSata0 (
+    IN       UINT32 Portnum
+    );
+
+  /**
+   *---------------------------------------------------------------------------------------
+   *
+   *  SetCwMinSata1
+   *
+   *  Description:
+   *
+   *  Parameters:
+   *    @param[in]      Portnum            Port number
+   *
+   *    @return         VOID
+   *
+   *------------------------------------------------------------------------------------
+   **/
+  VOID
+  EFIAPI
+  SetCwMinSata1 (
+    IN       UINT32 Portnum
+    );
+
+  /**
+   *---------------------------------------------------------------------------------------
+   *
+   *  SetPrdSingleSata0
+   *
+   *  Description:
+   *
+   *  Parameters:
+   *    @param[in]      Portnum            Port number
+   *
+   *    @return         VOID
+   *
+   *------------------------------------------------------------------------------------
+   **/
+  VOID
+  EFIAPI
+  SetPrdSingleSata0 (
+    IN       UINT32 Portnum
+    );
+
+  /**
+  *---------------------------------------------------------------------------------------
+  *
+  *  SetPrdSingleSata1
+  *
+  *  Description:
+  *
+  *  Parameters:
+  *    @param[in]      Portnum            Port number
+  *
+  *    @return         VOID
+  *
+  *------------------------------------------------------------------------------------
+  **/
+  VOID
+  EFIAPI
+  SetPrdSingleSata1 (
+    IN       UINT32 Portnum
+    );
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+  #ifdef __cplusplus
+  }
+#endif
+#endif
+
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/GionbPpi.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/GionbPpi.h
new file mode 100644
index 0000000..85b088c
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/GionbPpi.h
@@ -0,0 +1,78 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * GionbPpi.h
+ *
+ * GioNb Protocol-Protocol Interface header file.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+
+#ifndef _PEI_GIONB_PPI_H_
+#define _PEI_GIONB_PPI_H_
+
+///
+/// Global ID for the PEI_GIONB_PPI.
+///
+#define PEI_GIONB_PPI_GUID \
+{ \
+  0x24b8ebcc, 0x3871, 0x4b39, { 0xaa, 0x1a, 0xf, 0x86, 0x7d, 0xbf, 0x97, 0xc6 } \
+}
+
+///
+/// Forward declaration for the PEI_CAPSULE_PPI.
+///
+typedef struct _EFI_PEI_GIONB_PPI EFI_PEI_GIONB_PPI;
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PEI_INIT_GIONB_REGISTERS
+ *
+ *  Description:
+ *    Initialize GIONB registers.
+ *
+ *  Parameters:
+ *    @param[in]  **PeiServices        Pointer to the PEI
+ *                                     Services Table.
+ *
+ *    @return     EFI_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_INIT_GIONB_REGISTERS)(
+  IN CONST  EFI_PEI_SERVICES   **PeiServices
+  );
+
+///
+/// This PPI provides several services in PEI to initialize and configure GIO NB registers.
+///
+struct _EFI_PEI_GIONB_PPI {
+  PEI_INIT_GIONB_REGISTERS       GioNbEarlyInit;
+};
+
+extern EFI_GUID gPeiGionbPpiGuid;
+
+#endif // #ifndef _PEI_GIONB_PPI_H_
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/IscpPpi.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/IscpPpi.h
new file mode 100644
index 0000000..ca59b11
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/IscpPpi.h
@@ -0,0 +1,219 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * IscpPpi.h
+ *
+ * Contains Intra-SoC Communication Protocol-Protocol Interface definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+
+#ifndef _PEI_ISCP_PPI_H_
+#define _PEI_ISCP_PPI_H_
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include <Iscp.h>
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define PEI_ISCP_PPI_GUID {\
+  0xca2c1ecd, 0xc702, 0x49b1, { 0xae, 0x24, 0x9b, 0x6f, 0xa8, 0x71, 0x3b, 0x23 } \
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct _EFI_PEI_ISCP_PPI EFI_PEI_ISCP_PPI;
+
+
+/// ISCP Memory Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_MEMORY_TRANSACTION)(
+  IN     CONST EFI_PEI_SERVICES             **PeiServices,        ///< Pointer to the PEI Services Table
+  IN OUT AMD_MEMORY_RANGE_DESCRIPTOR  *MemRangeDescriptor   ///< Pointer to Memory Range Descriptor
+  );
+
+
+/// ISCP Fuse Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_FUSE_TRANSACTION)(
+  IN CONST EFI_PEI_SERVICES     **PeiServices,  ///< Pointer to the PEI Services Table
+  IN OUT   ISCP_FUSE_INFO       *FuseInfo       ///< Pointer to the Fuse Info structure
+  );
+
+
+/// ISCP CPU Retrieve ID Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_CPU_RETRIEVE_ID_TRANSACTION)(
+  IN CONST  EFI_PEI_SERVICES     **PeiServices,    ///< Pointer to the PEI Services Table
+  IN OUT    ISCP_CPU_RESET_INFO  *CpuResetInfo     ///< Pointer to CPU Reset Info structure
+  );
+
+
+/// ISCP CPU Reset transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_CPU_RESET_TRANSACTION)(
+  IN CONST EFI_PEI_SERVICES     **PeiServices,    ///< Pointer to the PEI Services Table
+  IN OUT   ISCP_CPU_RESET_INFO  *CpuResetInfo     ///< Pointer to CPU Reset Info structure
+  );
+
+
+/// ISCP Get Real-Time-Clock Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_GET_RTC_TRANSACTION)(
+  IN CONST EFI_PEI_SERVICES           **PeiServices,   ///< Pointer to the PEI Services Table
+  IN OUT   ISCP_RTC_INFO              *RtcInfo         ///< Pointer to the Real-Time-Clock
+  );
+
+
+/// ISCP Set Real-Time-Clock Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_SET_RTC_TRANSACTION)(
+  IN CONST EFI_PEI_SERVICES           **PeiServices,  ///< Pointer to the PEI Services Table
+  IN OUT   ISCP_RTC_INFO              *RtcInfo        ///< Pointer to the Real-Time-Clock
+  );
+
+
+/// ISCP Get MAC Address Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_GET_MAC_ADDRESS_TRANSACTION)(
+  IN CONST EFI_PEI_SERVICES           **PeiServices,  ///< Pointer to the PEI Services Table
+  IN OUT   ISCP_MAC_INFO              *MacInfo        ///< Pointer to the MAC Address info
+  );
+
+
+/// ISCP Set MAC Address Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_SET_MAC_ADDRESS_TRANSACTION)(
+  IN CONST EFI_PEI_SERVICES           **PeiServices,  ///< Pointer to the PEI Services Table
+  IN OUT   ISCP_MAC_INFO              *MacInfo        ///< Pointer to the MAC Address info
+  );
+
+
+/// ISCP Update Firmware Volume Block Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_UPDATE_FV_BLOCK_TRANSACTION)(
+  IN CONST  EFI_PEI_SERVICES         **PeiServices,  ///< Pointer to the PEI Services Table
+  IN CONST  UINT32                   Offset,         ///< Offset from base of FV Block
+  IN OUT    UINT8                    *NvData,        ///< Pointer to the NV data being stored
+  IN CONST  UINT32                   NvSize          ///< Size of NV Data being stored
+  );
+
+
+/// SCP Load Firmware Volume Block Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_LOAD_FV_BLOCK_TRANSACTION)(
+  IN CONST  EFI_PEI_SERVICES         **PeiServices,   ///< Pointer to the PEI Services Table
+  IN CONST  UINT32                   Offset,          ///< Offset from base of FV Block
+  IN OUT    UINT8                    *NvData,         ///< Pointer to the NV data being stored
+  IN CONST  UINT32                   NvSize           ///< Size of NV Data being stored
+  );
+
+
+/// ISCP Erase Firmware Volume Block Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_ERASE_FV_BLOCK_TRANSACTION)(
+  IN CONST  EFI_PEI_SERVICES         **PeiServices,  ///< Pointer to the PEI Services Table
+  IN CONST  UINT32                   Offset,         ///< Offset from base of FV Block
+  IN CONST  UINT32                   NvSize          ///< Size of NV Data being stored
+  );
+
+
+/// ISCP PCIE Reset Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_PCIE_RESET_TRANSACTION)(
+  IN CONST  EFI_PEI_SERVICES          **PeiServices,  ///< Pointer to the PEI Services Table
+  IN OUT    ISCP_PCIE_RESET_INFO      *PcieResetInfo  ///< Pointer to PCIE Reset info structure
+  );
+
+
+/// ISCP Send UART Config Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_SEND_UART_CONFIG_TRANSACTION)(
+  IN CONST  EFI_PEI_SERVICES          **PeiServices,  ///< Pointer to the PEI Services Table
+  IN OUT    ISCP_UART_INFO            *UartInfo       ///< Pointer to UART Config info structure
+  );
+
+/// ISCP Sata1 get Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_SATA1_GET_TRANSACTION)(
+  IN CONST  EFI_PEI_SERVICES          **PeiServices,  ///< Pointer to the PEI Services Table
+  IN OUT    ISCP_SATA1_RESET_INFO     *Sata1ResetInfo ///< Pointer to SATA1 reset structure
+  );
+
+/// ISCP BMC Present
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_BMC_PRESENT_TRANSACTION)(
+  IN CONST  EFI_PEI_SERVICES          **PeiServices,   ///< Pointer to the PEI Services Table
+  OUT       ISCP_BMC_PRESENCE_INFO    *BmcPresenceInfo ///< Pointer to BMC presence structure
+  );
+
+/// This PPI provides several services in PEI to work with the underlying
+/// Intra-SOC Communication Protocol capabilities of the platform.  These
+/// services include the ability for PEI to send/receive Firmware Setup data,
+/// retrieve memory data, retrieve fuse data, perform CPU core reset, e.g launch,
+/// retrieve OEM NVRAM transactions.
+struct _EFI_PEI_ISCP_PPI {
+  PEI_ISCP_MEMORY_TRANSACTION           ExecuteMemoryTransaction;
+  PEI_ISCP_FUSE_TRANSACTION             ExecuteFuseTransaction;
+  PEI_ISCP_CPU_RETRIEVE_ID_TRANSACTION  ExecuteCpuRetrieveIdTransaction;
+  PEI_ISCP_CPU_RESET_TRANSACTION        ExecuteCpuResetTransaction;
+  PEI_ISCP_GET_RTC_TRANSACTION          ExecuteGetRtcTransaction;
+  PEI_ISCP_SET_RTC_TRANSACTION          ExecuteSetRtcTransaction;
+  PEI_ISCP_GET_MAC_ADDRESS_TRANSACTION  ExecuteGetMacAddressTransaction;
+  PEI_ISCP_SET_MAC_ADDRESS_TRANSACTION  ExecuteSetMacAddressTransaction;
+  PEI_ISCP_UPDATE_FV_BLOCK_TRANSACTION  ExecuteUpdateFvBlock;
+  PEI_ISCP_LOAD_FV_BLOCK_TRANSACTION    ExecuteLoadNvBlock;
+  PEI_ISCP_ERASE_FV_BLOCK_TRANSACTION   ExecuteEraseNvBlock;
+  PEI_ISCP_PCIE_RESET_TRANSACTION       ExecutePcieResetTransaction;
+  PEI_ISCP_SEND_UART_CONFIG_TRANSACTION ExecuteSendUartConfigTransaction;
+  PEI_ISCP_SATA1_GET_TRANSACTION        ExecuteSata1GetTransaction;
+  PEI_ISCP_BMC_PRESENT_TRANSACTION      ExecuteBmcPresentTransaction;
+};
+
+extern EFI_GUID gPeiIscpPpiGuid;
+
+#endif // #ifndef _PEI_ISCP_PPI_H_
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h
new file mode 100644
index 0000000..5daeb0c
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h
@@ -0,0 +1,309 @@
+/* $NoKeywords */
+/**
+ * @file
+ *
+ * AmdIscpDxeProtocol.h
+ *
+ * Contains Intra-SoC Communication DXE Protocol definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 337020 $ @e date: $Date: 2016-03-02 11:49:34 -0600 (Wed, 02 Mar 2016) $
+ *
+ */
+/*****************************************************************************
+*
+*  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+*  IMPLIED.
+*
+***************************************************************************/
+
+#ifndef __AMD_ISCP_DXE_PROTOCOL__H_
+#define __AMD_ISCP_DXE_PROTOCOL__H_
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include <Iscp.h>
+
+
+/*----------------------------------------------------------------------------------------
+ *                         G U I D    D E F I N I T I O N
+ *----------------------------------------------------------------------------------------
+ */
+#define AMD_ISCP_DXE_PROTOCOL_GUID {\
+  0x5c794c8, 0x6aef, 0x4450, 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 \
+}
+
+/*----------------------------------------------------------------------------------------
+ *                                  E X T E R N S
+ *----------------------------------------------------------------------------------------
+ */
+extern EFI_GUID gAmdIscpDxeProtocolGuid;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct _AMD_ISCP_DXE_PROTOCOL AMD_ISCP_DXE_PROTOCOL;
+
+  /// HEST Notification type
+  typedef enum {
+    HEST_NOTIFY_POLLED  = 0,                  ///< Polled
+    HEST_NOTIFY_GPIO    = 7,                  ///< GPIO-Signal
+  } HEST_NOTIFY_TYPE;
+
+  /// Trusted Firmware Generic Error Source structure
+  typedef struct {
+    UINT32 IscpVersion;                       ///< Version of BERT Region structure
+    UINT8  SourceGUID[16];                    ///< ACPI v6.0: Table 18-331 [Section Type]
+    UINT64 ErrorStatusPhysAddr;               ///< ACPI v6.0: Table 18-329 [Error Status Address]
+    UINT32 ErrorStatusLength;                 ///< ACPI v6.0: Table 18-329 [Error Status Block Length]
+    HEST_NOTIFY_TYPE NotificationType;        ///< ACPI v6.0: Table 18-332 [Type]
+  } ISCP_TFW_GENERIC_ERROR_SOURCE;
+
+/// CPU Core Reset Prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_CPU_CORE_RESET) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,          ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN OUT  ISCP_CPU_RESET_INFO             *CpuResetInfo   ///< Pointer to CPU Reset Info structure
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_CPU_RETRIEVE_ID) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,          ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN OUT  ISCP_CPU_RESET_INFO             *CpuResetInfo   ///< Pointer to CPU Reset Info structure
+  );
+
+/// ISCP call to get MAC Address
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_GET_MAC_ADDRESS) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,      ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN OUT  ISCP_MAC_INFO                   *MacInfo    ///< Pointer to the Firmware MAC Address structure
+  );
+
+
+/// ISCP call to set MAC Address
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SET_MAC_ADDRESS) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,      ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN OUT  ISCP_MAC_INFO                   *MacInfo    ///< Pointer to the Firmware MAC Address structure
+  );
+
+
+/// ISCP call to get Real-Time-Clock
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_GET_RTC) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,    ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN OUT  ISCP_RTC_INFO                   *RtcInfo  ///< Pointer to the Real-Time-Clock structure
+  );
+
+
+/// ISCP call to set Real-Time-Clock
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SET_RTC) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,    ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN OUT  ISCP_RTC_INFO                   *RtcInfo  ///< Pointer to the Real-Time-Clock structure
+  );
+
+
+/// Update Firmware Volume Block into SPI from local memory
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_UPDATE_FV_BLOCK_DXE) (
+  IN        AMD_ISCP_DXE_PROTOCOL       *This,    ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN CONST  UINT32                      Offset,   ///< Offset to base of Firmware Volume Block
+  IN OUT    UINT8                       *NvData,  ///< Pointer to data being stored in FV Block
+  IN CONST  UINT32                      NvSize    ///< Size of data being stored FV Block
+  );
+
+
+/// Load Firmware Volume Block from SPI into local memory
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_LOAD_FV_BLOCK_DXE) (
+  IN        AMD_ISCP_DXE_PROTOCOL       *This,    ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN CONST  UINT32                      Offset,   ///< Offset to base of Firmware Volume Block
+  IN OUT    UINT8                       *NvData,  ///< Pointer to data being stored in FV Block
+  IN CONST  UINT32                      NvSize    ///< Size of data being retrieved from FV Block
+  );
+
+
+/// Erase Firmware Volume Block Prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_ERASE_FV_BLOCK_DXE) (
+  IN        AMD_ISCP_DXE_PROTOCOL       *This,    ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN CONST  UINT32                      Offset,   ///< Offset to base of Firmware Volume Block
+  IN CONST  UINT32                      NvSize    ///< Size of data being erased
+  );
+
+
+/// Update EEPROM Block from local memory prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE) (
+  IN        AMD_ISCP_DXE_PROTOCOL       *This,    ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN CONST  UINT32                      Offset,   ///< Offset to base of EEPROM Block
+  IN OUT    UINT8                       *Data,    ///< Pointer to data being stored in EEPROM Block
+  IN CONST  UINT32                      Size      ///< Size of data being stored EEPROM Block
+  );
+
+
+/// Load EEPROM Block into local memory prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE) (
+  IN        AMD_ISCP_DXE_PROTOCOL       *This,    ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN CONST  UINT32                      Offset,   ///< Offset to base of EEPROM Block
+  IN OUT    UINT8                       *Data,    ///< Pointer to data being stored in EEPROM Block
+  IN CONST  UINT32                      Size      ///< Size of data being retrieved from EEPROM Block
+  );
+
+
+/// Erase EEPROM Block prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE) (
+  IN        AMD_ISCP_DXE_PROTOCOL       *This,    ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN CONST  UINT32                      Offset,   ///< Offset to base of EEPROM Block
+  IN CONST  UINT32                      Size      ///< Size of data being erased
+  );
+
+
+/// Issue ISCP Doorbell command
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_GET_BMC_IP_ADDRESS) (
+  IN      AMD_ISCP_DXE_PROTOCOL         *This,
+  IN OUT  ISCP_BMC_IP_ADDRESS_INFO      *BmcIpAddressInfo
+  );
+
+/// Issue ISCP command to retrieve SMBIOS info
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SMBIOS_INFO) (
+  IN       AMD_ISCP_DXE_PROTOCOL           *This,
+  IN OUT   ISCP_SMBIOS_INFO                *SmbiosInfo
+  );
+
+/// Issue ISCP command to issue SoC shutdown command
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SOC_SHUTDOWN) (
+  IN       AMD_ISCP_DXE_PROTOCOL           *This
+  );
+
+/// Issue ISCP command to issue SoC reset command
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SOC_RESET) (
+  IN       AMD_ISCP_DXE_PROTOCOL           *This
+  );
+
+/// ISCP call to set Memory Set up Nodes
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_MEM_SETUP) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,        ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN OUT  MEM_SETUP_VAR                   *SetupInfo    ///< Pointer to the Firmware MAC Address structure
+  );
+
+/// Issue Override Command
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_OVERRIDE_CMD) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,                ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN      ISCP_OVERRIDE_CMD_INFO          *OverrideCmdInfo      ///< Pointer to the Overrride Command structure
+  );
+
+/// Issue Sata1 get state
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SATA1_GET) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,                ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN OUT  ISCP_SATA1_RESET_INFO           *Sata1ResetInfo       ///< Pointer to the SATA1 reset structure
+  );
+
+/// Issue Sata1 set state
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SATA1_SET) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,                ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  IN      ISCP_SATA1_RESET_INFO           *Sata1ResetInfo       ///< Pointer to the SATA1 reset structure
+  );
+
+/// Issue BMC presence check
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_BMC_PRESENT) (
+  IN       AMD_ISCP_DXE_PROTOCOL          *This,             ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+  OUT      ISCP_BMC_PRESENCE_INFO         *BmcPresenceInfo   ///< Pointer to BMC presence structure
+  );
+
+/// Register Boot Error Region
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_RETRIEVE_BERT_RECORD) (
+  IN      AMD_ISCP_DXE_PROTOCOL           *This,
+  IN OUT  ISCP_BERT_REGION_INFO           *BertRegionInfo
+  );
+
+/// Register generic hardware error soure
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_REGISTER_ERROR_SOURCE) (
+  IN  AMD_ISCP_DXE_PROTOCOL               *This,
+  IN  ISCP_TFW_GENERIC_ERROR_SOURCE       *GenericErrorSource
+  );
+
+
+/*----------------------------------------------------------------------------------------
+ *                         P R O T O C O L    S T R U C T U R E
+ *----------------------------------------------------------------------------------------
+ */
+/// ISCP DXE Protocol Structure
+typedef
+struct _AMD_ISCP_DXE_PROTOCOL {
+  AMD_EXECUTE_CPU_CORE_RESET          AmdExecuteCpuCoreReset;         ///< Execute CPU Core Reset
+  AMD_EXECUTE_CPU_RETRIEVE_ID         AmdExecuteCpuRetrieveId;        ///< Execute CPU Retrieve ID
+  AMD_EXECUTE_GET_MAC_ADDRESS         AmdExecuteGetMacAddress;        ///< Execute Get MAC Address
+  AMD_EXECUTE_SET_MAC_ADDRESS         AmdExecuteSetMacAddress;        ///< Execute Set MAC Address
+  AMD_EXECUTE_GET_RTC                 AmdExecuteGetRtc;               ///< Execute Get Real-Time-Clock Time
+  AMD_EXECUTE_SET_RTC                 AmdExecuteSetRtc;               ///< Execute Set Real-Time-Clock Time
+  AMD_EXECUTE_UPDATE_FV_BLOCK_DXE     AmdExecuteUpdateFvBlockDxe;     ///< Execute Update FV Block Data on the SPI device
+  AMD_EXECUTE_LOAD_FV_BLOCK_DXE       AmdExecuteLoadFvBlockDxe;       ///< Execute Load FV Block Data from the SPI device
+  AMD_EXECUTE_ERASE_FV_BLOCK_DXE      AmdExecuteEraseFvBlockDxe;      ///< Execute Erase FV Block Data on the SPI device
+  AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE AmdExecuteUpdateEepromBlockDxe; ///< Execute Update EEPROM Data on the EEPROM device
+  AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE   AmdExecuteLoadEepromBlockDxe;   ///< Execute Load EEPROM Data on the EEPROM device
+  AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE  AmdExecuteEraseEepromBlockDxe;  ///< Execute Erase EEPROM Data on the EEPROM device
+  AMD_EXECUTE_GET_BMC_IP_ADDRESS      AmdExecuteGetBmcIpAddress;      ///< Execute Get BMC IP Address
+  AMD_EXECUTE_SMBIOS_INFO             AmdExecuteSmbiosInfoDxe;        ///< Execute SMBIOS info
+  AMD_EXECUTE_SOC_SHUTDOWN            AmdExecuteSocShutdownDxe;       ///< Execute SoC Shutdown
+  AMD_EXECUTE_SOC_RESET               AmdExecuteSocResetDxe;          ///< Execute SoC Reset
+  AMD_EXECUTE_MEM_SETUP               AmdExecuteMemSetup;             ///< Execute Set MAC Address
+  AMD_EXECUTE_OVERRIDE_CMD            AmdExecuteOverrideCmd;          ///< Execute Override Command
+  AMD_EXECUTE_SATA1_GET               AmdExecuteSata1Get;             ///< Execute Sata1 get state
+  AMD_EXECUTE_SATA1_SET               AmdExecuteSata1Set;             ///< Execute Sata1 set state
+  AMD_EXECUTE_BMC_PRESENT             AmdExecuteBmcPresent;           ///< Execute BMC presence check
+  AMD_EXECUTE_RETRIEVE_BERT_RECORD    AmdExecuteRetrieveBertRecord;   ///< Execute Retrieve Boot Error Record
+  AMD_EXECUTE_REGISTER_ERROR_SOURCE   AmdExecuteRegisterErrorSource;  ///< Execute Register Generic Hardware Error Source
+} AMD_ISCP_DXE_PROTOCOL;
+
+#endif //_AMD_ISCP_DXE_PROTOCOL_H_
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h
new file mode 100644
index 0000000..94f4f26
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h
@@ -0,0 +1,86 @@
+/* $NoKeywords: $ */
+/**
+ * @file
+ *
+ * AMD RAS APEI Protocol
+ *
+ * AMD Ras Interface Protocol GUID initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      FDK
+ * @e sub-project:  UEFI
+ * @e \$Revision: 281924 $   @e \$Date: 2014-01-02 13:57:19 -0600 (Thu, 02 Jan 2014) $
+ */
+/*****************************************************************************
+ *
+ *  Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ *  This program and the accompanying materials are licensed and made available
+ *  under the terms and conditions of the BSD License which accompanies this
+ *  distribution. The full text of the license may be found at
+ *  http://opensource.org/licenses/bsd-license.php
+ *
+ *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ *  IMPLIED.
+ *
+ ***************************************************************************/
+
+#ifndef _AMD_RAS_APEI_PROTOCOL_H_
+#define _AMD_RAS_APEI_PROTOCOL_H_
+
+#include "AmdApei.h"
+
+//
+// GUID definition
+//
+#define AMD_RAS_APEI_PROTOCOL_GUID \
+  { 0xe9dbcc60, 0x8f93, 0x47ed, 0x84, 0x78, 0x46, 0x78, 0xf1, 0x9f, 0x73, 0x4a }
+// {E9DBCC60-8F93-47ed-8478-4678F19F734A}
+
+extern EFI_GUID gAmdRasApeiProtocolGuid;
+
+// current PPI revision
+#define AMD_RAS_APEI_REV  0x01
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct _AMD_RAS_APEI_PROTOCOL AMD_RAS_APEI_PROTOCOL;
+
+/// APEI Interface data pointer
+typedef
+struct _AMD_APEI_INTERFACE {
+  APEI_DRIVER_PRIVATE_DATA  *ApeiPrivData;
+} AMD_APEI_INTERFACE;
+
+
+/// APEI add Boot error record
+typedef
+EFI_STATUS
+(EFIAPI *AMD_ADD_BOOT_ERROR_RECORD_ENTRY) (
+  IN    UINT8   *ErrorRecord,
+  IN    UINT32  RecordLen,
+  IN    UINT8   ErrorType,
+  IN    UINT8   SeverityType
+);
+
+/// APEI add HEST error source
+typedef
+EFI_STATUS
+(EFIAPI *ADD_HEST_ERROR_SOURCE_ENTRY) (
+  IN    UINT8   *pErrorRecord,
+  IN    UINT32  RecordLen
+);
+
+
+/// RAS APEI Protocol Structure
+typedef struct _AMD_RAS_APEI_PROTOCOL {
+  AMD_APEI_INTERFACE               *AmdApeiInterface;        /// APEI Interface
+  AMD_ADD_BOOT_ERROR_RECORD_ENTRY  AddBootErrorRecordEntry;  /// Boot error record to be added
+  ADD_HEST_ERROR_SOURCE_ENTRY      AddHestErrorSourceEntry;  /// HEST error source to be added
+} AMD_RAS_APEI_PROTOCOL;
+
+
+#endif //_AMD_RAS_APEI_PROTOCOL_H_
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.depex
new file mode 100644
index 0000000..0dc7ce4
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.depex
@@ -0,0 +1 @@
+��J&�>����4/4
+\ No newline at end of file
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.efi
new file mode 100644
index 0000000..3bfc2a8
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.efi
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.inf
new file mode 100644
index 0000000..4cb7bb2
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.inf
@@ -0,0 +1,47 @@
+# $NoKeywords */
+#
+# @file
+#
+# IscpDxe.inf
+#
+# AMD-specific DXE-Phase Intra-SoC Communication Protocol module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 323117 $ @e date: $Date: 2015-07-22 15:39:01 -0500 (Wed, 22 Jul 2015) $
+#
+#
+#*****************************************************************************
+#
+#  Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IscpDxe
+  FILE_GUID                      = 2FC9C0DD-1CB9-44E1-874F-C63B751F34B3
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = IscpInitEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+#
+
+[Binaries.AARCH64]
+  PE32|IscpDxe.efi|*
+  DXE_DEPEX|IscpDxe.depex|*
+
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.depex
new file mode 100644
index 0000000..53e435a
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.depex
@@ -0,0 +1 @@
+%M��M�#?�65?�#�
+\ No newline at end of file
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.efi
new file mode 100644
index 0000000..7e917fd
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.efi
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.inf
new file mode 100644
index 0000000..98fd81c
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.inf
@@ -0,0 +1,45 @@
+#**
+# @file
+#
+# IscpPei.inf
+#
+# AMD-specific PEI-Phase Intra-SoC Communication Protocol module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 321113 $ @e date: $Date: 2015-06-19 10:25:47 -0500 (Fri, 19 Jun 2015) $
+#
+#
+#*****************************************************************************
+#
+#  Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IscpPei
+  FILE_GUID                      = 4C4C6624-DDDA-4C49-B542-DAFF4CBF2F20
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = PeiInitIscp
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+#
+
+[Binaries.AARCH64]
+  PE32|IscpPei.efi|*
+  PEI_DEPEX|IscpPei.depex
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInit.lib b/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInit.lib
new file mode 100644
index 0000000..2ea410d
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInit.lib
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
new file mode 100644
index 0000000..97b7305
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
@@ -0,0 +1,49 @@
+# $NoKeywords */
+#
+# @file
+#
+# AmdSataInitLib.inf
+#
+# AMD-specific SATA Library Initialization information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 19:25:20 -0500 (Thu, 29 May 2014) $
+#
+#
+#*****************************************************************************
+#
+#  Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AmdSataInit
+  FILE_GUID                      = 15336efd-ab12-512E-cca1-2584695123a0
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = AmdSataInit
+
+[Binaries.AARCH64]
+  LIB|AmdSataInit.lib|*
+
+[Packages]
+  AmdModulePkg/AmdModulePkg.dec
+
+[FixedPcd]
+  gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen1
+  gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen2
+  gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen3
+  gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen1
+  gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen2
+  gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen3
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.depex
new file mode 100644
index 0000000..cb68e14
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.depex
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.efi
new file mode 100644
index 0000000..7575200
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.efi
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.inf
new file mode 100644
index 0000000..e45d360
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.inf
@@ -0,0 +1,48 @@
+# $NoKeywords */
+#
+# @file
+#
+# SnpDxePort0.inf
+#
+# Ethernet port 0 driver module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 17:25:20 -0700 (Thu, 29 May 2014) $
+#
+#
+#*****************************************************************************
+#
+#  Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+  INF_VERSION          = 0x00010005
+  VERSION_STRING       = 1.0
+  BASE_NAME            = SnpDxePort0
+  MODULE_TYPE          = UEFI_DRIVER
+  FILE_GUID            = 25ac458a-cf60-476e-861a-211c757657a6
+  ENTRY_POINT          = UefiMain
+
+[Binaries.AARCH64]
+  PE32|SnpDxePort0.efi
+  DEPEX|SnpDxePort0.depex
+
+[Packages]
+  AmdModulePkg/AmdModulePkg.dec
+
+[PatchPcd]
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeRev
+  gAmdModulePkgTokenSpaceGuid.PcdEthMacA
+  gAmdModulePkgTokenSpaceGuid.PcdEthMacB
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.depex
new file mode 100644
index 0000000..cb68e14
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.depex
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.efi
new file mode 100644
index 0000000..bf2c84d
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.efi
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.inf
new file mode 100644
index 0000000..12f8be2
--- /dev/null
+++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.inf
@@ -0,0 +1,48 @@
+# $NoKeywords */
+#
+# @file
+#
+# SnpDxePort1.inf
+#
+# Ethernet port 1 driver module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 17:25:20 -0700 (Thu, 29 May 2014) $
+#
+#
+#*****************************************************************************
+#
+#  Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+  INF_VERSION          = 0x00010005
+  VERSION_STRING       = 1.0
+  BASE_NAME            = SnpDxePort1
+  MODULE_TYPE          = UEFI_DRIVER
+  FILE_GUID            = 92ea3d06-5990-4436-b4e1-07a02f4a98a9
+  ENTRY_POINT          = UefiMain
+
+[Binaries.AARCH64]
+  PE32|SnpDxePort1.efi
+  DEPEX|SnpDxePort1.depex
+
+[Packages]
+  AmdModulePkg/AmdModulePkg.dec
+
+[PatchPcd]
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeRev
+  gAmdModulePkgTokenSpaceGuid.PcdEthMacA
+  gAmdModulePkgTokenSpaceGuid.PcdEthMacB
diff --git a/Platforms/AMD/Styx/CelloBoard/Binary/PreUefiFirmware.bin b/Platforms/AMD/Styx/CelloBoard/Binary/PreUefiFirmware.bin
new file mode 100644
index 0000000..6efb6a8
--- /dev/null
+++ b/Platforms/AMD/Styx/CelloBoard/Binary/PreUefiFirmware.bin
diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
new file mode 100644
index 0000000..d7e1a53
--- /dev/null
+++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
@@ -0,0 +1,666 @@
+#
+#  Copyright (c) 2015 - 2016, AMD Incorporated. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and made
+#  available under the terms and conditions of the BSD License which
+#  accompanies this distribution.  The full text of the license may
+#  be found at http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+
+DEFINE NUM_CORES = 8
+DEFINE DO_KCS    = 0
+
+  PLATFORM_NAME                  = Cello
+  PLATFORM_GUID                  = 77861b3e-74b0-4ff3-8d18-c5ba5803e1bf
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/Cello
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+  #
+  # Allow dynamic PCDs
+  #
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+  # Networking Requirements
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+  # ARM Architectural Libraries
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+  # ARM PL011 UART Driver
+  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+  #
+  # PCI support
+  #
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+  PciHostBridgeLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
+
+  #
+  # Styx specific libraries
+  #
+  AmdSataInit|AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
+  AmdStyxAcpiLib|OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf
+  EfiResetSystemLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf
+  RealTimeClockLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  #
+  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+  # in the debugger will show load and unload commands for symbols. You can cut and paste this
+  # into the command window to load symbols. We should be able to use a script to do this, but
+  # the version of RVD I have does not support scripts accessing system memory.
+  #
+  #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+  #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
+
+  ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+  DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+  # Trustzone Support
+  ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
+  MemoryInitPeiLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+###################################################################################################
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+#                        the default flags for a module. These flags are appended to any
+#                        standard flags that are defined by the build process.
+###################################################################################################
+
+[BuildOptions]
+  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+
+  *_*_*_ASL_FLAGS               = -tc -li -l -so
+  *_*_*_ASLPP_FLAGS             = $(ARCHCC_FLAGS)
+  *_*_*_ASLCC_FLAGS             = $(ARCHCC_FLAGS)
+
+  GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+  GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+
+  GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  # All pages are cached by default
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle
+  ## created by ConsplitterDxe. It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+  # DEBUG_ASSERT_ENABLED       0x01
+  # DEBUG_PRINT_ENABLED        0x02
+  # DEBUG_CODE_ENABLED         0x04
+  # CLEAR_MEMORY_ENABLED       0x08
+  # ASSERT_BREAKPOINT_ENABLED  0x10
+  # ASSERT_DEADLOOP_ENABLED    0x20
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+  #  DEBUG_INIT      0x00000001  // Initialization
+  #  DEBUG_WARN      0x00000002  // Warnings
+  #  DEBUG_LOAD      0x00000004  // Load events
+  #  DEBUG_FS        0x00000008  // EFI File system
+  #  DEBUG_POOL      0x00000010  // Alloc & Free's
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free's
+  #  DEBUG_INFO      0x00000040  // Verbose
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+  #  DEBUG_VARIABLE  0x00000100  // Variable
+  #  DEBUG_BM        0x00000400  // Boot Manager
+  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+  #  DEBUG_NET       0x00004000  // SNI Driver
+  #  DEBUG_UNDI      0x00010000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
+  #  DEBUG_EVENT     0x00080000  // Event messages
+  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
+  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
+  #  DEBUG_ERROR     0x80000000  // Error
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD Seattle"
+
+  # Number of configured cores
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES)
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800
+
+  # Declare system memory base
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000
+
+  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+  # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
+  # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
+  # that)
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
+  #
+  # ARM PrimeCell
+  #
+
+  ## PL011 - Serial Terminal (Atlas UART)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0E1010000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+  # serial port is clocked at 100MHz
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|100000000
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0E1010000
+  gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200
+
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xE1110000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
+
+  #
+  # ARM Architectual Timer Frequency
+  #
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000
+
+  #
+  # Cello has 2 SATA ports on the first controller.
+  #
+  gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2
+  gAmdStyxTokenSpaceGuid.PcdSata1PortCount|0
+
+  # PCIe Support
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
+
+  gArmTokenSpaceGuid.PcdPciBusMin|0x0
+  gArmTokenSpaceGuid.PcdPciBusMax|0xFF
+
+  gArmTokenSpaceGuid.PcdPciIoBase|0x1000
+  gArmTokenSpaceGuid.PcdPciIoSize|0xF000
+  gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFFF0000
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
+
+  gArmTokenSpaceGuid.PcdPciMmio32Base|0x40000000
+  gArmTokenSpaceGuid.PcdPciMmio32Size|0x80000000
+  gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+
+  gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+  gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000
+  gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
+  ## ACPI (no tables < 4GB)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE
+
+  # SMBIOS 3.0 only
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
+  gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000
+
+  # map the stack as non-executable when entering the DXE phase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+
+[PcdsPatchableInModule]
+# PCIe Configuration: x4x2x2
+  gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1
+  gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE
+
+[PcdsDynamicDefault.common]
+  gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
+
+[PcdsDynamicExHii.common.DEFAULT]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  AmdModulePkg/Iscp/IscpPei.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+  ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+  ArmPkg/Drivers/CpuPei/CpuPei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  #
+  # Console IO support
+  #
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  #
+  # Environment Variables Protocol
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+      TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+      VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  }
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+  #
+  # Iscp support
+  #
+  AmdModulePkg/Iscp/IscpDxe.inf
+
+  #
+  # PCI support
+  #
+  AmdModulePkg/Gionb/Gionb.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+  #
+  # USB Support
+  #
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # Networking stack
+  #
+  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+  #
+  # Core Info
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
+
+  #
+  # Crypto Accelerator support (RNG only)
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+      FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+
+!ifdef $(RENESAS_XHCI_FW_DIR)
+  OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
+!endif
diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf
new file mode 100644
index 0000000..2910353
--- /dev/null
+++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf
@@ -0,0 +1,397 @@
+#
+#  Copyright (c) 2015 - 2016, AMD Incorporated. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.STYX_ROM]
+BaseAddress   = 0x8000C80000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00500000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x500
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+FILE = OpenPlatformPkg/Platforms/AMD/Styx/CelloBoard/Binary/PreUefiFirmware.bin
+
+0x00200000|0x00260000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = STYX_EFI
+
+!include OpenPlatformPkg/Platforms/AMD/Styx/Common/Varstore.fdf.inc
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid         = 72b41709-8499-4841-a383-f432de6fce2a
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  #
+  # Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Environment Variables Protocol
+  #
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+  #
+  # Iscp support
+  #
+  INF AmdModulePkg/Iscp/IscpDxe.inf
+
+  #
+  # PCI support
+  #
+  INF AmdModulePkg/Gionb/Gionb.inf
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+  #
+  # USB Support
+  #
+  INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # Networking stack
+  #
+  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+  #
+  # Core Info
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+  #
+  # Crypto Accelerator support (RNG only)
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+  #
+  # Renesas PD720202 XHCI firmware uploader, requires firmware image
+  # in directory $(RENESAS_XHCI_FW_DIR)
+  #
+!ifdef $(RENESAS_XHCI_FW_DIR)
+  INF OpenPlatformPkg/Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf
+  FILE FREEFORM = A059EBC4-D73D-4279-81BF-E4A89308B923 {
+    SECTION RAW = $(RENESAS_XHCI_FW_DIR)/K2013080.mem
+  }
+!endif
+
+[FV.STYX_EFI]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  INF AmdModulePkg/Iscp/IscpPei.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE Align = 4K                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE Align = Auto              $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE Align = Auto           $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.Binary]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       |.depex
+     TE       TE Align = Auto           |.efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER.Binary]
+  FILE DRIVER = $(NAMED_GUID) {
+    PE32         PE32                   |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.Binary]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional |.depex
+    PE32         PE32                   |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)"     Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ASL                |.aml
+  }
+
diff --git a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h
new file mode 100644
index 0000000..698a5d3
--- /dev/null
+++ b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h
@@ -0,0 +1,61 @@
+/** @file
+  This library provides support for various platform-specific DXE drivers.
+
+  Copyright (c) 2014 - 2015, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMDSTYX_ACPI_LIB_H_
+#define _AMDSTYX_ACPI_LIB_H_
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_DESCRIPTION_HEADER *FadtTable (void);
+EFI_ACPI_DESCRIPTION_HEADER *FacsTable (void);
+EFI_ACPI_DESCRIPTION_HEADER *MadtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *GtdtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *DsdtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void);
+EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void);
+
+#define EFI_ACPI_AMD_OEM_ID_ARRAY        {'A','M','D','I','N','C'}
+#define EFI_ACPI_AMD_OEM_TABLE_ID        SIGNATURE_64('S','E','A','T','T','L','E',' ')
+#define EFI_ACPI_AMD_OEM_REVISION        0
+#define EFI_ACPI_AMD_CREATOR_ID          SIGNATURE_32('A','M','D',' ')
+#define EFI_ACPI_AMD_CREATOR_REVISION    0
+
+/**
+ * A macro to initialize the common header part of EFI ACPI tables
+ * as defined by EFI_ACPI_DESCRIPTION_HEADER structure.
+ **/
+#define AMD_ACPI_HEADER(sign, type, rev) {                      \
+  sign,                           /* UINT32  Signature */       \
+  sizeof (type),                  /* UINT32  Length */          \
+  rev,                            /* UINT8   Revision */        \
+  0,                              /* UINT8   Checksum */        \
+  EFI_ACPI_AMD_OEM_ID_ARRAY,      /* UINT8   OemId[6] */        \
+  EFI_ACPI_AMD_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+  EFI_ACPI_AMD_OEM_REVISION,      /* UINT32  OemRevision */     \
+  EFI_ACPI_AMD_CREATOR_ID,        /* UINT32  CreatorId */       \
+  EFI_ACPI_AMD_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+  }
+
+#define NULL_GAS               {EFI_ACPI_5_1_SYSTEM_MEMORY,  0, 0, EFI_ACPI_5_1_UNDEFINED, 0L}
+#define AMD_GAS8(address)      {EFI_ACPI_5_1_SYSTEM_MEMORY,  8, 0, EFI_ACPI_5_1_BYTE,      address}
+#define AMD_GAS16(address)     {EFI_ACPI_5_1_SYSTEM_MEMORY, 16, 0, EFI_ACPI_5_1_WORD,      address}
+#define AMD_GAS32(address)     {EFI_ACPI_5_1_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_1_DWORD,     address}
+#define AMD_GAS64(address)     {EFI_ACPI_5_1_SYSTEM_MEMORY, 64, 0, EFI_ACPI_5_1_QWORD,     address}
+#define AMD_GASN(address)      AMD_GAS32(address)
+
+#endif // _AMDSTYX_ACPI_LIB_H_
+
diff --git a/Platforms/AMD/Styx/Common/Protocol/AmdMpBoot.h b/Platforms/AMD/Styx/Common/Protocol/AmdMpBoot.h
new file mode 100644
index 0000000..2aa4c55
--- /dev/null
+++ b/Platforms/AMD/Styx/Common/Protocol/AmdMpBoot.h
@@ -0,0 +1,39 @@
+/** @file
+
+  Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMD_MP_BOOT_H_
+#define _AMD_MP_BOOT_H_
+
+extern EFI_GUID gAmdMpBootProtocolGuid;
+
+typedef
+VOID
+(EFIAPI *PARK_SECONDARY_CORE) (
+  IN ARM_CORE_INFO        *ArmCoreInfo,
+  IN EFI_PHYSICAL_ADDRESS SecondaryEntry
+  );
+
+typedef struct _AMD_MP_BOOT_INFO {
+  EFI_PHYSICAL_ADDRESS  MpParkingBase;
+  UINTN                 MpParkingSize;
+  ARM_CORE_INFO         *ArmCoreInfoTable;
+  UINTN                 ArmCoreCount;
+} AMD_MP_BOOT_INFO;
+
+typedef struct _AMD_MP_BOOT_PROTOCOL {
+  PARK_SECONDARY_CORE  ParkSecondaryCore;
+  AMD_MP_BOOT_INFO     *MpBootInfo;
+} AMD_MP_BOOT_PROTOCOL;
+
+#endif // _AMD_MP_BOOT_H_
diff --git a/Platforms/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h b/Platforms/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h
new file mode 100644
index 0000000..95f46e8
--- /dev/null
+++ b/Platforms/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h
@@ -0,0 +1,45 @@
+/** @file
+
+  Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMD_MP_CORE_INFO_H_
+#define _AMD_MP_CORE_INFO_H_
+
+extern EFI_GUID gAmdMpCoreInfoProtocolGuid;
+
+typedef
+ARM_CORE_INFO *
+(EFIAPI *GET_ARM_CORE_INFO_TABLE) (
+  OUT UINTN  *NumEntries
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_PMU_SPI_FROM_MPID) (
+  IN  UINT32  MpId,
+  OUT UINT32  *PmuSpi
+  );
+
+typedef
+EFI_PHYSICAL_ADDRESS
+(EFIAPI *GET_MP_PARKING_BASE) (
+  OUT UINTN  *MpParkingSize
+  );
+
+typedef struct _AMD_MP_CORE_INFO_PROTOCOL {
+  GET_ARM_CORE_INFO_TABLE  GetArmCoreInfoTable;
+  GET_PMU_SPI_FROM_MPID    GetPmuSpiFromMpId;
+  GET_MP_PARKING_BASE      GetMpParkingBase;
+} AMD_MP_CORE_INFO_PROTOCOL;
+
+#endif // _AMD_MP_CORE_INFO_H_
diff --git a/Platforms/AMD/Styx/Common/Varstore.fdf.inc b/Platforms/AMD/Styx/Common/Varstore.fdf.inc
new file mode 100644
index 0000000..83aa433
--- /dev/null
+++ b/Platforms/AMD/Styx/Common/Varstore.fdf.inc
@@ -0,0 +1,70 @@
+## @file
+#  FDF include file with Layout Regions that define an empty variable store.
+#
+#  Copyright (C) 2016, Linaro, Ltd.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+#  IMPLIED.
+#
+##
+
+0x00460000|0x0000F000
+gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  #     { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x30000
+  0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"       # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0xF Blocks * 0x1000 Bytes / Block
+  0x0F, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiAuthenticatedVariableGuid =
+  #   { 0xaaf32c78, 0x947b, 0x439a,
+  #     { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+  # Size: 0xF000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  #         0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xefb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xEF, 0x00, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x0046F000|0x00001000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid         =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00470000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 0000000..1bad597
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,110 @@
+/** @file
+
+  Sample ACPI Platform Driver
+
+  Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  Derived from:
+   MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatform.c
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <Protocol/AcpiTable.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+#define MAX_ACPI_TABLES    12
+
+EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES];
+
+
+/**
+  Entrypoint of Acpi Platform driver.
+
+  @param  ImageHandle
+  @param  SystemTable
+
+  @return EFI_SUCCESS
+  @return EFI_LOAD_ERROR
+  @return EFI_OUT_OF_RESOURCES
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS                Status;
+  EFI_ACPI_TABLE_PROTOCOL   *AcpiTable;
+  UINTN                     TableHandle;
+  UINTN                     TableIndex;
+
+  ZeroMem(AcpiTableList, sizeof(AcpiTableList));
+
+  TableIndex = 0;
+  AcpiTableList[TableIndex++] = FadtTable();
+  AcpiTableList[TableIndex++] = DsdtHeader();
+  AcpiTableList[TableIndex++] = MadtHeader();
+  AcpiTableList[TableIndex++] = GtdtHeader();
+  AcpiTableList[TableIndex++] = Dbg2Header();
+  AcpiTableList[TableIndex++] = SpcrHeader();
+  AcpiTableList[TableIndex++] = McfgHeader();
+  AcpiTableList[TableIndex++] = CsrtHeader();
+  AcpiTableList[TableIndex++] = NULL;
+
+  DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__));
+
+  //
+  // Find the AcpiTable protocol
+  //
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+  if (EFI_ERROR (Status)) {
+    DEBUG((EFI_D_ERROR, "Failed to locate AcpiTable protocol. Status = %r\n", Status));
+    ASSERT_EFI_ERROR(Status);
+  }
+
+  TableIndex = 0;
+  while (AcpiTableList[TableIndex] != NULL) {
+    //
+    // Install ACPI table
+    //
+    DEBUG ((EFI_D_ERROR, "Installing %c%c%c%c Table (Revision %d, Length %d) ...\n",
+                          *((UINT8*)&AcpiTableList[TableIndex]->Signature),
+                          *((UINT8*)&AcpiTableList[TableIndex]->Signature + 1),
+                          *((UINT8*)&AcpiTableList[TableIndex]->Signature + 2),
+                          *((UINT8*)&AcpiTableList[TableIndex]->Signature + 3),
+                          AcpiTableList[TableIndex]->Revision,
+                          AcpiTableList[TableIndex]->Length));
+
+    Status = AcpiTable->InstallAcpiTable (
+                            AcpiTable,
+                            AcpiTableList[TableIndex],
+                            (AcpiTableList[TableIndex])->Length,
+                            &TableHandle
+                            );
+    if (EFI_ERROR (Status)) {
+      DEBUG((DEBUG_ERROR,"Error adding ACPI Table. Status = %r\n", Status));
+      ASSERT_EFI_ERROR(Status);
+    }
+    TableIndex++;
+    ASSERT( TableIndex < MAX_ACPI_TABLES );
+  }
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
index 1fec2db..9f4c3ea 100644
--- a/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
+++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -1,6 +1,9 @@
 #/** @file
+#  Sample ACPI Platform Driver
+#
+#  Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
 #
-#  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
@@ -10,43 +13,37 @@
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 #**/
+#/**
+#  Derived from:
+#   MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+#**/
 
 [Defines]
   INF_VERSION                    = 0x00010005
-  BASE_NAME                      = LcdGraphicsDxe
-  FILE_GUID                      = E68088EF-D1A4-4336-C1DB-4D3A204730A6
+  BASE_NAME                      = AcpiPlatform
+  FILE_GUID                      = f229c831-6a35-440b-9c84-dd3bc71e3865
   MODULE_TYPE                    = DXE_DRIVER
   VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = LcdGraphicsOutputDxeInitialize
+  ENTRY_POINT                    = AcpiPlatformEntryPoint
 
-[Sources.common]
-  LcdGraphicsOutputDxe.c
-  LcdGraphicsOutputBlt.c
+[Sources]
+  AcpiPlatform.c
 
 [Packages]
+  ArmPkg/ArmPkg.dec
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
-  ArmPkg/ArmPkg.dec
-  ArmPlatformPkg/ArmPlatformPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
 
 [LibraryClasses]
-  ArmLib
-  UefiLib
-  BaseLib
   DebugLib
-  TimerLib
-  UefiDriverEntryPoint
   UefiBootServicesTableLib
-  IoLib
-  BaseMemoryLib
+  UefiDriverEntryPoint
+  AmdStyxAcpiLib
 
 [Protocols]
-  gEfiDevicePathProtocolGuid
-  gEfiGraphicsOutputProtocolGuid
-  gEfiDevicePathToTextProtocolGuid
-  gEmbeddedExternalDeviceProtocolGuid
+  gEfiAcpiTableProtocolGuid                     ## ALWAYS_CONSUMED
 
 [Depex]
-  gEfiCpuArchProtocolGuid AND gEfiTimerArchProtocolGuid
+  gEfiAcpiTableProtocolGuid
diff --git a/Platforms/AMD/Styx/Drivers/FdtDxe/BdsLinuxFdt.c b/Platforms/AMD/Styx/Drivers/FdtDxe/BdsLinuxFdt.c
new file mode 100644
index 0000000..aa59504
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/FdtDxe/BdsLinuxFdt.c
@@ -0,0 +1,760 @@
+/** @file
+*
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+*  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+
+  Derived from:
+   ArmPkg/Library/BdsLib/BdsLinuxFdt.c
+
+**/
+
+#include <Library/PcdLib.h>
+#include <libfdt.h>
+
+#include <Library/BdsLib/BdsInternal.h>
+
+#include <Guid/ArmMpCoreInfo.h>
+#include <Protocol/AmdMpCoreInfo.h>
+
+#define LINUX_FDT_MAX_OFFSET      (PcdGet64 (PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset))
+
+
+// Additional size that could be used for FDT entries added by the UEFI OS Loader
+// Estimation based on: EDID (300bytes) + bootargs (200bytes) + initrd region (20bytes)
+//                      + system memory region (20bytes) + mp_core entries (200 bytes)
+#define FDT_ADDITIONAL_ENTRIES_SIZE     0x300
+
+
+EFI_STATUS
+GetSystemMemoryResources (
+  IN  LIST_ENTRY *ResourceList
+  );
+
+VOID
+DebugDumpFdt (
+  IN VOID*                FdtBlob
+  );
+
+#define ALIGN(x, a)     (((x) + ((a) - 1)) & ~((a) - 1))
+#define PALIGN(p, a)    ((void *)(ALIGN((unsigned long)(p), (a))))
+#define GET_CELL(p)     (p += 4, *((const UINT32 *)(p-4)))
+
+//
+// PMU interrupts per core
+//
+#pragma pack(push, 1)
+typedef struct {
+  UINT32 Flag;          // 0 == SPI
+  UINT32 IntId;         // GSIV == IntId+32
+  UINT32 Type;          // 4 == Level-Sensitive, Active-High
+} PMU_INTERRUPT;
+#pragma pack(pop)
+
+#define PMU_INT_FLAG_SPI        0
+#define PMU_INT_TYPE_HIGH_LEVEL 4
+
+
+typedef struct {
+  UINTN   Base;
+  UINTN   Size;
+} FdtRegion;
+
+
+STATIC
+UINTN
+cpu_to_fdtn (UINTN x) {
+  if (sizeof (UINTN) == sizeof (UINT32)) {
+    return cpu_to_fdt32 (x);
+  } else {
+    return cpu_to_fdt64 (x);
+  }
+}
+
+
+STATIC
+BOOLEAN
+ClusterInRange(
+  IN ARM_CORE_INFO *ArmCoreInfoTable,
+  IN UINTN         ClusterId,
+  IN UINTN         LowIndex,
+  IN UINTN         HighIndex
+  )
+{
+  do {
+    if (ClusterId == ArmCoreInfoTable[LowIndex].ClusterId)
+      return TRUE;
+  } while (++LowIndex <= HighIndex);
+
+  return FALSE;
+}
+
+
+STATIC
+UINTN
+NumberOfCoresInCluster(
+  IN ARM_CORE_INFO *ArmCoreInfoTable,
+  IN UINTN         NumberOfEntries,
+  IN UINTN         ClusterId
+  )
+{
+  UINTN Index, Cores;
+
+  Cores = 0;
+  for (Index = 0; Index < NumberOfEntries; ++Index) {
+    if (ClusterId == ArmCoreInfoTable[Index].ClusterId)
+      ++Cores;
+  }
+
+  return Cores;
+}
+
+
+STATIC
+UINTN
+NumberOfClustersInTable(
+  IN ARM_CORE_INFO *ArmCoreInfoTable,
+  IN UINTN         NumberOfEntries
+  )
+{
+  UINTN Index, Cores, Clusters, ClusterId;
+
+  Index = 0;
+  Clusters = 0;
+  Cores = NumberOfEntries;
+  while (Cores) {
+     ++Clusters;
+     ClusterId = ArmCoreInfoTable[Index].ClusterId;
+     Cores -= NumberOfCoresInCluster (ArmCoreInfoTable,
+                                      NumberOfEntries,
+                                      ClusterId);
+     if (Cores) {
+       do {
+         ++Index;
+       } while (ClusterInRange (ArmCoreInfoTable,
+                                ArmCoreInfoTable[Index].ClusterId,
+                                0, Index-1));
+     }
+  }
+
+  return Clusters;
+}
+
+
+STATIC
+int
+fdt_alloc_phandle(
+  IN VOID *blob
+  )
+{
+
+  int offset, phandle = 0;
+
+  for (offset = fdt_next_node(blob, -1, NULL); offset >= 0;
+       offset = fdt_next_node(blob, offset, NULL)) {
+       phandle = MAX(phandle, fdt_get_phandle(blob, offset));
+  }
+
+  return phandle + 1;
+}
+
+
+STATIC
+BOOLEAN
+IsLinuxReservedRegion (
+  IN EFI_MEMORY_TYPE MemoryType
+  )
+{
+  switch(MemoryType) {
+  case EfiRuntimeServicesCode:
+  case EfiRuntimeServicesData:
+  case EfiUnusableMemory:
+  case EfiACPIReclaimMemory:
+  case EfiACPIMemoryNVS:
+  case EfiReservedMemoryType:
+    return TRUE;
+  default:
+    return FALSE;
+  }
+}
+
+STATIC
+VOID
+SetDeviceStatus (
+  IN VOID *fdt,
+  IN CHAR8 *device,
+  IN BOOLEAN enable
+  )
+{
+  int node, subnode, rc;
+
+  node = fdt_subnode_offset (fdt, 0, "smb");
+  if (node >= 0) {
+    subnode = fdt_subnode_offset (fdt, node, device);
+    if (subnode >= 0) {
+      rc = fdt_setprop_string(fdt, subnode, "status", enable ? "ok" : "disabled");
+      if (rc) {
+        DEBUG((EFI_D_ERROR,"%a: Could not set 'status' property for '%a' node\n",
+            __FUNCTION__, device));
+      }
+    }
+  }
+}
+
+#if DO_XGBE
+STATIC
+VOID
+SetMacAddress (
+  IN VOID *fdt,
+  IN CHAR8 *device,
+  IN UINT64 mac_addr
+  )
+{
+  int node, subnode, rc;
+
+  node = fdt_subnode_offset (fdt, 0, "smb");
+  if (node >= 0) {
+    subnode = fdt_subnode_offset (fdt, node, device);
+    if (subnode >= 0) {
+      rc = fdt_setprop(fdt, subnode, "mac-address", (void *)&mac_addr, 6);
+      if (rc) {
+        DEBUG((EFI_D_ERROR,"%a: Could not set 'mac-address' property for '%a' node\n",
+            __FUNCTION__, device));
+      }
+    }
+  }
+}
+#endif
+
+VOID
+SetSocIdStatus (
+  IN VOID *fdt
+  )
+{
+  UINT32                SocId;
+  BOOLEAN               IsRevB1;
+
+  SocId = PcdGet32 (PcdSocCpuId);
+  IsRevB1 = (SocId & 0xFF0) && (SocId & 0x00F);
+
+  SetDeviceStatus (fdt, "sata@e0d00000",
+    IsRevB1 && FixedPcdGet8(PcdSata1PortCount) > 0);
+  SetDeviceStatus (fdt, "gpio@e0020000", IsRevB1);
+  SetDeviceStatus (fdt, "gpio@e0030000", IsRevB1);
+  SetDeviceStatus (fdt, "gwdt@e0bb0000", IsRevB1);
+#if DO_KCS
+  SetDeviceStatus (fdt, "kcs@e0010000", IsRevB1);
+#else
+  SetDeviceStatus (fdt, "kcs@e0010000", FALSE);
+#endif
+}
+
+VOID
+SetXgbeStatus (
+  IN VOID *fdt
+  )
+{
+#if DO_XGBE
+  SetDeviceStatus (fdt, "xgmac@e0700000", TRUE);
+  SetDeviceStatus (fdt, "phy@e1240800", TRUE);
+  SetDeviceStatus (fdt, "xgmac@e0900000", TRUE);
+  SetDeviceStatus (fdt, "phy@e1240c00", TRUE);
+
+  SetMacAddress (fdt, "xgmac@e0700000", PcdGet64 (PcdEthMacA));
+  SetMacAddress (fdt, "xgmac@e0900000", PcdGet64 (PcdEthMacB));
+#else
+  SetDeviceStatus (fdt, "xgmac@e0700000", FALSE);
+  SetDeviceStatus (fdt, "phy@e1240800", FALSE);
+  SetDeviceStatus (fdt, "xgmac@e0900000", FALSE);
+  SetDeviceStatus (fdt, "phy@e1240c00", FALSE);
+#endif
+}
+
+
+/**
+** Relocate the FDT blob to a more appropriate location for the Linux kernel.
+** This function will allocate memory for the relocated FDT blob.
+**
+** @retval EFI_SUCCESS on success.
+** @retval EFI_OUT_OF_RESOURCES or EFI_INVALID_PARAMETER on failure.
+*/
+STATIC
+EFI_STATUS
+RelocateFdt (
+  EFI_PHYSICAL_ADDRESS   OriginalFdt,
+  UINTN                  OriginalFdtSize,
+  EFI_PHYSICAL_ADDRESS   *RelocatedFdt,
+  UINTN                  *RelocatedFdtSize,
+  EFI_PHYSICAL_ADDRESS   *RelocatedFdtAlloc
+  )
+{
+  EFI_STATUS            Status;
+  INTN                  Error;
+  UINT64                FdtAlignment;
+
+  *RelocatedFdtSize = OriginalFdtSize + FDT_ADDITIONAL_ENTRIES_SIZE;
+
+  // If FDT load address needs to be aligned, allocate more space.
+  FdtAlignment = PcdGet32 (PcdArmLinuxFdtAlignment);
+  if (FdtAlignment != 0) {
+    *RelocatedFdtSize += FdtAlignment;
+  }
+
+  // Try below a watermark address.
+  Status = EFI_NOT_FOUND;
+  if (PcdGet32 (PcdArmLinuxFdtMaxOffset) != 0) {
+    *RelocatedFdt = LINUX_FDT_MAX_OFFSET;
+    Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData,
+                    EFI_SIZE_TO_PAGES (*RelocatedFdtSize), RelocatedFdt);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((EFI_D_WARN, "Warning: Failed to load FDT below address 0x%lX (%r). Will try again at a random address anywhere.\n", *RelocatedFdt, Status));
+    }
+  }
+
+  // Try anywhere there is available space.
+  if (EFI_ERROR (Status)) {
+    Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData,
+                    EFI_SIZE_TO_PAGES (*RelocatedFdtSize), RelocatedFdt);
+    if (EFI_ERROR (Status)) {
+      ASSERT_EFI_ERROR (Status);
+      return EFI_OUT_OF_RESOURCES;
+    } else {
+      DEBUG ((EFI_D_WARN, "WARNING: Loaded FDT at random address 0x%lX.\nWARNING: There is a risk of accidental overwriting by other code/data.\n", *RelocatedFdt));
+    }
+  }
+
+  *RelocatedFdtAlloc = *RelocatedFdt;
+  if (FdtAlignment != 0) {
+    *RelocatedFdt = ALIGN (*RelocatedFdt, FdtAlignment);
+  }
+
+  // Load the Original FDT tree into the new region
+  Error = fdt_open_into ((VOID*)(UINTN) OriginalFdt,
+            (VOID*)(UINTN)(*RelocatedFdt), *RelocatedFdtSize);
+  if (Error) {
+    DEBUG ((EFI_D_ERROR, "fdt_open_into(): %a\n", fdt_strerror (Error)));
+    gBS->FreePages (*RelocatedFdtAlloc, EFI_SIZE_TO_PAGES (*RelocatedFdtSize));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  DEBUG_CODE_BEGIN();
+    // DebugDumpFdt ((VOID*)(UINTN)(*RelocatedFdt));
+  DEBUG_CODE_END();
+
+  return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+AmdStyxPrepareFdt (
+  IN     CONST CHAR8*         CommandLineArguments,
+  IN     EFI_PHYSICAL_ADDRESS InitrdImage,
+  IN     UINTN                InitrdImageSize,
+  IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
+  IN OUT UINTN                *FdtBlobSize
+  )
+{
+  EFI_STATUS            Status;
+  EFI_PHYSICAL_ADDRESS  NewFdtBlobBase;
+  EFI_PHYSICAL_ADDRESS  NewFdtBlobAllocation;
+  UINTN                 NewFdtBlobSize;
+  VOID                 *fdt;
+  int                   err;
+  int                   node;
+  int                   cpu_node;
+  int                   lenp;
+  CONST VOID           *BootArg;
+  EFI_PHYSICAL_ADDRESS  InitrdImageStart;
+  EFI_PHYSICAL_ADDRESS  InitrdImageEnd;
+  FdtRegion             Region;
+  UINTN                 Index;
+  CHAR8                 Name[10];
+  LIST_ENTRY            ResourceList;
+  BDS_SYSTEM_MEMORY_RESOURCE  *Resource;
+  ARM_CORE_INFO         *ArmCoreInfoTable;
+  UINTN                 ArmCoreCount;
+  UINT32                PrimaryClusterId;
+  UINT32                PrimaryCoreId;
+  UINTN                 MemoryMapSize;
+  EFI_MEMORY_DESCRIPTOR *MemoryMap;
+  EFI_MEMORY_DESCRIPTOR *MemoryMapPtr;
+  UINTN                 MapKey;
+  UINTN                 DescriptorSize;
+  UINT32                DescriptorVersion;
+  UINTN                 Pages;
+  UINTN                 OriginalFdtSize;
+  int                   map_node;
+  int                   cluster_node;
+  int                   pmu_node;
+  PMU_INTERRUPT         PmuInt;
+  int                   phandle[NUM_CORES];
+  UINT32                ClusterIndex, CoreIndex;
+  UINT32                ClusterCount, CoresInCluster;
+  UINT32                ClusterId;
+  UINTN                 MpId, MbAddr;
+  AMD_MP_CORE_INFO_PROTOCOL *AmdMpCoreInfoProtocol;
+
+  //
+  // Sanity checks on the original FDT blob.
+  //
+  err = fdt_check_header ((VOID*)(UINTN)(*FdtBlobBase));
+  if (err != 0) {
+    Print (L"ERROR: Device Tree header not valid (err:%d)\n", err);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // The original FDT blob might have been loaded partially.
+  // Check that it is not the case.
+  OriginalFdtSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(*FdtBlobBase));
+  if (OriginalFdtSize > *FdtBlobSize) {
+    Print (L"ERROR: Incomplete FDT. Only %d/%d bytes have been loaded.\n",
+           *FdtBlobSize, OriginalFdtSize);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Relocate the FDT to its final location.
+  //
+  NewFdtBlobAllocation = 0;
+  Status = RelocateFdt (*FdtBlobBase, OriginalFdtSize,
+             &NewFdtBlobBase, &NewFdtBlobSize, &NewFdtBlobAllocation);
+  if (EFI_ERROR (Status)) {
+    goto FAIL_RELOCATE_FDT;
+  }
+  fdt = (VOID*)(UINTN)NewFdtBlobBase;
+
+  node = fdt_subnode_offset (fdt, 0, "chosen");
+  if (node < 0) {
+    // The 'chosen' node does not exist, create it
+    node = fdt_add_subnode(fdt, 0, "chosen");
+    if (node < 0) {
+      DEBUG((EFI_D_ERROR,"Error on finding 'chosen' node\n"));
+      Status = EFI_INVALID_PARAMETER;
+      goto FAIL_COMPLETE_FDT;
+    }
+  }
+
+  DEBUG_CODE_BEGIN();
+    BootArg = fdt_getprop(fdt, node, "bootargs", &lenp);
+    if (BootArg != NULL) {
+      DEBUG((EFI_D_ERROR,"BootArg: %a\n",BootArg));
+    }
+  DEBUG_CODE_END();
+
+  //
+  // Set Linux CmdLine
+  //
+  if ((CommandLineArguments != NULL) && (AsciiStrLen (CommandLineArguments) > 0)) {
+    err = fdt_setprop(fdt, node, "bootargs", CommandLineArguments, AsciiStrSize(CommandLineArguments));
+    if (err) {
+      DEBUG((EFI_D_ERROR,"Fail to set new 'bootarg' (err:%d)\n",err));
+    }
+  }
+
+  //
+  // Set Linux Initrd
+  //
+  if (InitrdImageSize != 0) {
+    InitrdImageStart = cpu_to_fdt64 (InitrdImage);
+    err = fdt_setprop(fdt, node, "linux,initrd-start", &InitrdImageStart, sizeof(EFI_PHYSICAL_ADDRESS));
+    if (err) {
+      DEBUG((EFI_D_ERROR,"Fail to set new 'linux,initrd-start' (err:%d)\n",err));
+    }
+    InitrdImageEnd = cpu_to_fdt64 (InitrdImage + InitrdImageSize);
+    err = fdt_setprop(fdt, node, "linux,initrd-end", &InitrdImageEnd, sizeof(EFI_PHYSICAL_ADDRESS));
+    if (err) {
+      DEBUG((EFI_D_ERROR,"Fail to set new 'linux,initrd-start' (err:%d)\n",err));
+    }
+  }
+
+  //
+  // Set Physical memory setup if does not exist
+  //
+  node = fdt_subnode_offset(fdt, 0, "memory");
+  if (node < 0) {
+    // The 'memory' node does not exist, create it
+    node = fdt_add_subnode(fdt, 0, "memory");
+    if (node >= 0) {
+      fdt_setprop_string(fdt, node, "name", "memory");
+      fdt_setprop_string(fdt, node, "device_type", "memory");
+
+      GetSystemMemoryResources (&ResourceList);
+      Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)ResourceList.ForwardLink;
+
+      Region.Base = cpu_to_fdtn ((UINTN)Resource->PhysicalStart);
+      Region.Size = cpu_to_fdtn ((UINTN)Resource->ResourceLength);
+
+      err = fdt_setprop(fdt, node, "reg", &Region, sizeof(Region));
+      if (err) {
+        DEBUG((EFI_D_ERROR,"Fail to set new 'memory region' (err:%d)\n",err));
+      }
+    }
+  }
+
+  //
+  // Add the memory regions reserved by the UEFI Firmware
+  //
+
+  // Retrieve the UEFI Memory Map
+  MemoryMap = NULL;
+  MemoryMapSize = 0;
+  Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+  if (Status == EFI_BUFFER_TOO_SMALL) {
+    // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive
+    // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size.
+    Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
+    MemoryMap = AllocatePages (Pages);
+    if (MemoryMap == NULL) {
+      Status = EFI_OUT_OF_RESOURCES;
+      goto FAIL_COMPLETE_FDT;
+    }
+    Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+  }
+
+  // Go through the list and add the reserved region to the Device Tree
+  if (!EFI_ERROR(Status)) {
+    MemoryMapPtr = MemoryMap;
+    for (Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++) {
+      if (IsLinuxReservedRegion ((EFI_MEMORY_TYPE)MemoryMapPtr->Type)) {
+        DEBUG((DEBUG_VERBOSE, "Reserved region of type %d [0x%lX, 0x%lX]\n",
+            MemoryMapPtr->Type,
+            (UINTN)MemoryMapPtr->PhysicalStart,
+            (UINTN)(MemoryMapPtr->PhysicalStart + MemoryMapPtr->NumberOfPages * EFI_PAGE_SIZE)));
+        err = fdt_add_mem_rsv(fdt, MemoryMapPtr->PhysicalStart, MemoryMapPtr->NumberOfPages * EFI_PAGE_SIZE);
+        if (err != 0) {
+          Print(L"Warning: Fail to add 'memreserve' (err:%d)\n", err);
+        }
+      }
+      MemoryMapPtr = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + DescriptorSize);
+    }
+  }
+
+  //
+  // Setup Arm Mpcore Info if it is a multi-core or multi-cluster platforms.
+  //
+  // For 'cpus' and 'cpu' device tree nodes bindings, refer to this file
+  // in the kernel documentation:
+  // Documentation/devicetree/bindings/arm/cpus.txt
+  //
+  Status = gBS->LocateProtocol (
+               &gAmdMpCoreInfoProtocolGuid,
+               NULL,
+               (VOID **)&AmdMpCoreInfoProtocol
+               );
+  ASSERT_EFI_ERROR (Status);
+
+  // Get pointer to ARM core info table
+  ArmCoreInfoTable = AmdMpCoreInfoProtocol->GetArmCoreInfoTable (&ArmCoreCount);
+  ASSERT (ArmCoreInfoTable != NULL);
+  ASSERT (ArmCoreCount <= NUM_CORES);
+
+  // Get Id from primary CPU
+  MpId = (UINTN) ArmReadMpidr ();
+  PrimaryClusterId = GET_CLUSTER_ID((UINT32) MpId);
+  PrimaryCoreId    = GET_CORE_ID((UINT32) MpId);
+
+  // Remove existing 'pmu' node and create a new one
+  pmu_node = fdt_subnode_offset (fdt, 0, "pmu");
+  if (pmu_node >= 0) {
+    fdt_del_node (fdt, pmu_node);
+  }
+  pmu_node = fdt_add_subnode(fdt, 0, "pmu");
+  if (pmu_node >= 0) {
+    // append PMU interrupts
+    for (Index = 0; Index < ArmCoreCount; Index++) {
+      MpId = (UINTN) GET_MPID (ArmCoreInfoTable[Index].ClusterId,
+                               ArmCoreInfoTable[Index].CoreId);
+
+      Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId);
+      if (EFI_ERROR (Status)) {
+        DEBUG ((EFI_D_ERROR, "FDT: Error getting PMU interrupt for MpId '0x%x'\n", MpId));
+        goto FAIL_COMPLETE_FDT;
+      }
+
+      PmuInt.Flag = cpu_to_fdt32(PMU_INT_FLAG_SPI);
+      PmuInt.IntId = cpu_to_fdt32(PmuInt.IntId);
+      PmuInt.Type = cpu_to_fdt32(PMU_INT_TYPE_HIGH_LEVEL);
+      fdt_appendprop(fdt, pmu_node, "interrupts", &PmuInt, sizeof(PmuInt));
+    }
+    fdt_setprop_string(fdt, pmu_node, "compatible", "arm,armv8-pmuv3");
+  } else {
+    DEBUG((EFI_D_ERROR,"FDT: Error creating 'pmu' node\n"));
+    Status = EFI_INVALID_PARAMETER;
+    goto FAIL_COMPLETE_FDT;
+  }
+
+  // Remove existing 'psci' node if feature not supported
+  node = fdt_subnode_offset (fdt, 0, "psci");
+  if (node >= 0) {
+    if (!FixedPcdGetBool (PcdPsciOsSupport)) {
+      fdt_del_node (fdt, node);
+    }
+  } else if (FixedPcdGetBool (PcdPsciOsSupport) &&
+      FixedPcdGetBool (PcdTrustedFWSupport)) {
+    // Add 'psci' node if not present
+    node = fdt_add_subnode(fdt, 0, "psci");
+    if (node >= 0) {
+      fdt_setprop_string(fdt, node, "compatible", "arm,psci-0.2");
+      fdt_appendprop_string(fdt, node, "compatible", "arm,psci");
+      fdt_setprop_string(fdt, node, "method", "smc");
+    } else {
+      DEBUG((EFI_D_ERROR,"FDT: Error creating 'psci' node\n"));
+      Status = EFI_INVALID_PARAMETER;
+      goto FAIL_COMPLETE_FDT;
+    }
+  }
+
+  // Remove existing 'cpus' node and create a new one
+  node = fdt_subnode_offset (fdt, 0, "cpus");
+  if (node >= 0) {
+    fdt_del_node (fdt, node);
+  }
+  node = fdt_add_subnode(fdt, 0, "cpus");
+  if (node >= 0) {
+    // Configure the 'cpus' node
+    fdt_setprop_string(fdt, node, "name", "cpus");
+    fdt_setprop_cell (fdt, node, "#address-cells", sizeof (UINTN) / 4);
+    fdt_setprop_cell(fdt, node, "#size-cells", 0);
+  } else {
+    DEBUG((EFI_D_ERROR,"FDT: Error creating 'cpus' node\n"));
+    Status = EFI_INVALID_PARAMETER;
+    goto FAIL_COMPLETE_FDT;
+  }
+
+  //
+  // Walk the processor table in reverse order for proper listing in FDT
+  //
+  Index = ArmCoreCount;
+  while (Index--) {
+    // Create 'cpu' node
+    AsciiSPrint (Name, sizeof(Name), "CPU%d", Index);
+    cpu_node = fdt_add_subnode (fdt, node, Name);
+    if (cpu_node < 0) {
+      DEBUG ((EFI_D_ERROR, "FDT: Error on creating '%a' node\n", Name));
+      Status = EFI_INVALID_PARAMETER;
+      goto FAIL_COMPLETE_FDT;
+    }
+    phandle[Index] = fdt_alloc_phandle(fdt);
+    fdt_setprop_cell (fdt, cpu_node, "phandle", phandle[Index]);
+    fdt_setprop_cell (fdt, cpu_node, "linux,phandle", phandle[Index]);
+
+    if (FixedPcdGetBool (PcdPsciOsSupport) &&
+      FixedPcdGetBool (PcdTrustedFWSupport)) {
+      fdt_setprop_string(fdt, cpu_node, "enable-method", "psci");
+    } else {
+      fdt_setprop_string(fdt, cpu_node, "enable-method", "spin-table");
+      MbAddr = ArmCoreInfoTable[Index].MailboxSetAddress;
+      MbAddr = cpu_to_fdtn (MbAddr);
+      fdt_setprop (fdt, cpu_node, "cpu-release-addr", &MbAddr, sizeof (MbAddr));
+    }
+    MpId = (UINTN) GET_MPID (ArmCoreInfoTable[Index].ClusterId,
+                                 ArmCoreInfoTable[Index].CoreId);
+    MpId = cpu_to_fdtn (MpId);
+    fdt_setprop (fdt, cpu_node, "reg", &MpId, sizeof (MpId));
+    fdt_setprop_string(fdt, cpu_node, "compatible", "arm,armv8");
+    fdt_setprop_string (fdt, cpu_node, "device_type", "cpu");
+
+    // If it is not the primary core than the cpu should be disabled
+    if (((ArmCoreInfoTable[Index].ClusterId != PrimaryClusterId) ||
+         (ArmCoreInfoTable[Index].CoreId != PrimaryCoreId))) {
+      fdt_setprop_string(fdt, cpu_node, "status", "disabled");
+    }
+  }
+
+  // Remove existing 'cpu-map' node and create a new one
+  map_node = fdt_subnode_offset (fdt, node, "cpu-map");
+  if (map_node >= 0) {
+    fdt_del_node (fdt, map_node);
+  }
+  map_node = fdt_add_subnode(fdt, node, "cpu-map");
+  if (map_node >= 0) {
+    ClusterIndex = ArmCoreCount - 1;
+    ClusterCount = NumberOfClustersInTable (ArmCoreInfoTable,
+                                            ArmCoreCount);
+    while (ClusterCount--) {
+      // Create 'cluster' node
+      AsciiSPrint (Name, sizeof(Name), "cluster%d", ClusterCount);
+      cluster_node = fdt_add_subnode (fdt, map_node, Name);
+      if (cluster_node < 0) {
+        DEBUG ((EFI_D_ERROR, "FDT: Error creating '%a' node\n", Name));
+        Status = EFI_INVALID_PARAMETER;
+        goto FAIL_COMPLETE_FDT;
+      }
+
+      ClusterId = ArmCoreInfoTable[ClusterIndex].ClusterId;
+      CoreIndex = ClusterIndex;
+      CoresInCluster = NumberOfCoresInCluster (ArmCoreInfoTable,
+                                               ArmCoreCount,
+                                               ClusterId);
+      while (CoresInCluster--) {
+        // Create 'core' node
+        AsciiSPrint (Name, sizeof(Name), "core%d", CoresInCluster);
+        cpu_node = fdt_add_subnode (fdt, cluster_node, Name);
+        if (cpu_node < 0) {
+          DEBUG ((EFI_D_ERROR, "FDT: Error creating '%a' node\n", Name));
+          Status = EFI_INVALID_PARAMETER;
+          goto FAIL_COMPLETE_FDT;
+        }
+        fdt_setprop_cell (fdt, cpu_node, "cpu", phandle[CoreIndex]);
+
+        // iterate to next core in cluster
+        if (CoresInCluster) {
+          do {
+             --CoreIndex;
+          } while (ClusterId != ArmCoreInfoTable[CoreIndex].ClusterId);
+        }
+      }
+
+      // iterate to next cluster
+      if (ClusterCount) {
+        do {
+           --ClusterIndex;
+        } while (ClusterInRange (ArmCoreInfoTable,
+                                 ArmCoreInfoTable[ClusterIndex].ClusterId,
+                                 ClusterIndex + 1,
+                                 ArmCoreCount - 1));
+      }
+    }
+  } else {
+    DEBUG((EFI_D_ERROR,"FDT: Error creating 'cpu-map' node\n"));
+    Status = EFI_INVALID_PARAMETER;
+    goto FAIL_COMPLETE_FDT;
+  }
+
+  SetSocIdStatus (fdt);
+  SetXgbeStatus (fdt);
+
+  DEBUG_CODE_BEGIN();
+    // DebugDumpFdt (fdt);
+  DEBUG_CODE_END();
+
+  // If we succeeded to generate the new Device Tree then free the old Device Tree
+  gBS->FreePages (*FdtBlobBase, EFI_SIZE_TO_PAGES (*FdtBlobSize));
+
+  // Update the real size of the Device Tree
+  fdt_pack ((VOID*)(UINTN)(NewFdtBlobBase));
+
+  *FdtBlobBase = NewFdtBlobBase;
+  *FdtBlobSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(NewFdtBlobBase));
+  return EFI_SUCCESS;
+
+FAIL_COMPLETE_FDT:
+  gBS->FreePages (NewFdtBlobAllocation, EFI_SIZE_TO_PAGES (NewFdtBlobSize));
+
+FAIL_RELOCATE_FDT:
+  *FdtBlobSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(*FdtBlobBase));
+  // Return success even if we failed to update the FDT blob.
+  // The original one is still valid.
+  return EFI_SUCCESS;
+}
+
diff --git a/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.c b/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.c
new file mode 100644
index 0000000..09d650d
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.c
@@ -0,0 +1,274 @@
+/** @file
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "FdtDxe.h"
+
+extern  EFI_BOOT_SERVICES       *gBS;
+
+EFI_EVENT mFdtReadyToBootEvent;
+
+VOID
+EFIAPI
+FdtReadyToBoot (
+  IN      EFI_EVENT      Event,
+  IN      VOID           *Context
+  );
+
+EFI_STATUS
+EFIAPI
+FdtOverrideDevicePath(
+  IN CHAR16 *FdtFileName,
+  OUT EFI_DEVICE_PATH **FdtDevicePath
+  );
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  FdtDxeEntryPoint
+ *
+ *  Description:
+ *    Entry point of the FDT Runtime Driver.
+ *
+ *  Control flow:
+ *    Configure reserved regions.
+ *
+ *  Parameters:
+ *    @param[in]      ImageHandle          The firmware allocate handle for the
+ *                                         EFI image.
+ *    @param[in]      *SystemTable         Pointer to the EFI System Table.
+ *
+ *    @return         EFI_STATUS
+ *
+ *------------------------------------------------------------------------------------
+ **/
+EFI_STATUS
+EFIAPI
+FdtDxeEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS              Status;
+
+  DEBUG ((EFI_D_ERROR, "FdtDxe Loaded\n"));
+
+  //
+  // Ready-To-Boot callback
+  //
+  Status = EfiCreateEventReadyToBootEx(
+                               TPL_CALLBACK,
+                               FdtReadyToBoot,
+                               NULL,
+                               &mFdtReadyToBootEvent
+                               );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  FdtReadyToBoot
+ *
+ *  Description:
+ *  Ready-2-Boot Event Callback for EFI_EVENT_SIGNAL_READY_TO_BOOT.
+ *
+ *  Control flow:
+ *    1. Read FDT blob
+ *    2. Edit FDT table
+ *    3. Submit FDT to EFI system table
+ *
+ *  Parameters:
+ *    @param[in]      Event                EFI_EVENT notification.
+ *    @param[in]      *Context             Pointer to the Event Context.
+ *
+ *    @return         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+EFIAPI
+FdtReadyToBoot (
+  IN      EFI_EVENT      Event,
+  IN      VOID           *Context
+  )
+{
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         HandleCount;
+  UINTN                         Index;
+  EFI_STATUS                    Status;
+  UINT32                        AuthenticationStatus;
+  EFI_GUID                      *FdtGuid = FixedPcdGetPtr(PcdStyxFdt);
+  UINT8                         *FdtBlobBase = NULL;
+  UINTN                         FdtBlobSize = 0;
+  EFI_DEVICE_PATH               *FdtDevicePath;
+
+  // Search for FDT blob in EFI partition
+  Status = FdtOverrideDevicePath(L"fdt.dtb", &FdtDevicePath);
+  if (!EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "%a: Loading Override FDT blob...\n", __FUNCTION__));
+
+    FdtBlobBase = (UINT8 *)(UINTN)LINUX_FDT_MAX_OFFSET;
+    Status = BdsLoadImage (FdtDevicePath,
+                           AllocateMaxAddress,
+                           (EFI_PHYSICAL_ADDRESS *)&FdtBlobBase,
+                           &FdtBlobSize);
+    if (!EFI_ERROR (Status) && FdtBlobBase && FdtBlobSize)
+      goto LOAD_FDT_BLOB;
+    else
+      goto LOAD_FDT_ERROR;
+  }
+
+  DEBUG ((EFI_D_ERROR, "%a: Loading Embedded FDT blob...\n", __FUNCTION__));
+  HandleBuffer = NULL;
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiFirmwareVolume2ProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  for (Index = 0; Index < HandleCount; Index++) {
+    Status = gBS->HandleProtocol (
+                  HandleBuffer[Index],
+                  &gEfiFirmwareVolume2ProtocolGuid,
+                  (VOID **) &FvProtocol
+                  );
+    if (!EFI_ERROR (Status)) {
+      Status = FvProtocol->ReadSection (
+                            FvProtocol,
+                            FdtGuid,
+                            EFI_SECTION_RAW,
+                            0,
+                            (VOID **)&FdtBlobBase,
+                            &FdtBlobSize,
+                            &AuthenticationStatus
+                            );
+      if (!EFI_ERROR (Status) && FdtBlobBase && FdtBlobSize)
+        goto LOAD_FDT_BLOB;
+    }
+  }
+
+LOAD_FDT_ERROR:
+  DEBUG ((EFI_D_ERROR, "%a: Error loading FDT blob!\n", __FUNCTION__));
+  goto LOAD_FDT_DONE;
+
+LOAD_FDT_BLOB:
+  Status = AmdStyxPrepareFdt(NULL, 0, 0, (EFI_PHYSICAL_ADDRESS *)&FdtBlobBase, &FdtBlobSize);
+  ASSERT_EFI_ERROR (Status);
+
+  // Install the FDT blob into EFI system configuration table
+  Status = gBS->InstallConfigurationTable (&gFdtTableGuid, (VOID *)FdtBlobBase);
+  ASSERT_EFI_ERROR (Status);
+  DEBUG ((EFI_D_ERROR, "%a: FDT ready!\n", __FUNCTION__));
+
+LOAD_FDT_DONE:
+  gBS->CloseEvent (mFdtReadyToBootEvent);
+  return;
+}
+
+/**
+*---------------------------------------------------------------------------------------
+*
+*  FdtOverrideDevicePath
+*
+*  Description:
+*    Looks for a user-provided FDT blob to override the default file built with the UEFI image.
+*
+*  Parameters:
+*    @param[in]      FdtFileName       Name of the FDT blob located in the EFI partition.
+*    @param[out]     FdtDevicePath     EFI Device Path of the FDT blob.
+*
+*    @return EFI_SUCCESS           The function completed successfully.
+*    @return EFI_NOT_FOUND         The protocol could not be located.
+*    @return EFI_OUT_OF_RESOURCES  There are not enough resources to find the protocol.
+*
+*---------------------------------------------------------------------------------------
+**/
+EFI_STATUS
+EFIAPI
+FdtOverrideDevicePath(
+  IN CHAR16 *FdtFileName,
+  OUT EFI_DEVICE_PATH **FdtDevicePath
+  )
+{
+  EFI_DEVICE_PATH_PROTOCOL        *DevPathProtocol;
+  EFI_HANDLE                      *HandleBuffer;
+  UINTN                           HandleCount;
+  UINTN                           Index;
+  EFI_STATUS                      Status;
+  CHAR16                          *DevPathText;
+  EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *VolProtocol;
+  EFI_FILE_PROTOCOL               *FileProtocol;
+  EFI_FILE_PROTOCOL               *FileHandle;
+  CHAR16                          FilePathText[120];
+
+  HandleBuffer = NULL;
+  Status = gBS->LocateHandleBuffer (
+                ByProtocol,
+                &gEfiSimpleFileSystemProtocolGuid,
+                NULL,
+                &HandleCount,
+                &HandleBuffer);
+  if (EFI_ERROR (Status))
+    return Status;
+
+  for (Index = 0; Index < HandleCount; Index++) {
+    DevPathProtocol = NULL;
+    Status = gBS->HandleProtocol (
+                  HandleBuffer[Index],
+                  &gEfiDevicePathProtocolGuid,
+                  (VOID **) &DevPathProtocol);
+
+    if (!EFI_ERROR (Status)) {
+      VolProtocol = NULL;
+      Status = gBS->HandleProtocol (
+                    HandleBuffer[Index],
+                    &gEfiSimpleFileSystemProtocolGuid,
+                    (VOID **) &VolProtocol);
+
+      if (!EFI_ERROR (Status)) {
+        FileProtocol = NULL;
+        Status = VolProtocol->OpenVolume(VolProtocol, &FileProtocol);
+
+        if (!EFI_ERROR (Status)) {
+          FileHandle = NULL;
+          Status = FileProtocol->Open(FileProtocol,
+                                      &FileHandle,
+                                      FdtFileName,
+                                      EFI_FILE_MODE_READ,
+                                      0);
+
+          if (!EFI_ERROR (Status)) {
+            FileProtocol->Close(FileHandle);
+            DevPathText = ConvertDevicePathToText(DevPathProtocol, TRUE, FALSE);
+            StrCpy(FilePathText, DevPathText);
+            StrCat(FilePathText, L"/");
+            StrCat(FilePathText, FdtFileName);
+            *FdtDevicePath = ConvertTextToDevicePath (FilePathText);
+            return EFI_SUCCESS;
+          }
+        }
+      }
+    }
+  }
+
+  return Status;
+}
+
diff --git a/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.h b/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.h
new file mode 100644
index 0000000..c61b7ec
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.h
@@ -0,0 +1,54 @@
+/** @file
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __FDT_DXE__H_
+#define __FDT_DXE__H_
+
+#include <Uefi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BdsLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Guid/DxeServices.h>
+#include <Library/DxeServicesTableLib.h>
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/LoadFile.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/DevicePathFromText.h>
+
+#define LINUX_FDT_MAX_OFFSET      (PcdGet64 (PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset))
+
+VOID
+EFIAPI
+AmdStyxParkSecondaryCores(
+  VOID
+  );
+
+EFI_STATUS
+AmdStyxPrepareFdt (
+  IN     CONST CHAR8*         CommandLineArguments,
+  IN     EFI_PHYSICAL_ADDRESS InitrdImage,
+  IN     UINTN                InitrdImageSize,
+  IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
+  IN OUT UINTN                *FdtBlobSize
+  );
+
+
+#endif // __FDT_DXE__H_
diff --git a/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf b/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf
new file mode 100644
index 0000000..5479c7b
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf
@@ -0,0 +1,76 @@
+#/* @file
+#
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = FdtDxe
+  FILE_GUID                      = 17f50855-6484-4b56-814b-1a88702d88e1
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = FdtDxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+#
+
+[Sources.common]
+  FdtDxe.c
+  BdsLinuxFdt.c
+  LinuxLoaderHelper.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+  ShellPkg/ShellPkg.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  DxeServicesTableLib
+  BdsLib
+  FdtLib
+  PcdLib
+  DevicePathLib
+
+[Guids]
+  gEfiEventReadyToBootGuid           ## CONSUMED
+  gEfiDxeServicesTableGuid           ## CONSUMED
+  gFdtTableGuid                      ## CONSUMED
+
+[Protocols]
+  gEfiFirmwareVolume2ProtocolGuid    ## CONSUMED
+  gAmdMpCoreInfoProtocolGuid         ## CONSUMED
+
+[Pcd]
+  gAmdStyxTokenSpaceGuid.PcdStyxFdt
+  gAmdStyxTokenSpaceGuid.PcdSocCpuId
+  gAmdStyxTokenSpaceGuid.PcdEthMacA
+  gAmdStyxTokenSpaceGuid.PcdEthMacB
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset
+  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+  gAmdStyxTokenSpaceGuid.PcdSata1PortCount
+
+[Depex]
+  TRUE
diff --git a/Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoader.h b/Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoader.h
new file mode 100644
index 0000000..ff6c72c
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoader.h
@@ -0,0 +1,173 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+
+  Derived from:
+   ArmPkg/Library/BdsLib/LinuxLoader.h
+
+**/
+
+#ifndef __LINUX_LOADER_H__
+#define __LINUX_LOADER_H__
+
+#include <Library/BdsLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HiiLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/PrintLib.h>
+#include <Library/ShellLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/EfiShellParameters.h>
+#include <Protocol/EfiShell.h>
+
+#include <libfdt.h>
+
+//
+// Definitions
+//
+
+#define MAX_MSG_LEN 80
+
+#define LINUX_UIMAGE_SIGNATURE    0x56190527
+#define LINUX_KERNEL_MAX_OFFSET   (SystemMemoryBase + PcdGet32(PcdArmLinuxKernelMaxOffset))
+#define LINUX_ATAG_MAX_OFFSET     (SystemMemoryBase + PcdGet32(PcdArmLinuxAtagMaxOffset))
+#define LINUX_FDT_MAX_OFFSET      (SystemMemoryBase + PcdGet32(PcdArmLinuxFdtMaxOffset))
+
+#define ARM_FDT_MACHINE_TYPE      0xFFFFFFFF
+
+// Additional size that could be used for FDT entries added by the UEFI OS Loader
+// Estimation based on: EDID (300bytes) + bootargs (200bytes) + initrd region (20bytes)
+//                      + system memory region (20bytes) + mp_core entries (200 bytes)
+#define FDT_ADDITIONAL_ENTRIES_SIZE     0x300
+
+//
+// Global variables
+//
+extern CONST EFI_GUID mLinuxLoaderHiiGuid;
+extern EFI_HANDLE mLinuxLoaderHiiHandle;
+
+//
+// Local Types
+//
+typedef struct _SYSTEM_MEMORY_RESOURCE {
+  LIST_ENTRY                  Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
+  EFI_PHYSICAL_ADDRESS        PhysicalStart;
+  UINT64                      ResourceLength;
+} SYSTEM_MEMORY_RESOURCE;
+
+typedef VOID (*LINUX_KERNEL)(UINT32 Zero, UINT32 Arch, UINTN ParametersBase);
+
+//
+// Functions
+//
+EFI_STATUS
+PrintHii (
+  IN CONST CHAR8          *Language OPTIONAL,
+  IN CONST EFI_STRING_ID  HiiFormatStringId,
+  ...
+  );
+
+VOID
+PrintHelp (
+  IN CONST CHAR8  *Language OPTIONAL
+  );
+
+EFI_STATUS
+ProcessShellParameters (
+  OUT  CHAR16   **KernelPath,
+  OUT  CHAR16   **FdtPath,
+  OUT  CHAR16   **InitrdPath,
+  OUT  CHAR16   **LinuxCommandLine,
+  OUT  UINTN    *AtagMachineType
+  );
+
+EFI_STATUS
+ProcessAppCommandLine (
+  OUT  CHAR16   **KernelTextDevicePath,
+  OUT  CHAR16   **FdtTextDevicePath,
+  OUT  CHAR16   **InitrdTextDevicePath,
+  OUT  CHAR16   **LinuxCommandLine,
+  OUT  UINTN    *AtagMachineType
+  );
+
+VOID
+PrintPerformance (
+  VOID
+  );
+
+EFI_STATUS
+GetSystemMemoryResources (
+  IN  LIST_ENTRY *ResourceList
+  );
+
+EFI_STATUS
+PrepareFdt (
+  IN     EFI_PHYSICAL_ADDRESS SystemMemoryBase,
+  IN     CONST CHAR8*         CommandLineArguments,
+  IN     EFI_PHYSICAL_ADDRESS InitrdImage,
+  IN     UINTN                InitrdImageSize,
+  IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
+  IN OUT UINTN                *FdtBlobSize
+  );
+
+/**
+  Start a Linux kernel from a Device Path
+
+  @param  SystemMemoryBase      Base of the system memory
+  @param  LinuxKernel           Device Path to the Linux Kernel
+  @param  Parameters            Linux kernel arguments
+  @param  Fdt                   Device Path to the Flat Device Tree
+  @param  MachineType           ARM machine type value
+
+  @retval EFI_SUCCESS           All drivers have been connected
+  @retval EFI_NOT_FOUND         The Linux kernel Device Path has not been found
+  @retval EFI_OUT_OF_RESOURCES  There is not enough resource memory to store the matching results.
+  @retval RETURN_UNSUPPORTED    ATAG is not support by this architecture
+
+**/
+EFI_STATUS
+BootLinuxAtag (
+  IN  EFI_PHYSICAL_ADDRESS      SystemMemoryBase,
+  IN  EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath,
+  IN  EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath,
+  IN  CONST CHAR8*              CommandLineArguments,
+  IN  UINTN                     MachineType
+  );
+
+/**
+  Start a Linux kernel from a Device Path
+
+  @param[in]  LinuxKernelDevicePath  Device Path to the Linux Kernel
+  @param[in]  InitrdDevicePath       Device Path to the Initrd
+  @param[in]  Arguments              Linux kernel arguments
+
+  @retval EFI_SUCCESS           All drivers have been connected
+  @retval EFI_NOT_FOUND         The Linux kernel Device Path has not been found
+  @retval EFI_OUT_OF_RESOURCES  There is not enough resource memory to store the matching results.
+
+**/
+EFI_STATUS
+BootLinuxFdt (
+  IN  EFI_PHYSICAL_ADDRESS      SystemMemoryBase,
+  IN  EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath,
+  IN  EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath,
+  IN  EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath,
+  IN  CONST CHAR8*              Arguments
+  );
+
+#endif /* __LINUX_LOADER_H__ */
diff --git a/Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoaderHelper.c b/Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoaderHelper.c
new file mode 100644
index 0000000..80dce8d
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoaderHelper.c
@@ -0,0 +1,200 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+
+  Derived from:
+   ArmPkg/Application/LinuxLoader/LinuxLoaderHelper.c
+
+**/
+
+
+#include <PiDxe.h>
+#include <Library/HobLib.h>
+#include <Library/TimerLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "LinuxLoader.h"
+
+STATIC CONST CHAR8 *mTokenList[] = {
+  /*"SEC",*/
+  "PEI",
+  "DXE",
+  "BDS",
+  NULL
+};
+
+VOID
+PrintPerformance (
+  VOID
+  )
+{
+  UINTN       Key;
+  CONST VOID  *Handle;
+  CONST CHAR8 *Token, *Module;
+  UINT64      Start, Stop, TimeStamp;
+  UINT64      Delta, TicksPerSecond, Milliseconds;
+  UINTN       Index;
+  CHAR8       Buffer[100];
+  UINTN       CharCount;
+  BOOLEAN     CountUp;
+
+  TicksPerSecond = GetPerformanceCounterProperties (&Start, &Stop);
+  if (Start < Stop) {
+    CountUp = TRUE;
+  } else {
+    CountUp = FALSE;
+  }
+
+  TimeStamp = 0;
+  Key       = 0;
+  do {
+    Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop);
+    if (Key != 0) {
+      for (Index = 0; mTokenList[Index] != NULL; Index++) {
+        if (AsciiStriCmp (mTokenList[Index], Token) == 0) {
+          Delta = CountUp ? (Stop - Start) : (Start - Stop);
+          TimeStamp += Delta;
+          Milliseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000), TicksPerSecond, NULL);
+          CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "%6a %6ld ms\n", Token, Milliseconds);
+          SerialPortWrite ((UINT8 *) Buffer, CharCount);
+          break;
+        }
+      }
+    }
+  } while (Key != 0);
+
+  CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Total Time = %ld ms\n\n",
+      DivU64x64Remainder (MultU64x32 (TimeStamp, 1000), TicksPerSecond, NULL));
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);
+}
+
+STATIC
+EFI_STATUS
+InsertSystemMemoryResources (
+  LIST_ENTRY *ResourceList,
+  EFI_HOB_RESOURCE_DESCRIPTOR *ResHob
+  )
+{
+  SYSTEM_MEMORY_RESOURCE  *NewResource;
+  LIST_ENTRY              *Link;
+  LIST_ENTRY              *NextLink;
+  LIST_ENTRY              AttachedResources;
+  SYSTEM_MEMORY_RESOURCE  *Resource;
+  EFI_PHYSICAL_ADDRESS    NewResourceEnd;
+
+  if (IsListEmpty (ResourceList)) {
+    NewResource = AllocateZeroPool (sizeof (SYSTEM_MEMORY_RESOURCE));
+    NewResource->PhysicalStart = ResHob->PhysicalStart;
+    NewResource->ResourceLength = ResHob->ResourceLength;
+    InsertTailList (ResourceList, &NewResource->Link);
+    return EFI_SUCCESS;
+  }
+
+  InitializeListHead (&AttachedResources);
+
+  Link = ResourceList->ForwardLink;
+  ASSERT (Link != NULL);
+  while (Link != ResourceList) {
+    Resource = (SYSTEM_MEMORY_RESOURCE*)Link;
+
+    // Sanity Check. The resources should not overlapped.
+    ASSERT (!((ResHob->PhysicalStart >= Resource->PhysicalStart) && (ResHob->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))));
+    ASSERT (!((ResHob->PhysicalStart + ResHob->ResourceLength - 1 >= Resource->PhysicalStart) &&
+        ((ResHob->PhysicalStart + ResHob->ResourceLength - 1) < (Resource->PhysicalStart + Resource->ResourceLength))));
+
+    // The new resource is attached after this resource descriptor
+    if (ResHob->PhysicalStart == Resource->PhysicalStart + Resource->ResourceLength) {
+      Resource->ResourceLength =  Resource->ResourceLength + ResHob->ResourceLength;
+
+      NextLink = RemoveEntryList (&Resource->Link);
+      InsertTailList (&AttachedResources, &Resource->Link);
+      Link = NextLink;
+    }
+    // The new resource is attached before this resource descriptor
+    else if (ResHob->PhysicalStart + ResHob->ResourceLength == Resource->PhysicalStart) {
+      Resource->PhysicalStart = ResHob->PhysicalStart;
+      Resource->ResourceLength =  Resource->ResourceLength + ResHob->ResourceLength;
+
+      NextLink = RemoveEntryList (&Resource->Link);
+      InsertTailList (&AttachedResources, &Resource->Link);
+      Link = NextLink;
+    } else {
+      Link = Link->ForwardLink;
+    }
+  }
+
+  if (!IsListEmpty (&AttachedResources)) {
+    // See if we can merge the attached resource with other resources
+
+    NewResource = (SYSTEM_MEMORY_RESOURCE*)GetFirstNode (&AttachedResources);
+    Link = RemoveEntryList (&NewResource->Link);
+    while (!IsListEmpty (&AttachedResources)) {
+      // Merge resources
+      Resource = (SYSTEM_MEMORY_RESOURCE*)Link;
+
+      // Ensure they overlap each other
+      ASSERT (
+          ((NewResource->PhysicalStart >= Resource->PhysicalStart) && (NewResource->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))) ||
+          (((NewResource->PhysicalStart + NewResource->ResourceLength) >= Resource->PhysicalStart) && ((NewResource->PhysicalStart + NewResource->ResourceLength) < (Resource->PhysicalStart + Resource->ResourceLength)))
+      );
+
+      NewResourceEnd = MAX (NewResource->PhysicalStart + NewResource->ResourceLength, Resource->PhysicalStart + Resource->ResourceLength);
+      NewResource->PhysicalStart = MIN (NewResource->PhysicalStart, Resource->PhysicalStart);
+      NewResource->ResourceLength = NewResourceEnd - NewResource->PhysicalStart;
+
+      Link = RemoveEntryList (Link);
+    }
+  } else {
+    // None of the Resource of the list is attached to this ResHob. Create a new entry for it
+    NewResource = AllocateZeroPool (sizeof (SYSTEM_MEMORY_RESOURCE));
+    NewResource->PhysicalStart = ResHob->PhysicalStart;
+    NewResource->ResourceLength = ResHob->ResourceLength;
+  }
+  InsertTailList (ResourceList, &NewResource->Link);
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GetSystemMemoryResources (
+  IN  LIST_ENTRY *ResourceList
+  )
+{
+  EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
+
+  InitializeListHead (ResourceList);
+
+  // Find the first System Memory Resource Descriptor
+  ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
+  while ((ResHob != NULL) && (ResHob->ResourceType != EFI_RESOURCE_SYSTEM_MEMORY)) {
+    ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
+  }
+
+  // Did not find any
+  if (ResHob == NULL) {
+    return EFI_NOT_FOUND;
+  } else {
+    InsertSystemMemoryResources (ResourceList, ResHob);
+  }
+
+  ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
+  while (ResHob != NULL) {
+    if (ResHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
+      InsertSystemMemoryResources (ResourceList, ResHob);
+    }
+    ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c
new file mode 100644
index 0000000..bd72446
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c
@@ -0,0 +1,170 @@
+/** @file
+
+  Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmSmcLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Guid/ArmMpCoreInfo.h>
+#include <Protocol/AmdMpBoot.h>
+
+
+/* These externs are used to relocate our Pen code into pre-allocated memory */
+extern VOID  *SecondariesPenStart;
+extern VOID  *SecondariesPenEnd;
+extern UINTN *AsmParkingBase;
+extern UINTN *AsmMailboxBase;
+
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+ConfigurePen (
+  IN EFI_PHYSICAL_ADDRESS     MpParkingBase,
+  IN UINTN                    MpParkingSize,
+  IN ARM_CORE_INFO            *ArmCoreInfoTable,
+  IN UINTN                    ArmCoreCount
+  )
+{
+  EFI_PHYSICAL_ADDRESS     PenBase;
+  UINTN                    PenSize;
+  UINTN                    MailboxBase;
+  UINTN                    CoreNum;
+  UINTN                    CoreMailbox;
+  UINTN                    CoreParking;
+
+  //
+  // Set Pen at the 2K-offset of the Parking area, skipping an 8-byte slot for the Core#.
+  // For details, refer to the "Multi-processor Startup for ARM Platforms" document:
+  // https://acpica.org/sites/acpica/files/MP%20Startup%20for%20ARM%20platforms.docx
+  //
+  PenBase = (EFI_PHYSICAL_ADDRESS)((UINTN)MpParkingBase + SIZE_2KB + sizeof(UINT64));
+  PenSize  = (UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart;
+
+  // Relocate the Pen code
+  CopyMem ((VOID*)(PenBase), (VOID*)&SecondariesPenStart, PenSize);
+
+  // Put spin-table mailboxes below the pen code so we know where they are relative to code.
+  // Make sure this is 8 byte aligned.
+  MailboxBase = (UINTN)PenBase + ((UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart);
+  if (MailboxBase % sizeof(UINT64) != 0) {
+    MailboxBase += sizeof(UINT64) - MailboxBase % sizeof(UINT64);
+  }
+
+  // Update variables used in the Pen code
+  *(UINTN*)(PenBase + ((UINTN)&AsmMailboxBase - (UINTN)&SecondariesPenStart)) = MailboxBase;
+  *(UINTN*)(PenBase + ((UINTN)&AsmParkingBase - (UINTN)&SecondariesPenStart)) = (UINTN)MpParkingBase;
+
+  for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) {
+    // Clear the jump address at spin-table slot
+    CoreMailbox = MailboxBase + CoreNum * sizeof (UINT64);
+    *((UINTN*)(CoreMailbox)) = 0x0;
+
+    // Clear the jump address and set Core# at mp-parking slot
+    CoreParking = (UINTN)MpParkingBase + CoreNum * SIZE_4KB;
+    *((UINTN*)(CoreParking + sizeof (UINT64))) = 0x0;
+    *((UINTN*)(CoreParking + SIZE_2KB)) = CoreNum;
+
+    // Update table entry to be consumed by FDT parser
+    ArmCoreInfoTable[CoreNum].MailboxSetAddress = CoreMailbox;
+  }
+
+  // flush the cache before launching secondary cores
+  WriteBackDataCacheRange ((VOID *)MpParkingBase, MpParkingSize);
+
+  return PenBase;
+}
+
+
+EFI_STATUS
+EFIAPI
+MpBootDxeEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS               Status;
+  AMD_MP_BOOT_PROTOCOL     *MpBootProtocol;
+  EFI_PHYSICAL_ADDRESS     MpParkingBase;
+  UINTN                    MpParkingSize;
+  ARM_CORE_INFO            *ArmCoreInfoTable;
+  UINTN                    ArmCoreCount;
+  UINTN                    CoreNum;
+  EFI_PHYSICAL_ADDRESS     PenBase;
+
+  DEBUG ((EFI_D_ERROR, "MpBootDxe Loaded\n"));
+
+  MpBootProtocol = NULL;
+  Status = gBS->LocateProtocol (
+               &gAmdMpBootProtocolGuid,
+               NULL,
+               (VOID **)&MpBootProtocol
+               );
+  if (EFI_ERROR (Status) || MpBootProtocol == NULL) {
+    DEBUG ((EFI_D_ERROR, "Warning: Failed to locate MP-Boot Protocol.\n"));
+    return EFI_UNSUPPORTED;
+  }
+
+  if ((VOID *)MpBootProtocol->MpBootInfo == NULL) {
+    DEBUG ((EFI_D_ERROR, "Warning: MpBootInfo not allocated.\n"));
+    return EFI_UNSUPPORTED;
+  }
+
+  MpParkingBase = MpBootProtocol->MpBootInfo->MpParkingBase;
+  if ((VOID *)MpParkingBase == NULL) {
+    DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not allocated.\n"));
+    return EFI_UNSUPPORTED;
+  }
+  if (((UINTN)MpParkingBase & (SIZE_4KB -1)) != 0) {
+    DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not 4K aligned.\n"));
+    return EFI_UNSUPPORTED;
+  }
+
+  ArmCoreInfoTable = MpBootProtocol->MpBootInfo->ArmCoreInfoTable;
+  if (ArmCoreInfoTable == NULL) {
+    DEBUG ((EFI_D_ERROR, "Warning: ArmCoreInfoTable not allocated.\n"));
+    return EFI_UNSUPPORTED;
+  }
+
+  ArmCoreCount = MpBootProtocol->MpBootInfo->ArmCoreCount;
+  if (ArmCoreCount < 2) {
+    DEBUG ((EFI_D_ERROR, "Warning: Found %d cores.\n", ArmCoreCount));
+    return EFI_UNSUPPORTED;
+  }
+
+  MpParkingSize = ArmCoreCount * SIZE_4KB;
+  if (MpParkingSize > MpBootProtocol->MpBootInfo->MpParkingSize) {
+    DEBUG ((EFI_D_ERROR, "Warning: MpParkingSize = 0x%lX, not large enough for %d cores.\n",
+      MpBootProtocol->MpBootInfo->MpParkingSize, ArmCoreCount));
+    return EFI_UNSUPPORTED;
+  }
+
+  if ((VOID *)MpBootProtocol->ParkSecondaryCore == NULL) {
+    DEBUG ((EFI_D_ERROR, "Warning: ParkSecondaryCore() not supported.\n"));
+    return EFI_UNSUPPORTED;
+  }
+
+  // Move secondary cores to our new Pen
+  PenBase = ConfigurePen (MpParkingBase, MpParkingSize, ArmCoreInfoTable, ArmCoreCount);
+  for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) {
+    MpBootProtocol->ParkSecondaryCore (&ArmCoreInfoTable[CoreNum], PenBase);
+  }
+
+  return EFI_SUCCESS;
+}
+
+
diff --git a/Chips/TexasInstruments/Omap35xx/InterruptDxe/InterruptDxe.inf b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
index 76276dd..ff6ccb6 100644
--- a/Chips/TexasInstruments/Omap35xx/InterruptDxe/InterruptDxe.inf
+++ b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
@@ -1,8 +1,7 @@
-#/** @file
+#/* @file
 #
-#  Interrupt DXE driver
+#  Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
 #
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
@@ -11,44 +10,44 @@
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
-#**/
+#*/
 
 [Defines]
   INF_VERSION                    = 0x00010005
-  BASE_NAME                      = Omap35xxBoardInterruptDxe
-  FILE_GUID                      = 23eed05d-1b93-4a1a-8e1b-931d69e37952
+  BASE_NAME                      = MpBootDxe
+  FILE_GUID                      = ff3f9c9b-6d36-4787-9144-6b22acba5e9b
   MODULE_TYPE                    = DXE_DRIVER
   VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = MpBootDxeEntryPoint
 
-  ENTRY_POINT                    = InterruptDxeInitialize
-
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+#
 
 [Sources.common]
-  HardwareInterrupt.c
+  MpBootDxe.c
 
+[Sources.AARCH64]
+  MpBootHelper.S
 
 [Packages]
   ArmPkg/ArmPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
   MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
 
 [LibraryClasses]
-  BaseLib
-  UefiLib
+  UefiDriverEntryPoint
   UefiBootServicesTableLib
+  CacheMaintenanceLib
+  BaseMemoryLib
   DebugLib
-  PrintLib
-  UefiDriverEntryPoint
-  IoLib
-  ArmLib
 
 [Protocols]
-  gHardwareInterruptProtocolGuid
-  gEfiCpuArchProtocolGuid
-
-[FixedPcd.common]
-  gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress
+  gAmdMpBootProtocolGuid             ## CONSUMED
 
 [Depex]
-  gEfiCpuArchProtocolGuid
+  gAmdMpBootProtocolGuid
diff --git a/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S
new file mode 100644
index 0000000..c16cc59
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S
@@ -0,0 +1,87 @@
+//
+//  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+//  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+//
+//  This program and the accompanying materials
+//  are licensed and made available under the terms and conditions of the BSD License
+//  which accompanies this distribution.  The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//**
+//  Derived from:
+//   ArmPkg/Library/BdsLib/AArch64/BdsLinuxLoaderHelper.S
+//
+//**
+
+/* Secondary core pens for AArch64 Linux booting.
+
+   This code is placed in Linux kernel memory and marked reserved. UEFI ensures
+   that the secondary cores get to this pen and the kernel can then start the
+   cores from here.
+   NOTE: This code must be self-contained.
+*/
+
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(SecondariesPenStart)
+ASM_GLOBAL SecondariesPenEnd
+
+ASM_PFX(SecondariesPenStart):
+   // Registers x0-x3 are reserved for future use and should be set to zero.
+   mov x0, xzr
+   mov x1, xzr
+   mov x2, xzr
+   mov x3, xzr
+
+   mrs x4, mpidr_el1             // Get MPCore register
+   and x5, x4, #ARM_CORE_MASK    // Get core number
+   and x4, x4, #ARM_CLUSTER_MASK // Get cluster number
+
+   add x4, x5, x4, LSR #7        // Add scaled cluster number to core number
+   mov x6, x4                    // Save a copy to compute mp-parking offset
+
+   ldr x5, AsmMailboxBase   // Get mailbox addr relative to PC
+   lsl x4, x4, 3            // Add 8-byte offset for this core
+   add x4, x4, x5           //
+
+   ldr x5, AsmParkingBase   // Get mp-parking addr relative to PC
+   lsl x6, x6, 12           // Add 4K-byte offset for this core
+   add x6, x6, x5           //
+
+   mov x5, 1                // Get mp-parking id# at 2K offset
+   lsl x5, x5, 11           //
+   add x5, x5, x6           //
+   ldr x10, [x5]            //
+
+1: ldr x5, [x4]             // Load jump-addr from spin-table mailbox
+   cmp xzr, x5              // Has the value been set?
+   b.ne 4f                  // If so, break out of loop
+
+   ldr x5, [x6]             // Load mp-parking id#
+   cmp w10, w5              // Is it my id?
+   b.ne 2f                  // If not, continue polling
+
+   ldr x5, [x6, 8]          // Load jump-addr from mp-parking
+   cmp xzr, x5              // Has the value been set?
+   b.ne 3f                  // If so, break out of loop
+
+2: wfe                      // Wait a bit
+   b 1b                     // Wait over, check again
+
+3: str xzr, [x6, 8]         // Clear to acknowledge
+   mov x0, x6               // Return mp-parking address
+4: br x5                    // Jump to new addr
+
+.align 3 // Make sure the variable below is 8 byte aligned.
+                .global     AsmParkingBase
+AsmParkingBase: .xword      0xdeaddeadbeefbeef
+                .global     AsmMailboxBase
+AsmMailboxBase: .xword      0xdeaddeadbeefbeef
+
+SecondariesPenEnd:
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c b/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c
new file mode 100644
index 0000000..fd5bb96
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c
@@ -0,0 +1,237 @@
+/** @file
+
+  Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <PiDxe.h>
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Common/CoreState.h>
+#include <Library/ArmSmcLib.h>
+#include <IndustryStandard/ArmStdSmc.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <Protocol/AmdMpCoreInfo.h>
+#include <Protocol/AmdMpBoot.h>
+
+
+STATIC AMD_MP_CORE_INFO_PROTOCOL  mAmdMpCoreInfoProtocol = { 0 };
+STATIC AMD_MP_BOOT_PROTOCOL       mAmdMpBootProtocol = { 0 };
+STATIC AMD_MP_BOOT_INFO           mAmdMpBootInfo = { 0 };
+
+
+STATIC
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+  OUT UINTN  *NumEntries
+  );
+
+STATIC
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+  IN  UINT32  MpId,
+  OUT UINT32  *PmuSpi
+  );
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+AmdStyxGetMpParkingBase (
+  OUT UINTN  *MpParkingSize
+  );
+
+STATIC
+VOID
+AmdStyxParkSecondaryCore (
+  ARM_CORE_INFO         *ArmCoreInfo,
+  EFI_PHYSICAL_ADDRESS  SecondaryEntry
+  );
+
+
+#pragma pack(push, 1)
+typedef struct _PMU_INFO {
+  UINT32 MpId;
+  UINT32 PmuSpi;
+} PMU_INFO;
+
+STATIC
+PMU_INFO mPmuInfo[] = {
+ {0x000, 7},
+ {0x001, 8},
+ {0x100, 9},
+ {0x101, 10},
+ {0x200, 11},
+ {0x201, 12},
+ {0x300, 13},
+ {0x301, 14}
+};
+#pragma pack(pop)
+
+#define MAX_CPUS   sizeof(mPmuInfo) / sizeof(PMU_INFO)
+
+
+EFI_STATUS
+EFIAPI
+PlatInitDxeEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS                Status;
+  EFI_PHYSICAL_ADDRESS      MpParkingBase;
+  UINTN                     MpParkingSize;
+  ARM_CORE_INFO             *ArmCoreInfoTable;
+  UINTN                     ArmCoreCount;
+  EFI_HANDLE                Handle = NULL;
+
+  DEBUG ((EFI_D_ERROR, "PlatInitDxe Loaded\n"));
+
+  // Get core information
+  ArmCoreCount = 0;
+  ArmCoreInfoTable = AmdStyxGetArmCoreInfoTable (&ArmCoreCount);
+  ASSERT (ArmCoreInfoTable != NULL);
+  ASSERT (ArmCoreCount != 0);
+
+  // Install CoreInfo Protocol
+  mAmdMpCoreInfoProtocol.GetArmCoreInfoTable = AmdStyxGetArmCoreInfoTable;
+  mAmdMpCoreInfoProtocol.GetPmuSpiFromMpId = AmdStyxGetPmuSpiFromMpId;
+  mAmdMpCoreInfoProtocol.GetMpParkingBase = AmdStyxGetMpParkingBase;
+  Status = gBS->InstallProtocolInterface (
+                  &Handle,
+                  &gAmdMpCoreInfoProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  (VOID *)&mAmdMpCoreInfoProtocol
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  // Install MP-Boot Protocol
+  if (!FixedPcdGetBool (PcdPsciOsSupport) &&
+      FixedPcdGetBool (PcdTrustedFWSupport)) {
+    // Allocate Parking area (4KB-aligned, 4KB per core) as Reserved memory
+    MpParkingBase = 0;
+    MpParkingSize = ArmCoreCount * SIZE_4KB;
+    Status = gBS->AllocatePages (AllocateAnyPages, EfiReservedMemoryType,
+                    EFI_SIZE_TO_PAGES (MpParkingSize),
+                    &MpParkingBase);
+    if (EFI_ERROR (Status) || MpParkingBase == 0) {
+      DEBUG ((EFI_D_ERROR, "Warning: Failed to allocate MpParkingBase."));
+    } else {
+      mAmdMpBootInfo.MpParkingBase = MpParkingBase;
+      mAmdMpBootInfo.MpParkingSize = MpParkingSize;
+      mAmdMpBootInfo.ArmCoreInfoTable = ArmCoreInfoTable;
+      mAmdMpBootInfo.ArmCoreCount = ArmCoreCount;
+
+      mAmdMpBootProtocol.ParkSecondaryCore = AmdStyxParkSecondaryCore;
+      mAmdMpBootProtocol.MpBootInfo = &mAmdMpBootInfo;
+
+      Status = gBS->InstallProtocolInterface (
+                      &Handle,
+                      &gAmdMpBootProtocolGuid,
+                      EFI_NATIVE_INTERFACE,
+                      (VOID *)&mAmdMpBootProtocol
+                      );
+      if (EFI_ERROR (Status)) {
+        DEBUG ((EFI_D_ERROR, "Warning: Failed to install MP-Boot Protocol."));
+        gBS->FreePages (MpParkingBase, EFI_SIZE_TO_PAGES (MpParkingSize));
+      }
+    }
+  }
+
+  return Status;
+}
+
+
+STATIC
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+  OUT UINTN  *NumEntries
+  )
+{
+  EFI_HOB_GUID_TYPE   *Hob;
+
+  ASSERT (NumEntries != NULL);
+
+  Hob = GetFirstGuidHob (&gAmdStyxMpCoreInfoGuid);
+  if (Hob == NULL) {
+    return NULL;
+  }
+
+  *NumEntries = GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (ARM_CORE_INFO);
+  return GET_GUID_HOB_DATA (Hob);
+}
+
+
+STATIC
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+  IN  UINT32  MpId,
+  OUT UINT32  *PmuSpi
+  )
+{
+  UINT32 i;
+
+  for (i = 0; i < MAX_CPUS; ++i) {
+    if (mPmuInfo[ i ].MpId == MpId) {
+      *PmuSpi = mPmuInfo[ i ].PmuSpi;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+AmdStyxGetMpParkingBase (
+  OUT UINTN  *MpParkingSize
+  )
+{
+  ASSERT (MpParkingSize != NULL);
+
+  *MpParkingSize = mAmdMpBootInfo.MpParkingBase;
+  return mAmdMpBootInfo.MpParkingBase;
+}
+
+
+STATIC
+VOID
+AmdStyxParkSecondaryCore (
+  ARM_CORE_INFO         *ArmCoreInfo,
+  EFI_PHYSICAL_ADDRESS  SecondaryEntry
+  )
+{
+  ARM_SMC_ARGS  SmcRegs = {0};
+  UINTN         MpId;
+
+  MpId = GET_MPID (ArmCoreInfo->ClusterId, ArmCoreInfo->CoreId);
+
+  SmcRegs.Arg0 = ARM_SMC_ID_PSCI_CPU_ON_AARCH64;
+  SmcRegs.Arg1 = MpId;
+  SmcRegs.Arg2 = SecondaryEntry;
+  SmcRegs.Arg3 = FixedPcdGet64 (PcdPsciCpuOnContext);
+  ArmCallSmc (&SmcRegs);
+
+  if (SmcRegs.Arg0 == ARM_SMC_PSCI_RET_SUCCESS ||
+      SmcRegs.Arg0 == ARM_SMC_PSCI_RET_ALREADY_ON) {
+    DEBUG ((EFI_D_ERROR, "CPU[MpId] = 0x%X at RUN state.\n", MpId));
+  } else {
+    DEBUG ((EFI_D_ERROR, "Warning: Could not transition CPU[MpId] = 0x%X to RUN state.\n", MpId));
+  }
+}
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf b/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
new file mode 100644
index 0000000..2eb77cd
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
@@ -0,0 +1,62 @@
+#/* @file
+#
+#  Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatInitDxe
+  FILE_GUID                      = 6ae8bdbc-c0eb-40c5-9b3e-18119c0e2710
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = PlatInitDxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+#
+
+[Sources.common]
+  PlatInitDxe.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  BaseMemoryLib
+  ArmSmcLib
+  HobLib
+  PcdLib
+  DebugLib
+
+[Guids]
+  gAmdStyxMpCoreInfoGuid
+
+[Protocols]
+  gAmdMpCoreInfoProtocolGuid         ## PRODUCER
+  gAmdMpBootProtocolGuid             ## PRODUCER
+
+[FixedPcd]
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+  gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+
+[Depex]
+  TRUE
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c
new file mode 100644
index 0000000..61e3734
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c
@@ -0,0 +1,256 @@
+/** @file
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/ArmLib.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <Ppi/IscpPpi.h>
+#include <Iscp.h>
+
+/*----------------------------------------------------------------------------------------
+ *                                  G L O B A L S
+ *----------------------------------------------------------------------------------------
+ */
+//
+// CoreInfo table
+//
+STATIC ARM_CORE_INFO mAmdMpCoreInfoTable[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+  },
+  {
+    // Cluster 1, Core 0
+    0x1, 0x0,
+  },
+  {
+    // Cluster 1, Core 1
+    0x1, 0x1,
+  },
+  {
+    // Cluster 2, Core 0
+    0x2, 0x0,
+  },
+  {
+    // Cluster 2, Core 1
+    0x2, 0x1,
+  },
+  {
+    // Cluster 3, Core 0
+    0x3, 0x0,
+  },
+  {
+    // Cluster 3, Core 1
+    0x3, 0x1,
+  }
+};
+
+//
+// Core count
+//
+STATIC UINTN mAmdCoreCount = sizeof (mAmdMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
+
+
+/*----------------------------------------------------------------------------------------
+ *                                   P P I   L I S T
+ *----------------------------------------------------------------------------------------
+ */
+STATIC EFI_PEI_ISCP_PPI            *PeiIscpPpi;
+
+
+/*----------------------------------------------------------------------------------------
+ *                            P P I   D E S C R I P T O R
+ *----------------------------------------------------------------------------------------
+ */
+STATIC EFI_PEI_PPI_DESCRIPTOR mPlatInitPpiDescriptor =
+{
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gAmdStyxPlatInitPpiGuid,
+  NULL
+};
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *  PlatInitPeiEntryPoint
+ *
+ *  Description:
+ *    Entry point of the PlatInit PEI module.
+ *
+ *  Control flow:
+ *    Query platform parameters via ISCP.
+ *
+ *  Parameters:
+ *    @param[in]      FfsHeader            EFI_PEI_FILE_HANDLE
+ *    @param[in]      **PeiServices        Pointer to the PEI Services Table.
+ *
+ *    @return         EFI_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+EFI_STATUS
+EFIAPI
+PlatInitPeiEntryPoint (
+  IN       EFI_PEI_FILE_HANDLE      FfsHeader,
+  IN       CONST EFI_PEI_SERVICES   **PeiServices
+  )
+{
+  EFI_STATUS                  Status = EFI_SUCCESS;
+  AMD_MEMORY_RANGE_DESCRIPTOR IscpMemDescriptor = {0};
+  ISCP_FUSE_INFO              IscpFuseInfo = {0};
+  ISCP_CPU_RESET_INFO         CpuResetInfo = {0};
+#if DO_XGBE == 1
+  ISCP_MAC_INFO               MacAddrInfo = {0};
+  UINT64                      MacAddr0, MacAddr1;
+#endif
+  UINTN                       CpuCoreCount, CpuMap, CpuMapSize;
+  UINTN                       Index, CoreNum;
+  UINT32                      *CpuIdReg = (UINT32 *)FixedPcdGet32 (PcdCpuIdRegister);
+
+  DEBUG ((EFI_D_ERROR, "PlatInit PEIM Loaded\n"));
+
+  // CPUID
+  PcdSet32 (PcdSocCpuId, *CpuIdReg);
+  DEBUG ((EFI_D_ERROR, "SocCpuId = 0x%X\n", PcdGet32 (PcdSocCpuId)));
+
+  // Update core count based on PCD option
+  if (mAmdCoreCount > PcdGet32 (PcdSocCoreCount)) {
+    mAmdCoreCount = PcdGet32 (PcdSocCoreCount);
+  }
+
+  if (FixedPcdGetBool (PcdIscpSupport)) {
+    Status = PeiServicesLocatePpi (&gPeiIscpPpiGuid, 0, NULL, (VOID**)&PeiIscpPpi);
+    ASSERT_EFI_ERROR (Status);
+
+    // Get fuse information from ISCP
+    Status = PeiIscpPpi->ExecuteFuseTransaction (PeiServices, &IscpFuseInfo);
+    ASSERT_EFI_ERROR (Status);
+
+    CpuMap = IscpFuseInfo.SocConfiguration.CpuMap;
+    CpuCoreCount = IscpFuseInfo.SocConfiguration.CpuCoreCount;
+    CpuMapSize = sizeof (IscpFuseInfo.SocConfiguration.CpuMap) * 8;
+
+    ASSERT (CpuMap != 0);
+    ASSERT (CpuCoreCount != 0);
+    ASSERT (CpuCoreCount <= CpuMapSize);
+
+    // Update core count based on fusing
+    if (mAmdCoreCount > CpuCoreCount) {
+      mAmdCoreCount = CpuCoreCount;
+    }
+  }
+
+  //
+  // Update per-core information from ISCP
+  //
+  if (!FixedPcdGetBool (PcdIscpSupport)) {
+    DEBUG ((EFI_D_ERROR, "Warning: Could not get CPU info via ISCP, using default values.\n"));
+  } else {
+    //
+    // Walk CPU map to enumerate active cores
+    //
+    for (CoreNum = 0, Index = 0; CoreNum < CpuMapSize && Index < mAmdCoreCount; ++CoreNum) {
+      if (CpuMap & 1) {
+        CpuResetInfo.CoreNum = CoreNum;
+        Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction (
+                   PeiServices, &CpuResetInfo );
+        ASSERT_EFI_ERROR (Status);
+        ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED);
+        ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED);
+
+        mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId;
+        mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId;
+
+        DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d   CoreId = %d\n",
+          Index, mAmdMpCoreInfoTable[Index].ClusterId,
+          mAmdMpCoreInfoTable[Index].CoreId));
+
+        // Next core in Table
+        ++Index;
+      }
+      // Next core in Map
+      CpuMap >>= 1;
+    }
+
+    // Update core count based on CPU map
+    if (mAmdCoreCount > Index) {
+      mAmdCoreCount = Index;
+    }
+  }
+
+  // Update SocCoreCount on Dynamic PCD
+  if (PcdGet32 (PcdSocCoreCount) != mAmdCoreCount) {
+    PcdSet32 (PcdSocCoreCount, mAmdCoreCount);
+  }
+
+  DEBUG ((EFI_D_ERROR, "SocCoreCount = %d\n", PcdGet32 (PcdSocCoreCount)));
+
+  // Build AmdMpCoreInfo HOB
+  BuildGuidDataHob (&gAmdStyxMpCoreInfoGuid, mAmdMpCoreInfoTable, sizeof (ARM_CORE_INFO) * mAmdCoreCount);
+
+  // Get SystemMemorySize from ISCP
+  IscpMemDescriptor.Size0 = 0;
+  if (FixedPcdGetBool (PcdIscpSupport)) {
+    Status = PeiIscpPpi->ExecuteMemoryTransaction (PeiServices, &IscpMemDescriptor);
+    ASSERT_EFI_ERROR (Status);
+
+    // Update SystemMemorySize on Dynamic PCD
+    if (IscpMemDescriptor.Size0) {
+      PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0);
+    }
+  }
+  if (IscpMemDescriptor.Size0 == 0) {
+    DEBUG ((EFI_D_ERROR, "Warning: Could not get SystemMemorySize via ISCP, using default value.\n"));
+  }
+
+  DEBUG ((EFI_D_ERROR, "SystemMemorySize = %ld\n", PcdGet64 (PcdSystemMemorySize)));
+
+#if DO_XGBE == 1
+  // Get MAC Address from ISCP
+  if (FixedPcdGetBool (PcdIscpSupport)) {
+    Status = PeiIscpPpi->ExecuteGetMacAddressTransaction (
+               PeiServices, &MacAddrInfo );
+    ASSERT_EFI_ERROR (Status);
+
+    MacAddr0 = MacAddr1 = 0;
+    for (Index = 0; Index < 6; ++Index) {
+      MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8);
+      MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8);
+    }
+    PcdSet64 (PcdEthMacA, MacAddr0);
+    PcdSet64 (PcdEthMacB, MacAddr1);
+  }
+
+  DEBUG ((EFI_D_ERROR, "EthMacA = 0x%lX\n", PcdGet64 (PcdEthMacA)));
+  DEBUG ((EFI_D_ERROR, "EthMacB = 0x%lX\n", PcdGet64 (PcdEthMacB)));
+#endif
+
+  // Let other PEI modules know we're done!
+  Status = (*PeiServices)->InstallPpi (PeiServices, &mPlatInitPpiDescriptor);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
new file mode 100644
index 0000000..8084fbd
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
@@ -0,0 +1,76 @@
+#/* @file
+#
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatInitPei
+  FILE_GUID                      = 769694a4-2572-4f29-a5bb-33d7df7be001
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = PlatInitPeiEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+#
+
+[Sources]
+  PlatInitPei.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  PeimEntryPoint
+  PeiServicesLib
+  PeiServicesTablePointerLib
+  BaseMemoryLib
+  HobLib
+  PcdLib
+  DebugLib
+  ArmLib
+  ArmSmcLib
+
+[Ppis]
+  gPeiIscpPpiGuid                      ## CONSUMER
+  gEfiEndOfPeiSignalPpiGuid            ## CONSUMER
+  gAmdStyxPlatInitPpiGuid              ## PRODUCER
+
+[Guids]
+  gAmdStyxMpCoreInfoGuid               ## PRODUCER
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gAmdStyxTokenSpaceGuid.PcdSocCoreCount
+  gAmdStyxTokenSpaceGuid.PcdSocCpuId
+
+  gAmdStyxTokenSpaceGuid.PcdEthMacA
+  gAmdStyxTokenSpaceGuid.PcdEthMacB
+
+[FixedPcd]
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+  gAmdStyxTokenSpaceGuid.PcdCpuIdRegister
+
+[Depex]
+  gPeiIscpPpiGuid
+
diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c
new file mode 100644
index 0000000..5ee5d92
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c
@@ -0,0 +1,989 @@
+/** @file
+  Static SMBIOS Table for ARM platform
+  Derived from EmulatorPkg package
+
+  Note SMBIOS 2.7.1 Required structures:
+    BIOS Information (Type 0)
+    System Information (Type 1)
+    Board Information (Type 2)
+    System Enclosure (Type 3)
+    Processor Information (Type 4) - CPU Driver
+    Cache Information (Type 7) - For cache that is external to processor
+    System Slots (Type 9) - If system has slots
+    Physical Memory Array (Type 16)
+    Memory Device (Type 17) - For each socketed system-memory Device
+    Memory Array Mapped Address (Type 19) - One per contiguous block per Physical Memroy Array
+    System Boot Information (Type 32)
+
+  Copyright (c) 2012, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2013, Linaro Ltd. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Guid/SmBios.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Protocol/AmdIscpDxeProtocol.h>
+
+/*----------------------------------------------------------------------------------------
+ *                                  E X T E R N S
+ *----------------------------------------------------------------------------------------
+ */
+extern  EFI_BOOT_SERVICES       *gBS;
+
+
+/*----------------------------------------------------------------------------------------
+ *                                  G L O B A L S
+ *----------------------------------------------------------------------------------------
+ */
+EFI_SMBIOS_PROTOCOL   *mSmbiosProtocol;
+AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol;
+ISCP_SMBIOS_INFO      mSmbiosInfo;
+
+
+/***********************************************************************
+        SMBIOS data definition  TYPE0  BIOS Information
+************************************************************************/
+SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = {
+  { EFI_SMBIOS_TYPE_BIOS_INFORMATION, sizeof (SMBIOS_TABLE_TYPE0), 0 },
+  1,                    // Vendor String
+  2,                    // BiosVersion String
+  0xE000,               // BiosSegment
+  3,                    // BiosReleaseDate String
+  0x7F,                 // BiosSize
+  {                     // BiosCharacteristics
+    0,    //  Reserved                          :2;  ///< Bits 0-1.
+    0,    //  Unknown                           :1;
+    0,    //  BiosCharacteristicsNotSupported   :1;
+    0,    //  IsaIsSupported                    :1;
+    0,    //  McaIsSupported                    :1;
+    0,    //  EisaIsSupported                   :1;
+    0,    //  PciIsSupported                    :1;
+    0,    //  PcmciaIsSupported                 :1;
+    0,    //  PlugAndPlayIsSupported            :1;
+    0,    //  ApmIsSupported                    :1;
+    1,    //  BiosIsUpgradable                  :1;
+    1,    //  BiosShadowingAllowed              :1;
+    0,    //  VlVesaIsSupported                 :1;
+    0,    //  EscdSupportIsAvailable            :1;
+    0,    //  BootFromCdIsSupported             :1;
+    1,    //  SelectableBootIsSupported         :1;
+    0,    //  RomBiosIsSocketed                 :1;
+    0,    //  BootFromPcmciaIsSupported         :1;
+    0,    //  EDDSpecificationIsSupported       :1;
+    0,    //  JapaneseNecFloppyIsSupported      :1;
+    0,    //  JapaneseToshibaFloppyIsSupported  :1;
+    0,    //  Floppy525_360IsSupported          :1;
+    0,    //  Floppy525_12IsSupported           :1;
+    0,    //  Floppy35_720IsSupported           :1;
+    0,    //  Floppy35_288IsSupported           :1;
+    0,    //  PrintScreenIsSupported            :1;
+    0,    //  Keyboard8042IsSupported           :1;
+    0,    //  SerialIsSupported                 :1;
+    0,    //  PrinterIsSupported                :1;
+    0,    //  CgaMonoIsSupported                :1;
+    0,    //  NecPc98                           :1;
+    0     //  ReservedForVendor                 :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor
+                                                 ///< and bits 48-63 reserved for System Vendor.
+  },
+  {       // BIOSCharacteristicsExtensionBytes[]
+    0x81, //  AcpiIsSupported                   :1;
+          //  UsbLegacyIsSupported              :1;
+          //  AgpIsSupported                    :1;
+          //  I2OBootIsSupported                :1;
+          //  Ls120BootIsSupported              :1;
+          //  AtapiZipDriveBootIsSupported      :1;
+          //  Boot1394IsSupported               :1;
+          //  SmartBatteryIsSupported           :1;
+                  //  BIOSCharacteristicsExtensionBytes[1]
+    0x0a, //  BiosBootSpecIsSupported              :1;
+          //  FunctionKeyNetworkBootIsSupported    :1;
+          //  TargetContentDistributionEnabled     :1;
+          //  UefiSpecificationSupported           :1;
+          //  VirtualMachineSupported              :1;
+          //  ExtensionByte2Reserved               :3;
+  },
+  0x00,                    // SystemBiosMajorRelease
+  0x01,                    // SystemBiosMinorRelease
+  0xFF,                    // EmbeddedControllerFirmwareMajorRelease
+  0xFF,                    // EmbeddedControllerFirmwareMinorRelease
+};
+
+CHAR8 *mBIOSInfoType0Strings[] = {
+  "edk2.sourceforge.net",  // Vendor String
+  __TIME__,                // BiosVersion String
+  __DATE__,                // BiosReleaseDate String
+  NULL
+};
+
+/***********************************************************************
+        SMBIOS data definition  TYPE1  System Information
+************************************************************************/
+SMBIOS_TABLE_TYPE1 mSysInfoType1 = {
+  { EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, sizeof (SMBIOS_TABLE_TYPE1), 0 },
+  1,    // Manufacturer String
+  2,    // ProductName String
+  3,    // Version String
+  4,    // SerialNumber String
+  { 0x25EF0280, 0xEC82, 0x42B0, { 0x8F, 0xB6, 0x10, 0xAD, 0xCC, 0xC6, 0x7C, 0x02 } },
+  SystemWakeupTypePowerSwitch,
+  5,    // SKUNumber String
+  6,    // Family String
+};
+CHAR8  *mSysInfoType1Strings[] = {
+  "AMD",
+  "Seattle",
+  "1.0",
+  "System Serial#",
+  "System SKU#",
+  "edk2",
+  NULL
+};
+
+/***********************************************************************
+        SMBIOS data definition  TYPE2  Board Information
+************************************************************************/
+SMBIOS_TABLE_TYPE2  mBoardInfoType2 = {
+  { EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, sizeof (SMBIOS_TABLE_TYPE2), 0 },
+  1,    // Manufacturer String
+  2,    // ProductName String
+  3,    // Version String
+  4,    // SerialNumber String
+  5,    // AssetTag String
+  {     // FeatureFlag
+    1,    //  Motherboard           :1;
+    0,    //  RequiresDaughterCard  :1;
+    0,    //  Removable             :1;
+    0,    //  Replaceable           :1;
+    0,    //  HotSwappable          :1;
+    0,    //  Reserved              :3;
+  },
+  6,    // LocationInChassis String
+  0,                        // ChassisHandle;
+  BaseBoardTypeMotherBoard, // BoardType;
+  0,                        // NumberOfContainedObjectHandles;
+  { 0 }                     // ContainedObjectHandles[1];
+};
+CHAR8  *mBoardInfoType2Strings[] = {
+  "AMD",
+  "Seattle",
+  "1.0",
+  "Base Board Serial#",
+  "Base Board Asset Tag#",
+  "Part Component",
+  NULL
+};
+
+/***********************************************************************
+        SMBIOS data definition  TYPE3  Enclosure Information
+************************************************************************/
+SMBIOS_TABLE_TYPE3  mEnclosureInfoType3 = {
+  { EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, sizeof (SMBIOS_TABLE_TYPE3), 0 },
+  1,                        // Manufacturer String
+  MiscChassisTypeLapTop,    // Type;
+  2,                        // Version String
+  3,                        // SerialNumber String
+  4,                        // AssetTag String
+  ChassisStateSafe,         // BootupState;
+  ChassisStateSafe,         // PowerSupplyState;
+  ChassisStateSafe,         // ThermalState;
+  ChassisSecurityStatusNone,// SecurityStatus;
+  { 0, 0, 0, 0 },           // OemDefined[4];
+  0,    // Height;
+  0,    // NumberofPowerCords;
+  0,    // ContainedElementCount;
+  0,    // ContainedElementRecordLength;
+  { { 0 } },    // ContainedElements[1];
+};
+CHAR8  *mEnclosureInfoType3Strings[] = {
+  "AMD",
+  "1.0",
+  "Chassis Board Serial#",
+  "Chassis Board Asset Tag#",
+  NULL
+};
+
+/***********************************************************************
+        SMBIOS data definition  TYPE4  Processor Information
+************************************************************************/
+SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = {
+  { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0},
+  1,                    // Socket String
+  ProcessorOther,       // ProcessorType;                                     ///< The enumeration value from PROCESSOR_TYPE_DATA.
+  ProcessorFamilyIndicatorFamily2, // ProcessorFamily;        ///< The enumeration value from PROCESSOR_FAMILY2_DATA.
+  2,                    // ProcessorManufacture String;
+  {                     // ProcessorId;
+    {  // PROCESSOR_SIGNATURE
+      0, //  ProcessorSteppingId:4;
+      0, //  ProcessorModel:     4;
+      0, //  ProcessorFamily:    4;
+      0, //  ProcessorType:      2;
+      0, //  ProcessorReserved1: 2;
+      0, //  ProcessorXModel:    4;
+      0, //  ProcessorXFamily:   8;
+      0, //  ProcessorReserved2: 4;
+    },
+
+    {  // PROCESSOR_FEATURE_FLAGS
+      0, //  ProcessorFpu       :1;
+      0, //  ProcessorVme       :1;
+      0, //  ProcessorDe        :1;
+      0, //  ProcessorPse       :1;
+      0, //  ProcessorTsc       :1;
+      0, //  ProcessorMsr       :1;
+      0, //  ProcessorPae       :1;
+      0, //  ProcessorMce       :1;
+      0, //  ProcessorCx8       :1;
+      0, //  ProcessorApic      :1;
+      0, //  ProcessorReserved1 :1;
+      0, //  ProcessorSep       :1;
+      0, //  ProcessorMtrr      :1;
+      0, //  ProcessorPge       :1;
+      0, //  ProcessorMca       :1;
+      0, //  ProcessorCmov      :1;
+      0, //  ProcessorPat       :1;
+      0, //  ProcessorPse36     :1;
+      0, //  ProcessorPsn       :1;
+      0, //  ProcessorClfsh     :1;
+      0, //  ProcessorReserved2 :1;
+      0, //  ProcessorDs        :1;
+      0, //  ProcessorAcpi      :1;
+      0, //  ProcessorMmx       :1;
+      0, //  ProcessorFxsr      :1;
+      0, //  ProcessorSse       :1;
+      0, //  ProcessorSse2      :1;
+      0, //  ProcessorSs        :1;
+      0, //  ProcessorReserved3 :1;
+      0, //  ProcessorTm        :1;
+      0, //  ProcessorReserved4 :2;
+    }
+  },
+  3,                    // ProcessorVersion String;
+  {                     // Voltage;
+    1,  // ProcessorVoltageCapability5V        :1;
+    1,  // ProcessorVoltageCapability3_3V      :1;
+    1,  // ProcessorVoltageCapability2_9V      :1;
+    0,  // ProcessorVoltageCapabilityReserved  :1; ///< Bit 3, must be zero.
+    0,  // ProcessorVoltageReserved            :3; ///< Bits 4-6, must be zero.
+    0   // ProcessorVoltageIndicateLegacy      :1;
+  },
+  0,                      // ExternalClock;
+  0,                      // MaxSpeed;
+  0,                      // CurrentSpeed;
+  0x41,                   // Status;
+  ProcessorUpgradeOther,  // ProcessorUpgrade;      ///< The enumeration value from PROCESSOR_UPGRADE.
+  0,                      // L1CacheHandle;
+  0,                      // L2CacheHandle;
+  0,                      // L3CacheHandle;
+  4,                      // SerialNumber;
+  5,                      // AssetTag;
+  6,                      // PartNumber;
+  0,                      // CoreCount;
+  0,                      // EnabledCoreCount;
+  0,                      // ThreadCount;
+  0,                      // ProcessorCharacteristics;
+  ProcessorFamilyARM,     // ARM Processor Family;
+};
+
+CHAR8 *mProcessorInfoType4Strings[] = {
+  "Socket",
+  "ARM",
+#ifdef ARM_CPU_AARCH64
+  "v8",
+#else
+  "v7",
+#endif
+  "1.0",
+  "1.0",
+  "1.0",
+  NULL
+};
+
+/***********************************************************************
+        SMBIOS data definition  TYPE7  Cache Information
+************************************************************************/
+SMBIOS_TABLE_TYPE7  mCacheInfoType7 = {
+  { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 },
+  1,                        // SocketDesignation String
+  0x018A,                                       // Cache Configuration
+  0x00FF,                                       // Maximum Size 256k
+  0x00FF,                                       // Install Size 256k
+  {                         // Supported SRAM Type
+        0,  //Other             :1
+        0,  //Unknown           :1
+        0,  //NonBurst          :1
+        1,  //Burst             :1
+        0,  //PiplelineBurst    :1
+        1,  //Synchronous       :1
+        0,  //Asynchronous      :1
+        0       //Reserved          :9
+  },
+  {                         // Current SRAM Type
+        0,  //Other             :1
+        0,  //Unknown           :1
+        0,  //NonBurst          :1
+        1,  //Burst             :1
+        0,  //PiplelineBurst    :1
+        1,  //Synchronous       :1
+        0,  //Asynchronous      :1
+        0       //Reserved          :9
+  },
+  0,                                            // Cache Speed unknown
+  CacheErrorMultiBit,           // Error Correction Multi
+  CacheTypeUnknown,                     // System Cache Type
+  CacheAssociativity2Way        // Associativity
+};
+#if (FixedPcdGetBool (PcdIscpSupport))
+CHAR8  *mCacheInfoType7Strings[] = {
+  "L# Cache",
+  NULL
+};
+#else
+CHAR8  *mCacheInfoType7Strings[] = {
+  "Cache1",
+  NULL
+};
+#endif
+
+/***********************************************************************
+        SMBIOS data definition  TYPE9  System Slot Information
+************************************************************************/
+SMBIOS_TABLE_TYPE9  mSysSlotInfoType9 = {
+  { EFI_SMBIOS_TYPE_SYSTEM_SLOTS, sizeof (SMBIOS_TABLE_TYPE9), 0 },
+  1,    // SlotDesignation String
+  SlotTypeOther,          // SlotType;                 ///< The enumeration value from MISC_SLOT_TYPE.
+  SlotDataBusWidthOther,  // SlotDataBusWidth;         ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
+  SlotUsageAvailable,    // CurrentUsage;             ///< The enumeration value from MISC_SLOT_USAGE.
+  SlotLengthOther,    // SlotLength;               ///< The enumeration value from MISC_SLOT_LENGTH.
+  0,    // SlotID;
+  {    // SlotCharacteristics1;
+    1,  // CharacteristicsUnknown  :1;
+    0,  // Provides50Volts         :1;
+    0,  // Provides33Volts         :1;
+    0,  // SharedSlot              :1;
+    0,  // PcCard16Supported       :1;
+    0,  // CardBusSupported        :1;
+    0,  // ZoomVideoSupported      :1;
+    0,  // ModemRingResumeSupported:1;
+  },
+  {     // SlotCharacteristics2;
+    0,  // PmeSignalSupported      :1;
+    0,  // HotPlugDevicesSupported :1;
+    0,  // SmbusSignalSupported    :1;
+    0,  // Reserved                :5;  ///< Set to 0.
+  },
+  0,    // SegmentGroupNum;
+  0,    // BusNum;
+  0,    // DevFuncNum;
+};
+CHAR8  *mSysSlotInfoType9Strings[] = {
+  "SD Card",
+  NULL
+};
+
+/***********************************************************************
+        SMBIOS data definition  TYPE16  Physical Memory ArrayInformation
+************************************************************************/
+SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = {
+  { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 },
+  MemoryArrayLocationSystemBoard, // Location;                       ///< The enumeration value from MEMORY_ARRAY_LOCATION.
+  MemoryArrayUseSystemMemory,     // Use;                            ///< The enumeration value from MEMORY_ARRAY_USE.
+  MemoryErrorCorrectionUnknown,   // MemoryErrorCorrection;          ///< The enumeration value from MEMORY_ERROR_CORRECTION.
+  0x80000000,                     // MaximumCapacity;
+  0xFFFE,                         // MemoryErrorInformationHandle;
+  1,                              // NumberOfMemoryDevices;
+  0x3fffffffffffffffULL,          // ExtendedMaximumCapacity;
+};
+CHAR8 *mPhyMemArrayInfoType16Strings[] = {
+  NULL
+};
+
+/***********************************************************************
+        SMBIOS data definition  TYPE17  Memory Device Information
+************************************************************************/
+SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = {
+  { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 },
+  0,          // MemoryArrayHandle;
+  0xFFFE,     // MemoryErrorInformationHandle;
+  0xFFFF,     // TotalWidth;
+  0xFFFF,     // DataWidth;
+  0xFFFF,     // Size;
+  MemoryFormFactorUnknown, // FormFactor;                     ///< The enumeration value from MEMORY_FORM_FACTOR.
+  0xff,       // DeviceSet;
+  1,          // DeviceLocator String
+  2,          // BankLocator String
+  MemoryTypeDram,         // MemoryType;                     ///< The enumeration value from MEMORY_DEVICE_TYPE.
+  {           // TypeDetail;
+    0,  // Reserved        :1;
+    0,  // Other           :1;
+    1,  // Unknown         :1;
+    0,  // FastPaged       :1;
+    0,  // StaticColumn    :1;
+    0,  // PseudoStatic    :1;
+    0,  // Rambus          :1;
+    0,  // Synchronous     :1;
+    0,  // Cmos            :1;
+    0,  // Edo             :1;
+    0,  // WindowDram      :1;
+    0,  // CacheDram       :1;
+    0,  // Nonvolatile     :1;
+    0,  // Registered      :1;
+    0,  // Unbuffered      :1;
+    0,  // Reserved1       :1;
+  },
+  0,          // Speed;
+  3,          // Manufacturer String
+  0,          // SerialNumber String
+  0,          // AssetTag String
+  0,          // PartNumber String
+  0,          // Attributes;
+  0,          // ExtendedSize;
+  0,          // ConfiguredMemoryClockSpeed;
+};
+
+#if (FixedPcdGetBool (PcdIscpSupport))
+CHAR8 *mMemDevInfoType17Strings[ 7 ] = {0};
+#else
+CHAR8 *mMemDevInfoType17Strings[] = {
+  "OS Virtual Memory",
+  "malloc",
+  "OSV",
+  NULL
+};
+#endif
+
+/***********************************************************************
+        SMBIOS data definition  TYPE19  Memory Array Mapped Address Information
+************************************************************************/
+SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = {
+  { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 },
+  0x80000000, // StartingAddress;
+  0xbfffffff, // EndingAddress;
+  0,          // MemoryArrayHandle;
+  1,          // PartitionWidth;
+  0,          // ExtendedStartingAddress;
+  0,          // ExtendedEndingAddress;
+};
+CHAR8 *mMemArrMapInfoType19Strings[] = {
+  NULL
+};
+
+/***********************************************************************
+        SMBIOS data definition  TYPE32  Boot Information
+************************************************************************/
+SMBIOS_TABLE_TYPE32 mBootInfoType32 = {
+  { EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, sizeof (SMBIOS_TABLE_TYPE32), 0 },
+  { 0, 0, 0, 0, 0, 0 },         // Reserved[6];
+  BootInformationStatusNoError  // BootStatus
+};
+
+CHAR8 *mBootInfoType32Strings[] = {
+  NULL
+};
+
+
+/**
+
+  Create SMBIOS record.
+
+  Converts a fixed SMBIOS structure and an array of pointers to strings into
+  an SMBIOS record where the strings are cat'ed on the end of the fixed record
+  and terminated via a double NULL and add to SMBIOS table.
+
+  SMBIOS_TABLE_TYPE32 gSmbiosType12 = {
+    { EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS, sizeof (SMBIOS_TABLE_TYPE12), 0 },
+    1 // StringCount
+  };
+
+  CHAR8 *gSmbiosType12Strings[] = {
+    "Not Found",
+    NULL
+  };
+
+  ...
+
+  LogSmbiosData (
+    (EFI_SMBIOS_TABLE_HEADER*)&gSmbiosType12,
+    gSmbiosType12Strings
+    );
+
+  @param  Template    Fixed SMBIOS structure, required.
+  @param  StringArray Array of strings to convert to an SMBIOS string pack.
+                      NULL is OK.
+**/
+
+EFI_STATUS
+EFIAPI
+LogSmbiosData (
+  IN  EFI_SMBIOS_TABLE_HEADER *Template,
+  IN  CHAR8                   **StringPack
+  )
+{
+  EFI_STATUS                Status;
+  EFI_SMBIOS_HANDLE         SmbiosHandle;
+  EFI_SMBIOS_TABLE_HEADER   *Record;
+  UINTN                     Index;
+  UINTN                     StringSize;
+  UINTN                     Size;
+  CHAR8                     *Str;
+
+
+  // Calculate the size of the fixed record and optional string pack
+  Size = Template->Length;
+  if (StringPack == NULL) {
+    // At least a double null is required
+    Size += 2;
+  } else {
+    for (Index = 0; StringPack[Index] != NULL; Index++) {
+      StringSize = AsciiStrSize (StringPack[Index]);
+      Size += StringSize;
+    }
+  if (StringPack[0] == NULL) {
+    // At least a double null is required
+    Size += 1;
+    }
+
+    // Don't forget the terminating double null
+    Size += 1;
+  }
+
+  // Copy over Template
+  Record = (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size);
+  if (Record == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+  CopyMem (Record, Template, Template->Length);
+
+  // Append string pack
+  Str = ((CHAR8 *)Record) + Record->Length;
+  for (Index = 0; StringPack[Index] != NULL; Index++) {
+    StringSize = AsciiStrSize (StringPack[Index]);
+    CopyMem (Str, StringPack[Index], StringSize);
+    Str += StringSize;
+  }
+  *Str = 0;
+
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+  Status = mSmbiosProtocol->Add (
+                     mSmbiosProtocol,
+                     gImageHandle,
+                     &SmbiosHandle,
+                     Record
+                     );
+
+  ASSERT_EFI_ERROR (Status);
+  FreePool (Record);
+  return Status;
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE0  BIOS Information
+************************************************************************/
+VOID
+BIOSInfoUpdateSmbiosType0 (
+  VOID
+  )
+{
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBIOSInfoType0, mBIOSInfoType0Strings);
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE1  System Information
+************************************************************************/
+VOID
+SysInfoUpdateSmbiosType1 (
+  VOID
+  )
+{
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysInfoType1, mSysInfoType1Strings);
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE2  Board Information
+************************************************************************/
+VOID
+BoardInfoUpdateSmbiosType2 (
+  VOID
+  )
+{
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBoardInfoType2, mBoardInfoType2Strings);
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE3  Enclosure Information
+************************************************************************/
+VOID
+EnclosureInfoUpdateSmbiosType3 (
+  VOID
+  )
+{
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mEnclosureInfoType3, mEnclosureInfoType3Strings);
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE4  Processor Information
+************************************************************************/
+VOID
+ProcessorInfoUpdateSmbiosType4 (
+  VOID
+  )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+  ISCP_TYPE4_SMBIOS_INFO *SmbiosT4 = &mSmbiosInfo.SmbiosCpuBuffer.T4[0];
+
+  DEBUG ((EFI_D_ERROR, "Logging SmbiosType4 from ISCP.\n"));
+
+  mProcessorInfoType4.ProcessorType = SmbiosT4->T4ProcType;
+  mProcessorInfoType4.ProcessorFamily = SmbiosT4->T4ProcFamily;
+  mProcessorInfoType4.ProcessorFamily2 = SmbiosT4->T4ProcFamily2;
+  mProcessorInfoType4.ProcessorCharacteristics = SmbiosT4->T4ProcCharacteristics;
+  mProcessorInfoType4.MaxSpeed = SmbiosT4->T4MaxSpeed;
+  mProcessorInfoType4.CurrentSpeed = SmbiosT4->T4CurrentSpeed;
+  mProcessorInfoType4.CoreCount = SmbiosT4->T4CoreCount;
+  mProcessorInfoType4.EnabledCoreCount = SmbiosT4->T4CoreEnabled;
+  mProcessorInfoType4.ThreadCount = SmbiosT4->T4ThreadCount;
+  mProcessorInfoType4.ProcessorUpgrade = SmbiosT4->T4ProcUpgrade;
+  mProcessorInfoType4.Status= (UINT8)SmbiosT4->T4Status;
+  mProcessorInfoType4.ExternalClock = SmbiosT4->T4ExternalClock;
+  CopyMem (&mProcessorInfoType4.ProcessorId.Signature,
+           &SmbiosT4->T4ProcId.ProcIDLsd, sizeof(UINT32));
+  CopyMem (&mProcessorInfoType4.ProcessorId.FeatureFlags,
+           &SmbiosT4->T4ProcId.ProcIDMsd, sizeof(UINT32));
+  CopyMem (&mProcessorInfoType4.Voltage,
+           &SmbiosT4->T4Voltage, sizeof(UINT8));
+#else
+  mProcessorInfoType4.ProcessorType = CentralProcessor;
+  mProcessorInfoType4.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+  mProcessorInfoType4.ProcessorFamily2 = ProcessorFamilyARM;
+  #ifdef ARM_CPU_AARCH64
+    mProcessorInfoType4.ProcessorCharacteristics = 0x6C;
+  #else
+    mProcessorInfoType4.ProcessorCharacteristics = 0x68;
+  #endif
+  mProcessorInfoType4.MaxSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000;        // In MHz
+  mProcessorInfoType4.CurrentSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000;    // In MHz
+  mProcessorInfoType4.CoreCount = PcdGet32(PcdCoreCount);
+  mProcessorInfoType4.EnabledCoreCount = PcdGet32(PcdCoreCount);
+  mProcessorInfoType4.ThreadCount = PcdGet32(PcdCoreCount);
+  mProcessorInfoType4.ProcessorUpgrade = ProcessorUpgradeDaughterBoard;
+#endif
+
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4, mProcessorInfoType4Strings);
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE7  Cache Information
+************************************************************************/
+VOID
+CacheInfoUpdateSmbiosType7 (
+  VOID
+  )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+  ISCP_TYPE7_SMBIOS_INFO *SmbiosT7;
+  SMBIOS_TABLE_TYPE7 dstType7 = {{0}};
+
+  DEBUG ((EFI_D_ERROR, "Logging SmbiosType7 from ISCP.\n"));
+
+  CopyMem ((VOID *) &dstType7.Hdr, (VOID *) &mCacheInfoType7.Hdr, sizeof (SMBIOS_STRUCTURE));
+  dstType7.SocketDesignation = 1;  // "L# Cache"
+
+  // L1 cache settings
+  mCacheInfoType7Strings[0][1] = '1'; // "L# Cache" --> "L1 Cache"
+  SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L1[0];
+  dstType7.CacheConfiguration  = SmbiosT7->T7CacheCfg;
+  dstType7.MaximumCacheSize    = SmbiosT7->T7MaxCacheSize;
+  dstType7.InstalledSize       = SmbiosT7->T7InstallSize;
+  CopyMem (&dstType7.SupportedSRAMType,
+           &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+  CopyMem (&dstType7.CurrentSRAMType,
+           &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+  dstType7.CacheSpeed          = SmbiosT7->T7CacheSpeed;
+  dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+  dstType7.SystemCacheType     = SmbiosT7->T7SystemCacheType;
+  dstType7.Associativity       = SmbiosT7->T7Associativity;
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+
+  // L2 cache settings
+  mCacheInfoType7Strings[0][1] = '2'; // "L# Cache" --> "L2 Cache"
+  SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L2[0];
+  dstType7.CacheConfiguration  = SmbiosT7->T7CacheCfg;
+  dstType7.MaximumCacheSize    = SmbiosT7->T7MaxCacheSize;
+  dstType7.InstalledSize       = SmbiosT7->T7InstallSize;
+  CopyMem (&dstType7.SupportedSRAMType,
+           &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+  CopyMem (&dstType7.CurrentSRAMType,
+           &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+  dstType7.CacheSpeed          = SmbiosT7->T7CacheSpeed;
+  dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+  dstType7.SystemCacheType     = SmbiosT7->T7SystemCacheType;
+  dstType7.Associativity       = SmbiosT7->T7Associativity;
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+
+  // L3 cache settings
+  mCacheInfoType7Strings[0][1] = '3'; // "L# Cache" --> "L3 Cache"
+  SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L3[0];
+  dstType7.CacheConfiguration  = SmbiosT7->T7CacheCfg;
+  dstType7.MaximumCacheSize    = SmbiosT7->T7MaxCacheSize;
+  dstType7.InstalledSize       = SmbiosT7->T7InstallSize;
+  CopyMem (&dstType7.SupportedSRAMType,
+           &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+  CopyMem (&dstType7.CurrentSRAMType,
+           &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+  dstType7.CacheSpeed          = SmbiosT7->T7CacheSpeed;
+  dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+  dstType7.SystemCacheType     = SmbiosT7->T7SystemCacheType;
+  dstType7.Associativity       = SmbiosT7->T7Associativity;
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+#else
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, mCacheInfoType7Strings);
+#endif
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE9  System Slot Information
+************************************************************************/
+VOID
+SysSlotInfoUpdateSmbiosType9 (
+  VOID
+  )
+{
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysSlotInfoType9, mSysSlotInfoType9Strings);
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE16  Physical Memory Array Information
+************************************************************************/
+VOID
+PhyMemArrayInfoUpdateSmbiosType16 (
+  VOID
+  )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+  ISCP_TYPE16_SMBIOS_INFO *SmbiosT16 = &mSmbiosInfo.SmbiosMemBuffer.T16;
+
+  DEBUG ((EFI_D_ERROR, "Logging SmbiosType16 from ISCP.\n"));
+
+  mPhyMemArrayInfoType16.Location = SmbiosT16->Location;
+  mPhyMemArrayInfoType16.Use = SmbiosT16->Use;
+  mPhyMemArrayInfoType16.MemoryErrorCorrection = SmbiosT16->MemoryErrorCorrection;
+  mPhyMemArrayInfoType16.NumberOfMemoryDevices = SmbiosT16->NumberOfMemoryDevices;
+#endif
+
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mPhyMemArrayInfoType16, mPhyMemArrayInfoType16Strings);
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE17  Memory Device Information
+************************************************************************/
+VOID
+MemDevInfoUpdatedstType17 (
+  VOID
+  )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+  SMBIOS_TABLE_TYPE17 dstType17 = {{0}};
+  ISCP_TYPE17_SMBIOS_INFO *srcType17;
+  UINTN i, j, StrIndex, LastIndex;
+
+  DEBUG ((EFI_D_ERROR, "Logging SmbiosType17 from ISCP.\n"));
+
+  LastIndex = (sizeof(mMemDevInfoType17Strings) / sizeof (CHAR8 *)) - 1;
+  for (i = 0; i < 2; ++i) {
+    for (j = 0; j < 2; ++j) {
+      srcType17 = &mSmbiosInfo.SmbiosMemBuffer.T17[i][j];
+
+      CopyMem ((VOID *) &dstType17.Hdr, (VOID *) &mMemDevInfoType17.Hdr, sizeof (SMBIOS_STRUCTURE));
+      dstType17.MemoryArrayHandle = srcType17->Handle;
+      dstType17.TotalWidth = srcType17->TotalWidth;
+      dstType17.DataWidth = srcType17->DataWidth;
+      dstType17.Size = srcType17->MemorySize;
+      dstType17.FormFactor = srcType17->FormFactor;
+      dstType17.DeviceSet = srcType17->DeviceSet;
+      dstType17.MemoryType = srcType17->MemoryType;
+
+      CopyMem ((VOID *) &dstType17.TypeDetail, (VOID *) &mMemDevInfoType17.TypeDetail, sizeof (UINT16));
+      dstType17.Speed = srcType17->Speed;
+      dstType17.Attributes = srcType17->Attributes;
+      dstType17.ExtendedSize = srcType17->ExtSize;
+      dstType17.ConfiguredMemoryClockSpeed = srcType17->ConfigSpeed;
+
+      // Build table of TYPE17 strings
+      StrIndex = 0;
+
+      if (AsciiStrLen ((CHAR8 *)srcType17->DeviceLocator) && StrIndex < LastIndex) {
+        mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->DeviceLocator;
+        dstType17.DeviceLocator = (SMBIOS_TABLE_STRING) StrIndex;
+      } else {
+        dstType17.DeviceLocator = 0;
+      }
+
+      if (AsciiStrLen ((CHAR8 *)srcType17->BankLocator) && StrIndex < LastIndex) {
+        mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->BankLocator;
+        dstType17.BankLocator = (SMBIOS_TABLE_STRING) StrIndex;
+      } else {
+        dstType17.BankLocator = 0;
+      }
+
+      if (AsciiStrLen ((CHAR8 *)srcType17->ManufacturerIdCode) && StrIndex < LastIndex) {
+        mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->ManufacturerIdCode;
+        dstType17.Manufacturer = (SMBIOS_TABLE_STRING) StrIndex;
+      } else {
+        dstType17.Manufacturer = 0;
+      }
+
+      if (AsciiStrLen ((CHAR8 *)srcType17->SerialNumber) && StrIndex < LastIndex) {
+        mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->SerialNumber;
+        dstType17.SerialNumber = (SMBIOS_TABLE_STRING) StrIndex;
+      } else {
+        dstType17.SerialNumber = 0;
+      }
+
+      if (AsciiStrLen ((CHAR8 *)srcType17->PartNumber) && StrIndex < LastIndex) {
+        mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->PartNumber;
+        dstType17.PartNumber = (SMBIOS_TABLE_STRING) StrIndex;
+      } else {
+        dstType17.PartNumber = 0;
+      }
+
+      mMemDevInfoType17Strings[StrIndex] = NULL;
+      LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType17, mMemDevInfoType17Strings);
+    }
+  }
+#else
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings);
+#endif
+}
+
+/***********************************************************************
+        SMBIOS data update  TYPE19  Memory Array Map Information
+************************************************************************/
+VOID
+MemArrMapInfoUpdateSmbiosType19 (
+  VOID
+  )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+  ISCP_TYPE19_SMBIOS_INFO *SmbiosT19 = &mSmbiosInfo.SmbiosMemBuffer.T19;
+
+  DEBUG ((EFI_D_ERROR, "Logging SmbiosType19 from ISCP.\n"));
+
+  mMemArrMapInfoType19.StartingAddress = SmbiosT19->StartingAddr;
+  mMemArrMapInfoType19.EndingAddress = SmbiosT19->EndingAddr;
+  mMemArrMapInfoType19.MemoryArrayHandle = SmbiosT19->MemoryArrayHandle;
+  mMemArrMapInfoType19.PartitionWidth = SmbiosT19->PartitionWidth;
+  mMemArrMapInfoType19.ExtendedStartingAddress = SmbiosT19->ExtStartingAddr;
+  mMemArrMapInfoType19.ExtendedEndingAddress = SmbiosT19->ExtEndingAddr;
+#endif
+
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings);
+}
+
+
+/***********************************************************************
+        SMBIOS data update  TYPE32  Boot Information
+************************************************************************/
+VOID
+BootInfoUpdateSmbiosType32 (
+  VOID
+  )
+{
+  LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBootInfoType32, mBootInfoType32Strings);
+}
+
+/***********************************************************************
+        Driver Entry
+************************************************************************/
+EFI_STATUS
+EFIAPI
+PlatformSmbiosDriverEntryPoint (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS Status;
+
+  DEBUG ((EFI_D_ERROR, "PlatformSmbiosDxe Loaded\n"));
+
+  //
+  // Locate Smbios protocol
+  //
+  Status = gBS->LocateProtocol (
+               &gEfiSmbiosProtocolGuid,
+               NULL,
+               (VOID **)&mSmbiosProtocol
+               );
+
+  if (EFI_ERROR (Status)) {
+    mSmbiosProtocol = NULL;
+    DEBUG ((EFI_D_ERROR, "Failed to Locate SMBIOS Protocol"));
+    return Status;
+  }
+
+#if (FixedPcdGetBool (PcdIscpSupport))
+  Status = gBS->LocateProtocol (
+               &gAmdIscpDxeProtocolGuid,
+               NULL,
+               (VOID **)&mIscpDxeProtocol
+               );
+  if (EFI_ERROR (Status)) {
+    mIscpDxeProtocol = NULL;
+    DEBUG ((EFI_D_ERROR, "Failed to Locate ISCP DXE Protocol"));
+    return Status;
+  }
+
+  Status = mIscpDxeProtocol-> AmdExecuteSmbiosInfoDxe (
+                    mIscpDxeProtocol,
+                    &mSmbiosInfo
+                    );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Failed to get SMBIOS data via ISCP"));
+    return Status;
+  }
+#endif
+
+  BIOSInfoUpdateSmbiosType0();
+
+  SysInfoUpdateSmbiosType1();
+
+  BoardInfoUpdateSmbiosType2();
+
+  EnclosureInfoUpdateSmbiosType3();
+
+  ProcessorInfoUpdateSmbiosType4();
+
+  CacheInfoUpdateSmbiosType7();
+
+  SysSlotInfoUpdateSmbiosType9();
+
+  PhyMemArrayInfoUpdateSmbiosType16();
+
+  MemDevInfoUpdatedstType17();
+
+  MemArrMapInfoUpdateSmbiosType19();
+
+  BootInfoUpdateSmbiosType32();
+
+  return Status;
+}
diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
new file mode 100644
index 0000000..82684ad
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
@@ -0,0 +1,60 @@
+#/** @file
+#  SMBIOS Table for ARM platform
+#
+#  Copyright (c) 2013, Linaro Ltd. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformSmbiosDxe
+  FILE_GUID                      = 3847D23F-1D95-4772-B60C-4BBFBC4D532F
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = PlatformSmbiosDriverEntryPoint
+
+[Sources]
+  PlatformSmbiosDxe.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  MemoryAllocationLib
+  BaseMemoryLib
+  BaseLib
+  UefiLib
+  UefiDriverEntryPoint
+  DebugLib
+
+
+[Protocols]
+  gEfiSmbiosProtocolGuid             ## CONSUMER
+  gAmdIscpDxeProtocolGuid            ## CONSUMER
+
+[Guids]
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+[Depex]
+  gEfiSmbiosProtocolGuid AND
+  gAmdIscpDxeProtocolGuid
+
diff --git a/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c b/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c
new file mode 100644
index 0000000..be6cf9e
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c
@@ -0,0 +1,189 @@
+/** @file
+
+  This driver produces an EFI_RNG_PROTOCOL instance for the AMD Seattle CCP
+
+  Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+
+#include <Protocol/Rng.h>
+
+#define CCP_TRNG_OFFSET     0xc
+#define CCP_TNRG_RETRIES    5
+
+STATIC EFI_PHYSICAL_ADDRESS mCcpRngOutputReg;
+
+STATIC EFI_HANDLE mHandle;
+
+/**
+  Returns information about the random number generation implementation.
+
+  @param[in]     This                 A pointer to the EFI_RNG_PROTOCOL
+                                      instance.
+  @param[in,out] RNGAlgorithmListSize On input, the size in bytes of
+                                      RNGAlgorithmList.
+                                      On output with a return code of
+                                      EFI_SUCCESS, the size in bytes of the
+                                      data returned in RNGAlgorithmList. On
+                                      output with a return code of
+                                      EFI_BUFFER_TOO_SMALL, the size of
+                                      RNGAlgorithmList required to obtain the
+                                      list.
+  @param[out] RNGAlgorithmList        A caller-allocated memory buffer filled
+                                      by the driver with one EFI_RNG_ALGORITHM
+                                      element for each supported RNG algorithm.
+                                      The list must not change across multiple
+                                      calls to the same driver. The first
+                                      algorithm in the list is the default
+                                      algorithm for the driver.
+
+  @retval EFI_SUCCESS                 The RNG algorithm list was returned
+                                      successfully.
+  @retval EFI_UNSUPPORTED             The services is not supported by this
+                                      driver.
+  @retval EFI_DEVICE_ERROR            The list of algorithms could not be
+                                      retrieved due to a hardware or firmware
+                                      error.
+  @retval EFI_INVALID_PARAMETER       One or more of the parameters are
+                                      incorrect.
+  @retval EFI_BUFFER_TOO_SMALL        The buffer RNGAlgorithmList is too small
+                                      to hold the result.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+StyxRngGetInfo (
+  IN      EFI_RNG_PROTOCOL        *This,
+  IN OUT  UINTN                   *RNGAlgorithmListSize,
+  OUT     EFI_RNG_ALGORITHM       *RNGAlgorithmList
+  )
+{
+  if (This == NULL || RNGAlgorithmListSize == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) {
+    *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+    return EFI_BUFFER_TOO_SMALL;
+  }
+
+  if (RNGAlgorithmList == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+  CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Produces and returns an RNG value using either the default or specified RNG
+  algorithm.
+
+  @param[in]  This                    A pointer to the EFI_RNG_PROTOCOL
+                                      instance.
+  @param[in]  RNGAlgorithm            A pointer to the EFI_RNG_ALGORITHM that
+                                      identifies the RNG algorithm to use. May
+                                      be NULL in which case the function will
+                                      use its default RNG algorithm.
+  @param[in]  RNGValueLength          The length in bytes of the memory buffer
+                                      pointed to by RNGValue. The driver shall
+                                      return exactly this numbers of bytes.
+  @param[out] RNGValue                A caller-allocated memory buffer filled
+                                      by the driver with the resulting RNG
+                                      value.
+
+  @retval EFI_SUCCESS                 The RNG value was returned successfully.
+  @retval EFI_UNSUPPORTED             The algorithm specified by RNGAlgorithm
+                                      is not supported by this driver.
+  @retval EFI_DEVICE_ERROR            An RNG value could not be retrieved due
+                                      to a hardware or firmware error.
+  @retval EFI_NOT_READY               There is not enough random data available
+                                      to satisfy the length requested by
+                                      RNGValueLength.
+  @retval EFI_INVALID_PARAMETER       RNGValue is NULL or RNGValueLength is
+                                      zero.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+StyxRngGetRNG (
+  IN EFI_RNG_PROTOCOL            *This,
+  IN EFI_RNG_ALGORITHM           *RNGAlgorithm, OPTIONAL
+  IN UINTN                       RNGValueLength,
+  OUT UINT8                      *RNGValue
+  )
+{
+  UINT32 Val;
+  UINT32 Retries;
+  UINT32 Loop;
+
+  if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // We only support the raw algorithm, so reject requests for anything else
+  //
+  if (RNGAlgorithm != NULL &&
+      !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) {
+    return EFI_UNSUPPORTED;
+  }
+
+  do {
+    Retries = CCP_TNRG_RETRIES;
+    do {
+      Val = MmioRead32 (mCcpRngOutputReg);
+    } while (!Val && Retries-- > 0);
+
+    if (!Val) {
+      return EFI_DEVICE_ERROR;
+    }
+
+    for (Loop = 0; Loop < 4 && RNGValueLength > 0; Loop++, RNGValueLength--) {
+      *RNGValue++ = (UINT8)Val;
+      Val >>= 8;
+    }
+  } while (RNGValueLength > 0);
+
+  return EFI_SUCCESS;
+}
+
+STATIC EFI_RNG_PROTOCOL mStyxRngProtocol = {
+  StyxRngGetInfo,
+  StyxRngGetRNG
+};
+
+//
+// Entry point of this driver.
+//
+EFI_STATUS
+EFIAPI
+StyxRngEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  mCcpRngOutputReg = PcdGet64 (PcdCCPBase) + CCP_TRNG_OFFSET;
+
+  return SystemTable->BootServices->InstallMultipleProtocolInterfaces (
+                                      &mHandle,
+                                      &gEfiRngProtocolGuid, &mStyxRngProtocol,
+                                      NULL
+                                      );
+}
diff --git a/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf b/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
new file mode 100644
index 0000000..0f4fe7c
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
@@ -0,0 +1,47 @@
+## @file
+# This driver produces an EFI_RNG_PROTOCOL instance for the AMD Seattle CCP
+#
+# Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = StyxRngDxe
+  FILE_GUID                      = 58E26F0D-CBAC-4BBA-B70F-18221415665A
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = StyxRngEntryPoint
+
+[Sources]
+  StyxRngDxe.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  IoLib
+  PcdLib
+  UefiDriverEntryPoint
+
+[Pcd]
+  gAmdModulePkgTokenSpaceGuid.PcdCCPBase
+
+[Protocols]
+  gEfiRngProtocolGuid              ## PRODUCES
+
+[Guids]
+  gEfiRngAlgorithmRaw
+
+[Depex]
+  TRUE
diff --git a/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c b/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c
new file mode 100644
index 0000000..1958d91
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c
@@ -0,0 +1,201 @@
+/** @file
+  Initialize SATA Phy, Serdes, and Controller.
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "SataRegisters.h"
+
+#include <Library/AmdSataInitLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+STATIC
+VOID
+ResetSataController (
+  EFI_PHYSICAL_ADDRESS    AhciBaseAddr
+  )
+{
+  // Make a minimal global reset for HBA regiser
+  MmioOr32 (AhciBaseAddr + EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
+
+  // Clear all interrupts
+  MmioWrite32 (AhciBaseAddr + EFI_AHCI_PORT_IS, EFI_AHCI_PORT_IS_CLEAR);
+
+  // Turn on interrupts and ensure that the HBA is working in AHCI mode
+  MmioOr32 (AhciBaseAddr + EFI_AHCI_GHC_OFFSET,
+    EFI_AHCI_GHC_IE | EFI_AHCI_GHC_ENABLE);
+}
+
+STATIC
+VOID
+SetSataCapabilities (
+  EFI_PHYSICAL_ADDRESS    AhciBaseAddr
+  )
+{
+  UINT32                  Capability;
+
+  Capability = 0;
+  if (FixedPcdGetBool (PcdSataSssSupport)) // Staggered Spin-Up Support bit
+    Capability |= EFI_AHCI_CAP_SSS;
+  if (FixedPcdGetBool (PcdSataSmpsSupport)) // Mechanical Presence Support bit
+    Capability |= EFI_AHCI_CAP_SMPS;
+
+  MmioOr32 (AhciBaseAddr + EFI_AHCI_CAPABILITY_OFFSET, Capability);
+}
+
+STATIC
+VOID
+InitializeSataPorts (
+  EFI_PHYSICAL_ADDRESS    AhciBaseAddr,
+  UINTN                   PortCount
+  )
+{
+  INTN                    PortNum;
+  BOOLEAN                 IsCpd;
+  BOOLEAN                 IsMpsp;
+  UINT32                  PortRegAddr;
+  UINT32                  RegVal;
+
+  // Set Ports Implemented (PI)
+  MmioWrite32 (AhciBaseAddr + EFI_AHCI_PI_OFFSET, (1 << PortCount) - 1);
+
+  IsCpd = FixedPcdGetBool (PcdSataPortCpd);
+  IsMpsp = FixedPcdGetBool (PcdSataPortMpsp);
+  if (!IsCpd && !IsMpsp) {
+    return;
+  }
+
+  for (PortNum = 0; PortNum < PortCount; PortNum++) {
+    PortRegAddr = EFI_AHCI_PORT_OFFSET (PortNum) + EFI_AHCI_PORT_CMD;
+    RegVal = MmioRead32(AhciBaseAddr + PortRegAddr);
+    if (IsCpd)
+      RegVal |= EFI_AHCI_PORT_CMD_CPD;
+    else
+      RegVal &= ~EFI_AHCI_PORT_CMD_CPD;
+    if (IsMpsp)
+      RegVal |= EFI_AHCI_PORT_CMD_MPSP;
+    else
+      RegVal &= ~EFI_AHCI_PORT_CMD_MPSP;
+    RegVal |= EFI_AHCI_PORT_CMD_HPCP;
+    MmioWrite32(AhciBaseAddr + PortRegAddr, RegVal);
+  }
+}
+
+STATIC
+EFI_STATUS
+InitializeSataController (
+  EFI_PHYSICAL_ADDRESS    AhciBaseAddr,
+  UINTN                   SataPortCount,
+  UINTN                   StartPort
+  )
+{
+  UINT8                   SataChPerSerdes;
+  UINT32                  PortNum;
+  UINT32                  EvenPort;
+  UINT32                  OddPort;
+
+  SataChPerSerdes = FixedPcdGet8 (PcdSataNumChPerSerdes);
+
+  for (PortNum = 0; PortNum < SataPortCount; PortNum += SataChPerSerdes) {
+    EvenPort = (UINT32)(FixedPcdGet16 (PcdSataPortMode) >> (PortNum * 2)) & 3;
+    OddPort = (UINT32)(FixedPcdGet16 (PcdSataPortMode) >> ((PortNum+1) * 2)) & 3;
+    SataPhyInit ((StartPort + PortNum) / SataChPerSerdes, EvenPort, OddPort);
+  }
+
+  //
+  // Reset SATA controller
+  //
+  ResetSataController (AhciBaseAddr);
+
+  //
+  // Set SATA capabilities
+  //
+  SetSataCapabilities (AhciBaseAddr);
+
+  //
+  // Set and intialize the Sata ports
+  //
+  InitializeSataPorts (AhciBaseAddr, SataPortCount);
+
+  return RegisterNonDiscoverableMmioDevice (
+           NonDiscoverableDeviceTypeAhci,
+           NonDiscoverableDeviceDmaTypeCoherent,
+           NULL,
+           NULL,
+           1,
+           AhciBaseAddr, SIZE_4KB);
+}
+
+#define STYX_SOC_VERSION_MASK    0xFFF
+#define STYX_SOC_VERSION_A0      0x000
+#define STYX_SOC_VERSION_B0      0x010
+#define STYX_SOC_VERSION_B1      0x011
+
+EFI_STATUS
+EFIAPI
+StyxSataPlatformDxeEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  UINT32                  PortNum;
+  EFI_STATUS              Status;
+
+  //
+  // Perform SATA workarounds
+  //
+  for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata0PortCount); PortNum++) {
+      SetCwMinSata0 (PortNum);
+  }
+
+  Status = InitializeSataController (FixedPcdGet32(PcdSata0CtrlAxiSlvPort),
+             FixedPcdGet8(PcdSata0PortCount), 0);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_WARN, "%a: failed to initialize primary SATA controller!\n",
+      __FUNCTION__));
+    return Status;
+  }
+
+  for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata0PortCount); PortNum++) {
+      SetPrdSingleSata0 (PortNum);
+  }
+
+  //
+  // Ignore the second SATA controller on pre-B1 silicon
+  //
+  if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
+    return EFI_SUCCESS;
+  }
+
+  if (FixedPcdGet8(PcdSata1PortCount) > 0) {
+    for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata1PortCount); PortNum++) {
+        SetCwMinSata1 (PortNum);
+    }
+
+    Status = InitializeSataController (FixedPcdGet32(PcdSata1CtrlAxiSlvPort),
+               FixedPcdGet8(PcdSata1PortCount),
+               FixedPcdGet8(PcdSata0PortCount));
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_WARN, "%a: failed to initialize secondary SATA controller!\n",
+        __FUNCTION__));
+    } else {
+      for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata1PortCount); PortNum++) {
+          SetPrdSingleSata1 (PortNum);
+      }
+    }
+  }
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/SataRegisters.h b/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/SataRegisters.h
new file mode 100644
index 0000000..ff78f4a
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/SataRegisters.h
@@ -0,0 +1,180 @@
+/** @file
+  Header file for AHCI mode of ATA host controller.
+
+  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SATA_REGISTERS_H__
+#define __SATA_REGISTERS_H__
+
+#define EFI_AHCI_BAR_INDEX                     0x05
+
+#define EFI_AHCI_CAPABILITY_OFFSET             0x0000
+#define   EFI_AHCI_CAP_SSS                     BIT27
+#define   EFI_AHCI_CAP_SMPS                    BIT28
+#define   EFI_AHCI_CAP_S64A                    BIT31
+#define EFI_AHCI_GHC_OFFSET                    0x0004
+#define   EFI_AHCI_GHC_RESET                   BIT0
+#define   EFI_AHCI_GHC_IE                      BIT1
+#define   EFI_AHCI_GHC_ENABLE                  BIT31
+#define EFI_AHCI_IS_OFFSET                     0x0008
+#define EFI_AHCI_PI_OFFSET                     0x000C
+
+#define EFI_AHCI_MAX_PORTS                     32
+
+//
+// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
+//
+#define  EFI_AHCI_BUS_PHY_DETECT_TIMEOUT       10
+//
+// Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
+//
+#define  EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT    EFI_TIMER_PERIOD_MILLISECONDS(500)
+//
+// Refer SATA1.0a spec, the bus reset time should be less than 1s.
+//
+#define  EFI_AHCI_BUS_RESET_TIMEOUT            EFI_TIMER_PERIOD_SECONDS(1)
+
+#define  EFI_AHCI_ATAPI_DEVICE_SIG             0xEB140000
+#define  EFI_AHCI_ATA_DEVICE_SIG               0x00000000
+#define  EFI_AHCI_PORT_MULTIPLIER_SIG          0x96690000
+#define  EFI_AHCI_ATAPI_SIG_MASK               0xFFFF0000
+
+//
+// Each PRDT entry can point to a memory block up to 4M byte
+//
+#define EFI_AHCI_MAX_DATA_PER_PRDT             0x400000
+
+#define EFI_AHCI_FIS_REGISTER_H2D              0x27      //Register FIS - Host to Device
+#define   EFI_AHCI_FIS_REGISTER_H2D_LENGTH     20
+#define EFI_AHCI_FIS_REGISTER_D2H              0x34      //Register FIS - Device to Host
+#define   EFI_AHCI_FIS_REGISTER_D2H_LENGTH     20
+#define EFI_AHCI_FIS_DMA_ACTIVATE              0x39      //DMA Activate FIS - Device to Host
+#define   EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH     4
+#define EFI_AHCI_FIS_DMA_SETUP                 0x41      //DMA Setup FIS - Bi-directional
+#define   EFI_AHCI_FIS_DMA_SETUP_LENGTH        28
+#define EFI_AHCI_FIS_DATA                      0x46      //Data FIS - Bi-directional
+#define EFI_AHCI_FIS_BIST                      0x58      //BIST Activate FIS - Bi-directional
+#define   EFI_AHCI_FIS_BIST_LENGTH             12
+#define EFI_AHCI_FIS_PIO_SETUP                 0x5F      //PIO Setup FIS - Device to Host
+#define   EFI_AHCI_FIS_PIO_SETUP_LENGTH        20
+#define EFI_AHCI_FIS_SET_DEVICE                0xA1      //Set Device Bits FIS - Device to Host
+#define   EFI_AHCI_FIS_SET_DEVICE_LENGTH       8
+
+#define EFI_AHCI_D2H_FIS_OFFSET                0x40
+#define EFI_AHCI_DMA_FIS_OFFSET                0x00
+#define EFI_AHCI_PIO_FIS_OFFSET                0x20
+#define EFI_AHCI_SDB_FIS_OFFSET                0x58
+#define EFI_AHCI_FIS_TYPE_MASK                 0xFF
+#define EFI_AHCI_U_FIS_OFFSET                  0x60
+
+//
+// Port register
+//
+#define EFI_AHCI_PORT_START                    0x0100
+#define EFI_AHCI_PORT_REG_WIDTH                0x0080
+#define EFI_AHCI_PORT_CLB                      0x0000
+#define EFI_AHCI_PORT_CLBU                     0x0004
+#define EFI_AHCI_PORT_FB                       0x0008
+#define EFI_AHCI_PORT_FBU                      0x000C
+#define EFI_AHCI_PORT_IS                       0x0010
+#define   EFI_AHCI_PORT_IS_DHRS                BIT0
+#define   EFI_AHCI_PORT_IS_PSS                 BIT1
+#define   EFI_AHCI_PORT_IS_SSS                 BIT2
+#define   EFI_AHCI_PORT_IS_SDBS                BIT3
+#define   EFI_AHCI_PORT_IS_UFS                 BIT4
+#define   EFI_AHCI_PORT_IS_DPS                 BIT5
+#define   EFI_AHCI_PORT_IS_PCS                 BIT6
+#define   EFI_AHCI_PORT_IS_DIS                 BIT7
+#define   EFI_AHCI_PORT_IS_PRCS                BIT22
+#define   EFI_AHCI_PORT_IS_IPMS                BIT23
+#define   EFI_AHCI_PORT_IS_OFS                 BIT24
+#define   EFI_AHCI_PORT_IS_INFS                BIT26
+#define   EFI_AHCI_PORT_IS_IFS                 BIT27
+#define   EFI_AHCI_PORT_IS_HBDS                BIT28
+#define   EFI_AHCI_PORT_IS_HBFS                BIT29
+#define   EFI_AHCI_PORT_IS_TFES                BIT30
+#define   EFI_AHCI_PORT_IS_CPDS                BIT31
+#define   EFI_AHCI_PORT_IS_CLEAR               0xFFFFFFFF
+#define   EFI_AHCI_PORT_IS_FIS_CLEAR           0x0000000F
+
+#define EFI_AHCI_PORT_OFFSET(PortNum) \
+        (EFI_AHCI_PORT_START + ((PortNum) * EFI_AHCI_PORT_REG_WIDTH))
+
+#define EFI_AHCI_PORT_IE                       0x0014
+#define EFI_AHCI_PORT_CMD                      0x0018
+#define   EFI_AHCI_PORT_CMD_ST_MASK            0xFFFFFFFE
+#define   EFI_AHCI_PORT_CMD_ST                 BIT0
+#define   EFI_AHCI_PORT_CMD_SUD                BIT1
+#define   EFI_AHCI_PORT_CMD_POD                BIT2
+#define   EFI_AHCI_PORT_CMD_CLO                BIT3
+#define   EFI_AHCI_PORT_CMD_CR                 BIT15
+#define   EFI_AHCI_PORT_CMD_FRE                BIT4
+#define   EFI_AHCI_PORT_CMD_FR                 BIT14
+#define   EFI_AHCI_PORT_CMD_MASK               ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
+#define   EFI_AHCI_PORT_CMD_PMA                BIT17
+#define   EFI_AHCI_PORT_CMD_HPCP               BIT18
+#define   EFI_AHCI_PORT_CMD_MPSP               BIT19
+#define   EFI_AHCI_PORT_CMD_CPD                BIT20
+#define   EFI_AHCI_PORT_CMD_ESP                BIT21
+#define   EFI_AHCI_PORT_CMD_ATAPI              BIT24
+#define   EFI_AHCI_PORT_CMD_DLAE               BIT25
+#define   EFI_AHCI_PORT_CMD_ALPE               BIT26
+#define   EFI_AHCI_PORT_CMD_ASP                BIT27
+#define   EFI_AHCI_PORT_CMD_ICC_MASK           (BIT28 | BIT29 | BIT30 | BIT31)
+#define   EFI_AHCI_PORT_CMD_ACTIVE             (1 << 28 )
+#define EFI_AHCI_PORT_TFD                      0x0020
+#define   EFI_AHCI_PORT_TFD_MASK               (BIT7 | BIT3 | BIT0)
+#define   EFI_AHCI_PORT_TFD_BSY                BIT7
+#define   EFI_AHCI_PORT_TFD_DRQ                BIT3
+#define   EFI_AHCI_PORT_TFD_ERR                BIT0
+#define   EFI_AHCI_PORT_TFD_ERR_MASK           0x00FF00
+#define EFI_AHCI_PORT_SIG                      0x0024
+#define EFI_AHCI_PORT_SSTS                     0x0028
+#define   EFI_AHCI_PORT_SSTS_DET_MASK          0x000F
+#define   EFI_AHCI_PORT_SSTS_DET               0x0001
+#define   EFI_AHCI_PORT_SSTS_DET_PCE           0x0003
+#define   EFI_AHCI_PORT_SSTS_SPD_MASK          0x00F0
+#define EFI_AHCI_PORT_SCTL                     0x002C
+#define   EFI_AHCI_PORT_SCTL_DET_MASK          0x000F
+#define   EFI_AHCI_PORT_SCTL_MASK              (~EFI_AHCI_PORT_SCTL_DET_MASK)
+#define   EFI_AHCI_PORT_SCTL_DET_INIT          0x0001
+#define   EFI_AHCI_PORT_SCTL_DET_PHYCOMM       0x0003
+#define   EFI_AHCI_PORT_SCTL_SPD_MASK          0x00F0
+#define   EFI_AHCI_PORT_SCTL_IPM_MASK          0x0F00
+#define   EFI_AHCI_PORT_SCTL_IPM_INIT          0x0300
+#define   EFI_AHCI_PORT_SCTL_IPM_PSD           0x0100
+#define   EFI_AHCI_PORT_SCTL_IPM_SSD           0x0200
+#define EFI_AHCI_PORT_SERR                     0x0030
+#define   EFI_AHCI_PORT_SERR_RDIE              BIT0
+#define   EFI_AHCI_PORT_SERR_RCE               BIT1
+#define   EFI_AHCI_PORT_SERR_TDIE              BIT8
+#define   EFI_AHCI_PORT_SERR_PCDIE             BIT9
+#define   EFI_AHCI_PORT_SERR_PE                BIT10
+#define   EFI_AHCI_PORT_SERR_IE                BIT11
+#define   EFI_AHCI_PORT_SERR_PRC               BIT16
+#define   EFI_AHCI_PORT_SERR_PIE               BIT17
+#define   EFI_AHCI_PORT_SERR_CW                BIT18
+#define   EFI_AHCI_PORT_SERR_BDE               BIT19
+#define   EFI_AHCI_PORT_SERR_DE                BIT20
+#define   EFI_AHCI_PORT_SERR_CRCE              BIT21
+#define   EFI_AHCI_PORT_SERR_HE                BIT22
+#define   EFI_AHCI_PORT_SERR_LSE               BIT23
+#define   EFI_AHCI_PORT_SERR_TSTE              BIT24
+#define   EFI_AHCI_PORT_SERR_UFT               BIT25
+#define   EFI_AHCI_PORT_SERR_EX                BIT26
+#define   EFI_AHCI_PORT_ERR_CLEAR              0xFFFFFFFF
+#define EFI_AHCI_PORT_SACT                     0x0034
+#define EFI_AHCI_PORT_CI                       0x0038
+#define EFI_AHCI_PORT_SNTF                     0x003C
+
+#endif
diff --git a/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf b/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
new file mode 100644
index 0000000..5fbfcf5
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
@@ -0,0 +1,63 @@
+## @file
+#
+#  Component description file for the Styx SATA platform driver.
+#
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = StyxSataPlatformDxe
+  FILE_GUID                      = 4703fac4-9de9-4010-87d1-11402894296a
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = StyxSataPlatformDxeEntryPoint
+
+[Sources]
+  InitController.c
+
+[Packages]
+  AmdModulePkg/AmdModulePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  AmdSataInit
+  BaseLib
+  DebugLib
+  IoLib
+  NonDiscoverableDeviceRegistrationLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[FixedPcd]
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset
+  gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes
+
+  gAmdStyxTokenSpaceGuid.PcdSata0CtrlAxiSlvPort
+  gAmdStyxTokenSpaceGuid.PcdSata0PortCount
+  gAmdStyxTokenSpaceGuid.PcdSata1CtrlAxiSlvPort
+  gAmdStyxTokenSpaceGuid.PcdSata1PortCount
+  gAmdStyxTokenSpaceGuid.PcdSataPortMode
+  gAmdStyxTokenSpaceGuid.PcdSataSmpsSupport
+  gAmdStyxTokenSpaceGuid.PcdSataSssSupport
+  gAmdStyxTokenSpaceGuid.PcdSataPortCpd
+  gAmdStyxTokenSpaceGuid.PcdSataPortMpsp
+
+[Pcd]
+  gAmdStyxTokenSpaceGuid.PcdSocCpuId
+
+[Depex]
+  TRUE
diff --git a/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c
new file mode 100644
index 0000000..03fd9e8
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c
@@ -0,0 +1,501 @@
+/** @file
+
+  FV block I/O protocol driver for Styx SPI flash exposed via ISCP
+
+  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <Protocol/AmdIscpDxeProtocol.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+#define SPI_BASE                (FixedPcdGet64 (PcdFdBaseAddress))
+#define BLOCK_SIZE              (FixedPcdGet32 (PcdFlashNvStorageBlockSize))
+
+STATIC AMD_ISCP_DXE_PROTOCOL    *mIscpDxeProtocol;
+STATIC EFI_HANDLE               mStyxSpiFvHandle;
+
+STATIC EFI_EVENT                mVirtualAddressChangeEvent;
+
+STATIC UINT64 mNvStorageBase;
+STATIC UINT64 mNvStorageLbaOffset;
+
+STATIC CONST UINT64 mNvStorageSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+                                     FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+                                     FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
+
+
+/**
+  Notification function of EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE.
+
+  This is a notification function registered on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
+  It convers pointer to new virtual address.
+
+  @param  Event        Event whose notification function is being invoked.
+  @param  Context      Pointer to the notification function's context.
+
+**/
+STATIC
+VOID
+EFIAPI
+VariableClassAddressChangeEvent (
+  IN EFI_EVENT                            Event,
+  IN VOID                                 *Context
+  )
+{
+  EfiConvertPointer (0x0, (VOID **)&mIscpDxeProtocol);
+  EfiConvertPointer (0x0, (VOID **)&mNvStorageBase);
+}
+
+/**
+  The GetAttributes() function retrieves the attributes and
+  current settings of the block.
+
+  @param This       Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+  @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the
+                    attributes and current settings are
+                    returned. Type EFI_FVB_ATTRIBUTES_2 is defined
+                    in EFI_FIRMWARE_VOLUME_HEADER.
+
+  @retval EFI_SUCCESS The firmware volume attributes were
+                      returned.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetAttributes (
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+  OUT       EFI_FVB_ATTRIBUTES_2                *Attributes
+  )
+{
+  *Attributes = EFI_FVB2_READ_ENABLED_CAP   | // Reads may be enabled
+                EFI_FVB2_READ_STATUS        | // Reads are currently enabled
+                EFI_FVB2_WRITE_STATUS       | // Writes are currently enabled
+                EFI_FVB2_WRITE_ENABLED_CAP  | // Writes may be enabled
+                EFI_FVB2_STICKY_WRITE       | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+                EFI_FVB2_MEMORY_MAPPED      | // It is memory mapped
+                EFI_FVB2_ERASE_POLARITY;      // After erasure all bits take this value (i.e. '1')
+
+  return EFI_SUCCESS;
+}
+
+/**
+  The SetAttributes() function sets configurable firmware volume
+  attributes and returns the new settings of the firmware volume.
+
+  @param This         Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+  @param Attributes   On input, Attributes is a pointer to
+                      EFI_FVB_ATTRIBUTES_2 that contains the
+                      desired firmware volume settings. On
+                      successful return, it contains the new
+                      settings of the firmware volume. Type
+                      EFI_FVB_ATTRIBUTES_2 is defined in
+                      EFI_FIRMWARE_VOLUME_HEADER.
+
+  @retval EFI_SUCCESS           The firmware volume attributes were returned.
+
+  @retval EFI_INVALID_PARAMETER The attributes requested are in
+                                conflict with the capabilities
+                                as declared in the firmware
+                                volume header.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeSetAttributes (
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+  IN OUT    EFI_FVB_ATTRIBUTES_2                *Attributes
+  )
+{
+  return EFI_SUCCESS;  // ignore for now
+}
+
+/**
+  The GetPhysicalAddress() function retrieves the base address of
+  a memory-mapped firmware volume. This function should be called
+  only for memory-mapped firmware volumes.
+
+  @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+  @param Address  Pointer to a caller-allocated
+                  EFI_PHYSICAL_ADDRESS that, on successful
+                  return from GetPhysicalAddress(), contains the
+                  base address of the firmware volume.
+
+  @retval EFI_SUCCESS       The firmware volume base address was returned.
+
+  @retval EFI_UNSUPPORTED   The firmware volume is not memory mapped.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetPhysicalAddress (
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+  OUT       EFI_PHYSICAL_ADDRESS                *Address
+  )
+{
+  *Address = (EFI_PHYSICAL_ADDRESS)mNvStorageBase;
+  return EFI_SUCCESS;
+}
+
+/**
+  The GetBlockSize() function retrieves the size of the requested
+  block. It also returns the number of additional blocks with
+  the identical size. The GetBlockSize() function is used to
+  retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+  @param This           Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+  @param Lba            Indicates the block for which to return the size.
+
+  @param BlockSize      Pointer to a caller-allocated UINTN in which
+                        the size of the block is returned.
+
+  @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+                        which the number of consecutive blocks,
+                        starting with Lba, is returned. All
+                        blocks in this range have a size of
+                        BlockSize.
+
+
+  @retval EFI_SUCCESS             The firmware volume base address was returned.
+
+  @retval EFI_INVALID_PARAMETER   The requested LBA is out of range.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetBlockSize (
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+  IN        EFI_LBA                             Lba,
+  OUT       UINTN                               *BlockSize,
+  OUT       UINTN                               *NumberOfBlocks
+  )
+{
+  *BlockSize = BLOCK_SIZE;
+  *NumberOfBlocks = mNvStorageSize / BLOCK_SIZE - (UINTN)Lba;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Reads the specified number of bytes into a buffer from the specified block.
+
+  The Read() function reads the requested number of bytes from the
+  requested block and stores them in the provided buffer.
+  Implementations should be mindful that the firmware volume
+  might be in the ReadDisabled state. If it is in this state,
+  the Read() function must return the status code
+  EFI_ACCESS_DENIED without modifying the contents of the
+  buffer. The Read() function must also prevent spanning block
+  boundaries. If a read is requested that would span a block
+  boundary, the read must read up to the boundary but not
+  beyond. The output parameter NumBytes must be set to correctly
+  indicate the number of bytes actually read. The caller must be
+  aware that a read may be partially completed.
+
+  @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+  @param Lba      The starting logical block index
+                  from which to read.
+
+  @param Offset   Offset into the block at which to begin reading.
+
+  @param NumBytes Pointer to a UINTN. At entry, *NumBytes
+                  contains the total size of the buffer. At
+                  exit, *NumBytes contains the total number of
+                  bytes read.
+
+  @param Buffer   Pointer to a caller-allocated buffer that will
+                  be used to hold the data that is read.
+
+  @retval EFI_SUCCESS         The firmware volume was read successfully,
+                              and contents are in Buffer.
+
+  @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA
+                              boundary. On output, NumBytes
+                              contains the total number of bytes
+                              returned in Buffer.
+
+  @retval EFI_ACCESS_DENIED   The firmware volume is in the
+                              ReadDisabled state.
+
+  @retval EFI_DEVICE_ERROR    The block device is not
+                              functioning correctly and could
+                              not be read.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeRead (
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+  IN        EFI_LBA                             Lba,
+  IN        UINTN                               Offset,
+  IN OUT    UINTN                               *NumBytes,
+  IN OUT    UINT8                               *Buffer
+  )
+{
+  VOID            *Base;
+
+  if (Offset + *NumBytes > BLOCK_SIZE) {
+    return EFI_BAD_BUFFER_SIZE;
+  }
+
+  Base = (VOID *)mNvStorageBase + Lba * BLOCK_SIZE + Offset;
+
+  //
+  // Copy the data from the in-memory image
+  //
+  CopyMem (Buffer, Base, *NumBytes);
+
+  DEBUG_CODE_BEGIN ();
+    EFI_STATUS      Status;
+
+    if (!EfiAtRuntime ()) {
+      Lba += mNvStorageLbaOffset;
+      Status = mIscpDxeProtocol->AmdExecuteLoadFvBlockDxe (mIscpDxeProtocol,
+                                   Lba * BLOCK_SIZE + Offset, Buffer, *NumBytes);
+      ASSERT_EFI_ERROR (Status);
+
+      ASSERT (CompareMem (Base, Buffer, *NumBytes) == 0);
+    }
+  DEBUG_CODE_END ();
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Writes the specified number of bytes from the input buffer to the block.
+
+  The Write() function writes the specified number of bytes from
+  the provided buffer to the specified block and offset. If the
+  firmware volume is sticky write, the caller must ensure that
+  all the bits of the specified range to write are in the
+  EFI_FVB_ERASE_POLARITY state before calling the Write()
+  function, or else the result will be unpredictable. This
+  unpredictability arises because, for a sticky-write firmware
+  volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+  state but cannot flip it back again.  Before calling the
+  Write() function,  it is recommended for the caller to first call
+  the EraseBlocks() function to erase the specified block to
+  write. A block erase cycle will transition bits from the
+  (NOT)EFI_FVB_ERASE_POLARITY state back to the
+  EFI_FVB_ERASE_POLARITY state. Implementations should be
+  mindful that the firmware volume might be in the WriteDisabled
+  state. If it is in this state, the Write() function must
+  return the status code EFI_ACCESS_DENIED without modifying the
+  contents of the firmware volume. The Write() function must
+  also prevent spanning block boundaries. If a write is
+  requested that spans a block boundary, the write must store up
+  to the boundary but not beyond. The output parameter NumBytes
+  must be set to correctly indicate the number of bytes actually
+  written. The caller must be aware that a write may be
+  partially completed. All writes, partial or otherwise, must be
+  fully flushed to the hardware before the Write() service
+  returns.
+
+  @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+  @param Lba      The starting logical block index to write to.
+
+  @param Offset   Offset into the block at which to begin writing.
+
+  @param NumBytes The pointer to a UINTN. At entry, *NumBytes
+                  contains the total size of the buffer. At
+                  exit, *NumBytes contains the total number of
+                  bytes actually written.
+
+  @param Buffer   The pointer to a caller-allocated buffer that
+                  contains the source for the write.
+
+  @retval EFI_SUCCESS         The firmware volume was written successfully.
+
+  @retval EFI_BAD_BUFFER_SIZE The write was attempted across an
+                              LBA boundary. On output, NumBytes
+                              contains the total number of bytes
+                              actually written.
+
+  @retval EFI_ACCESS_DENIED   The firmware volume is in the
+                              WriteDisabled state.
+
+  @retval EFI_DEVICE_ERROR    The block device is malfunctioning
+                              and could not be written.
+
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeWrite (
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+  IN        EFI_LBA                             Lba,
+  IN        UINTN                               Offset,
+  IN OUT    UINTN                               *NumBytes,
+  IN        UINT8                               *Buffer
+  )
+{
+  EFI_STATUS      Status;
+  VOID            *Base;
+
+  if (Offset + *NumBytes > BLOCK_SIZE) {
+    return EFI_BAD_BUFFER_SIZE;
+  }
+
+  Base = (VOID *)mNvStorageBase + Lba * BLOCK_SIZE + Offset;
+
+  Lba += mNvStorageLbaOffset;
+  Status = mIscpDxeProtocol->AmdExecuteUpdateFvBlockDxe (mIscpDxeProtocol,
+                               Lba * BLOCK_SIZE + Offset, Buffer, *NumBytes);
+  if (!EFI_ERROR (Status)) {
+    //
+    // Copy the data we just wrote to the in-memory copy of the
+    // firmware volume
+    //
+    CopyMem (Base, Buffer, *NumBytes);
+  }
+  return Status;
+}
+
+/**
+  Erases and initializes a firmware volume block.
+
+  The EraseBlocks() function erases one or more blocks as denoted
+  by the variable argument list. The entire parameter list of
+  blocks must be verified before erasing any blocks. If a block is
+  requested that does not exist within the associated firmware
+  volume (it has a larger index than the last block of the
+  firmware volume), the EraseBlocks() function must return the
+  status code EFI_INVALID_PARAMETER without modifying the contents
+  of the firmware volume. Implementations should be mindful that
+  the firmware volume might be in the WriteDisabled state. If it
+  is in this state, the EraseBlocks() function must return the
+  status code EFI_ACCESS_DENIED without modifying the contents of
+  the firmware volume. All calls to EraseBlocks() must be fully
+  flushed to the hardware before the EraseBlocks() service
+  returns.
+
+  @param This   Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+                instance.
+
+  @param ...    The variable argument list is a list of tuples.
+                Each tuple describes a range of LBAs to erase
+                and consists of the following:
+                - An EFI_LBA that indicates the starting LBA
+                - A UINTN that indicates the number of blocks to
+                  erase.
+
+                The list is terminated with an
+                EFI_LBA_LIST_TERMINATOR. For example, the
+                following indicates that two ranges of blocks
+                (5-7 and 10-11) are to be erased: EraseBlocks
+                (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+  @retval EFI_SUCCESS The erase request successfully
+                      completed.
+
+  @retval EFI_ACCESS_DENIED   The firmware volume is in the
+                              WriteDisabled state.
+  @retval EFI_DEVICE_ERROR  The block device is not functioning
+                            correctly and could not be written.
+                            The firmware device may have been
+                            partially erased.
+  @retval EFI_INVALID_PARAMETER One or more of the LBAs listed
+                                in the variable argument list do
+                                not exist in the firmware volume.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeErase (
+  IN CONST  EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+  ...
+  )
+{
+  VA_LIST       Args;
+  EFI_LBA       Start;
+  UINTN         Length;
+  EFI_STATUS    Status;
+
+  VA_START (Args, This);
+
+  for (Start = VA_ARG (Args, EFI_LBA);
+       Start != EFI_LBA_LIST_TERMINATOR;
+       Start = VA_ARG (Args, EFI_LBA)) {
+    Start += mNvStorageLbaOffset;
+    Length = VA_ARG (Args, UINTN);
+    Status = mIscpDxeProtocol->AmdExecuteEraseFvBlockDxe (mIscpDxeProtocol,
+                                 (Start + mNvStorageLbaOffset) * BLOCK_SIZE,
+                                 Length * BLOCK_SIZE);
+    if (!EFI_ERROR (Status)) {
+      SetMem64 ((VOID *)mNvStorageBase + Start * BLOCK_SIZE,
+                Length * BLOCK_SIZE, ~0UL);
+    }
+  }
+
+  VA_END (Args);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mStyxSpiFvProtocol = {
+  StyxSpiFvDxeGetAttributes,
+  StyxSpiFvDxeSetAttributes,
+  StyxSpiFvDxeGetPhysicalAddress,
+  StyxSpiFvDxeGetBlockSize,
+  StyxSpiFvDxeRead,
+  StyxSpiFvDxeWrite,
+  StyxSpiFvDxeErase
+};
+
+EFI_STATUS
+EFIAPI
+StyxSpiFvDxeInitialize (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS      Status;
+
+  mNvStorageBase = PcdGet64 (PcdFlashNvStorageVariableBase64);
+  mNvStorageLbaOffset = (FixedPcdGet64 (PcdFlashNvStorageOriginalBase) -
+                         SPI_BASE) / BLOCK_SIZE;
+
+  DEBUG ((EFI_D_INFO,
+    "%a: Using NV store FV in-memory copy at 0x%lx, LBA offset == 0x%lx\n",
+    __FUNCTION__, mNvStorageBase, mNvStorageLbaOffset));
+
+  Status = gBS->LocateProtocol (&gAmdIscpDxeProtocolGuid, NULL,
+                  (VOID **)&mIscpDxeProtocol);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_NOTIFY,
+                  VariableClassAddressChangeEvent, NULL,
+                  &gEfiEventVirtualAddressChangeGuid,
+                  &mVirtualAddressChangeEvent);
+  ASSERT_EFI_ERROR (Status);
+
+  return gBS->InstallMultipleProtocolInterfaces (&mStyxSpiFvHandle,
+                &gEfiFirmwareVolumeBlockProtocolGuid, &mStyxSpiFvProtocol,
+                NULL);
+}
diff --git a/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
new file mode 100644
index 0000000..2c1f243
--- /dev/null
+++ b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
@@ -0,0 +1,63 @@
+#/** @file
+#
+#  Component description file for StyxSpiFvDxe module
+#
+#  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = StyxSpiFvDxe
+  FILE_GUID                      = F549FC67-C4A6-4E92-B9BA-297E1F82A1A8
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = StyxSpiFvDxeInitialize
+
+[Sources]
+  StyxSpiFvDxe.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  UefiLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  UefiRuntimeLib
+  DxeServicesTableLib
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+  gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase
+  gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+
+[Protocols]
+  gAmdIscpDxeProtocolGuid                         ## CONSUMES
+  gEfiFirmwareVolumeBlockProtocolGuid             ## PRODUCES
+
+[Depex]
+  gAmdIscpDxeProtocolGuid
diff --git a/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c b/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c
new file mode 100644
index 0000000..d8b70f5
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c
@@ -0,0 +1,77 @@
+/** @file
+
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxHelperLib.h>
+
+#include <PiDxe.h>
+#include <Library/HobLib.h>
+
+extern  EFI_SYSTEM_TABLE        *gST;
+
+#pragma pack(push, 1)
+typedef struct {
+  UINT32 MpId;
+  UINT32 PmuSpi;
+} PMU_INFO;
+
+PMU_INFO mPmuInfo[] = {
+ {0x000, 7},
+ {0x001, 8},
+ {0x100, 9},
+ {0x101, 10},
+ {0x200, 11},
+ {0x201, 12},
+ {0x300, 13},
+ {0x301, 14}
+};
+#pragma pack(pop)
+
+#define MAX_CPUS   sizeof(mPmuInfo) / sizeof(PMU_INFO)
+
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+  UINT32 MpId,
+  UINT32 *PmuSpi
+  )
+{
+  UINT32 i;
+
+  for (i = 0; i < MAX_CPUS; ++i) {
+    if (mPmuInfo[ i ].MpId == MpId) {
+      *PmuSpi = mPmuInfo[ i ].PmuSpi;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_INVALID_PARAMETER;
+}
+
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+  OUT UINTN   *NumEntries
+  )
+{
+  EFI_HOB_GUID_TYPE   *Hob;
+
+  ASSERT (NumEntries != NULL);
+
+  Hob = GetFirstGuidHob (&gAmdStyxMpCoreInfoGuid);
+  if (Hob == NULL) {
+    return NULL;
+  }
+
+  *NumEntries = GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (ARM_CORE_INFO);
+
+  return GET_GUID_HOB_DATA (Hob);
+}
diff --git a/Chips/TexasInstruments/Omap35xx/Library/OmapLib/OmapLib.inf b/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.inf
index b75d686..17681d9 100644
--- a/Chips/TexasInstruments/Omap35xx/Library/OmapLib/OmapLib.inf
+++ b/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.inf
@@ -1,6 +1,7 @@
 #/** @file
 #
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
@@ -13,25 +14,24 @@
 
 [Defines]
   INF_VERSION                    = 0x00010005
-  BASE_NAME                      = OmapLib
-  FILE_GUID                      = d035f5c2-1b92-4746-9f6c-5ff6202970df
-  MODULE_TYPE                    = UEFI_DRIVER
+  BASE_NAME                      = AmdStyxHelperLib
+  FILE_GUID                      = a2a9afbb-6776-4585-8a81-f82f98b4ea53
+  MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = OmapLib
+  LIBRARY_CLASS                  = AmdStyxHelperLib
 
 [Sources.common]
-  OmapLib.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
+  AmdStyxHelperLib.c
 
 [LibraryClasses]
-  DebugLib
+  HobLib
 
-[Protocols]
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
 
 [Guids]
-
-[Pcd]
+  gAmdStyxMpCoreInfoGuid
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S b/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S
new file mode 100644
index 0000000..b7ec02f
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S
@@ -0,0 +1,78 @@
+#/**
+#
+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+#  Derived from:
+#   ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.S
+#
+#**/
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+PrimaryCoreMpid:  .word    0x0
+PrimaryCoreBoot:  .word    0x0
+
+//VOID
+//ArmPlatformPeiBootAction (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformPeiBootAction)
+  ldr  w0, PrimaryCoreBoot
+  cbnz w0, 1f
+
+  // Save the primary CPU MPID
+  mrs  x0, mpidr_el1
+  adr  x2, PrimaryCoreMpid
+  mov  w1, #1
+  stp  w0, w1, [x2]
+1:
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  ldr   w0, PrimaryCoreMpid
+  ret
+
+# IN None
+# OUT x0 = number of cores present in the system
+ASM_FUNC(ArmGetCpuCountPerCluster)
+  MOV32 (w0, FixedPcdGet32 (PcdCoreCount))
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  ldr   w1, PrimaryCoreMpid
+
+  cmp   w0, w1
+  cset  x0, eq
+  ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #7
+  ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
new file mode 100644
index 0000000..8e91691
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
@@ -0,0 +1,76 @@
+#/* @file
+#
+#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+#/**
+#  Derived from:
+#   ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AmdStyxLib
+  FILE_GUID                      = 256ee872-5a3e-4b6e-afd6-63c49ba3d7ba
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  DebugLib
+
+[Sources.common]
+  Styx.c
+  StyxMem.c
+
+[Sources.AARCH64]
+  AArch64/Helper.S  | GCC
+
+[Guids]
+  gAmdStyxMpCoreInfoGuid               ## CONSUMER
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
+
+[Depex]
+  gAmdStyxPlatInitPpiGuid
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
new file mode 100644
index 0000000..2a2d6ff
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
@@ -0,0 +1,67 @@
+#/* @file
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+#/**
+#  Derived from:
+#   ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AmdStyxLibSec
+  FILE_GUID                      = 2228e985-60ae-406e-bdf0-410c6750c7d2
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  DebugLib
+
+[Sources.common]
+  Styx.c
+
+[Sources.AARCH64]
+  AArch64/Helper.S  | GCC
+
+[Guids]
+  gAmdStyxMpCoreInfoGuid               ## CONSUMER
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/Styx.c b/Platforms/AMD/Styx/Library/AmdStyxLib/Styx.c
new file mode 100644
index 0000000..f17a960
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/AmdStyxLib/Styx.c
@@ -0,0 +1,164 @@
+/** @file
+*
+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
+*  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+  Derived from:
+   ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include <Ppi/ArmMpCoreInfo.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+
+
+extern EFI_GUID gAmdStyxMpCoreInfoGuid;
+
+
+UINTN
+ArmGetCpuCountPerCluster (
+  VOID
+  );
+
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  if (!ArmPlatformIsPrimaryCore (MpId)) {
+    return RETURN_SUCCESS;
+  }
+
+  // XXX Place holder XXX ...
+
+  return RETURN_SUCCESS;
+}
+
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+  // Nothing to do here
+}
+
+
+//
+// Return list of cores in the system
+//
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *ArmCoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreInfoTable
+  )
+{
+  EFI_PEI_HOB_POINTERS    Hob;
+
+  if (ArmIsMpCore()) {
+    // Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB
+    for (Hob.Raw = GetHobList (); !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) {
+      // Check for Correct HOB type
+      if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {
+        // Check for correct GUID type
+        if (CompareGuid(&(Hob.Guid->Name), &gAmdStyxMpCoreInfoGuid)) {
+          *ArmCoreInfoTable = (ARM_CORE_INFO *) GET_GUID_HOB_DATA(Hob);
+          *ArmCoreCount = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO);
+          return EFI_SUCCESS;
+        }
+      }
+    }
+  }
+
+  return EFI_UNSUPPORTED;
+}
+
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  if (ArmIsMpCore()) {
+    *PpiListSize = sizeof(gPlatformPpiTable);
+    *PpiList = gPlatformPpiTable;
+  } else {
+    *PpiListSize = 0;
+    *PpiList = NULL;
+  }
+}
+
+
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/StyxMem.c b/Platforms/AMD/Styx/Library/AmdStyxLib/StyxMem.c
new file mode 100644
index 0000000..3b82132
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/AmdStyxLib/StyxMem.c
@@ -0,0 +1,118 @@
+/** @file
+*
+*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+*  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+  Derived from:
+   ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+
+#if !defined(MDEPKG_NDEBUG)
+
+static const char *tblAttrDesc[] =
+{
+  "UNCACHED_UNBUFFERED          ",
+  "NONSECURE_UNCACHED_UNBUFFERED",
+  "WRITE_BACK                   ",
+  "NONSECURE_WRITE_BACK         ",
+  "WRITE_THROUGH                ",
+  "NONSECURE_WRITE_THROUGH      ",
+  "DEVICE                       ",
+  "NONSECURE_DEVICE             "
+};
+#endif
+
+#define LOG_MEM(desc) DEBUG ((EFI_D_ERROR, desc, VirtualMemoryTable[Index].PhysicalBase, \
+                            ( VirtualMemoryTable[Index].PhysicalBase+VirtualMemoryTable[Index].Length - 1), \
+                             VirtualMemoryTable[Index].Length, tblAttrDesc[VirtualMemoryTable[Index].Attributes]));
+
+
+// Number of Virtual Memory Map Descriptors
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          16
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  UINTN                         Index = 0;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+
+  ASSERT(VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+      return;
+  }
+
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+      CacheAttributes = DDR_ATTRIBUTES_CACHED;
+  } else {
+      CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+  }
+
+  DEBUG ((EFI_D_ERROR, " Memory Map\n------------------------------------------------------------------------\n"));
+  DEBUG ((EFI_D_ERROR, "Description                    :        START       -        END         [        SIZE        ]    {              ATTR             }\n"));
+
+  // 0xE000_0000 - 0xEFFF_FFFF: Mapped I/O space
+  VirtualMemoryTable[Index].PhysicalBase   = 0xE0000000UL;
+  VirtualMemoryTable[Index].VirtualBase    = 0xE0000000UL;
+  VirtualMemoryTable[Index].Length         = SIZE_256MB;
+  VirtualMemoryTable[Index].Attributes     = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+  LOG_MEM ("I/O Space [Platform MMIO]      : 0x%016lx - 0x%016lx [ 0x%016lx ]    { %a }\n");
+
+  // 0xF000_0000 - 0xFFFF_FFFF: PCI config space
+  VirtualMemoryTable[++Index].PhysicalBase = 0xF0000000UL;
+  VirtualMemoryTable[Index].VirtualBase    = 0xF0000000UL;
+  VirtualMemoryTable[Index].Length         = SIZE_256MB;
+  VirtualMemoryTable[Index].Attributes     = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+  LOG_MEM ("I/O Space [PCI config space]   : 0x%016lx - 0x%016lx [ 0x%016lx ]    { %a }\n");
+
+  // DRAM
+  VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].VirtualBase    = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].Length         = PcdGet64 (PcdSystemMemorySize);
+  VirtualMemoryTable[Index].Attributes     = CacheAttributes;
+  LOG_MEM ("DRAM                           : 0x%016lx - 0x%016lx [ 0x%016lx ]    { %a }\n");
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase = 0;
+  VirtualMemoryTable[Index].VirtualBase    = 0;
+  VirtualMemoryTable[Index].Length         = 0;
+  VirtualMemoryTable[Index].Attributes     = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c
new file mode 100644
index 0000000..8d8c76a
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c
@@ -0,0 +1,196 @@
+/** @file
+  PCI Host Bridge Library instance for AMD Seattle SOC
+
+  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <PiDxe.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#pragma pack(1)
+typedef struct {
+  ACPI_HID_DEVICE_PATH     AcpiDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
+  {
+    {
+      ACPI_DEVICE_PATH,
+      ACPI_DP,
+      {
+        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+      }
+    },
+    EISA_PNP_ID(0x0A08), // PCI Express
+    0
+  },
+
+  {
+    END_DEVICE_PATH_TYPE,
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    {
+      END_DEVICE_PATH_LENGTH,
+      0
+    }
+  }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+  L"Mem", L"I/O", L"Bus"
+};
+
+/**
+  Return all the root bridge instances in an array.
+
+  @param Count  Return the count of root bridge instances.
+
+  @return All the root bridge instances in an array.
+          The array should be passed into PciHostBridgeFreeRootBridges()
+          when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+  UINTN *Count
+  )
+{
+  PCI_ROOT_BRIDGE     *RootBridge;
+
+  *Count = 1;
+  RootBridge = AllocateZeroPool (*Count * sizeof *RootBridge);
+
+  RootBridge->Segment     = 0;
+
+  RootBridge->Supports    = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
+                            EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
+                            EFI_PCI_ATTRIBUTE_ISA_IO_16 |
+                            EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
+                            EFI_PCI_ATTRIBUTE_VGA_MEMORY |
+                            EFI_PCI_ATTRIBUTE_VGA_IO_16  |
+                            EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
+  RootBridge->Attributes  = RootBridge->Supports;
+
+  RootBridge->DmaAbove4G  = TRUE;
+
+  RootBridge->AllocationAttributes  = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
+                                      EFI_PCI_HOST_BRIDGE_MEM64_DECODE ;
+
+  RootBridge->Bus.Base              = PcdGet32 (PcdPciBusMin);
+  RootBridge->Bus.Limit             = PcdGet32 (PcdPciBusMax);
+  RootBridge->Io.Base               = PcdGet64 (PcdPciIoBase);
+  RootBridge->Io.Limit              = PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1;
+  RootBridge->Mem.Base              = PcdGet32 (PcdPciMmio32Base);
+  RootBridge->Mem.Limit             = PcdGet32 (PcdPciMmio32Base) + PcdGet32 (PcdPciMmio32Size) - 1;
+  RootBridge->MemAbove4G.Base       = PcdGet64 (PcdPciMmio64Base);
+  RootBridge->MemAbove4G.Limit      = PcdGet64 (PcdPciMmio64Base) + PcdGet64 (PcdPciMmio64Size) - 1;
+
+  //
+  // No separate ranges for prefetchable and non-prefetchable BARs
+  //
+  RootBridge->PMem.Base             = MAX_UINT64;
+  RootBridge->PMem.Limit            = 0;
+  RootBridge->PMemAbove4G.Base      = MAX_UINT64;
+  RootBridge->PMemAbove4G.Limit     = 0;
+
+  ASSERT (FixedPcdGet64 (PcdPciMmio32Translation) == 0);
+  ASSERT (FixedPcdGet64 (PcdPciMmio64Translation) == 0);
+
+  RootBridge->NoExtendedConfigSpace = FALSE;
+
+  RootBridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
+
+  return RootBridge;
+}
+
+/**
+  Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+  @param Bridges The root bridge instances array.
+  @param Count   The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+  PCI_ROOT_BRIDGE *Bridges,
+  UINTN           Count
+  )
+{
+  FreePool (Bridges);
+}
+
+/**
+  Inform the platform that the resource conflict happens.
+
+  @param HostBridgeHandle Handle of the Host Bridge.
+  @param Configuration    Pointer to PCI I/O and PCI memory resource
+                          descriptors. The Configuration contains the resources
+                          for all the root bridges. The resource for each root
+                          bridge is terminated with END descriptor and an
+                          additional END is appended indicating the end of the
+                          entire resources. The resource descriptor field
+                          values follow the description in
+                          EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+                          .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+  EFI_HANDLE                        HostBridgeHandle,
+  VOID                              *Configuration
+  )
+{
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+  UINTN                             RootBridgeIndex;
+  DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+  RootBridgeIndex = 0;
+  Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+  while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+    DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+    for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+      ASSERT (Descriptor->ResType <
+              (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
+               sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
+               )
+              );
+      DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+              mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+              Descriptor->AddrLen, Descriptor->AddrRangeMax
+              ));
+      if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+        DEBUG ((EFI_D_ERROR, "     Granularity/SpecificFlag = %ld / %02x%s\n",
+                Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+                ((Descriptor->SpecificFlag &
+                  EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+                  ) != 0) ? L" (Prefetchable)" : L""
+                ));
+      }
+    }
+    //
+    // Skip the END descriptor for root bridge
+    //
+    ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+    Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+                   (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+                   );
+  }
+}
diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
new file mode 100644
index 0000000..3fdaf14
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
@@ -0,0 +1,55 @@
+## @file
+#  PCI Host Bridge Library instance for AMD Seattle SOC
+#
+#  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+#  IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AmdStyxPciHostBridgeLib
+  FILE_GUID                      = 05E7AB83-EF8D-482D-80F8-905B73377A15
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PciHostBridgeLib
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  AmdStyxPciHostBridgeLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  DevicePathLib
+  MemoryAllocationLib
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdPciBusMin
+  gArmTokenSpaceGuid.PcdPciBusMax
+  gArmTokenSpaceGuid.PcdPciIoBase
+  gArmTokenSpaceGuid.PcdPciIoSize
+  gArmTokenSpaceGuid.PcdPciMmio32Base
+  gArmTokenSpaceGuid.PcdPciMmio32Size
+  gArmTokenSpaceGuid.PcdPciMmio32Translation
+  gArmTokenSpaceGuid.PcdPciMmio64Base
+  gArmTokenSpaceGuid.PcdPciMmio64Size
+  gArmTokenSpaceGuid.PcdPciMmio64Translation
diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c
new file mode 100644
index 0000000..70821d1
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c
@@ -0,0 +1,185 @@
+/** @file
+
+  Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016 AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  Derived from:
+   ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.c
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmMmuLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+VOID
+BuildMemoryTypeInformationHob (
+  VOID
+  );
+
+VOID
+InitMmu (
+  VOID
+  )
+{
+  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable;
+  VOID                          *TranslationTableBase;
+  UINTN                         TranslationTableSize;
+  RETURN_STATUS                 Status;
+
+  // Get Virtual Memory Map from the Platform Library
+  ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+  // Note: Because we called PeiServicesInstallPeiMemory() before to call
+  //       InitMmu() the MMU Page Table resides in DRAM (even at the top
+  //       of DRAM as it is the first permanent memory allocation)
+  Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU\n"));
+  }
+}
+
+STATIC
+VOID
+MoveNvStoreImage (
+  VOID
+  )
+{
+  VOID      *OldBase, *NewBase;
+  UINTN     Size;
+
+  //
+  // Move the in-memory image of the NV store firmware volume to a dynamically
+  // allocated buffer. This gets rid of the annoying static memory reservation
+  // at the base of memory where all other UEFI allocations are near the top.
+  //
+  OldBase = (VOID *)FixedPcdGet64 (PcdFlashNvStorageOriginalBase);
+
+  Size = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+         FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+         FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
+
+  NewBase = AllocateAlignedRuntimePages (EFI_SIZE_TO_PAGES (Size), SIZE_64KB);
+  ASSERT (NewBase != NULL);
+
+  CopyMem (NewBase, OldBase, Size);
+
+  DEBUG ((EFI_D_INFO, "%a: Relocating NV store FV from %p to %p\n",
+    __FUNCTION__, OldBase, NewBase));
+
+  PcdSet64 (PcdFlashNvStorageVariableBase64, (UINT64)NewBase);
+
+  PcdSet64 (PcdFlashNvStorageFtwWorkingBase64, (UINT64)NewBase +
+    FixedPcdGet32 (PcdFlashNvStorageVariableSize));
+
+  PcdSet64 (PcdFlashNvStorageFtwSpareBase64, (UINT64)NewBase +
+    FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+    FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize));
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+  FileHandle  - Handle of the file being invoked.
+  PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+  Status -  EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+  IN EFI_PHYSICAL_ADDRESS               UefiMemoryBase,
+  IN UINT64                             UefiMemorySize
+  )
+{
+  UINT64  Base, Size;
+
+  // Ensure PcdSystemMemorySize has been set
+  ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);
+
+  //
+  // Now, the permanent memory has been installed, we can call AllocatePages()
+  //
+
+  Base = PcdGet64 (PcdSystemMemoryBase);
+  Size = PcdGet64 (PcdSystemMemorySize);
+  if (FixedPcdGetBool (PcdTrustedFWSupport)) {
+
+    //
+    // For now, we assume that the trusted firmware region is at the base of
+    // system memory, since that is much easier to deal with.
+    //
+    ASSERT (Base == PcdGet64 (PcdTrustedFWMemoryBase));
+
+    Base += PcdGet64 (PcdTrustedFWMemorySize);
+    Size -= PcdGet64 (PcdTrustedFWMemorySize);
+
+    // Reserved Trusted Firmware region
+    BuildResourceDescriptorHob (
+        EFI_RESOURCE_SYSTEM_MEMORY,
+      ( EFI_RESOURCE_ATTRIBUTE_PRESENT |
+        EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+        EFI_RESOURCE_ATTRIBUTE_TESTED ),
+        PcdGet64 (PcdTrustedFWMemoryBase),
+        PcdGet64 (PcdTrustedFWMemorySize)
+      );
+
+      BuildMemoryAllocationHob (
+        PcdGet64 (PcdTrustedFWMemoryBase),
+        PcdGet64 (PcdTrustedFWMemorySize),
+        EfiReservedMemoryType
+      );
+  }
+
+  // Declare system memory
+  BuildResourceDescriptorHob (
+      EFI_RESOURCE_SYSTEM_MEMORY,
+    ( EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED ),
+      Base,
+      Size
+  );
+
+  // Build Memory Allocation Hob
+  InitMmu ();
+
+  // Optional feature that helps prevent EFI memory map fragmentation.
+  if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+    BuildMemoryTypeInformationHob ();
+  }
+
+  MoveNvStoreImage ();
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
new file mode 100644
index 0000000..1ae0b70
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -0,0 +1,92 @@
+#/** @file
+#
+#  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#**/
+#/**
+#  Derived from:
+#   ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AmdStyxMemoryInitPeiLib
+  FILE_GUID                      = 25466f78-a75a-4aae-be09-a68a347c3228
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = MemoryInitPeiLib|SEC PEIM
+
+[Sources]
+  MemoryInitPeiLib.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  DebugLib
+  HobLib
+  ArmMmuLib
+  ArmPlatformLib
+  PcdLib
+
+[Ppis]
+  gAmdStyxPlatInitPpiGuid              ## CONSUMER
+
+[Guids]
+  gEfiMemoryTypeInformationGuid
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+  gArmTokenSpaceGuid.PcdFdSize
+
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
+
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize
+
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+  gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+
+[Depex]
+  gAmdStyxPlatInitPpiGuid
diff --git a/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c b/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c
new file mode 100644
index 0000000..1b92624
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c
@@ -0,0 +1,277 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  Derived from:
+   ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Guid/EventGroup.h>
+
+#include <Protocol/AmdIscpDxeProtocol.h>
+#include <Iscp.h>
+
+extern  EFI_BOOT_SERVICES       *gBS;
+
+AMD_ISCP_DXE_PROTOCOL *mRtcIscpDxeProtocol = NULL;
+STATIC EFI_EVENT     mRtcVirtualAddrChangeEvent;
+
+
+/**
+  Returns the current time and date information, and the time-keeping capabilities
+  of the hardware platform.
+
+  @param  Time                  A pointer to storage to receive a snapshot of the current time.
+  @param  Capabilities          An optional pointer to a buffer to receive the real time clock
+                                device's capabilities.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER Time is NULL.
+  @retval EFI_DEVICE_ERROR      The time could not be retrieved due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT EFI_TIME                *Time,
+  OUT  EFI_TIME_CAPABILITIES  *Capabilities
+  )
+{
+  ISCP_RTC_INFO  RtcInfo;
+  EFI_STATUS     Status;
+
+  if (!FixedPcdGetBool (PcdIscpSupport)) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  if (mRtcIscpDxeProtocol == NULL) {
+      DEBUG((EFI_D_ERROR, "RTC: ISCP DXE Protocol is NULL!\n"));
+      return EFI_DEVICE_ERROR;
+  }
+
+  //
+  // Fill in Time and Capabilities via data from you RTC
+  //
+  Status = mRtcIscpDxeProtocol->AmdExecuteGetRtc (
+                                  mRtcIscpDxeProtocol,
+                                  &RtcInfo
+                                  );
+  if (EFI_ERROR(Status)) {
+      DEBUG((EFI_D_ERROR, "RTC: Failed GetRtc() via ISCP - Status = %r \n", Status));
+      return Status;
+  }
+
+  Time->Year = RtcInfo.Year;
+  Time->Month = RtcInfo.Month;
+  Time->Day = RtcInfo.Day;
+  Time->Hour = RtcInfo.Hour;
+  Time->Minute = RtcInfo.Minute;
+  Time->Second = RtcInfo.Second;
+
+  return Status;
+}
+
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time                  A pointer to the current time.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+  IN EFI_TIME                *Time
+  )
+{
+  EFI_STATUS     Status;
+  ISCP_RTC_INFO  RtcInfo;
+
+  if (!FixedPcdGetBool (PcdIscpSupport)) {
+    return EFI_DEVICE_ERROR;
+  }
+
+  //
+  // Use Time, to set the time in your RTC hardware
+  //
+  RtcInfo.Year = Time->Year;
+  RtcInfo.Month = Time->Month;
+  RtcInfo.Day = Time->Day;
+  RtcInfo.Hour = Time->Hour;
+  RtcInfo.Minute = Time->Minute;
+  RtcInfo.Second = Time->Second;
+
+  if (mRtcIscpDxeProtocol == NULL) {
+      DEBUG((EFI_D_ERROR, "RTC: ISCP DXE Protocol is NULL!\n"));
+      return EFI_DEVICE_ERROR;
+  }
+
+  Status = mRtcIscpDxeProtocol->AmdExecuteSetRtc (
+                                  mRtcIscpDxeProtocol,
+                                  &RtcInfo
+                                  );
+  if (EFI_ERROR(Status)) {
+      DEBUG((EFI_D_ERROR, "RTC: Failed SetRtc() via ISCP - Status = %r \n", Status));
+      return Status;
+  }
+
+  return Status;
+}
+
+
+/**
+  Returns the current wakeup alarm clock setting.
+
+  @param  Enabled               Indicates if the alarm is currently enabled or disabled.
+  @param  Pending               Indicates if the alarm signal is pending and requires acknowledgement.
+  @param  Time                  The current alarm setting.
+
+  @retval EFI_SUCCESS           The alarm settings were returned.
+  @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+  OUT BOOLEAN     *Enabled,
+  OUT BOOLEAN     *Pending,
+  OUT EFI_TIME    *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+
+/**
+  Sets the system wakeup alarm clock time.
+
+  @param  Enabled               Enable or disable the wakeup alarm.
+  @param  Time                  If Enable is TRUE, the time to set the wakeup alarm for.
+
+  @retval EFI_SUCCESS           If Enable is TRUE, then the wakeup alarm was enabled. If
+                                Enable is FALSE, then the wakeup alarm was disabled.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be set due to a hardware error.
+  @retval EFI_UNSUPPORTED       A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+  IN BOOLEAN      Enabled,
+  OUT EFI_TIME    *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+  This is the declaration of an EFI image entry point. This can be the entry point to an application
+  written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+  @param  ImageHandle           Handle that identifies the loaded image.
+  @param  SystemTable           System Table for this image.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS    Status;
+
+  if (!FixedPcdGetBool (PcdIscpSupport)) {
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Do some initialization if required to turn on the RTC
+  //
+  Status = gBS->LocateProtocol (
+               &gAmdIscpDxeProtocolGuid,
+               NULL,
+               (VOID **)&mRtcIscpDxeProtocol
+               );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "RTC: Failed to Locate ISCP DXE Protocol - Status = %r \n", Status));
+    return Status;
+  }
+
+  //
+  // Register for the virtual address change event
+  //
+  Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  LibRtcVirtualNotifyEvent,
+                  NULL,
+                  &gEfiEventVirtualAddressChangeGuid,
+                  &mRtcVirtualAddrChangeEvent
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+
+/**
+  Fixup internal data so that EFI can be call in virtual mode.
+  Call the passed in Child Notify event and convert any pointers in
+  lib to virtual mode.
+
+  @param[in]    Event   The Event that is being processed
+  @param[in]    Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  //
+  // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+  // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+  // to virtual address. After the OS transistions to calling in virtual mode, all future
+  // runtime calls will be made in virtual mode.
+  //
+  if (FixedPcdGetBool (PcdIscpSupport)) {
+    EfiConvertPointer (0x0, (VOID**)&mRtcIscpDxeProtocol);
+  }
+}
+
+
+
diff --git a/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf b/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
new file mode 100644
index 0000000..9a66934
--- /dev/null
+++ b/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
@@ -0,0 +1,57 @@
+#/** @file
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+#  Derived from:
+#   ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AmdStyxRealTimeClockLib
+  FILE_GUID                      = fd922639-f4ee-4d2f-955b-804e60df1e68
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RealTimeClockLib
+
+[Sources.common]
+  RealTimeClockLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+  IoLib
+  DebugLib
+  UefiRuntimeLib
+  DxeServicesTableLib
+
+[FixedPcd]
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+[Guids]
+  gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+  gAmdIscpDxeProtocolGuid            ## CONSUMER
+
+[Depex]
+  gAmdIscpDxeProtocolGuid
+
+
+
diff --git a/Chips/TexasInstruments/Omap35xx/Library/ResetSystemLib/ResetSystemLib.c b/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.c
index 82f04ea..90eec09 100644
--- a/Chips/TexasInstruments/Omap35xx/Library/ResetSystemLib/ResetSystemLib.c
+++ b/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.c
@@ -1,10 +1,14 @@
 /** @file
-  Template library implementation to support ResetSystem Runtime call.
-
-  Fill in the templates with what ever makes you system reset.
+  Support ResetSystem Runtime call using PSCI calls
 
+  Note: A similar library is implemented in
+  ArmVirtPkg/Library/ArmVirtualizationPsciResetSystemLib
+  So similar issues might exist in this implementation too.
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -15,16 +19,20 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
+/**
+  Derived from:
+   ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
 
+**/
 
 #include <PiDxe.h>
 
-#include <Library/PcdLib.h>
-#include <Library/ArmLib.h>
-#include <Library/CacheMaintenanceLib.h>
+#include <Library/BaseLib.h>
 #include <Library/DebugLib.h>
 #include <Library/EfiResetSystemLib.h>
+#include <Library/ArmSmcLib.h>
 
+#include <IndustryStandard/ArmStdSmc.h>
 
 /**
   Resets the entire platform.
@@ -46,27 +54,37 @@ LibResetSystem (
   IN CHAR16           *ResetData OPTIONAL
   )
 {
-  if (ResetData != NULL) {
-    DEBUG((EFI_D_ERROR, "%s", ResetData));
+  ARM_SMC_ARGS ArmSmcArgs;
+
+  if (!FixedPcdGetBool (PcdTrustedFWSupport)) {
+     return EFI_UNSUPPORTED;
   }
 
   switch (ResetType) {
+  case EfiResetPlatformSpecific:
+    // Map the platform specific reset as reboot
   case EfiResetWarm:
     // Map a warm reset into a cold reset
   case EfiResetCold:
+    // Send a PSCI 0.2 SYSTEM_RESET command
+    ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
+    break;
   case EfiResetShutdown:
-  default:
-    // Perform cold reset of the system.
-    MmioOr32 (PRM_RSTCTRL, RST_DPLL3);
-    while ((MmioRead32 (PRM_RSTST) & GLOBAL_COLD_RST) != 0x1);
+    // Send a PSCI 0.2 SYSTEM_OFF command
+    ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
     break;
+  default:
+    ASSERT (FALSE);
+    return EFI_UNSUPPORTED;
   }
 
-  // If the reset didn't work, return an error.
-  ASSERT (FALSE);
-  return EFI_DEVICE_ERROR;
-}
+  ArmCallSmc (&ArmSmcArgs);
 
+  // We should never be here
+  DEBUG ((EFI_D_ERROR, "%a: PSCI Reset failed\n", __FUNCTION__));
+  CpuDeadLoop ();
+  return EFI_UNSUPPORTED;
+}
 
 
 /**
@@ -85,6 +103,11 @@ LibInitializeResetSystem (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  return EFI_SUCCESS;
+
+  if (FixedPcdGetBool (PcdTrustedFWSupport)) {
+    return EFI_SUCCESS;
+  } else {
+    return EFI_UNSUPPORTED;
+  }
 }
 
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/ResetSystemLib/ResetSystemLib.inf b/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf
index 27bb8d1..5af4c9c 100644
--- a/Platforms/TexasInstruments/BeagleBoard/Library/ResetSystemLib/ResetSystemLib.inf
+++ b/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf
@@ -1,7 +1,10 @@
 #/** @file
-# Reset System lib to make it easy to port new platforms
+# Reset System lib using PSCI hypervisor or secure monitor calls
 #
 # Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -10,40 +13,35 @@
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
+#**/
+#/**
+#  Derived from:
+#   ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
 #
 #**/
 
 [Defines]
   INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardResetSystemLib
-  FILE_GUID                      = 781371a2-3fdd-41d4-96a1-7b34cbc9e895
+  BASE_NAME                      = AmdStyxResetSystemLib
+  FILE_GUID                      = 624f6cc6-c38f-4897-b3b7-8a601701291b
   MODULE_TYPE                    = BASE
   VERSION_STRING                 = 1.0
   LIBRARY_CLASS                  = EfiResetSystemLib
 
-
 [Sources.common]
   ResetSystemLib.c
 
 [Packages]
-  MdePkg/MdePkg.dec
   ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[Pcd.common]
-  gArmTokenSpaceGuid.PcdCpuResetAddress
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+  AmdModulePkg/AmdModulePkg.dec
+  OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
 
 [LibraryClasses]
-  DebugLib
-  ArmLib
-  CacheMaintenanceLib
-  MemoryAllocationLib
-  UefiRuntimeServicesTableLib
-  TimerLib
-  UefiLib
-  UefiBootServicesTableLib
+  PcdLib
+  BaseLib
+  ArmSmcLib
 
-[Pcd]
-  gArmTokenSpaceGuid.PcdFvBaseAddress
+[FixedPcd]
+  gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
diff --git a/Platforms/TexasInstruments/BeagleBoard/License.txt b/Platforms/AMD/Styx/License.txt
index 05dbd36..ff85835 100755..100644
--- a/Platforms/TexasInstruments/BeagleBoard/License.txt
+++ b/Platforms/AMD/Styx/License.txt
@@ -1,16 +1,15 @@
-Copyright (c) 2009-2010, Apple Inc. All rights reserved.
-Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+Copyright (c) 2013 - 2016, AMD Inc. All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
-* Redistributions of source code must retain the above copyright
-  notice, this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright
-  notice, this list of conditions and the following disclaimer in
-  the documentation and/or other materials provided with the
-  distribution.
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in
+   the documentation and/or other materials provided with the
+   distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
diff --git a/Platforms/AMD/Styx/Overdrive1000Board/Binary/PreUefiFirmware.bin b/Platforms/AMD/Styx/Overdrive1000Board/Binary/PreUefiFirmware.bin
new file mode 100644
index 0000000..737fbb2
--- /dev/null
+++ b/Platforms/AMD/Styx/Overdrive1000Board/Binary/PreUefiFirmware.bin
diff --git a/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb b/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb
new file mode 100644
index 0000000..b792b2a
--- /dev/null
+++ b/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb
diff --git a/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dts b/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dts
new file mode 100644
index 0000000..b1fbefe
--- /dev/null
+++ b/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dts
@@ -0,0 +1,446 @@
+/*
+ * DTS file for SoftIron Overdrive 1000, based on AMD Seattle (Rev.B1)
+ *
+ *  Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ *  This program and the accompanying materials are licensed and made available
+ *  under the terms and conditions of the BSD License which accompanies this
+ *  distribution. The full text of the license may be found at
+ *  http://opensource.org/licenses/bsd-license.php
+ *
+ *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ *  IMPLIED.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	model = "SoftIron Overdrive 1000 (AMD Seattle (Rev.B1))";
+	compatible = "amd,seattle-overdrive", "amd,seattle";
+	interrupt-parent = <0x1>;
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	interrupt-controller@e1101000 {
+		compatible = "arm,gic-400", "arm,cortex-a15-gic";
+		interrupt-controller;
+		#interrupt-cells = <0x3>;
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		reg = <0x0 0xe1110000 0x0 0x1000>,
+                      <0x0 0xe112f000 0x0 0x2000>,
+                      <0x0 0xe1140000 0x0 0x10000>,
+                      <0x0 0xe1160000 0x0 0x10000>;
+		interrupts = <0x1 0x9 0xf04>;
+		ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
+		linux,phandle = <0x1>;
+		phandle = <0x1>;
+
+		v2m@e0080000 {
+			compatible = "arm,gic-v2m-frame";
+			msi-controller;
+			reg = <0x0 0x80000 0x0 0x1000>;
+			linux,phandle = <0x4>;
+			phandle = <0x4>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <0x1 0xd 0xff04>,
+                             <0x1 0xe 0xff04>,
+                             <0x1 0xb 0xff04>,
+                             <0x1 0xa 0xff04>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0x0 0x7 0x4>,
+                             <0x0 0x8 0x4>,
+                             <0x0 0x9 0x4>,
+                             <0x0 0xa 0x4>,
+                             <0x0 0xb 0x4>,
+                             <0x0 0xc 0x4>,
+                             <0x0 0xd 0x4>,
+                             <0x0 0xe 0x4>;
+	};
+
+	smb {
+		compatible = "simple-bus";
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+		/*
+		 * dma-ranges is 40-bit address space containing:
+		 * - GICv2m MSI register is at 0xe0080000
+		 * - DRAM range [0x8000000000 to 0xffffffffff]
+		 */
+		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+
+		clk100mhz_0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "adl3clk_100mhz";
+		};
+
+		clk375mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <375000000>;
+			clock-output-names = "ccpclk_375mhz";
+		};
+
+		clk333mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <333000000>;
+			clock-output-names = "sataclk_333mhz";
+			linux,phandle = <0x2>;
+			phandle = <0x2>;
+		};
+
+		clk500mhz_0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <500000000>;
+			clock-output-names = "pcieclk_500mhz";
+		};
+
+		clk500mhz_1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <500000000>;
+			clock-output-names = "dmaclk_500mhz";
+		};
+
+		clk250mhz_4 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "miscclk_250mhz";
+			linux,phandle = <0xd>;
+			phandle = <0xd>;
+		};
+
+		clk100mhz_1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "uartspiclk_100mhz";
+			linux,phandle = <0x3>;
+			phandle = <0x3>;
+		};
+
+		sata@e0300000 {
+			compatible = "snps,dwc-ahci";
+			reg = <0x0 0xe0300000 0x0 0xf0000>;
+			interrupts = <0x0 0x163 0x4>;
+			clocks = <0x2>;
+			dma-coherent;
+		};
+
+		sata@e0d00000 {
+			status = "disabled";
+			compatible = "snps,dwc-ahci";
+			reg = <0x0 0xe0d00000 0x0 0xf0000>;
+			interrupts = <0x0 0x162 0x4>;
+			clocks = <0x2>;
+			dma-coherent;
+		};
+
+		i2c@e1000000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xe1000000 0x0 0x1000>;
+			interrupts = <0x0 0x165 0x4>;
+			clocks = <0xd>;
+		};
+
+		i2c@e0050000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xe0050000 0x0 0x1000>;
+			interrupts = <0x0 0x154 0x4>;
+			clocks = <0xd>;
+		};
+
+		serial@e1010000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xe1010000 0x0 0x1000>;
+			interrupts = <0x0 0x148 0x4>;
+			clocks = <0x3 0x3>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		ssp@e1020000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x0 0xe1020000 0x0 0x1000>;
+			spi-controller;
+			interrupts = <0x0 0x14a 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		ssp@e1030000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x0 0xe1030000 0x0 0x1000>;
+			spi-controller;
+			interrupts = <0x0 0x149 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+			num-cs = <0x1>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+
+			sdcard@0 {
+				compatible = "mmc-spi-slot";
+				reg = <0x0>;
+				spi-max-frequency = <20000000>;
+				voltage-ranges = <3200 3400>;
+				pl022,hierarchy = <0x0>;
+				pl022,interface = <0x0>;
+				pl022,com-mode = <0x0>;
+				pl022,rx-level-trig = <0x0>;
+				pl022,tx-level-trig = <0x0>;
+			};
+		};
+
+		gpio@e1050000 { /* [0 : 7] */
+			compatible = "arm,pl061", "arm,primecell";
+			#gpio-cells = <0x2>;
+			reg = <0x0 0xe1050000 0x0 0x1000>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupts = <0x0 0x166 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio@e0020000 { /* [8 : 15] */
+			status = "disabled";
+			compatible = "arm,pl061", "arm,primecell";
+			#gpio-cells = <0x2>;
+			reg = <0x0 0xe0020000 0x0 0x1000>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupts = <0x0 0x16e 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio@e0030000 { /* [16 : 23] */
+			status = "disabled";
+			compatible = "arm,pl061", "arm,primecell";
+			#gpio-cells = <0x2>;
+			reg = <0x0 0xe0030000 0x0 0x1000>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupts = <0x0 0x16d 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio@e0080000 { /* [24] */
+			compatible = "arm,pl061", "arm,primecell";
+			#gpio-cells = <0x2>;
+			reg = <0x0 0xe0080000 0x0 0x1000>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupts = <0x0 0x169 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		ccp: ccp@e0100000 {
+			compatible = "amd,ccp-seattle-v1a";
+			reg = <0x0 0xe0100000 0x0 0x10000>;
+			interrupts = <0x0 0x3 0x4>;
+			dma-coherent;
+			amd,zlib-support = <0x1>;
+		};
+
+		pcie: pcie@f0000000 {
+			compatible = "pci-host-ecam-generic";
+			#address-cells = <0x3>;
+			#size-cells = <0x2>;
+			#interrupt-cells = <0x1>;
+			device_type = "pci";
+			bus-range = <0x0 0x7f>;
+			msi-parent = <0x4>;
+			reg = <0x0 0xf0000000 0x0 0x10000000>;
+			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+			interrupt-map = <0x1000 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>,
+                                        <0x1000 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>,
+                                        <0x1000 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>,
+                                        <0x1000 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>;
+			dma-coherent;
+			dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
+			ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
+                                 <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
+                                 <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
+		};
+
+		ccn@0xe8000000 {
+			compatible = "arm,ccn-504";
+			reg = <0x0 0xe8000000 0x0 0x1000000>;
+			interrupts = <0x0 0x17c 0x4>;
+		};
+
+                gwdt@e0bb0000 {
+			status = "disabled";
+                        compatible = "arm,sbsa-gwdt";
+                        reg = <0x0 0xe0bb0000 0x0 0x10000
+			       0x0 0xe0bc0000 0x0 0x10000>;
+                        reg-names = "refresh", "control";
+                        interrupts = <0x0 0x151 0x4>;
+                        interrupt-names = "ws0";
+                };
+
+		kcs@e0010000 {
+			status = "disabled";
+			compatible = "ipmi-kcs";
+			device_type = "ipmi";
+			reg = <0x0 0xe0010000 0 0x8>;
+			interrupts = <0 389 4>;
+			interrupt-names = "ipmi_kcs";
+			reg-size = <1>;
+			reg-spacing = <4>;
+		};
+
+		clk250mhz_0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "xgmacclk0_dma_250mhz";
+			linux,phandle = <0x5>;
+			phandle = <0x5>;
+		};
+
+		clk250mhz_1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "xgmacclk0_ptp_250mhz";
+			linux,phandle = <0x6>;
+			phandle = <0x6>;
+		};
+
+		clk250mhz_2 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "xgmacclk1_dma_250mhz";
+			linux,phandle = <0x7>;
+			phandle = <0x7>;
+		};
+
+		clk250mhz_3 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "xgmacclk1_ptp_250mhz";
+			linux,phandle = <0x8>;
+			phandle = <0x8>;
+		};
+
+		phy@e1240800 {
+			status = "disabled";
+			compatible = "amd,xgbe-phy-seattle-v1a";
+			reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
+                              <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
+                              <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
+			interrupts = <0x0 0x143 0x4>;
+			amd,speed-set = <0x0>;
+			amd,serdes-blwc = <0x1 0x1 0x0>;
+			amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+			amd,serdes-pq-skew = <0xa 0xa 0x12>;
+			amd,serdes-tx-amp = <0xf 0xf 0xa>;
+			amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+			amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+			linux,phandle = <0x9>;
+			phandle = <0x9>;
+		};
+
+		phy@e1240c00 {
+			status = "disabled";
+			compatible = "amd,xgbe-phy-seattle-v1a";
+			reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
+                              <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
+                              <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
+			interrupts = <0x0 0x142 0x4>;
+			amd,speed-set = <0x0>;
+			amd,serdes-blwc = <0x1 0x1 0x0>;
+			amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+			amd,serdes-pq-skew = <0xa 0xa 0x12>;
+			amd,serdes-tx-amp = <0xf 0xf 0xa>;
+			amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+			amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+			linux,phandle = <0xa>;
+			phandle = <0xa>;
+		};
+
+		xgmac@e0700000 {
+			status = "disabled";
+			compatible = "amd,xgbe-seattle-v1a";
+			reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
+			interrupts = <0x0 0x145 0x4>,
+                                     <0x0 0x15a 0x1>,
+                                     <0x0 0x15b 0x1>,
+                                     <0x0 0x15c 0x1>,
+                                     <0x0 0x15d 0x1>;
+			amd,per-channel-interrupt;
+			mac-address = [02 a1 a2 a3 a4 a5];
+			clocks = <0x5 0x6>;
+			clock-names = "dma_clk", "ptp_clk";
+			phy-handle = <0x9>;
+			phy-mode = "xgmii";
+			#stream-id-cells = <0x18>;
+			dma-coherent;
+			linux,phandle = <0xb>;
+			phandle = <0xb>;
+		};
+
+		xgmac@e0900000 {
+			status = "disabled";
+			compatible = "amd,xgbe-seattle-v1a";
+			reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
+			interrupts = <0x0 0x144 0x4>,
+                                     <0x0 0x155 0x1>,
+                                     <0x0 0x156 0x1>,
+                                     <0x0 0x157 0x1>,
+                                     <0x0 0x158 0x1>;
+			amd,per-channel-interrupt;
+			mac-address = [02 b1 b2 b3 b4 b5];
+			clocks = <0x7 0x8>;
+			clock-names = "dma_clk", "ptp_clk";
+			phy-handle = <0xa>;
+			phy-mode = "xgmii";
+			#stream-id-cells = <0x18>;
+			dma-coherent;
+			linux,phandle = <0xc>;
+			phandle = <0xc>;
+		};
+	};
+
+	chosen {
+		stdout-path = "/smb/serial@e1010000";
+		/* Note:
+		 * Linux support for pci-probe-only DT is not
+		 * stable. Disable this for now and let Linux
+		 * take care of the resource assignment.
+		 */
+		// linux,pci-probe-only;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2", "arm,psci";
+		method = "smc";
+	};
+};
+
+
diff --git a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc
new file mode 100644
index 0000000..60ceb71
--- /dev/null
+++ b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc
@@ -0,0 +1,703 @@
+#
+#  Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and made
+#  available under the terms and conditions of the BSD License which
+#  accompanies this distribution.  The full text of the license may
+#  be found at http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+
+DEFINE NUM_CORES    = 4
+DEFINE DO_PSCI      = 1
+DEFINE DO_ISCP      = 1
+DEFINE DO_KCS       = 1
+
+  PLATFORM_NAME                  = Overdrive1000
+  PLATFORM_GUID                  = 36774DD7-20DE-4C5B-8722-f8861DFF1F16
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/Overdrive1000
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.fdf
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+  #
+  # Allow dynamic PCDs
+  #
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+  # Networking Requirements
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+  # ARM Architectural Libraries
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+  # ARM PL011 UART Driver
+  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+  #
+  # PCI support
+  #
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+  PciHostBridgeLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
+
+  #
+  # Styx specific libraries
+  #
+  AmdSataInit|AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
+  AmdStyxAcpiLib|OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf
+  EfiResetSystemLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf
+  RealTimeClockLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  #
+  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+  # in the debugger will show load and unload commands for symbols. You can cut and paste this
+  # into the command window to load symbols. We should be able to use a script to do this, but
+  # the version of RVD I have does not support scripts accessing system memory.
+  #
+  #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+  #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
+
+  ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+  DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+  # Trustzone Support
+  ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
+  MemoryInitPeiLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEIM]
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+###################################################################################################
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+#                        the default flags for a module. These flags are appended to any
+#                        standard flags that are defined by the build process.
+###################################################################################################
+
+[BuildOptions]
+  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+
+  *_*_*_ASL_FLAGS               = -tc -li -l -so
+  *_*_*_ASLPP_FLAGS             = $(ARCHCC_FLAGS)
+  *_*_*_ASLCC_FLAGS             = $(ARCHCC_FLAGS)
+
+  GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+  GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+
+  GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  # All pages are cached by default
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle
+  ## created by ConsplitterDxe. It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+  # DEBUG_ASSERT_ENABLED       0x01
+  # DEBUG_PRINT_ENABLED        0x02
+  # DEBUG_CODE_ENABLED         0x04
+  # CLEAR_MEMORY_ENABLED       0x08
+  # ASSERT_BREAKPOINT_ENABLED  0x10
+  # ASSERT_DEADLOOP_ENABLED    0x20
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+  #  DEBUG_INIT      0x00000001  // Initialization
+  #  DEBUG_WARN      0x00000002  // Warnings
+  #  DEBUG_LOAD      0x00000004  // Load events
+  #  DEBUG_FS        0x00000008  // EFI File system
+  #  DEBUG_POOL      0x00000010  // Alloc & Free's
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free's
+  #  DEBUG_INFO      0x00000040  // Verbose
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+  #  DEBUG_VARIABLE  0x00000100  // Variable
+  #  DEBUG_BM        0x00000400  // Boot Manager
+  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+  #  DEBUG_NET       0x00004000  // SNI Driver
+  #  DEBUG_UNDI      0x00010000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
+  #  DEBUG_EVENT     0x00080000  // Event messages
+  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
+  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
+  #  DEBUG_ERROR     0x80000000  // Error
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"SoftIron Overdrive 1000"
+
+  # Number of configured cores
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES)
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800
+
+  # Declare system memory base
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000
+
+  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+  # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
+  # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
+  # that)
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
+  #
+  # ARM PrimeCell
+  #
+
+  ## PL011 - Serial Terminal (Atlas UART)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0E1010000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+  # serial port is clocked at 100MHz
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|100000000
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0E1010000
+  gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200
+
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xE1110000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
+
+  #
+  # ARM Architectual Timer Frequency
+  #
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000
+
+  #
+  # 2 ports active on Overdrive 1000
+  #
+  gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2
+  gAmdStyxTokenSpaceGuid.PcdSata1PortCount|0
+
+  # PCIe Support
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
+
+  gArmTokenSpaceGuid.PcdPciBusMin|0x0
+  gArmTokenSpaceGuid.PcdPciBusMax|0xFF
+
+  gArmTokenSpaceGuid.PcdPciIoBase|0x1000
+  gArmTokenSpaceGuid.PcdPciIoSize|0xF000
+  gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFFF0000
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
+
+  gArmTokenSpaceGuid.PcdPciMmio32Base|0x40000000
+  gArmTokenSpaceGuid.PcdPciMmio32Size|0x80000000
+  gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+
+  gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+  gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000
+  gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
+  ## Use PCI emulation for ATA PassThru
+  # gEfiMdeModulePkgTokenSpaceGuid.PcdAtaPassThruPciEmulation|TRUE
+
+  ## ACPI (no tables < 4GB)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+!if $(DO_PSCI)
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE
+!else
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE
+!endif
+
+!if $(DO_ISCP)
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE
+!else
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE
+!endif
+
+  # SMBIOS 3.0 only
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
+  gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000
+
+  # map the stack as non-executable when entering the DXE phase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+
+[PcdsPatchableInModule]
+# PCIe Configuration: x4x2x2 (=2 See Include/FDKGionb.h)
+  gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|0
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1
+  gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE
+
+[PcdsDynamicDefault.common]
+  gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
+
+[PcdsDynamicExHii.common.DEFAULT]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  AmdModulePkg/Iscp/IscpPei.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+  ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+  ArmPkg/Drivers/CpuPei/CpuPei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  #
+  # Console IO support
+  #
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  #
+  # Environment Variables Protocol
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+      TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+      VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  }
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+  #
+  # Iscp support
+  #
+  AmdModulePkg/Iscp/IscpDxe.inf
+
+  #
+  # FDT support
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf {
+    <LibraryClasses>
+      # deprecated BdsLib from the ARM BDS
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+      FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  }
+
+  #
+  # PCI support
+  #
+  AmdModulePkg/Gionb/Gionb.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
+  # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+  #
+  # USB Support
+  #
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # Marvell Yukon Ethernet (Overdrive 1000 has 88e8059)
+  #
+  OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
+
+  #
+  # Networking stack
+  #
+  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf {
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+  }
+  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+  #
+  # Core Info
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
+
+  #
+  # Crypto Accelerator support (RNG only)
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+      FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.fdf b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.fdf
new file mode 100644
index 0000000..170d80b
--- /dev/null
+++ b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.fdf
@@ -0,0 +1,414 @@
+#
+#  Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.Overdrive1000_ROM]
+BaseAddress   = 0x8000C80000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00500000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x500
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+FILE = OpenPlatformPkg/Platforms/AMD/Styx/Overdrive1000Board/Binary/PreUefiFirmware.bin
+
+0x00200000|0x00260000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = STYX_EFI
+
+!include OpenPlatformPkg/Platforms/AMD/Styx/Common/Varstore.fdf.inc
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid         = 94f067ae-2aa6-4b30-aa07-4e47fe518bb8
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  #
+  # Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Environment Variables Protocol
+  #
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+  #
+  # Iscp support
+  #
+  INF AmdModulePkg/Iscp/IscpDxe.inf
+
+  #
+  # FDT support
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf
+
+  FILE FREEFORM = PCD(gAmdStyxTokenSpaceGuid.PcdStyxFdt) {
+    SECTION RAW = OpenPlatformPkg/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb
+  }
+
+  #
+  # PCI support
+  #
+  INF AmdModulePkg/Gionb/Gionb.inf
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+  #
+  # USB Support
+  #
+  INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!if $(DO_XGBE)
+  #
+  # SNP support
+  #
+  INF AmdModulePkg/SnpDxe/SnpDxePort0.inf
+  INF AmdModulePkg/SnpDxe/SnpDxePort1.inf
+!endif
+
+  #
+  # Marvell Ethernet Driver (Overdrive 1000)
+  #
+  INF OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
+
+  #
+  # Networking stack
+  #
+  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+  #
+  # Core Info
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+  #
+  # Crypto Accelerator support (RNG only)
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+[FV.STYX_EFI]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  INF AmdModulePkg/Iscp/IscpPei.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE Align = 4K                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE Align = Auto              $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE Align = Auto           $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.Binary]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       |.depex
+     TE       TE Align = Auto           |.efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER.Binary]
+  FILE DRIVER = $(NAMED_GUID) {
+    PE32         PE32                   |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.Binary]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional |.depex
+    PE32         PE32                   |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)"     Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ASL                |.aml
+  }
+
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Binary/PreUefiFirmware.bin b/Platforms/AMD/Styx/OverdriveBoard/Binary/PreUefiFirmware.bin
new file mode 100644
index 0000000..8da3b4f
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/Binary/PreUefiFirmware.bin
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb
new file mode 100644
index 0000000..0c0468d
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts
new file mode 100644
index 0000000..dab3c2c
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts
@@ -0,0 +1,446 @@
+/*
+ * DTS file for AMD Seattle (Rev.B) Overdrive Development Board
+ *
+ *  Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ *  This program and the accompanying materials are licensed and made available
+ *  under the terms and conditions of the BSD License which accompanies this
+ *  distribution. The full text of the license may be found at
+ *  http://opensource.org/licenses/bsd-license.php
+ *
+ *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ *  IMPLIED.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	model = "AMD Seattle (Rev.B) Development Board (Overdrive)";
+	compatible = "amd,seattle-overdrive", "amd,seattle";
+	interrupt-parent = <0x1>;
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	interrupt-controller@e1101000 {
+		compatible = "arm,gic-400", "arm,cortex-a15-gic";
+		interrupt-controller;
+		#interrupt-cells = <0x3>;
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		reg = <0x0 0xe1110000 0x0 0x1000>,
+                      <0x0 0xe112f000 0x0 0x2000>,
+                      <0x0 0xe1140000 0x0 0x10000>,
+                      <0x0 0xe1160000 0x0 0x10000>;
+		interrupts = <0x1 0x9 0xf04>;
+		ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
+		linux,phandle = <0x1>;
+		phandle = <0x1>;
+
+		v2m@e0080000 {
+			compatible = "arm,gic-v2m-frame";
+			msi-controller;
+			reg = <0x0 0x80000 0x0 0x1000>;
+			linux,phandle = <0x4>;
+			phandle = <0x4>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <0x1 0xd 0xff04>,
+                             <0x1 0xe 0xff04>,
+                             <0x1 0xb 0xff04>,
+                             <0x1 0xa 0xff04>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0x0 0x7 0x4>,
+                             <0x0 0x8 0x4>,
+                             <0x0 0x9 0x4>,
+                             <0x0 0xa 0x4>,
+                             <0x0 0xb 0x4>,
+                             <0x0 0xc 0x4>,
+                             <0x0 0xd 0x4>,
+                             <0x0 0xe 0x4>;
+	};
+
+	smb {
+		compatible = "simple-bus";
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+		/*
+		 * dma-ranges is 40-bit address space containing:
+		 * - GICv2m MSI register is at 0xe0080000
+		 * - DRAM range [0x8000000000 to 0xffffffffff]
+		 */
+		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+
+		clk100mhz_0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "adl3clk_100mhz";
+		};
+
+		clk375mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <375000000>;
+			clock-output-names = "ccpclk_375mhz";
+		};
+
+		clk333mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <333000000>;
+			clock-output-names = "sataclk_333mhz";
+			linux,phandle = <0x2>;
+			phandle = <0x2>;
+		};
+
+		clk500mhz_0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <500000000>;
+			clock-output-names = "pcieclk_500mhz";
+		};
+
+		clk500mhz_1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <500000000>;
+			clock-output-names = "dmaclk_500mhz";
+		};
+
+		clk250mhz_4 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "miscclk_250mhz";
+			linux,phandle = <0xd>;
+			phandle = <0xd>;
+		};
+
+		clk100mhz_1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "uartspiclk_100mhz";
+			linux,phandle = <0x3>;
+			phandle = <0x3>;
+		};
+
+		sata@e0300000 {
+			compatible = "snps,dwc-ahci";
+			reg = <0x0 0xe0300000 0x0 0xf0000>;
+			interrupts = <0x0 0x163 0x4>;
+			clocks = <0x2>;
+			dma-coherent;
+		};
+
+		sata@e0d00000 {
+			status = "disabled";
+			compatible = "snps,dwc-ahci";
+			reg = <0x0 0xe0d00000 0x0 0xf0000>;
+			interrupts = <0x0 0x162 0x4>;
+			clocks = <0x2>;
+			dma-coherent;
+		};
+
+		i2c@e1000000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xe1000000 0x0 0x1000>;
+			interrupts = <0x0 0x165 0x4>;
+			clocks = <0xd>;
+		};
+
+		i2c@e0050000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0xe0050000 0x0 0x1000>;
+			interrupts = <0x0 0x154 0x4>;
+			clocks = <0xd>;
+		};
+
+		serial@e1010000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xe1010000 0x0 0x1000>;
+			interrupts = <0x0 0x148 0x4>;
+			clocks = <0x3 0x3>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		ssp@e1020000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x0 0xe1020000 0x0 0x1000>;
+			spi-controller;
+			interrupts = <0x0 0x14a 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		ssp@e1030000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x0 0xe1030000 0x0 0x1000>;
+			spi-controller;
+			interrupts = <0x0 0x149 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+			num-cs = <0x1>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+
+			sdcard@0 {
+				compatible = "mmc-spi-slot";
+				reg = <0x0>;
+				spi-max-frequency = <20000000>;
+				voltage-ranges = <3200 3400>;
+				pl022,hierarchy = <0x0>;
+				pl022,interface = <0x0>;
+				pl022,com-mode = <0x0>;
+				pl022,rx-level-trig = <0x0>;
+				pl022,tx-level-trig = <0x0>;
+			};
+		};
+
+		gpio@e1050000 { /* [0 : 7] */
+			compatible = "arm,pl061", "arm,primecell";
+			#gpio-cells = <0x2>;
+			reg = <0x0 0xe1050000 0x0 0x1000>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupts = <0x0 0x166 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio@e0020000 { /* [8 : 15] */
+			status = "disabled";
+			compatible = "arm,pl061", "arm,primecell";
+			#gpio-cells = <0x2>;
+			reg = <0x0 0xe0020000 0x0 0x1000>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupts = <0x0 0x16e 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio@e0030000 { /* [16 : 23] */
+			status = "disabled";
+			compatible = "arm,pl061", "arm,primecell";
+			#gpio-cells = <0x2>;
+			reg = <0x0 0xe0030000 0x0 0x1000>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupts = <0x0 0x16d 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio@e0080000 { /* [24] */
+			compatible = "arm,pl061", "arm,primecell";
+			#gpio-cells = <0x2>;
+			reg = <0x0 0xe0080000 0x0 0x1000>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupts = <0x0 0x169 0x4>;
+			clocks = <0x3>;
+			clock-names = "apb_pclk";
+		};
+
+		ccp: ccp@e0100000 {
+			compatible = "amd,ccp-seattle-v1a";
+			reg = <0x0 0xe0100000 0x0 0x10000>;
+			interrupts = <0x0 0x3 0x4>;
+			dma-coherent;
+			amd,zlib-support = <0x1>;
+		};
+
+		pcie: pcie@f0000000 {
+			compatible = "pci-host-ecam-generic";
+			#address-cells = <0x3>;
+			#size-cells = <0x2>;
+			#interrupt-cells = <0x1>;
+			device_type = "pci";
+			bus-range = <0x0 0x7f>;
+			msi-parent = <0x4>;
+			reg = <0x0 0xf0000000 0x0 0x10000000>;
+			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+			interrupt-map = <0x1000 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>,
+                                        <0x1000 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>,
+                                        <0x1000 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>,
+                                        <0x1000 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>;
+			dma-coherent;
+			dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
+			ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
+                                 <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
+                                 <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
+		};
+
+		ccn@0xe8000000 {
+			compatible = "arm,ccn-504";
+			reg = <0x0 0xe8000000 0x0 0x1000000>;
+			interrupts = <0x0 0x17c 0x4>;
+		};
+
+                gwdt@e0bb0000 {
+			status = "disabled";
+                        compatible = "arm,sbsa-gwdt";
+                        reg = <0x0 0xe0bb0000 0x0 0x10000
+			       0x0 0xe0bc0000 0x0 0x10000>;
+                        reg-names = "refresh", "control";
+                        interrupts = <0x0 0x151 0x4>;
+                        interrupt-names = "ws0";
+                };
+
+		kcs@e0010000 {
+			status = "disabled";
+			compatible = "ipmi-kcs";
+			device_type = "ipmi";
+			reg = <0x0 0xe0010000 0 0x8>;
+			interrupts = <0 389 4>;
+			interrupt-names = "ipmi_kcs";
+			reg-size = <1>;
+			reg-spacing = <4>;
+		};
+
+		clk250mhz_0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "xgmacclk0_dma_250mhz";
+			linux,phandle = <0x5>;
+			phandle = <0x5>;
+		};
+
+		clk250mhz_1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "xgmacclk0_ptp_250mhz";
+			linux,phandle = <0x6>;
+			phandle = <0x6>;
+		};
+
+		clk250mhz_2 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "xgmacclk1_dma_250mhz";
+			linux,phandle = <0x7>;
+			phandle = <0x7>;
+		};
+
+		clk250mhz_3 {
+			compatible = "fixed-clock";
+			#clock-cells = <0x0>;
+			clock-frequency = <250000000>;
+			clock-output-names = "xgmacclk1_ptp_250mhz";
+			linux,phandle = <0x8>;
+			phandle = <0x8>;
+		};
+
+		phy@e1240800 {
+			status = "disabled";
+			compatible = "amd,xgbe-phy-seattle-v1a";
+			reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
+                              <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
+                              <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
+			interrupts = <0x0 0x143 0x4>;
+			amd,speed-set = <0x0>;
+			amd,serdes-blwc = <0x1 0x1 0x0>;
+			amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+			amd,serdes-pq-skew = <0xa 0xa 0x12>;
+			amd,serdes-tx-amp = <0xf 0xf 0xa>;
+			amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+			amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+			linux,phandle = <0x9>;
+			phandle = <0x9>;
+		};
+
+		phy@e1240c00 {
+			status = "disabled";
+			compatible = "amd,xgbe-phy-seattle-v1a";
+			reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
+                              <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
+                              <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
+			interrupts = <0x0 0x142 0x4>;
+			amd,speed-set = <0x0>;
+			amd,serdes-blwc = <0x1 0x1 0x0>;
+			amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+			amd,serdes-pq-skew = <0xa 0xa 0x12>;
+			amd,serdes-tx-amp = <0xf 0xf 0xa>;
+			amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+			amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+			linux,phandle = <0xa>;
+			phandle = <0xa>;
+		};
+
+		xgmac@e0700000 {
+			status = "disabled";
+			compatible = "amd,xgbe-seattle-v1a";
+			reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
+			interrupts = <0x0 0x145 0x4>,
+                                     <0x0 0x15a 0x1>,
+                                     <0x0 0x15b 0x1>,
+                                     <0x0 0x15c 0x1>,
+                                     <0x0 0x15d 0x1>;
+			amd,per-channel-interrupt;
+			mac-address = [02 a1 a2 a3 a4 a5];
+			clocks = <0x5 0x6>;
+			clock-names = "dma_clk", "ptp_clk";
+			phy-handle = <0x9>;
+			phy-mode = "xgmii";
+			#stream-id-cells = <0x18>;
+			dma-coherent;
+			linux,phandle = <0xb>;
+			phandle = <0xb>;
+		};
+
+		xgmac@e0900000 {
+			status = "disabled";
+			compatible = "amd,xgbe-seattle-v1a";
+			reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
+			interrupts = <0x0 0x144 0x4>,
+                                     <0x0 0x155 0x1>,
+                                     <0x0 0x156 0x1>,
+                                     <0x0 0x157 0x1>,
+                                     <0x0 0x158 0x1>;
+			amd,per-channel-interrupt;
+			mac-address = [02 b1 b2 b3 b4 b5];
+			clocks = <0x7 0x8>;
+			clock-names = "dma_clk", "ptp_clk";
+			phy-handle = <0xa>;
+			phy-mode = "xgmii";
+			#stream-id-cells = <0x18>;
+			dma-coherent;
+			linux,phandle = <0xc>;
+			phandle = <0xc>;
+		};
+	};
+
+	chosen {
+		stdout-path = "/smb/serial@e1010000";
+		/* Note:
+		 * Linux support for pci-probe-only DT is not
+		 * stable. Disable this for now and let Linux
+		 * take care of the resource assignment.
+		 */
+		// linux,pci-probe-only;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2", "arm,psci";
+		method = "smc";
+	};
+};
+
+
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
new file mode 100644
index 0000000..a236836
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
@@ -0,0 +1,725 @@
+#
+#  Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+#  This program and the accompanying materials are licensed and made
+#  available under the terms and conditions of the BSD License which
+#  accompanies this distribution.  The full text of the license may
+#  be found at http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+
+DEFINE DO_XGBE      = 1
+DEFINE NUM_CORES    = 8
+DEFINE DO_PSCI      = 1
+DEFINE DO_ISCP      = 1
+DEFINE DO_KCS       = 1
+
+  PLATFORM_NAME                  = Overdrive
+  PLATFORM_GUID                  = B2296C02-9DA1-4CD1-BD48-4D4F0F1276EB
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/Overdrive
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+  #
+  # Allow dynamic PCDs
+  #
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+  # Networking Requirements
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+  # ARM Architectural Libraries
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+  # ARM PL011 UART Driver
+  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+  #
+  # PCI support
+  #
+  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+  PciHostBridgeLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
+
+  #
+  # Styx specific libraries
+  #
+  AmdSataInit|AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
+  AmdStyxAcpiLib|OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf
+  EfiResetSystemLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf
+  RealTimeClockLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  #
+  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+  # in the debugger will show load and unload commands for symbols. You can cut and paste this
+  # into the command window to load symbols. We should be able to use a script to do this, but
+  # the version of RVD I have does not support scripts accessing system memory.
+  #
+  #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+  #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
+
+  ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+  DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+  # Trustzone Support
+  ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
+  MemoryInitPeiLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+  PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+  PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+###################################################################################################
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+#                        the default flags for a module. These flags are appended to any
+#                        standard flags that are defined by the build process.
+###################################################################################################
+
+[BuildOptions]
+  RVCT:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+  GCC:RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG
+
+  *_*_*_ASL_FLAGS               = -tc -li -l -so
+  *_*_*_ASLPP_FLAGS             = $(ARCHCC_FLAGS)
+  *_*_*_ASLCC_FLAGS             = $(ARCHCC_FLAGS)
+
+  GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+  GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+
+  GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  # All pages are cached by default
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle
+  ## created by ConsplitterDxe. It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+  # DEBUG_ASSERT_ENABLED       0x01
+  # DEBUG_PRINT_ENABLED        0x02
+  # DEBUG_CODE_ENABLED         0x04
+  # CLEAR_MEMORY_ENABLED       0x08
+  # ASSERT_BREAKPOINT_ENABLED  0x10
+  # ASSERT_DEADLOOP_ENABLED    0x20
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+  #  DEBUG_INIT      0x00000001  // Initialization
+  #  DEBUG_WARN      0x00000002  // Warnings
+  #  DEBUG_LOAD      0x00000004  // Load events
+  #  DEBUG_FS        0x00000008  // EFI File system
+  #  DEBUG_POOL      0x00000010  // Alloc & Free's
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free's
+  #  DEBUG_INFO      0x00000040  // Verbose
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+  #  DEBUG_VARIABLE  0x00000100  // Variable
+  #  DEBUG_BM        0x00000400  // Boot Manager
+  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+  #  DEBUG_NET       0x00004000  // SNI Driver
+  #  DEBUG_UNDI      0x00010000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
+  #  DEBUG_EVENT     0x00080000  // Event messages
+  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
+  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
+  #  DEBUG_ERROR     0x80000000  // Error
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD Seattle"
+
+  # Number of configured cores
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES)
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800
+
+  # Declare system memory base
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000
+
+  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+  # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
+  # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
+  # that)
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
+  #
+  # ARM PrimeCell
+  #
+
+  ## PL011 - Serial Terminal (Atlas UART)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0E1010000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+  # serial port is clocked at 100MHz
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|100000000
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0E1010000
+  gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200
+
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xE1110000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
+
+  #
+  # ARM Architectual Timer Frequency
+  #
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000
+
+  #
+  # Overdrive B1 has 14 SATA ports across 2 controllers.
+  #
+  gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8
+  gAmdStyxTokenSpaceGuid.PcdSata1PortCount|6
+
+  # PCIe Support
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
+
+  gArmTokenSpaceGuid.PcdPciBusMin|0x0
+  gArmTokenSpaceGuid.PcdPciBusMax|0xFF
+
+  gArmTokenSpaceGuid.PcdPciIoBase|0x1000
+  gArmTokenSpaceGuid.PcdPciIoSize|0xF000
+  gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFFF0000
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
+
+  gArmTokenSpaceGuid.PcdPciMmio32Base|0x40000000
+  gArmTokenSpaceGuid.PcdPciMmio32Size|0x80000000
+  gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+
+  gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+  gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000
+  gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
+  ## Use PCI emulation for ATA PassThru
+  # gEfiMdeModulePkgTokenSpaceGuid.PcdAtaPassThruPciEmulation|TRUE
+
+  ## ACPI (no tables < 4GB)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+!if $(DO_PSCI)
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE
+!else
+  gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE
+!endif
+
+!if $(DO_ISCP)
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE
+!else
+  gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE
+!endif
+
+  # SMBIOS 3.0 only
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
+  gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000
+  gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000
+
+  # map the stack as non-executable when entering the DXE phase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+
+!if $(DO_XGBE)
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeEnable|TRUE
+
+  gAmdModulePkgTokenSpaceGuid.PcdPort0PhyMode|0
+  gAmdModulePkgTokenSpaceGuid.PcdPort1PhyMode|0
+  gAmdModulePkgTokenSpaceGuid.PcdPort0NetSpeed|1
+  gAmdModulePkgTokenSpaceGuid.PcdPort1NetSpeed|1
+
+[PcdsDynamicDefault.common]
+  gAmdStyxTokenSpaceGuid.PcdEthMacA|0x02A1A2A3A4A5
+  gAmdStyxTokenSpaceGuid.PcdEthMacB|0x02B1B2B3B4B5
+
+[PcdsPatchableInModule]
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp|TRUE
+  gAmdModulePkgTokenSpaceGuid.PcdXgbeRev|2
+!endif
+
+[PcdsPatchableInModule]
+# PCIe Configuration: x4x4
+  gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|1
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1
+  gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1
+  gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE
+
+[PcdsDynamicDefault.common]
+  gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
+
+[PcdsDynamicExHii.common.DEFAULT]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  AmdModulePkg/Iscp/IscpPei.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+  ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+  ArmPkg/Drivers/CpuPei/CpuPei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  #
+  # Console IO support
+  #
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  #
+  # Environment Variables Protocol
+  #
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+      TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+      VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  }
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+  #
+  # Iscp support
+  #
+  AmdModulePkg/Iscp/IscpDxe.inf
+
+  #
+  # FDT support
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf {
+    <LibraryClasses>
+      # deprecated BdsLib from the ARM BDS
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+      FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  }
+
+  #
+  # PCI support
+  #
+  AmdModulePkg/Gionb/Gionb.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
+  # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+  #
+  # USB Support
+  #
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!if $(DO_XGBE)
+  #
+  # SNP support
+  #
+  AmdModulePkg/SnpDxe/SnpDxePort0.inf
+  AmdModulePkg/SnpDxe/SnpDxePort1.inf
+!endif
+
+  #
+  # Networking stack
+  #
+  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf {
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+  }
+  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+  #
+  # Core Info
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+  #
+  # ACPI Support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
+
+  #
+  # Crypto Accelerator support (RNG only)
+  #
+  OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+      FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
new file mode 100644
index 0000000..c0a1282
--- /dev/null
+++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
@@ -0,0 +1,409 @@
+#
+#  Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.STYX_ROM]
+BaseAddress   = 0x8000C80000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00500000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x500
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+FILE = OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Binary/PreUefiFirmware.bin
+
+0x00200000|0x00260000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = STYX_EFI
+
+!include OpenPlatformPkg/Platforms/AMD/Styx/Common/Varstore.fdf.inc
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid         = 94f067ae-2aa6-4b30-aa07-4e47fe518bb8
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  #
+  # Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # Environment Variables Protocol
+  #
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+  #
+  # Iscp support
+  #
+  INF AmdModulePkg/Iscp/IscpDxe.inf
+
+  #
+  # FDT support
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf
+
+  FILE FREEFORM = PCD(gAmdStyxTokenSpaceGuid.PcdStyxFdt) {
+    SECTION RAW = OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb
+  }
+
+  #
+  # PCI support
+  #
+  INF AmdModulePkg/Gionb/Gionb.inf
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/StyxSataPlatformDxe.inf
+
+  #
+  # USB Support
+  #
+  INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!if $(DO_XGBE)
+  #
+  # SNP support
+  #
+  INF AmdModulePkg/SnpDxe/SnpDxePort0.inf
+  INF AmdModulePkg/SnpDxe/SnpDxePort1.inf
+!endif
+
+  #
+  # Networking stack
+  #
+  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+  #
+  # Core Info
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+  #
+  # ACPI Support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+  #
+  # SMBIOS Support
+  #
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+  #
+  # Crypto Accelerator support (RNG only)
+  #
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+[FV.STYX_EFI]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  INF AmdModulePkg/Iscp/IscpPei.inf
+  INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE Align = 4K                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE Align = Auto              $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE Align = Auto           $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.Binary]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       |.depex
+     TE       TE Align = Auto           |.efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER.Binary]
+  FILE DRIVER = $(NAMED_GUID) {
+    PE32         PE32                   |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.Binary]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional |.depex
+    PE32         PE32                   |.efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)"     Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ASL                |.aml
+  }
+
diff --git a/Platforms/ARM/Binary/Library/PseudoRngLib/License.txt b/Platforms/ARM/Binary/Library/PseudoRngLib/License.txt
new file mode 100644
index 0000000..fe5821e
--- /dev/null
+++ b/Platforms/ARM/Binary/Library/PseudoRngLib/License.txt
@@ -0,0 +1,19 @@
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+
+Redistribution and use in binary form without modification is permitted
+provided that this copyright notice and the following disclaimer are
+reproduced in the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/Platforms/ARM/Binary/Library/PseudoRngLib/PseudoRngLib.inf b/Platforms/ARM/Binary/Library/PseudoRngLib/PseudoRngLib.inf
new file mode 100644
index 0000000..10942ac
--- /dev/null
+++ b/Platforms/ARM/Binary/Library/PseudoRngLib/PseudoRngLib.inf
@@ -0,0 +1,38 @@
+## @file
+#  Instance of RNG (Random Number Generator) Library.
+#
+#  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PseudoRngLib
+  FILE_GUID                      = 0b9d239e-e958-4071-882a-102835914533
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RngLib|DXE_DRIVER
+
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Binaries.AARCH64]
+  LIB|PseudoRngLib.lib|*
+
+[Packages]
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  ArmGenericTimerCounterLib
+  UefiBootServicesTableLib
diff --git a/Platforms/ARM/Binary/Library/PseudoRngLib/PseudoRngLib.lib b/Platforms/ARM/Binary/Library/PseudoRngLib/PseudoRngLib.lib
new file mode 100644
index 0000000..90bf9dd
--- /dev/null
+++ b/Platforms/ARM/Binary/Library/PseudoRngLib/PseudoRngLib.lib
diff --git a/Platforms/ARM/Binary/Library/PseudoRngLib/README b/Platforms/ARM/Binary/Library/PseudoRngLib/README
new file mode 100644
index 0000000..b338682
--- /dev/null
+++ b/Platforms/ARM/Binary/Library/PseudoRngLib/README
@@ -0,0 +1,8 @@
+This pseudo-random implementation of RngLib is unsafe, and is not intended for
+use in production. It is provided for development purposes only, and only to be
+used on development platforms that lack any hardware peripherals to implement
+RngLib properly.
+
+Note that this code blindly assumes the availability of the AES instructions,
+and the accessibility of the cycle counter. If either is not available, this
+code will crash.
diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
index 800d2cb..96f1c59 100644
--- a/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
+++ b/Platforms/ARM/Juno/AcpiTables/AcpiSsdtRootPci.asl
@@ -15,20 +15,43 @@
 #include "ArmPlatform.h"
 
 /*
-  See Reference [1] 6.2.12
-  "There are two ways that _PRT can be used. ...
-  In the second model, the PCI interrupts are hardwired to specific interrupt
-  inputs on the interrupt controller and are not configurable. In this case,
-  the Source field in _PRT does not reference a device, but instead contains
-  the value zero, and the Source Index field contains the global system
-  interrupt to which the PCI interrupt is hardwired."
+  See ACPI 6.1 Section 6.2.13
+
+  There are two ways that _PRT can be used. ...
+
+  In the first model, a PCI Link device is used to provide additional
+  configuration information such as whether the interrupt is Level or
+  Edge triggered, it is active High or Low, Shared or Exclusive, etc.
+
+  In the second model, the PCI interrupts are hardwired to specific
+  interrupt inputs on the interrupt controller and are not
+  configurable. In this case, the Source field in _PRT does not
+  reference a device, but instead contains the value zero, and the
+  Source Index field contains the global system interrupt to which the
+  PCI interrupt is hardwired.
+
+  We use the first model with link indirection to set the correct
+  interrupt type as PCI defaults (Level Triggered, Active Low) are not
+  compatible with GICv2.
 */
-#define PRT_ENTRY(Address, Pin, Interrupt)                                                       \
-          Package (4) {                                                                           \
+#define LNK_DEVICE(Unique_Id, Link_Name, irq)							\
+	Device(Link_Name) {									\
+	    Name(_HID, EISAID("PNP0C0F"))							\
+	    Name(_UID, Unique_Id)								\
+	    Name(_PRS, ResourceTemplate() {							\
+	        Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq }		\
+	    })											\
+	    Method (_CRS, 0) { Return (_PRS) }							\
+	    Method (_SRS, 1) { }								\
+	    Method (_DIS) { }									\
+	}
+
+#define PRT_ENTRY(Address, Pin, Link)								  \
+        Package (4) {                                                                             \
             Address,    /* uses the same format as _ADR */                                        \
             Pin,        /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */  \
-            Zero,       /* allocated from the global interrupt pool. */                           \
-            Interrupt   /* global system interrupt number */                                      \
+            Link,       /* Interrupt allocated via Link device. */   	     	     	      	  \
+            Zero        /* global system interrupt number (no used) */				  \
           }
 
 /*
@@ -36,7 +59,7 @@
   "High word–Device #, Low word–Function #. (for example, device 3, function 2 is
    0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."
 */
-#define ROOT_PRT_ENTRY(Pin, Interrupt)   PRT_ENTRY(0x0000FFFF, Pin, Interrupt)
+#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x0000FFFF, Pin, Link)
                                                     // Device 0 for Bridge.
 
 
@@ -45,6 +68,11 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM
 	//
 	// PCI Root Complex
 	//
+	LNK_DEVICE(1, LNKA, 168)
+	LNK_DEVICE(2, LNKB, 169)
+	LNK_DEVICE(3, LNKC, 170)
+	LNK_DEVICE(4, LNKD, 171)
+
 	Device(PCI0)
     {
   		Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
@@ -60,10 +88,10 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM
 
 		// PCI Routing Table
 		Name(_PRT, Package() {
-			ROOT_PRT_ENTRY(0, 168),   // INTA
-			ROOT_PRT_ENTRY(1, 169),   // INTB
-			ROOT_PRT_ENTRY(2, 170),   // INTC
-			ROOT_PRT_ENTRY(3, 171),   // INTD
+			ROOT_PRT_ENTRY(0, LNKA),   // INTA
+			ROOT_PRT_ENTRY(1, LNKB),   // INTB
+			ROOT_PRT_ENTRY(2, LNKC),   // INTC
+			ROOT_PRT_ENTRY(3, LNKD),   // INTD
 		})
         // Root complex resources
 		Method (_CRS, 0, Serialized) {
@@ -107,10 +135,11 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM
 					PosDecode,
 					EntireRange,
 					0x00000000, 							// Granularity
-					0x5f800000, 							// Min Base Address
-					0x5fffffff, 							// Max Base Address
+					0x00000000, 							// Min Base Address
+					0x007fffff, 							// Max Base Address
 					0x5f800000, 							// Translate
-					0x00800000  							// Length
+					0x00800000,  							// Length
+					,,,TypeTranslation
 				)
 			}) // Name(RBUF)
 
diff --git a/Platforms/ARM/Juno/AcpiTables/AcpiTables.inf b/Platforms/ARM/Juno/AcpiTables/AcpiTables.inf
index 3159d7d..e099c02 100644
--- a/Platforms/ARM/Juno/AcpiTables/AcpiTables.inf
+++ b/Platforms/ARM/Juno/AcpiTables/AcpiTables.inf
@@ -2,7 +2,7 @@
 #
 #  ACPI table data and ASL sources required to boot the platform.
 #
-#  Copyright (c) 2014-2015, ARM Ltd. All rights reserved.
+#  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -23,9 +23,8 @@
 
 [Sources]
   Dsdt.asl
-  Dbg2.asl
-  Spcr.asl
-  Facs.aslc
+  Dbg2.aslc
+  Spcr.aslc
   Fadt.aslc
   Gtdt.aslc
   Madt.aslc
@@ -52,3 +51,13 @@
 
   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+  #
+  # PL011 UART Settings for Serial Port Console Redirection
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
diff --git a/Platforms/ARM/Juno/AcpiTables/Dbg2.asl b/Platforms/ARM/Juno/AcpiTables/Dbg2.asl
deleted file mode 100644
index f57fa7e..0000000
--- a/Platforms/ARM/Juno/AcpiTables/Dbg2.asl
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2015, Graeme Gregory <graeme.gregory@linaro.org>
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 
- * 1. Redistributions of source code must retain the above copyright 
- * notice, this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the 
- * documentation and/or other materials provided with the distribution.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * 
- * NB: This License is also known as the "BSD 2-Clause License".
- * 
- *
- * [DBG2] ACPI Table
- *
- */
-
-[0004]                    Signature : "DBG2"    [Debug Port table type 2]
-[0004]                 Table Length : 0000005A
-[0001]                     Revision : 00
-[0001]                     Checksum : 06
-[0006]                       Oem ID : "LINARO"
-[0008]                 Oem Table ID : "ARM-JUNO"
-[0004]                 Oem Revision : 00000000
-[0004]              Asl Compiler ID : "INTL"
-[0004]        Asl Compiler Revision : 20140926
-
-[0004]                  Info Offset : 0000002C
-[0004]                   Info Count : 00000001
-
-[0001]                     Revision : 00
-[0002]                       Length : 002C
-[0001]               Register Count : 01
-[0002]              Namepath Length : 0005
-[0002]              Namepath Offset : 0026
-[0002]              OEM Data Length : 0000 [Optional field not present]
-[0002]              OEM Data Offset : 0000 [Optional field not present]
-[0002]                    Port Type : 8000
-[0002]                 Port Subtype : 0003
-[0002]                     Reserved : 0000
-[0002]          Base Address Offset : 0016
-[0002]          Address Size Offset : 0022
-
-[000C]        Base Address Register : [Generic Address Structure]
-[0001]                     Space ID : 00 [SystemMemory]
-[0001]                    Bit Width : 20
-[0001]                   Bit Offset : 00
-[0001]         Encoded Access Width : 03 [DWord Access:32]
-[0008]                      Address : 000000007FF80000
-
-[0004]                 Address Size : 00001000
-
-[0004]                     Namepath : "COM1"
-[0001]                     OEM Data : 00
diff --git a/Platforms/ARM/Juno/AcpiTables/Dbg2.aslc b/Platforms/ARM/Juno/AcpiTables/Dbg2.aslc
new file mode 100644
index 0000000..be30cd0
--- /dev/null
+++ b/Platforms/ARM/Juno/AcpiTables/Dbg2.aslc
@@ -0,0 +1,92 @@
+/** @file
+*  DBG2 Table
+*
+*  Copyright (c) 2012-2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "ArmPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+
+#pragma pack(1)
+
+#define DBG2_NUM_DEBUG_PORTS                       1
+#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS   1
+#define DBG2_NAMESPACESTRING_FIELD_SIZE            8
+#define PL011_UART_LENGTH                          0x1000
+
+#define NAME_STR_UART1     {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'}
+
+typedef struct {
+  EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
+  EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE        BaseAddressRegister;
+  UINT32                                        AddressSize;
+  UINT8                                         NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+  EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE       Description;
+  DBG2_DEBUG_DEVICE_INFORMATION                 Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS];
+} DBG2_TABLE;
+
+
+#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) {                                    \
+    {                                                                                                                 \
+      EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,         /* UINT8     Revision */                        \
+      sizeof (DBG2_DEBUG_DEVICE_INFORMATION),                         /* UINT16    Length */                          \
+      NumReg,                                                         /* UINT8     NumberofGenericAddressRegisters */ \
+      DBG2_NAMESPACESTRING_FIELD_SIZE,                                /* UINT16    NameSpaceStringLength */           \
+      OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),     /* UINT16    NameSpaceStringOffset */           \
+      0,                                                              /* UINT16    OemDataLength */                   \
+      0,                                                              /* UINT16    OemDataOffset */                   \
+      EFI_ACPI_DBG2_PORT_TYPE_SERIAL,                                 /* UINT16    Port Type */                       \
+      SubType,                                                        /* UINT16    Port Subtype */                    \
+      {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},               /* UINT8     Reserved[2] */                     \
+      OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16    BaseAddressRegister Offset */      \
+      OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)          /* UINT16    AddressSize Offset */              \
+    },                                                                                                                \
+    ARM_GAS32 (UartBase),                            /* EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \
+    UartAddrLen,                                     /* UINT32  AddressSize */                                        \
+    UartNameStr                                      /* UINT8   NameSpaceString[MAX_DBG2_NAME_LEN] */                 \
+  }
+
+
+STATIC DBG2_TABLE Dbg2 = {
+  {
+    ARM_ACPI_HEADER (EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE,
+                       DBG2_TABLE,
+                       EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION),
+    OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),
+    DBG2_NUM_DEBUG_PORTS                                              /* UINT32  NumberDbgDeviceInfo */
+  },
+  {
+    /*
+     * Kernel Debug Port
+     */
+    DBG2_DEBUG_PORT_DDI (DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS,
+                          EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
+                          FixedPcdGet64 (PcdSerialDbgRegisterBase),
+                          PL011_UART_LENGTH,
+                          NAME_STR_UART1),
+  }
+};
+
+#pragma pack()
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Dbg2;
diff --git a/Platforms/ARM/Juno/AcpiTables/Dsdt.asl b/Platforms/ARM/Juno/AcpiTables/Dsdt.asl
index c80f46a..07e32ba 100644
--- a/Platforms/ARM/Juno/AcpiTables/Dsdt.asl
+++ b/Platforms/ARM/Juno/AcpiTables/Dsdt.asl
@@ -19,29 +19,223 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
     //
     // A57x2-A53x4 Processor declaration
     //
-    Device(CPU0) { // A53-0: Cluster 1, Cpu 0
-      Name(_HID, "ACPI0007")
-      Name(_UID, 0)
+    Method (_OSC, 4, Serialized)  { // _OSC: Operating System Capabilities
+      CreateDWordField (Arg3, 0x00, STS0)
+      CreateDWordField (Arg3, 0x04, CAP0)
+      If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) {
+        If (!(Arg1 == One)) {
+          STS0 &= ~0x1F
+          STS0 |= 0x0A
+        } Else {
+          If ((CAP0 & 0x100)) {
+            CAP0 &= ~0x100 /* No support for OS Initiated LPI */
+            STS0 &= ~0x1F
+            STS0 |= 0x12
+          }
+        }
+      } Else {
+        STS0 &= ~0x1F
+        STS0 |= 0x06
+      }
+      Return (Arg3)
     }
-    Device(CPU1) { // A53-1: Cluster 1, Cpu 1
-      Name(_HID, "ACPI0007")
+    Device (CLU0) { // Cluster0 state
+      Name(_HID, "ACPI0010")
       Name(_UID, 1)
+      Name (_LPI, Package() {
+        0, // Version
+        0, // Level Index
+        1, // Count
+        Package() { // Power Gating state for Cluster
+          2500, // Min residency (uS)
+          1150, // Wake latency (uS)
+          1, // Flags
+          1, // Arch Context Flags
+          100, //Residency Counter Frequency
+          0, // No Parent State
+          0x01000000, // Integer Entry method
+          ResourceTemplate() { // Null Residency Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          ResourceTemplate() { // Null Usage Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          "CluPwrDn"
+        },
+      })
+      Name(PLPI, Package() {
+        0, // Version
+        1, // Level Index
+        2, // Count
+        Package() { // WFI for CPU
+          1, // Min residency (uS)
+          1, // Wake latency (uS)
+          1, // Flags
+          0, // Arch Context Flags
+          100, //Residency Counter Frequency
+          0, // No parent state
+          ResourceTemplate () {
+            // Register Entry method
+            Register (FFixedHW,
+              0x20,               // Bit Width
+              0x00,               // Bit Offset
+              0xFFFFFFFF,         // Address
+              0x03,               // Access Size
+              )
+          },
+          ResourceTemplate() { // Null Residency Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          ResourceTemplate() { // Null Usage Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          "WFI",
+        },
+        Package() { // Power Gating state for CPU
+          150, // Min residency (uS)
+          350, // Wake latency (uS)
+          1, // Flags
+          1, // Arch Context Flags
+          100, //Residency Counter Frequency
+          1, // Parent node can be in any state
+          ResourceTemplate () {
+            // Register Entry method
+            Register (FFixedHW,
+              0x20,               // Bit Width
+              0x00,               // Bit Offset
+              0x00010000,         // Address
+              0x03,               // Access Size
+              )
+          },
+          ResourceTemplate() { // Null Residency Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          ResourceTemplate() { // Null Usage Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          "CorePwrDn"
+        },
+      })
+      Device(CPU0) { // A57-0: Cluster 0, Cpu 0
+        Name(_HID, "ACPI0007")
+        Name(_UID, 4)
+        Method (_LPI, 0, NotSerialized) {
+          return(PLPI)
+        }
+      }
+      Device(CPU1) { // A57-1: Cluster 0, Cpu 1
+        Name(_HID, "ACPI0007")
+        Name(_UID, 5)
+        Method (_LPI, 0, NotSerialized) {
+          return(PLPI)
+        }
+      }
     }
-    Device(CPU2) { // A53-2: Cluster 1, Cpu 2
-      Name(_HID, "ACPI0007")
+    Device (CLU1) { // Cluster1 state
+      Name(_HID, "ACPI0010")
       Name(_UID, 2)
-    }
-    Device(CPU3) { // A53-3: Cluster 1, Cpu 3
-      Name(_HID, "ACPI0007")
-      Name(_UID, 3)
-    }
-    Device(CPU4) { // A57-0: Cluster 0, Cpu 0
-      Name(_HID, "ACPI0007")
-      Name(_UID, 4)
-    }
-    Device(CPU5) { // A57-1: Cluster 0, Cpu 1
-      Name(_HID, "ACPI0007")
-      Name(_UID, 5)
+      Name (_LPI, Package() {
+        0, // Version
+        0, // Level Index
+        1, // Count
+        Package() { // Power Gating state for Cluster
+          2500, // Min residency (uS)
+          1150, // Wake latency (uS)
+          1, // Flags
+          1, // Arch Context Flags
+          100, //Residency Counter Frequency
+          0, // No Parent State
+          0x01000000, // Integer Entry method
+          ResourceTemplate() { // Null Residency Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          ResourceTemplate() { // Null Usage Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          "CluPwrDn"
+        },
+      })
+      Name(PLPI, Package() {
+        0, // Version
+        1, // Level Index
+        2, // Count
+        Package() { // WFI for CPU
+          1, // Min residency (uS)
+          1, // Wake latency (uS)
+          1, // Flags
+          0, // Arch Context Flags
+          100, //Residency Counter Frequency
+          0, // No parent state
+          ResourceTemplate () {
+            // Register Entry method
+            Register (FFixedHW,
+              0x20,               // Bit Width
+              0x00,               // Bit Offset
+              0xFFFFFFFF,         // Address
+              0x03,               // Access Size
+              )
+          },
+          ResourceTemplate() { // Null Residency Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          ResourceTemplate() { // Null Usage Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          "WFI",
+        },
+        Package() { // Power Gating state for CPU
+          150, // Min residency (uS)
+          350, // Wake latency (uS)
+          1, // Flags
+          1, // Arch Context Flags
+          100, //Residency Counter Frequency
+          1, // Parent node can be in any state
+          ResourceTemplate () {
+            // Register Entry method
+            Register (FFixedHW,
+              0x20,               // Bit Width
+              0x00,               // Bit Offset
+              0x00010000,         // Address
+              0x03,               // Access Size
+              )
+          },
+          ResourceTemplate() { // Null Residency Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          ResourceTemplate() { // Null Usage Counter
+            Register (SystemMemory, 0, 0, 0, 0)
+          },
+          "CorePwrDn"
+        },
+      })
+      Device(CPU2) { // A53-0: Cluster 1, Cpu 0
+        Name(_HID, "ACPI0007")
+        Name(_UID, 0)
+        Method (_LPI, 0, NotSerialized) {
+          return(PLPI)
+        }
+      }
+      Device(CPU3) { // A53-1: Cluster 1, Cpu 1
+        Name(_HID, "ACPI0007")
+        Name(_UID, 1)
+        Method (_LPI, 0, NotSerialized) {
+          return(PLPI)
+        }
+      }
+      Device(CPU4) { // A53-2: Cluster 1, Cpu 2
+        Name(_HID, "ACPI0007")
+        Name(_UID, 2)
+        Method (_LPI, 0, NotSerialized) {
+          return(PLPI)
+        }
+      }
+      Device(CPU5) { // A53-3: Cluster 1, Cpu 3
+        Name(_HID, "ACPI0007")
+        Name(_UID, 3)
+        Method (_LPI, 0, NotSerialized) {
+          return(PLPI)
+        }
+      }
     }
 
     //
@@ -65,7 +259,7 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
       Name(_HID, "ARMH9118")
       Name(_UID, Zero)
       Name(_CRS, ResourceTemplate() {
-              Memory32Fixed(ReadWrite, 0x1A000000, 0x1000)
+              Memory32Fixed(ReadWrite, 0x18000000, 0x1000)
               Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 }
       })
       Name(_DSD, Package() {
diff --git a/Platforms/ARM/Juno/AcpiTables/Fadt.aslc b/Platforms/ARM/Juno/AcpiTables/Fadt.aslc
index eafdecb..6b75629 100644
--- a/Platforms/ARM/Juno/AcpiTables/Fadt.aslc
+++ b/Platforms/ARM/Juno/AcpiTables/Fadt.aslc
@@ -1,7 +1,7 @@
 /** @file
 *  Fixed ACPI Description Table (FADT)
 *
-*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -72,7 +72,7 @@ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
   EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
   NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  ResetReg
   0,                                                                        // UINT8      ResetValue
-#if ARM_JUNO_ACPI_5_0
+#ifdef ARM_JUNO_ACPI_5_0
   {EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE},   // UINT8      Reserved2[3]
 #else
   EFI_ACPI_5_1_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
diff --git a/Platforms/ARM/Juno/AcpiTables/Gtdt.aslc b/Platforms/ARM/Juno/AcpiTables/Gtdt.aslc
index c0e3f5f..5e2daf9 100644
--- a/Platforms/ARM/Juno/AcpiTables/Gtdt.aslc
+++ b/Platforms/ARM/Juno/AcpiTables/Gtdt.aslc
@@ -1,7 +1,7 @@
 /** @file
 *  Generic Timer Description Table (GTDT)
 *
-*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -61,16 +61,18 @@
 
   typedef struct {
     EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+#if (JUNO_WATCHDOG_COUNT != 0)
     EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdogs[JUNO_WATCHDOG_COUNT];
-  } EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+#endif
+  } GENERIC_TIMER_DESCRIPTION_TABLE;
 
   #pragma pack ()
 
-  EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+  GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
     {
       ARM_ACPI_HEADER(
         EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
-        EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE,
+        GENERIC_TIMER_DESCRIPTION_TABLE,
         EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
       ),
       SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
@@ -87,12 +89,14 @@
       JUNO_WATCHDOG_COUNT,                          // UINT32  PlatformTimerCount
       sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
     },
+#if (JUNO_WATCHDOG_COUNT != 0)
     {
       EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
           FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
       EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
           FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
     }
+#endif
   };
 #endif
 
diff --git a/Platforms/ARM/Juno/AcpiTables/Madt.aslc b/Platforms/ARM/Juno/AcpiTables/Madt.aslc
index 0a167d3..dffa5d6 100644
--- a/Platforms/ARM/Juno/AcpiTables/Madt.aslc
+++ b/Platforms/ARM/Juno/AcpiTables/Madt.aslc
@@ -1,7 +1,7 @@
 /** @file
 *  Multiple APIC Description Table (MADT)
 *
-*  Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -55,14 +55,14 @@
       //       For now we leave CPU2 (A53-0) at the first position.
       //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
       //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0
-      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase))  // A57-1
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-0
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-1
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-2
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-3
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A57-0
+      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase))  // A57-1
     },
-    EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)
+    EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0)
   };
 #else
   #pragma pack (1)
@@ -70,17 +70,17 @@
   typedef struct {
     EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
     EFI_ACPI_5_1_GIC_STRUCTURE                            GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
-    EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+    EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
     EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE                  MsiFrame;
-  } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+  } MULTIPLE_APIC_DESCRIPTION_TABLE;
 
   #pragma pack ()
 
-  EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+  MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
     {
       ARM_ACPI_HEADER (
         EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
-        EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+        MULTIPLE_APIC_DESCRIPTION_TABLE,
         EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
       ),
       //
@@ -100,25 +100,25 @@
       //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
       //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0
-          2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1
-          3, 1, GET_MPID(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          3, 1, GET_MPID(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2
-          4, 2, GET_MPID(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          4, 2, GET_MPID(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3
-          5, 3, GET_MPID(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          5, 3, GET_MPID(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0
-          0, 4, GET_MPID(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          0, 4, GET_MPID(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
       EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1
-          1, 5, GET_MPID(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+          1, 5, GET_MPID(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
     },
-    EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0),
+    EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 2),
     // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)
     EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)
   };
diff --git a/Platforms/ARM/Juno/AcpiTables/Spcr.asl b/Platforms/ARM/Juno/AcpiTables/Spcr.asl
deleted file mode 100644
index 2b65326..0000000
--- a/Platforms/ARM/Juno/AcpiTables/Spcr.asl
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2015, Graeme Gregory <graeme.gregory@linaro.org>
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 
- * 1. Redistributions of source code must retain the above copyright 
- * notice, this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the 
- * documentation and/or other materials provided with the distribution.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * 
- * NB: This License is also known as the "BSD 2-Clause License".
- * 
- *
- * [SPCR] ACPI Table
- *
- */
-
-[0004]                    Signature : "SPCR"    [Serial Port Console Redirection table]
-[0004]                 Table Length : 00000050
-[0001]                     Revision : 02
-[0001]                     Checksum : 29
-[0006]                       Oem ID : "LINARO"
-[0008]                 Oem Table ID : "ARM-JUNO"
-[0004]                 Oem Revision : 00000000
-[0004]              Asl Compiler ID : "INTL"
-[0004]        Asl Compiler Revision : 20140926
-
-[0001]               Interface Type : 03
-[0003]                     Reserved : 000000
-
-[000C]         Serial Port Register : [Generic Address Structure]
-[0001]                     Space ID : 00 [SystemMemory]
-[0001]                    Bit Width : 20
-[0001]                   Bit Offset : 00
-[0001]         Encoded Access Width : 03 [DWord Access:32]
-[0008]                      Address : 000000007FF80000
-
-[0001]               Interrupt Type : 08
-[0001]          PCAT-compatible IRQ : 00
-[0004]                    Interrupt : 00000073
-[0001]                    Baud Rate : 07
-[0001]                       Parity : 00
-[0001]                    Stop Bits : 01
-[0001]                 Flow Control : 00
-[0001]                Terminal Type : 03
-[0001]                     Reserved : 00
-[0002]                PCI Device ID : FFFF
-[0002]                PCI Vendor ID : FFFF
-[0001]                      PCI Bus : 00
-[0001]                   PCI Device : 00
-[0001]                 PCI Function : 00
-[0004]                    PCI Flags : 00000000
-[04Bh]                  PCI Segment : 00
-[04Ch]                     Reserved : 00000000
-
diff --git a/Platforms/ARM/Juno/AcpiTables/Spcr.aslc b/Platforms/ARM/Juno/AcpiTables/Spcr.aslc
new file mode 100644
index 0000000..8371669
--- /dev/null
+++ b/Platforms/ARM/Juno/AcpiTables/Spcr.aslc
@@ -0,0 +1,99 @@
+/** @file
+* SPCR Table
+*
+* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution.  The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "ArmPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+/**
+ * References:
+ * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
+ **/
+
+
+///
+/// SPCR Flow Control
+///
+#define SPCR_FLOW_CONTROL_NONE           0
+
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+  ARM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+                     EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+                     EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
+  // UINT8                                   InterfaceType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+  // UINT8                                   Reserved1[3];
+  {
+    EFI_ACPI_RESERVED_BYTE,
+    EFI_ACPI_RESERVED_BYTE,
+    EFI_ACPI_RESERVED_BYTE
+  },
+  // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  BaseAddress;
+  ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)),
+  // UINT8                                   InterruptType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+  // UINT8                                   Irq;
+  0,                                         // Not used on ARM
+  // UINT32                                  GlobalSystemInterrupt;
+  FixedPcdGet32 (PL011UartInterrupt),
+  // UINT8                                   BaudRate;
+#if (FixedPcdGet64 (PcdUartDefaultBaudRate) == 9600)
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600,
+#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 19200)
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200,
+#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 57600)
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600,
+#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 115200)
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+#else
+#error Unsupported SPCR Baud Rate
+#endif
+  // UINT8                                   Parity;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+  // UINT8                                   StopBits;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+  // UINT8                                   FlowControl;
+  SPCR_FLOW_CONTROL_NONE,
+  // UINT8                                   TerminalType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+  // UINT8                                   Reserved2;
+  EFI_ACPI_RESERVED_BYTE,
+  // UINT16                                  PciDeviceId;
+  0xFFFF,
+  // UINT16                                  PciVendorId;
+  0xFFFF,
+  // UINT8                                   PciBusNumber;
+  0x00,
+  // UINT8                                   PciDeviceNumber;
+  0x00,
+  // UINT8                                   PciFunctionNumber;
+  0x00,
+  // UINT32                                  PciFlags;
+  0x00000000,
+  // UINT8                                   PciSegment;
+  0x00,
+  // UINT32                                  Reserved3;
+  EFI_ACPI_RESERVED_DWORD
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc
index d015b35..4080c0b 100644
--- a/Platforms/ARM/Juno/ArmJuno.dsc
+++ b/Platforms/ARM/Juno/ArmJuno.dsc
@@ -34,6 +34,8 @@
 !include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress.dsc.inc
 
 [LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
   ArmPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
   ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
 
@@ -43,19 +45,11 @@
 
   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
-  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
-  PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
   CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
 
   # USB Requirements
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
 
-[LibraryClasses.ARM]
-  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
-
-[LibraryClasses.AARCH64]
-  ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
-
 [LibraryClasses.common.SEC]
   PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
   ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
@@ -73,7 +67,8 @@
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
 
 [BuildOptions]
-  *_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include
+  *_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include
+  GCC:*_*_ARM_PLATFORM_FLAGS = -march=armv8-a
 
 ################################################################################
 #
@@ -120,9 +115,14 @@
 
   ## PL011 - Serial Terminal
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
-  gArmPlatformTokenSpaceGuid.PL011UartInteger|4
-  gArmPlatformTokenSpaceGuid.PL011UartFractional|0
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|7372800
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt|115
+
+  ## PL011 - Serial Debug UART
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x7FF80000
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|7372800
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200
 
   ## PL031 RealTimeClock
   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
@@ -130,6 +130,7 @@
   # LAN9118 Ethernet Driver
   gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x18000000
   gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x1215161822242628
+  gEmbeddedTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout|40000
 
   #
   # ARM General Interrupt Controller
@@ -140,13 +141,13 @@
   #
   # PLDA PCI Root Complex
   #
-  gArmPlatformTokenSpaceGuid.PcdPciBusMax|255
-  gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x5f800000
-  gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x00800000
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x50000000
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x08000000
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x4000000000
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x100000000
+  gArmTokenSpaceGuid.PcdPciBusMax|255
+  gArmTokenSpaceGuid.PcdPciIoBase|0x5f800000
+  gArmTokenSpaceGuid.PcdPciIoSize|0x00800000
+  gArmTokenSpaceGuid.PcdPciMmio32Base|0x50000000
+  gArmTokenSpaceGuid.PcdPciMmio32Size|0x08000000
+  gArmTokenSpaceGuid.PcdPciMmio64Base|0x4000000000
+  gArmTokenSpaceGuid.PcdPciMmio64Size|0x100000000
 
   # List of Device Paths that support BootMonFs
   gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)"
@@ -159,8 +160,8 @@
   gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L"console=ttyAMA0,115200 earlycon=pl011,0x7ff80000 root=/dev/sda1 rootwait verbose debug"
 
   # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
-  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
-  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(7D916D80-5BB1-458C-A48F-E25FDD51EF94)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(7D916D80-5BB1-458C-A48F-E25FDD51EF94)"
 
   #
   # ARM Architectural Timer Frequency
@@ -171,6 +172,16 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
 
+  #
+  # SMBIOS entry point version
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
+  #
+  # ACPI Table Version
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
 [PcdsPatchableInModule]
   # Console Resolution (Full HD)
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920
@@ -198,7 +209,7 @@
   #
   # PEI Phase modules
   #
-  ArmPlatformPkg/PrePi/PeiMPCore.inf
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
 
   #
   # DXE
@@ -265,7 +276,10 @@
   # PCI Support
   #
   MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
-  ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <LibraryClasses>
+      DmaLib|EmbeddedPkg/Library/NullDmaLib/NullDmaLib.inf
+  }
 
   #
   # SATA Controller
@@ -274,14 +288,22 @@
   EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
 
   #
+  # NVMe boot devices
+  #
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+  #
   # Networking stack
   #
   EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
+  OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
 
   #
   # Usb Support
   #
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
   MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
   MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
   MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
   MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
@@ -290,7 +312,16 @@
   #
   # Juno platform driver
   #
-  ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
+  ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
+
+  #
+  # SMBIOS/DMI
+  #
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  OpenPlatformPkg/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
 
   #
   # Bds
@@ -298,4 +329,22 @@
   MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
   MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
+
+[Components.AARCH64]
+  #
+  # EBC
+  #
+  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf {
+    <LibraryClasses>
+      # DO NOT USE THIS LIBRARY FOR PRODUCTION DEVICES
+      RngLib|OpenPlatformPkg/Platforms/ARM/Binary/Library/PseudoRngLib/PseudoRngLib.inf
+  }
diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf
index 7c226b4..beee7af 100644
--- a/Platforms/ARM/Juno/ArmJuno.fdf
+++ b/Platforms/ARM/Juno/ArmJuno.fdf
@@ -86,10 +86,6 @@ READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
 
-  APRIORI DXE {
-    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
-  }
-
   INF MdeModulePkg/Core/Dxe/DxeMain.inf
   INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
 
@@ -152,7 +148,9 @@ FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
   #
   # Usb Support
   #
+  INF  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
   INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
   INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
   INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
   INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
@@ -171,6 +169,11 @@ FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
   INF EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
 
   #
+  # NVMe boot devices
+  #
+  INF  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+  #
   # Networking stack
   #
   INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
@@ -185,11 +188,13 @@ FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
   INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
   INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
   INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
+  INF OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf
 
   #
   # UEFI applications
   #
-  INF ShellBinPkg/UefiShell/UefiShell.inf
+  INF ShellPkg/Application/Shell/Shell.inf
+
 
   #
   # Juno platform driver
@@ -197,12 +202,19 @@ FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
   INF ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
 
   #
+  # SMBIOS/DMI
+  #
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF OpenPlatformPkg/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
+  #
   # Bds
   #
   INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
   INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
 
   #
   # FDT installation
@@ -211,6 +223,15 @@ FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
   # after the device drivers (eg: Ethernet) to ensure we have support for them.
   INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf
 
+!if $(ARCH) == AARCH64
+  #
+  # EBC
+  #
+  INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+  INF SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
+!endif
+
 [FV.FVMAIN_COMPACT]
 FvAlignment        = 8
 ERASE_POLARITY     = 1
@@ -229,7 +250,7 @@ READ_STATUS        = TRUE
 READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 
-  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
 
   FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
     SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
diff --git a/Platforms/ARM/Juno/Binary/bl0.bin b/Platforms/ARM/Juno/Binary/bl0.bin
index abf6dfd..b43a130 100644
--- a/Platforms/ARM/Juno/Binary/bl0.bin
+++ b/Platforms/ARM/Juno/Binary/bl0.bin
diff --git a/Platforms/ARM/Juno/Binary/bl30.bin b/Platforms/ARM/Juno/Binary/bl30.bin
index 67933ff..451c923 100644
--- a/Platforms/ARM/Juno/Binary/bl30.bin
+++ b/Platforms/ARM/Juno/Binary/bl30.bin
diff --git a/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c
new file mode 100644
index 0000000..fe5498e
--- /dev/null
+++ b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c
@@ -0,0 +1,865 @@
+/** @file
+  This driver installs SMBIOS information for ARM Juno platforms
+
+  Copyright (c) 2015, ARM Limited. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <ArmPlatform.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <PiDxe.h>
+#include <Protocol/Smbios.h>
+
+#define TYPE0_STRINGS                                    \
+  "EFI Development Kit II / ARM LTD\0" /* Vendor */      \
+  "EDK II\0"                           /* BiosVersion */ \
+  __DATE__"\0"                         /* BiosReleaseDate */
+
+#define TYPE1_STRINGS                                   \
+  "ARM LTD\0"                        /* Manufacturer */ \
+  "ARM Juno Development Platform\0"  /* Product Name */ \
+  "None\0"                           /* Version */      \
+  "                    \0"           /* 20 character buffer */
+
+#define TYPE2_STRINGS                                     \
+  "ARM LTD\0"                        /* Manufacturer */   \
+  "ARM Juno Development Platform\0"  /* Product Name */   \
+  "R0\0"                             /* Version */        \
+  "Serial Not Set\0"                 /* Serial */         \
+  "Base of Chassis\0"                /* board location */ \
+  "R1\0"                             /* Version */        \
+  "R2\0"                             /* Version */
+
+#define TYPE3_STRINGS                                   \
+  "ARM LTD\0"                        /* Manufacturer */ \
+  "None\0"                           /* Version */      \
+  "Serial Not Set\0"                 /* Serial  */
+
+#define TYPE4_STRINGS                                               \
+  "BGA-1156\0"                       /* socket type */              \
+  "ARM LTD\0"                        /* manufactuer */              \
+  "Cortex-A57\0"                     /* processor 1 description */  \
+  "Cortex-A53\0"                     /* processor 2 description */  \
+  "Cortex-A72\0"                     /* processor 2 description */  \
+  "0xd03\0"                          /* A53 part number */          \
+  "0xd07\0"                          /* A57 part number */          \
+  "0xd08\0"                          /* A72 part number */
+
+#define TYPE7_STRINGS                              \
+  "L1 Instruction\0"                 /* L1I  */    \
+  "L1 Data\0"                        /* L1D  */    \
+  "L2\0"                             /* L2   */
+
+#define TYPE9_STRINGS                              \
+  "PCIE_SLOT0\0"                     /* Slot0 */   \
+  "PCIE_SLOT1\0"                     /* Slot1 */   \
+  "PCIE_SLOT2\0"                     /* Slot2 */   \
+  "PCIE_SLOT3\0"                     /* Slot3 */
+
+#define TYPE16_STRINGS                             \
+  "\0"                               /* nothing */
+
+#define TYPE17_STRINGS                                       \
+  "RIGHT SIDE\0"                     /* location */          \
+  "BANK 0\0"                         /* bank description */
+
+#define TYPE19_STRINGS                             \
+  "\0"                               /* nothing */
+
+#define TYPE32_STRINGS                             \
+  "\0"                               /* nothing */
+
+
+//
+// Type definition and contents of the default SMBIOS table.
+// This table covers only the minimum structures required by
+// the SMBIOS specification (section 6.2, version 3.0)
+//
+#pragma pack(1)
+typedef struct {
+  SMBIOS_TABLE_TYPE0 Base;
+  INT8              Strings[sizeof(TYPE0_STRINGS)];
+} ARM_TYPE0;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE1 Base;
+  UINT8              Strings[sizeof(TYPE1_STRINGS)];
+} ARM_TYPE1;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE2 Base;
+  UINT8              Strings[sizeof(TYPE2_STRINGS)];
+} ARM_TYPE2;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE3 Base;
+  UINT8              Strings[sizeof(TYPE3_STRINGS)];
+} ARM_TYPE3;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE4 Base;
+  UINT8              Strings[sizeof(TYPE4_STRINGS)];
+} ARM_TYPE4;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE7 Base;
+  UINT8              Strings[sizeof(TYPE7_STRINGS)];
+} ARM_TYPE7;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE9 Base;
+  UINT8              Strings[sizeof(TYPE9_STRINGS)];
+} ARM_TYPE9;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE16 Base;
+  UINT8              Strings[sizeof(TYPE16_STRINGS)];
+} ARM_TYPE16;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE17 Base;
+  UINT8              Strings[sizeof(TYPE17_STRINGS)];
+} ARM_TYPE17;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE19 Base;
+  UINT8              Strings[sizeof(TYPE19_STRINGS)];
+} ARM_TYPE19;
+
+typedef struct {
+  SMBIOS_TABLE_TYPE32 Base;
+  UINT8              Strings[sizeof(TYPE32_STRINGS)];
+} ARM_TYPE32;
+
+// SMBIOS tables often reference each other using
+// fixed constants, define a list of these constants
+// for our hardcoded tables
+enum SMBIOS_REFRENCE_HANDLES {
+  SMBIOS_HANDLE_A57_L1I = 0x1000,
+  SMBIOS_HANDLE_A57_L1D,
+  SMBIOS_HANDLE_A57_L2,
+  SMBIOS_HANDLE_A53_L1I,
+  SMBIOS_HANDLE_A53_L1D,
+  SMBIOS_HANDLE_A53_L2,
+  SMBIOS_HANDLE_MOTHERBOARD,
+  SMBIOS_HANDLE_CHASSIS,
+  SMBIOS_HANDLE_A72_CLUSTER,
+  SMBIOS_HANDLE_A57_CLUSTER,
+  SMBIOS_HANDLE_A53_CLUSTER,
+  SMBIOS_HANDLE_MEMORY,
+  SMBIOS_HANDLE_DIMM
+};
+
+#define SERIAL_LEN 10  //this must be less than the buffer len allocated in the type1 structure
+
+#pragma pack()
+
+// BIOS information (section 7.1)
+STATIC ARM_TYPE0 mArmDefaultType0 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE0),      // UINT8 Length
+      SMBIOS_HANDLE_PI_RESERVED,
+    },
+    1,     // SMBIOS_TABLE_STRING       Vendor
+    2,     // SMBIOS_TABLE_STRING       BiosVersion
+    0xE800,// UINT16                    BiosSegment
+    3,     // SMBIOS_TABLE_STRING       BiosReleaseDate
+    0,     // UINT8                     BiosSize
+    {
+      0,0,0,0,0,0,
+      1, //PCI supported
+      0,
+      1, //PNP supported
+      0,
+      1, //BIOS upgradable
+      0, 0, 0,
+      1, //Boot from CD
+      1, //selectable boot
+    },  // MISC_BIOS_CHARACTERISTICS BiosCharacteristics
+    {      // BIOSCharacteristicsExtensionBytes[2]
+      0x3,
+      0xC,
+    },
+    0,     // UINT8                     SystemBiosMajorRelease
+    0,     // UINT8                     SystemBiosMinorRelease
+    0xFF,  // UINT8                     EmbeddedControllerFirmwareMajorRelease
+    0xFF   // UINT8                     EmbeddedControllerFirmwareMinorRelease
+  },
+  // Text strings (unformatted area)
+  TYPE0_STRINGS
+};
+
+// System information (section 7.2)
+STATIC CONST ARM_TYPE1 mArmDefaultType1 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_INFORMATION,
+      sizeof(SMBIOS_TABLE_TYPE1),
+      SMBIOS_HANDLE_PI_RESERVED,
+    },
+    1,     //Manufacturer
+    2,     //Product Name
+    3,     //Version
+    4,     //Serial
+    { 0x8a95d198, 0x7f46, 0x11e5, { 0xbf,0x8b,0x08,0x00,0x27,0x04,0xd4,0x8e }},    //UUID
+    6,     //Wakeup type
+    0,     //SKU
+    0,     //Family
+  },
+  // Text strings (unformatted)
+  TYPE1_STRINGS
+};
+
+// Baseboard (section 7.3)
+STATIC ARM_TYPE2 mArmDefaultType2 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE2),           // UINT8 Length
+      SMBIOS_HANDLE_MOTHERBOARD,
+    },
+    1,    //Manufacturer
+    2,    //Product Name
+    3,    //Version
+    4,    //Serial
+    0,    //Asset tag
+    {1},  //motherboard, not replaceable
+    5,    //location of board
+    SMBIOS_HANDLE_CHASSIS,
+    BaseBoardTypeMotherBoard,
+    1,
+    {SMBIOS_HANDLE_A53_CLUSTER}, //,SMBIOS_HANDLE_A53_CLUSTER,SMBIOS_HANDLE_MEMORY},
+  },
+  TYPE2_STRINGS
+};
+
+// Enclosure
+STATIC CONST ARM_TYPE3 mArmDefaultType3 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE3),      // UINT8 Length
+      SMBIOS_HANDLE_CHASSIS,
+    },
+    1,   //Manufacturer
+    4,   //enclosure type (low profile desktop)
+    2,   //version
+    3,   //serial
+    0,   //asset tag
+    ChassisStateUnknown,   //boot chassis state
+    ChassisStateSafe,      //power supply state
+    ChassisStateSafe,      //thermal state
+    ChassisSecurityStatusNone,   //security state
+    {0,0,0,0,}, //OEM defined
+    1,  //1U height
+    1,  //number of power cords
+    0,  //no contained elements
+  },
+  TYPE3_STRINGS
+};
+
+// Processor
+STATIC CONST ARM_TYPE4 mArmDefaultType4_a72 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE4),           // UINT8 Length
+      SMBIOS_HANDLE_A72_CLUSTER,
+    },
+    1, //socket type
+    3, //processor type CPU
+    ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
+    2, //manufactuer
+    {{0,},{0.}}, //processor id
+    5, //version
+    {0,0,0,0,0,1}, //voltage
+    0, //external clock
+    1200, //max speed
+    1200, //current speed
+    0x41, //status
+    ProcessorUpgradeOther,
+    SMBIOS_HANDLE_A57_L1I, //l1 cache handle
+    SMBIOS_HANDLE_A57_L2, //l2 cache handle
+    0xFFFF, //l3 cache handle
+    0, //serial not set
+    0, //asset not set
+    8, //part number
+    2, //core count in socket
+    2, //enabled core count in socket
+    0, //threads per socket
+    0xEC, // processor characteristics
+    ProcessorFamilyARM, //ARM core
+  },
+  TYPE4_STRINGS
+};
+
+STATIC CONST ARM_TYPE4 mArmDefaultType4_a57 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE4),           // UINT8 Length
+      SMBIOS_HANDLE_A57_CLUSTER,
+    },
+    1, //socket type
+    3, //processor type CPU
+    ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
+    2, //manufactuer
+    {{0,},{0.}}, //processor id
+    3, //version
+    {0,0,0,0,0,1}, //voltage
+    0, //external clock
+    1200, //max speed
+    1200, //current speed
+    0x41, //status
+    ProcessorUpgradeOther,
+    SMBIOS_HANDLE_A57_L1I, //l1 cache handle
+    SMBIOS_HANDLE_A57_L2, //l2 cache handle
+    0xFFFF, //l3 cache handle
+    0, //serial not set
+    0, //asset not set
+    7, //part number
+    2, //core count in socket
+    2, //enabled core count in socket
+    0, //threads per socket
+    0xEC, // processor characteristics
+    ProcessorFamilyARM, //ARM core
+  },
+  TYPE4_STRINGS
+};
+
+STATIC CONST ARM_TYPE4 mArmDefaultType4_a53 = {
+  {
+    {   // SMBIOS_STRUCTURE Hdr
+        EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
+        sizeof (SMBIOS_TABLE_TYPE4),           // UINT8 Length
+        SMBIOS_HANDLE_A53_CLUSTER,
+    },
+    1, //socket type
+    3, //processor type CPU
+    ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
+    2, //manufactuer
+    {{0,},{0.}}, //processor id
+    4, //version
+    {0,0,0,0,0,1}, //voltage
+    0, //external clock
+    650, //max speed
+    650, //current speed
+    0x41, //status
+    ProcessorUpgradeOther,
+    SMBIOS_HANDLE_A53_L1I, //l1 cache handle
+    SMBIOS_HANDLE_A53_L2, //l2 cache handle
+    0xFFFF, //l3 cache handle
+    0, //serial not set
+    0, //asset not set
+    6, //part number
+    4, //core count in socket
+    4, //enabled core count in socket
+    0, //threads per socket
+    0xEC, // processor characteristics
+    ProcessorFamilyARM, //ARM core
+  },
+  TYPE4_STRINGS
+};
+
+// Cache
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1i = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE7),       // UINT8 Length
+      SMBIOS_HANDLE_A57_L1I,
+    },
+    1,
+    0x380, //L1 enabled, unknown WB
+    48, //48k i cache max
+    48, //48k installed
+    {0,1}, //SRAM type
+    {0,1}, //SRAM type
+    0, //unkown speed
+    CacheErrorParity, //parity checking
+    CacheTypeInstruction, //instruction cache
+    CacheAssociativityOther, //three way
+  },
+  TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1i = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE7),       // UINT8 Length
+      SMBIOS_HANDLE_A53_L1I,
+    },
+    1,
+    0x380, //L1 enabled, unknown WB
+    32, //32k i cache max
+    32, //32k installed
+    {0,1}, //SRAM type
+    {0,1}, //SRAM type
+    0, //unkown speed
+    CacheErrorParity, //parity checking
+    CacheTypeInstruction, //instruction cache
+    CacheAssociativity2Way, //two way
+  },
+  TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1d = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE7),       // UINT8 Length
+      SMBIOS_HANDLE_A57_L1D,
+    },
+    2,
+    0x180, //L1 enabled, WB
+    32, //32k d cache max
+    32, //32k installed
+    {0,1}, //SRAM type
+    {0,1}, //SRAM type
+    0, //unkown speed
+    CacheErrorSingleBit, //ECC checking
+    CacheTypeData, //instruction cache
+    CacheAssociativity2Way, //two way associative
+  },
+  TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1d = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE7),       // UINT8 Length
+      SMBIOS_HANDLE_A53_L1D,
+    },
+    2,
+    0x180, //L1 enabled, WB
+    32, //32k d cache max
+    32, //32k installed
+    {0,1}, //SRAM type
+    {0,1}, //SRAM type
+    0, //unkown speed
+    CacheErrorSingleBit, //ECC checking
+    CacheTypeData, //instruction cache
+    CacheAssociativity4Way, //four way associative
+  },
+  TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l2 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE7),       // UINT8 Length
+      SMBIOS_HANDLE_A57_L2,
+    },
+    3,
+    0x181, //L2 enabled, WB
+    2048, //2M d cache max
+    2048, //2M installed
+    {0,1}, //SRAM type
+    {0,1}, //SRAM type
+    0, //unkown speed
+    CacheErrorSingleBit, //ECC checking
+    CacheTypeUnified, //instruction cache
+    CacheAssociativity16Way, //16 way associative
+  },
+  TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l2 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE7),       // UINT8 Length
+      SMBIOS_HANDLE_A53_L2,
+    },
+    3,
+    0x181, //L2 enabled, WB
+    1024, //1M D cache max
+    1024, //1M installed
+    {0,1}, //SRAM type
+    {0,1}, //SRAM type
+    0, //unkown speed
+    CacheErrorSingleBit, //ECC checking
+    CacheTypeUnified, //instruction cache
+    CacheAssociativity16Way, //16 way associative
+  },
+  TYPE7_STRINGS
+};
+
+// Slots
+STATIC CONST ARM_TYPE9 mArmDefaultType9_0 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE9),  // UINT8 Length
+      SMBIOS_HANDLE_PI_RESERVED,
+    },
+    1, //slot 0
+    SlotTypePciExpressGen2X4,
+    SlotDataBusWidth1X,
+    SlotUsageUnknown,
+    SlotLengthShort,
+    0,
+    {1}, //unknown
+    {1,0,1},  //PME and SMBUS
+    0,
+    2,
+    1,
+  },
+  TYPE9_STRINGS
+};
+
+STATIC CONST ARM_TYPE9 mArmDefaultType9_1 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE9),  // UINT8 Length
+      SMBIOS_HANDLE_PI_RESERVED,
+    },
+    1, //slot 0
+    SlotTypePciExpressGen2X4,
+    SlotDataBusWidth1X,
+    SlotUsageUnknown,
+    SlotLengthShort,
+    0,
+    {1},
+    {1,0,1}, //PME and SMBUS
+    0,
+    2,
+    2,
+  },
+  TYPE9_STRINGS
+};
+
+STATIC CONST ARM_TYPE9 mArmDefaultType9_2 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE9),  // UINT8 Length
+      SMBIOS_HANDLE_PI_RESERVED,
+    },
+    1, //slot 0
+    SlotTypePciExpressGen2X8,
+    SlotDataBusWidth4X,
+    SlotUsageUnknown,
+    SlotLengthShort,
+    0,
+    {1},
+    {1,0,1}, //PME and SMBUS
+    0,
+    2,
+    3,
+  },
+  TYPE9_STRINGS
+};
+
+STATIC CONST ARM_TYPE9 mArmDefaultType9_3 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE9),  // UINT8 Length
+      SMBIOS_HANDLE_PI_RESERVED,
+    },
+    1, //slot 0
+    SlotTypePciExpressGen2X16,
+    SlotDataBusWidth4X,
+    SlotUsageUnknown,
+    SlotLengthShort,
+    0,
+    {1},
+    {1,0,1}, //PME and SMBUS
+    0,
+    2,
+    0xc,
+  },
+  TYPE9_STRINGS
+};
+
+// Memory array
+STATIC CONST ARM_TYPE16 mArmDefaultType16 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE16),          // UINT8 Length
+      SMBIOS_HANDLE_MEMORY,
+    },
+    MemoryArrayLocationSystemBoard, //on motherboard
+    MemoryArrayUseSystemMemory,     //system RAM
+    MemoryErrorCorrectionNone,      //Juno doesn't have ECC RAM
+    0x800000, //8GB
+    0xFFFE,   //No error information structure
+    0x1,      //soldered memory
+  },
+  TYPE16_STRINGS
+};
+
+// Memory device
+STATIC CONST ARM_TYPE17 mArmDefaultType17 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE17),  // UINT8 Length
+      SMBIOS_HANDLE_DIMM,
+    },
+    SMBIOS_HANDLE_MEMORY, //array to which this module belongs
+    0xFFFE,               //no errors
+    64, //single DIMM, no ECC is 64bits (for ecc this would be 72)
+    64, //data width of this device (64-bits)
+    0x2000, //8GB
+    0x0B,   //row of chips
+    0,      //not part of a set
+    1,      //right side of board
+    2,      //bank 0
+//  MemoryTypeLpddr3, //LP DDR3, isn't defined yet
+    MemoryTypeDdr3,                  //LP DDR3
+    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered
+    1600,                            //1600Mhz DDR
+    0, //varies between diffrent production runs
+    0, //serial
+    0, //asset tag
+    0, //part number
+    0, //rank
+  },
+  TYPE17_STRINGS
+};
+
+// Memory array mapped address, this structure
+// is overridden by InstallMemoryStructure
+STATIC CONST ARM_TYPE19 mArmDefaultType19 = {
+  {
+    {  // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE19),                // UINT8 Length
+      SMBIOS_HANDLE_PI_RESERVED,
+    },
+    0xFFFFFFFF, //invalid, look at extended addr field
+    0xFFFFFFFF,
+    SMBIOS_HANDLE_DIMM, //handle
+    1,
+    0x080000000,        //starting addr of first 2GB
+    0x100000000,        //ending addr of first 2GB
+  },
+  TYPE19_STRINGS
+};
+
+// System boot info
+STATIC CONST ARM_TYPE32 mArmDefaultType32 = {
+  {
+    { // SMBIOS_STRUCTURE Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type
+      sizeof (SMBIOS_TABLE_TYPE32),            // UINT8 Length
+      SMBIOS_HANDLE_PI_RESERVED,
+    },
+    {0,0,0,0,0,0},                             //reserved
+    BootInformationStatusNoError,
+  },
+  TYPE32_STRINGS
+};
+
+STATIC CONST VOID *DefaultCommonTables[]=
+{
+  &mArmDefaultType0,
+  &mArmDefaultType1,
+  &mArmDefaultType2,
+  &mArmDefaultType3,
+  &mArmDefaultType7_a53_l1i,
+  &mArmDefaultType7_a53_l1d,
+  &mArmDefaultType7_a53_l2,
+  &mArmDefaultType4_a53,
+  &mArmDefaultType9_0,
+  &mArmDefaultType9_1,
+  &mArmDefaultType9_2,
+  &mArmDefaultType9_3,
+  &mArmDefaultType16,
+  &mArmDefaultType17,
+//    &mArmDefaultType19, //memory range type 19 dynamically generated
+  &mArmDefaultType32,
+  NULL
+};
+
+STATIC CONST VOID *DefaultTablesR0R1[]=
+{
+  &mArmDefaultType7_a57_l1i,
+  &mArmDefaultType7_a57_l1d,
+  &mArmDefaultType7_a57_l2,
+  &mArmDefaultType4_a57,
+  NULL
+};
+
+STATIC CONST VOID *DefaultTablesR2[]=
+{
+  &mArmDefaultType7_a57_l1i, // Cache layout is the same on the A72 vs A57
+  &mArmDefaultType7_a57_l1d,
+  &mArmDefaultType7_a57_l2,
+  &mArmDefaultType4_a72,
+  NULL
+};
+
+
+/**
+   Installs a memory descriptor (type19) for the given address range
+
+   @param  Smbios               SMBIOS protocol
+
+**/
+EFI_STATUS
+InstallMemoryStructure (
+  IN EFI_SMBIOS_PROTOCOL       *Smbios,
+  IN UINT64                    StartingAddress,
+  IN UINT64                    RegionLength
+  )
+{
+  EFI_SMBIOS_HANDLE         SmbiosHandle;
+  ARM_TYPE19                MemoryDescriptor;
+  EFI_STATUS                Status = EFI_SUCCESS;
+
+  CopyMem( &MemoryDescriptor, &mArmDefaultType19, sizeof(ARM_TYPE19));
+
+  MemoryDescriptor.Base.ExtendedStartingAddress = StartingAddress;
+  MemoryDescriptor.Base.ExtendedEndingAddress = StartingAddress+RegionLength;
+  SmbiosHandle = MemoryDescriptor.Base.Hdr.Handle;
+
+  Status = Smbios->Add (
+    Smbios,
+    NULL,
+    &SmbiosHandle,
+    (EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor
+    );
+  return Status;
+}
+
+/**
+   Install a whole table worth of structructures
+
+   @parm
+**/
+EFI_STATUS
+InstallStructures (
+   IN EFI_SMBIOS_PROTOCOL       *Smbios,
+   IN CONST VOID *DefaultTables[]
+   )
+{
+    EFI_STATUS                Status = EFI_SUCCESS;
+    EFI_SMBIOS_HANDLE         SmbiosHandle;
+
+    int TableEntry;
+    for ( TableEntry=0; DefaultTables[TableEntry] != NULL; TableEntry++)
+    {
+	SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER*)DefaultTables[TableEntry])->Handle;
+	Status = Smbios->Add (
+	    Smbios,
+	    NULL,
+	    &SmbiosHandle,
+	    (EFI_SMBIOS_TABLE_HEADER*) DefaultTables[TableEntry]
+	    );
+	if (EFI_ERROR(Status))
+	    break;
+    }
+    return Status;
+}
+
+
+/**
+   Install all structures from the DefaultTables structure
+
+   @param  Smbios               SMBIOS protocol
+
+**/
+EFI_STATUS
+InstallAllStructures (
+   IN EFI_SMBIOS_PROTOCOL       *Smbios
+   )
+{
+  EFI_STATUS                Status = EFI_SUCCESS;
+  UINT32                    JunoRevision;
+  VOID                      *ExtraTables = DefaultTablesR0R1;
+
+  GetJunoRevision(JunoRevision);
+
+  // Fixup some table values
+  mArmDefaultType0.Base.SystemBiosMajorRelease = (PcdGet32 ( PcdFirmwareRevision ) >> 16) & 0xFF;
+  mArmDefaultType0.Base.SystemBiosMinorRelease = PcdGet32 ( PcdFirmwareRevision ) & 0xFF;
+  if ( JunoRevision == JUNO_REVISION_R1 ) 
+  {
+    mArmDefaultType2.Base.Version = 6;
+  }
+  else if ( JunoRevision == JUNO_REVISION_R2 )
+  {
+    mArmDefaultType2.Base.Version = 7;
+    ExtraTables=DefaultTablesR2;
+  }
+
+  //
+  // Add all Juno table entries
+  //
+  Status=InstallStructures (Smbios,DefaultCommonTables);
+  ASSERT_EFI_ERROR (Status);
+
+  Status=InstallStructures (Smbios,ExtraTables);
+  ASSERT_EFI_ERROR (Status);
+
+  // Generate memory descriptors for the two memory ranges we know about
+  Status = InstallMemoryStructure ( Smbios, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemorySize));
+  ASSERT_EFI_ERROR (Status);
+  Status = InstallMemoryStructure ( Smbios, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+/**
+   Installs SMBIOS information for ARM platforms
+
+   @param ImageHandle     Module's image handle
+   @param SystemTable     Pointer of EFI_SYSTEM_TABLE
+
+   @retval EFI_SUCCESS    Smbios data successfully installed
+   @retval Other          Smbios data was not installed
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosTablePublishEntry (
+  IN EFI_HANDLE           ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+{
+  EFI_STATUS                Status;
+  EFI_SMBIOS_PROTOCOL       *Smbios;
+
+  //
+  // Find the SMBIOS protocol
+  //
+  Status = gBS->LocateProtocol (
+    &gEfiSmbiosProtocolGuid,
+    NULL,
+    (VOID**)&Smbios
+    );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = InstallAllStructures (Smbios);
+
+  return Status;
+}
diff --git a/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
new file mode 100644
index 0000000..457e1ff
--- /dev/null
+++ b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
@@ -0,0 +1,68 @@
+## @file
+#  This driver installs SMBIOS information for ArmJuno
+#
+#  Copyright (c) 2011, Bei Guan <gbtju85@gmail.com>
+#  Copyright (c) 2011, Intel Corporation. All rights reserved.
+#  Copyright (c) 2015, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SmbiosPlatformDxe
+  FILE_GUID                      = 4110465d-5ff3-4f4b-b580-24ed0d06747a
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = SmbiosTablePublishEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  SmbiosPlatformDxe.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  BaseMemoryLib
+  BaseLib
+  DebugLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  PcdLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[Guids]
+  gEfiGlobalVariableGuid
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision
+
+[Protocols]
+  gEfiSmbiosProtocolGuid                      # PROTOCOL ALWAYS_CONSUMED
+
+[Guids]
+
+[Depex]
+  gEfiSmbiosProtocolGuid
diff --git a/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf b/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000..59d3238
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
@@ -0,0 +1,43 @@
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = FvpAcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  Dsdt.asl
+  Spcr.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  Madt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dsdt.asl b/Platforms/ARM/VExpress/AcpiTables/Dsdt.asl
index 172ca3a..7e81ab7 100644
--- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dsdt.asl
+++ b/Platforms/ARM/VExpress/AcpiTables/Dsdt.asl
@@ -1,144 +1,144 @@
-/*
-* Copyright (c) 2013, Al Stone <al.stone@linaro.org>
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* 1. Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* 2. Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-*
-* NB: This License is also known as the "BSD 2-Clause License".
-*
-*
-* [DSDT] Description of the armv8 VE Model
-*
-*/
-
-DefinitionBlock (
-  "dsdt.aml",    // output filename
-  "DSDT",      // table signature
-  2,      // DSDT compliance revision
-  "LINARO",    // OEM ID
-  "RTSMVEV8",    // table ID
-  0x00000004)    // OEM revision
-{
-  Scope (\_SB)
-  {
-    Method (_OSC, 4, NotSerialized)
-    {
-      /* Platform-Wide OSPM Capabilities */
-      If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
-      {
-        /* APEI support unconditionally */
-        Return (Arg3)
-      } Else {
-        CreateDWordField (Arg3, Zero, CDW1)
-        /* Set invalid UUID error bit */
-        Or (CDW1, 0x04, CDW1)
-        Return (Arg3)
-      }
-    }
-
-    //
-    // Two Emulated aarch64 CPUs each with 4 cores
-    //
-    Device(CPU0) { // Cluster 0, Cpu 0
-      Name(_HID, "ACPI0007")
-      Name(_UID, 0)
-    }
-    Device(CPU1) { // Cluster 0, Cpu 1
-      Name(_HID, "ACPI0007")
-      Name(_UID, 1)
-    }
-    Device(CPU2) { // Cluster 0, Cpu 2
-      Name(_HID, "ACPI0007")
-      Name(_UID, 2)
-    }
-    Device(CPU3) { // Cluster 0, Cpu 3
-      Name(_HID, "ACPI0007")
-      Name(_UID, 3)
-    }
-    Device(CPU4) { // Cluster 1, Cpu 0
-      Name(_HID, "ACPI0007")
-      Name(_UID, 4)
-    }
-    Device(CPU5) { // Cluster 1, Cpu 1
-      Name(_HID, "ACPI0007")
-      Name(_UID, 5)
-    }
-    Device(CPU6) { // Cluster 1, Cpu 2
-      Name(_HID, "ACPI0007")
-      Name(_UID, 6)
-    }
-    Device(CPU7) { // Cluster 1, Cpu 3
-      Name(_HID, "ACPI0007")
-      Name(_UID, 7)
-    }
-
-    // SMC91X
-    Device (NET0) {
-      Name (_HID, "LNRO0003")
-      Name (_UID, 0)
-
-      Name (_CRS, ResourceTemplate () {
-        Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
-        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {0x2F}
-      })
-    }
-
-    // SYSREG
-    Device (SREG) {
-      Name (_HID, "LNRO0009")
-      Name (_UID, 0)
-
-      Method (_CRS, 0x0, Serialized) {
-        Name (RBUF, ResourceTemplate() {
-          Memory32Fixed (ReadWrite, 0x1c010000, 0x1000)
-        })
-        Return (RBUF)
-      }
-    }
-
-    // VIRTIO
-    Device (VIRT) {
-      Name (_HID, "LNRO0005")
-      Name (_UID, 0)
-
-      Name (_CRS, ResourceTemplate() {
-        Memory32Fixed (ReadWrite, 0x1c130000, 0x1000)
-        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x4A}
-      })
-    }
-
-    // UART PL011
-    Device(COM0) {
-      Name(_HID, "ARMH0011")
-      Name(_CID, "PL011")
-      Name(_UID, Zero)
-
-      Name(_CRS, ResourceTemplate() {
-        Memory32Fixed(ReadWrite, 0x1c090000, 0x1000)
-        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x25 }
-      })
-    }
-  }
-}
+/*
+* Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*
+* NB: This License is also known as the "BSD 2-Clause License".
+*
+*
+* [DSDT] Description of the armv8 VE Model
+*
+*/
+
+DefinitionBlock (
+  "dsdt.aml",    // output filename
+  "DSDT",      // table signature
+  2,      // DSDT compliance revision
+  "LINARO",    // OEM ID
+  "RTSMVEV8",    // table ID
+  0x00000004)    // OEM revision
+{
+  Scope (\_SB)
+  {
+    Method (_OSC, 4, NotSerialized)
+    {
+      /* Platform-Wide OSPM Capabilities */
+      If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
+      {
+        /* APEI support unconditionally */
+        Return (Arg3)
+      } Else {
+        CreateDWordField (Arg3, Zero, CDW1)
+        /* Set invalid UUID error bit */
+        Or (CDW1, 0x04, CDW1)
+        Return (Arg3)
+      }
+    }
+
+    //
+    // Two Emulated aarch64 CPUs each with 4 cores
+    //
+    Device(CPU0) { // Cluster 0, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 0)
+    }
+    Device(CPU1) { // Cluster 0, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 1)
+    }
+    Device(CPU2) { // Cluster 0, Cpu 2
+      Name(_HID, "ACPI0007")
+      Name(_UID, 2)
+    }
+    Device(CPU3) { // Cluster 0, Cpu 3
+      Name(_HID, "ACPI0007")
+      Name(_UID, 3)
+    }
+    Device(CPU4) { // Cluster 1, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 4)
+    }
+    Device(CPU5) { // Cluster 1, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 5)
+    }
+    Device(CPU6) { // Cluster 1, Cpu 2
+      Name(_HID, "ACPI0007")
+      Name(_UID, 6)
+    }
+    Device(CPU7) { // Cluster 1, Cpu 3
+      Name(_HID, "ACPI0007")
+      Name(_UID, 7)
+    }
+
+    // SMC91X
+    Device (NET0) {
+      Name (_HID, "LNRO0003")
+      Name (_UID, 0)
+
+      Name (_CRS, ResourceTemplate () {
+        Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {0x2F}
+      })
+    }
+
+    // SYSREG
+    Device (SREG) {
+      Name (_HID, "LNRO0009")
+      Name (_UID, 0)
+
+      Method (_CRS, 0x0, Serialized) {
+        Name (RBUF, ResourceTemplate() {
+          Memory32Fixed (ReadWrite, 0x1c010000, 0x1000)
+        })
+        Return (RBUF)
+      }
+    }
+
+    // VIRTIO
+    Device (VIRT) {
+      Name (_HID, "LNRO0005")
+      Name (_UID, 0)
+
+      Name (_CRS, ResourceTemplate() {
+        Memory32Fixed (ReadWrite, 0x1c130000, 0x1000)
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x4A}
+      })
+    }
+
+    // UART PL011
+    Device(COM0) {
+      Name(_HID, "ARMH0011")
+      Name(_CID, "PL011")
+      Name(_UID, Zero)
+
+      Name(_CRS, ResourceTemplate() {
+        Memory32Fixed(ReadWrite, 0x1c090000, 0x1000)
+        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x25 }
+      })
+    }
+  }
+}
diff --git a/Platforms/ARM/VExpress/AcpiTables/Fadt.aslc b/Platforms/ARM/VExpress/AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..087c191
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/Fadt.aslc
@@ -0,0 +1,86 @@
+/** @file
+*  Fixed ACPI Description Table (FADT)
+*
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "FvpPlatform.h"
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+  ARM_ACPI_HEADER (
+    EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
+    EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+  ),
+  0,                                                                        // UINT32     FirmwareCtrl
+  0,                                                                        // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
+  EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED,                                      // UINT8      PreferredPmProfile
+  0,                                                                        // UINT16     SciInt
+  0,                                                                        // UINT32     SmiCmd
+  0,                                                                        // UINT8      AcpiEnable
+  0,                                                                        // UINT8      AcpiDisable
+  0,                                                                        // UINT8      S4BiosReq
+  0,                                                                        // UINT8      PstateCnt
+  0,                                                                        // UINT32     Pm1aEvtBlk
+  0,                                                                        // UINT32     Pm1bEvtBlk
+  0,                                                                        // UINT32     Pm1aCntBlk
+  0,                                                                        // UINT32     Pm1bCntBlk
+  0,                                                                        // UINT32     Pm2CntBlk
+  0,                                                                        // UINT32     PmTmrBlk
+  0,                                                                        // UINT32     Gpe0Blk
+  0,                                                                        // UINT32     Gpe1Blk
+  0,                                                                        // UINT8      Pm1EvtLen
+  0,                                                                        // UINT8      Pm1CntLen
+  0,                                                                        // UINT8      Pm2CntLen
+  0,                                                                        // UINT8      PmTmrLen
+  0,                                                                        // UINT8      Gpe0BlkLen
+  0,                                                                        // UINT8      Gpe1BlkLen
+  0,                                                                        // UINT8      Gpe1Base
+  0,                                                                        // UINT8      CstCnt
+  0,                                                                        // UINT16     PLvl2Lat
+  0,                                                                        // UINT16     PLvl3Lat
+  0,                                                                        // UINT16     FlushSize
+  0,                                                                        // UINT16     FlushStride
+  0,                                                                        // UINT8      DutyOffset
+  0,                                                                        // UINT8      DutyWidth
+  0,                                                                        // UINT8      DayAlrm
+  0,                                                                        // UINT8      MonAlrm
+  0,                                                                        // UINT8      Century
+  0,                                                                        // UINT16     IaPcBootArch
+  0,                                                                        // UINT8      Reserved1
+  EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  ResetReg
+  0,                                                                        // UINT8      ResetValue
+  EFI_ACPI_6_1_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
+  EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
+  0,                                                                        // UINT64     XFirmwareCtrl
+  0,                                                                        // UINT64     XDsdt
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
+  NULL_GAS                                                                  // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Platforms/ARM/VExpress/AcpiTables/FvpPlatform.h b/Platforms/ARM/VExpress/AcpiTables/FvpPlatform.h
new file mode 100644
index 0000000..e3582bf
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/FvpPlatform.h
@@ -0,0 +1,46 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#ifndef _FVP_PLATFORM_H_
+#define _FVP_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID           'L','I','N','A','R','O'   // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('R','T','S','M','V','E','V','8') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION     0x00000002
+#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('L','N','R','O')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000002
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+  }
+
+#endif
diff --git a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..fc8f91f
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc
@@ -0,0 +1,166 @@
+/** @file
+*  Generic Timer Description Table (GTDT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Ltd. All rights reserved
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "FvpPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi61.h>
+
+#define FVP_SYSTEM_TIMER_BASE_ADDRESS   0x000000002a430000
+#define FVP_CNT_READ_BASE_ADDRESS       0x000000002a800000
+
+#define FVP_SECURE_TIMER_EL1_GSIV       0x1D
+#define FVP_NON_SECURE_TIMER_EL1_GSIV   0x1E
+#define FVP_VIRTUAL_TIMER_GSIV          0x1B
+#define FVP_NON_SECURE_EL2_GSIV         0x1A
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+#define GTDT_TIMER_SAVE_CONTEXT     EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+#define GTDT_TIMER_LOSE_CONTEXT     0
+
+#define FVP_GTDT_GTIMER_FLAGS       (GTDT_TIMER_LOSE_CONTEXT | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_EDGE_TRIGGERED)
+
+#define FVP_PLATFORM_TIMER_COUNT    2
+#define FVP_TIMER_FRAMES_COUNT      2
+#define FVP_WATCHDOG_COUNT          1
+
+#define FVP_GT_BLOCK_CTL_BASE           0x000000002A810000
+#define FVP_GT_BLOCK_FRAME0_CTL_BASE    0x000000002A820000
+#define FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE  0xFFFFFFFFFFFFFFFF
+#define FVP_GT_BLOCK_FRAME0_GSIV        0x39
+
+#define FVP_GT_BLOCK_FRAME1_CTL_BASE    0x000000002A830000
+#define FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE  0xFFFFFFFFFFFFFFFF
+#define FVP_GT_BLOCK_FRAME1_GSIV        0x3A
+
+#define GTX_TIMER_EDGE_TRIGGERED    EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTX_TIMER_LEVEL_TRIGGERED   0
+#define GTX_TIMER_ACTIVE_LOW        EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTX_TIMER_ACTIVE_HIGH       0
+
+#define FVP_GTX_TIMER_FLAGS         (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_SECURE            EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_NON_SECURE        0
+#define GTX_TIMER_SAVE_CONTEXT      EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_LOSE_CONTEXT      0
+
+#define FVP_GTX_COMMON_FLAGS        (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_SECURE)
+
+#define FVP_SBSA_WATCHDOG_REFRESH_BASE     0x000000002a450000
+#define FVP_SBSA_WATCHDOG_CONTROL_BASE     0x000000002a440000
+#define FVP_SBSA_WATCHDOG_GSIV             0x3B
+
+#define SBSA_WATCHDOG_EDGE_TRIGGERED   EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
+#define SBSA_WATCHDOG_LEVEL_TRIGGERED  0
+#define SBSA_WATCHDOG_ACTIVE_LOW       EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
+#define SBSA_WATCHDOG_ACTIVE_HIGH      0
+#define SBSA_WATCHDOG_SECURE           EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+#define SBSA_WATCHDOG_NON_SECURE       0
+
+#define FVP_SBSA_WATCHDOG_FLAGS            (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+  EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE                  GtBlock;
+  EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE            Frames[FVP_TIMER_FRAMES_COUNT];
+  EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdogs[FVP_WATCHDOG_COUNT];
+} FVP_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+  {
+    ARM_ACPI_HEADER(
+      EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+      FVP_GENERIC_TIMER_DESCRIPTION_TABLES,
+      EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+    ),
+    FVP_SYSTEM_TIMER_BASE_ADDRESS,                        // UINT64  PhysicalAddress
+    EFI_ACPI_RESERVED_DWORD,                              // UINT32  Reserved
+    FVP_SECURE_TIMER_EL1_GSIV,                            // UINT32  SecurePL1TimerGSIV
+    FVP_GTDT_GTIMER_FLAGS,                                // UINT32  SecurePL1TimerFlags
+    FVP_NON_SECURE_TIMER_EL1_GSIV,                        // UINT32  NonSecurePL1TimerGSIV
+    FVP_GTDT_GTIMER_FLAGS,                                // UINT32  NonSecurePL1TimerFlags
+    FVP_VIRTUAL_TIMER_GSIV,                               // UINT32  VirtualTimerGSIV
+    FVP_GTDT_GTIMER_FLAGS,                                // UINT32  VirtualTimerFlags
+    FVP_NON_SECURE_EL2_GSIV,                              // UINT32  NonSecurePL2TimerGSIV
+    FVP_GTDT_GTIMER_FLAGS,                                // UINT32  NonSecurePL2TimerFlags
+    FVP_CNT_READ_BASE_ADDRESS,                            // UINT64  CntReadBasePhysicalAddress
+    FVP_PLATFORM_TIMER_COUNT,                             // UINT32  PlatformTimerCount
+    sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32  PlatfromTimerOffset
+  },
+  {
+    EFI_ACPI_6_1_GTDT_GT_BLOCK,                           // UINT8 Type
+    sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE)          // UINT16 Length
+      + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE) *
+        FVP_TIMER_FRAMES_COUNT,
+    EFI_ACPI_RESERVED_BYTE,                               // UINT8 Reserved
+    FVP_GT_BLOCK_CTL_BASE,                                // UINT64 CntCtlBase
+    FVP_TIMER_FRAMES_COUNT,                               // UINT32 GTBlockTimerCount
+    sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE)          // UINT32 GTBlockTimerOffset
+  },
+  {
+    {
+      0,                                                    // UINT8 GTFrameNumber
+      {EFI_ACPI_RESERVED_BYTE,
+       EFI_ACPI_RESERVED_BYTE,
+       EFI_ACPI_RESERVED_BYTE},                             // UINT8 Reserved[3]
+      FVP_GT_BLOCK_FRAME0_CTL_BASE,                         // UINT64 CntBaseX
+      FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE,                     // UINT64 CntEL0BaseX
+      FVP_GT_BLOCK_FRAME0_GSIV,                             // UINT32 GTxPhysicalTimerGSIV
+      FVP_GTX_TIMER_FLAGS,                                  // UINT32 GTxPhysicalTimerFlags
+      0,                                                    // UINT32 GTxVirtualTimerGSIV
+      0,                                                    // UINT32 GTxVirtualTimerFlags
+      FVP_GTX_COMMON_FLAGS                                  // UINT32 GTxCommonFlags
+    },
+    {
+      1,                                                    // UINT8 GTFrameNumber
+      {EFI_ACPI_RESERVED_BYTE,
+       EFI_ACPI_RESERVED_BYTE,
+       EFI_ACPI_RESERVED_BYTE},                             // UINT8 Reserved[3]
+      FVP_GT_BLOCK_FRAME1_CTL_BASE,                         // UINT64 CntBaseX
+      FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE,                     // UINT64 CntEL0BaseX
+      FVP_GT_BLOCK_FRAME1_GSIV,                             // UINT32 GTxPhysicalTimerGSIV
+      FVP_GTX_TIMER_FLAGS,                                  // UINT32 GTxPhysicalTimerFlags
+      0,                                                    // UINT32 GTxVirtualTimerGSIV
+      0,                                                    // UINT32 GTxVirtualTimerFlags
+      FVP_GTX_COMMON_FLAGS                                  // UINT32 GTxCommonFlags
+    }
+  },
+  {
+    {
+      EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG,                // UINT8 Type
+      sizeof(EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), // UINT16 Length
+      EFI_ACPI_RESERVED_BYTE,                                 // UINT8 Reserved
+      FVP_SBSA_WATCHDOG_REFRESH_BASE,                         // UINT64 RefreshFramePhysicalAddress
+      FVP_SBSA_WATCHDOG_CONTROL_BASE,                         // UINT64 WatchdogControlFramePhysicalAddress
+      FVP_SBSA_WATCHDOG_GSIV,                                 // UINT32 WatchdogTimerGSIV
+      FVP_SBSA_WATCHDOG_FLAGS                                 // UINT32 WatchdogTimerFlags
+    }
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
new file mode 100644
index 0000000..bf90a9f
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
@@ -0,0 +1,91 @@
+/** @file
+*  Multiple APIC Description Table (MADT)
+*
+*  Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2016 Linaro Ltd. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "FvpPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi61.h>
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_6_1_GIC_STRUCTURE                            GicInterfaces[8];
+  EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+  EFI_ACPI_6_1_GICR_STRUCTURE                           Gicr;
+} FVP_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+  {
+    ARM_ACPI_HEADER (
+      EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+      FVP_MULTIPLE_APIC_DESCRIPTION_TABLE,
+      EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+    ),
+    //
+    // MADT specific fields
+    //
+    0, // LocalApicAddress
+    0, // Flags
+  },
+  {
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+        0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        0x2C02F000, 0x2C010000, 0x19, 0, 0),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+        1, 1, GET_MPID(0, 1),  EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        0x2C02F000, 0x2C010000, 0x19, 0, 0),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+        2, 2, GET_MPID(0, 2),  EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        0x2C02F000, 0x2C010000, 0x19, 0, 0),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+        3, 3, GET_MPID(0, 3),  EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        0x2C02F000, 0x2C010000, 0x19, 0, 0),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+        4, 4, GET_MPID(1, 0),  EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        0x2C02F000, 0x2C010000, 0x19, 0, 0),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+        5, 5, GET_MPID(1, 1),  EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        0x2C02F000, 0x2C010000, 0x19, 0, 0),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+        6, 6, GET_MPID(1, 2),  EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        0x2C02F000, 0x2C010000, 0x19, 0, 0),
+    EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+        7, 7, GET_MPID(1, 3),  EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
+        0x2C02F000, 0x2C010000, 0x19, 0, 0),
+  },
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
+  /* GIC Redistributor */
+  {
+    EFI_ACPI_6_1_GICR,                         // UINT8 Type
+    sizeof(EFI_ACPI_6_1_GICR_STRUCTURE),       // UINT8 Length
+    EFI_ACPI_RESERVED_WORD,                    // UINT16 Reserved
+    FixedPcdGet64 (PcdGicRedistributorsBase),  // UINT64 DiscoveryRangeBaseAddress
+    0x00200000,                                // UINT32 DiscoveryRangeLength
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platforms/ARM/VExpress/AcpiTables/Spcr.aslc b/Platforms/ARM/VExpress/AcpiTables/Spcr.aslc
new file mode 100644
index 0000000..68caa24
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/Spcr.aslc
@@ -0,0 +1,88 @@
+/** @file
+* SPCR Table
+*
+* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Ltd. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution.  The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "FvpPlatform.h"
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+/**
+ * References:
+ * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
+ **/
+
+
+///
+/// SPCR Flow Control
+///
+#define SPCR_FLOW_CONTROL_NONE           0
+
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+  ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+                     EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+                     EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
+  // UINT8                                   InterfaceType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+  // UINT8                                   Reserved1[3];
+  {
+    EFI_ACPI_RESERVED_BYTE,
+    EFI_ACPI_RESERVED_BYTE,
+    EFI_ACPI_RESERVED_BYTE
+  },
+  // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  BaseAddress;
+  ARM_GAS32 (0x1C090000),
+  // UINT8                                   InterruptType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+  // UINT8                                   Irq;
+  0,                                         // Not used on ARM
+  // UINT32                                  GlobalSystemInterrupt;
+  0x25,
+  // UINT8                                   BaudRate;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+  // UINT8                                   Parity;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+  // UINT8                                   StopBits;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+  // UINT8                                   FlowControl;
+  SPCR_FLOW_CONTROL_NONE,
+  // UINT8                                   TerminalType;
+  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+  // UINT8                                   Reserved2;
+  EFI_ACPI_RESERVED_BYTE,
+  // UINT16                                  PciDeviceId;
+  0xFFFF,
+  // UINT16                                  PciVendorId;
+  0xFFFF,
+  // UINT8                                   PciBusNumber;
+  0x00,
+  // UINT8                                   PciDeviceNumber;
+  0x00,
+  // UINT8                                   PciFunctionNumber;
+  0x00,
+  // UINT32                                  PciFlags;
+  0x00000000,
+  // UINT8                                   PciSegment;
+  0x00,
+  // UINT32                                  Reserved3;
+  EFI_ACPI_RESERVED_DWORD
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl
deleted file mode 100644
index 9cd3031..0000000
--- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * Copyright (c) 2013, Al Stone <al.stone@linaro.org>
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 
- * 1. Redistributions of source code must retain the above copyright 
- * notice, this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the 
- * documentation and/or other materials provided with the distribution.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * 
- * NB: This License is also known as the "BSD 2-Clause License".
- * 
- *
- * [APIC] Multiple APIC Description Table (MADT)
- * Format: [ByteLength]  FieldName : HexFieldValue
- *
- */
-
-[0004]                          Signature : "APIC"
-[0004]                       Table Length : 00000000
-[0001]                           Revision : 03
-[0001]                           Checksum : 00
-[0006]                             Oem ID : "LINARO"
-[0008]                       Oem Table ID : "RTSMVEV8"
-[0004]                       Oem Revision : 00000001
-[0004]                    Asl Compiler ID : "INTL"
-[0004]              Asl Compiler Revision : 20110623
-
-[0004]                 Local Apic Address : 2C000000
-[0004]              Flags (decoded below) : 00000000
-                      PC-AT Compatibility : 0
-
-[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
-[0001]                             Length : 50
-[0002]                           Reserved : 0000
-[0004]               CPU Interface Number : 00000000
-[0004]                      Processor UID : 00000000
-[0004]              Flags (decoded below) : 00000001
-                        Processor Enabled : 1
-       Performance Interrupt Trigger Mode : 0
-       Virtual GIC Interrupt Trigger Mode : 0
-[0004]           Parking Protocol Version : 00000000
-[0004]              Performance Interrupt : 00000000
-[0008]                     Parked Address : 0000000000000000
-[0008]                       Base Address : 000000002C000000  /* armv8 FVP Base GIC address */
-[0008]           Virtual GIC Base Address : 0
-[0008]        Hypervisor GIC Base Address : 0
-[0004]              Virtual GIC Interrupt : 0
-[0008]         Redistributor Base Address : 0
-[0008]                          ARM MPIDR : 0
-[0001]                   Efficiency Class : 00
-[0003]                           Reserved : 000000
-
-[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
-[0001]                             Length : 50
-[0002]                           Reserved : 0000
-[0004]               CPU Interface Number : 00000001
-[0004]                      Processor UID : 00000001
-[0004]              Flags (decoded below) : 00000001
-                        Processor Enabled : 1
-       Performance Interrupt Trigger Mode : 0
-       Virtual GIC Interrupt Trigger Mode : 0
-[0004]           Parking Protocol Version : 00000000
-[0004]              Performance Interrupt : 00000000
-[0008]                     Parked Address : 0000000000000000
-[0008]                       Base Address : 000000002C000000
-[0008]           Virtual GIC Base Address : 0
-[0008]        Hypervisor GIC Base Address : 0
-[0004]              Virtual GIC Interrupt : 0
-[0008]         Redistributor Base Address : 0
-[0008]                          ARM MPIDR : 0000000000000001
-[0001]                   Efficiency Class : 00
-[0003]                           Reserved : 000000
-
-[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
-[0001]                             Length : 50
-[0002]                           Reserved : 0000
-[0004]               CPU Interface Number : 00000002
-[0004]                      Processor UID : 00000002
-[0004]              Flags (decoded below) : 00000001
-                        Processor Enabled : 1
-       Performance Interrupt Trigger Mode : 0
-       Virtual GIC Interrupt Trigger Mode : 0
-[0004]           Parking Protocol Version : 00000000
-[0004]              Performance Interrupt : 00000000
-[0008]                     Parked Address : 0000000000000000
-[0008]                       Base Address : 000000002C000000
-[0008]           Virtual GIC Base Address : 0
-[0008]        Hypervisor GIC Base Address : 0
-[0004]              Virtual GIC Interrupt : 0
-[0008]         Redistributor Base Address : 0
-[0008]                          ARM MPIDR : 0000000000000002
-[0001]                   Efficiency Class : 00
-[0003]                           Reserved : 000000
-
-[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
-[0001]                             Length : 50
-[0002]                           Reserved : 0000
-[0004]               CPU Interface Number : 00000003
-[0004]                      Processor UID : 00000003
-[0004]              Flags (decoded below) : 00000001
-                        Processor Enabled : 1
-       Performance Interrupt Trigger Mode : 0
-       Virtual GIC Interrupt Trigger Mode : 0
-[0004]           Parking Protocol Version : 00000000
-[0004]              Performance Interrupt : 00000000
-[0008]                     Parked Address : 0000000000000000
-[0008]                       Base Address : 000000002C000000
-[0008]           Virtual GIC Base Address : 0
-[0008]        Hypervisor GIC Base Address : 0
-[0004]              Virtual GIC Interrupt : 0
-[0008]         Redistributor Base Address : 0
-[0008]                          ARM MPIDR : 0000000000000003
-[0001]                   Efficiency Class : 00
-[0003]                           Reserved : 000000
-
-[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
-[0001]                             Length : 50
-[0002]                           Reserved : 0000
-[0004]               CPU Interface Number : 00000004
-[0004]                      Processor UID : 00000004
-[0004]              Flags (decoded below) : 00000001
-                        Processor Enabled : 1
-       Performance Interrupt Trigger Mode : 0
-       Virtual GIC Interrupt Trigger Mode : 0
-[0004]           Parking Protocol Version : 00000000
-[0004]              Performance Interrupt : 00000000
-[0008]                     Parked Address : 0000000000000000
-[0008]                       Base Address : 000000002C000000
-[0008]           Virtual GIC Base Address : 0
-[0008]        Hypervisor GIC Base Address : 0
-[0004]              Virtual GIC Interrupt : 0
-[0008]         Redistributor Base Address : 0
-[0008]                          ARM MPIDR : 0000000000000100
-[0001]                   Efficiency Class : 00
-[0003]                           Reserved : 000000
-
-[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
-[0001]                             Length : 50
-[0002]                           Reserved : 0000
-[0004]               CPU Interface Number : 00000005
-[0004]                      Processor UID : 00000005
-[0004]              Flags (decoded below) : 00000001
-                        Processor Enabled : 1
-       Performance Interrupt Trigger Mode : 0
-       Virtual GIC Interrupt Trigger Mode : 0
-[0004]           Parking Protocol Version : 00000000
-[0004]              Performance Interrupt : 00000000
-[0008]                     Parked Address : 0000000000000000
-[0008]                       Base Address : 000000002C000000
-[0008]           Virtual GIC Base Address : 0
-[0008]        Hypervisor GIC Base Address : 0
-[0004]              Virtual GIC Interrupt : 0
-[0008]         Redistributor Base Address : 0
-[0008]                          ARM MPIDR : 0000000000000101
-[0001]                   Efficiency Class : 00
-[0003]                           Reserved : 000000
-
-[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
-[0001]                             Length : 50
-[0002]                           Reserved : 0000
-[0004]               CPU Interface Number : 00000006
-[0004]                      Processor UID : 00000006
-[0004]              Flags (decoded below) : 00000001
-                        Processor Enabled : 1
-       Performance Interrupt Trigger Mode : 0
-       Virtual GIC Interrupt Trigger Mode : 0
-[0004]           Parking Protocol Version : 00000000
-[0004]              Performance Interrupt : 00000000
-[0008]                     Parked Address : 0000000000000000
-[0008]                       Base Address : 000000002C000000
-[0008]           Virtual GIC Base Address : 0
-[0008]        Hypervisor GIC Base Address : 0
-[0004]              Virtual GIC Interrupt : 0
-[0008]         Redistributor Base Address : 0
-[0008]                          ARM MPIDR : 0000000000000102
-[0001]                   Efficiency Class : 00
-[0003]                           Reserved : 000000
-
-[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
-[0001]                             Length : 50
-[0002]                           Reserved : 0000
-[0004]               CPU Interface Number : 00000007
-[0004]                      Processor UID : 00000007
-[0004]              Flags (decoded below) : 00000001
-                        Processor Enabled : 1
-       Performance Interrupt Trigger Mode : 0
-       Virtual GIC Interrupt Trigger Mode : 0
-[0004]           Parking Protocol Version : 00000000
-[0004]              Performance Interrupt : 00000000
-[0008]                     Parked Address : 0000000000000000
-[0008]                       Base Address : 000000002C000000
-[0008]           Virtual GIC Base Address : 0
-[0008]        Hypervisor GIC Base Address : 0
-[0004]              Virtual GIC Interrupt : 0
-[0008]         Redistributor Base Address : 0
-[0008]                          ARM MPIDR : 0000000000000103
-[0001]                   Efficiency Class : 00
-[0003]                           Reserved : 000000
-
-[0001]                      Subtable Type : 0C [Generic Interrupt Distributor]
-[0001]                             Length : 18
-[0002]                           Reserved : 0000
-[0004]              Local GIC Hardware ID : 00000000
-[0008]                       Base Address : 000000002F000000 /* armv8 FVP Base GIC distributor base addr */
-[0004]                     Interrupt Base : 00000000
-[0001]                            Version : 02
-[0003]                           Reserved : 000000
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dbg2.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dbg2.asl
deleted file mode 100644
index 47cee69..0000000
--- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/dbg2.asl
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2015, Graeme Gregory <graeme.gregory@linaro.org>
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 
- * 1. Redistributions of source code must retain the above copyright 
- * notice, this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the 
- * documentation and/or other materials provided with the distribution.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * 
- * NB: This License is also known as the "BSD 2-Clause License".
- * 
- *
- * [DBG2] ACPI Table
- *
- */
-
-[0004]                    Signature : "DBG2"    [Debug Port table type 2]
-[0004]                 Table Length : 0000005A
-[0001]                     Revision : 00
-[0001]                     Checksum : 06
-[0006]                       Oem ID : "LINARO"
-[0008]                 Oem Table ID : "RTSMVEV8"
-[0004]                 Oem Revision : 00000000
-[0004]              Asl Compiler ID : "INTL"
-[0004]        Asl Compiler Revision : 20140926
-
-[0004]                  Info Offset : 0000002C
-[0004]                   Info Count : 00000001
-
-[0001]                     Revision : 00
-[0002]                       Length : 002C
-[0001]               Register Count : 01
-[0002]              Namepath Length : 0005
-[0002]              Namepath Offset : 0026
-[0002]              OEM Data Length : 0000 [Optional field not present]
-[0002]              OEM Data Offset : 0000 [Optional field not present]
-[0002]                    Port Type : 8000
-[0002]                 Port Subtype : 0003
-[0002]                     Reserved : 0000
-[0002]          Base Address Offset : 0016
-[0002]          Address Size Offset : 0022
-
-[000C]        Base Address Register : [Generic Address Structure]
-[0001]                     Space ID : 00 [SystemMemory]
-[0001]                    Bit Width : 20
-[0001]                   Bit Offset : 00
-[0001]         Encoded Access Width : 03 [DWord Access:32]
-[0008]                      Address : 000000001C090000
-
-[0004]                 Address Size : 00001000
-
-[0004]                     Namepath : "COM1"
-[0001]                     OEM Data : 00
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl
deleted file mode 100644
index c288ae2..0000000
--- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/facp.asl
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright (c) 2013, Al Stone <al.stone@linaro.org>
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 
- * 1. Redistributions of source code must retain the above copyright 
- * notice, this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the 
- * documentation and/or other materials provided with the distribution.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * 
- * NB: This License is also known as the "BSD 2-Clause License".
- * 
- *
- * [FACP] ACPI Table
- *
- */
-
-[0004]                          Signature : "FACP"
-[0004]                       Table Length : 0000010C
-[0001]                           Revision : 05
-[0001]                           Checksum : 18
-[0006]                             Oem ID : "LINARO"
-[0008]                       Oem Table ID : "RTSMVEV8"
-[0004]                       Oem Revision : 00000000
-[0004]                    Asl Compiler ID : "INTL"
-[0004]              Asl Compiler Revision : 20111123
-
-[0004]                       FACS Address : 00000000
-[0004]                       DSDT Address : 00000010
-[0001]                              Model : 00
-[0001]                         PM Profile : 04          /* Enterprise Server */
-[0002]                      SCI Interrupt : 0000
-[0004]                   SMI Command Port : 00000000
-[0001]                  ACPI Enable Value : 00
-[0001]                 ACPI Disable Value : 00
-[0001]                     S4BIOS Command : 00
-[0001]                    P-State Control : 00
-[0004]           PM1A Event Block Address : 00000001
-[0004]           PM1B Event Block Address : 00000000
-[0004]         PM1A Control Block Address : 00000001
-[0004]         PM1B Control Block Address : 00000000
-[0004]          PM2 Control Block Address : 00000001
-[0004]             PM Timer Block Address : 00000001
-[0004]                 GPE0 Block Address : 00000001
-[0004]                 GPE1 Block Address : 00000000
-[0001]             PM1 Event Block Length : 04
-[0001]           PM1 Control Block Length : 02
-[0001]           PM2 Control Block Length : 01
-[0001]              PM Timer Block Length : 04
-[0001]                  GPE0 Block Length : 08
-[0001]                  GPE1 Block Length : 00
-[0001]                   GPE1 Base Offset : 00
-[0001]                       _CST Support : 00
-[0002]                         C2 Latency : 0000
-[0002]                         C3 Latency : 0000
-[0002]                     CPU Cache Size : 0000
-[0002]                 Cache Flush Stride : 0000
-[0001]                  Duty Cycle Offset : 00
-[0001]                   Duty Cycle Width : 00
-[0001]                RTC Day Alarm Index : 00
-[0001]              RTC Month Alarm Index : 00
-[0001]                  RTC Century Index : 00
-[0002]         Boot Flags (decoded below) : 0000
-            Legacy Devices Supported (V2) : 0
-         8042 Present on ports 60/64 (V2) : 0
-                     VGA Not Present (V4) : 0
-                   MSI Not Supported (V4) : 0
-             PCIe ASPM Not Supported (V4) : 0
-                CMOS RTC Not Present (V5) : 0
-[0001]                           Reserved : 00
-[0004]              Flags (decoded below) : 00000000
-   WBINVD instruction is operational (V1) : 1
-           WBINVD flushes all caches (V1) : 1
-                 All CPUs support C1 (V1) : 0
-               C2 works on MP system (V1) : 0
-         Control Method Power Button (V1) : 1
-         Control Method Sleep Button (V1) : 1
-     RTC wake not in fixed reg space (V1) : 0
-         RTC can wake system from S4 (V1) : 0
-                     32-bit PM Timer (V1) : 0
-                   Docking Supported (V1) : 0
-            Reset Register Supported (V2) : 0
-                         Sealed Case (V3) : 0
-                 Headless - No Video (V3) : 1
-     Use native instr after SLP_TYPx (V3) : 0
-           PCIEXP_WAK Bits Supported (V4) : 0
-                  Use Platform Timer (V4) : 0
-            RTC_STS valid on S4 wake (V4) : 0
-             Remote Power-on capable (V4) : 1
-              Use APIC Cluster Model (V4) : 0
-  Use APIC Physical Destination Mode (V4) : 0
-                    Hardware Reduced (V5) : 1
-                   Low Power S0 Idle (V5) : 1
-
-[0012]                     Reset Register : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 08
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 01 [Byte Access:8]
-[0008]                            Address : 0000000000000001
-
-[0001]               Value to cause reset : 00
-[0002]      ARM_BOOT_ARCH (decoded below) : 0001
-                            Use PSCI 0.2+ : 1
-                             PSCI Use HVC : 0
-[0001]                FADT Minor Revision : 01
-[0008]                       FACS Address : 0000000000000000
-[0008]                       DSDT Address : 0000000000000010
-[0012]                   PM1A Event Block : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 20
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 02 [Word Access:16]
-[0008]                            Address : 0000000000000001
-
-[0012]                   PM1B Event Block : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 00
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 00 [Undefined/Legacy]
-[0008]                            Address : 0000000000000000
-
-[0012]                 PM1A Control Block : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 10
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 02 [Word Access:16]
-[0008]                            Address : 0000000000000001
-
-[0012]                 PM1B Control Block : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 00
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 00 [Undefined/Legacy]
-[0008]                            Address : 0000000000000000
-
-[0012]                  PM2 Control Block : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 08
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 00 [Undefined/Legacy]
-[0008]                            Address : 0000000000000001
-
-[0012]                     PM Timer Block : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 20
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 03 [DWord Access:32]
-[0008]                            Address : 0000000000000001
-
-[0012]                         GPE0 Block : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 80
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 01 [Byte Access:8]
-[0008]                            Address : 0000000000000001
-
-[0012]                         GPE1 Block : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 00
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 00 [Undefined/Legacy]
-[0008]                            Address : 0000000000000000
-
-
-[0012]             Sleep Control Register : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 08
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 01 [Byte Access:8]
-[0008]                            Address : 0000000000000000
-
-[0012]              Sleep Status Register : [Generic Address Structure]
-[0001]                           Space ID : 01 [SystemIO]
-[0001]                          Bit Width : 08
-[0001]                         Bit Offset : 00
-[0001]               Encoded Access Width : 01 [Byte Access:8]
-[0008]                            Address : 0000000000000000
-
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl
deleted file mode 100644
index d304243..0000000
--- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/gtdt.asl
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (c) 2013, Al Stone <al.stone@linaro.org>
- *                     Hanjun Guo <hanjun.guo@linaro.org>
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 
- * 1. Redistributions of source code must retain the above copyright 
- * notice, this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the 
- * documentation and/or other materials provided with the distribution.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * 
- * NB: This License is also known as the "BSD 2-Clause License".
- * 
- *
- * [GTDT] Generic Timer Description Table
- * Format: [ByteLength]  FieldName : HexFieldValue
- *
- */
-
-[0004]                          Signature : "GTDT"
-[0004]                       Table Length : 00000050
-[0001]                           Revision : 02
-[0001]                           Checksum : F1
-[0006]                             Oem ID : "LINARO"
-[0008]                       Oem Table ID : "RTSMVEV8"
-[0004]                       Oem Revision : 00000001
-[0004]                    Asl Compiler ID : "INTL"
-[0004]              Asl Compiler Revision : 20110623
-
-[0008]              Counter Block Address : 0000000000000000
-[0004]                           Reserved : 00000000
-
-/* In RTSM model's dts file, the last cell of interrupts
- * is 0xff01, it means its cpu mask is FF, and trigger type
- * and flag is 1 = low-to-high edge triggered.
- * 
- * so in ACPI the Trigger Mode is 1 - Edge triggered, and 
- * Polarity is 0 - Active high as ACPI spec describled.
- *
- * using direct mapping for hwirqs, it means that we using
- * ID [16, 31] for PPI, not [0, 15] used in FDT.
- */
-[0004]               Secure EL1 Interrupt : 0000001d
-[0004]         SEL1 Flags (decoded below) : 00000001
-                             Trigger Mode : 1
-                                 Polarity : 0
-                                Always-on : 0
-
-[0004]           Non-Secure EL1 Interrupt : 0000001e
-[0004]        NSEL1 Flags (decoded below) : 00000001
-                             Trigger Mode : 1
-                                 Polarity : 0
-                                Always-on : 0
-
-[0004]            Virtual Timer Interrupt : 0000001b
-[0004]           VT Flags (decoded below) : 00000001
-                             Trigger Mode : 1
-                                 Polarity : 0
-                                Always-on : 0
-
-[0004]           Non-Secure EL2 Interrupt : 0000001a
-[0004]        NSEL2 Flags (decoded below) : 00000001
-                             Trigger Mode : 1
-                                 Polarity : 0
-				Always-on : 0
-
-/* The 64-bit physical address at which the Counter Read block is located */
-[0008]	     CntReadBase Physical address : 0000000000000000
-
-[0004]               Platform Timer Count : 00000001
-[0004]              Platform Timer Offset : 0000005C
-
-/* Memory-mapped GT (Generic Timer) structures */
-[0001]                      Subtable Type : 00
-[0002]                             Length : 0064
-[0001]                           Reserved : 000000
-[0008]                      Block Address : 000000002a810000
-[0004]                        Timer Count : 00000001
-[0004]                       Timer Offset : 00000010
-
-/* One frame is available */
-[0001]                       Frame Number : 00
-[0003]                           Reserved : 000000
-[0008]                       Base Address : 000000002a820000
-[0008]                   EL0 Base Address : FFFFFFFFFFFFFFFF
-[0004]                    Timer Interrupt : 00000029 /* 25+16 */
-[0004]        Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */
-                             Trigger Mode : 0
-                                 Polarity : 0
-/* No virtual timer */
-[0004]            Virtual Timer Interrupt : 00000000
-[0004] Virtual Timer Flags (decoded below) : 00000000
-                             Trigger Mode : 0
-                                 Polarity : 0
-[0004]       Common Flags (decoded below) : 00000000
-                                   Secure : 0
-                                Always On : 0
-
diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/spcr.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/spcr.asl
deleted file mode 100644
index 9d0edba..0000000
--- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/spcr.asl
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2015, Graeme Gregory <graeme.gregory@linaro.org>
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 
- * 1. Redistributions of source code must retain the above copyright 
- * notice, this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the 
- * documentation and/or other materials provided with the distribution.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * 
- * NB: This License is also known as the "BSD 2-Clause License".
- * 
- *
- * [SPCR] ACPI Table
- *
- */
-
-[0004]                    Signature : "SPCR"    [Serial Port Console Redirection table]
-[0004]                 Table Length : 00000050
-[0001]                     Revision : 02
-[0001]                     Checksum : 29
-[0006]                       Oem ID : "LINARO"
-[0008]                 Oem Table ID : "RTSMVEV8"
-[0004]                 Oem Revision : 00000000
-[0004]              Asl Compiler ID : "INTL"
-[0004]        Asl Compiler Revision : 20140926
-
-[0001]               Interface Type : 03
-[0003]                     Reserved : 000000
-
-[000C]         Serial Port Register : [Generic Address Structure]
-[0001]                     Space ID : 00 [SystemMemory]
-[0001]                    Bit Width : 20
-[0001]                   Bit Offset : 00
-[0001]         Encoded Access Width : 03 [DWord Access:32]
-[0008]                      Address : 000000001C090000
-
-[0001]               Interrupt Type : 08
-[0001]          PCAT-compatible IRQ : 00
-[0004]                    Interrupt : 00000025
-[0001]                    Baud Rate : 07
-[0001]                       Parity : 00
-[0001]                    Stop Bits : 01
-[0001]                 Flow Control : 00
-[0001]                Terminal Type : 03
-[0001]                     Reserved : 00
-[0002]                PCI Device ID : FFFF
-[0002]                PCI Vendor ID : FFFF
-[0001]                      PCI Bus : 00
-[0001]                   PCI Device : 00
-[0001]                 PCI Function : 00
-[0004]                    PCI Flags : 00000000
-[04Bh]                  PCI Segment : 00
-[04Ch]                     Reserved : 00000000
-
diff --git a/Platforms/ARM/VExpress/ArmVExpress-RTSM-A15_MPCore.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc
index b0a4268..69048a3 100644
--- a/Platforms/ARM/VExpress/ArmVExpress-RTSM-A15_MPCore.dsc
+++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc
@@ -1,293 +1,288 @@
-#
-#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
-  PLATFORM_NAME                  = ArmVExpressPkg-RTSM-A15_MPCore
-  PLATFORM_GUID                  = 3a91a0f8-3af4-409d-a71d-a199dc134357
-  PLATFORM_VERSION               = 0.1
-  DSC_SPECIFICATION              = 0x00010005
-  OUTPUT_DIRECTORY               = Build/ArmVExpress-RTSM-A15_MPCore
-  SUPPORTED_ARCHITECTURES        = ARM
-  BUILD_TARGETS                  = DEBUG|RELEASE
-  SKUID_IDENTIFIER               = DEFAULT
-  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress-RTSM-A15_MPCore.fdf
-
-!include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress.dsc.inc
-
-[LibraryClasses.common]
-  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
-  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
-  ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
-
-  ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
-  NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
-  LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
-
-  #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
-
-  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
-
-  # Virtio Support
-  VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
-  VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf
-
-[LibraryClasses.common.SEC]
-  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
-  ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf
-  ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
-
-[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
-  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
-
-[BuildOptions]
-  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM
-
-  GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM
-
-  XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM
-
-################################################################################
-#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
-#
-################################################################################
-
-[PcdsFeatureFlag.common]
-!ifdef EDK2_SKIP_PEICORE
-  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
-  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
-!endif
-
-  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
-  #  It could be set FALSE to save size.
-  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
-
-[PcdsFixedAtBuild.common]
-  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress-RTSM"
-
-  gArmPlatformTokenSpaceGuid.PcdCoreCount|2
-
-  #
-  # NV Storage PCDs. Use base of 0x0C000000 for NOR1
-  #
-!if $(EDK2_ARMVE_SUPPORT_QEMU) == 1
-  # QEMU only models a single flash block size, so use larger blocks
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FF00000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00040000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FF40000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00040000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FF80000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00040000
-!else
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
-!endif
-
-  gArmTokenSpaceGuid.PcdVFPEnabled|1
-
-  # Stacks for MPCores in Secure World
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E009000
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000
-
-  # Stacks for MPCores in Monitor Mode
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
-
-  # Stacks for MPCores in Normal World
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000
-  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
-
-  # System Memory (1GB)
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
-
-  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
-  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
-
-  #
-  # ARM Pcds
-  #
-  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
-
-  #
-  # ARM PrimeCell
-  #
-
-  ## SP805 Watchdog - Motherboard Watchdog
-  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000
-
-  ## PL011 - Serial Terminal
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400
-
-  ## PL031 RealTimeClock
-  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
-
-  ## PL111 Versatile Express Motherboard controller
-  gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000
-
-  ## PL180 MMC/SD card controller
-  gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
-  gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
-
-  #
-  # ARM General Interrupt Controller
-  #
-  gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000
-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000
-
-  #
-  # ARM OS Loader
-  #
-  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SemiHosting"
-  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"Fv(12C68BE9-0996-49D3-8C5B-4957379027EE)/LinuxLoader.efi"
-  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/Image -c \"console=ttyAMA0,38400 earlyprintk debug verbose\""
-
-  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
-  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
-  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
-
-  #
-  # ARM Architectural Timer Frequency
-  #
-  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000
-
-[PcdsDynamicDefault.common]
-  #
-  # The size of a dynamic PCD of the (VOID*) type can not be increased at run
-  # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128
-  # character "empty" string, to allow to be able to set FDT text device paths
-  # up to 128 characters long.
-  #
-  gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L"                                                                                                                                "
-
-################################################################################
-#
-# Components Section - list of all EDK II Modules needed by this Platform
-#
-################################################################################
-[Components.common]
-
-  #
-  # SEC
-  #
-  ArmPlatformPkg/Sec/Sec.inf {
-    <LibraryClasses>
-      # Use the implementation which set the Secure bits
-      ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
-  }
-
-  #
-  # PEI Phase modules
-  #
-!ifdef EDK2_SKIP_PEICORE
-  ArmPlatformPkg/PrePi/PeiMPCore.inf {
-    <LibraryClasses>
-      ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
-      ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
-  }
-!else
-  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
-  MdeModulePkg/Core/Pei/PeiMain.inf
-  MdeModulePkg/Universal/PCD/Pei/Pcd.inf  {
-    <LibraryClasses>
-      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-  }
-  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
-  ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
-  ArmPkg/Drivers/CpuPei/CpuPei.inf
-  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
-  Nt32Pkg/BootModePei/BootModePei.inf
-  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
-  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
-    <LibraryClasses>
-      NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
-  }
-!endif
-
-  #
-  # DXE
-  #
-  MdeModulePkg/Core/Dxe/DxeMain.inf {
-    <LibraryClasses>
-      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
-  }
-
-  #
-  # Architectural Protocols
-  #
-  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
-  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
-  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
-  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
-  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
-
-  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
-  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
-  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
-  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
-  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
-
-  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-
-  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
-  ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
-  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-  ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
-  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
-
-  #
-  # Semi-hosting filesystem
-  #
-  ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
-
-  #
-  # Multimedia Card Interface
-  #
-  EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
-  ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
-
-  #
-  # Platform Driver
-  #
-  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf
-  OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
-
-  #
-  # FAT filesystem + GPT/MBR partitioning
-  #
-  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
-  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
-  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-
-  #
-  # Bds
-  #
-  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-  ArmPlatformPkg/Bds/Bds.inf
+#
+#  Copyright (c) 2012-2015, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ArmVExpressPkg-CTA15-A7
+  PLATFORM_GUID                  = 0b511920-978d-4b34-acc0-3d9f8e6f9d81
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+!ifdef $(EDK2_OUT_DIR)
+  OUTPUT_DIRECTORY               = $(EDK2_OUT_DIR)
+!else
+  OUTPUT_DIRECTORY               = Build/ArmVExpress-CTA15-A7
+!endif
+  SUPPORTED_ARCHITECTURES        = ARM
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf
+
+  DEFINE EDK2_SKIP_PEICORE = 1
+  DEFINE ARM_BIGLITTLE_TC2 = 1 # We build for the TC2 hardware by default
+
+!include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf
+
+  ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+  NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+
+  #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
+
+  # ARM General Interrupt Driver in Secure and Non-secure
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+
+  LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf
+
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+
+[BuildOptions]
+!ifdef ARM_BIGLITTLE_TC2
+  *_*_ARM_ARCHCC_FLAGS  = -DARM_BIGLITTLE_TC2=1
+  *_*_ARM_PP_FLAGS  = -DARM_BIGLITTLE_TC2=1
+!endif
+
+  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7
+
+  GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7
+
+  XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress-CTA15-A7"
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|5
+
+  #
+  # NV Storage PCDs. Use base of 0x0C000000 for NOR1
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
+
+  gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+  # Stacks for MPCores in Secure World
+  # SRAM (CS1) is only available between 0x14000000 and 0x14001000 on the model
+  # ZBT SRAM is available between 0x2E000000 and 0x2E010000 on the model
+!ifdef ARM_BIGLITTLE_TC2
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x17000000
+!else
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E000000
+!endif
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x8000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000
+  # Share Monitor stacks with Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0
+
+  # System Memory (1GB) - An additional 1GB will be added if UEFI is running on a 2GB Test Chip
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+
+!ifdef ARM_BIGLITTLE_TC2
+  # TC2 Dual-Cluster profile
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|2
+
+  # Core Ids and Gic values
+  # A15_0 = 0x000, GicCoreId = 0
+  # A15_1 = 0x001, GicCoreId = 1
+  #  A7_0 = 0x100, GicCoreId = 2
+  #  A7_1 = 0x101, GicCoreId = 3
+  #  A7_2 = 0x102, GicCoreId = 4
+  gArmTokenSpaceGuid.PcdArmPrimaryCore|0x100
+!endif
+
+  #
+  # ARM PrimeCell
+  #
+
+  ## SP805 Watchdog - Motherboard Watchdog
+  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000
+
+  ## PL011 - Serial Terminal
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C090000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+
+  ## PL031 RealTimeClock
+  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
+
+!ifdef ARM_BIGLITTLE_TC2
+  ## PL111 Lcd & HdLcd
+  gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000
+  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x2B000000
+  gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|5
+!endif
+
+  #
+  # PL180 MMC/SD card controller
+  #
+  gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
+  gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
+
+
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000
+
+  # ISP1761 USB OTG Controller
+  gEmbeddedTokenSpaceGuid.PcdIsp1761BaseAddress|0x1B000000
+
+  # Ethernet (SMSC LAN9118)
+  gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x1A000000
+  gEmbeddedTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout|400000
+
+  #
+  # Define the device path to the FDT for the platform
+  #
+  gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/ca15a7"
+
+  #
+  # ARM Architectural Timer Frequency
+  #
+!ifdef ARM_BIGLITTLE_TC2
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|24000000
+!else
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|10000000
+!endif
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiMPCore.inf {
+    <LibraryClasses>
+      ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  }
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+  #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
+  ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  #
+  # Platform
+  #
+  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
+
+  #
+  # Filesystems
+  #
+!ifndef ARM_BIGLITTLE_TC2
+  ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+!endif
+
+  #
+  # Multimedia Card Interface
+  #
+  EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+  # SMSC LAN 9118
+  EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
diff --git a/Platforms/ARM/VExpress/ArmVExpress-RTSM-A15_MPCore.fdf b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf
index 456df10..9074615 100644
--- a/Platforms/ARM/VExpress/ArmVExpress-RTSM-A15_MPCore.fdf
+++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf
@@ -1,354 +1,330 @@
-#
-#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-################################################################################
-#
-# FD Section
-# The [FD] Section is made up of the definition statements and a
-# description of what goes into  the Flash Device Image.  Each FD section
-# defines one flash "device" image.  A flash device image may be one of
-# the following: Removable media bootable image (like a boot floppy
-# image,) an Option ROM image (that would be "flashed" into an add-in
-# card,) a System "Flash"  image (that would be burned into a system's
-# flash) or an Update ("Capsule") image that will be used to update and
-# existing system flash.
-#
-################################################################################
-
-[FD.RTSM_VE_Cortex-A15_MPCore_EFI]
-BaseAddress   = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
-Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
-ErasePolarity = 1
-
-# This one is tricky, it must be: BlockSize * NumBlocks = Size
-BlockSize     = 0x00001000
-NumBlocks     = 0x300
-
-################################################################################
-#
-# Following are lists of FD Region layout which correspond to the locations of different
-# images within the flash device.
-#
-# Regions must be defined in ascending order and may not overlap.
-#
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
-# the pipe "|" character, followed by the size of the region, also in hex with the leading
-# "0x" characters. Like:
-# Offset|Size
-# PcdOffsetCName|PcdSizeCName
-# RegionType <FV, DATA, or FILE>
-#
-################################################################################
-
-0x00000000|0x00080000
-gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
-FV = FVMAIN_SEC
-
-0x00080000|0x00280000
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
-FV = FVMAIN_COMPACT
-
-
-################################################################################
-#
-# FV Section
-#
-# [FV] section is used to define what components or modules are placed within a flash
-# device file.  This section also defines order the components and modules are positioned
-# within the image.  The [FV] section consists of define statements, set statements and
-# module statements.
-#
-################################################################################
-
-[FV.FVMAIN_SEC]
-FvAlignment        = 8
-ERASE_POLARITY     = 1
-MEMORY_MAPPED      = TRUE
-STICKY_WRITE       = TRUE
-LOCK_CAP           = TRUE
-LOCK_STATUS        = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP  = TRUE
-WRITE_STATUS       = TRUE
-WRITE_LOCK_CAP     = TRUE
-WRITE_LOCK_STATUS  = TRUE
-READ_DISABLED_CAP  = TRUE
-READ_ENABLED_CAP   = TRUE
-READ_STATUS        = TRUE
-READ_LOCK_CAP      = TRUE
-READ_LOCK_STATUS   = TRUE
-
-  INF ArmPlatformPkg/Sec/Sec.inf
-
-
-[FV.FvMain]
-BlockSize          = 0x40
-NumBlocks          = 0         # This FV gets compressed so make it just big enough
-FvAlignment        = 8         # FV alignment and FV attributes setting.
-ERASE_POLARITY     = 1
-MEMORY_MAPPED      = TRUE
-STICKY_WRITE       = TRUE
-LOCK_CAP           = TRUE
-LOCK_STATUS        = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP  = TRUE
-WRITE_STATUS       = TRUE
-WRITE_LOCK_CAP     = TRUE
-WRITE_LOCK_STATUS  = TRUE
-READ_DISABLED_CAP  = TRUE
-READ_ENABLED_CAP   = TRUE
-READ_STATUS        = TRUE
-READ_LOCK_CAP      = TRUE
-READ_LOCK_STATUS   = TRUE
-FvNameGuid         = 12c68be9-0996-49d3-8c5b-4957379027ee
-
-  APRIORI DXE {
-    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
-  }
-
-  INF MdeModulePkg/Core/Dxe/DxeMain.inf
-  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
-
-  #
-  # PI DXE Drivers producing Architectural Protocols (EFI Services)
-  #
-  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
-  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
-  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
-  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
-  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
-
-  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-
-  #
-  # Multiple Console IO support
-  #
-  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
-  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
-  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
-  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
-  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
-
-  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
-  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-  INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
-  INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
-  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
-
-  #
-  # Semi-hosting filesystem
-  #
-  INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
-
-  #
-  # FAT filesystem + GPT/MBR partitioning
-  #
-  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
-  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
-  INF FatBinPkg/EnhancedFatDxe/Fat.inf
-  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-
-  # Versatile Express FileSystem
-  INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf
-
-  #
-  # Multimedia Card Interface
-  #
-  INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
-  INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
-
-  #
-  # Platform  Driver
-  #
-  INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf
-  INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
-
-  #
-  # UEFI application (Shell Embedded Boot Loader)
-  #
-  INF ShellBinPkg/UefiShell/UefiShell.inf
-
-!ifdef EDK2_ENABLE_SMSC_91X
-!include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress-networking.fdf.inc
-  INF OpenPlatformPkg/Drivers/Net/Lan91xDxe/Lan91xDxe.inf
-!endif
-
-  #
-  # Bds
-  #
-  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-  INF ArmPlatformPkg/Bds/Bds.inf
-
-  # FV Filesystem
-  INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
-
-  #
-  # FDT installation
-  #
-  # The UEFI driver is at the end of the list of the driver to be dispatched
-  # after the device drivers (eg: Ethernet) to ensure we have support for them.
-  INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf
-
-  # Example to add a Device Tree to the Firmware Volume
-  #FILE FREEFORM = PCD(gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA15x4) {
-  #  SECTION RAW = ArmPlatformPkg/ArmVExpressPkg/Fdts/rtsm_ve-ca15x4.dtb
-  #}
-
-  # Legacy Linux Loader
-  INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf
-
-[FV.FVMAIN_COMPACT]
-FvAlignment        = 8
-ERASE_POLARITY     = 1
-MEMORY_MAPPED      = TRUE
-STICKY_WRITE       = TRUE
-LOCK_CAP           = TRUE
-LOCK_STATUS        = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP  = TRUE
-WRITE_STATUS       = TRUE
-WRITE_LOCK_CAP     = TRUE
-WRITE_LOCK_STATUS  = TRUE
-READ_DISABLED_CAP  = TRUE
-READ_ENABLED_CAP   = TRUE
-READ_STATUS        = TRUE
-READ_LOCK_CAP      = TRUE
-READ_LOCK_STATUS   = TRUE
-
-!if $(EDK2_SKIP_PEICORE) == 1
-  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
-!else
-  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
-  INF MdeModulePkg/Core/Pei/PeiMain.inf
-  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
-  INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
-  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
-  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
-  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
-  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
-  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
-!endif
-
-  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
-    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
-      SECTION FV_IMAGE = FVMAIN
-    }
-  }
-
-
-################################################################################
-#
-# Rules are use with the [FV] section's module INF type to define
-# how an FFS file is created for a given INF file. The following Rule are the default
-# rules for the different module type. User can add the customized rules to define the
-# content of the FFS file.
-#
-################################################################################
-
-
-############################################################################
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
-############################################################################
-#
-#[Rule.Common.DXE_DRIVER]
-#  FILE DRIVER = $(NAMED_GUID) {
-#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-#    COMPRESS PI_STD {
-#      GUIDED {
-#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
-#        UI       STRING="$(MODULE_NAME)" Optional
-#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-#      }
-#    }
-#  }
-#
-############################################################################
-
-[Rule.Common.SEC]
-  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
-    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
-  }
-
-[Rule.Common.PEI_CORE]
-  FILE PEI_CORE = $(NAMED_GUID) {
-    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI     STRING ="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.PEIM]
-  FILE PEIM = $(NAMED_GUID) {
-     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
-     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
-     UI       STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.PEIM.TIANOCOMPRESSED]
-  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
-    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
-    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
-      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
-      UI        STRING="$(MODULE_NAME)" Optional
-    }
-  }
-
-[Rule.Common.DXE_CORE]
-  FILE DXE_CORE = $(NAMED_GUID) {
-    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI       STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.UEFI_DRIVER]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI           STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.DXE_DRIVER]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI           STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.DXE_RUNTIME_DRIVER]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI           STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.UEFI_APPLICATION]
-  FILE APPLICATION = $(NAMED_GUID) {
-    UI     STRING ="$(MODULE_NAME)" Optional
-    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
-  }
-
-[Rule.Common.UEFI_DRIVER.BINARY]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX DXE_DEPEX Optional      |.depex
-    PE32      PE32                    |.efi
-    UI        STRING="$(MODULE_NAME)" Optional
-    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-  }
-
-[Rule.Common.UEFI_APPLICATION.BINARY]
-  FILE APPLICATION = $(NAMED_GUID) {
-    PE32      PE32                    |.efi
-    UI        STRING="$(MODULE_NAME)" Optional
-    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-  }
+#
+#  Copyright (c) 2012-2015, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.ARM_VEXPRESS_CTA15A7_EFI]
+BaseAddress   = 0xB0000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in remapped DRAM.
+Size          = 0x000E0000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize     = 0x00001000
+NumBlocks     = 0xE0
+
+0x00000000|0x000E0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = 73dcb643-3862-4904-9076-a94af1890243
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+  #INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
+  INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf
+  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  #
+  # Platform
+  #
+  INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+  #
+  # Filesystems
+  #
+!ifndef $(ARM_BIGLITTLE_TC2)
+  INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+!endif
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatBinPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  # Versatile Express FileSystem
+  INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf
+
+  #
+  # USB support
+  #
+  INF EmbeddedPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.inf
+
+  #
+  # Android Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+  INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBootDxe.inf
+
+  # ACPI Support
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+  #
+  # Networking stack
+  #
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+  INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
+
+  #
+  # UEFI application
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+  #
+  # TianoCore logo (splash screen)
+  #
+  FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
+   SECTION RAW = MdeModulePkg/Logo/Logo.bmp
+  }
+
+  # FV Filesystem
+  INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+
+  #
+  # FDT installation
+  #
+  # The UEFI driver is at the end of the list of the driver to be dispatched
+  # after the device drivers (eg: Ethernet) to ensure we have support for them.
+  INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf
+
+  # Example to add a Device Tree to the Firmware Volume
+  #FILE FREEFORM = PCD(gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA15x2A7x3) {
+  #  SECTION RAW = ArmPlatformPkg/ArmVExpressPkg/Fdts/vexpress-v2p-ca15_a7.dtb
+  #}
+
+[FV.FVMAIN_COMPACT]
+FvBaseAddress      = 0xB0000000
+FvForceRebase      = TRUE
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)" Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
index c566d4d..cf4b803 100644
--- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
+++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
@@ -39,13 +39,14 @@
 !include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress.dsc.inc
 
 [LibraryClasses.common]
-  ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
   ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf
   ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
 
   ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
   NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
-!ifndef ARM_FOUNDATION_FVP
+!ifdef EDK2_ENABLE_PL111
   LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
 !endif
 
@@ -54,9 +55,11 @@
   # Virtio Support
   VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
   VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+!endif
 
 [LibraryClasses.common.SEC]
-  ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
   ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf
   ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
 
@@ -79,24 +82,12 @@
   #  It could be set FALSE to save size.
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
 
-  # Force the UEFI GIC driver to use GICv2 legacy mode. To use
-  # GICv3 without GICv2 legacy in UEFI, the ARM Trusted Firmware needs
-  # to configure the Non-Secure interrupts in the GIC Redistributors
-  # which is not supported at the moment.
-  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE
-
 [PcdsFixedAtBuild.common]
   gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Fixed Virtual Platform"
   gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ARM-FVP"
 
-!ifndef ARM_FOUNDATION_FVP
-  # Up to 8 cores on Base models. This works fine if model happens to have less.
-  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
-  gArmPlatformTokenSpaceGuid.PcdClusterCount|2
-!else
-  # Up to 4 cores on Foundation models. This works fine if model happens to have less.
-  gArmPlatformTokenSpaceGuid.PcdCoreCount|4
-!endif
+  # Only one core enters UEFI, and PSCI is implemented in EL3 by ATF
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|1
 
   #
   # NV Storage PCDs. Use base of 0x0C000000 for NOR1
@@ -110,18 +101,11 @@
 
   gArmTokenSpaceGuid.PcdVFPEnabled|1
 
-  # FVP models can have 2 clusters with 4 cpus each
-  # Stacks for MPCores in Secure World
-  # Trusted SRAM (DRAM on Foundation model)
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x04000000
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x800
-
   # Stacks for MPCores in Normal World
   # Non-Trusted SRAM
   gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000
   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0
 
   # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
@@ -148,31 +132,27 @@
 
   ## PL011 - Serial Terminal
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
 
   ## PL031 RealTimeClock
   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
 
-!ifndef ARM_FOUNDATION_FVP
+!ifdef EDK2_ENABLE_PL111
   ## PL111 Versatile Express Motherboard controller
   gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000
+!endif
 
   ## PL180 MMC/SD card controller
   gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
   gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
-!endif
 
   #
   # ARM General Interrupt Controller
   #
-!ifdef ARM_FVP_LEGACY_GICV2_LOCATION
-  gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000
-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000
-!else
   gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000
   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x2f100000
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000
-!endif
 
   #
   # ARM OS Loader
@@ -182,8 +162,12 @@
   gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L"console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9"
 
   # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
-  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
-  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
+!ifdef EDK2_ENABLE_PL111
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(7D916D80-5BB1-458C-A48F-E25FDD51EF94);VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+!else
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(7D916D80-5BB1-458C-A48F-E25FDD51EF94)"
+!endif
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(7D916D80-5BB1-458C-A48F-E25FDD51EF94)"
 
   #
   # ARM Architectural Timer Frequency
@@ -191,6 +175,9 @@
   # Set tick frequency value to 100Mhz
   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000
 
+  # the entire FVP address space can be covered by 36 bit VAs
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36
+
 [PcdsDynamicDefault.common]
   #
   # The size of a dynamic PCD of the (VOID*) type can not be increased at run
@@ -208,27 +195,17 @@
 [Components.common]
 
   #
-  # SEC
-  #
-  ArmPlatformPkg/Sec/Sec.inf {
-    <LibraryClasses>
-      # Use the implementation which set the Secure bits
-      ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
-  }
-
-  #
   # PEI Phase modules
   #
 !ifdef EDK2_SKIP_PEICORE
   # UEFI is placed in RAM by bootloader
-  ArmPlatformPkg/PrePi/PeiMPCore.inf {
+  ArmPlatformPkg/PrePi/PeiUniCore.inf {
     <LibraryClasses>
-      ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
       ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
   }
 !else
   # UEFI lives in FLASH and copies itself to RAM
-  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
   MdeModulePkg/Core/Pei/PeiMain.inf
   MdeModulePkg/Universal/PCD/Pei/Pcd.inf  {
     <LibraryClasses>
@@ -270,7 +247,10 @@
   MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
 !endif
   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  }
   MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
   MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
   EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
@@ -290,16 +270,12 @@
   #
   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
   MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
-  OpenPlatformPkg/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
+  OpenPlatformPkg/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
 
   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
-!if $(SECURE_BOOT_ENABLE) == TRUE
-  ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashAuthenticatedDxe.inf
-!else
   ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
-!endif
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-!ifndef ARM_FOUNDATION_FVP
+!ifdef EDK2_ENABLE_PL111
   ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
 !endif
   ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
@@ -313,18 +289,19 @@
   #
   ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
 
-!ifndef ARM_FOUNDATION_FVP
   #
   # Multimedia Card Interface
   #
   EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
   ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
-!endif
 
   #
   # Platform Driver
   #
-  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf
+  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
   OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
 
   #
@@ -338,10 +315,12 @@
   # Bds
   #
   MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-!if $(USE_ARM_BDS) == TRUE
-  ArmPlatformPkg/Bds/Bds.inf
-!else
   MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
-!endif
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf
index 05cd173..2ace4d8 100644
--- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf
+++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf
@@ -24,35 +24,6 @@
 #
 ################################################################################
 
-[FD.FVP_AARCH64_EFI_SEC]
-BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in SecureROM.
-Size          = 0x04000000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the device (64MiB).
-ErasePolarity = 1
-
-# This one is tricky, it must be: BlockSize * NumBlocks = Size
-BlockSize     = 0x00001000
-NumBlocks     = 0x4000
-
-################################################################################
-#
-# Following are lists of FD Region layout which correspond to the locations of different
-# images within the flash device.
-#
-# Regions must be defined in ascending order and may not overlap.
-#
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
-# the pipe "|" character, followed by the size of the region, also in hex with the leading
-# "0x" characters. Like:
-# Offset|Size
-# PcdOffsetCName|PcdSizeCName
-# RegionType <FV, DATA, or FILE>
-#
-################################################################################
-
-0x00000000|0x00080000
-gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
-FV = FVMAIN_SEC
-
 [FD.FVP_AARCH64_EFI]
 !ifdef ARM_FVP_RUN_NORFLASH
 BaseAddress   = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in Flash0.
@@ -81,29 +52,6 @@ FV = FVMAIN_COMPACT
 #
 ################################################################################
 
-[FV.FVMAIN_SEC]
-FvBaseAddress      = 0x0  # Secure ROM
-FvForceRebase      = TRUE
-FvAlignment        = 16
-ERASE_POLARITY     = 1
-MEMORY_MAPPED      = TRUE
-STICKY_WRITE       = TRUE
-LOCK_CAP           = TRUE
-LOCK_STATUS        = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP  = TRUE
-WRITE_STATUS       = TRUE
-WRITE_LOCK_CAP     = TRUE
-WRITE_LOCK_STATUS  = TRUE
-READ_DISABLED_CAP  = TRUE
-READ_ENABLED_CAP   = TRUE
-READ_STATUS        = TRUE
-READ_LOCK_CAP      = TRUE
-READ_LOCK_STATUS   = TRUE
-
-  INF ArmPlatformPkg/Sec/Sec.inf
-
-
 [FV.FvMain]
 BlockSize          = 0x40
 NumBlocks          = 0         # This FV gets compressed so make it just big enough
@@ -125,10 +73,6 @@ READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 FvNameGuid         = 87940482-fc81-41c3-87e6-399cf85ac8a0
 
-  APRIORI DXE {
-    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
-  }
-
   INF MdeModulePkg/Core/Dxe/DxeMain.inf
   INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
 
@@ -155,7 +99,7 @@ FvNameGuid         = 87940482-fc81-41c3-87e6-399cf85ac8a0
   #
   INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
   INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-  INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
+  INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
 
   #
   # Multiple Console IO support
@@ -168,12 +112,8 @@ FvNameGuid         = 87940482-fc81-41c3-87e6-399cf85ac8a0
 
   INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-!if $(SECURE_BOOT_ENABLE) == TRUE
-  INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashAuthenticatedDxe.inf
-!else
   INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
-!endif
-!ifndef ARM_FOUNDATION_FVP
+!ifdef EDK2_ENABLE_PL111
   INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
 !endif
   INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
@@ -191,13 +131,11 @@ FvNameGuid         = 87940482-fc81-41c3-87e6-399cf85ac8a0
   INF FatBinPkg/EnhancedFatDxe/Fat.inf
   INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
 
-!ifndef ARM_FOUNDATION_FVP
   #
   # Multimedia Card Interface
   #
   INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
   INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
-!endif
 
   #
   # SMBIOS Support
@@ -218,18 +156,16 @@ FvNameGuid         = 87940482-fc81-41c3-87e6-399cf85ac8a0
   #
   # UEFI application (Shell Embedded Boot Loader)
   #
-  INF ShellBinPkg/UefiShell/UefiShell.inf
+  INF ShellPkg/Application/Shell/Shell.inf
 
   #
   # Bds
   #
   INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-!if $(USE_ARM_BDS) == TRUE
-  INF ArmPlatformPkg/Bds/Bds.inf
-!else
   INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
 
   #
   # TianoCore logo (splash screen)
@@ -237,10 +173,6 @@ FvNameGuid         = 87940482-fc81-41c3-87e6-399cf85ac8a0
   FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
    SECTION RAW = MdeModulePkg/Logo/Logo.bmp
   }
-!endif
-
-  # Legacy Linux Loader
-  INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf
 
   # FV Filesystem
   INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
@@ -296,9 +228,9 @@ READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 
 !if $(EDK2_SKIP_PEICORE) == 1
-  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
 !else
-  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
   INF MdeModulePkg/Core/Pei/PeiMain.inf
   INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
   INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
@@ -345,20 +277,20 @@ READ_LOCK_STATUS   = TRUE
 ############################################################################
 
 [Rule.Common.SEC]
-  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
-    TE  TE Align = 4K                  $(INF_OUTPUT)/$(MODULE_NAME).efi
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+    TE  TE Align = Auto                 $(INF_OUTPUT)/$(MODULE_NAME).efi
   }
 
 [Rule.Common.PEI_CORE]
-  FILE PEI_CORE = $(NAMED_GUID) {
-    TE     TE Align = 8                 $(INF_OUTPUT)/$(MODULE_NAME).efi
+  FILE PEI_CORE = $(NAMED_GUID) FIXED {
+    TE     TE Align = Auto              $(INF_OUTPUT)/$(MODULE_NAME).efi
     UI     STRING ="$(MODULE_NAME)" Optional
   }
 
 [Rule.Common.PEIM]
-  FILE PEIM = $(NAMED_GUID) {
+  FILE PEIM = $(NAMED_GUID) FIXED {
      PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
-     TE       TE Align = 8              $(INF_OUTPUT)/$(MODULE_NAME).efi
+     TE       TE Align = Auto           $(INF_OUTPUT)/$(MODULE_NAME).efi
      UI       STRING="$(MODULE_NAME)" Optional
   }
 
@@ -421,5 +353,6 @@ READ_LOCK_STATUS   = TRUE
 
 [Rule.Common.USER_DEFINED.ACPITABLE]
   FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI               |.acpi
     RAW ASL                |.aml
   }
diff --git a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc
index 86bad01..ddf617c 100644
--- a/Platforms/ARM/VExpress/ArmVExpress.dsc.inc
+++ b/Platforms/ARM/VExpress/ArmVExpress.dsc.inc
@@ -12,7 +12,6 @@
 #
 
 [Defines]
-  USE_ARM_BDS         = FALSE
   SECURE_BOOT_ENABLE  = FALSE
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
@@ -58,9 +57,7 @@
   #
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
 
-  # 1/123 faster than Stm or Vstm version
-  #BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-  BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
 
   # Networking Requirements
   NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
@@ -71,7 +68,7 @@
   # ARM Architectural Libraries
   CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
   DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
-  CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
   ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
   DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
   ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -85,8 +82,10 @@
   ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
   NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
   EfiResetSystemLib|ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf
+!ifdef EDK2_ENABLE_PL111
   # ARM PL111 Lcd Driver
   LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+!endif
   # ARM PL031 RTC Driver
   RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
   # ARM PL354 SMC Driver
@@ -119,7 +118,8 @@
   SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
 
   # BDS Libraries
-  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 
   AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
   FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
@@ -149,12 +149,8 @@
 !endif
   VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
 
-!if $(USE_ARM_BDS) == FALSE
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
-  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
-  PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
   CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
-!endif
 
 [LibraryClasses.common.SEC]
   ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
@@ -190,6 +186,7 @@
   ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
 
   PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
 
 [LibraryClasses.common.PEIM]
   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
@@ -208,6 +205,7 @@
 
 [LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
   MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
 
 [LibraryClasses.common.DXE_CORE]
   HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
@@ -232,6 +230,11 @@
   MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
 
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
 [LibraryClasses.common.UEFI_DRIVER]
   ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
   UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
@@ -342,19 +345,21 @@
   #  DEBUG_WARN      0x00000002  // Warnings
   #  DEBUG_LOAD      0x00000004  // Load events
   #  DEBUG_FS        0x00000008  // EFI File system
-  #  DEBUG_POOL      0x00000010  // Alloc & Free's
-  #  DEBUG_PAGE      0x00000020  // Alloc & Free's
-  #  DEBUG_INFO      0x00000040  // Verbose
-  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+  #  DEBUG_POOL      0x00000010  // Alloc & Free (pool)
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free (page)
+  #  DEBUG_INFO      0x00000040  // Informational debug messages
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE/SMM Dispatchers
   #  DEBUG_VARIABLE  0x00000100  // Variable
   #  DEBUG_BM        0x00000400  // Boot Manager
   #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
-  #  DEBUG_NET       0x00004000  // SNI Driver
+  #  DEBUG_NET       0x00004000  // SNP Driver
   #  DEBUG_UNDI      0x00010000  // UNDI Driver
-  #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // LoadFile
   #  DEBUG_EVENT     0x00080000  // Event messages
   #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
   #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
+  #  DEBUG_VERBOSE   0x00400000  // Detailed debug messages that may
+  #                              // significantly impact boot performance
   #  DEBUG_ERROR     0x80000000  // Error
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
 
@@ -421,10 +426,11 @@
   # Shell.
   gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
 
-!if $(USE_ARM_BDS) == FALSE
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
-!endif
+
+  # use the TTY terminal type
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
 
 !ifdef EDK2_ENABLE_SMSC_91X
   # Ethernet (SMSC 91C111)
@@ -438,8 +444,14 @@
   gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
 !endif
 
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
 [Components.common]
-  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
 
   # Versatile Express FileSystem
   ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf
@@ -469,7 +481,10 @@
   #
   # Android Fastboot
   #
-  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
   EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
   ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBootDxe.inf
 
@@ -479,7 +494,26 @@
   #
   # FDT installation
   #
-  EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf
+  EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
 
-  # Legacy Linux Loader
-  ArmPkg/Application/LinuxLoader/LinuxLoader.inf
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+  }
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf b/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
new file mode 100644
index 0000000..fd586bd
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
@@ -0,0 +1,28 @@
+## @file
+#  AtaAtapiPassThru driver to provide native IDE/AHCI mode support.
+#
+#  This driver installs AtaPassThru and ExtScsiPassThru protocol in each ide/sata controller
+#  to access to all attached Ata/Atapi devices.
+#
+#  Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AtaAtapiPassThruDxe
+  FILE_GUID                      = 5E523CB4-D397-4986-87BD-A6DD8B22F455
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeAtaAtapiPassThru
+
+[Binaries]
+  PE32|AtaAtapiPassThruDxe.efi|*
+  DXE_DEPEX|AtaAtapiPassThruDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.depex b/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.depex
new file mode 100644
index 0000000..a104090
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.depex
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.efi b/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.efi
new file mode 100644
index 0000000..e94c36d
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.efi
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SFCDriver.depex b/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SFCDriver.depex
new file mode 100644
index 0000000..e5c4b16
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SFCDriver.depex
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SFCDriver.efi b/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SFCDriver.efi
new file mode 100644
index 0000000..6969a61
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SFCDriver.efi
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SfcDxeDriver.inf b/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SfcDxeDriver.inf
new file mode 100644
index 0000000..e10275a
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SfcDxeDriver.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SFCDriver
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = SFCInitialize
+
+
+
+[Binaries.common]
+  PE32|SFCDriver.efi|*
+  DXE_DEPEX|SFCDriver.depex|*
+
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac4PhyInitOnly.efi b/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac4PhyInitOnly.efi
new file mode 100644
index 0000000..a7d3acf
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac4PhyInitOnly.efi
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac4PhyInitOnly.inf b/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac4PhyInitOnly.inf
new file mode 100644
index 0000000..7e21274
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac4PhyInitOnly.inf
@@ -0,0 +1,29 @@
+## @file
+# Component name for module SnpNt32Dxe
+#
+# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SnpPV600DxeMac4PhyInitOnly
+  FILE_GUID                      = 3247F153-3612-4803-BD4E-4104D7EF944A
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac4PhyInitOnly.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac5.efi b/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac5.efi
new file mode 100644
index 0000000..00c3711
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac5.efi
diff --git a/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac5.inf b/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac5.inf
new file mode 100644
index 0000000..42d234f
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac5.inf
@@ -0,0 +1,28 @@
+## @file
+# Component name for module SnpNt32Dxe
+#
+# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 3246F154-3612-4803-BD4E-4104D7EF944A
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac5.efi|*
diff --git a/Platforms/Hisilicon/Binary/D02/Ebl/Ebl.efi b/Platforms/Hisilicon/Binary/D02/Ebl/Ebl.efi
new file mode 100644
index 0000000..7458733
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Ebl/Ebl.efi
diff --git a/Platforms/Hisilicon/Binary/D02/Ebl/Ebl.inf b/Platforms/Hisilicon/Binary/D02/Ebl/Ebl.inf
new file mode 100644
index 0000000..960a426
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Ebl/Ebl.inf
@@ -0,0 +1,32 @@
+#/** @file
+# EBL Applicaiton
+#
+# This is a shell application that will display Hello World.
+# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Ebl
+  FILE_GUID                      = 3CEF354A-3B7A-4519-AD70-72A134698311
+  MODULE_TYPE                    = UEFI_APPLICATION
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = EdkBootLoaderEntry
+
+[Binaries.common]
+  PE32|Ebl.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.inf b/Platforms/Hisilicon/Binary/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.inf
new file mode 100644
index 0000000..82acb9e
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.inf
@@ -0,0 +1,44 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemAddressMapPv660D02
+  FILE_GUID                      = DDDA42BC-772E-4ff5-8C9F-524F7F6601A2
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemAddressMapLib
+
+[Sources.common]
+
+[Sources.AARCH64.GCC]
+
+[Binaries.AARCH64]
+  LIB|OemAddressMapPv660D02.lib|*
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+
+[BuildOptions]
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdNORFlashBase
+
diff --git a/Platforms/Hisilicon/Binary/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.lib b/Platforms/Hisilicon/Binary/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.lib
new file mode 100644
index 0000000..3b4d3fc
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.lib
diff --git a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi
new file mode 100644
index 0000000..8d2a9f3
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi
diff --git a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeiLib.c b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeiLib.c
new file mode 100644
index 0000000..6eb85bb
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeiLib.c
@@ -0,0 +1,201 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/MemoryInitPei/
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+VOID
+BuildMemoryTypeInformationHob (
+  VOID
+  );
+
+VOID
+InitMmu (
+  VOID
+  )
+{
+  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable;
+  VOID                          *TranslationTableBase;
+  UINTN                         TranslationTableSize;
+  RETURN_STATUS                 Status;
+
+  // Get Virtual Memory Map from the Platform Library
+  ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+  //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
+  //      DRAM (even at the top of DRAM as it is the first permanent memory allocation)
+  Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU\n"));
+  }
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+  FileHandle  - Handle of the file being invoked.
+  PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+  Status -  EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+  IN EFI_PHYSICAL_ADDRESS               UefiMemoryBase,
+  IN UINT64                             UefiMemorySize
+  )
+{
+  EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+  UINT64                      ResourceLength;
+  EFI_PEI_HOB_POINTERS        NextHob;
+  EFI_PHYSICAL_ADDRESS        FdTop;
+  EFI_PHYSICAL_ADDRESS        SystemMemoryTop;
+  EFI_PHYSICAL_ADDRESS        ResourceTop;
+  BOOLEAN                     Found;
+
+  // Ensure PcdSystemMemorySize has been set
+  ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);
+
+  ResourceAttributes = (
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED
+  );
+  BuildResourceDescriptorHob (
+        EFI_RESOURCE_MEMORY_MAPPED_IO,
+        ResourceAttributes,
+        PcdGet64(PcdSerialRegisterBase),
+        PcdGet64(PcdSerialRegisterSpaceSize)
+    );
+  ResourceAttributes = (
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED
+  );
+  BuildResourceDescriptorHob (
+        EFI_RESOURCE_MEMORY_MAPPED_IO,
+        ResourceAttributes,
+        PcdGet64(PcdSysControlBaseAddress),
+        0x10000
+  );
+  //
+  // Now, the permanent memory has been installed, we can call AllocatePages()
+  //
+  ResourceAttributes = (
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED
+  );
+
+  // Reserved the memory space occupied by the firmware volume
+  BuildResourceDescriptorHob (
+      EFI_RESOURCE_SYSTEM_MEMORY,
+      ResourceAttributes,
+      PcdGet64 (PcdSystemMemoryBase),
+      PcdGet64 (PcdSystemMemorySize)
+  );
+
+  SystemMemoryTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemoryBase) + (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemorySize);
+  FdTop = (EFI_PHYSICAL_ADDRESS)PcdGet64(PcdFdBaseAddress) + (EFI_PHYSICAL_ADDRESS)PcdGet32(PcdFdSize);
+
+  // EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE
+  // core to overwrite this area we must mark the region with the attribute non-present
+  if ((PcdGet64 (PcdFdBaseAddress) >= PcdGet64 (PcdSystemMemoryBase)) && (FdTop <= SystemMemoryTop)) {
+    Found = FALSE;
+
+    // Search for System Memory Hob that contains the firmware
+    NextHob.Raw = GetHobList ();
+    while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
+      if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
+          (PcdGet64(PcdFdBaseAddress) >= NextHob.ResourceDescriptor->PhysicalStart) &&
+          (FdTop <= NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))
+      {
+        ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
+        ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
+        ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
+
+        if (PcdGet64(PcdFdBaseAddress) == NextHob.ResourceDescriptor->PhysicalStart) {
+          if (SystemMemoryTop == FdTop) {
+            NextHob.ResourceDescriptor->ResourceAttribute = ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT;
+          } else {
+            // Create the System Memory HOB for the firmware with the non-present attribute
+            BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
+                                        ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,
+                                        PcdGet64(PcdFdBaseAddress),
+                                        PcdGet32(PcdFdSize));
+
+            // Top of the FD is system memory available for UEFI
+            NextHob.ResourceDescriptor->PhysicalStart += PcdGet32(PcdFdSize);
+            NextHob.ResourceDescriptor->ResourceLength -= PcdGet32(PcdFdSize);
+          }
+        } else {
+          // Create the System Memory HOB for the firmware with the non-present attribute
+          BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
+                                      ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,
+                                      PcdGet64(PcdFdBaseAddress),
+                                      PcdGet32(PcdFdSize));
+
+          // Update the HOB
+          NextHob.ResourceDescriptor->ResourceLength = PcdGet64(PcdFdBaseAddress) - NextHob.ResourceDescriptor->PhysicalStart;
+
+          // If there is some memory available on the top of the FD then create a HOB
+          if (FdTop < NextHob.ResourceDescriptor->PhysicalStart + ResourceLength) {
+            // Create the System Memory HOB for the remaining region (top of the FD)
+            BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
+                                        ResourceAttributes,
+                                        FdTop,
+                                        ResourceTop - FdTop);
+          }
+        }
+        Found = TRUE;
+        break;
+      }
+      NextHob.Raw = GET_NEXT_HOB (NextHob);
+    }
+
+    ASSERT(Found);
+  }
+
+  // Build Memory Allocation Hob
+  InitMmu ();
+
+  if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+    // Optional feature that helps prevent EFI memory map fragmentation.
+    BuildMemoryTypeInformationHob ();
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeiLib.inf b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeiLib.inf
new file mode 100644
index 0000000..d8ef479
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeiLib.inf
@@ -0,0 +1,75 @@
+#/** @file
+#
+#  Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/MemoryInitPei/
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmMemoryInitPeiLib
+  FILE_GUID                      = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
+  MODULE_TYPE                    = SEC
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PlatformPeiLib
+
+[Sources]
+  MemoryInitPeiLib.c
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  HobLib
+  ArmLib
+  ArmPlatformLib
+
+[Guids]
+  gEfiMemoryTypeInformationGuid
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gHisiTokenSpaceGuid.PcdSerialRegisterSpaceSize
+  gHisiTokenSpaceGuid.PcdSysControlBaseAddress
+
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+  gArmTokenSpaceGuid.PcdFdSize
+
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+
+[Depex]
+  TRUE
diff --git a/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeim.inf b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeim.inf
new file mode 100644
index 0000000..c221de9
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeim.inf
@@ -0,0 +1,33 @@
+#/** @file
+#
+#  Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/MemoryInitPei/
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MemoryInit
+  FILE_GUID                      = c61ef796-b50d-4f98-9f78-4f6f79d800d5
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeMemory
+
+[Sources]
+
+[Binaries.AARCH64]
+  TE|MemoryInit.efi|*
+
+[Depex]
+  TRUE
diff --git a/Platforms/Hisilicon/Binary/D02/Sec/FVMAIN_SEC.Fv b/Platforms/Hisilicon/Binary/D02/Sec/FVMAIN_SEC.Fv
new file mode 100644
index 0000000..bac8767
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/Sec/FVMAIN_SEC.Fv
diff --git a/Platforms/Hisilicon/Binary/D02/bl1.bin b/Platforms/Hisilicon/Binary/D02/bl1.bin
new file mode 100644
index 0000000..d64bfd8
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/bl1.bin
diff --git a/Platforms/Hisilicon/Binary/D02/fip.bin b/Platforms/Hisilicon/Binary/D02/fip.bin
new file mode 100644
index 0000000..7cdd9db
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D02/fip.bin
diff --git a/Platforms/Hisilicon/Binary/D03/CustomData.Fv b/Platforms/Hisilicon/Binary/D03/CustomData.Fv
new file mode 100644
index 0000000..466b1a8
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/CustomData.Fv
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi
new file mode 100644
index 0000000..0b17045
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
new file mode 100644
index 0000000..fb29319
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
@@ -0,0 +1,26 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = GetInfoFromBmc
+  FILE_GUID                      = 43B59C81-9C5F-4021-B0F2-947DB839B781
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = GetBmcInfoDriverEntry
+
+[Binaries]
+  PE32|GetInfoFromBmc.efi|*
+  DXE_DEPEX|GetInfoFromBmc.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi
new file mode 100644
index 0000000..c3347c1
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
new file mode 100644
index 0000000..91ac33c
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
@@ -0,0 +1,32 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IpmiInterfacePei
+  FILE_GUID                      = 269702AF-8004-4570-A08E-00762AE65D15
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = IpmiInterfacePeiEntry
+
+[Sources]
+
+[Binaries.AARCH64]
+  TE|IpmiInterfacePei.efi|*
+
+[Depex]
+  TRUE
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.depex b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi
new file mode 100644
index 0000000..f6a2333
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
new file mode 100644
index 0000000..49ef812
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
@@ -0,0 +1,28 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IpmiInterfaceDxe
+  FILE_GUID                      = EF5483F8-68AD-4D71-9A23-674D2E9C013E
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.common]
+  PE32|IpmiInterfaceDxe.efi|*
+  DXE_DEPEX|IpmiInterfaceDxe.depex|*
+
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi
new file mode 100644
index 0000000..2c064c1
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
new file mode 100644
index 0000000..02618fc
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
@@ -0,0 +1,27 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IpmiMiscOp
+  FILE_GUID                      = EC68451C-6D10-4ba2-9862-D27D4D6090DB
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = IpmiMiscOpEntry
+
+[Binaries]
+  PE32|IpmiMiscOp.efi|*
+  DXE_DEPEX|IpmiMiscOpDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi
new file mode 100644
index 0000000..048ac5c
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
new file mode 100644
index 0000000..bda12e2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
@@ -0,0 +1,27 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = IpmiWatchdogDxe
+  FILE_GUID                      = 7C7ACA9F-DB25-43FB-A479-1B6E42F38792
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeWatchdogDxeEntry
+
+[Binaries]
+  PE32|IpmiWatchdogDxe.efi|*
+  DXE_DEPEX|IpmiWatchdogDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi
new file mode 100644
index 0000000..d88b511
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
new file mode 100644
index 0000000..adb115b
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 92D37768-571C-48d9-BEF5-9744AE2FDAF4
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac0.efi|*
+
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi
new file mode 100644
index 0000000..40eceb1
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
new file mode 100644
index 0000000..4363d1e
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
@@ -0,0 +1,28 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 3247F150-3612-4803-BD4E-4104D7EF944A
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac1.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi
new file mode 100644
index 0000000..9fff194
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
new file mode 100644
index 0000000..7fc67c1
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
@@ -0,0 +1,27 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 3247F153-3612-4803-BD4E-4104D7EF944A
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac4.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi
new file mode 100644
index 0000000..709bcb6
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
new file mode 100644
index 0000000..ab4120d
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
@@ -0,0 +1,27 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 3246F154-3612-4803-BD4E-4104D7EF944A
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac5.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi
new file mode 100644
index 0000000..9abddfc
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf
new file mode 100644
index 0000000..5053ece
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf
@@ -0,0 +1,26 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = NativeOhci
+  FILE_GUID                      = 043D0B5E-DAC1-463a-85BA-2CEDC33A8C4F
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+   PE32|NativeOhci.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi
new file mode 100644
index 0000000..251c786
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
new file mode 100644
index 0000000..52b219d
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
@@ -0,0 +1,25 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ReportPciePlugDidVidToBmc
+  FILE_GUID                      = 9BC4A5D1-5A46-4A6C-AF11-4875268179D3
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+  PE32|ReportPciePlugDidVidToBmc.efi|*
+  DXE_DEPEX|ReportPciePlugDidVidToBmc.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.depex b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.depex
new file mode 100644
index 0000000..e5c4b16
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.depex
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi
new file mode 100644
index 0000000..e1e04eb
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf
new file mode 100644
index 0000000..e10275a
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SFCDriver
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = SFCInitialize
+
+
+
+[Binaries.common]
+  PE32|SFCDriver.efi|*
+  DXE_DEPEX|SFCDriver.depex|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi
new file mode 100644
index 0000000..19cd038
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf
new file mode 100644
index 0000000..0cb90f7
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf
@@ -0,0 +1,28 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SasDriverDxe
+  FILE_GUID                      = 49ea041e-6752-42ca-b0b1-7344fe234567
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = SasDriverInitialize
+
+[Binaries]
+   PE32|SasDriverDxe.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi
new file mode 100644
index 0000000..a8241c1
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf
new file mode 100644
index 0000000..a261833
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf
@@ -0,0 +1,32 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION          = 0x00010005
+  BASE_NAME            = SmiGraphicsOutput
+  FILE_GUID            = BFB7B510-B09B-11DB-96E3-005056C00008
+  MODULE_TYPE          = UEFI_DRIVER
+  VERSION_STRING       = 1.0
+
+  PCI_VENDOR_ID        = 0x126F
+  PCI_DEVICE_ID        = 0x0750
+  PCI_CLASS_CODE       = 0x030000
+  PCI_REVISION         = 0xA1
+  COMPRESS             = TRUE
+
+[Binaries]
+  PE32|SmiGraphicsOutput.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi
new file mode 100644
index 0000000..53edeba
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
new file mode 100644
index 0000000..f6b966d
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
@@ -0,0 +1,26 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = TransSmbiosInfo
+  FILE_GUID                      = 13668C32-1977-436a-800C-F8644D11CB76
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = TransferSmbiosInfoToBMC
+
+[Binaries]
+  PE32|TransSmbiosInfo.efi|*
+  DXE_DEPEX|TransSmbiosInfo.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi
new file mode 100644
index 0000000..914370a
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi
diff --git a/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf
new file mode 100644
index 0000000..5bc73c2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf
@@ -0,0 +1,32 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Ebl
+  FILE_GUID                      = 3CEF354A-3B7A-4519-AD70-72A134698311
+  MODULE_TYPE                    = UEFI_APPLICATION
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = EdkBootLoaderEntry
+
+[Binaries.common]
+  PE32|Ebl.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib
new file mode 100644
index 0000000..fe23d93
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib
diff --git a/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf
new file mode 100644
index 0000000..9de7cdf
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf
@@ -0,0 +1,44 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemAddressMap2P
+  FILE_GUID                      = 32BC48E3-5428-4556-A383-25A23EA816A7
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemAddressMapLib
+
+[Sources.common]
+
+[Binaries.AARCH64]
+  LIB|OemAddressMap2P.lib|*
+
+[Sources.AARCH64.GCC]
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  CpldIoLib
+[BuildOptions]
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdNORFlashBase
+
diff --git a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi
new file mode 100644
index 0000000..f335e5c
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi
diff --git a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf
new file mode 100644
index 0000000..c221de9
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf
@@ -0,0 +1,33 @@
+#/** @file
+#
+#  Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/MemoryInitPei/
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MemoryInit
+  FILE_GUID                      = c61ef796-b50d-4f98-9f78-4f6f79d800d5
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeMemory
+
+[Sources]
+
+[Binaries.AARCH64]
+  TE|MemoryInit.efi|*
+
+[Depex]
+  TRUE
diff --git a/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv
new file mode 100644
index 0000000..1830a6a
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv
diff --git a/Platforms/Hisilicon/Binary/D03/bl1.bin b/Platforms/Hisilicon/Binary/D03/bl1.bin
new file mode 100644
index 0000000..7bf0698
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/bl1.bin
diff --git a/Platforms/Hisilicon/Binary/D03/fip.bin b/Platforms/Hisilicon/Binary/D03/fip.bin
new file mode 100644
index 0000000..913d40d
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D03/fip.bin
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi
new file mode 100644
index 0000000..3eb81a6
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
new file mode 100644
index 0000000..20e2f05
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
@@ -0,0 +1,26 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = GetInfoFromBmc
+  FILE_GUID                      = 43B59C81-9C5F-4021-B0F2-947DB839B781
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = GetBmcInfoDriverEntry
+
+[Binaries]
+  PE32|GetInfoFromBmc.efi|*
+  DXE_DEPEX|GetInfoFromBmc.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi
new file mode 100644
index 0000000..eba2141
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
new file mode 100644
index 0000000..a614b68
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
@@ -0,0 +1,28 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = IpmiInterfaceDxe
+  FILE_GUID                      = EF5483F8-68AD-4D71-9A23-674D2E9C013E
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.common]
+  PE32|IpmiInterfaceDxe.efi|*
+  DXE_DEPEX|IpmiInterfaceDxe.depex|*
+
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi
new file mode 100644
index 0000000..c4b5cd3
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
new file mode 100644
index 0000000..e55d3f7
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
@@ -0,0 +1,32 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = IpmiInterfacePei
+  FILE_GUID                      = 269702AF-8004-4570-A08E-00762AE65D15
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = IpmiInterfacePeiEntry
+
+[Sources]
+
+[Binaries.AARCH64]
+  TE|IpmiInterfacePei.efi|*
+
+[Depex]
+  TRUE
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi
new file mode 100644
index 0000000..1ff9bdc
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
new file mode 100644
index 0000000..8075f40
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
@@ -0,0 +1,27 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = IpmiMiscOp
+  FILE_GUID                      = EC68451C-6D10-4ba2-9862-D27D4D6090DB
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = IpmiMiscOpEntry
+
+[Binaries]
+  PE32|IpmiMiscOp.efi|*
+  DXE_DEPEX|IpmiMiscOpDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi
new file mode 100644
index 0000000..5152d4b
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
new file mode 100644
index 0000000..c173587
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
@@ -0,0 +1,27 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = IpmiWatchdogDxe
+  FILE_GUID                      = 7C7ACA9F-DB25-43FB-A479-1B6E42F38792
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeWatchdogDxeEntry
+
+[Binaries]
+  PE32|IpmiWatchdogDxe.efi|*
+  DXE_DEPEX|IpmiWatchdogDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi
new file mode 100644
index 0000000..65e9a06
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
new file mode 100644
index 0000000..6c69e5b
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 92D37768-571C-48d9-BEF5-9744AE2FDAF4
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac0.efi|*
+
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi
new file mode 100644
index 0000000..edc32a8
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
new file mode 100644
index 0000000..b2c801d
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
@@ -0,0 +1,28 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 3247F150-3612-4803-BD4E-4104D7EF944A
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac1.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi
new file mode 100644
index 0000000..e2d25cb
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
new file mode 100644
index 0000000..c7794be
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
@@ -0,0 +1,27 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 3247F153-3612-4803-BD4E-4104D7EF944A
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac4.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi
new file mode 100644
index 0000000..282c2fb
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
new file mode 100644
index 0000000..b06a3db
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
@@ -0,0 +1,27 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SnpPV600Dxe
+  FILE_GUID                      = 3246F154-3612-4803-BD4E-4104D7EF944A
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = InitializeSnpPV600Driver
+  UNLOAD_IMAGE                   = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac5.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/NativeOhci.efi b/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/NativeOhci.efi
new file mode 100644
index 0000000..01bd9b4
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/NativeOhci.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
new file mode 100644
index 0000000..80d9c49
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
@@ -0,0 +1,26 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = NativeOhci
+  FILE_GUID                      = 043D0B5E-DAC1-463a-85BA-2CEDC33A8C4F
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+   PE32|NativeOhci.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi
new file mode 100644
index 0000000..cc72539
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
new file mode 100644
index 0000000..ab2be5e
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
@@ -0,0 +1,25 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = ReportPciePlugDidVidToBmc
+  FILE_GUID                      = 9BC4A5D1-5A46-4A6C-AF11-4875268179D3
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries]
+  PE32|ReportPciePlugDidVidToBmc.efi|*
+  DXE_DEPEX|ReportPciePlugDidVidToBmc.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.depex b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi
new file mode 100644
index 0000000..89bac2d
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
new file mode 100644
index 0000000..909462f
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SFCDriver
+  FILE_GUID                      = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = SFCInitialize
+
+
+
+[Binaries.common]
+  PE32|SFCDriver.efi|*
+  DXE_DEPEX|SFCDriver.depex|*
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi
new file mode 100644
index 0000000..8d9ecd2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
new file mode 100644
index 0000000..539d612
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
@@ -0,0 +1,28 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SasDriverDxe
+  FILE_GUID                      = 49ea041e-6752-42ca-b0b1-7344fe234567
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = SasDriverInitialize
+
+[Binaries]
+   PE32|SasDriverDxe.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi
new file mode 100644
index 0000000..3bbfcd0
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
new file mode 100644
index 0000000..0590919
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
@@ -0,0 +1,32 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION          = 0x00010019
+  BASE_NAME            = SmiGraphicsOutput
+  FILE_GUID            = BFB7B510-B09B-11DB-96E3-005056C00008
+  MODULE_TYPE          = UEFI_DRIVER
+  VERSION_STRING       = 1.0
+
+  PCI_VENDOR_ID        = 0x126F
+  PCI_DEVICE_ID        = 0x0750
+  PCI_CLASS_CODE       = 0x030000
+  PCI_REVISION         = 0xA1
+  COMPRESS             = TRUE
+
+[Binaries]
+  PE32|SmiGraphicsOutput.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex
new file mode 100644
index 0000000..2a47cc2
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex
@@ -0,0 +1 @@
+
+\ No newline at end of file
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi
new file mode 100644
index 0000000..3cb9a4e
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
new file mode 100644
index 0000000..6b34037
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
@@ -0,0 +1,26 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = TransSmbiosInfo
+  FILE_GUID                      = 13668C32-1977-436a-800C-F8644D11CB76
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = TransferSmbiosInfoToBMC
+
+[Binaries]
+  PE32|TransSmbiosInfo.efi|*
+  DXE_DEPEX|TransSmbiosInfo.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi b/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi
new file mode 100644
index 0000000..f053519
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi
diff --git a/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf b/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
new file mode 100644
index 0000000..9419fcb
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
@@ -0,0 +1,32 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = Ebl
+  FILE_GUID                      = 3CEF354A-3B7A-4519-AD70-72A134698311
+  MODULE_TYPE                    = UEFI_APPLICATION
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = EdkBootLoaderEntry
+
+[Binaries.common]
+  PE32|Ebl.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
new file mode 100644
index 0000000..cb4cda8
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
@@ -0,0 +1,51 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = FdtUpdateLib
+  FILE_GUID                      = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = FdtUpdateLib
+
+[Sources.common]
+
+[Binaries.AARCH64]
+  LIB|FdtUpdateLib.lib|*
+
+[Sources.AARCH64.GCC]
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  FdtLib
+  OemMiscLib
+  PlatformSysCtrlLib
+
+[Protocols]
+  gEfiGenericMemTestProtocolGuid
+
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdIsMPBoot
+  gHisiTokenSpaceGuid.PcdNumaEnable
+  gHisiTokenSpaceGuid.Pcdsoctype
+
diff --git a/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.lib b/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.lib
new file mode 100644
index 0000000..8045d7a
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.lib
diff --git a/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf b/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
new file mode 100644
index 0000000..6743eef
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
@@ -0,0 +1,44 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = OemAddressMapD05
+  FILE_GUID                      = 32BC48E3-5428-4556-A383-25A23EA816A7
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemAddressMapLib
+
+[Sources.common]
+
+[Binaries.AARCH64]
+  LIB|OemAddressMapD05.lib|*
+
+[Sources.AARCH64.GCC]
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  CpldIoLib
+[BuildOptions]
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdNORFlashBase
+
diff --git a/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.lib b/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.lib
new file mode 100644
index 0000000..e37546e
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.lib
diff --git a/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInit.efi
new file mode 100644
index 0000000..fd1208e
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInit.efi
diff --git a/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf b/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
new file mode 100644
index 0000000..da28c5a
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
@@ -0,0 +1,33 @@
+#/** @file
+#
+#  Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/MemoryInitPei/
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = MemoryInit
+  FILE_GUID                      = c61ef796-b50d-4f98-9f78-4f6f79d800d5
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeMemory
+
+[Sources]
+
+[Binaries.AARCH64]
+  TE|MemoryInit.efi|*
+
+[Depex]
+  TRUE
diff --git a/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv b/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
new file mode 100644
index 0000000..16500b7
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
diff --git a/Platforms/Hisilicon/Binary/D05/bl1.bin b/Platforms/Hisilicon/Binary/D05/bl1.bin
new file mode 100644
index 0000000..f207cd9
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/bl1.bin
diff --git a/Platforms/Hisilicon/Binary/D05/fip.bin b/Platforms/Hisilicon/Binary/D05/fip.bin
new file mode 100644
index 0000000..0952662
--- /dev/null
+++ b/Platforms/Hisilicon/Binary/D05/fip.bin
diff --git a/Platforms/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c b/Platforms/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c
new file mode 100644
index 0000000..1d011fb
--- /dev/null
+++ b/Platforms/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c
@@ -0,0 +1,94 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/ArmLib.h>
+
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+
+#include <Library/OemMiscLib.h>
+
+#define TIMER_SUBCTRL_BASE                              PcdGet64(PcdPeriSubctrlAddress)
+#define ALG_BASE                                        (0xA0000000)
+#define PERI_SUB_CTRL_BASE                              (0x80000000)
+#define SC_TM_CLKEN0_REG                                (0x2050)
+#define SYS_APB_IF_BASE                                 (0x10000)
+#define TSENSOR_REG                                     (0x5000)
+#define SC_ITS_M3_INT_MUX_SEL_REG                       (0x21F0)
+#define SC_HLLC_RESET_DREQ_REG                          (0xA8C)
+#define SC_ITS_M3_INT_MUX_SEL_VALUE                     (0xF)
+#define SC_HLLC_RESET_DREQ_VALUE                        (0x1f)
+#define TSENSOR_CONFIG_VALUE                            (0x1)
+
+VOID PlatformTimerStart (VOID)
+{
+    // Timer0 clock enable
+    MmioWrite32 (TIMER_SUBCTRL_BASE + SC_TM_CLKEN0_REG, 0x3);
+}
+
+EFI_STATUS
+EFIAPI
+EarlyConfigEntry (
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+    DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
+    SmmuConfigForOS();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"ITS CONFIG........."));
+    ITSCONFIG();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"AP CONFIG........."));
+    MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
+    (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
+    ArmDataSynchronizationBarrier ();
+    ArmInstructionSynchronizationBarrier ();
+
+    CoreSelectBoot();
+
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"MN CONFIG........."));
+    MN_CONFIG ();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"RTC CONFIG........."));
+
+    MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_VALUE);
+
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"Tsensor CONFIG........."));
+
+    MmioWrite32(PERI_SUB_CTRL_BASE + SYS_APB_IF_BASE + TSENSOR_REG, TSENSOR_CONFIG_VALUE);
+    MmioWrite32(ALG_BASE + SC_HLLC_RESET_DREQ_REG, SC_HLLC_RESET_DREQ_VALUE);
+
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"Timer CONFIG........."));
+    PlatformTimerStart ();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    return EFI_SUCCESS;
+}
diff --git a/Platforms/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf b/Platforms/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
new file mode 100644
index 0000000..ffc42df
--- /dev/null
+++ b/Platforms/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
@@ -0,0 +1,53 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = EarlyConfigPeim
+  FILE_GUID                      = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = EarlyConfigEntry
+
+[Sources.common]
+  EarlyConfigPeim.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PeimEntryPoint
+  PcdLib
+  DebugLib
+  IoLib
+  CacheMaintenanceLib
+  ArmLib
+
+  PlatformSysCtrlLib
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdMailBoxAddress
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
+
+[Depex]
+## As we will clean mailbox in this module, need to wait memory init complete
+  gEfiPeiMemoryDiscoveredPpiGuid
+
+[BuildOptions]
+
diff --git a/Platforms/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c b/Platforms/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c
new file mode 100644
index 0000000..429306b
--- /dev/null
+++ b/Platforms/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c
@@ -0,0 +1,341 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <libfdt.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/FdtUpdateLib.h>
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <Library/MemoryAllocationLib.h>
+
+MAC_ADDRESS gMacAddress[1];
+
+CHAR8  *EthName[8]=
+{
+ "ethernet@0","ethernet@1",
+ "ethernet@2","ethernet@3",
+ "ethernet@4","ethernet@5",
+ "ethernet@6","ethernet@7"
+};
+
+CHAR8  *MacName[4]=
+{
+ "ethernet-mac@c7040000",
+ "ethernet-mac@c7044000",
+ "ethernet-mac@c7048000",
+ "ethernet-mac@c704c000"
+};
+
+STATIC
+BOOLEAN
+IsMemMapRegion (
+  IN EFI_MEMORY_TYPE MemoryType
+  )
+{
+  switch(MemoryType)
+    {
+        case EfiRuntimeServicesCode:
+        case EfiRuntimeServicesData:
+        case EfiConventionalMemory:
+        case EfiACPIReclaimMemory:
+        case EfiACPIMemoryNVS:
+        case EfiLoaderCode:
+        case EfiLoaderData:
+        case EfiBootServicesCode:
+        case EfiBootServicesData:
+        case EfiPalCode:
+                return TRUE;
+        default:
+                return FALSE;
+  }
+}
+
+EFI_STATUS
+GetMacAddress (UINT32 Port)
+{
+    EFI_MAC_ADDRESS Mac;
+    EFI_STATUS Status;
+    HISI_BOARD_NIC_PROTOCOL *OemNic = NULL;
+
+    Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    Status = OemNic->GetMac(&Mac, Port);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] GetMac failed %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    gMacAddress[0].data0=Mac.Addr[0];
+    gMacAddress[0].data1=Mac.Addr[1];
+    gMacAddress[0].data2=Mac.Addr[2];
+    gMacAddress[0].data3=Mac.Addr[3];
+    gMacAddress[0].data4=Mac.Addr[4];
+    gMacAddress[0].data5=Mac.Addr[5];
+    DEBUG((EFI_D_ERROR, "Port%d:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+        Port,gMacAddress[0].data0,gMacAddress[0].data1,gMacAddress[0].data2,
+        gMacAddress[0].data3,gMacAddress[0].data4,gMacAddress[0].data5));
+
+    return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+DelPhyhandleUpdateMacAddress(IN VOID* Fdt)
+{
+    UINT8               port;
+    INTN                ethernetnode;
+    INTN                node;
+    INTN                Error;
+    struct              fdt_property *m_prop;
+    int                 m_oldlen;
+    EFI_STATUS          Status = EFI_SUCCESS;
+
+    node = fdt_subnode_offset(Fdt, 0, "soc");
+    if (node < 0)
+    {
+        DEBUG ((EFI_D_ERROR, "can not find soc root node\n"));
+        return EFI_INVALID_PARAMETER;
+    }
+    else
+    {
+        for( port=0; port<8; port++ )
+        {
+            (VOID) GetMacAddress(port);
+            ethernetnode=fdt_subnode_offset(Fdt, node,EthName[port]);
+            if (ethernetnode < 0)
+            {
+                DEBUG ((EFI_D_ERROR, "can not find ethernet@ %d node\n",port));
+            }
+            m_prop = fdt_get_property_w(Fdt, ethernetnode, "local-mac-address", &m_oldlen);
+            if(m_prop)
+            {
+                Error = fdt_delprop(Fdt, ethernetnode, "local-mac-address");
+                if (Error)
+                {
+                    DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop() Local-mac-address: %a\n", fdt_strerror (Error)));
+                    Status = EFI_INVALID_PARAMETER;
+                }
+                Error = fdt_setprop(Fdt, ethernetnode, "local-mac-address",gMacAddress,sizeof(MAC_ADDRESS));
+                if (Error)
+                {
+                    DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop():local-mac-address %a\n", fdt_strerror (Error)));
+                    Status = EFI_INVALID_PARAMETER;
+                }
+            }
+        }
+    }
+    return Status;
+}
+
+EFI_STATUS UpdateMemoryNode(VOID* Fdt)
+{
+    INTN                Error = 0;
+    EFI_STATUS          Status = EFI_SUCCESS;
+    UINT32              Index = 0;
+    UINT32              MemIndex;
+    INTN                node;
+    struct              fdt_property *m_prop;
+    int                 m_oldlen;
+    EFI_MEMORY_DESCRIPTOR *MemoryMap;
+    EFI_MEMORY_DESCRIPTOR *MemoryMapPtr;
+    EFI_MEMORY_DESCRIPTOR *MemoryMapPtrCurrent;
+    UINTN                 MemoryMapSize;
+    UINTN                 Pages0 = 0;
+    UINTN                 Pages1 = 0;
+    UINTN                 MapKey;
+    UINTN                 DescriptorSize;
+    UINT32                DescriptorVersion;
+    PHY_MEM_REGION        *mRegion;
+    UINTN                 MemoryMapLastEndAddress ;
+    UINTN                 MemoryMapcontinuousStartAddress ;
+    UINTN                 MemoryMapCurrentStartAddress;
+    BOOLEAN               FindMemoryRegionFlag = FALSE;
+    node = fdt_subnode_offset(Fdt, 0, "memory");
+    if (node < 0)
+    {
+        // Create the memory node
+        node = fdt_add_subnode(Fdt, 0, "memory");
+        if(node < 0)
+        {
+          DEBUG((EFI_D_INFO, "[%a]:[%dL] fdt add subnode error\n", __FUNCTION__, __LINE__));
+        }
+    }
+    //find the memory node property
+    m_prop = fdt_get_property_w(Fdt, node, "memory", &m_oldlen);
+    if(m_prop)
+        Error=fdt_delprop(Fdt, node, "reg");
+    if (Error)
+    {
+        DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop(): %a\n", fdt_strerror (Error)));
+        Status = EFI_INVALID_PARAMETER;
+        return Status;
+    }
+
+    MemoryMap = NULL;
+    MemoryMapSize = 0;
+    MemIndex = 0;
+
+    Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+    if (Status == EFI_BUFFER_TOO_SMALL)
+    {
+        // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive
+        // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size.
+        //DEBUG ((EFI_D_ERROR, "MemoryMapsize: 0x%lx\n",MemoryMapSize));
+        Pages0 = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
+        MemoryMap = AllocatePages (Pages0);
+        if (MemoryMap == NULL)
+        {
+            Status = EFI_OUT_OF_RESOURCES;
+            return Status;
+        }
+        Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+    }
+
+    if(MemoryMap == NULL)
+    {
+        Status = EFI_OUT_OF_RESOURCES;
+        //goto EXIT;
+        return Status;
+    }
+
+    mRegion = NULL;
+    Pages1 = EFI_SIZE_TO_PAGES (sizeof(PHY_MEM_REGION) *( MemoryMapSize / DescriptorSize));
+    mRegion = (PHY_MEM_REGION*)AllocatePages(Pages1);
+    if (mRegion == NULL)
+    {
+      Status = EFI_OUT_OF_RESOURCES;
+      return Status;
+    }
+
+    if (!EFI_ERROR(Status))
+    {
+        MemoryMapPtr = MemoryMap;
+        MemoryMapPtrCurrent = MemoryMapPtr;
+        MemoryMapLastEndAddress = 0;
+        MemoryMapcontinuousStartAddress = 0;
+        MemoryMapCurrentStartAddress = 0;
+        for ( Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++)
+        {
+            MemoryMapPtrCurrent = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + Index*DescriptorSize);
+            MemoryMapCurrentStartAddress = (UINTN)MemoryMapPtrCurrent->PhysicalStart;
+
+            if (!IsMemMapRegion ((EFI_MEMORY_TYPE)MemoryMapPtrCurrent->Type))
+            {
+                continue;
+            }
+            else
+            {
+                FindMemoryRegionFlag = TRUE;
+                if(MemoryMapCurrentStartAddress != MemoryMapLastEndAddress)
+                {
+                    mRegion[MemIndex].BaseHigh= cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32);
+                    mRegion[MemIndex].BaseLow=cpu_to_fdt32(MemoryMapcontinuousStartAddress);
+                    mRegion[MemIndex].LengthHigh= cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32);
+                    mRegion[MemIndex].LengthLow=cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress);
+                    MemIndex+=1;
+                    MemoryMapcontinuousStartAddress=MemoryMapCurrentStartAddress;
+                }
+            }
+            MemoryMapLastEndAddress = (UINTN)(MemoryMapPtrCurrent->PhysicalStart + MemoryMapPtrCurrent->NumberOfPages * EFI_PAGE_SIZE);
+        }
+        if (FindMemoryRegionFlag)
+        {
+            mRegion[MemIndex].BaseHigh = cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32);
+            mRegion[MemIndex].BaseLow = cpu_to_fdt32(MemoryMapcontinuousStartAddress);
+            mRegion[MemIndex].LengthHigh = cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32);
+            mRegion[MemIndex].LengthLow = cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress);
+        }
+    }
+    Error = fdt_setprop(Fdt, node, "reg",mRegion,sizeof(PHY_MEM_REGION) *(MemIndex+1));
+    FreePages (mRegion, Pages1);
+    FreePages (MemoryMap, Pages0);
+    if (Error)
+    {
+        DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop(): %a\n", fdt_strerror (Error)));
+        Status = EFI_INVALID_PARAMETER;
+        return Status;
+    }
+  return Status;
+}
+
+/*
+ * Entry point for fdtupdate lib.
+ */
+
+EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr)
+{
+    INTN                Error;
+    VOID*               Fdt;
+    UINT32              Size;
+    UINTN               NewFdtBlobSize;
+    UINTN               NewFdtBlobBase;
+    EFI_STATUS          Status = EFI_SUCCESS;
+
+    Error = fdt_check_header ((VOID*)(UINTN)(FdtFileAddr));
+    if (Error != 0)
+    {
+        DEBUG ((EFI_D_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error)));
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Size = (UINTN)fdt_totalsize ((VOID*)(UINTN)(FdtFileAddr));
+    NewFdtBlobSize = Size + ADD_FILE_LENGTH;
+    Fdt = (VOID*)(UINTN)FdtFileAddr;
+
+    Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase);
+    if (EFI_ERROR (Status))
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+
+    Error = fdt_open_into(Fdt,(VOID*)(UINTN)(NewFdtBlobBase), (NewFdtBlobSize));
+    if (Error) {
+        DEBUG ((EFI_D_ERROR, "ERROR:fdt_open_into(): %a\n", fdt_strerror (Error)));
+        Status = EFI_INVALID_PARAMETER;
+        goto EXIT;
+    }
+
+    Fdt = (VOID*)(UINTN)NewFdtBlobBase;
+
+    Status = DelPhyhandleUpdateMacAddress(Fdt);
+    if (EFI_ERROR (Status))
+    {
+        DEBUG ((EFI_D_ERROR, "DelPhyhandleUpdateMacAddress fail:\n"));
+        Status = EFI_SUCCESS;
+    }
+
+    Status = UpdateMemoryNode(Fdt);
+    if (EFI_ERROR (Status))
+    {
+        goto EXIT;
+    }
+
+    gBS->CopyMem(((VOID*)(UINTN)(FdtFileAddr)),((VOID*)(UINTN)(NewFdtBlobBase)),NewFdtBlobSize);
+
+EXIT:
+    gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize));
+
+    return Status;
+}
diff --git a/Platforms/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf b/Platforms/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
new file mode 100644
index 0000000..c952414
--- /dev/null
+++ b/Platforms/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
@@ -0,0 +1,43 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = FdtUpdateLib
+  FILE_GUID                      = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = FdtUpdateLib
+
+
+[Sources.common]
+  FdtUpdateLib.c
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  FdtLib
+  OemAddressMapLib
+
+[Protocols]
+  gHisiBoardNicProtocolGuid
+
+[Pcd]
+
diff --git a/Platforms/Hisilicon/D02/Include/Library/CpldD02.h b/Platforms/Hisilicon/D02/Include/Library/CpldD02.h
new file mode 100644
index 0000000..b899dbb
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Include/Library/CpldD02.h
@@ -0,0 +1,34 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CPLDD02_H__
+#define __CPLDD02_H__
+#define CPLD_LOGIC_VERSION                (0x52)
+#define PRODUCT_VERSION                   (0x53)
+#define CPLD_LOGIC_COMPLIER_YEAR          (0x54)
+#define CPLD_LOGIC_COMPLIER_MONTH         (0x55)
+#define CPLD_LOGIC_COMPLIER_DAY           (0x56)
+#define CPLD_LOGIC_COMPLIER_HOUR          (0x57)
+#define CPLD_LOGIC_COMPLIER_MINUTE        (0x58)
+#define BOARD_ID                          (0x59)
+#define BOM_VERSION                       (0x5A)
+#define CPLD_BIOS_CURRENT_CHANNEL_REG_D02 (0x5B)
+
+#define CPU0_PCIE1_RESET_REG                (0x12)
+#define CPU0_PCIE2_RESET_REG                (0x13)
+#define CPU1_PCIE1_RESET_REG                (0x14)
+#define CPU1_PCIE2_RESET_REG                (0x15)
+
+#endif /* __CPLDD02_H__ */
diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
new file mode 100644
index 0000000..49942e5
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c
@@ -0,0 +1,105 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <PlatformArch.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Library/CpldIoLib.h>
+#include <Library/CpldD02.h>
+#include <Library/TimerLib.h>
+#include <Library/I2CLib.h>
+#include <Library/HiiLib.h>
+
+I2C_DEVICE gDS3231RtcDevice = {
+    .Socket = 0,
+    .Port = 7,
+    .DeviceType = DEVICE_TYPE_SPD,
+    .SlaveDeviceAddress = 0x68
+};
+
+// Set Tx output polarity. Not inverting data is default. For Phosphor660 D02 Board
+//if((1 == ulMacroId) && ((7 == ulDsNum)||(0 == ulDsNum)))
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
+{
+    {1, 7},
+    {1, 0},
+    {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+// Set Rx data polarity. Not inverting data is default. For Phosphor660 D02 Board
+//if((1 == ulMacroId) && ((0 == ulDsNum) || (1 == ulDsNum)))
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
+{
+    {1, 0},
+    {1, 1},
+    {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_PARAM gSerdesParam = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = EmHilink3GeX4,
+  .Hilink4Mode = EmHilink4XgeX4,
+  .Hilink5Mode = EmHilink5Sas1X4,
+};
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId)
+{
+  if (ParamA == NULL) {
+    DEBUG((DEBUG_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA));
+  return EFI_SUCCESS;
+}
+
+
+VOID OemPcieResetAndOffReset(void)
+  {
+    WriteCpldReg(CPU0_PCIE1_RESET_REG,0x0);
+    WriteCpldReg(CPU0_PCIE2_RESET_REG,0x0);
+    WriteCpldReg(CPU1_PCIE1_RESET_REG,0x0);
+    WriteCpldReg(CPU1_PCIE2_RESET_REG,0x0);
+    MicroSecondDelay(100000);
+    WriteCpldReg(CPU0_PCIE1_RESET_REG,0x55);
+    WriteCpldReg(CPU0_PCIE2_RESET_REG,0x55);
+    WriteCpldReg(CPU1_PCIE1_RESET_REG,0x55);
+    WriteCpldReg(CPU1_PCIE2_RESET_REG,0x55);
+    return;
+  }
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+  {{STRING_TOKEN(STR_D02_DIMM_000), STRING_TOKEN(STR_D02_DIMM_001), 0xFFFF},
+   {STRING_TOKEN(STR_D02_DIMM_010), STRING_TOKEN(STR_D02_DIMM_011), 0xFFFF}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+  )
+{
+    return HiiAddPackages (
+                            &gEfiCallerIdGuid,
+                            NULL,
+                            OemMiscLibD02Strings,
+                            NULL,
+                            NULL
+                            );
+}
diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni
new file mode 100644
index 0000000..dcd79eb
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni
diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c
new file mode 100644
index 0000000..df7d158
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c
@@ -0,0 +1,77 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CpldIoLib.h>
+#include <Library/OemMiscLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/SerialPortLib.h>
+
+// Right now we only support 1P
+BOOLEAN OemIsSocketPresent (UINTN Socket)
+{
+  if (0 == Socket)
+  {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+UINTN OemGetSocketNumber (VOID)
+{
+    return 1;
+}
+
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel)
+{
+    return 2;
+}
+
+UINTN OemGetDdrChannel (VOID)
+{
+    return 2;
+}
+
+VOID CoreSelectBoot(VOID)
+{
+    if (!PcdGet64 (PcdTrustedFirmwareEnable))
+    {
+        StartupAp ();
+    }
+
+    return;
+}
+
+BOOLEAN OemIsMpBoot()
+{
+    return FALSE;
+}
+
+VOID OemBiosSwitch(UINT32 Master)
+{
+    return;
+}
+
+UINT32 OemIsWarmBoot(VOID)
+{
+    return 0;
+}
diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf
new file mode 100644
index 0000000..1954fe2
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf
@@ -0,0 +1,45 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemMiscLibD02
+  FILE_GUID                      = 1DCE7EC8-3DB6-47cf-A2B5-717FD9AB2570
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemMiscLib
+
+[Sources.common]
+  BoardFeatureD02.c
+  OemMiscLibD02.c
+  BoardFeatureD02Strings.uni
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+  OpenPlatformPkg/Platforms/Hisilicon/D02/Pv660D02.dec
+
+[LibraryClasses]
+  SerialPortLib
+  CpldIoLib
+
+[BuildOptions]
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c
new file mode 100644
index 0000000..797163a
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c
@@ -0,0 +1,147 @@
+/** @file
+
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ {// HostBridge 0
+  /* Port 0 */
+  {
+      PCI_HB0RB0_ECAM_BASE,
+      0,  //BusBase
+      63, //BusLimit
+      (PCI_HB0RB0_ECAM_BASE + SIZE_64MB),  //MemBase
+      (PCI_HB0RB0_ECAM_BASE + PCI_HB0RB0_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB0RB0_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+  /* Port 1 */
+  {
+      PCI_HB0RB1_ECAM_BASE,
+      64,  //BusBase
+      127, //BusLimit
+      PCI_HB0RB1_PCIREGION_BASE,
+      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1,
+      PCI_HB0RB1_IO_BASE, //IoBase
+      PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1,  //IoLimit
+      PCI_HB0RB1_CPUMEMREGIONBASE,
+      PCI_HB0RB2_CPUIOREGIONBASE,
+      (PCI_HB0RB1_PCI_BASE),  //RbPciBar
+      PCI_HB0RB1_PCIREGION_BASE,
+      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1
+  },
+  /* Port 2 */
+  {
+      PCI_HB0RB2_ECAM_BASE,
+      128,  //BusBase
+      191, //BusLimit
+      PCI_HB0RB2_PCIREGION_BASE ,
+      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1,
+      PCI_HB0RB2_IO_BASE, //IoBase
+      PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1,  //IoLimit
+      PCI_HB0RB2_CPUMEMREGIONBASE,
+      PCI_HB0RB2_CPUIOREGIONBASE,
+      (PCI_HB0RB2_PCI_BASE),  //RbPciBar
+      PCI_HB0RB2_PCIREGION_BASE ,
+      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB0RB3_ECAM_BASE,
+      192,  //BusBase
+      255, //BusLimit
+      (PCI_HB0RB3_ECAM_BASE),  //MemBase
+      (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB0RB3_PCI_BASE),  //RbPciBar
+      0,
+      0
+  }
+ },
+{// HostBridge 1
+  /* Port 0 */
+  {
+      PCI_HB1RB0_ECAM_BASE,
+      0,  //BusBase
+      0x1, //BusLimit
+      (PCI_HB1RB0_ECAM_BASE),  //MemBase
+      (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB0_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+  /* Port 1 */
+  {
+       PCI_HB1RB1_ECAM_BASE,
+      0x2,  //BusBase
+      0x3, //BusLimit
+      (PCI_HB1RB1_ECAM_BASE),  //MemBase
+      (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB1_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+  /* Port 2 */
+  {
+      PCI_HB1RB2_ECAM_BASE,
+      0x4,  //BusBase
+      0x5, //BusLimit
+      (PCI_HB1RB2_ECAM_BASE),  //MemBase
+      (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB2_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB1RB3_ECAM_BASE,
+      0x6,  //BusBase
+      0x7, //BusLimit
+      (PCI_HB1RB3_ECAM_BASE),  //MemBase
+      (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB3_PCI_BASE),  //RbPciBar
+      0,
+      0
+  }
+ }
+};
+
diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
new file mode 100644
index 0000000..c9ce45f
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
@@ -0,0 +1,182 @@
+## @file
+#
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformPciLib
+  FILE_GUID                      = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  PlatformPciLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PciHb0Rb0Base
+  gHisiTokenSpaceGuid.PciHb0Rb1Base
+  gHisiTokenSpaceGuid.PciHb0Rb2Base
+  gHisiTokenSpaceGuid.PciHb0Rb3Base
+  gHisiTokenSpaceGuid.PciHb0Rb4Base
+  gHisiTokenSpaceGuid.PciHb0Rb5Base
+  gHisiTokenSpaceGuid.PciHb0Rb6Base
+  gHisiTokenSpaceGuid.PciHb0Rb7Base
+  gHisiTokenSpaceGuid.PciHb1Rb0Base
+  gHisiTokenSpaceGuid.PciHb1Rb1Base
+  gHisiTokenSpaceGuid.PciHb1Rb2Base
+  gHisiTokenSpaceGuid.PciHb1Rb3Base
+  gHisiTokenSpaceGuid.PciHb1Rb4Base
+  gHisiTokenSpaceGuid.PciHb1Rb5Base
+  gHisiTokenSpaceGuid.PciHb1Rb6Base
+  gHisiTokenSpaceGuid.PciHb1Rb7Base
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
diff --git a/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h b/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h
new file mode 100644
index 0000000..5f07116
--- /dev/null
+++ b/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h
@@ -0,0 +1,31 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __OEM_NIC_CONFIG_H__
+#define __OEM_NIC_CONFIG_H__
+
+#define I2C_SLAVEADDR_EEPROM     (0x52)
+
+#define I2C_OFFSET_EEPROM_ETH0   (0xc00)
+#define I2C_OFFSET_EEPROM_ETH1   (I2C_OFFSET_EEPROM_ETH0 + 6)
+#define I2C_OFFSET_EEPROM_ETH2   (I2C_OFFSET_EEPROM_ETH1 + 6)
+#define I2C_OFFSET_EEPROM_ETH3   (I2C_OFFSET_EEPROM_ETH2 + 6)
+#define I2C_OFFSET_EEPROM_ETH4   (I2C_OFFSET_EEPROM_ETH3 + 6)
+#define I2C_OFFSET_EEPROM_ETH5   (I2C_OFFSET_EEPROM_ETH4 + 6)
+#define I2C_OFFSET_EEPROM_ETH6   (I2C_OFFSET_EEPROM_ETH5 + 6)
+#define I2C_OFFSET_EEPROM_ETH7   (I2C_OFFSET_EEPROM_ETH6 + 6)
+
+
+#endif
diff --git a/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c b/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c
new file mode 100644
index 0000000..d327fa4
--- /dev/null
+++ b/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c
@@ -0,0 +1,173 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <Library/I2CLib.h>
+#include <OemNicConfig.h>
+
+#define EEPROM_I2C_PORT 7
+
+EFI_STATUS
+EFIAPI OemGetMac (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+EFI_STATUS
+EFIAPI OemSetMac (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+HISI_BOARD_NIC_PROTOCOL mOemNicProtocol = {
+  .GetMac = OemGetMac,
+  .SetMac = OemSetMac,
+};
+
+
+EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr)
+{
+    I2C_DEVICE stI2cDev = {0};
+    EFI_STATUS Status;
+    UINT16     I2cOffset;
+
+    Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * 6);
+
+    stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+    stI2cDev.Port = EEPROM_I2C_PORT;
+    stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+    stI2cDev.Socket = 0;
+    Status = I2CRead(&stI2cDev, I2cOffset, 6, pucAddr);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr)
+{
+    I2C_DEVICE stI2cDev = {0};
+    EFI_STATUS Status;
+    UINT16     I2cOffset;
+
+    Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * 6);
+
+    stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+    stI2cDev.Port = EEPROM_I2C_PORT;
+    stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+    stI2cDev.Socket = 0;
+    Status = I2CWrite(&stI2cDev, I2cOffset, 6, pucAddr);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemGetMac (
+  IN OUT EFI_MAC_ADDRESS *Mac,
+  IN UINTN Port
+  )
+{
+  EFI_STATUS Status;
+
+  if (NULL == Mac)
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //TODO: discard port number, only support one port
+  // Only 6 bytes are used
+  Status = OemGetMacE2prom(Port, Mac->Addr);
+  if ((EFI_ERROR(Status)))
+  {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] Get mac failed!\n", __FUNCTION__, __LINE__));
+      return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemSetMac (
+  IN EFI_MAC_ADDRESS *Mac,
+  IN UINTN Port
+  )
+{
+  EFI_STATUS Status;
+
+  if (NULL == Mac)
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = OemSetMacE2prom(Port, Mac->Addr);
+  if ((EFI_ERROR(Status)))
+  {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] Set mac failed!\n", __FUNCTION__, __LINE__));
+      return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+OemNicConfigEntry (
+  IN EFI_HANDLE           ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+{
+  EFI_STATUS Status;
+
+  Status = gBS->InstallProtocolInterface(
+    &ImageHandle,
+    &gHisiBoardNicProtocolGuid,
+    EFI_NATIVE_INTERFACE,
+    &mOemNicProtocol
+    );
+
+  if(EFI_ERROR(Status))
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status));
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf b/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
new file mode 100644
index 0000000..8787cef
--- /dev/null
+++ b/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemNicConfig
+  FILE_GUID                      = 3A23A929-1F38-4d04-8A01-38AD993EB2CE
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = OemNicConfigEntry
+
+[Sources.common]
+  OemNicConfigD02.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[Protocols]
+  gHisiBoardNicProtocolGuid       ##Produce
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  DebugLib
+  IoLib
+  TimerLib
+  I2CLib
+
+[FixedPcd]
+
+[Depex]
+  TRUE
+
+[BuildOptions]
+
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dec b/Platforms/Hisilicon/D02/Pv660D02.dec
new file mode 100644
index 0000000..5c34c2e
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Pv660D02.dec
@@ -0,0 +1,44 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#
+# PV660 D02 Package
+#
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = Pv660D02Pkg
+  PACKAGE_GUID                   = 54392E0D-972B-459D-8CBE-DB381E7D1B98
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  Include
+
+[Ppis]
+
+[Protocols]
+
+[Guids]
+
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild]
+
+[PcdsFeatureFlag]
+
+
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc
new file mode 100644
index 0000000..2f5fbe5
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Pv660D02.dsc
@@ -0,0 +1,468 @@
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = Pv660D02
+  PLATFORM_GUID                  = E1AB8AC3-3EF1-4c6f-8D9F-ABE3EC67188E
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Hisilicon/D02/$(PLATFORM_NAME).fdf
+  DEFINE INCLUDE_TFTP_COMMAND=1
+
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
+
+  ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+  NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+  LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+  I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+  IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
+
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+!ifdef $(FDT_ENABLE)
+  #FDTUpdateLib
+  FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
+
+  CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+
+  SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf
+
+  EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
+  RealTimeClockLib|OpenPlatformPkg/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
+  OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf
+  OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.inf
+  PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when
+## input signal is de-asserted, except for virtual timer interrupt IRQ #27.
+## So we choose to use virtual timer instead of physical one as a workaround.
+## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc.
+[LibraryClasses.AARCH64]
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf
+
+[LibraryClasses.common.SEC]
+  ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
+
+[BuildOptions]
+  GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Pv660/Include
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D02"
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+
+  # Stacks for MPCores in Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
+
+  # Stacks for MPCores in Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
+
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
+
+  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
+
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+  #
+  # ARM PrimeCell
+  #
+
+
+  ## SP805 Watchdog - Motherboard Watchdog
+  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x801e0000
+
+  ## Serial Terminal
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x80300000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+
+  gHisiTokenSpaceGuid.PcdUartClkInHz|200000000
+
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|10000000
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D02 UEFI 16.08 RC1"
+
+  gHisiTokenSpaceGuid.PcdSystemProductName|L"D02"
+  gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
+  gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D02"
+  gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
+
+  gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
+
+  #
+  # ARM PL390 General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x8D000000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x8D100000
+
+  ## DTB address at spi flash
+  gHisiTokenSpaceGuid.FdtFileAddress|0xA4B00000
+
+  gHisiTokenSpaceGuid.PcdNORFlashBase|0x90000000
+  gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
+
+  #
+  # ARM OS Loader
+  #
+  # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SATA"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"EFI\GRUB2\grubaa64.efi"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
+
+  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+  #
+  # ARM Architectual Timer Frequency
+  #
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+
+  gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x80010000
+  gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
+  gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x98000000
+  gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
+  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
+
+  gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
+
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x80000000
+
+  gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x80000000
+
+  ## 1 SCCL + 1 SICL
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x0
+  gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80020000
+  gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x80000000
+  gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  ## SP804 DualTimer
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|304
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x80060000
+  ## TODO: need to confirm the base for Performance and Metronome base for PV660
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x80060000
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x80060000
+
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x6 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x400000000000 # 4T
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0x30000000000
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0x22000000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0x24000000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0x26000000000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PciHb0Rb0Base|0xb0070000
+  gHisiTokenSpaceGuid.PciHb0Rb1Base|0xb0080000
+  gHisiTokenSpaceGuid.PciHb0Rb2Base|0xb0090000
+  gHisiTokenSpaceGuid.PciHb0Rb3Base|0xb00a0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xb0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0x7feffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xc0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x3feffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0x22008000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0x2400c000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0x2200fff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0x2400fff0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeim.inf
+  ArmPkg/Drivers/CpuPei/CpuPei.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+  OpenPlatformPkg/Platforms/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+
+  OpenPlatformPkg/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SfcDxeDriver.inf
+
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  }
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+  #
+  #ACPI
+  #
+  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf
+
+  #Pci Express
+  OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+     <LibraryClasses>
+       NULL|OpenPlatformPkg/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
+  }
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
+  #network
+  #
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac4PhyInitOnly.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac5.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Ebl/Ebl.inf
+  MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # USB Support
+  #
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf {
+    <LibraryClasses>
+      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  }
+!endif #$(FDT_ENABLE)
+
+  #
+  # Memory test
+  #
+  MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
+
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+!ifdef $(INCLUDE_DP)
+      NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+!endif #$(INCLUDE_DP)
+!ifdef $(INCLUDE_TFTP_COMMAND)
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/Hisilicon/D02/Pv660D02.fdf b/Platforms/Hisilicon/D02/Pv660D02.fdf
new file mode 100644
index 0000000..406b501
--- /dev/null
+++ b/Platforms/Hisilicon/D02/Pv660D02.fdf
@@ -0,0 +1,324 @@
+#
+#  Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[DEFINES]
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.PV660D02]
+BaseAddress   = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+
+Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00010000
+NumBlocks     = 0x30
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Sec/FVMAIN_SEC.Fv
+
+0x00040000|0x00240000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+## Place for Trusted Firmware
+0x00280000|0x00020000
+gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/bl1.bin
+0x002a0000|0x00020000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/fip.bin
+
+0x002e0000|0x0000e000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x20000
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
+  0xB8, 0xdF, 0x00, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002ee000|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
+  0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002f0000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Drivers/SFC/SfcDxeDriver.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
+
+  # PCI Express
+  INF OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  ## Sometimes we need to switch to emulated variable store for debug reason
+  #INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+  # This is simpler than generic serial console and may be used for debug
+  #INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatBinPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf
+
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+  #
+  #ACPI
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  #Network
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac4PhyInitOnly.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Drivers/SnpPV600Dxe_PLAT/SnpPV600DxeMac5.inf
+
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf
+
+  #
+  #Sata
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+  #
+  # USB Support
+  #
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/Ebl/Ebl.inf
+
+  #
+  # Build Shell from latest source code instead of prebuilt binary
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
+
diff --git a/Platforms/Hisilicon/D03/D03.dec b/Platforms/Hisilicon/D03/D03.dec
new file mode 100644
index 0000000..8b08a32
--- /dev/null
+++ b/Platforms/Hisilicon/D03/D03.dec
@@ -0,0 +1,44 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#
+# D03 Package
+#
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = D03Pkg
+  PACKAGE_GUID                   = D42C5D53-63FA-4FBA-9FD4-E8EA684FD3BE
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  Include
+
+[Ppis]
+
+[Protocols]
+
+[Guids]
+
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild]
+
+[PcdsFeatureFlag]
+
+
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc
new file mode 100644
index 0000000..4c90326
--- /dev/null
+++ b/Platforms/Hisilicon/D03/D03.dsc
@@ -0,0 +1,546 @@
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = D03
+  PLATFORM_GUID                  = e5003abd-8809-6194-ac3d-a6a99ff52478
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
+  DEFINE INCLUDE_TFTP_COMMAND=1
+
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
+
+  ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+  NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+  LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+
+
+  I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+  IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
+
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+
+
+!ifdef $(FDT_ENABLE)
+  #FDTUpdateLib
+  FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
+
+  CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+
+  SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.inf
+
+  EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
+  RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
+
+  OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
+  OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf
+  PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
+  SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf
+
+## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when
+## input signal is de-asserted, except for virtual timer interrupt IRQ #27.
+## So we choose to use virtual timer instead of physical one as a workaround.
+## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc.
+[LibraryClasses.AARCH64]
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf
+
+[LibraryClasses.common.SEC]
+  ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
+  SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf
+
+[BuildOptions]
+  GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+  gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+  gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03"
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+
+  # Stacks for MPCores in Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x81000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
+
+  # Stacks for MPCores in Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x8100FF00
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x81000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
+
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+
+
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
+
+
+  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
+
+
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+  #
+  # ARM PrimeCell
+  #
+
+
+  gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
+
+
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x7 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3
+
+  ## SP805 Watchdog - Motherboard Watchdog
+  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
+
+  ## Serial Terminal
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2F8
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+
+  gHisiTokenSpaceGuid.PcdUartClkInHz|1846100
+
+  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|10000000
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.12 Release"
+
+  gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
+
+  gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
+
+  gHisiTokenSpaceGuid.PcdSystemProductName|L"D03"
+  gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
+  gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D03"
+  gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
+
+  gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1612"
+
+  #
+  # ARM PL390 General Interrupt Controller
+  #
+
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
+
+  #
+  # ARM OS Loader
+  #
+  # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SATA"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"EFI\GRUB2\grubaa64.efi"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
+
+  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+  #
+  # ARM Architectual Timer Frequency
+  #
+  # Set it to 0 so that the code will read frequence from register and be
+  # adapted to 66M and 50M boards
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
+
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
+  gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
+
+  gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
+
+  gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
+  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
+
+
+  gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
+
+
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
+
+
+  gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
+
+  gHisiTokenSpaceGuid.FdtFileAddress|0xA47C0000
+
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
+
+  gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
+
+  gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
+
+  gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x2000000000
+
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
+  gHisiTokenSpaceGuid.PcdNumaEnable|0
+
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
+
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xB0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x8000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xB0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xAC000000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x4000000
+
+  gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
+  gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
+  gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
+  gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xb2000000
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0x5feffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xb8000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0x5feffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xaa000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x5feffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xB2000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xB8000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xAA000000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xb7ff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xbdff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xAfff0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+  ## SP804 DualTimer
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0xb0
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x40060000
+  ## TODO: need to confirm the base for Performance and Metronome base for PV660
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000
+
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+  #
+  # SEC
+  #
+
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
+
+  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf
+  ArmPkg/Drivers/CpuPei/CpuPei.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf
+
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  }
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+    <LibraryClasses>
+      CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+  #
+  #ACPI
+  #
+  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # Usb Support
+  #
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
+
+  #
+  #network
+  #
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
+
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+
+  OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf
+  MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf {
+    <LibraryClasses>
+      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  }
+!endif #$(FDT_ENABLE)
+
+  #PCIe Support
+  OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
+    <LibraryClasses>
+      NULL|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf
+  }
+  OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <LibraryClasses>
+      NULL|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf
+  }
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+
+
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+  #
+  # Memory test
+  #
+  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+!ifdef $(INCLUDE_DP)
+      NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+!endif #$(INCLUDE_DP)
+!ifdef $(INCLUDE_TFTP_COMMAND)
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf
new file mode 100644
index 0000000..3302ec9
--- /dev/null
+++ b/Platforms/Hisilicon/D03/D03.fdf
@@ -0,0 +1,342 @@
+#
+#  Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[DEFINES]
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.D03]
+BaseAddress   = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+
+Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00010000
+NumBlocks     = 0x30
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv
+
+0x00040000|0x00240000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+0x00280000|0x00020000
+gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/bl1.bin
+0x002A0000|0x00020000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/fip.bin
+
+0x002D0000|0x0000E000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x20000
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
+  0xB8, 0xdF, 0x00, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002DE000|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
+  0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002E0000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+0x002F0000|0x00010000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatBinPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+
+  #
+  # Usb Support
+  #
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+  #
+  #ACPI
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  #Network
+  #
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
+
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
+
+  #
+  # PCI Support
+  #
+  INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
+  # VGA Driver
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf
+
+  #
+  # Build Shell from latest source code instead of prebuilt binary
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+  INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
+
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
+
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h
new file mode 100644
index 0000000..46c77d3
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h
@@ -0,0 +1,40 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __OEM_NIC_CONFIG_H__
+#define __OEM_NIC_CONFIG_H__
+
+#define I2C_SLAVEADDR_EEPROM     (0x52)
+
+#define I2C_OFFSET_EEPROM_ETH0   (0xc00)
+#define I2C_OFFSET_EEPROM_ETH1   (I2C_OFFSET_EEPROM_ETH0 + 6)
+#define I2C_OFFSET_EEPROM_ETH2   (I2C_OFFSET_EEPROM_ETH1 + 6)
+#define I2C_OFFSET_EEPROM_ETH3   (I2C_OFFSET_EEPROM_ETH2 + 6)
+#define I2C_OFFSET_EEPROM_ETH4   (I2C_OFFSET_EEPROM_ETH3 + 6)
+#define I2C_OFFSET_EEPROM_ETH5   (I2C_OFFSET_EEPROM_ETH4 + 6)
+#define I2C_OFFSET_EEPROM_ETH6   (I2C_OFFSET_EEPROM_ETH5 + 6)
+#define I2C_OFFSET_EEPROM_ETH7   (I2C_OFFSET_EEPROM_ETH6 + 6)
+
+#define MAC_ADDR_LEN  6
+
+#pragma pack(1)
+typedef struct {
+  UINT16 Crc16;
+  UINT16 MacLen;
+  UINT8  Mac[MAC_ADDR_LEN];
+} NIC_MAC_ADDRESS;
+#pragma pack()
+
+#endif
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c
new file mode 100644
index 0000000..dcaf3aa
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c
@@ -0,0 +1,362 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <OemNicConfig.h>
+#include <Library/CpldIoLib.h>
+
+#include <Library/I2CLib.h>
+
+#define EEPROM_I2C_PORT 6
+#define EEPROM_PAGE_SIZE 0x40
+
+EFI_STATUS
+EFIAPI OemGetMac2P (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+EFI_STATUS
+EFIAPI OemSetMac2P (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr);
+EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr);
+
+volatile unsigned char g_2pserveraddr[4][6] =
+{
+    {0x00, 0x18, 0x16, 0x29, 0x11, 0x00},
+    {0x00, 0x18, 0x16, 0x29, 0x11, 0x01},
+    {0x00, 0x18, 0x16, 0x29, 0x11, 0x02},
+    {0x00, 0x18, 0x16, 0x29, 0x11, 0x03}
+};
+
+UINT16 crc_tab[256] = {
+    0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
+    0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
+    0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
+    0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
+    0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
+    0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
+    0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
+    0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
+    0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
+    0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
+    0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
+    0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
+    0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
+    0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
+    0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
+    0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
+    0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
+    0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
+    0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
+    0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
+    0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
+    0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+    0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
+    0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
+    0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
+    0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
+    0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
+    0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
+    0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
+    0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
+    0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
+    0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0,
+};
+
+UINT16 make_crc_checksum(UINT8 *buf, UINT32 len)
+{
+    UINT16 StartCRC = 0;
+
+    if (len > (512 * 1024))
+    {
+        return 0;
+    }
+
+    if (NULL == buf)
+    {
+        return 0;
+    }
+
+    while (len)
+    {
+        StartCRC = crc_tab[((UINT8)((StartCRC >> 8) & 0xff)) ^ *(buf++)] ^ ((UINT16)(StartCRC << 8));
+        len--;
+    }
+
+    return StartCRC;
+}
+
+
+EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr)
+{
+    I2C_DEVICE stI2cDev = {0};
+    EFI_STATUS Status;
+    UINT16     I2cOffset;
+    UINT16     crc16;
+    NIC_MAC_ADDRESS stMacDesc = {0};
+    UINT16     RemainderMacOffset;
+    UINT16     LessSizeOfPage;
+
+    Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS));
+
+    stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+    stI2cDev.Port = EEPROM_I2C_PORT;
+    stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+    stI2cDev.Socket = 0;
+    RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE;
+    LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset;
+    //The length of NIC_MAC_ADDRESS is 10 bytes long,
+    //It surly less than EEPROM page size, so we could
+    //code as bellow, check the address whether across the page boundary,
+    //and split the data when across page boundary.
+    if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) {
+      Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
+    } else {
+      Status = I2CRead(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc);
+      if (!(EFI_ERROR(Status))) {
+        Status |= I2CRead(
+                          &stI2cDev,
+                          I2cOffset + LessSizeOfPage,
+                          sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage,
+                          (UINT8 *)&stMacDesc + LessSizeOfPage
+                         );
+      }
+    }
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + sizeof(stMacDesc.Mac));
+    if ((crc16 != stMacDesc.Crc16) || (0 == crc16))
+    {
+        return EFI_NOT_FOUND;
+    }
+
+    gBS->CopyMem((VOID *)(pucAddr), (VOID *)(stMacDesc.Mac), MAC_ADDR_LEN);
+
+
+    return EFI_SUCCESS;
+}
+
+
+EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr)
+{
+    I2C_DEVICE stI2cDev = {0};
+    EFI_STATUS Status;
+    UINT16     I2cOffset;
+    NIC_MAC_ADDRESS stMacDesc = {0};
+
+
+    stMacDesc.MacLen = MAC_ADDR_LEN;
+    UINT16     RemainderMacOffset;
+    UINT16     LessSizeOfPage;
+    gBS->CopyMem((VOID *)(stMacDesc.Mac), (VOID *)pucAddr, MAC_ADDR_LEN);
+
+    stMacDesc.Crc16  = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + MAC_ADDR_LEN);
+
+    Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS));
+
+    stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+    stI2cDev.Port = EEPROM_I2C_PORT;
+    stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+    stI2cDev.Socket = 0;
+    RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE;
+    LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset;
+    //The length of NIC_MAC_ADDRESS is 10 bytes long,
+    //It surly less than EEPROM page size, so we could
+    //code as bellow, check the address whether across the page boundary,
+    //and split the data when across page boundary.
+    if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) {
+      Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
+    } else {
+      Status = I2CWrite(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc);
+      if (!(EFI_ERROR(Status))) {
+        Status |= I2CWrite(
+                           &stI2cDev,
+                           I2cOffset + LessSizeOfPage,
+                           sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage,
+                           (UINT8 *)&stMacDesc + LessSizeOfPage
+                          );
+      }
+    }
+    if (EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemGetMac2P (
+  IN OUT EFI_MAC_ADDRESS *Mac,
+  IN UINTN Port
+  )
+{
+    EFI_STATUS Status;
+
+    if (NULL == Mac)
+    {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+      return EFI_INVALID_PARAMETER;
+    }
+
+    Status = OemGetMacE2prom(Port, Mac->Addr);
+    if ((EFI_ERROR(Status)))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Get mac failed!\n", __FUNCTION__, __LINE__));
+
+        Mac->Addr[0] = 0x00;
+        Mac->Addr[1] = 0x18;
+        Mac->Addr[2] = 0x82;
+        Mac->Addr[3] = 0x2F;
+        Mac->Addr[4] = 0x02;
+        Mac->Addr[5] = Port;
+        return Status;
+    }
+
+    return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemSetMac2P (
+  IN EFI_MAC_ADDRESS *Mac,
+  IN UINTN Port
+  )
+{
+  EFI_STATUS Status;
+
+  if (NULL == Mac)
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = OemSetMacE2prom(Port, Mac->Addr);
+  if ((EFI_ERROR(Status)))
+  {
+      DEBUG((EFI_D_ERROR, "[%a]:[%dL] Set mac failed!\n", __FUNCTION__, __LINE__));
+      return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+HISI_BOARD_NIC_PROTOCOL mHisiBoardNicProtocol2P = {
+  .GetMac = OemGetMac2P,
+  .SetMac = OemSetMac2P,
+};
+
+VOID OemFeedbackXGeStatus(BOOLEAN IsLinkup, BOOLEAN IsActOK, UINT32 port)
+{
+    UINT8 CpldValue = 0;
+    UINTN RegOffset = 0x10 + (UINTN)port * 4;
+
+    if (port > 2)
+    {
+        return;
+    }
+
+    if (IsLinkup)
+    {
+        CpldValue = ReadCpldReg(RegOffset);
+        CpldValue |= BIT2;
+        WriteCpldReg(RegOffset, CpldValue);
+    }
+    else
+    {
+        CpldValue = ReadCpldReg(RegOffset);
+        CpldValue &= ~((UINT8)BIT2);
+        WriteCpldReg(RegOffset, CpldValue);
+    }
+
+    if (IsActOK)
+    {
+        CpldValue = ReadCpldReg(RegOffset);
+        CpldValue |= BIT4;
+        WriteCpldReg(RegOffset, CpldValue);
+    }
+    else
+    {
+        CpldValue = ReadCpldReg(RegOffset);
+        CpldValue &= ~((UINT8)BIT4);
+        WriteCpldReg(RegOffset, CpldValue);
+    }
+}
+
+HISI_BOARD_XGE_STATUS_PROTOCOL mHisiBoardXgeStatusProtocol2p = {
+  .FeedbackXgeStatus = OemFeedbackXGeStatus,
+};
+
+
+EFI_STATUS
+EFIAPI
+OemNicConfigEntry (
+  IN EFI_HANDLE           ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+{
+  EFI_STATUS Status;
+
+  Status = gBS->InstallProtocolInterface(
+    &ImageHandle,
+    &gHisiBoardNicProtocolGuid,
+    EFI_NATIVE_INTERFACE,
+    &mHisiBoardNicProtocol2P
+    );
+
+  if(EFI_ERROR(Status))
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status));
+    return Status;
+  }
+
+  Status = gBS->InstallProtocolInterface(
+    &ImageHandle,
+    &gHisiBoardXgeStatusProtocolGuid,
+    EFI_NATIVE_INTERFACE,
+    &mHisiBoardXgeStatusProtocol2p
+    );
+
+  if(EFI_ERROR(Status))
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status));
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
new file mode 100644
index 0000000..8e1fd9d
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
@@ -0,0 +1,52 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemNicConfigPangea
+  FILE_GUID                      = 3A23A929-1F38-4d04-8A01-38AD993EB2CE
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = OemNicConfigEntry
+
+[Sources.common]
+  OemNicConfig2P.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[Protocols]
+  gHisiBoardNicProtocolGuid       ##Produce
+  gHisiBoardXgeStatusProtocolGuid
+
+[LibraryClasses]
+  CpldIoLib
+  UefiDriverEntryPoint
+  UefiBootServicesTableLib
+  DebugLib
+  IoLib
+  TimerLib
+  I2CLib
+  PcdLib
+
+[FixedPcd]
+
+[Depex]
+  TRUE
+
+[BuildOptions]
+
diff --git a/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c
new file mode 100644
index 0000000..8bfac2d
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c
@@ -0,0 +1,437 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/PciPlatform.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/MemoryAllocationLib.h>
+
+//
+// Global variables for Option ROMs
+//
+#define NULL_ROM_FILE_GUID \
+  { \
+    0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} \
+  }
+
+#define SAS_OPTION_ROM_FILE_GUID \
+{ 0xb47533c7, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xdb}}
+
+#define SAS3108_OPTION_ROM_FILE_GUID \
+{ 0xb47533c8, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xd8}}
+
+#define INVALID                     0xBD
+
+
+typedef struct {
+  EFI_HANDLE                      PciPlatformHandle;
+  EFI_PCI_PLATFORM_PROTOCOL       PciPlatform;
+} PCI_PLATFORM_PRIVATE_DATA;
+
+
+#define MAX_ROM_NUMBER  2
+
+
+typedef struct {
+  EFI_GUID  FileName;
+  UINTN     Segment;
+  UINTN     Bus;
+  UINTN     Device;
+  UINTN     Function;
+  UINT16    VendorId;
+  UINT16    DeviceId;
+} PCI_OPTION_ROM_TABLE;
+
+typedef struct {
+  UINTN                   RomSize;
+  VOID                    *RomBase;
+} OPTION_ROM_INFO;
+
+PCI_PLATFORM_PRIVATE_DATA *mPciPrivateData = NULL;
+
+PCI_OPTION_ROM_TABLE      mPciOptionRomTable[] = {
+  {
+    SAS_OPTION_ROM_FILE_GUID,
+    0,
+    2,
+    0,
+    0,
+    0x1000,
+    0x0097
+  },
+  {
+    SAS3108_OPTION_ROM_FILE_GUID,
+    0,
+    1,
+    0,
+    0,
+    0x1000,
+    0x005D
+  },
+
+    //
+    // End of OptionROM Entries
+    //
+  {
+    NULL_ROM_FILE_GUID, // Guid
+    0,                  // Segment
+    0,                  // Bus Number
+    0,                  // Device Number
+    0,                  // Function Number
+    0xffff,             // Vendor ID
+    0xffff              // Device ID
+  }
+};
+
+EFI_STATUS
+EFIAPI
+GetPlatformPolicy (
+  IN CONST EFI_PCI_PLATFORM_PROTOCOL         *This,
+  OUT EFI_PCI_PLATFORM_POLICY           *PciPolicy
+  )
+/*++
+
+Routine Description:
+
+  Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS.
+
+Arguments:
+
+  This       -  The pointer to the Protocol itself.
+  PciPolicy  -  the returned Policy.
+
+Returns:
+
+  EFI_UNSUPPORTED        -  Function not supported.
+  EFI_INVALID_PARAMETER  -  Invalid PciPolicy value.
+
+--*/
+{
+  if (PciPolicy == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+GetRawImage (
+  IN     EFI_GUID                       *NameGuid,
+  IN OUT VOID                           **Buffer,
+  IN OUT UINTN                          *Size
+  )
+/*++
+
+Routine Description:
+
+  Get an indicated image in raw sections.
+
+Arguments:
+
+  NameGuid  -  NameGuid of the image to get.
+  Buffer    -  Buffer to store the image get.
+  Size      -  size of the image get.
+
+Returns:
+
+  EFI_NOT_FOUND   -  Could not find the image.
+  EFI_LOAD_ERROR  -  Error occurred during image loading.
+  EFI_SUCCESS     -  Image has been successfully loaded.
+
+--*/
+{
+  EFI_STATUS                    Status;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         HandleCount;
+  UINTN                         Index;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+  UINT32                        AuthenticationStatus;
+
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiFirmwareVolume2ProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer
+                  );
+  if (EFI_ERROR (Status) || HandleCount == 0) {
+    return EFI_NOT_FOUND;
+  }
+  //
+  // Find desired image in all Fvs
+  //
+  for (Index = 0; Index < HandleCount; Index++) {
+    Status = gBS->HandleProtocol (
+                    HandleBuffer[Index],
+                    &gEfiFirmwareVolume2ProtocolGuid,
+                    (VOID **)&Fv
+                    );
+    if (EFI_ERROR (Status)) {
+      return EFI_LOAD_ERROR;
+    }
+    //
+    // Try a raw file
+    //
+    *Buffer = NULL;
+    *Size   = 0;
+    Status = Fv->ReadSection (
+                  Fv,
+                  NameGuid,
+                  EFI_SECTION_RAW,
+                  0,
+                  Buffer,
+                  Size,
+                  &AuthenticationStatus
+                  );
+
+    if (!EFI_ERROR (Status)) {
+      break;
+    }
+  }
+
+  if (Index >= HandleCount) {
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+GetPciRom (
+  IN CONST EFI_PCI_PLATFORM_PROTOCOL         *This,
+  IN  EFI_HANDLE                        PciHandle,
+  OUT VOID                              **RomImage,
+  OUT UINTN                             *RomSize
+  )
+/*++
+
+Routine Description:
+
+  Return a PCI ROM image for the onboard device represented by PciHandle.
+
+Arguments:
+
+  This       -  Protocol instance pointer.
+  PciHandle  -  PCI device to return the ROM image for.
+  RomImage   -  PCI Rom Image for onboard device.
+  RomSize    -  Size of RomImage in bytes.
+
+Returns:
+
+  EFI_SUCCESS    -  RomImage is valid.
+  EFI_NOT_FOUND  -  No RomImage.
+
+--*/
+{
+  EFI_STATUS                        Status;
+  EFI_PCI_IO_PROTOCOL               *PciIo;
+  UINT16                            VendorId;
+  UINT16                            DeviceId;
+  UINTN                             TableIndex;
+  UINTN                             RomImageNumber;
+  OPTION_ROM_INFO                   OptionRominfo[MAX_ROM_NUMBER];
+
+  Status = gBS->HandleProtocol (
+                  PciHandle,
+                  &gEfiPciIoProtocolGuid,
+                  (VOID **) &PciIo
+                  );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, 1, &VendorId);
+  (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_DEVICE_ID_OFFSET, 1, &DeviceId);
+
+  //
+  // Loop through table of video option rom descriptions
+  //
+  RomImageNumber = 0;
+  for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff; TableIndex++) {
+    //
+    // See if the PCI device specified by PciHandle matches at device in mPciOptionRomTable
+    //
+        if ((VendorId != mPciOptionRomTable[TableIndex].VendorId)
+            || (DeviceId != mPciOptionRomTable[TableIndex].DeviceId)
+        )
+        {
+            continue;
+        }
+
+    Status = GetRawImage (
+              &mPciOptionRomTable[TableIndex].FileName,
+              &(OptionRominfo[RomImageNumber].RomBase),
+              &(OptionRominfo[RomImageNumber].RomSize)
+              );
+
+    if (EFI_ERROR (Status)) {
+      continue;
+    } else {
+      RomImageNumber++;
+      if (RomImageNumber == MAX_ROM_NUMBER) {
+        break;
+      }
+    }
+  }
+
+  if (RomImageNumber == 0) {
+
+    return EFI_NOT_FOUND;
+
+  } else {
+    *RomImage = OptionRominfo[RomImageNumber - 1].RomBase;
+    *RomSize  = OptionRominfo[RomImageNumber - 1].RomSize;
+
+    if (RomImageNumber > 1) {
+      //
+      // More than one OPROM have been found!
+      //
+
+    }
+
+    return EFI_SUCCESS;
+  }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformPrepController (
+  IN  EFI_PCI_PLATFORM_PROTOCOL                      *This,
+  IN  EFI_HANDLE                                     HostBridge,
+  IN  EFI_HANDLE                                     RootBridge,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS    PciAddress,
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE   Phase,
+  IN  EFI_PCI_CHIPSET_EXECUTION_PHASE                ChipsetPhase
+  )
+/*++
+
+Routine Description:
+
+  The PlatformPrepController() function can be used to notify the platform driver so that
+  it can perform platform-specific actions. No specific actions are required.
+  Several notification points are defined at this time. More synchronization points may be
+  added as required in the future. The PCI bus driver calls the platform driver twice for
+  every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver
+  is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has
+  been notified.
+  This member function may not perform any error checking on the input parameters. It also
+  does not return any error codes. If this member function detects any error condition, it
+  needs to handle those errors on its own because there is no way to surface any errors to
+  the caller.
+
+Arguments:
+
+  This          -  Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+  HostBridge    -  The associated PCI host bridge handle.
+  RootBridge    -  The associated PCI root bridge handle.
+  PciAddress    -  The address of the PCI device on the PCI bus.
+  Phase         -  The phase of the PCI controller enumeration.
+  ChipsetPhase  -  Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+  EFI_SUCCESS     -  The function completed successfully.
+  EFI_UNSUPPORTED -  Not supported.
+
+--*/
+{
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PhaseNotify (
+  IN EFI_PCI_PLATFORM_PROTOCOL                       *This,
+  IN  EFI_HANDLE                                     HostBridge,
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE  Phase,
+  IN  EFI_PCI_CHIPSET_EXECUTION_PHASE                ChipsetPhase
+  )
+/*++
+
+Routine Description:
+
+  Perform initialization by the phase indicated.
+
+Arguments:
+
+  This          -  Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+  HostBridge    -  The associated PCI host bridge handle.
+  Phase         -  The phase of the PCI controller enumeration.
+  ChipsetPhase  -  Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+  EFI_SUCCESS  -  Must return with success.
+
+--*/
+{
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciPlatformDriverEntry (
+  IN EFI_HANDLE                         ImageHandle,
+  IN EFI_SYSTEM_TABLE                   *SystemTable
+  )
+/*++
+
+Routine Description:
+  Main Entry point of the Pci Platform Driver.
+
+Arguments:
+
+  ImageHandle  -  Handle to the image.
+  SystemTable  -  Handle to System Table.
+
+Returns:
+
+  EFI_STATUS  -  Status of the function calling.
+
+--*/
+{
+  EFI_STATUS  Status;
+  PCI_PLATFORM_PRIVATE_DATA *PciPrivateData;
+
+  PciPrivateData = AllocateZeroPool (sizeof (PCI_PLATFORM_PRIVATE_DATA));
+  mPciPrivateData = PciPrivateData;
+
+  mPciPrivateData->PciPlatform.PlatformNotify             = PhaseNotify;
+  mPciPrivateData->PciPlatform.PlatformPrepController     = PlatformPrepController;
+  mPciPrivateData->PciPlatform.GetPlatformPolicy          = GetPlatformPolicy;
+  mPciPrivateData->PciPlatform.GetPciRom                  = GetPciRom;
+
+  //
+  // Install on a new handle
+  //
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &mPciPrivateData->PciPlatformHandle,
+                  &gEfiPciPlatformProtocolGuid,
+                  &mPciPrivateData->PciPlatform,
+                  NULL
+                  );
+
+  return Status;
+}
diff --git a/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h
new file mode 100644
index 0000000..a89f7c6
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h
@@ -0,0 +1,180 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef PCI_PLATFORM_H_
+#define PCI_PLATFORM_H_
+
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/PciPlatform.h>
+
+
+//
+// Global variables for Option ROMs
+//
+#define NULL_ROM_FILE_GUID \
+  { \
+    0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 \
+  }
+
+
+typedef struct {
+  EFI_GUID  FileName;
+  UINTN     Segment;
+  UINTN     Bus;
+  UINTN     Device;
+  UINTN     Function;
+  UINT16    VendorId;
+  UINT16    DeviceId;
+} PCI_OPTION_ROM_TABLE;
+
+#define INVALID                     0xBD
+
+
+typedef struct {
+  EFI_HANDLE                      PciPlatformHandle;
+  EFI_PCI_PLATFORM_PROTOCOL       PciPlatform;
+} PCI_PLATFORM_PRIVATE_DATA;
+
+
+
+extern PCI_PLATFORM_PRIVATE_DATA  mPciPrivateData;
+
+EFI_STATUS
+EFIAPI
+PhaseNotify (
+  IN EFI_PCI_PLATFORM_PROTOCOL                        *This,
+  IN EFI_HANDLE                                       HostBridge,
+  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase,
+  IN EFI_PCI_CHIPSET_EXECUTION_PHASE                  ChipsetPhase
+  )
+/*++
+
+Routine Description:
+
+  Perform initialization by the phase indicated.
+
+Arguments:
+
+  This          -  Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+  HostBridge    -  The associated PCI host bridge handle.
+  Phase         -  The phase of the PCI controller enumeration.
+  ChipsetPhase  -  Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+  EFI_SUCCESS  -  Must return with success.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+PlatformPrepController (
+  IN  EFI_PCI_PLATFORM_PROTOCOL                      *This,
+  IN  EFI_HANDLE                                     HostBridge,
+  IN  EFI_HANDLE                                     RootBridge,
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS    PciAddress,
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE   Phase,
+  IN  EFI_PCI_CHIPSET_EXECUTION_PHASE                ChipsetPhase
+  )
+/*++
+
+Routine Description:
+
+  The PlatformPrepController() function can be used to notify the platform driver so that
+  it can perform platform-specific actions. No specific actions are required.
+  Several notification points are defined at this time. More synchronization points may be
+  added as required in the future. The PCI bus driver calls the platform driver twice for
+  every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver
+  is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has
+  been notified.
+  This member function may not perform any error checking on the input parameters. It also
+  does not return any error codes. If this member function detects any error condition, it
+  needs to handle those errors on its own because there is no way to surface any errors to
+  the caller.
+
+Arguments:
+
+  This          -  Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+  HostBridge    -  The associated PCI host bridge handle.
+  RootBridge    -  The associated PCI root bridge handle.
+  PciAddress    -  The address of the PCI device on the PCI bus.
+  Phase         -  The phase of the PCI controller enumeration.
+  ChipsetPhase  -  Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+  EFI_SUCCESS  -  The function completed successfully.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+GetPlatformPolicy (
+  IN  EFI_PCI_PLATFORM_PROTOCOL            *This,
+  OUT EFI_PCI_PLATFORM_POLICY              *PciPolicy
+  )
+/*++
+
+Routine Description:
+
+  Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS.
+
+Arguments:
+
+  This       -  The pointer to the Protocol itself.
+  PciPolicy  -  the returned Policy.
+
+Returns:
+
+  EFI_UNSUPPORTED        -  Function not supported.
+  EFI_INVALID_PARAMETER  -  Invalid PciPolicy value.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+GetPciRom (
+  IN   EFI_PCI_PLATFORM_PROTOCOL            *This,
+  IN   EFI_HANDLE                           PciHandle,
+  OUT  VOID                                 **RomImage,
+  OUT  UINTN                                *RomSize
+  )
+/*++
+
+Routine Description:
+
+  Return a PCI ROM image for the onboard device represented by PciHandle.
+
+Arguments:
+
+  This       -  Protocol instance pointer.
+  PciHandle  -  PCI device to return the ROM image for.
+  RomImage   -  PCI Rom Image for onboard device.
+  RomSize    -  Size of RomImage in bytes.
+
+Returns:
+
+  EFI_SUCCESS    -  RomImage is valid.
+  EFI_NOT_FOUND  -  No RomImage.
+
+--*/
+;
+
+#endif
diff --git a/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
new file mode 100644
index 0000000..6d1b085
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
@@ -0,0 +1,53 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[defines]
+  INF_VERSION          = 0x00010005
+  BASE_NAME            = PciPlatform
+  FILE_GUID            = E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017
+  MODULE_TYPE          = DXE_DRIVER
+  VERSION_STRING       = 1.0
+  ENTRY_POINT          = PciPlatformDriverEntry
+
+[sources.common]
+  PciPlatform.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  UefiLib
+  BaseLib
+  DebugLib
+  ArmLib
+  IoLib
+  MemoryAllocationLib
+
+[Protocols]
+  gEfiPciPlatformProtocolGuid
+  gEfiFirmwareVolume2ProtocolGuid
+  gEfiPciIoProtocolGuid
+
+[Pcd]
+
+[FixedPcd]
+
+[Depex]
+  TRUE
+
diff --git a/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c b/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c
new file mode 100644
index 0000000..97cf6b8
--- /dev/null
+++ b/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c
@@ -0,0 +1,180 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/CacheMaintenanceLib.h>
+
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+
+#include <Library/OemMiscLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/ArmLib.h>
+
+#define PERI_SUBCTRL_BASE                               (0x40000000)
+#define MDIO_SUBCTRL_BASE                               (0x60000000)
+#define PCIE2_SUBCTRL_BASE                              (0xA0000000)
+#define PCIE0_SUBCTRL_BASE                              (0xB0000000)
+#define ALG_BASE                                        (0xD0000000)
+
+#define SC_BROADCAST_EN_REG                             (0x16220)
+#define SC_BROADCAST_SCL1_ADDR0_REG                     (0x16230)
+#define SC_BROADCAST_SCL1_ADDR1_REG                     (0x16234)
+#define SC_BROADCAST_SCL2_ADDR0_REG                     (0x16238)
+#define SC_BROADCAST_SCL2_ADDR1_REG                     (0x1623C)
+#define SC_BROADCAST_SCL3_ADDR0_REG                     (0x16240)
+#define SC_BROADCAST_SCL3_ADDR1_REG                     (0x16244)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG                 (0x1000)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG         (0x1010)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG         (0x1014)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG         (0x1018)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG         (0x101C)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG                  (0x1200)
+#define SC_ITS_M3_INT_MUX_SEL_REG                       (0x21F0)
+#define SC_TM_CLKEN0_REG                                (0x2050)
+
+#define SC_TM_CLKEN0_REG_VALUE                          (0x3)
+#define SC_BROADCAST_EN_REG_VALUE                       (0x7)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0              (0x0)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1              (0x40016260)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2              (0x60016260)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3              (0x400)
+#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE                 (0x7)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0           (0x0)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0          (0x27)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1          (0x2F)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2          (0x77)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0  (0x178033)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0  (0x17003c)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0  (0x15003d)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1  (0x170035)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0  (0x16003e)
+
+VOID PlatformTimerStart (VOID)
+{
+    // Timer0 clock enable
+    MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE);
+}
+
+void QResetAp(VOID)
+{
+    MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
+    (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
+    ArmDataSynchronizationBarrier ();
+    ArmInstructionSynchronizationBarrier ();
+
+    //SCCL A
+    if (!PcdGet64 (PcdTrustedFirmwareEnable))
+    {
+        StartupAp();
+    }
+}
+
+
+EFI_STATUS
+EFIAPI
+EarlyConfigEntry (
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+    DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
+    (VOID)SmmuConfigForOS();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+
+    DEBUG((EFI_D_INFO,"AP CONFIG........."));
+    (VOID)QResetAp();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"MN CONFIG........."));
+    (VOID)MN_CONFIG();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    if(OemIsMpBoot())
+    {
+        DEBUG((EFI_D_INFO,"Event Broadcast CONFIG........."));
+        //EVENT broadcast
+        MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
+        MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+        MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+        MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+        MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+        MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+        MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+
+        MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
+        MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+        MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+        MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+        MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+        MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+        MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+
+        MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
+        MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+        MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+        MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+        MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+        MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+        MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+
+        MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
+        MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+        MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+        MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+        MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+        MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+        MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+
+        DEBUG((EFI_D_INFO,"Done\n"));
+    }
+
+    DEBUG((EFI_D_INFO,"PCIE RAM Address CONFIG........."));
+
+    if(OemIsMpBoot())
+    {
+        MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0);
+        MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
+        MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1);
+        MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0);
+        MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1);
+    }
+
+    else
+    {
+        MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_REMAP_CTRL_REG, PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0);
+        MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2);
+        MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0);
+        MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
+        MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0);
+    }
+
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_REG_VALUE);
+
+    DEBUG((EFI_D_INFO,"Timer CONFIG........."));
+    PlatformTimerStart ();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    return EFI_SUCCESS;
+}
+
diff --git a/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf b/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
new file mode 100644
index 0000000..cd6b964
--- /dev/null
+++ b/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
@@ -0,0 +1,55 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = EarlyConfigPeimD03
+  FILE_GUID                      = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = EarlyConfigEntry
+
+[Sources.common]
+  EarlyConfigPeimD03.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PeimEntryPoint
+  PcdLib
+  DebugLib
+  IoLib
+  CacheMaintenanceLib
+
+  PlatformSysCtrlLib
+  ArmLib
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdMailBoxAddress
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
+
+[Depex]
+## As we will clean mailbox in this module, need to wait memory init complete
+  gEfiPeiMemoryDiscoveredPpiGuid
+
+[BuildOptions]
+
diff --git a/Platforms/Hisilicon/D03/Include/Library/CpldD03.h b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h
new file mode 100644
index 0000000..456bf4b
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Include/Library/CpldD03.h
@@ -0,0 +1,25 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CPLD_D03_H__
+#define __CPLD_D03_H__
+
+#define CPLD_BIOSINDICATE_FLAG  0x09
+#define CPLD_I2C_SWITCH_FLAG    0x17
+#define CPU_GET_I2C_CONTROL     BIT2
+#define BMC_I2C_STATUS          BIT3
+
+
+#endif
diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h
new file mode 100644
index 0000000..d1e6c41
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h
@@ -0,0 +1,178 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+**/
+
+
+#ifndef __DS3231_REAL_TIME_CLOCK_H__
+#define __DS3231_REAL_TIME_CLOCK_H__
+
+#define DS3231_REGADDR_SECONDS      0x00
+#define DS3231_REGADDR_MIUTES       0x01
+#define DS3231_REGADDR_HOURS        0x02
+#define DS3231_REGADDR_DAY          0x03
+#define DS3231_REGADDR_DATE         0x04
+#define DS3231_REGADDR_MONTH        0x05
+#define DS3231_REGADDR_YEAR         0x06
+#define DS3231_REGADDR_ALARM1SEC    0x07
+#define DS3231_REGADDR_ALARM1MIN    0x08
+#define DS3231_REGADDR_ALARM1HOUR   0x09
+#define DS3231_REGADDR_ALARM1DAY    0x0A
+#define DS3231_REGADDR_ALARM2MIN    0x0B
+#define DS3231_REGADDR_ALARM2HOUR   0x0C
+#define DS3231_REGADDR_ALARM2DAY    0x0D
+#define DS3231_REGADDR_CONTROL      0x0E
+#define DS3231_REGADDR_STATUS       0x0F
+#define DS3231_REGADDR_AGOFFSET     0x10
+#define DS3231_REGADDR_TEMPMSB      0x11
+#define DS3231_REGADDR_TEMPLSB      0x12
+
+
+typedef union {
+  struct{
+    UINT8 A1IE:1;
+    UINT8 A2IE:1;
+    UINT8 INTCN:1;
+    UINT8 RSV:2;
+    UINT8 CONV:1;
+    UINT8 BBSQW:1;
+    UINT8 EOSC_N:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_CONTROL;
+
+typedef union {
+  struct{
+    UINT8 A1F:1;
+    UINT8 A2F:1;
+    UINT8 BSY:1;
+    UINT8 EN32KHZ:2;
+    UINT8 Rsv:3;
+    UINT8 OSF:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_STATUS;
+
+
+typedef union {
+  struct{
+    UINT8 Data:7;
+    UINT8 Sign:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_AGOFFSET;
+
+typedef union {
+  struct{
+    UINT8 Data:7;
+    UINT8 Sign:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_TEMPMSB;
+
+
+typedef union {
+  struct{
+    UINT8 Rsv:6;
+    UINT8 Data:2;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_TEMPLSB;
+
+typedef union {
+  struct{
+    UINT8 Seconds:4;
+    UINT8 Seconds10:3;
+    UINT8 Rsv:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_SECONDS;
+
+typedef union {
+  struct{
+    UINT8 Minutes:4;
+    UINT8 Minutes10:3;
+    UINT8 Rsv:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_MINUTES;
+
+typedef union {
+  struct{
+    UINT8 Hour:4;
+    UINT8 Hours10:1;
+    UINT8 PM_20Hours:1;
+    UINT8 Hour24_n:1;
+    UINT8 Rsv:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_HOURS;
+
+typedef union {
+  struct{
+    UINT8 Day:3;
+    UINT8 Rsv:5;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_DAY;
+
+typedef union {
+  struct{
+    UINT8 Month:4;
+    UINT8 Month10:1;
+    UINT8 Rsv:2;
+    UINT8 Century:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_MONTH;
+
+typedef union {
+  struct{
+    UINT8 Year:4;
+    UINT8 Year10:4;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_YEAR;
+
+typedef union {
+  struct{
+    UINT8 Seconds:4;
+    UINT8 Seconds10:3;
+    UINT8 A1M1:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_ALARM1SEC;
+
+typedef union {
+  struct{
+    UINT8 Minutes:4;
+    UINT8 Minutes10:3;
+    UINT8 A1M2:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_ALARM1MIN;
+
+typedef union {
+  struct{
+    UINT8 Hour:4;
+    UINT8 Hours10:1;
+    UINT8 PM_20Hours:1;
+    UINT8 Hours24:1;
+    UINT8 A1M3:1;
+  }bits;
+  UINT8 u8;
+}RTC_DS3231_ALARM1HOUR;
+
+#endif
diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
new file mode 100644
index 0000000..91d7de1
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
@@ -0,0 +1,504 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Currently this driver does not support runtime virtual calling.
+
+  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+// Use EfiAtRuntime to check stage
+#include <Library/UefiRuntimeLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/TimerLib.h>
+#include <Library/EfiTimeBaseLib.h>
+#include <Protocol/RealTimeClock.h>
+#include <Library/I2CLib.h>
+#include "DS3231RealTimeClock.h"
+#include <Library/CpldD03.h>
+#include <Library/CpldIoLib.h>
+
+extern I2C_DEVICE gDS3231RtcDevice;
+
+STATIC BOOLEAN       mDS3231Initialized = FALSE;
+
+EFI_STATUS
+IdentifyDS3231 (
+  VOID
+  )
+{
+  EFI_STATUS    Status;
+
+  Status = EFI_SUCCESS;
+  return Status;
+}
+
+EFI_STATUS
+SwitchRtcI2cChannelAndLock (
+  VOID
+  )
+{
+  UINT8   Temp;
+  UINT8   Count;
+
+  for (Count = 0; Count < 20; Count++) {
+    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+
+    if ((Temp & BMC_I2C_STATUS) != 0) {
+      //The I2C channel is shared with BMC,
+      //Check if BMC has taken ownership of I2C.
+      //If so, wait 30ms, then try again.
+      //If not, start using I2C.
+      //And the CPLD_I2C_SWITCH_FLAG will be set to CPU_GET_I2C_CONTROL
+      //BMC will check this flag to decide to use I2C or not.
+      MicroSecondDelay (30000);
+      continue;
+    }
+
+    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+    Temp = Temp | CPU_GET_I2C_CONTROL;
+    WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
+
+    //This is empirical value,give cpld some time to make sure the
+    //value is wrote in
+    MicroSecondDelay (2);
+    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+
+    if ((Temp & CPU_GET_I2C_CONTROL) == CPU_GET_I2C_CONTROL) {
+      return EFI_SUCCESS;
+    }
+
+    //There need 30ms to keep consistent with the previous loops if the CPU failed
+    //to get control of I2C
+    MicroSecondDelay (30000);
+  }
+
+  Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+  Temp = Temp & ~CPU_GET_I2C_CONTROL;
+  WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
+
+  return EFI_NOT_READY;
+}
+
+
+EFI_STATUS
+InitializeDS3231 (
+  VOID
+  )
+{
+  EFI_STATUS    Status;
+  I2C_DEVICE    Dev;
+  RTC_DS3231_CONTROL Temp;
+  RTC_DS3231_HOURS   Hours;
+
+  // Prepare the hardware
+  (VOID)IdentifyDS3231();
+
+  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+  Status = I2CInit(Dev.Socket,Dev.Port,Normal);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+  // Ensure interrupts are masked. We do not want RTC interrupts in UEFI
+  Status = I2CRead(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+  Temp.bits.INTCN = 0;
+  Status = I2CWrite(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+
+  MicroSecondDelay(2000);
+  Status = I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+  Hours.bits.Hour24_n = 0;
+  Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8);
+  if (EFI_ERROR (Status)) {
+    goto EXIT;
+  }
+
+
+  mDS3231Initialized = TRUE;
+
+  EXIT:
+  return Status;
+}
+
+/**
+  Returns the current time and date information, and the time-keeping capabilities
+  of the hardware platform.
+
+  @param  Time                   A pointer to storage to receive a snapshot of the current time.
+  @param  Capabilities           An optional pointer to a buffer to receive the real time clock
+                                 device's capabilities.
+
+  @retval EFI_SUCCESS            The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER  Time is NULL.
+  @retval EFI_DEVICE_ERROR       The time could not be retrieved due to hardware error.
+  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT EFI_TIME                *Time,
+  OUT EFI_TIME_CAPABILITIES   *Capabilities
+  )
+{
+  EFI_STATUS  Status = EFI_SUCCESS;
+  UINT8       Temp;
+  UINT8       BaseHour = 0;
+
+  UINT16      BaseYear = 1900;
+
+  I2C_DEVICE    Dev;
+
+  // Ensure Time is a valid pointer
+  if (NULL == Time) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = SwitchRtcI2cChannelAndLock();
+  if(EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Initialize the hardware if not already done
+  if (!mDS3231Initialized) {
+    Status = InitializeDS3231 ();
+    if (EFI_ERROR (Status)) {
+      Status = EFI_NOT_READY;
+      goto GExit;
+    }
+  }
+
+  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+
+  Time->Month = ((Temp>>4)&1)*10+(Temp&0x0F);
+
+
+  if(Temp&0x80){
+    BaseYear = 2000;
+  }
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_YEAR,1,&Temp);
+
+  Time->Year  = BaseYear+(Temp>>4) *10 + (Temp&0x0F);
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_DATE,1,&Temp);
+
+  Time->Day   = ((Temp>>4)&3) *10 + (Temp&0x0F);
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Temp);
+
+  BaseHour = 0;
+  if((Temp&0x30) == 0x30){
+    Status = EFI_DEVICE_ERROR;
+    goto GExit;
+  }else if(Temp&0x20){
+    BaseHour = 20;
+  }else if(Temp&0x10){
+    BaseHour = 10;
+  }
+  Time->Hour        = BaseHour + (Temp&0x0F);
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_MIUTES,1,&Temp);
+
+  Time->Minute      = ((Temp>>4)&7) * 10 + (Temp&0x0F);
+
+  Status |= I2CRead(&Dev,DS3231_REGADDR_SECONDS,1,&Temp);
+
+  Time->Second      = (Temp>>4) * 10 + (Temp&0x0F);
+
+  Time->Nanosecond  = 0;
+  Time->Daylight    = 0;
+  Time->TimeZone    = EFI_UNSPECIFIED_TIMEZONE;
+
+  if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) {
+    Status = EFI_UNSUPPORTED;
+  }
+
+GExit:
+  Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+  Temp = Temp & ~CPU_GET_I2C_CONTROL;
+  WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
+
+  return Status;
+
+}
+
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time                  A pointer to the current time.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+  IN  EFI_TIME                *Time
+  )
+{
+  EFI_STATUS  Status = EFI_SUCCESS;
+  I2C_DEVICE    Dev;
+  UINT8 Temp;
+
+  UINT16 BaseYear = 1900;
+
+
+
+  // Check the input parameters are within the range specified by UEFI
+  if(!IsTimeValid(Time)){
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = SwitchRtcI2cChannelAndLock();
+  if(EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // Initialize the hardware if not already done
+  if (!mDS3231Initialized) {
+    Status = InitializeDS3231 ();
+    if (EFI_ERROR (Status)) {
+      goto EXIT;
+    }
+  }
+
+  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
+
+  Temp = ((Time->Second/10)<<4) | (Time->Second%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_SECONDS,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = ((Time->Minute/10)<<4) | (Time->Minute%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_MIUTES,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = 0;
+  if(Time->Hour > 19){
+    Temp = 2;
+  } else if(Time->Hour > 9){
+    Temp = 1;
+  }
+
+  Temp = (Temp << 4) | (Time->Hour%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = ((Time->Day/10)<<4) | (Time->Day%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_DATE,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+
+  Temp = 0;
+  if(Time->Year >= 2000){
+    Temp = 0x8;
+    BaseYear = 2000;
+  }
+
+  if(Time->Month > 9){
+    Temp |= 0x1;
+  }
+  Temp = (Temp<<4) | (Time->Month%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  Temp = (((Time->Year-BaseYear)/10)<<4) | (Time->Year%10);
+  MicroSecondDelay(1000);
+  Status = I2CWrite(&Dev,DS3231_REGADDR_YEAR,1,&Temp);
+  if(EFI_ERROR (Status)){
+    goto EXIT;
+  }
+
+  EXIT:
+
+  Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
+  Temp = Temp & ~CPU_GET_I2C_CONTROL;
+  WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
+
+  return Status;
+}
+
+
+/**
+  Returns the current wakeup alarm clock setting.
+
+  @param  Enabled               Indicates if the alarm is currently enabled or disabled.
+  @param  Pending               Indicates if the alarm signal is pending and requires acknowledgement.
+  @param  Time                  The current alarm setting.
+
+  @retval EFI_SUCCESS           The alarm settings were returned.
+  @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+  OUT BOOLEAN     *Enabled,
+  OUT BOOLEAN     *Pending,
+  OUT EFI_TIME    *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+
+/**
+  Sets the system wakeup alarm clock time.
+
+  @param  Enabled               Enable or disable the wakeup alarm.
+  @param  Time                  If Enable is TRUE, the time to set the wakeup alarm for.
+
+  @retval EFI_SUCCESS           If Enable is TRUE, then the wakeup alarm was enabled. If
+                                Enable is FALSE, then the wakeup alarm was disabled.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR      The wakeup time could not be set due to a hardware error.
+  @retval EFI_UNSUPPORTED       A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+  IN BOOLEAN      Enabled,
+  OUT EFI_TIME    *Time
+  )
+{
+  // Not a required feature
+  return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+  This is the declaration of an EFI image entry point. This can be the entry point to an application
+  written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+  @param  ImageHandle           Handle that identifies the loaded image.
+  @param  SystemTable           System Table for this image.
+
+  @retval EFI_SUCCESS           The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS    Status;
+  EFI_HANDLE    Handle;
+
+
+  EFI_TIME      EfiTime;
+
+  // Setup the setters and getters
+  gRT->GetTime       = LibGetTime;
+  gRT->SetTime       = LibSetTime;
+  gRT->GetWakeupTime = LibGetWakeupTime;
+  gRT->SetWakeupTime = LibSetWakeupTime;
+
+
+  (VOID)gRT->GetTime (&EfiTime, NULL);
+  if((EfiTime.Year < 2015) || (EfiTime.Year > 2099)){
+      EfiTime.Year          = 2015;
+      EfiTime.Month         = 1;
+      EfiTime.Day           = 1;
+      EfiTime.Hour          = 0;
+      EfiTime.Minute        = 0;
+      EfiTime.Second        = 0;
+      EfiTime.Nanosecond    = 0;
+      Status = gRT->SetTime(&EfiTime);
+      if (EFI_ERROR(Status))
+      {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status));
+      }
+  }
+
+  // Install the protocol
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gEfiRealTimeClockArchProtocolGuid,  NULL,
+                  NULL
+                 );
+
+  return Status;
+}
+
+
+/**
+  Fixup internal data so that EFI can be call in virtual mode.
+  Call the passed in Child Notify event and convert any pointers in
+  lib to virtual mode.
+
+  @param[in]    Event   The Event that is being processed
+  @param[in]    Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  //
+  // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+  // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+  // to virtual address. After the OS transitions to calling in virtual mode, all future
+  // runtime calls will be made in virtual mode.
+  //
+  return;
+}
diff --git a/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
new file mode 100644
index 0000000..ae1b9b8
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
@@ -0,0 +1,49 @@
+#/** @file
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = DS3231RealTimeClockLib
+  FILE_GUID                      = 470DFB96-E205-4515-A75E-2E60F853E79D
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RealTimeClockLib
+
+[Sources.common]
+  DS3231RealTimeClockLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/OpenPlatformPkg.dec
+  OpenPlatformPkg/Platforms/Hisilicon/D03/D03.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  IoLib
+  UefiLib
+  DebugLib
+  PcdLib
+  I2CLib
+  TimerLib
+# Use EFiAtRuntime to check stage
+  UefiRuntimeLib
+  CpldIoLib
+  EfiTimeBaseLib
+
+[Pcd]
+
diff --git a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c
new file mode 100755
index 0000000..d00cb9b
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c
@@ -0,0 +1,487 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/ArmArchTimer.h>
+#include <Library/BaseLib.h>
+#include <libfdt.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/FdtUpdateLib.h>
+#include <PlatformArch.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/OemMiscLib.h>
+
+typedef union AA_DAW
+{
+    /* Define the struct bits */
+    struct
+    {
+        unsigned int    sysdaw_id           : 7  ; /* [6:0] */
+        unsigned int    interleave_en       : 1  ; /* [7] */
+        unsigned int    sysdaw_size         : 4  ; /* [11:8] */
+        unsigned int    reserved            : 4  ; /* [15:12] */
+        unsigned int    sysdaw_addr         : 16 ; /* [31:16] */
+    } bits;
+
+    /* Define an unsigned member */
+    unsigned int    u32;
+
+} AA_DAW_U;
+
+
+
+MAC_ADDRESS gMacAddress[1];
+
+
+CHAR8  *EthName[8]=
+{
+ "ethernet@0","ethernet@1",
+ "ethernet@2","ethernet@3",
+ "ethernet@4","ethernet@5",
+ "ethernet@6","ethernet@7"
+};
+
+UINT8 DawNum[4] = {0, 0, 0, 0};
+PHY_MEM_REGION    *NodemRegion[4] = {NULL, NULL, NULL, NULL};
+UINTN  NumaPages[4] = {0, 0, 0, 0};
+
+CHAR8  *NumaNodeName[4]=
+{
+ "p0-ta","p0-tc",
+ "p1-ta","p1-tc",
+};
+
+STATIC
+BOOLEAN
+IsMemMapRegion (
+  IN EFI_MEMORY_TYPE MemoryType
+  )
+{
+  switch(MemoryType)
+    {
+        case EfiRuntimeServicesCode:
+        case EfiRuntimeServicesData:
+        case EfiConventionalMemory:
+        case EfiACPIReclaimMemory:
+        case EfiACPIMemoryNVS:
+        case EfiLoaderCode:
+        case EfiLoaderData:
+        case EfiBootServicesCode:
+        case EfiBootServicesData:
+        case EfiPalCode:
+                return TRUE;
+        default:
+                return FALSE;
+  }
+}
+
+
+EFI_STATUS
+GetMacAddress (UINT32 Port)
+{
+    EFI_MAC_ADDRESS Mac;
+    EFI_STATUS Status;
+    HISI_BOARD_NIC_PROTOCOL *OemNic = NULL;
+
+    Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    Status = OemNic->GetMac(&Mac, Port);
+    if(EFI_ERROR(Status))
+    {
+        DEBUG((EFI_D_ERROR, "[%a]:[%dL] GetMac failed %r\n", __FUNCTION__, __LINE__, Status));
+        return Status;
+    }
+
+    gMacAddress[0].data0=Mac.Addr[0];
+    gMacAddress[0].data1=Mac.Addr[1];
+    gMacAddress[0].data2=Mac.Addr[2];
+    gMacAddress[0].data3=Mac.Addr[3];
+    gMacAddress[0].data4=Mac.Addr[4];
+    gMacAddress[0].data5=Mac.Addr[5];
+    DEBUG((EFI_D_INFO, "Port%d:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+        Port,gMacAddress[0].data0,gMacAddress[0].data1,gMacAddress[0].data2,
+        gMacAddress[0].data3,gMacAddress[0].data4,gMacAddress[0].data5));
+
+    return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+DelPhyhandleUpdateMacAddress(IN VOID* Fdt)
+{
+    UINT8               port;
+    INTN                ethernetnode;
+    INTN                node;
+    INTN                Error;
+    struct              fdt_property *m_prop;
+    int                 m_oldlen;
+    EFI_STATUS          Status = EFI_SUCCESS;
+    EFI_STATUS          GetMacStatus = EFI_SUCCESS;
+
+    node = fdt_subnode_offset(Fdt, 0, "soc");
+    if (node < 0)
+    {
+        DEBUG ((EFI_D_ERROR, "can not find soc root node\n"));
+        return EFI_INVALID_PARAMETER;
+    }
+    else
+    {
+        for( port=0; port<8; port++ )
+        {
+            GetMacStatus= GetMacAddress(port);
+            ethernetnode = fdt_subnode_offset(Fdt, node,EthName[port]);
+            if(!EFI_ERROR(GetMacStatus))
+            {
+
+                if (ethernetnode < 0)
+                {
+                    DEBUG ((EFI_D_WARN, "Can not find ethernet@%d node\n",port));
+                    DEBUG ((EFI_D_WARN, "Suppose port %d is not enabled.\n", port));
+                    continue;
+                }
+                m_prop = fdt_get_property_w(Fdt, ethernetnode, "local-mac-address", &m_oldlen);
+                if(m_prop)
+                {
+                    Error = fdt_delprop(Fdt, ethernetnode, "local-mac-address");
+                    if (Error)
+                    {
+                        DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop() Local-mac-address: %a\n", fdt_strerror (Error)));
+                        Status = EFI_INVALID_PARAMETER;
+                    }
+                    Error = fdt_setprop(Fdt, ethernetnode, "local-mac-address",gMacAddress,sizeof(MAC_ADDRESS));
+                    if (Error)
+                    {
+                        DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop():local-mac-address %a\n", fdt_strerror (Error)));
+                        Status = EFI_INVALID_PARAMETER;
+                    }
+                }
+            }
+        }
+    }
+    return Status;
+}
+
+STATIC
+EFI_STATUS
+UpdateRefClk (IN VOID* Fdt)
+{
+  INTN                node;
+  INTN                Error;
+  struct              fdt_property *m_prop;
+  int                 m_oldlen;
+  UINTN               ArchTimerFreq = 0;
+  UINT32              Data;
+  CONST CHAR8         *Property = "clock-frequency";
+
+  ArmArchTimerReadReg (CntFrq, &ArchTimerFreq);
+  if (!ArchTimerFreq) {
+    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Get timer frequency failed!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  node = fdt_subnode_offset(Fdt, 0, "soc");
+  if (node < 0) {
+    DEBUG ((DEBUG_ERROR, "can not find soc node\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  node = fdt_subnode_offset(Fdt, node, "refclk");
+  if (node < 0) {
+    DEBUG ((DEBUG_ERROR, "can not find refclk node\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  m_prop = fdt_get_property_w(Fdt, node, Property, &m_oldlen);
+  if(!m_prop) {
+    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Can't find property %a\n", __FUNCTION__, __LINE__, Property));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Error = fdt_delprop(Fdt, node, Property);
+  if (Error) {
+    DEBUG ((DEBUG_ERROR, "ERROR: fdt_delprop() %a: %a\n", Property, fdt_strerror (Error)));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // UINT32 is enough for refclk data length
+  Data = (UINT32) ArchTimerFreq;
+  Data = cpu_to_fdt32 (Data);
+  Error = fdt_setprop(Fdt, node, Property, &Data, sizeof(Data));
+  if (Error) {
+    DEBUG ((DEBUG_ERROR, "ERROR:fdt_setprop() %a: %a\n", Property, fdt_strerror (Error)));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  DEBUG ((DEBUG_INFO, "Update refclk successfully.\n"));
+  return EFI_SUCCESS;
+}
+
+INTN
+GetMemoryNode(VOID* Fdt)
+{
+    INTN                node;
+    int                 m_oldlen;
+    struct              fdt_property *m_prop;
+    INTN                Error = 0;
+
+
+    node = fdt_subnode_offset(Fdt, 0, "memory");
+    if (node < 0)
+    {
+        // Create the memory node
+        node = fdt_add_subnode(Fdt, 0, "memory");
+
+        if(node < 0)
+        {
+          DEBUG((EFI_D_ERROR, "[%a]:[%dL] fdt add subnode error\n", __FUNCTION__, __LINE__));
+
+          return node;
+        }
+
+    }
+    //find the memory node property
+    m_prop = fdt_get_property_w(Fdt, node, "memory", &m_oldlen);
+    if(m_prop)
+    {
+        Error = fdt_delprop(Fdt, node, "reg");
+
+        if (Error)
+        {
+            DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop(): %a\n", fdt_strerror (Error)));
+            node = -1;
+            return node;
+        }
+    }
+
+    return node;
+}
+
+
+EFI_STATUS UpdateMemoryNode(VOID* Fdt)
+{
+    INTN                Error = 0;
+    EFI_STATUS          Status = EFI_SUCCESS;
+    UINT32              Index = 0;
+    UINT32              MemIndex;
+    INTN                node;
+    EFI_MEMORY_DESCRIPTOR *MemoryMap;
+    EFI_MEMORY_DESCRIPTOR *MemoryMapPtr;
+    EFI_MEMORY_DESCRIPTOR *MemoryMapPtrCurrent;
+    UINTN                 MemoryMapSize;
+    UINTN                 Pages0 = 0;
+    UINTN                 Pages1 = 0;
+    UINTN                 MapKey;
+    UINTN                 DescriptorSize;
+    UINT32                DescriptorVersion;
+    PHY_MEM_REGION        *mRegion;
+    UINTN                 MemoryMapLastEndAddress ;
+    UINTN                 MemoryMapcontinuousStartAddress ;
+    UINTN                 MemoryMapCurrentStartAddress;
+    BOOLEAN               FindMemoryRegionFlag = FALSE;
+
+    node = GetMemoryNode(Fdt);
+    if (node < 0)
+    {
+        DEBUG((EFI_D_ERROR, "Can not find memory node\n"));
+        return EFI_NOT_FOUND;
+    }
+    MemoryMap = NULL;
+    MemoryMapSize = 0;
+    MemIndex = 0;
+
+    Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+    if (Status == EFI_BUFFER_TOO_SMALL)
+    {
+        // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive
+        // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size.
+        Pages0 = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
+        MemoryMap = AllocatePages (Pages0);
+        if (MemoryMap == NULL)
+        {
+            Status = EFI_OUT_OF_RESOURCES;
+            return Status;
+        }
+        Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+
+        if (EFI_ERROR(Status))
+        {
+            DEBUG ((EFI_D_ERROR, "FdtUpdateLib GetMemoryMap Error\n"));
+            FreePages (MemoryMap, Pages0);
+            return Status;
+        }
+    }
+    else
+    {
+        DEBUG ((EFI_D_ERROR, "FdtUpdateLib GetmemoryMap Status: %r\n",Status));
+        return EFI_ABORTED;
+    }
+
+    mRegion = NULL;
+    Pages1 = EFI_SIZE_TO_PAGES (sizeof(PHY_MEM_REGION) *( MemoryMapSize / DescriptorSize));
+
+    mRegion = (PHY_MEM_REGION*)AllocatePool(Pages1);
+    if (mRegion == NULL)
+    {
+      Status = EFI_OUT_OF_RESOURCES;
+      FreePages (MemoryMap, Pages0);
+      return Status;
+    }
+
+
+    MemoryMapPtr = MemoryMap;
+    MemoryMapPtrCurrent = MemoryMapPtr;
+    MemoryMapLastEndAddress = 0;
+    MemoryMapcontinuousStartAddress = 0;
+    MemoryMapCurrentStartAddress = 0;
+    for (Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++)
+    {
+        MemoryMapPtrCurrent = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + Index*DescriptorSize);
+        MemoryMapCurrentStartAddress = (UINTN)MemoryMapPtrCurrent->PhysicalStart;
+
+        if (!IsMemMapRegion ((EFI_MEMORY_TYPE)MemoryMapPtrCurrent->Type))
+        {
+            continue;
+        }
+        else
+        {
+            FindMemoryRegionFlag = TRUE;
+            if(MemoryMapCurrentStartAddress != MemoryMapLastEndAddress)
+            {
+                mRegion[MemIndex].BaseHigh= cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32);
+                mRegion[MemIndex].BaseLow=cpu_to_fdt32(MemoryMapcontinuousStartAddress);
+                mRegion[MemIndex].LengthHigh= cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32);
+                mRegion[MemIndex].LengthLow=cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress);
+                MemIndex+=1;
+                MemoryMapcontinuousStartAddress=MemoryMapCurrentStartAddress;
+            }
+        }
+        MemoryMapLastEndAddress = (UINTN)(MemoryMapPtrCurrent->PhysicalStart + MemoryMapPtrCurrent->NumberOfPages * EFI_PAGE_SIZE);
+    }
+    if (FindMemoryRegionFlag)
+    {
+        mRegion[MemIndex].BaseHigh = cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32);
+        mRegion[MemIndex].BaseLow = cpu_to_fdt32(MemoryMapcontinuousStartAddress);
+        mRegion[MemIndex].LengthHigh = cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32);
+        mRegion[MemIndex].LengthLow = cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress);
+    }
+
+    Error = fdt_setprop(Fdt, node, "reg",mRegion,sizeof(PHY_MEM_REGION) *(MemIndex+1));
+
+    FreePool (mRegion);
+    FreePages (MemoryMap, Pages0);
+    if (Error)
+    {
+        DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop(): %a\n", fdt_strerror (Error)));
+        Status = EFI_INVALID_PARAMETER;
+        return Status;
+    }
+
+  return Status;
+}
+
+
+EFI_STATUS
+UpdateNumaNode(VOID* Fdt)
+{
+    //TODO: Need to update numa node
+    return EFI_SUCCESS;
+}
+/*
+ * Entry point for fdtupdate lib.
+ */
+
+EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr)
+{
+    INTN                Error;
+    VOID*               Fdt;
+    UINT32              Size;
+    UINTN               NewFdtBlobSize;
+    UINTN               NewFdtBlobBase;
+    EFI_STATUS          Status = EFI_SUCCESS;
+    EFI_STATUS          UpdateNumaStatus = EFI_SUCCESS;
+
+
+    Error = fdt_check_header ((VOID*)(FdtFileAddr));
+    if (0 != Error)
+    {
+        DEBUG ((EFI_D_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error)));
+        return EFI_INVALID_PARAMETER;
+    }
+
+    Size = (UINTN)fdt_totalsize ((VOID*)(UINTN)(FdtFileAddr));
+    NewFdtBlobSize = Size + ADD_FILE_LENGTH;
+    Fdt = (VOID*)(UINTN)FdtFileAddr;
+
+    Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase);
+    if (EFI_ERROR (Status))
+    {
+        return EFI_OUT_OF_RESOURCES;
+    }
+
+
+    Error = fdt_open_into(Fdt,(VOID*)(UINTN)(NewFdtBlobBase), (NewFdtBlobSize));
+    if (Error) {
+        DEBUG ((EFI_D_ERROR, "ERROR:fdt_open_into(): %a\n", fdt_strerror (Error)));
+        Status = EFI_INVALID_PARAMETER;
+        goto EXIT;
+    }
+
+    Fdt = (VOID*)(UINTN)NewFdtBlobBase;
+    Status = DelPhyhandleUpdateMacAddress(Fdt);
+    if (EFI_ERROR (Status))
+    {
+        DEBUG ((EFI_D_ERROR, "DelPhyhandleUpdateMacAddress fail:\n"));
+        Status = EFI_SUCCESS;
+    }
+
+    Status =  UpdateRefClk (Fdt);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "UpdateiRefClk fail.\n"));
+    }
+
+    Status = UpdateMemoryNode(Fdt);
+    if (EFI_ERROR (Status))
+    {
+        DEBUG ((EFI_D_ERROR, "UpdateMemoryNode Error\n"));
+        goto EXIT;
+    }
+
+    UpdateNumaStatus = UpdateNumaNode(Fdt);
+    if (EFI_ERROR (UpdateNumaStatus))
+    {
+        DEBUG ((EFI_D_ERROR, "Update NumaNode fail\n"));
+    }
+
+    gBS->CopyMem(((VOID*)(UINTN)(FdtFileAddr)),((VOID*)(UINTN)(NewFdtBlobBase)),NewFdtBlobSize);
+
+EXIT:
+    gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize));
+
+    return Status;
+
+
+
+}
diff --git a/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf
new file mode 100755
index 0000000..9569b91
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = FdtUpdateLib
+  FILE_GUID                      = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = FdtUpdateLib
+
+
+[Sources.common]
+  FdtUpdateLib.c
+
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  ArmLib
+ FdtLib
+ PlatformSysCtrlLib
+ OemMiscLib
+
+[Protocols]
+ gHisiBoardNicProtocolGuid
+
+[Guids]
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdNumaEnable
+
+
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
new file mode 100644
index 0000000..66d6289
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
@@ -0,0 +1,197 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+
+#include <PlatformArch.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Library/I2CLib.h>
+#include <Library/HiiLib.h>
+
+I2C_DEVICE gDS3231RtcDevice = {
+    .Socket = 0,
+    .Port = 6,
+    .DeviceType = DEVICE_TYPE_SPD,
+    .SlaveDeviceAddress = 0x68
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
+{
+    {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
+{
+    {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_PARAM gSerdesParam = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Sas1X4,
+  .Hilink6Mode = 0x0,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParam0 = {
+  .Hilink0Mode = EmHilink0Hccs1X8Width16,
+  .Hilink1Mode = EmHilink1Hccs0X8Width16,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Sas1X4,
+  .Hilink6Mode = 0x0,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParam1 = {
+  .Hilink0Mode = EmHilink0Hccs1X8Width16,
+  .Hilink1Mode = EmHilink1Hccs0X8Width16,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Pcie3X4,
+  .Hilink6Mode = 0xF,
+  .UseSsc      = 0,
+};
+
+EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId)
+{
+  if (ParamA == NULL) {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA));
+  return EFI_SUCCESS;
+}
+
+
+VOID OemPcieResetAndOffReset(void)
+  {
+    return;
+  }
+
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
+    // PCIe0 Slot 1
+    {
+        {                                                     // Hdr
+            EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,
+            0,                                                    // Length,
+            0                                                     // Handle
+        },
+        1,                                                    // SlotDesignation
+        SlotTypePciExpressX8,     // SlotType
+        SlotDataBusWidth8X,       // SlotDataBusWidth
+        SlotUsageAvailable,       // SlotUsage
+        SlotLengthOther,          // SlotLength
+        0x0001,                   // SlotId
+        {                         // SlotCharacteristics1
+            0,                      // CharacteristicsUnknown  :1;
+            0,                      // Provides50Volts         :1;
+            0,                      // Provides33Volts         :1;
+            0,                      // SharedSlot              :1;
+            0,                      // PcCard16Supported       :1;
+            0,                      // CardBusSupported        :1;
+            0,                      // ZoomVideoSupported      :1;
+            0                       // ModemRingResumeSupported:1;
+        },
+        {                         // SlotCharacteristics2
+            0,                      // PmeSignalSupported      :1;
+            0,                      // HotPlugDevicesSupported  :1;
+            0,                      // SmbusSignalSupported    :1;
+            0                       // Reserved                :5;
+        },
+        0x00,                     // SegmentGroupNum
+        0x00,                     // BusNum
+        0                         // DevFuncNum
+    },
+
+    // PCIe0 Slot 4
+    {
+        {                                                     // Hdr
+            EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,
+            0,                                                    // Length,
+            0                                                     // Handle
+        },
+        1,                                                    // SlotDesignation
+        SlotTypePciExpressX8,     // SlotType
+        SlotDataBusWidth8X,       // SlotDataBusWidth
+        SlotUsageAvailable,       // SlotUsage
+        SlotLengthOther,          // SlotLength
+        0x0004,                   // SlotId
+        {                         // SlotCharacteristics1
+            0,                      // CharacteristicsUnknown  :1;
+            0,                      // Provides50Volts         :1;
+            0,                      // Provides33Volts         :1;
+            0,                      // SharedSlot              :1;
+            0,                      // PcCard16Supported       :1;
+            0,                      // CardBusSupported        :1;
+            0,                      // ZoomVideoSupported      :1;
+            0                       // ModemRingResumeSupported:1;
+        },
+        {                         // SlotCharacteristics2
+            0,                      // PmeSignalSupported      :1;
+            0,                      // HotPlugDevicesSupported  :1;
+            0,                      // SmbusSignalSupported    :1;
+            0                       // Reserved                :5;
+        },
+        0x00,                     // SegmentGroupNum
+        0x00,                     // BusNum
+        0                         // DevFuncNum
+    }
+};
+
+
+UINT8 OemGetPcieSlotNumber ()
+{
+    return  sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
+
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+  )
+{
+    return HiiAddPackages (
+                            &gEfiCallerIdGuid,
+                            NULL,
+                            OemMiscLib2PStrings,
+                            NULL,
+                            NULL
+                            );
+}
+
+
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni
new file mode 100644
index 0000000..38def40
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
new file mode 100644
index 0000000..fa1039b
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
@@ -0,0 +1,141 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/OemMiscLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/LpcLib.h>
+REPORT_PCIEDIDVID2BMC  PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+      {67,0,0,0},
+      {225,0,0,3},
+      {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+      {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+
+// Right now we only support 1P
+BOOLEAN OemIsSocketPresent (UINTN Socket)
+{
+  if (0 == Socket)
+  {
+    return TRUE;
+  }
+
+  if(1 == Socket)
+  {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+
+UINTN OemGetSocketNumber (VOID)
+{
+
+    if(!OemIsMpBoot())
+    {
+        return 1;
+    }
+
+    return 2;
+
+}
+
+
+UINTN OemGetDdrChannel (VOID)
+{
+    return 4;
+}
+
+
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel)
+{
+    return 2;
+}
+
+
+// Nothing to do for EVB
+VOID OemPostEndIndicator (VOID)
+{
+
+     DEBUG((EFI_D_ERROR,"M3 release reset CONFIG........."));
+
+     MmioWrite32(0xd0002180, 0x3);
+     MmioWrite32(0xd0002194, 0xa4);
+     MmioWrite32(0xd0000a54, 0x1);
+
+     MicroSecondDelay(10000);
+
+     MmioWrite32(0xd0002108, 0x1);
+     MmioWrite32(0xd0002114, 0x1);
+     MmioWrite32(0xd0002120, 0x1);
+     MmioWrite32(0xd0003108, 0x1);
+
+     MicroSecondDelay(500000);
+     DEBUG((EFI_D_ERROR,"Done\n"));
+
+}
+
+
+
+VOID CoreSelectBoot(VOID)
+{
+    if (!PcdGet64 (PcdTrustedFirmwareEnable))
+    {
+        StartupAp ();
+    }
+
+    return;
+}
+
+BOOLEAN OemIsMpBoot()
+{
+    UINT32 Tmp;
+
+    Tmp = MmioRead32(0x602E0050);
+    if ( ((Tmp >> 10) & 0xF) == 0x3)
+        return TRUE;
+    else
+        return FALSE;
+}
+
+VOID OemLpcInit(VOID)
+{
+    LpcInit();
+    return;
+}
+
+UINT32 OemIsWarmBoot(VOID)
+{
+    return 0;
+}
+
+VOID OemBiosSwitch(UINT32 Master)
+{
+    (VOID)Master;
+    return;
+}
+
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID)
+{
+    return TRUE;
+}
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
new file mode 100644
index 0000000..eb384db
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
@@ -0,0 +1,54 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemMiscLib2P
+  FILE_GUID                      = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemMiscLib
+
+[Sources.common]
+  BoardFeature2PHi1610.c
+  OemMiscLib2PHi1610.c
+  BoardFeature2PHi1610Strings.uni
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  TimerLib
+
+[BuildOptions]
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid   ## SOMETIMES_CONSUMES
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+
+[FixedPcd.common]
+
+[Guids]
+
+[Protocols]
+
diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
new file mode 100644
index 0000000..c58118f
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
@@ -0,0 +1,156 @@
+/** @file
+
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000},
+                                        {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000}};
+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000},
+                                      {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}};
+UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000},
+                                  {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}};
+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040},
+                                  {0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}};
+
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ {// HostBridge 0
+  /* Port 0 */
+  {
+      PCI_HB0RB0_ECAM_BASE, //ecam
+      0,  //BusBase
+      31, //BusLimit
+      PCI_HB0RB0_PCIREGION_BASE, //Membase
+      PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
+      PCI_HB0RB0_IO_BASE,  //IoBase
+      (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB0_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB0_PCI_BASE),  //RbPciBar
+      PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase
+      PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit
+
+  },
+  /* Port 1 */
+  {
+      PCI_HB0RB1_ECAM_BASE,//ecam
+      224,  //BusBase
+      254, //BusLimit
+      PCI_HB0RB1_PCIREGION_BASE, //Membase
+      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB1_IO_BASE),  //IoBase
+      (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB1_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB1_PCI_BASE),  //RbPciBar
+      PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase
+      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit
+  },
+  /* Port 2 */
+  {
+      PCI_HB0RB2_ECAM_BASE,
+      128,  //BusBase
+      159, //BusLimit
+      PCI_HB0RB2_PCIREGION_BASE ,//MemBase
+      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB2_IO_BASE),  //IOBase
+      (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB2_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB2_PCI_BASE),  //RbPciBar
+      PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase
+      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB0RB3_ECAM_BASE,
+      96,  //BusBase
+      127, //BusLimit
+      (PCI_HB0RB3_ECAM_BASE),  //MemBase
+      (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB0RB3_PCI_BASE),  //RbPciBar
+      0,
+      0
+  }
+ },
+{// HostBridge 1
+  /* Port 0 */
+  {
+      PCI_HB1RB0_ECAM_BASE,
+      128,  //BusBase
+      159, //BusLimit
+      (PCI_HB1RB0_ECAM_BASE),  //MemBase
+      (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB0_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+  /* Port 1 */
+  {
+      PCI_HB1RB1_ECAM_BASE,
+      160,  //BusBase
+      191, //BusLimit
+      (PCI_HB1RB1_ECAM_BASE),  //MemBase
+      (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB1_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+  /* Port 2 */
+  {
+      PCI_HB1RB2_ECAM_BASE,
+      192,  //BusBase
+      223, //BusLimit
+      (PCI_HB1RB2_ECAM_BASE),  //MemBase
+      (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB2_PCI_BASE),  //RbPciBar
+      0,
+      0
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB1RB3_ECAM_BASE,
+      224,  //BusBase
+      255, //BusLimit
+      (PCI_HB1RB3_ECAM_BASE),  //MemBase
+      (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
+      (0), //IoBase
+      (0),  //IoLimit
+      0,
+      0,
+      (PCI_HB1RB3_PCI_BASE),  //RbPciBar
+      0,
+      0
+  }
+ }
+};
+
diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf
new file mode 100644
index 0000000..c9ce45f
--- /dev/null
+++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf
@@ -0,0 +1,182 @@
+## @file
+#
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformPciLib
+  FILE_GUID                      = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  PlatformPciLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PciHb0Rb0Base
+  gHisiTokenSpaceGuid.PciHb0Rb1Base
+  gHisiTokenSpaceGuid.PciHb0Rb2Base
+  gHisiTokenSpaceGuid.PciHb0Rb3Base
+  gHisiTokenSpaceGuid.PciHb0Rb4Base
+  gHisiTokenSpaceGuid.PciHb0Rb5Base
+  gHisiTokenSpaceGuid.PciHb0Rb6Base
+  gHisiTokenSpaceGuid.PciHb0Rb7Base
+  gHisiTokenSpaceGuid.PciHb1Rb0Base
+  gHisiTokenSpaceGuid.PciHb1Rb1Base
+  gHisiTokenSpaceGuid.PciHb1Rb2Base
+  gHisiTokenSpaceGuid.PciHb1Rb3Base
+  gHisiTokenSpaceGuid.PciHb1Rb4Base
+  gHisiTokenSpaceGuid.PciHb1Rb5Base
+  gHisiTokenSpaceGuid.PciHb1Rb6Base
+  gHisiTokenSpaceGuid.PciHb1Rb7Base
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc
new file mode 100644
index 0000000..5645b15
--- /dev/null
+++ b/Platforms/Hisilicon/D05/D05.dsc
@@ -0,0 +1,679 @@
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = D05
+  PLATFORM_GUID                  = D0D445F1-B2CA-4101-9986-1B23525CBEA6
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
+  DEFINE EDK2_SKIP_PEICORE=0
+  DEFINE INCLUDE_TFTP_COMMAND=1
+  DEFINE NETWORK_IP6_ENABLE      = FALSE
+  DEFINE HTTP_BOOT_ENABLE        = FALSE
+
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
+  ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+  NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+  LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+
+
+  I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+  IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
+
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+  OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+!endif
+
+!if $(HTTP_BOOT_ENABLE) == TRUE
+  HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+
+!ifdef $(FDT_ENABLE)
+  #FDTUpdateLib
+  FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
+
+  CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+
+  SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
+
+  EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
+  #D05 RTC hardware is same as D03
+  RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
+
+  OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
+  OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
+  PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+[LibraryClasses.common.SEC]
+  ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+[BuildOptions]
+  GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+
+!if $(EDK2_SKIP_PEICORE) == 1
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+  gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+
+  # Stacks for MPCores in Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
+
+  # Stacks for MPCores in Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
+
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+
+
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
+
+
+  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
+
+
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+  gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
+
+
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
+                                                # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
+  ## enable all the pcie device, because it is ok for bios
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
+                                                # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
+
+  ## SP805 Watchdog - Motherboard Watchdog
+  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
+
+  ## Serial Terminal
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+  # use the TTY terminal type (which has a working backspace)
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+
+  gHisiTokenSpaceGuid.PcdIsMPBoot|1
+  gHisiTokenSpaceGuid.PcdSocketMask|0x3
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.12 Release"
+
+  gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
+
+  gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
+
+  gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
+  gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
+  gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
+  gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
+
+  gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"
+
+
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
+
+
+  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+  #
+  # ARM Architectual Timer Frequency
+  #
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
+  gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
+
+  gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
+
+  gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
+  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
+
+
+  gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
+
+
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
+
+
+  gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
+
+  ## DTB address at spi flash
+  gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000
+
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
+
+  gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
+
+  gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
+
+  gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
+
+  gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
+  gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
+
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
+  gHisiTokenSpaceGuid.PcdNumaEnable|1
+  gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
+
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
+
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
+  gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
+  gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
+  gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
+  gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
+  gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
+  gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
+  gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
+  gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
+  gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
+  gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
+  gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
+  gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
+  gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
+  gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
+  gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+  #
+  # SEC
+  #
+
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
+
+  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
+  ArmPkg/Drivers/CpuPei/CpuPei.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
+
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug.
+  #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  }
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+    <LibraryClasses>
+      CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+  #
+  #ACPI
+  #
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # Usb Support
+  #
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
+
+  #
+  #network
+  #
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
+
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  NetworkPkg/TcpDxe/TcpDxe.inf
+  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
+  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
+  NetworkPkg/DnsDxe/DnsDxe.inf
+  NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
+  NetworkPkg/HttpDxe/HttpDxe.inf
+  NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
+
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+
+  OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf {
+    <LibraryClasses>
+      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  }
+!endif #$(FDT_ENABLE)
+
+  #PCIe Support
+  OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
+    <LibraryClasses>
+      NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
+  }
+  OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <LibraryClasses>
+      NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
+  }
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+
+
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+  #
+  # Memory test
+  #
+  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+      NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
+!endif
+
+!ifdef $(INCLUDE_DP)
+      NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+!endif #$(INCLUDE_DP)
+!ifdef $(INCLUDE_TFTP_COMMAND)
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf
new file mode 100644
index 0000000..bdfb211
--- /dev/null
+++ b/Platforms/Hisilicon/D05/D05.fdf
@@ -0,0 +1,366 @@
+#
+#  Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[DEFINES]
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.D05]
+
+BaseAddress   = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+
+Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00010000
+NumBlocks     = 0x30
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
+
+0x00040000|0x00240000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+0x00280000|0x00020000
+gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin
+0x002A0000|0x00020000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin
+
+0x002D0000|0x0000E000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x20000
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
+  0xB8, 0xdF, 0x00, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002DE000|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
+  0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002E0000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+0x002F0000|0x00010000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatBinPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+
+  #
+  # Usb Support
+  #
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+  #
+  #ACPI
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  #Network
+  #
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
+
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  INF NetworkPkg/TcpDxe/TcpDxe.inf
+  INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
+  INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
+  INF NetworkPkg/DnsDxe/DnsDxe.inf
+  INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
+  INF NetworkPkg/HttpDxe/HttpDxe.inf
+  INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
+
+!ifdef $(FDT_ENABLE)
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
+
+  #
+  # PCI Support
+  #
+  INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
+  # VGA Driver
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
+  INF  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
+
+  #
+  # Build Shell from latest source code instead of prebuilt binary
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI PEI {
+    INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  }
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+  INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
+
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
+
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c
new file mode 100644
index 0000000..76a055c
--- /dev/null
+++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c
@@ -0,0 +1,64 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <PiPei.h>
+#include <PlatformArch.h>
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformSysCtrlLib.h>
+
+VOID
+QResetAp (
+  VOID
+  )
+{
+  MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
+  (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
+
+  if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
+    StartupAp();
+  }
+}
+
+
+EFI_STATUS
+EFIAPI
+EarlyConfigEntry (
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+  DEBUG((DEBUG_INFO,"SMMU CONFIG........."));
+  (VOID)SmmuConfigForBios();
+  DEBUG((DEBUG_INFO,"Done\n"));
+
+  DEBUG((DEBUG_INFO,"AP CONFIG........."));
+  (VOID)QResetAp();
+  DEBUG((DEBUG_INFO,"Done\n"));
+
+  DEBUG((DEBUG_INFO,"MN CONFIG........."));
+  (VOID)MN_CONFIG();
+  DEBUG((DEBUG_INFO,"Done\n"));
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
new file mode 100644
index 0000000..5fdf555
--- /dev/null
+++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
@@ -0,0 +1,53 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = EarlyConfigPeimD05
+  FILE_GUID                      = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = EarlyConfigEntry
+
+[Sources.common]
+  EarlyConfigPeimD05.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  CacheMaintenanceLib
+  DebugLib
+  IoLib
+  PcdLib
+  PeimEntryPoint
+  PlatformSysCtrlLib
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdMailBoxAddress
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
+[Depex]
+## As we will clean mailbox in this module, need to wait memory init complete
+  gEfiPeiMemoryDiscoveredPpiGuid
+
+[BuildOptions]
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
new file mode 100644
index 0000000..15a509b
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
@@ -0,0 +1,225 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PlatformArch.h>
+#include <Uefi.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HiiLib.h>
+#include <Library/I2CLib.h>
+#include <Library/IoLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Protocol/Smbios.h>
+
+
+I2C_DEVICE gDS3231RtcDevice = {
+  .Socket = 0,
+  .Port = 4,
+  .DeviceType = DEVICE_TYPE_SPD,
+  .SlaveDeviceAddress = 0x68
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = {
+  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = {
+  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_PARAM gSerdesParamNA = {
+  .Hilink0Mode = EmHilink0Hccs1X8Width16,
+  .Hilink1Mode = EmHilink1Hccs0X8Width16,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Sas1X4,
+  .Hilink6Mode = 0x0,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamNB = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Sas0X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
+  .Hilink6Mode = 0xF,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamS1NA = {
+  .Hilink0Mode = EmHilink0Hccs1X8Width16,
+  .Hilink1Mode = EmHilink1Hccs0X8Width16,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Sas1X4,
+  .Hilink6Mode = 0x0,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamS1NB = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Sas0X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
+  .Hilink6Mode = 0xF,
+  .UseSsc      = 0,
+};
+
+
+EFI_STATUS
+OemGetSerdesParam (
+ OUT SERDES_PARAM *ParamA,
+ OUT SERDES_PARAM *ParamB,
+ IN  UINT32 SocketId
+ )
+{
+  if (ParamA == NULL || ParamB == NULL) {
+    DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (SocketId == 0) {
+    (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
+    (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
+  } else {
+    (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
+    (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
+  }
+
+  return EFI_SUCCESS;
+}
+
+VOID
+OemPcieResetAndOffReset (
+  VOID
+  )
+{
+  return;
+}
+
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
+  // PCIe0 Slot 1
+  {
+    {                                                     // Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                       // Type,
+      0,                                                  // Length,
+      0                                                   // Handle
+    },
+    1,                                                    // SlotDesignation
+    SlotTypePciExpressX8,     // SlotType
+    SlotDataBusWidth8X,       // SlotDataBusWidth
+    SlotUsageAvailable,       // SlotUsage
+    SlotLengthOther,          // SlotLength
+    0x0001,                   // SlotId
+    {                         // SlotCharacteristics1
+      0,                      // CharacteristicsUnknown  :1;
+      0,                      // Provides50Volts         :1;
+      0,                      // Provides33Volts         :1;
+      0,                      // SharedSlot              :1;
+      0,                      // PcCard16Supported       :1;
+      0,                      // CardBusSupported        :1;
+      0,                      // ZoomVideoSupported      :1;
+      0                       // ModemRingResumeSupported:1;
+    },
+    {                         // SlotCharacteristics2
+      0,                      // PmeSignalSupported      :1;
+      0,                      // HotPlugDevicesSupported  :1;
+      0,                      // SmbusSignalSupported    :1;
+      0                       // Reserved                :5;
+    },
+    0x00,                     // SegmentGroupNum
+    0x00,                     // BusNum
+    0                         // DevFuncNum
+  },
+
+  // PCIe0 Slot 4
+  {
+    {                                                  // Hdr
+      EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                    // Type,
+      0,                                               // Length,
+      0                                                // Handle
+    },
+    1,                                                 // SlotDesignation
+    SlotTypePciExpressX8,     // SlotType
+    SlotDataBusWidth8X,       // SlotDataBusWidth
+    SlotUsageAvailable,       // SlotUsage
+    SlotLengthOther,          // SlotLength
+    0x0004,                   // SlotId
+    {                         // SlotCharacteristics1
+      0,                      // CharacteristicsUnknown  :1;
+      0,                      // Provides50Volts         :1;
+      0,                      // Provides33Volts         :1;
+      0,                      // SharedSlot              :1;
+      0,                      // PcCard16Supported       :1;
+      0,                      // CardBusSupported        :1;
+      0,                      // ZoomVideoSupported      :1;
+      0                       // ModemRingResumeSupported:1;
+    },
+    {                         // SlotCharacteristics2
+      0,                      // PmeSignalSupported      :1;
+      0,                      // HotPlugDevicesSupported  :1;
+      0,                      // SmbusSignalSupported    :1;
+      0                       // Reserved                :5;
+    },
+    0x00,                     // SegmentGroupNum
+    0x00,                     // BusNum
+    0                         // DevFuncNum
+  }
+};
+
+
+UINT8
+OemGetPcieSlotNumber (
+  VOID
+  )
+{
+  return  sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
+
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+  )
+{
+  return HiiAddPackages (
+                        &gEfiCallerIdGuid,
+                        NULL,
+                        OemMiscLibHi1616EvbStrings,
+                        NULL,
+                        NULL
+                        );
+}
+
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni
new file mode 100644
index 0000000..9f5be02
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni
@@ -0,0 +1,56 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// --*/
+
+/=#
+
+#langdef en-US "English"
+
+//
+// Begin English Language Strings
+//
+#string STR_MEMORY_SUBCLASS_UNKNOWN    #language en-US  "Unknown"
+
+//
+// DIMM Device Locator strings
+
+#string STR_LEMON_C10_DIMM_000     #language en-US "J5"
+#string STR_LEMON_C10_DIMM_001     #language en-US "J6"
+#string STR_LEMON_C10_DIMM_002     #language en-US "J7"
+#string STR_LEMON_C10_DIMM_010     #language en-US "J8"
+#string STR_LEMON_C10_DIMM_011     #language en-US "J9"
+#string STR_LEMON_C10_DIMM_012     #language en-US "J10"
+#string STR_LEMON_C10_DIMM_020     #language en-US "J11"
+#string STR_LEMON_C10_DIMM_021     #language en-US "J12"
+#string STR_LEMON_C10_DIMM_022     #language en-US "J13"
+#string STR_LEMON_C10_DIMM_030     #language en-US "J14"
+#string STR_LEMON_C10_DIMM_031     #language en-US "J15"
+#string STR_LEMON_C10_DIMM_032     #language en-US "J16"
+#string STR_LEMON_C10_DIMM_100     #language en-US "J17"
+#string STR_LEMON_C10_DIMM_101     #language en-US "J18"
+#string STR_LEMON_C10_DIMM_102     #language en-US "J19"
+#string STR_LEMON_C10_DIMM_110     #language en-US "J20"
+#string STR_LEMON_C10_DIMM_111     #language en-US "J21"
+#string STR_LEMON_C10_DIMM_112     #language en-US "J22"
+#string STR_LEMON_C10_DIMM_120     #language en-US "J23"
+#string STR_LEMON_C10_DIMM_121     #language en-US "J24"
+#string STR_LEMON_C10_DIMM_122     #language en-US "J25"
+#string STR_LEMON_C10_DIMM_130     #language en-US "J26"
+#string STR_LEMON_C10_DIMM_131     #language en-US "J27"
+#string STR_LEMON_C10_DIMM_132     #language en-US "J28"
+
+//
+// End English Language Strings
+//
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
new file mode 100644
index 0000000..b17eead
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
@@ -0,0 +1,107 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PlatformArch.h>
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/LpcLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/TimerLib.h>
+
+#define OEM_SINGLE_SOCKET 1
+#define OEM_DUAL_SOCKET 2
+
+REPORT_PCIEDIDVID2BMC  PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+  {67,0,0,0},
+  {225,0,0,3},
+  {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+  {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+
+
+BOOLEAN OemIsSocketPresent (UINTN Socket)
+{
+  if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+
+UINTN OemGetSocketNumber (VOID)
+{
+
+  if(!OemIsMpBoot()) {
+    return OEM_SINGLE_SOCKET;
+  }
+
+  return OEM_DUAL_SOCKET;
+}
+
+
+UINTN OemGetDdrChannel (VOID)
+{
+  return 4;
+}
+
+
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel)
+{
+  return 2;
+}
+
+VOID CoreSelectBoot(VOID)
+{
+  if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
+      StartupAp ();
+  }
+
+  return;
+}
+
+BOOLEAN OemIsMpBoot()
+{
+  return PcdGet32(PcdIsMPBoot);
+}
+
+VOID OemLpcInit(VOID)
+{
+  LpcInit();
+  return;
+}
+
+UINT32 OemIsWarmBoot(VOID)
+{
+  return 0;
+}
+
+VOID OemBiosSwitch(UINT32 Master)
+{
+  (VOID)Master;
+  return;
+}
+
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID)
+{
+  return TRUE;
+}
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
new file mode 100644
index 0000000..b2f41b8
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
@@ -0,0 +1,55 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = OemMiscLibHi1616Evb
+  FILE_GUID                      = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemMiscLib
+
+[Sources.common]
+  BoardFeatureD05.c
+  BoardFeatureD05Strings.uni
+  OemMiscLibD05.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  TimerLib
+
+[BuildOptions]
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid   ## SOMETIMES_CONSUMES
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+  gHisiTokenSpaceGuid.PcdIsMPBoot
+  gHisiTokenSpaceGuid.PcdSocketMask
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
+[FixedPcd.common]
+
+[Guids]
+
+[Protocols]
+
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
new file mode 100644
index 0000000..57283a1
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
@@ -0,0 +1,279 @@
+/** @file
+
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
+                                        {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};
+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
+                                         {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};
+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
+                                 {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};
+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
+                           {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};
+
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ {// HostBridge 0
+  /* Port 0 */
+  {
+      PCI_HB0RB0_ECAM_BASE, //ecam
+      0x80,  //BusBase
+      0x87, //BusLimit
+      PCI_HB0RB0_PCIREGION_BASE, //Membase
+      PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
+      PCI_HB0RB0_IO_BASE,  //IoBase
+      (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB0_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB0_PCI_BASE),//RbPciBar
+      PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 1 */
+  {
+      PCI_HB0RB1_ECAM_BASE,//ecam
+      0x90,  //BusBase
+      0x97, //BusLimit
+      PCI_HB0RB1_PCIREGION_BASE, //Membase
+      PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB1_IO_BASE),  //IoBase
+      (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB1_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB1_PCI_BASE),  //RbPciBar
+      PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 2 */
+  {
+      PCI_HB0RB2_ECAM_BASE,
+      0x80,  //BusBase
+      0x87, //BusLimit
+      PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase
+      PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB2_IO_BASE),  //IOBase
+      (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB2_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB2_PCI_BASE),  //RbPciBar
+      PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB0RB3_ECAM_BASE,
+      0xb0,  //BusBase
+      0xb7, //BusLimit
+      (PCI_HB0RB3_ECAM_BASE),  //MemBase
+      (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit
+      (PCI_HB0RB3_IO_BASE), //IoBase
+      (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1),  //IoLimit
+      PCI_HB0RB3_CPUMEMREGIONBASE,
+      PCI_HB0RB3_CPUIOREGIONBASE,
+      (PCI_HB0RB3_PCI_BASE),  //RbPciBar
+      PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 4 */
+  {
+      PCI_HB0RB4_ECAM_BASE, //ecam
+      0x88,  //BusBase
+      0x8f, //BusLimit
+      PCI_HB0RB4_CPUMEMREGIONBASE, //Membase
+      PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit
+      PCI_HB0RB4_IO_BASE,  //IoBase
+      (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB4_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB4_PCI_BASE),  //RbPciBar
+      PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 5 */
+  {
+      PCI_HB0RB5_ECAM_BASE,//ecam
+      0x0,  //BusBase
+      0x7, //BusLimit
+      PCI_HB0RB5_CPUMEMREGIONBASE, //Membase
+      PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB5_IO_BASE),  //IoBase
+      (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB5_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB5_PCI_BASE),  //RbPciBar
+      PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 6 */
+  {
+      PCI_HB0RB6_ECAM_BASE,
+      0xC0,  //BusBase
+      0xC7, //BusLimit
+      PCI_HB0RB6_PCIREGION_BASE ,//MemBase
+      PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB6_IO_BASE),  //IOBase
+      (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB6_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB6_PCI_BASE),  //RbPciBar
+      PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+
+  /* Port 7 */
+  {
+      PCI_HB0RB7_ECAM_BASE,
+      0x90,  //BusBase
+      0x97, //BusLimit
+      PCI_HB0RB7_CPUMEMREGIONBASE,  //MemBase
+      PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB7_IO_BASE), //IoBase
+      (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1),  //IoLimit
+      PCI_HB0RB7_CPUMEMREGIONBASE,
+      PCI_HB0RB7_CPUIOREGIONBASE,
+      (PCI_HB0RB7_PCI_BASE),  //RbPciBar
+      PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit
+  }
+ },
+{// HostBridge 1
+  /* Port 0 */
+  {
+      PCI_HB1RB0_ECAM_BASE,
+      0x80,  //BusBase
+      0x87, //BusLimit
+      (PCI_HB1RB0_ECAM_BASE),  //MemBase
+      (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit
+      PCI_HB1RB0_IO_BASE, //IoBase
+      (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB0_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB0_PCI_BASE),  //RbPciBar
+      PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 1 */
+  {
+      PCI_HB1RB1_ECAM_BASE,
+      0x90,  //BusBase
+      0x97, //BusLimit
+      (PCI_HB1RB1_ECAM_BASE),  //MemBase
+      (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit
+      PCI_HB1RB1_IO_BASE, //IoBase
+      (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB1_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB1_PCI_BASE),  //RbPciBar
+      PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 2 */
+  {
+      PCI_HB1RB2_ECAM_BASE,
+      0x10,  //BusBase
+      0x1f, //BusLimit
+      PCI_HB1RB2_CPUMEMREGIONBASE,  //MemBase
+      PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB2_IO_BASE, //IoBase
+      (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB2_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB2_PCI_BASE),  //RbPciBar
+      PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB1RB3_ECAM_BASE,
+      0xb0,  //BusBase
+      0xb7, //BusLimit
+      (PCI_HB1RB3_ECAM_BASE),  //MemBase
+      (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit
+      PCI_HB1RB3_IO_BASE, //IoBase
+      (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB3_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB3_PCI_BASE),  //RbPciBar
+      PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 4 */
+  {
+      PCI_HB1RB4_ECAM_BASE,
+      0x20,  //BusBase
+      0x2f, //BusLimit
+      PCI_HB1RB4_CPUMEMREGIONBASE,  //MemBase
+      PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB4_IO_BASE, //IoBase
+      (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB4_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB4_PCI_BASE),  //RbPciBar
+      PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 5 */
+  {
+      PCI_HB1RB5_ECAM_BASE,
+      0x30,  //BusBase
+      0x3f, //BusLimit
+      PCI_HB1RB5_CPUMEMREGIONBASE,  //MemBase
+      PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB5_IO_BASE, //IoBase
+      (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB5_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB5_PCI_BASE),  //RbPciBar
+      PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 6 */
+  {
+      PCI_HB1RB6_ECAM_BASE,
+      0xa8,  //BusBase
+      0xaf, //BusLimit
+      (PCI_HB1RB6_ECAM_BASE),  //MemBase
+      PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB6_IO_BASE, //IoBase
+      (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB6_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB6_PCI_BASE),  //RbPciBar
+      PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+
+  /* Port 7 */
+  {
+      PCI_HB1RB7_ECAM_BASE,
+      0xb8,  //BusBase
+      0xbf, //BusLimit
+      (PCI_HB1RB7_ECAM_BASE),  //MemBase
+      PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB7_IO_BASE, //IoBase
+      (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB7_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB7_PCI_BASE),  //RbPciBar
+      PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit
+  }
+
+ }
+};
+
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
new file mode 100644
index 0000000..8e013ca
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
@@ -0,0 +1,183 @@
+## @file
+#
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = PlatformPciLib
+  FILE_GUID                      = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  PlatformPciLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PciHb0Rb0Base
+  gHisiTokenSpaceGuid.PciHb0Rb1Base
+  gHisiTokenSpaceGuid.PciHb0Rb2Base
+  gHisiTokenSpaceGuid.PciHb0Rb3Base
+  gHisiTokenSpaceGuid.PciHb0Rb4Base
+  gHisiTokenSpaceGuid.PciHb0Rb5Base
+  gHisiTokenSpaceGuid.PciHb0Rb6Base
+  gHisiTokenSpaceGuid.PciHb0Rb7Base
+  gHisiTokenSpaceGuid.PciHb1Rb0Base
+  gHisiTokenSpaceGuid.PciHb1Rb1Base
+  gHisiTokenSpaceGuid.PciHb1Rb2Base
+  gHisiTokenSpaceGuid.PciHb1Rb3Base
+  gHisiTokenSpaceGuid.PciHb1Rb4Base
+  gHisiTokenSpaceGuid.PciHb1Rb5Base
+  gHisiTokenSpaceGuid.PciHb1Rb6Base
+  gHisiTokenSpaceGuid.PciHb1Rb7Base
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
+
diff --git a/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-hikey.dtb b/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-hikey.dtb
deleted file mode 100644
index bf04cc5..0000000
--- a/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-hikey.dtb
+++ /dev/null
diff --git a/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-hikey.dts b/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-hikey.dts
deleted file mode 100644
index 9df44c8..0000000
--- a/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-hikey.dts
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * dts file for Hisilicon HiKey Development Board
- *
- * Copyright (C) 2015, Hisilicon Ltd.
- *
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-
-#include "hi6220.dtsi"
-#include "hikey-pinctrl.dtsi"
-
-/ {
-	model = "HiKey Development Board";
-	compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
-
-	aliases {
-		serial0 = &uart0; /* On board UART0 */
-		serial1 = &uart1; /* BT UART */
-		serial2 = &uart2; /* LS Expansion UART0 */
-		serial3 = &uart3; /* LS Expansion UART1 */
-	};
-
-	chosen {
-		stdout-path = "serial3:115200n8";
-	};
-
-	/*
-	 * Reserve below regions from memory node:
-	 *
-	 *  0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
-	 *  0x05f0,1000 - 0x05f0,1fff: Reboot reason
-	 *  0x06df,f000 - 0x06df,ffff: Mailbox message data
-	 *  0x0740,f000 - 0x0740,ffff: MCU firmware section
-	 *  0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
-	 *  0x3e00,0000 - 0x3fff,ffff: OP-TEE
-	 */
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
-		      <0x00000000 0x05f00000 0x00000000 0x00001000>,
-		      <0x00000000 0x05f02000 0x00000000 0x00efd000>,
-		      <0x00000000 0x06e00000 0x00000000 0x0060f000>,
-		      <0x00000000 0x07410000 0x00000000 0x1aaf0000>,
-		      <0x00000000 0x22000000 0x00000000 0x1c000000>;
-	};
-
-	firmware {
-		optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-
-	pstore: pstore@0x21f00000 {
-		no-map;
-		reg = <0x0 0x21f00000 0x0 0x00100000>;  /* pstore/ramoops buffer */
-	};
-
-	ramoops {
-		compatible = "ramoops";
-		memory-region = <&pstore>;
-		record-size	= <0x0 0x00020000>;
-		console-size	= <0x0 0x00020000>;
-		ftrace-size	= <0x0 0x00020000>;
-	};
-
-	reboot_reason: reboot-reason@05f01000 {
-		compatible		= "linux,reboot-reason-sram";
-		reg			= <0x0 0x05F01000 0x0 0x4>;
-		reason,none		= <0x77665501>;
-		reason,bootloader	= <0x77665500>;
-		reason,recovery		= <0x77665502>;
-		reason,oem		= <0x6f656d00>;
-	};
-
-	soc {
-		i2c0: i2c@f7100000 {
-			status = "ok";
-		};
-
-		i2c1: i2c@f7101000 {
-			status = "ok";
-		};
-
-		uart1: uart@f7111000 {
-			status = "ok";
-		};
-
-		uart2: uart@f7112000 {
-			status = "ok";
-		};
-
-		uart3: uart@f7113000 {
-			status = "ok";
-		};
-
-		dwmmc_2: dwmmc2@f723f000 {
-			ti,non-removable;
-			non-removable;
-			/* WL_EN */
-			vmmc-supply = <&wlan_en_reg>;
-
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			wlcore: wlcore@2 {
-				compatible = "ti,wl1835";
-				reg = <2>;	/* sdio func num */
-				/* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */
-				interrupt-parent = <&gpio1>;
-				interrupts = <3 IRQ_TYPE_EDGE_RISING>;
-			};
-		};
-
-		wlan_en_reg: fixedregulator@1 {
-			compatible = "regulator-fixed";
-			regulator-name = "wlan-en-regulator";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1800000>;
-			/* WLAN_EN GPIO */
-			gpio = <&gpio0 5 0>;
-			/* WLAN card specific delay */
-			startup-delay-us = <70000>;
-			enable-active-high;
-		};
-
-		hisi-ion@0 {
-			compatible = "hisilicon,ion";
-
-			heap_sys_user@0 {
-				heap-name = "sys_user";
-				heap-range = <0x0 0x0>;
-				heap-type = "ion_system";
-			};
-
-			heap_sys_contig@0 {
-				heap-name = "sys_contig";
-				heap-range = <0x0 0x0>;
-				heap-type = "ion_system_contig";
-			};
-
-			heap_cma@0 {
-				heap-name = "cma";
-				heap-range = <0x0 0x0>;
-				heap-type = "ion_cma";
-			};
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		user_led1 {
-			label = "user_led4";
-			gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */
-			linux,default-trigger = "heartbeat";
-		};
-
-		user_led2 {
-			label = "user_led3";
-			gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */
-			linux,default-trigger = "mmc0";
-		};
-
-		user_led3 {
-			label = "user_led2";
-			gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */
-			linux,default-trigger = "mmc1";
-		};
-
-		user_led4 {
-			label = "user_led1";
-			gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */
-			linux,default-trigger = "cpu0";
-		};
-
-		wlan_active_led {
-			label = "wifi_active";
-			gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */
-			linux,default-trigger = "phy0tx";
-			default-state = "off";
-		};
-
-		bt_active_led {
-			label = "bt_active";
-			gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */
-			linux,default-trigger = "hci0rx";
-			default-state = "off";
-		};
-	};
-
-	kim {
-		compatible = "kim";
-		pinctrl-names = "default";
-		pinctrl-0 = <>; /* FIXME: add BT PCM pinctrl here */
-		/*
-		 * FIXME: The following is complete CRAP since
-		 * the vendor driver doesn't follow the gpio
-		 * binding. Passing in a magic Linux gpio number
-		 * here until we fix the vendor driver.
-		 */
-		/* BT_EN: BT_REG_ON_GPIO1_7 */
-		nshutdown_gpio = <503>;
-		dev_name = "/dev/ttyAMA1";
-		flow_cntrl = <1>;
-		baud_rate = <3000000>;
-	};
-
-	btwilink {
-		compatible = "btwilink";
-	};
-
-	pmic: pmic@f8000000 {
-		compatible = "hisilicon,hi655x-pmic";
-		reg = <0x0 0xf8000000 0x0 0x1000>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
-		status = "okay";
-
-		ponkey:ponkey@b1{
-			compatible = "hisilicon,hi6552-powerkey";
-			interrupt-parent = <&pmic>;
-			interrupts = <6 0>, <5 0>, <4 0>;
-			interrupt-names = "down", "up", "hold 4s";
-		};
-
-		regulators {
-			ldo2: LDO2 {
-				regulator-name = "LDO2_2V8";
-				regulator-min-microvolt = <2500000>;
-				regulator-max-microvolt = <3200000>;
-				regulator-enable-ramp-delay = <120>;
-			};
-
-			ldo7: LDO7 {
-				regulator-name = "LDO7_SDIO";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-enable-ramp-delay = <120>;
-			};
-
-			ldo10: LDO10 {
-				regulator-name = "LDO10_2V85";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-enable-ramp-delay = <360>;
-			};
-
-			ldo13: LDO13 {
-				regulator-name = "LDO13_1V8";
-				regulator-min-microvolt = <1600000>;
-				regulator-max-microvolt = <1950000>;
-				regulator-enable-ramp-delay = <120>;
-			};
-
-			ldo14: LDO14 {
-				regulator-name = "LDO14_2V8";
-				regulator-min-microvolt = <2500000>;
-				regulator-max-microvolt = <3200000>;
-				regulator-enable-ramp-delay = <120>;
-			};
-
-			ldo15: LDO15 {
-				regulator-name = "LDO15_1V8";
-				regulator-min-microvolt = <1600000>;
-				regulator-max-microvolt = <1950000>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-enable-ramp-delay = <120>;
-			};
-
-			ldo17: LDO17 {
-				regulator-name = "LDO17_2V5";
-				regulator-min-microvolt = <2500000>;
-				regulator-max-microvolt = <3200000>;
-				regulator-enable-ramp-delay = <120>;
-			};
-
-			ldo19: LDO19 {
-				regulator-name = "LDO19_3V0";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-enable-ramp-delay = <360>;
-			};
-
-			ldo21: LDO21 {
-				regulator-name = "LDO21_1V8";
-				regulator-min-microvolt = <1650000>;
-				regulator-max-microvolt = <2000000>;
-				regulator-always-on;
-				regulator-enable-ramp-delay = <120>;
-			};
-
-			ldo22: LDO22 {
-				regulator-name = "LDO22_1V2";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-enable-ramp-delay = <120>;
-			};
-		};
-	};
-};
-
-&ade {
-	status = "ok";
-};
-
-&dsi {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	mux-gpio = <&gpio0 1 0>;
-	status = "ok";
-
-	ports {
-		/* 1 for output port */
-		port@1 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <1>;
-
-			dsi_out0: endpoint@0 {
-				reg = <0>;
-				remote-endpoint = <&adv7533_in>;
-			};
-
-			dsi_out1: endpoint@1 {
-				reg = <1>;
-				remote-endpoint = <&panel0_in>;
-			};
-		};
-	};
-
-	/* For panel reg's value should >= 1 */
-	panel@1 {
-		compatible = "innolux,n070icn-pb1";
-		reg = <1>;
-		power-on-delay= <50>;
-		reset-delay = <100>;
-		init-delay = <100>;
-		panel-width-mm = <58>;
-		panel-height-mm = <103>;
-		pwr-en-gpio = <&gpio2 1 0>;
-		bl-en-gpio = <&gpio2 3 0>;
-		pwm-gpio = <&gpio12 7 0>;
-
-		port {
-			panel0_in: endpoint {
-				remote-endpoint = <&dsi_out1>;
-			};
-		};
-	};
-};
-
-&i2c2 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "ok";
-
-	adv7533: adv7533@39 {
-		compatible = "adi,adv7533";
-		reg = <0x39>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <1 2>;
-		pd-gpio = <&gpio0 4 0>;
-		adi,dsi-lanes = <4>;
-		adi,disable-timing-generator;
-
-		port {
-			adv7533_in: endpoint {
-				remote-endpoint = <&dsi_out0>;
-			};
-		};
-	};
- };
diff --git a/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-sched-energy.dtsi b/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-sched-energy.dtsi
deleted file mode 100644
index 6dfc493..0000000
--- a/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-sched-energy.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Hikey specific energy cost model data.
- */
-
-/* static struct idle_state idle_states_cluster_a53[] = { */
-/*        { .power = 47 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */
-/*        { .power = 47 }, /\* WFI *\/ */
-/*        { .power = 47 }, /\* cpu-sleep-0 *\/ */
-/*        { .power = 0  }, /\* cluster-sleep-0 *\/ */
-/* }; */
-
-/* static struct capacity_state cap_states_cluster_a53[] = { */
-/*        /\* Power per cluster *\/ */
-/*        { .cap =  178, .power =  16, }, /\*  200 MHz *\/ */
-/*        { .cap =  369, .power =  29, }, /\*  432 MHz *\/ */
-/*        { .cap =  622, .power =  47, }, /\*  729 MHz *\/ */
-/*        { .cap =  819, .power =  75, }, /\*  960 MHz *\/ */
-/*        { .cap = 1024, .power = 112, }, /\* 1200 Mhz *\/ */
-/* }; */
-
-/* static struct idle_state idle_states_core_a53[] = { */
-/*        { .power = 15 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */
-/*        { .power = 15 }, /\* WFI *\/ */
-/*        { .power =  0 }, /\* cpu-sleep-0 *\/ */
-/*        { .power =  0 }, /\* cluster-sleep-0 *\/ */
-/* }; */
-
-/* static struct capacity_state cap_states_core_a53[] = { */
-/*         /\* Power per cpu *\/ */
-/*        { .cap =  178, .power =  69, }, /\*  200 MHz *\/ */
-/*        { .cap =  369, .power = 124, }, /\*  432 MHz *\/ */
-/*        { .cap =  622, .power = 224, }, /\*  729 MHz *\/ */
-/*        { .cap =  819, .power = 367, }, /\*  960 MHz *\/ */
-/*        { .cap = 1024, .power = 670, }, /\* 1200 Mhz *\/ */
-/* }; */
-
-energy-costs {
-	CPU_COST: core-cost {
-		busy-cost-data = <
-			178    69
-			369   124
-			622   224
-			819   367
-		       1024   670
-		>;
-		idle-cost-data = <
-		         15
-		         15
-		          0
-		          0
-		>;
-	};
-
-	CLUSTER_COST: cluster-cost {
-		busy-cost-data = <
-			178    16
-			369    29
-			622    47
-			819    75
-		       1024   112
-		>;
-		idle-cost-data = <
-			 47
-			 47
-			 47
-			  0
-		>;
-	};
-};
diff --git a/Platforms/Hisilicon/HiKey/DeviceTree/hi6220.dtsi b/Platforms/Hisilicon/HiKey/DeviceTree/hi6220.dtsi
deleted file mode 100644
index 18c92b3..0000000
--- a/Platforms/Hisilicon/HiKey/DeviceTree/hi6220.dtsi
+++ /dev/null
@@ -1,1032 +0,0 @@
-/*
- * dts file for Hisilicon Hi6220 SoC
- *
- * Copyright (C) 2015, Hisilicon Ltd.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/hi6220-clock.h>
-#include <dt-bindings/pinctrl/hisi.h>
-#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/reset/hisi,hi6220-resets.h>
-
-/ {
-	compatible = "hisilicon,hi6220";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		cpu-map {
-			cluster0 {
-				core0 {
-					cpu = <&cpu0>;
-				};
-				core1 {
-					cpu = <&cpu1>;
-				};
-				core2 {
-					cpu = <&cpu2>;
-				};
-				core3 {
-					cpu = <&cpu3>;
-				};
-			};
-			cluster1 {
-				core0 {
-					cpu = <&cpu4>;
-				};
-				core1 {
-					cpu = <&cpu5>;
-				};
-				core2 {
-					cpu = <&cpu6>;
-				};
-				core3 {
-					cpu = <&cpu7>;
-				};
-			};
-		};
-
-		idle-states {
-			entry-method = "psci";
-
-			CPU_SLEEP: cpu-sleep {
-				compatible = "arm,idle-state";
-				local-timer-stop;
-				arm,psci-suspend-param = <0x0010000>;
-				entry-latency-us = <700>;
-				exit-latency-us = <250>;
-				min-residency-us = <1000>;
-			};
-
-			CLUSTER_SLEEP: cluster-sleep {
-				compatible = "arm,idle-state";
-				local-timer-stop;
-				arm,psci-suspend-param = <0x1010000>;
-				entry-latency-us = <1000>;
-				exit-latency-us = <700>;
-				min-residency-us = <2700>;
-				wakeup-latency-us = <1500>;
-			};
-		};
-
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0x0 0x0>;
-			enable-method = "psci";
-			next-level-cache = <&CLUSTER0_L2>;
-			clocks = <&stub_clock 0>;
-			operating-points-v2 = <&cpu_opp_table>;
-			cooling-min-level = <4>;
-			cooling-max-level = <0>;
-			#cooling-cells = <2>; /* min followed by max */
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
-			dynamic-power-coefficient = <311>;
-		};
-
-		cpu1: cpu@1 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0x0 0x1>;
-			enable-method = "psci";
-			next-level-cache = <&CLUSTER0_L2>;
-			operating-points-v2 = <&cpu_opp_table>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
-		};
-
-		cpu2: cpu@2 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0x0 0x2>;
-			enable-method = "psci";
-			next-level-cache = <&CLUSTER0_L2>;
-			operating-points-v2 = <&cpu_opp_table>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
-		};
-
-		cpu3: cpu@3 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0x0 0x3>;
-			enable-method = "psci";
-			next-level-cache = <&CLUSTER0_L2>;
-			operating-points-v2 = <&cpu_opp_table>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
-		};
-
-		cpu4: cpu@100 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0x0 0x100>;
-			enable-method = "psci";
-			next-level-cache = <&CLUSTER1_L2>;
-			operating-points-v2 = <&cpu_opp_table>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
-		};
-
-		cpu5: cpu@101 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0x0 0x101>;
-			enable-method = "psci";
-			next-level-cache = <&CLUSTER1_L2>;
-			operating-points-v2 = <&cpu_opp_table>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
-		};
-
-		cpu6: cpu@102 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0x0 0x102>;
-			enable-method = "psci";
-			next-level-cache = <&CLUSTER1_L2>;
-			operating-points-v2 = <&cpu_opp_table>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
-		};
-
-		cpu7: cpu@103 {
-			compatible = "arm,cortex-a53", "arm,armv8";
-			device_type = "cpu";
-			reg = <0x0 0x103>;
-			enable-method = "psci";
-			next-level-cache = <&CLUSTER1_L2>;
-			operating-points-v2 = <&cpu_opp_table>;
-			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
-			sched-energy-costs = <&CPU_COST &CLUSTER_COST>;
-		};
-
-		CLUSTER0_L2: l2-cache0 {
-			compatible = "cache";
-		};
-
-		CLUSTER1_L2: l2-cache1 {
-			compatible = "cache";
-		};
-
-		/include/ "hi6220-sched-energy.dtsi"
-	};
-
-	cpu_opp_table: cpu_opp_table {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp00 {
-			opp-hz = /bits/ 64 <208000000>;
-			opp-microvolt = <1040000>;
-			clock-latency-ns = <500000>;
-		};
-		opp01 {
-			opp-hz = /bits/ 64 <432000000>;
-			opp-microvolt = <1040000>;
-			clock-latency-ns = <500000>;
-		};
-		opp02 {
-			opp-hz = /bits/ 64 <729000000>;
-			opp-microvolt = <1090000>;
-			clock-latency-ns = <500000>;
-		};
-		opp03 {
-			opp-hz = /bits/ 64 <960000000>;
-			opp-microvolt = <1180000>;
-			clock-latency-ns = <500000>;
-		};
-		opp04 {
-			opp-hz = /bits/ 64 <1200000000>;
-			opp-microvolt = <1330000>;
-			clock-latency-ns = <500000>;
-		};
-	};
-
-	gic: interrupt-controller@f6801000 {
-		compatible = "arm,gic-400";
-		reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
-		      <0x0 0xf6802000 0 0x2000>, /* GICC */
-		      <0x0 0xf6804000 0 0x2000>, /* GICH */
-		      <0x0 0xf6806000 0 0x2000>; /* GICV */
-		#address-cells = <0>;
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		#sound-dai-cells = <0>;
-		interrupt-parent = <&gic>;
-		ranges;
-
-		sram: sram@fff80000 {
-			compatible = "hisilicon,hi6220-sramctrl", "syscon";
-			reg = <0x0 0xfff80000 0x0 0x12000>;
-		};
-
-		ao_ctrl: ao_ctrl@f7800000 {
-			compatible = "hisilicon,hi6220-aoctrl", "syscon";
-			reg = <0x0 0xf7800000 0x0 0x2000>;
-			#clock-cells = <1>;
-		};
-
-		sys_ctrl: sys_ctrl@f7030000 {
-			compatible = "hisilicon,hi6220-sysctrl", "syscon";
-			reg = <0x0 0xf7030000 0x0 0x2000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		media_ctrl: media_ctrl@f4410000 {
-			compatible = "hisilicon,hi6220-mediactrl", "syscon";
-			reg = <0x0 0xf4410000 0x0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		pm_ctrl: pm_ctrl@f7032000 {
-			compatible = "hisilicon,hi6220-pmctrl", "syscon";
-			reg = <0x0 0xf7032000 0x0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		stub_clock: stub_clock {
-			compatible = "hisilicon,hi6220-stub-clk";
-			hisilicon,hi6220-clk-sram = <&sram>;
-			#clock-cells = <1>;
-			mbox-names = "mbox-tx";
-			mboxes = <&mailbox 1 0 11>;
-		};
-
-		medianoc_ade: medianoc_ade@f4520000 {
-			compatible = "syscon";
-			reg = <0x0 0xf4520000 0x0 0x4000>;
-		};
-
-		uart0: uart@f8015000 {	/* console */
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x0 0xf8015000 0x0 0x1000>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
-				 <&ao_ctrl HI6220_UART0_PCLK>;
-			clock-names = "uartclk", "apb_pclk";
-		};
-
-		uart1: uart@f7111000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x0 0xf7111000 0x0 0x1000>;
-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
-				 <&sys_ctrl HI6220_UART1_PCLK>;
-			clock-names = "uartclk", "apb_pclk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
-			status = "disabled";
-		};
-
-		uart2: uart@f7112000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x0 0xf7112000 0x0 0x1000>;
-			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
-				 <&sys_ctrl HI6220_UART2_PCLK>;
-			clock-names = "uartclk", "apb_pclk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
-			status = "disabled";
-		};
-
-		uart3: uart@f7113000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x0 0xf7113000 0x0 0x1000>;
-			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
-				 <&sys_ctrl HI6220_UART3_PCLK>;
-			clock-names = "uartclk", "apb_pclk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
-			status = "disabled";
-		};
-
-		uart4: uart@f7114000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x0 0xf7114000 0x0 0x1000>;
-			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
-				 <&sys_ctrl HI6220_UART4_PCLK>;
-			clock-names = "uartclk", "apb_pclk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
-			status = "disabled";
-		};
-
-		dma0: dma@f7370000 {
-			compatible = "hisilicon,k3-dma-1.0";
-			reg = <0x0 0xf7370000 0x0 0x1000>;
-			#dma-cells = <1>;
-			dma-channels = <15>;
-			dma-requests = <32>;
-			interrupts = <0 84 4>;
-			clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
-			dma-no-cci;
-			dma-type = "hi6220_dma";
-			status = "ok";
-		};
-
-		dual_timer0: dual_timer@f8008000 {
-			compatible = "arm,sp804", "arm,primecell";
-			reg = <0x0 0xf8008000 0x0 0x1000>;
-			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ao_ctrl 27>;
-			clock-names = "apb_pclk";
-		};
-
-		rtc0: rtc@170000 {
-			compatible = "arm,pl031", "arm,primecell";
-			reg = <0x0 0xf8003000 0x0 0x1000>;
-			interrupts = <0 12 4>;
-			clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
-			clock-names = "apb_pclk";
-		};
-
-		pmx0: pinmux@f7010000 {
-			compatible = "pinctrl-single";
-			reg = <0x0 0xf7010000  0x0 0x27c>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			#gpio-range-cells = <3>;
-			pinctrl-single,register-width = <32>;
-			pinctrl-single,function-mask = <7>;
-			pinctrl-single,gpio-range = <
-				&range  80  8 MUX_M0 /* gpio  3: [0..7] */
-				&range  88  8 MUX_M0 /* gpio  4: [0..7] */
-				&range  96  8 MUX_M0 /* gpio  5: [0..7] */
-				&range 104  8 MUX_M0 /* gpio  6: [0..7] */
-				&range 112  8 MUX_M0 /* gpio  7: [0..7] */
-				&range 120  2 MUX_M0 /* gpio  8: [0..1] */
-				&range   2  6 MUX_M1 /* gpio  8: [2..7] */
-				&range   8  8 MUX_M1 /* gpio  9: [0..7] */
-				&range   0  1 MUX_M1 /* gpio 10: [0]    */
-				&range  16  7 MUX_M1 /* gpio 10: [1..7] */
-				&range  23  3 MUX_M1 /* gpio 11: [0..2] */
-				&range  28  5 MUX_M1 /* gpio 11: [3..7] */
-				&range  33  3 MUX_M1 /* gpio 12: [0..2] */
-				&range  43  5 MUX_M1 /* gpio 12: [3..7] */
-				&range  48  8 MUX_M1 /* gpio 13: [0..7] */
-				&range  56  8 MUX_M1 /* gpio 14: [0..7] */
-				&range  74  6 MUX_M1 /* gpio 15: [0..5] */
-				&range 122  1 MUX_M1 /* gpio 15: [6]    */
-				&range 126  1 MUX_M1 /* gpio 15: [7]    */
-				&range 127  8 MUX_M1 /* gpio 16: [0..7] */
-				&range 135  8 MUX_M1 /* gpio 17: [0..7] */
-				&range 143  8 MUX_M1 /* gpio 18: [0..7] */
-				&range 151  8 MUX_M1 /* gpio 19: [0..7] */
-			>;
-			range: gpio-range {
-				#pinctrl-single,gpio-range-cells = <3>;
-			};
-		};
-
-		pmx1: pinmux@f7010800 {
-			compatible = "pinconf-single";
-			reg = <0x0 0xf7010800 0x0 0x28c>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			pinctrl-single,register-width = <32>;
-		};
-
-		pmx2: pinmux@f8001800 {
-			compatible = "pinconf-single";
-			reg = <0x0 0xf8001800 0x0 0x78>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			pinctrl-single,register-width = <32>;
-		};
-
-		gpio0: gpio@f8011000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf8011000 0x0 0x1000>;
-			interrupts = <0 52 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio1: gpio@f8012000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf8012000 0x0 0x1000>;
-			interrupts = <0 53 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio2: gpio@f8013000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf8013000 0x0 0x1000>;
-			interrupts = <0 54 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio3: gpio@f8014000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf8014000 0x0 0x1000>;
-			interrupts = <0 55 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 80 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio4: gpio@f7020000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7020000 0x0 0x1000>;
-			interrupts = <0 56 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 88 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio5: gpio@f7021000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7021000 0x0 0x1000>;
-			interrupts = <0 57 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 96 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio6: gpio@f7022000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7022000 0x0 0x1000>;
-			interrupts = <0 58 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 104 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio7: gpio@f7023000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7023000 0x0 0x1000>;
-			interrupts = <0 59 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 112 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio8: gpio@f7024000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7024000 0x0 0x1000>;
-			interrupts = <0 60 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio9: gpio@f7025000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7025000 0x0 0x1000>;
-			interrupts = <0 61 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 8 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio10: gpio@f7026000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7026000 0x0 0x1000>;
-			interrupts = <0 62 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio11: gpio@f7027000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7027000 0x0 0x1000>;
-			interrupts = <0 63 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio12: gpio@f7028000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7028000 0x0 0x1000>;
-			interrupts = <0 64 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio13: gpio@f7029000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf7029000 0x0 0x1000>;
-			interrupts = <0 65 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 48 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio14: gpio@f702a000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf702a000 0x0 0x1000>;
-			interrupts = <0 66 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 56 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio15: gpio@f702b000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf702b000 0x0 0x1000>;
-			interrupts = <0 67 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <
-				&pmx0 0 74 6
-				&pmx0 6 122 1
-				&pmx0 7 126 1
-			>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio16: gpio@f702c000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf702c000 0x0 0x1000>;
-			interrupts = <0 68 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 127 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio17: gpio@f702d000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf702d000 0x0 0x1000>;
-			interrupts = <0 69 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 135 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio18: gpio@f702e000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf702e000 0x0 0x1000>;
-			interrupts = <0 70 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 143 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		gpio19: gpio@f702f000 {
-			compatible = "arm,pl061", "arm,primecell";
-			reg = <0x0 0xf702f000 0x0 0x1000>;
-			interrupts = <0 71 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pmx0 0 151 8>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&ao_ctrl 2>;
-			clock-names = "apb_pclk";
-			status = "ok";
-		};
-
-		spi0: spi@f7106000 {
-			compatible = "arm,pl022", "arm,primecell";
-			reg = <0x0 0xf7106000 0x0 0x1000>;
-			interrupts = <0 50 4>;
-			bus-id = <0>;
-			enable-dma = <0>;
-			clocks = <&sys_ctrl HI6220_SPI_CLK>;
-			clock-names = "apb_pclk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
-			num-cs = <1>;
-			cs-gpios = <&gpio6 2 0>;
-			status = "disabled";
-		};
-
-		i2c0: i2c@f7100000 {
-			compatible = "snps,designware-i2c";
-			reg = <0x0 0xf7100000 0x0 0x1000>;
-			interrupts = <0 44 4>;
-			clocks = <&sys_ctrl HI6220_I2C0_CLK>;
-			i2c-sda-hold-time-ns = <300>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
-			status = "disabled";
-		};
-
-		i2c1: i2c@f7101000 {
-			compatible = "snps,designware-i2c";
-			reg = <0x0 0xf7101000 0x0 0x1000>;
-			clocks = <&sys_ctrl HI6220_I2C1_CLK>;
-			interrupts = <0 45 4>;
-			i2c-sda-hold-time-ns = <300>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
-			status = "disabled";
-		};
-
-		i2c2: i2c@f7102000 {
-			compatible = "snps,designware-i2c";
-			reg = <0x0 0xf7102000 0x0 0x1000>;
-			clocks = <&sys_ctrl HI6220_I2C2_CLK>;
-			interrupts = <0 46 4>;
-			i2c-sda-hold-time-ns = <300>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
-			status = "disabled";
-		};
-
-		fixed_5v_hub: regulator@0 {
-			compatible = "regulator-fixed";
-			regulator-name = "fixed_5v_hub";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			regulator-boot-on;
-			gpio = <&gpio0 7 0>;
-			regulator-always-on;
-		};
-
-		usb_phy: usbphy {
-			compatible = "hisilicon,hi6220-usb-phy";
-			#phy-cells = <0>;
-			phy-supply = <&fixed_5v_hub>;
-			hisilicon,peripheral-syscon = <&sys_ctrl>;
-		};
-
-		usb: usb@f72c0000 {
-			compatible = "hisilicon,hi6220-usb";
-			reg = <0x0 0xf72c0000 0x0 0x40000>;
-			phys = <&usb_phy>;
-			phy-names = "usb2-phy";
-			clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
-			clock-names = "otg";
-			dr_mode = "otg";
-			g-use-dma;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <128>;
-			g-tx-fifo-size = <128 128 128 128 128 128>;
-			interrupts = <0 77 0x4>;
-		};
-
-		mailbox: mailbox@f7510000 {
-			compatible = "hisilicon,hi6220-mbox";
-			reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
-			      <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
-			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			#mbox-cells = <3>;
-		};
-
-		dwmmc_0: dwmmc0@f723d000 {
-		        compatible = "hisilicon,hi6220-dw-mshc";
-		        num-slots = <0x1>;
-			cap-mmc-highspeed;
-			non-removable;
-		        reg = <0x0 0xf723d000 0x0 0x1000>;
-		        interrupts = <0x0 0x48 0x4>;
-		        clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
-		        clock-names = "ciu", "biu";
-			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
-			bus-width = <0x8>;
-			vmmc-supply = <&ldo19>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
-				     &emmc_cfg_func &emmc_rst_cfg_func>;
-		};
-
-		dwmmc_1: dwmmc1@f723e000 {
-			compatible = "hisilicon,hi6220-dw-mshc";
-			num-slots = <0x1>;
-			card-detect-delay = <200>;
-			hisilicon,peripheral-syscon = <&ao_ctrl>;
-			cap-sd-highspeed;
-			sd-uhs-sdr12;
-			sd-uhs-sdr25;
-			sd-uhs-sdr50;
-			reg = <0x0 0xf723e000 0x0 0x1000>;
-			interrupts = <0x0 0x49 0x4>;
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-			clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
-			clock-names = "ciu", "biu";
-			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
-			vqmmc-supply = <&ldo7>;
-			vmmc-supply = <&ldo10>;
-			bus-width = <0x4>;
-			disable-wp;
-			cd-gpios = <&gpio1 0 1>;
-			pinctrl-names = "default", "idle";
-			pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
-			pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
-		};
-
-		dwmmc_2: dwmmc2@f723f000 {
-			compatible = "hisilicon,hi6220-dw-mshc";
-			status = "okay";
-			num-slots = <0x1>;
-			reg = <0x0 0xf723f000 0x0 0x1000>;
-			interrupts = <0x0 0x4a 0x4>;
-			clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
-			clock-names = "ciu", "biu";
-			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
-			bus-width = <0x4>;
-			broken-cd;
-			pinctrl-names = "default", "idle";
-			pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
-			pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
-		};
-
-		tsensor: tsensor@0,f7030700 {
-			compatible = "hisilicon,tsensor";
-			reg = <0x0 0xf7030700 0x0 0x1000>;
-			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sys_ctrl 22>;
-			clock-names = "thermal_clk";
-			#thermal-sensor-cells = <1>;
-		};
-
-		thermal-zones {
-
-			cls0: cls0 {
-				polling-delay = <1000>;
-				polling-delay-passive = <100>;
-				sustainable-power = <3326>;
-
-				/* sensor ID */
-				thermal-sensors = <&tsensor 2>;
-
-				trips {
-					threshold: trip-point@0 {
-						temperature = <65000>;
-						hysteresis = <1000>;
-						type = "passive";
-					};
-
-					target: trip-point@1 {
-						temperature = <75000>;
-						hysteresis = <1000>;
-						type = "passive";
-					};
-				};
-
-				cooling-maps {
-					map0 {
-						trip = <&target>;
-						contribution = <1024>;
-						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-					};
-				};
-			};
-		};
-
-		mtcmos {
-			compatible = "hisilicon,hi6220-mtcmos-driver";
-			hisilicon,mtcmos-steady-us = <10>;
-			hisilicon,mtcmos-sc-on-base  = <0xf7800000>;
-			hisilicon,mtcmos-acpu-on-base = <0xf65a0000>;
-
-			g3d_vdd: regulator@a1{
-				regulator-name = "G3D_PD_VDD";
-				regulator-compatible = "mtcmos1";
-				hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
-				hisilicon,ctrl-data = <1 0x1>;
-			};
-
-			soc_med: regulator@a2{
-				regulator-name = "SOC_MED";
-				regulator-compatible = "mtcmos2";
-				hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
-				hisilicon,ctrl-data = <2 0x1>;
-			};
-		};
-
-		ade: ade@f4100000 {
-			compatible = "hisilicon,hi6220-ade";
-			reg = <0x0 0xf4100000 0x0 0x7800>;
-			reg-names = "ade_base";
-			hisilicon,noc-syscon = <&medianoc_ade>;
-			resets = <&media_ctrl MEDIA_ADE>;
-			interrupts = <0 115 4>; /* ldi interrupt */
-
-			clocks = <&media_ctrl HI6220_ADE_CORE>,
-				 <&media_ctrl HI6220_CODEC_JPEG>,
-				 <&media_ctrl HI6220_ADE_PIX_SRC>;
-			/*clock name*/
-			clock-names  = "clk_ade_core",
-				       "clk_codec_jpeg",
-				       "clk_ade_pix";
-
-			assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
-				<&media_ctrl HI6220_CODEC_JPEG>;
-			assigned-clock-rates = <360000000>, <288000000>;
-			status = "disabled";
-
-			port {
-				ade_out: endpoint {
-					remote-endpoint = <&dsi_in>;
-				};
-			};
-		};
-
-		dsi: dsi@f4107800 {
-			compatible = "hisilicon,hi6220-dsi";
-			reg = <0x0 0xf4107800 0x0 0x100>;
-			clocks = <&media_ctrl  HI6220_DSI_PCLK>;
-			clock-names = "pclk";
-			status = "disabled";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				/* 0 for input port */
-				port@0 {
-					reg = <0>;
-					dsi_in: endpoint {
-						remote-endpoint = <&ade_out>;
-					};
-				};
-			};
-		};
-
-		mali:mali@f4080000 {
-			compatible = "arm,mali-450", "arm,mali-utgard";
-			reg = <0x0 0x3f100000 0x0 0x00708000>;
-			clocks = <&media_ctrl HI6220_G3D_CLK>,
-				 <&media_ctrl HI6220_G3D_PCLK>;
-			clock-names = "clk_g3d", "pclk_g3d";
-			G3D_PD_VDD-supply  = <&g3d_vdd>;
-			mali_def_freq = <500>;
-			pclk_freq = <144>;
-			dfs_steps = <2>;
-			dfs_lockprf = <1>;
-			dfs_limit_max_prf = <1>;
-			dfs_profile_num = <2>;
-			dfs_profiles = <250 3 0>, <500 1 0>;
-			mali_type = <2>;
-
-			interrupt-parent = <&gic>;
-			interrupts =	<1 126 4>, /*gp*/
-					<1 126 4>, /*gp mmu*/
-					<1 126 4>, /*pp bc*/
-					<1 126 4>, /*pmu*/
-					<1 126 4>, /*pp0*/
-					<1 126 4>,
-					<1 126 4>, /*pp1*/
-					<1 126 4>,
-					<1 126 4>, /*pp2*/
-					<1 126 4>,
-					<1 126 4>, /*pp4*/
-					<1 126 4>,
-					<1 126 4>, /*pp5*/
-					<1 126 4>,
-					<1 126 4>, /*pp6*/
-					<1 126 4>;
-			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPMU",
-					"IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1",
-					"IRQPP2", "IRQPPMMU2","IRQPP4", "IRQPPMMU4",
-					"IRQPP5", "IRQPPMMU5", "IRQPP6", "IRQPPMMU6";
-		};
-
-		i2s0: hi6210_i2s {
-			compatible = "hisilicon,hi6210-i2s";
-			reg = <0x0 0xf7118000 0x0 0x8000>, /* i2s unit */
-			      <0x0 0xf7030000 0x0 0x400>,  /* syscon */
-			      <0x0 0xf7032000 0x0 0x400>;  /* pmctrl */
-			interrupts = <0 123 0x4>; /* 155 "DigACodec_intr" - 32 */
-			pinctrl-names = "default";
-			pinctrl-0 = <&bt_pmx_func &bt_cfg_func>;
-			clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
-				 <&sys_ctrl HI6220_BBPPLL0_DIV>;
-			clock-names = "dacodec", "i2s-base";
-			dmas = <&dma0 15 &dma0 14>;
-	                dma-names = "rx", "tx";
-		};
-
-		hi6210_hdmi_card: hi6210_hdmi_card {
-			compatible = "hisilicon,hi6210-hdmi-audio-card";
-			reg = <0 0 0 0>;
-			sound-dai = <&i2s0>;
-		};
-	};
-};
diff --git a/Platforms/Hisilicon/HiKey/DeviceTree/hikey-pinctrl.dtsi b/Platforms/Hisilicon/HiKey/DeviceTree/hikey-pinctrl.dtsi
deleted file mode 100644
index d103cf1..0000000
--- a/Platforms/Hisilicon/HiKey/DeviceTree/hikey-pinctrl.dtsi
+++ /dev/null
@@ -1,727 +0,0 @@
-/*
- * pinctrl dts fils for Hislicon HiKey development board
- *
- */
-#include <dt-bindings/pinctrl/hisi.h>
-
-/ {
-	soc {
-		pmx0: pinmux@f7010000 {
-			pinctrl-names = "default";
-			pinctrl-0 = <
-				&boot_sel_pmx_func
-				&hkadc_ssi_pmx_func
-				&codec_clk_pmx_func
-				&pwm_in_pmx_func
-				&bl_pwm_pmx_func
-				>;
-
-			boot_sel_pmx_func: boot_sel_pmx_func {
-				pinctrl-single,pins = <
-					0x0    MUX_M0	/* BOOT_SEL     (IOMG000) */
-				>;
-			};
-
-			emmc_pmx_func: emmc_pmx_func {
-				pinctrl-single,pins = <
-					0x100  MUX_M0	/* EMMC_CLK     (IOMG064) */
-					0x104  MUX_M0	/* EMMC_CMD     (IOMG065) */
-					0x108  MUX_M0	/* EMMC_DATA0   (IOMG066) */
-					0x10c  MUX_M0	/* EMMC_DATA1   (IOMG067) */
-					0x110  MUX_M0	/* EMMC_DATA2   (IOMG068) */
-					0x114  MUX_M0	/* EMMC_DATA3   (IOMG069) */
-					0x118  MUX_M0	/* EMMC_DATA4   (IOMG070) */
-					0x11c  MUX_M0	/* EMMC_DATA5   (IOMG071) */
-					0x120  MUX_M0	/* EMMC_DATA6   (IOMG072) */
-					0x124  MUX_M0	/* EMMC_DATA7   (IOMG073) */
-				>;
-			};
-
-			sd_pmx_func: sd_pmx_func {
-				pinctrl-single,pins = <
-					0xc    MUX_M0	/* SD_CLK       (IOMG003) */
-					0x10   MUX_M0	/* SD_CMD       (IOMG004) */
-					0x14   MUX_M0	/* SD_DATA0     (IOMG005) */
-					0x18   MUX_M0	/* SD_DATA1     (IOMG006) */
-					0x1c   MUX_M0	/* SD_DATA2     (IOMG007) */
-					0x20   MUX_M0	/* SD_DATA3     (IOMG008) */
-				>;
-			};
-			sd_pmx_idle: sd_pmx_idle {
-				pinctrl-single,pins = <
-					0xc    MUX_M1	/* SD_CLK       (IOMG003) */
-					0x10   MUX_M1	/* SD_CMD       (IOMG004) */
-					0x14   MUX_M1	/* SD_DATA0     (IOMG005) */
-					0x18   MUX_M1	/* SD_DATA1     (IOMG006) */
-					0x1c   MUX_M1	/* SD_DATA2     (IOMG007) */
-					0x20   MUX_M1	/* SD_DATA3     (IOMG008) */
-				>;
-			};
-
-			sdio_pmx_func: sdio_pmx_func {
-				pinctrl-single,pins = <
-					0x128  MUX_M0	/* SDIO_CLK     (IOMG074) */
-					0x12c  MUX_M0	/* SDIO_CMD     (IOMG075) */
-					0x130  MUX_M0	/* SDIO_DATA0   (IOMG076) */
-					0x134  MUX_M0	/* SDIO_DATA1   (IOMG077) */
-					0x138  MUX_M0	/* SDIO_DATA2   (IOMG078) */
-					0x13c  MUX_M0	/* SDIO_DATA3   (IOMG079) */
-				>;
-			};
-			sdio_pmx_idle: sdio_pmx_idle {
-				pinctrl-single,pins = <
-					0x128  MUX_M1	/* SDIO_CLK     (IOMG074) */
-					0x12c  MUX_M1	/* SDIO_CMD     (IOMG075) */
-					0x130  MUX_M1	/* SDIO_DATA0   (IOMG076) */
-					0x134  MUX_M1	/* SDIO_DATA1   (IOMG077) */
-					0x138  MUX_M1	/* SDIO_DATA2   (IOMG078) */
-					0x13c  MUX_M1	/* SDIO_DATA3   (IOMG079) */
-				>;
-			};
-
-			isp_pmx_func: isp_pmx_func {
-				pinctrl-single,pins = <
-					0x24   MUX_M0	/* ISP_PWDN0    (IOMG009) */
-					0x28   MUX_M0	/* ISP_PWDN1    (IOMG010) */
-					0x2c   MUX_M0	/* ISP_PWDN2    (IOMG011) */
-					0x30   MUX_M1	/* ISP_SHUTTER0 (IOMG012) */
-					0x34   MUX_M1	/* ISP_SHUTTER1 (IOMG013) */
-					0x38   MUX_M1	/* ISP_PWM      (IOMG014) */
-					0x3c   MUX_M0	/* ISP_CCLK0    (IOMG015) */
-					0x40   MUX_M0	/* ISP_CCLK1    (IOMG016) */
-					0x44   MUX_M0	/* ISP_RESETB0  (IOMG017) */
-					0x48   MUX_M0	/* ISP_RESETB1  (IOMG018) */
-					0x4c   MUX_M1	/* ISP_STROBE0  (IOMG019) */
-					0x50   MUX_M1	/* ISP_STROBE1  (IOMG020) */
-					0x54   MUX_M0	/* ISP_SDA0     (IOMG021) */
-					0x58   MUX_M0	/* ISP_SCL0     (IOMG022) */
-					0x5c   MUX_M0	/* ISP_SDA1     (IOMG023) */
-					0x60   MUX_M0	/* ISP_SCL1     (IOMG024) */
-				>;
-			};
-
-			hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
-				pinctrl-single,pins = <
-					0x68   MUX_M0	/* HKADC_SSI    (IOMG026) */
-				>;
-			};
-
-			codec_clk_pmx_func: codec_clk_pmx_func {
-				pinctrl-single,pins = <
-					0x6c   MUX_M0	/* CODEC_CLK    (IOMG027) */
-				>;
-			};
-
-			codec_pmx_func: codec_pmx_func {
-				pinctrl-single,pins = <
-					0x70   MUX_M1	/* DMIC_CLK     (IOMG028) */
-					0x74   MUX_M0	/* CODEC_SYNC   (IOMG029) */
-					0x78   MUX_M0	/* CODEC_DI     (IOMG030) */
-					0x7c   MUX_M0	/* CODEC_DO     (IOMG031) */
-				>;
-			};
-
-			fm_pmx_func: fm_pmx_func {
-				pinctrl-single,pins = <
-					0x80   MUX_M1	/* FM_XCLK      (IOMG032) */
-					0x84   MUX_M1	/* FM_XFS       (IOMG033) */
-					0x88   MUX_M1	/* FM_DI        (IOMG034) */
-					0x8c   MUX_M1	/* FM_DO        (IOMG035) */
-				>;
-			};
-
-			bt_pmx_func: bt_pmx_func {
-				pinctrl-single,pins = <
-					0x90   MUX_M0	/* BT_XCLK      (IOMG036) */
-					0x94   MUX_M0	/* BT_XFS       (IOMG037) */
-					0x98   MUX_M0	/* BT_DI        (IOMG038) */
-					0x9c   MUX_M0	/* BT_DO        (IOMG039) */
-				>;
-			};
-
-			pwm_in_pmx_func: pwm_in_pmx_func {
-				pinctrl-single,pins = <
-					0xb8   MUX_M1	/* PWM_IN       (IOMG046) */
-				>;
-			};
-
-			bl_pwm_pmx_func: bl_pwm_pmx_func {
-				pinctrl-single,pins = <
-					0xbc   MUX_M1	/* BL_PWM       (IOMG047) */
-				>;
-			};
-
-			uart0_pmx_func: uart0_pmx_func {
-				pinctrl-single,pins = <
-					0xc0   MUX_M0	/* UART0_RXD    (IOMG048) */
-					0xc4   MUX_M0	/* UART0_TXD    (IOMG049) */
-				>;
-			};
-
-			uart1_pmx_func: uart1_pmx_func {
-				pinctrl-single,pins = <
-					0xc8   MUX_M0	/* UART1_CTS_N  (IOMG050) */
-					0xcc   MUX_M0	/* UART1_RTS_N  (IOMG051) */
-					0xd0   MUX_M0	/* UART1_RXD    (IOMG052) */
-					0xd4   MUX_M0	/* UART1_TXD    (IOMG053) */
-				>;
-			};
-
-			uart2_pmx_func: uart2_pmx_func {
-				pinctrl-single,pins = <
-					0xd8   MUX_M0	/* UART2_CTS_N  (IOMG054) */
-					0xdc   MUX_M0	/* UART2_RTS_N  (IOMG055) */
-					0xe0   MUX_M0	/* UART2_RXD    (IOMG056) */
-					0xe4   MUX_M0	/* UART2_TXD    (IOMG057) */
-				>;
-			};
-
-			uart3_pmx_func: uart3_pmx_func {
-				pinctrl-single,pins = <
-					0x180  MUX_M1	/* UART3_CTS_N  (IOMG096) */
-					0x184  MUX_M1	/* UART3_RTS_N  (IOMG097) */
-					0x188  MUX_M1	/* UART3_RXD    (IOMG098) */
-					0x18c  MUX_M1	/* UART3_TXD    (IOMG099) */
-				>;
-			};
-
-			uart4_pmx_func: uart4_pmx_func {
-				pinctrl-single,pins = <
-					0x1d0  MUX_M1	/* UART4_CTS_N  (IOMG116) */
-					0x1d4  MUX_M1	/* UART4_RTS_N  (IOMG117) */
-					0x1d8  MUX_M1	/* UART4_RXD    (IOMG118) */
-					0x1dc  MUX_M1	/* UART4_TXD    (IOMG119) */
-				>;
-			};
-
-			uart5_pmx_func: uart5_pmx_func {
-				pinctrl-single,pins = <
-					0x1c8  MUX_M1	/* UART5_RXD    (IOMG114) */
-					0x1cc  MUX_M1	/* UART5_TXD    (IOMG115) */
-				>;
-			};
-
-			i2c0_pmx_func: i2c0_pmx_func {
-				pinctrl-single,pins = <
-					0xe8   MUX_M0	/* I2C0_SCL     (IOMG058) */
-					0xec   MUX_M0	/* I2C0_SDA     (IOMG059) */
-				>;
-			};
-
-			i2c1_pmx_func: i2c1_pmx_func {
-				pinctrl-single,pins = <
-					0xf0   MUX_M0	/* I2C1_SCL     (IOMG060) */
-					0xf4   MUX_M0	/* I2C1_SDA     (IOMG061) */
-				>;
-			};
-
-			i2c2_pmx_func: i2c2_pmx_func {
-				pinctrl-single,pins = <
-					0xf8   MUX_M0	/* I2C2_SCL     (IOMG062) */
-					0xfc   MUX_M0	/* I2C2_SDA     (IOMG063) */
-				>;
-			};
-
-			spi0_pmx_func: spi0_pmx_func {
-				pinctrl-single,pins = <
-					0x1a0  MUX_M1   /* SPI0_DI      (IOMG104) */
-					0x1a4  MUX_M1	/* SPI0_DO	(IOMG105) */
-					0x1a8  MUX_M1	/* SPI0_CS_N	(IOMG106) */
-					0x1ac  MUX_M1	/* SPI0_CLK	(IOMG107) */
-				>;
-			};
-
-			modem_pcm_pmx_func: modem_pcm_pmx_func {
-				pinctrl-single,pins = <
-					0x198  MUX_M3	/* MODEM_PCM_XCLK  (IOMG102) */
-					0x19c  MUX_M3	/* MODEM_PCM_XFS  (IOMG103) */
-					0x1d0  MUX_M3	/* MODEM_PCM_DI  (IOMG116) */
-					0x1d4  MUX_M3	/* MODEM_PCM_DO  (IOMG117) */
-				>;
-			};
-
-		};
-
-		pmx1: pinmux@f7010800 {
-
-			pinctrl-names = "default";
-			pinctrl-0 = <
-				&boot_sel_cfg_func
-				&hkadc_ssi_cfg_func
-				&codec_clk_cfg_func
-				&pwm_in_cfg_func
-				&bl_pwm_cfg_func
-				>;
-
-			boot_sel_cfg_func: boot_sel_cfg_func {
-				pinctrl-single,pins = <
-					0x0    0x0	/* BOOT_SEL     (IOCFG000) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
-				pinctrl-single,pins = <
-					0x6c   0x0	/* HKADC_SSI    (IOCFG027) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			emmc_clk_cfg_func: emmc_clk_cfg_func {
-				pinctrl-single,pins = <
-					0x104  0x0	/* EMMC_CLK     (IOCFG065) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
-			};
-
-			emmc_cfg_func: emmc_cfg_func {
-				pinctrl-single,pins = <
-					0x108  0x0	/* EMMC_CMD     (IOCFG066) */
-					0x10c  0x0	/* EMMC_DATA0   (IOCFG067) */
-					0x110  0x0	/* EMMC_DATA1   (IOCFG068) */
-					0x114  0x0	/* EMMC_DATA2   (IOCFG069) */
-					0x118  0x0	/* EMMC_DATA3   (IOCFG070) */
-					0x11c  0x0	/* EMMC_DATA4   (IOCFG071) */
-					0x120  0x0	/* EMMC_DATA5   (IOCFG072) */
-					0x124  0x0	/* EMMC_DATA6   (IOCFG073) */
-					0x128  0x0	/* EMMC_DATA7   (IOCFG074) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
-			};
-
-			emmc_rst_cfg_func: emmc_rst_cfg_func {
-				pinctrl-single,pins = <
-					0x12c  0x0	/* EMMC_RST_N   (IOCFG075) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
-			};
-
-			sd_clk_cfg_func: sd_clk_cfg_func {
-				pinctrl-single,pins = <
-					0xc    0x0	/* SD_CLK       (IOCFG003) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
-			};
-			sd_clk_cfg_idle: sd_clk_cfg_idle {
-				pinctrl-single,pins = <
-					0xc    0x0	/* SD_CLK       (IOCFG003) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			sd_cfg_func: sd_cfg_func {
-				pinctrl-single,pins = <
-					0x10   0x0	/* SD_CMD       (IOCFG004) */
-					0x14   0x0	/* SD_DATA0     (IOCFG005) */
-					0x18   0x0	/* SD_DATA1     (IOCFG006) */
-					0x1c   0x0	/* SD_DATA2     (IOCFG007) */
-					0x20   0x0	/* SD_DATA3     (IOCFG008) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
-			};
-			sd_cfg_idle: sd_cfg_idle {
-				pinctrl-single,pins = <
-					0x10   0x0	/* SD_CMD       (IOCFG004) */
-					0x14   0x0	/* SD_DATA0     (IOCFG005) */
-					0x18   0x0	/* SD_DATA1     (IOCFG006) */
-					0x1c   0x0	/* SD_DATA2     (IOCFG007) */
-					0x20   0x0	/* SD_DATA3     (IOCFG008) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			sdio_clk_cfg_func: sdio_clk_cfg_func {
-				pinctrl-single,pins = <
-					0x134  0x0	/* SDIO_CLK     (IOCFG077) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
-			};
-			sdio_clk_cfg_idle: sdio_clk_cfg_idle {
-				pinctrl-single,pins = <
-					0x134  0x0	/* SDIO_CLK     (IOCFG077) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			sdio_cfg_func: sdio_cfg_func {
-				pinctrl-single,pins = <
-					0x138  0x0	/* SDIO_CMD     (IOCFG078) */
-					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */
-					0x140  0x0	/* SDIO_DATA1   (IOCFG080) */
-					0x144  0x0	/* SDIO_DATA2   (IOCFG081) */
-					0x148  0x0	/* SDIO_DATA3   (IOCFG082) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
-			};
-			sdio_cfg_idle: sdio_cfg_idle {
-				pinctrl-single,pins = <
-					0x138  0x0	/* SDIO_CMD     (IOCFG078) */
-					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */
-					0x140  0x0	/* SDIO_DATA1   (IOCFG080) */
-					0x144  0x0	/* SDIO_DATA2   (IOCFG081) */
-					0x148  0x0	/* SDIO_DATA3   (IOCFG082) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			isp_cfg_func1: isp_cfg_func1 {
-				pinctrl-single,pins = <
-					0x28   0x0	/* ISP_PWDN0    (IOCFG010) */
-					0x2c   0x0	/* ISP_PWDN1    (IOCFG011) */
-					0x30   0x0	/* ISP_PWDN2    (IOCFG012) */
-					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */
-					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */
-					0x3c   0x0	/* ISP_PWM      (IOCFG015) */
-					0x40   0x0	/* ISP_CCLK0    (IOCFG016) */
-					0x44   0x0	/* ISP_CCLK1    (IOCFG017) */
-					0x48   0x0	/* ISP_RESETB0  (IOCFG018) */
-					0x4c   0x0	/* ISP_RESETB1  (IOCFG019) */
-					0x50   0x0	/* ISP_STROBE0  (IOCFG020) */
-					0x58   0x0	/* ISP_SDA0     (IOCFG022) */
-					0x5c   0x0	/* ISP_SCL0     (IOCFG023) */
-					0x60   0x0	/* ISP_SDA1     (IOCFG024) */
-					0x64   0x0	/* ISP_SCL1     (IOCFG025) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-			isp_cfg_idle1: isp_cfg_idle1 {
-				pinctrl-single,pins = <
-					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */
-					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			isp_cfg_func2: isp_cfg_func2 {
-				pinctrl-single,pins = <
-					0x54   0x0	/* ISP_STROBE1  (IOCFG021) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			codec_clk_cfg_func: codec_clk_cfg_func {
-				pinctrl-single,pins = <
-					0x70   0x0	/* CODEC_CLK    (IOCFG028) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
-			};
-			codec_clk_cfg_idle: codec_clk_cfg_idle {
-				pinctrl-single,pins = <
-					0x70   0x0	/* CODEC_CLK    (IOCFG028) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			codec_cfg_func1: codec_cfg_func1 {
-				pinctrl-single,pins = <
-					0x74   0x0	/* DMIC_CLK     (IOCFG029) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			codec_cfg_func2: codec_cfg_func2 {
-				pinctrl-single,pins = <
-					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */
-					0x7c   0x0	/* CODEC_DI     (IOCFG031) */
-					0x80   0x0	/* CODEC_DO     (IOCFG032) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
-			};
-			codec_cfg_idle2: codec_cfg_idle2 {
-				pinctrl-single,pins = <
-					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */
-					0x7c   0x0	/* CODEC_DI     (IOCFG031) */
-					0x80   0x0	/* CODEC_DO     (IOCFG032) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			fm_cfg_func: fm_cfg_func {
-				pinctrl-single,pins = <
-					0x84   0x0	/* FM_XCLK      (IOCFG033) */
-					0x88   0x0	/* FM_XFS       (IOCFG034) */
-					0x8c   0x0	/* FM_DI        (IOCFG035) */
-					0x90   0x0	/* FM_DO        (IOCFG036) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			bt_cfg_func: bt_cfg_func {
-				pinctrl-single,pins = <
-					0x94   0x0	/* BT_XCLK      (IOCFG037) */
-					0x98   0x0	/* BT_XFS       (IOCFG038) */
-					0x9c   0x0	/* BT_DI        (IOCFG039) */
-					0xa0   0x0	/* BT_DO        (IOCFG040) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-			bt_cfg_idle: bt_cfg_idle {
-				pinctrl-single,pins = <
-					0x94   0x0	/* BT_XCLK      (IOCFG037) */
-					0x98   0x0	/* BT_XFS       (IOCFG038) */
-					0x9c   0x0	/* BT_DI        (IOCFG039) */
-					0xa0   0x0	/* BT_DO        (IOCFG040) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			pwm_in_cfg_func: pwm_in_cfg_func {
-				pinctrl-single,pins = <
-					0xbc   0x0	/* PWM_IN       (IOCFG047) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			bl_pwm_cfg_func: bl_pwm_cfg_func {
-				pinctrl-single,pins = <
-					0xc0   0x0	/* BL_PWM       (IOCFG048) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			uart0_cfg_func1: uart0_cfg_func1 {
-				pinctrl-single,pins = <
-					0xc4   0x0	/* UART0_RXD    (IOCFG049) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			uart0_cfg_func2: uart0_cfg_func2 {
-				pinctrl-single,pins = <
-					0xc8   0x0	/* UART0_TXD    (IOCFG050) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
-			};
-
-			uart1_cfg_func1: uart1_cfg_func1 {
-				pinctrl-single,pins = <
-					0xcc   0x0	/* UART1_CTS_N  (IOCFG051) */
-					0xd4   0x0	/* UART1_RXD    (IOCFG053) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			uart1_cfg_func2: uart1_cfg_func2 {
-				pinctrl-single,pins = <
-					0xd0   0x0	/* UART1_RTS_N  (IOCFG052) */
-					0xd8   0x0	/* UART1_TXD    (IOCFG054) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			uart2_cfg_func: uart2_cfg_func {
-				pinctrl-single,pins = <
-					0xdc   0x0	/* UART2_CTS_N  (IOCFG055) */
-					0xe0   0x0	/* UART2_RTS_N  (IOCFG056) */
-					0xe4   0x0	/* UART2_RXD    (IOCFG057) */
-					0xe8   0x0	/* UART2_TXD    (IOCFG058) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			uart3_cfg_func: uart3_cfg_func {
-				pinctrl-single,pins = <
-					0x190  0x0	/* UART3_CTS_N  (IOCFG100) */
-					0x194  0x0	/* UART3_RTS_N  (IOCFG101) */
-					0x198  0x0	/* UART3_RXD    (IOCFG102) */
-					0x19c  0x0	/* UART3_TXD    (IOCFG103) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			uart4_cfg_func: uart4_cfg_func {
-				pinctrl-single,pins = <
-					0x1e0  0x0	/* UART4_CTS_N  (IOCFG120) */
-					0x1e4  0x0	/* UART4_RTS_N  (IOCFG121) */
-					0x1e8  0x0	/* UART4_RXD    (IOCFG122) */
-					0x1ec  0x0	/* UART4_TXD    (IOCFG123) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			uart5_cfg_func: uart5_cfg_func {
-				pinctrl-single,pins = <
-					0x1d8  0x0	/* UART4_RXD    (IOCFG118) */
-					0x1dc  0x0	/* UART4_TXD    (IOCFG119) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			i2c0_cfg_func: i2c0_cfg_func {
-				pinctrl-single,pins = <
-					0xec   0x0	/* I2C0_SCL     (IOCFG059) */
-					0xf0   0x0	/* I2C0_SDA     (IOCFG060) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			i2c1_cfg_func: i2c1_cfg_func {
-				pinctrl-single,pins = <
-					0xf4   0x0	/* I2C1_SCL     (IOCFG061) */
-					0xf8   0x0	/* I2C1_SDA     (IOCFG062) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			i2c2_cfg_func: i2c2_cfg_func {
-				pinctrl-single,pins = <
-					0xfc   0x0	/* I2C2_SCL     (IOCFG063) */
-					0x100  0x0	/* I2C2_SDA     (IOCFG064) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			spi0_cfg_func: spi0_cfg_func {
-				pinctrl-single,pins = <
-					0x1b0  0x0	/* SPI0_DI	(IOCFG108) */
-					0x1b4  0x0	/* SPI0_DO	(IOCFG109) */
-					0x1b8  0x0	/* SPI0_CS_N	(IOCFG110) */
-					0x1bc  0x0	/* SPI0_CLK	(IOCFG111) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			modem_pcm_cfg_func: modem_pcm_cfg_func {
-				pinctrl-single,pins = <
-					0x1a8  0x0	/* MODEM_PCM_XCLK  (IOCFG106) */
-					0x1ac  0x0	/* MODEM_PCM_XFS  (IOCFG107) */
-					0x1e0  0x0	/* MODEM_PCM_DI  (IOCFG120) */
-					0x1e4  0x0	/* MODEM_PCM_DO  (IOCFG121) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DOWN  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE2_02MA DRIVE_MASK>;
-			};
-		};
-
-		pmx2: pinmux@f8001800 {
-
-			pinctrl-names = "default";
-			pinctrl-0 = <
-				&rstout_n_cfg_func
-				>;
-
-			rstout_n_cfg_func: rstout_n_cfg_func {
-				pinctrl-single,pins = <
-					0x0    0x0	/* RSTOUT_N     (IOCFG000) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
-				pinctrl-single,pins = <
-					0x4    0x0	/* PMU_PERI_EN  (IOCFG001) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			sysclk0_en_cfg_func: sysclk0_en_cfg_func {
-				pinctrl-single,pins = <
-					0x8    0x0	/* SYSCLK0_EN   (IOCFG002) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-
-			jtag_tdo_cfg_func: jtag_tdo_cfg_func {
-				pinctrl-single,pins = <
-					0xc    0x0	/* JTAG_TDO     (IOCFG003) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
-			};
-
-			rf_reset_cfg_func: rf_reset_cfg_func {
-				pinctrl-single,pins = <
-					0x70   0x0	/* RF_RESET0    (IOCFG028) */
-					0x74   0x0	/* RF_RESET1    (IOCFG029) */
-				>;
-				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
-				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
-				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
-			};
-		};
-	};
-};
diff --git a/Platforms/Hisilicon/HiKey/HiKey.dec b/Platforms/Hisilicon/HiKey/HiKey.dec
index 70f441f..c4a4ad3 100644
--- a/Platforms/Hisilicon/HiKey/HiKey.dec
+++ b/Platforms/Hisilicon/HiKey/HiKey.dec
@@ -1,42 +1,39 @@
-#
-#  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-#  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-[Defines]
-  DEC_SPECIFICATION              = 0x00010005
-  PACKAGE_NAME                   = HiKey
-  PACKAGE_GUID                   = d6db414d-ea67-4312-94d5-9c9e5b224d25
-  PACKAGE_VERSION                = 0.1
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-#                   Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-[Includes.common]
-  Include                        # Root include for the package
-
-[Guids.common]
-  gArmPL061GpioGuid             =  { 0x5c1997d7, 0x8d45, 0x4f21, { 0xaf, 0x3c, 0x22, 0x06, 0xb8, 0xed, 0x8b, 0xec } }
-  gDwUsbDeviceGuid              =  { 0x72d78ea6, 0x4dee, 0x11e3, { 0x81, 0x00, 0xf3, 0x84, 0x2a, 0x48, 0xd0, 0xa0 } }
-  gFaultTolerantWriteGuid       =  { 0xfe5cea76, 0x4f72, 0x49e8, { 0x98, 0x6f, 0x2c, 0xd8, 0x99, 0xdf, 0xfe, 0x5d } }
-  gHiKeyTokenSpaceGuid          =  { 0x91148425, 0xcdd2, 0x4830, { 0x8b, 0xd0, 0xc6, 0x1c, 0x6d, 0xea, 0x36, 0x21 } }
-  gHiKeyVariableGuid            =  { 0x66b8d063, 0x1daa, 0x4c60, { 0xb9, 0xf2, 0x55, 0x0d, 0x7e, 0xe1, 0x2f, 0x38 } }
-
-[PcdsFixedAtBuild.common]
-  gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|L""|VOID*|0x00000001
-  gHiKeyTokenSpaceGuid.PcdArmFastbootFlashLimit|L""|VOID*|0x00000002
-  gHiKeyTokenSpaceGuid.PcdBootImagePath|L""|VOID*|0x00000003
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = HiKey
+  PACKAGE_GUID                   = d6db414d-ea67-4312-94d5-9c9e5b224d25
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
+
+[Guids.common]
+  gArmPL061GpioGuid             =  { 0x5c1997d7, 0x8d45, 0x4f21, { 0xaf, 0x3c, 0x22, 0x06, 0xb8, 0xed, 0x8b, 0xec } }
+  gDwUsbDeviceGuid              =  { 0x72d78ea6, 0x4dee, 0x11e3, { 0x81, 0x00, 0xf3, 0x84, 0x2a, 0x48, 0xd0, 0xa0 } }
+  gHiKeyTokenSpaceGuid          =  { 0x91148425, 0xcdd2, 0x4830, { 0x8b, 0xd0, 0xc6, 0x1c, 0x6d, 0xea, 0x36, 0x21 } }
+  gHiKeyVariableGuid            =  { 0x66b8d063, 0x1daa, 0x4c60, { 0xb9, 0xf2, 0x55, 0x0d, 0x7e, 0xe1, 0x2f, 0x38 } }
+
+[PcdsFixedAtBuild.common]
+  gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|L""|VOID*|0x00000001
+  gHiKeyTokenSpaceGuid.PcdArmFastbootFlashLimit|L""|VOID*|0x00000002
diff --git a/Platforms/Hisilicon/HiKey/HiKey.dsc b/Platforms/Hisilicon/HiKey/HiKey.dsc
index 53fd5d0..3a6b554 100644
--- a/Platforms/Hisilicon/HiKey/HiKey.dsc
+++ b/Platforms/Hisilicon/HiKey/HiKey.dsc
@@ -1,501 +1,528 @@
-#
-#  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-#  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
-  PLATFORM_NAME                  = HiKey
-  PLATFORM_GUID                  = 8edf1480-da5c-4857-bc02-7530bd8e7b7a
-  PLATFORM_VERSION               = 0.2
-  DSC_SPECIFICATION              = 0x00010005
-  OUTPUT_DIRECTORY               = Build/HiKey
-  SUPPORTED_ARCHITECTURES        = AARCH64
-  BUILD_TARGETS                  = DEBUG|RELEASE
-  SKUID_IDENTIFIER               = DEFAULT
-  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.fdf
-
-[LibraryClasses.common]
-!if $(TARGET) == RELEASE
-  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
-!else
-  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!endif
-  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
-
-  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
-  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
-  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
-  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
-  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
-  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
-
-  ArmPlatformLib|OpenPlatformPkg/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf
-  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
-  ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf
-
-  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
-  BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
-  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
-  CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
-  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
-  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
-  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
-  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
-  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
-  EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
-
-  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
-  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
-  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
-  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
-  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
-  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
-  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
-  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
-
-  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
-  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
-  RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
-
-  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
-
-  #
-  # Assume everything is fixed at build
-  #
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-
-  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
-  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
-  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
-  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
-  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
-  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
-  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
-  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
-  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
-
-  # USB Requirements
-  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
-  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
-
-  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
-
-  # Network Libraries
-  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
-  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
-  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
-  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
-  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
-
-[LibraryClasses.AARCH64]
-  ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
-  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf
-
-[LibraryClasses.common.SEC]
-  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
-  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
-  LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
-  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
-  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
-  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
-  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
-  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
-  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
-  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
-
-[LibraryClasses.common.DXE_CORE]
-  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
-  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
-  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
-  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
-  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-
-[LibraryClasses.common.UEFI_DRIVER]
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-
-[LibraryClasses.common.DXE_DRIVER]
-  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
-
-[LibraryClasses.common.DXE_RUNTIME_DRIVER]
-  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
-  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-
-[BuildOptions]
-  GCC:*_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/MdeModulePkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include -I$(WORKSPACE)/OpenPlatformPkg/Platforms/Hisilicon/HiKey/Include
-
-[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
-  GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
-  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
-
-################################################################################
-#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
-#
-################################################################################
-
-[PcdsFeatureFlag.common]
-  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
-
-  #
-  # Control what commands are supported from the UI
-  # Turn these on and off to add features or save size
-  #
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
-
-  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
-
-  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
-  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
-
-  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
-
-  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
-
-  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
-  #  It could be set FALSE to save size.
-  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
-
-  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
-
-[PcdsFixedAtBuild.common]
-  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
-  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
-  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
-  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
-  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
-  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
-  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
-  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
-
-  # DEBUG_ASSERT_ENABLED       0x01
-  # DEBUG_PRINT_ENABLED        0x02
-  # DEBUG_CODE_ENABLED         0x04
-  # CLEAR_MEMORY_ENABLED       0x08
-  # ASSERT_BREAKPOINT_ENABLED  0x10
-  # ASSERT_DEADLOOP_ENABLED    0x20
-!if $(TARGET) == RELEASE
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
-!else
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
-!endif
-
-  #  DEBUG_INIT      0x00000001  // Initialization
-  #  DEBUG_WARN      0x00000002  // Warnings
-  #  DEBUG_LOAD      0x00000004  // Load events
-  #  DEBUG_FS        0x00000008  // EFI File system
-  #  DEBUG_POOL      0x00000010  // Alloc & Free's
-  #  DEBUG_PAGE      0x00000020  // Alloc & Free's
-  #  DEBUG_INFO      0x00000040  // Verbose
-  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
-  #  DEBUG_VARIABLE  0x00000100  // Variable
-  #  DEBUG_BM        0x00000400  // Boot Manager
-  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
-  #  DEBUG_NET       0x00004000  // SNI Driver
-  #  DEBUG_UNDI      0x00010000  // UNDI Driver
-  #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
-  #  DEBUG_EVENT     0x00080000  // Event messages
-  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
-  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
-  #  DEBUG_ERROR     0x80000000  // Error
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
-
-  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
-
-  #
-  # Optional feature to help prevent EFI memory map fragments
-  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
-  # Values are in EFI Pages (4K). DXE Core will make sure that
-  # at least this much of each type of memory can be allocated
-  # from a single memory range. This way you only end up with
-  # maximum of two fragements for each type in the memory map
-  # (the memory used, and the free memory that was prereserved
-  # but not used).
-  #
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
-
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
-
-  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"hikey"
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha"
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"HiKey"
-
-  #
-  # NV Storage PCDs.
-  #
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockCount|0x00001000
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockSize|0x00000200
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockLba|0x00006000
-  gBlockVariableDxeTokenSpaceGuid.PcdNvStorageVariableBlockDevicePath|L"VenHw(B549F005-4BD4-4020-A0CB-06F42BDA68C3)/HD(5,GPT,00354BCD-BBCB-4CB3-B5AE-CDEFCB5DAC43)"
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x30000000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x30010000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x30020000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
-
-  # System Memory (1GB)
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3E000000
-
-  # HiKey Dual-Cluster profile
-  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
-  gArmPlatformTokenSpaceGuid.PcdClusterCount|2
-
-  gArmTokenSpaceGuid.PcdVFPEnabled|1
-
-  #
-  # ARM Pcds
-  #
-  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
-
-  #
-  # ARM PrimeCell
-  #
-
-  ## PL011 - Serial Terminal
-  DEFINE SERIAL_BASE = 0xF7113000 # UART3
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
-  gArmPlatformTokenSpaceGuid.PL011UartInteger|10
-  gArmPlatformTokenSpaceGuid.PL011UartFractional|26
-
-  ## PL031 RealTimeClock
-  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
-
-  #
-  # ARM General Interrupt Controller
-  #
-  gArmTokenSpaceGuid.PcdGicDistributorBase|0xF6801000
-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF6802000
-
-  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
-  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
-  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
-  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10
-
-  #
-  # ARM Architectural Timer Frequency
-  #
-  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|1200000
-  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units, 10,000 x 100 ns = 1,000,000 ns = 1 ms
-
-  #
-  # DW MMC/SD card controller
-  #
-  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xF723D000
-  gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
-  gDwSdDxeTokenSpaceGuid.PcdDwSdDxeBaseAddress|0xF723E000
-  gDwSdDxeTokenSpaceGuid.PcdDwSdDxeClockFrequencyInHz|24000000
-
-  #
-  # DW USB controller
-  #
-  gDwUsbDxeTokenSpaceGuid.PcdDwUsbDxeBaseAddress|0xF72C0000
-
-  #
-  # Fastboot
-  #
-  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x18d1
-  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0xd00d
-  gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|L"VenHw(b549f005-4bd4-4020-a0cb-06f42bda68c3)"
-  # Flash limit 128M/time, for memory concern
-  gHiKeyTokenSpaceGuid.PcdArmFastbootFlashLimit|"134217728"
-
-  #
-  # HiKey Boot Image
-  #
-  gHiKeyTokenSpaceGuid.PcdBootImagePath|L"VenHw(B549F005-4BD4-4020-A0CB-06F42BDA68C3)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E)"
-
-  #
-  # Variable Size
-  #
-  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|2048
-
-[PcdsDynamicDefault.common]
-  #
-  # The size of a dynamic PCD of the (VOID*) type can not be increased at run
-  # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128
-  # character "empty" string, to allow to be able to set FDT text device paths
-  # up to 128 characters long.
-  #
-  gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L"                                                                                                                                "
-
-################################################################################
-#
-# Components Section - list of all EDK II Modules needed by this Platform
-#
-################################################################################
-[Components.common]
-  #
-  # PEI Phase modules
-  #
-  ArmPlatformPkg/PrePi/PeiMPCore.inf
-
-  #
-  # DXE
-  #
-  MdeModulePkg/Core/Dxe/DxeMain.inf {
-    <LibraryClasses>
-      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
-  }
-
-  #
-  # Architectural Protocols
-  #
-  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
-  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
-  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
-  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
-
-  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
-  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
-  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
-  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
-
-  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
-  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
-    <LibraryClasses>
-      AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
-      TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
-      VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
-      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
-  }
-  OpenPlatformPkg/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.inf
-
-  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-
-  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
-  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-
-  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
-
-  #
-  # GPIO
-  #
-  ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
-  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyGpio/HiKeyGpio.inf
-
-  #
-  # MMC/SD
-  #
-  EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
-  OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf
-  OpenPlatformPkg/Drivers/Mmc/DwSdDxe/DwSdDxe.inf
-
-  #
-  # USB Host Support
-  #
-  OpenPlatformPkg/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.inf
-  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
-
-  #
-  # USB Mass Storage Support
-  #
-  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-
-  #
-  # USB Peripheral Support
-  #
-  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
-  OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.inf
-
-  #
-  # Fastboot
-  #
-  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
-  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.inf
-
-  #
-  # UEFI Network Stack
-  #
-  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
-  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
-  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
-  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
-  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
-  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
-  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
-  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
-  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
-
-  #
-  # AX88772 Ethernet Driver
-  #
-  OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
-
-  #
-  # FAT filesystem + GPT/MBR partitioning
-  #
-  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
-  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
-  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-
-  #
-  # Bds
-  #
-  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-  ArmPlatformPkg/Bds/Bds.inf
-
-  #
-  # Legacy Linux Loader
-  #
-  ArmPkg/Application/LinuxLoader/LinuxLoader.inf {
-    <LibraryClasses>
-      FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
-      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
-      SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
-  }
-
-  #
-  # HiKey Platform
-  #
-  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = HiKey
+  PLATFORM_GUID                  = 8edf1480-da5c-4857-bc02-7530bd8e7b7a
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/HiKey
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.fdf
+
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmPlatformLib|OpenPlatformPkg/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  #CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+
+  AbootimgLib|EmbeddedPkg/Library/AbootimgLib/AbootimgLib.inf
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  PlatformBootManagerLib|OpenPlatformPkg/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  UsbSerialNumberLib|OpenPlatformPkg/Library/UsbSerialNumberLib/UsbSerialNumberLib.inf
+
+  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+
+  #
+  # Assume everything is fixed at build
+  #
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+
+  # Network Libraries
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+
+  # It is not possible to prevent compilers from generating calls to generic
+  # intrinsic functions. This library provides the intrinsic functions
+  # generated by a given compiler.
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+  # Add support for GCC stack protector
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+[LibraryClasses.common.SEC]
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+[LibraryClasses.common.DXE_CORE]
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include -I$(WORKSPACE)/OpenPlatformPkg/Platforms/Hisilicon/HiKey/Include -I$(WORKSPACE)/OpenPlatformPkg/Include
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  #
+  # Control what commands are supported from the UI
+  # Turn these on and off to add features or save size
+  #
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+  # DEBUG_ASSERT_ENABLED       0x01
+  # DEBUG_PRINT_ENABLED        0x02
+  # DEBUG_CODE_ENABLED         0x04
+  # CLEAR_MEMORY_ENABLED       0x08
+  # ASSERT_BREAKPOINT_ENABLED  0x10
+  # ASSERT_DEADLOOP_ENABLED    0x20
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+  #  DEBUG_INIT      0x00000001  // Initialization
+  #  DEBUG_WARN      0x00000002  // Warnings
+  #  DEBUG_LOAD      0x00000004  // Load events
+  #  DEBUG_FS        0x00000008  // EFI File system
+  #  DEBUG_POOL      0x00000010  // Alloc & Free's
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free's
+  #  DEBUG_INFO      0x00000040  // Verbose
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+  #  DEBUG_VARIABLE  0x00000100  // Variable
+  #  DEBUG_BM        0x00000400  // Boot Manager
+  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+  #  DEBUG_NET       0x00004000  // SNI Driver
+  #  DEBUG_UNDI      0x00010000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // Load File
+  #  DEBUG_EVENT     0x00080000  // Event messages
+  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
+  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
+  #  DEBUG_ERROR     0x80000000  // Error
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"hikey"
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha"
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"HiKey"
+
+  #
+  # NV Storage PCDs.
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x30000000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x30010000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x30020000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
+
+  # TimerPeriod
+  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000
+
+  # System Memory (1GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3E000000
+
+  # HiKey Dual-Cluster profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|2
+
+  gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+
+  #
+  # ARM PrimeCell
+  #
+
+  ## PL011 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xF7113000 # UART3
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+  gArmPlatformTokenSpaceGuid.PL011UartInteger|10
+  gArmPlatformTokenSpaceGuid.PL011UartFractional|26
+
+  ## PL031 RealTimeClock
+  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
+
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xF6801000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF6802000
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10
+
+  # GUID of the UEFI Shell
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # DW USB controller
+  #
+  gDwUsbDxeTokenSpaceGuid.PcdDwUsbDxeBaseAddress|0xF72C0000
+
+  #
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x18d1
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0xd00d
+  gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00D023F70000000000)/eMMC(0x0)/Ctrl(0x0)"
+  # Flash limit 128M/time, for memory concern
+  gHiKeyTokenSpaceGuid.PcdArmFastbootFlashLimit|"134217728"
+
+  #
+  # Android Loader
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00D023F70000000000)/eMMC(0x0)/Ctrl(0x0)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E,0x7000,0x20000)"
+  gEmbeddedTokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)/HD(1,MBR,0x00000000,0x3F,0x21FC0)"
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|1
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # GPIO
+  #
+  ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  OpenPlatformPkg/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # MMC/SD
+  #
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.inf
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf
+  MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
+  #MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+  OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.inf
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.inf
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/HiKeyUsbDxe.inf
+
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
+
+  #
+  # Android Loader
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
+
+  #
+  # UEFI Network Stack
+  #
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+  #
+  # AX88772 Ethernet Driver
+  #
+  OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/Hisilicon/HiKey/HiKey.fdf b/Platforms/Hisilicon/HiKey/HiKey.fdf
index 8d763b8..91f6f3e 100644
--- a/Platforms/Hisilicon/HiKey/HiKey.fdf
+++ b/Platforms/Hisilicon/HiKey/HiKey.fdf
@@ -1,367 +1,370 @@
-#
-#  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-#  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-################################################################################
-#
-# FD Section
-# The [FD] Section is made up of the definition statements and a
-# description of what goes into  the Flash Device Image.  Each FD section
-# defines one flash "device" image.  A flash device image may be one of
-# the following: Removable media bootable image (like a boot floppy
-# image,) an Option ROM image (that would be "flashed" into an add-in
-# card,) a System "Flash"  image (that would be burned into a system's
-# flash) or an Update ("Capsule") image that will be used to update and
-# existing system flash.
-#
-################################################################################
-
-[FD.BL33_AP_UEFI]
-BaseAddress   = 0x35000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
-Size          = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
-ErasePolarity = 1
-
-# This one is tricky, it must be: BlockSize * NumBlocks = Size
-BlockSize     = 0x00001000
-NumBlocks     = 0xF0
-
-################################################################################
-#
-# Following are lists of FD Region layout which correspond to the locations of different
-# images within the flash device.
-#
-# Regions must be defined in ascending order and may not overlap.
-#
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
-# the pipe "|" character, followed by the size of the region, also in hex with the leading
-# "0x" characters. Like:
-# Offset|Size
-# PcdOffsetCName|PcdSizeCName
-# RegionType <FV, DATA, or FILE>
-#
-################################################################################
-
-0x00000000|0x000F0000
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
-FV = FVMAIN_COMPACT
-
-
-################################################################################
-#
-# FV Section
-#
-# [FV] section is used to define what components or modules are placed within a flash
-# device file.  This section also defines order the components and modules are positioned
-# within the image.  The [FV] section consists of define statements, set statements and
-# module statements.
-#
-################################################################################
-
-[FV.FvMain]
-BlockSize          = 0x40
-NumBlocks          = 0         # This FV gets compressed so make it just big enough
-FvAlignment        = 8         # FV alignment and FV attributes setting.
-ERASE_POLARITY     = 1
-MEMORY_MAPPED      = TRUE
-STICKY_WRITE       = TRUE
-LOCK_CAP           = TRUE
-LOCK_STATUS        = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP  = TRUE
-WRITE_STATUS       = TRUE
-WRITE_LOCK_CAP     = TRUE
-WRITE_LOCK_STATUS  = TRUE
-READ_DISABLED_CAP  = TRUE
-READ_ENABLED_CAP   = TRUE
-READ_STATUS        = TRUE
-READ_LOCK_CAP      = TRUE
-READ_LOCK_STATUS   = TRUE
-
-  INF MdeModulePkg/Core/Dxe/DxeMain.inf
-
-  #
-  # PI DXE Drivers producing Architectural Protocols (EFI Services)
-  #
-  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
-  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
-  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
-  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
-
-  #
-  # Multiple Console IO support
-  #
-  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
-  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
-  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
-
-  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
-  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-
-  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
-
-  #
-  # GPIO
-  #
-  INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
-  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyGpio/HiKeyGpio.inf
-
-  #
-  # Multimedia Card Interface
-  #
-  INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
-  INF OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf
-  INF OpenPlatformPkg/Drivers/Mmc/DwSdDxe/DwSdDxe.inf
-
-  #
-  # USB Host Support
-  #
-  INF OpenPlatformPkg/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.inf
-  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
-
-  #
-  # USB Mass Storage Support
-  #
-  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-
-  #
-  # USB Peripheral Support
-  #
-  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
-  INF OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.inf
-
-  #
-  # Fastboot
-  #
-  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
-  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.inf
-
-  #
-  # UEFI Network Stack
-  #
-  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
-  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
-  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
-  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
-  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
-  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
-  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
-  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
-  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
-
-  #
-  # AX88772 Ethernet Driver for Apple Ethernet Adapter
-  #
-  INF OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
-
-  #
-  # FAT filesystem + GPT/MBR partitioning
-  #
-  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
-  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
-  INF FatBinPkg/EnhancedFatDxe/Fat.inf
-  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-
-  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
-  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
-  INF OpenPlatformPkg/Drivers/Variable/BlockVariableDxe/BlockVariableDxe.inf
-
-  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-
-  #
-  # UEFI applications
-  #
-  INF ShellBinPkg/UefiShell/UefiShell.inf
-
-  #
-  # Bds
-  #
-  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-  INF ArmPlatformPkg/Bds/Bds.inf
-
-  # add Device Tree to the Firmware Volume
-  FILE FREEFORM = 91148425-CDD2-4830-8BD0-C61C6DEA3621 {
-    SECTION RAW = OpenPlatformPkg/Platforms/Hisilicon/HiKey/DeviceTree/hi6220-hikey.dtb
-  }
-
-  #
-  # Legacy Linux Loader
-  #
-  INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf
-
-  #
-  # HiKey Platform
-  #
-  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf
-
-[FV.FVMAIN_COMPACT]
-FvAlignment        = 8
-ERASE_POLARITY     = 1
-MEMORY_MAPPED      = TRUE
-STICKY_WRITE       = TRUE
-LOCK_CAP           = TRUE
-LOCK_STATUS        = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP  = TRUE
-WRITE_STATUS       = TRUE
-WRITE_LOCK_CAP     = TRUE
-WRITE_LOCK_STATUS  = TRUE
-READ_DISABLED_CAP  = TRUE
-READ_ENABLED_CAP   = TRUE
-READ_STATUS        = TRUE
-READ_LOCK_CAP      = TRUE
-READ_LOCK_STATUS   = TRUE
-
-  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
-
-  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
-    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
-      SECTION FV_IMAGE = FVMAIN
-    }
-  }
-
-
-################################################################################
-#
-# Rules are use with the [FV] section's module INF type to define
-# how an FFS file is created for a given INF file. The following Rule are the default
-# rules for the different module type. User can add the customized rules to define the
-# content of the FFS file.
-#
-################################################################################
-
-
-############################################################################
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
-############################################################################
-#
-#[Rule.Common.DXE_DRIVER]
-#  FILE DRIVER = $(NAMED_GUID) {
-#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-#    COMPRESS PI_STD {
-#      GUIDED {
-#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
-#        UI       STRING="$(MODULE_NAME)" Optional
-#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-#      }
-#    }
-#  }
-#
-############################################################################
-
-#
-# These SEC rules are used for ArmPlatformPkg/PrePi module.
-# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the
-# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint
-#
-[Rule.ARM.SEC]
-  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
-    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
-  }
-
-[Rule.AARCH64.SEC]
-  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
-    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
-  }
-
-# A shim specific rule is required to ensure the alignment is 4K.
-# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)
-[Rule.ARM.SEC.SHIM]
-  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
-    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
-  }
-
-[Rule.Common.PEI_CORE]
-  FILE PEI_CORE = $(NAMED_GUID) {
-    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI     STRING ="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.PEIM]
-  FILE PEIM = $(NAMED_GUID) {
-     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
-     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
-     UI       STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.PEIM.TIANOCOMPRESSED]
-  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
-    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
-    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
-      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
-      UI        STRING="$(MODULE_NAME)" Optional
-    }
-  }
-
-[Rule.Common.DXE_CORE]
-  FILE DXE_CORE = $(NAMED_GUID) {
-    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI       STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.UEFI_DRIVER]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI           STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.DXE_DRIVER]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI           STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.DXE_DRIVER.BINARY]
-  FILE DRIVER = $(NAMED_GUID) {
-  DXE_DEPEX    DXE_DEPEX              Optional |.depex
-  PE32         PE32                   |.efi
-  UI           STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.DXE_RUNTIME_DRIVER]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
-    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
-    UI           STRING="$(MODULE_NAME)" Optional
-  }
-
-[Rule.Common.UEFI_APPLICATION]
-  FILE APPLICATION = $(NAMED_GUID) {
-    UI     STRING ="$(MODULE_NAME)" Optional
-    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
-  }
-
-[Rule.Common.UEFI_DRIVER.BINARY]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX DXE_DEPEX Optional      |.depex
-    PE32      PE32                    |.efi
-    UI        STRING="$(MODULE_NAME)" Optional
-    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-  }
-
-[Rule.Common.UEFI_APPLICATION.BINARY]
-  FILE APPLICATION = $(NAMED_GUID) {
-    PE32      PE32                    |.efi
-    UI        STRING="$(MODULE_NAME)" Optional
-    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-  }
-
-[Rule.Common.USER_DEFINED.ACPITABLE]
-  FILE FREEFORM = $(NAMED_GUID) {
-    RAW ACPI               |.acpi
-    RAW ASL                |.aml
-  }
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.BL33_AP_UEFI]
+BaseAddress   = 0x35000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0xF0
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x000F0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid         = 69b7d469-55a2-49d8-a426-42bfb22f5b9d
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # GPIO
+  #
+  INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF OpenPlatformPkg/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # Multimedia Card Interface
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  INF OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf
+  INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
+  #INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+  INF OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/HiKeyUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Loader
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI Network Stack
+  #
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+#
+# These SEC rules are used for ArmPlatformPkg/PrePi module.
+# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the
+# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint
+#
+[Rule.ARM.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.AARCH64.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+# A shim specific rule is required to ensure the alignment is 4K.
+# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)
+[Rule.ARM.SEC.SHIM]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+  DXE_DEPEX    DXE_DEPEX              Optional |.depex
+  PE32         PE32                   |.efi
+  UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)" Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI               |.acpi
+    RAW ASL                |.aml
+  }
diff --git a/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c b/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c
index 60d7fe5..952e3ef 100644
--- a/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c
+++ b/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c
@@ -14,173 +14,325 @@
 **/
 
 #include <Library/BaseMemoryLib.h>
-#include <Library/BdsLib.h>
 #include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
 #include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
 #include <Library/MemoryAllocationLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+#include <Library/PrintLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 #include <Library/UefiLib.h>
 #include <Library/UefiRuntimeServicesTableLib.h>
 
-#include <Guid/HiKeyVariable.h>
-
+#include <Protocol/Abootimg.h>
 #include <Protocol/BlockIo.h>
-#include <Protocol/DwUsb.h>
+#include <Protocol/EmbeddedGpio.h>
+#include <Protocol/PlatformVirtualKeyboard.h>
 
-#include "HiKeyDxeInternal.h"
+#include <Hi6220.h>
+#include <libfdt.h>
 
-#define SERIAL_NUMBER_LENGTH        17
-#define SERIAL_NUMBER_LBA           1024
-#define SERIAL_NUMBER_BLOCK_SIZE    512
-#define RANDOM_MAGIC                0x9a4dbeaf
+#include "Hi6220RegsPeri.h"
 
-struct RandomSerialNo {
-  UINTN              Magic;
-  UINTN              Data;
-  CHAR8              SerialNo[32];
-};
+#define SERIAL_NUMBER_SIZE               17
+#define SERIAL_NUMBER_BLOCK_SIZE         EFI_PAGE_SIZE
+#define SERIAL_NUMBER_LBA                1024
+#define RANDOM_MAX                       0x7FFFFFFFFFFFFFFF
+#define RANDOM_MAGIC                     0x9A4DBEAF
+
+#define DETECT_J15_FASTBOOT              24   // GPIO3_0
+
+#define ADB_REBOOT_ADDRESS               0x05F01000
+#define ADB_REBOOT_BOOTLOADER            0x77665500
+#define ADB_REBOOT_NONE                  0x77665501
+
+
+typedef struct {
+  UINT64        Magic;
+  UINT64        Data;
+  CHAR16        UnicodeSN[SERIAL_NUMBER_SIZE];
+} RANDOM_SERIAL_NUMBER;
+
+STATIC EMBEDDED_GPIO        *mGpio;
+
+STATIC
+VOID
+UartInit (
+  IN VOID
+  )
+{
+  UINT32     Val;
+
+  /* make UART1 out of reset */
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1);
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1);
+  /* make UART2 out of reset */
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2);
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2);
+  /* make UART3 out of reset */
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3);
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3);
+  /* make UART4 out of reset */
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4);
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4);
+
+  /* make DW_MMC2 out of reset */
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2);
 
-STATIC CHAR16 mSerialNo[17];
+  /* enable clock for BT/WIFI */
+  Val = MmioRead32 (PMUSSI_REG(0x1c)) | 0x40;
+  MmioWrite32 (PMUSSI_REG(0x1c), Val);
+}
 
 STATIC
-UINTN
+VOID
+MtcmosInit (
+  IN VOID
+  )
+{
+  UINT32     Data;
+
+  /* enable MTCMOS for GPU */
+  MmioWrite32 (AO_CTRL_BASE + SC_PW_MTCMOS_EN0, PW_EN0_G3D);
+  do {
+    Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0);
+  } while ((Data & PW_EN0_G3D) == 0);
+}
+
+EFI_STATUS
+HiKeyInitPeripherals (
+  IN VOID
+  )
+{
+  UINT32     Data, Bits;
+
+  /* make I2C0/I2C1/I2C2/SPI0 out of reset */
+  Bits = PERIPH_RST3_I2C0 | PERIPH_RST3_I2C1 | PERIPH_RST3_I2C2 | \
+         PERIPH_RST3_SSP;
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, Bits);
+
+  do {
+    Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT3);
+  } while (Data & Bits);
+
+  UartInit ();
+  MtcmosInit ();
+
+  /* Set DETECT_J15_FASTBOOT (GPIO24) pin as GPIO function */
+  MmioWrite32 (0xf7010950, 0);        /* configure GPIO24 as nopull */
+  MmioWrite32 (0xf7010140, 0);        /* configure GPIO24 as GPIO */
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
 EFIAPI
-HiKeyInitSerialNo (
-  IN   VOID
+AbootimgAppendKernelArgs (
+  IN CHAR16            *Args,
+  IN UINTN              Size
   )
 {
-  EFI_STATUS                      Status;
-  UINTN                           VariableSize;
-  EFI_DEVICE_PATH_PROTOCOL        *BlockDevicePath;
-  EFI_BLOCK_IO_PROTOCOL           *BlockIoProtocol;
-  EFI_HANDLE                      Handle;
-  VOID                            *DataPtr;
-  struct RandomSerialNo           *Random;
-  CHAR16                          DefaultSerialNo[] = L"0123456789abcdef";
-  CHAR16                          SerialNoUnicode[32], DataUnicode[32];
-
-  BlockDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
-  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &BlockDevicePath, &Handle);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Couldn't locate block device (status: %r)\n", Status));
+  EFI_STATUS                  Status;
+  EFI_BLOCK_IO_PROTOCOL      *BlockIoProtocol;
+  VOID                       *DataPtr;
+  RANDOM_SERIAL_NUMBER       *RandomSN;
+  EFI_DEVICE_PATH_PROTOCOL   *FlashDevicePath;
+  EFI_HANDLE                  FlashHandle;
+
+  if (Args == NULL) {
     return EFI_INVALID_PARAMETER;
   }
+  FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePath, &FlashHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
   Status = gBS->OpenProtocol (
-		      Handle,
-                      &gEfiBlockIoProtocolGuid,
-		      (VOID **) &BlockIoProtocol,
-                      gImageHandle,
-                      NULL,
-                      EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                      );
+                  FlashHandle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &BlockIoProtocol,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
   if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Couldn't open block device (status: %r)\n", Status));
+    DEBUG ((DEBUG_WARN, "Warning: Couldn't open block device (status: %r)\n", Status));
     return EFI_DEVICE_ERROR;
   }
-  DataPtr = AllocateZeroPool (SERIAL_NUMBER_BLOCK_SIZE);
-  WriteBackDataCacheRange (DataPtr, SERIAL_NUMBER_BLOCK_SIZE);
-  Status = BlockIoProtocol->ReadBlocks (BlockIoProtocol, BlockIoProtocol->Media->MediaId,
-                                        SERIAL_NUMBER_LBA, SERIAL_NUMBER_BLOCK_SIZE,
-                                        DataPtr);
+
+  DataPtr = AllocatePages (1);
+  if (DataPtr == NULL) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+  Status = BlockIoProtocol->ReadBlocks (
+                              BlockIoProtocol,
+                              BlockIoProtocol->Media->MediaId,
+                              SERIAL_NUMBER_LBA,
+                              SERIAL_NUMBER_BLOCK_SIZE,
+                              DataPtr
+                              );
   if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: failed on reading blocks.\n"));
-    goto exit;
-  }
-  InvalidateDataCacheRange (DataPtr, SERIAL_NUMBER_BLOCK_SIZE);
-  Random = (struct RandomSerialNo *)DataPtr;
-  if (Random->Magic != RANDOM_MAGIC) {
-    VariableSize = SERIAL_NUMBER_LENGTH * sizeof (CHAR16);
-    Status = gRT->GetVariable (
-                    (CHAR16 *)L"SerialNo",
-                    &gHiKeyVariableGuid,
-                    NULL,
-                    &VariableSize,
-                    &DefaultSerialNo
-                    );
-    if (Status == EFI_NOT_FOUND) {
-      Status = gRT->SetVariable (
-                      (CHAR16*)L"SerialNo",
-                      &gHiKeyVariableGuid,
-                      EFI_VARIABLE_NON_VOLATILE       |
-                      EFI_VARIABLE_BOOTSERVICE_ACCESS |
-                      EFI_VARIABLE_RUNTIME_ACCESS,
-                      VariableSize,
-                      DefaultSerialNo
-                      );
-    }
-    CopyMem (mSerialNo, DefaultSerialNo, sizeof (DefaultSerialNo));
-  } else {
-    ZeroMem (DataUnicode, 32 * sizeof(CHAR16));
-    ZeroMem (SerialNoUnicode, 32 * sizeof(CHAR16));
-    AsciiStrToUnicodeStr (Random->SerialNo, SerialNoUnicode);
-    VariableSize = SERIAL_NUMBER_LENGTH * sizeof (CHAR16);
-    Status = gRT->GetVariable (
-                    (CHAR16 *)L"SerialNo",
-                    &gHiKeyVariableGuid,
-                    NULL,
-                    &VariableSize,
-                    &DataUnicode
-                    );
-    if ((Status == EFI_NOT_FOUND) || StrCmp (DataUnicode, SerialNoUnicode)) {
-      Status = gRT->SetVariable (
-                      (CHAR16*)L"SerialNo",
-                      &gHiKeyVariableGuid,
-                      EFI_VARIABLE_NON_VOLATILE       |
-                      EFI_VARIABLE_BOOTSERVICE_ACCESS |
-                      EFI_VARIABLE_RUNTIME_ACCESS,
-                      VariableSize,
-                      SerialNoUnicode
-                      );
-    }
-    CopyMem (mSerialNo, SerialNoUnicode, VariableSize);
+    DEBUG ((DEBUG_WARN, "Warning: Failed on reading blocks\n"));
+    goto Exit;
+  }
+  RandomSN = (RANDOM_SERIAL_NUMBER *)DataPtr;
+  if (RandomSN->Magic != RANDOM_MAGIC) {
+    UnicodeSPrint(
+      RandomSN->UnicodeSN, SERIAL_NUMBER_SIZE * sizeof (CHAR16),
+      L"0123456789abcdef"
+      );
   }
-exit:
-  FreePool (DataPtr);
+  UnicodeSPrint (
+    Args + StrLen (Args), Size - StrLen (Args),
+    L" androidboot.serialno=%s",
+    RandomSN->UnicodeSN
+    );
+  FreePages (DataPtr, 1);
+  return EFI_SUCCESS;
+Exit:
+  FreePages (DataPtr, 1);
   return Status;
 }
 
 EFI_STATUS
 EFIAPI
-GetSerialNo (
-  OUT CHAR16            *SerialNo,
-  OUT UINT8             *Length
+AbootimgUpdateDtb (
+  IN  EFI_PHYSICAL_ADDRESS        OrigFdtBase,
+  OUT EFI_PHYSICAL_ADDRESS       *NewFdtBase
   )
 {
-  EFI_STATUS             Status;
-  UINTN                  VariableSize;
-  CHAR16                 DataUnicode[32];
+  UINTN             FdtSize, NumPages;
+  INTN              err;
+  EFI_STATUS        Status;
 
-  if (SerialNo == NULL)
+  //
+  // Sanity checks on the original FDT blob.
+  //
+  err = fdt_check_header ((VOID*)(UINTN)OrigFdtBase);
+  if (err != 0) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Device Tree header not valid (err:%d)\n", err));
     return EFI_INVALID_PARAMETER;
-  VariableSize = SERIAL_NUMBER_LENGTH * sizeof (CHAR16);
-  ZeroMem (DataUnicode, 32 * sizeof(CHAR16));
-  Status = gRT->GetVariable (
-                  (CHAR16 *)L"SerialNo",
-                  &gHiKeyVariableGuid,
+  }
+
+  //
+  // Store the FDT as Runtime Service Data to prevent the Kernel from
+  // overwritting its data.
+  //
+  FdtSize = fdt_totalsize ((VOID *)(UINTN)OrigFdtBase);
+  NumPages = EFI_SIZE_TO_PAGES (FdtSize) + 20;
+  Status = gBS->AllocatePages (
+                  AllocateAnyPages, EfiRuntimeServicesData,
+                  NumPages, NewFdtBase);
+  if (EFI_ERROR (Status)) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+
+  CopyMem (
+    (VOID*)(UINTN)*NewFdtBase,
+    (VOID*)(UINTN)OrigFdtBase,
+    FdtSize
+    );
+
+  fdt_pack ((VOID*)(UINTN)*NewFdtBase);
+  err = fdt_check_header ((VOID*)(UINTN)*NewFdtBase);
+  if (err != 0) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Device Tree header not valid (err:%d)\n", err));
+    gBS->FreePages (*NewFdtBase, NumPages);
+    return EFI_INVALID_PARAMETER;
+  }
+  return EFI_SUCCESS;
+}
+
+ABOOTIMG_PROTOCOL mAbootimg = {
+  AbootimgAppendKernelArgs,
+  AbootimgUpdateDtb
+};
+
+EFI_STATUS
+EFIAPI
+VirtualKeyboardRegister (
+  IN VOID
+  )
+{
+  EFI_STATUS           Status;
+
+  Status = gBS->LocateProtocol (
+                  &gEmbeddedGpioProtocolGuid,
                   NULL,
-                  &VariableSize,
-                  &DataUnicode
+                  (VOID **) &mGpio
                   );
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  CopyMem (SerialNo, DataUnicode, VariableSize);
-  *Length = VariableSize;
   return EFI_SUCCESS;
 }
 
 EFI_STATUS
 EFIAPI
-UsbPhyInit (
-  IN UINT8     Mode
+VirtualKeyboardReset (
+  IN VOID
+  )
+{
+  EFI_STATUS           Status;
+
+  if (mGpio == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = mGpio->Set (mGpio, DETECT_J15_FASTBOOT, GPIO_MODE_INPUT);
+  return Status;
+}
+
+BOOLEAN
+EFIAPI
+VirtualKeyboardQuery (
+  IN VIRTUAL_KBD_KEY             *VirtualKey
+  )
+{
+  EFI_STATUS           Status;
+  UINTN                Value = 0;
+
+  if ((VirtualKey == NULL) || (mGpio == NULL)) {
+    return FALSE;
+  }
+  if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
+    goto Done;
+  } else {
+    Status = mGpio->Get (mGpio, DETECT_J15_FASTBOOT, &Value);
+    if (EFI_ERROR (Status) || (Value != 0)) {
+      return FALSE;
+    }
+  }
+Done:
+  VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE;
+  VirtualKey->Key.ScanCode = SCAN_NULL;
+  VirtualKey->Key.UnicodeChar = L'f';
+  return TRUE;
+}
+
+EFI_STATUS
+EFIAPI
+VirtualKeyboardClear (
+  IN VIRTUAL_KBD_KEY            *VirtualKey
   )
 {
-  return HiKeyUsbPhyInit (Mode);
+  if (VirtualKey == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
+    MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE);
+    WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4);
+  }
+  return EFI_SUCCESS;
 }
 
-DW_USB_PROTOCOL mDwUsbDevice = {
-  GetSerialNo,
-  UsbPhyInit
+PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = {
+  VirtualKeyboardRegister,
+  VirtualKeyboardReset,
+  VirtualKeyboardQuery,
+  VirtualKeyboardClear
 };
 
 EFI_STATUS
@@ -190,22 +342,54 @@ HiKeyEntryPoint (
   IN EFI_SYSTEM_TABLE   *SystemTable
   )
 {
-  EFI_STATUS           Status;
+  EFI_STATUS            Status;
 
-  Status = gBS->InstallProtocolInterface (
-		  &ImageHandle,
-		  &gDwUsbProtocolGuid,
-		  EFI_NATIVE_INTERFACE,
-		  &mDwUsbDevice
-		  );
+  Status = HiKeyInitPeripherals ();
   if (EFI_ERROR (Status)) {
     return Status;
   }
 
-  HiKeyInitSerialNo ();
-  HiKeyInitPeripherals ();
+  // RegisterNonDicoverableMmioDevice
+  Status = RegisterNonDiscoverableMmioDevice (
+             NonDiscoverableDeviceTypeSdhci,
+             NonDiscoverableDeviceDmaTypeNonCoherent,
+             NULL,
+             NULL,
+             1,
+             0xF723D000, // eMMC
+             SIZE_4KB
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = RegisterNonDiscoverableMmioDevice (
+             NonDiscoverableDeviceTypeSdhci,
+             NonDiscoverableDeviceDmaTypeNonCoherent,
+             NULL,
+             NULL,
+             1,
+             0xF723E000, // SD
+             SIZE_4KB
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
 
-  Status = HiKeyBootMenuInstall ();
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gAbootimgProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  &mAbootimg
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
 
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gPlatformVirtualKeyboardProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  &mVirtualKeyboard
+                  );
   return Status;
 }
diff --git a/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf b/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf
index 8600b18..b3ce059 100644
--- a/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf
+++ b/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf
@@ -22,25 +22,24 @@
 
 [Sources.common]
   HiKeyDxe.c
-  InitPeripherals.c
-  InstallBootMenu.c
 
 [Packages]
   ArmPkg/ArmPkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
-  OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec
+  OpenPlatformPkg/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.dec
   OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec
 
 [LibraryClasses]
   BaseMemoryLib
-  BdsLib
   CacheMaintenanceLib
   DebugLib
   DxeServicesLib
   DxeServicesTableLib
+  FdtLib
   IoLib
+  NonDiscoverableDeviceRegistrationLib
   PcdLib
   PrintLib
   SerialPortLib
@@ -50,28 +49,18 @@
   UefiLib
   UefiDriverEntryPoint
 
-[Guids]
-  gEfiEndOfDxeEventGroupGuid
-  gEfiFileInfoGuid
-  gEfiGlobalVariableGuid
-  gFdtTableGuid
-  gFdtVariableGuid
-  gHiKeyVariableGuid
-
 [Protocols]
-  gDwUsbProtocolGuid
+  gAbootimgProtocolGuid
   gEfiBlockIoProtocolGuid
-  gEfiDevicePathFromTextProtocolGuid
-  gEfiDevicePathToTextProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEfiSimpleFileSystemProtocolGuid
   gEmbeddedGpioProtocolGuid
+  gPlatformVirtualKeyboardProtocolGuid
+
+[Guids]
+  gEfiEndOfDxeEventGroupGuid
+  gEfiFileInfoGuid
 
-[FixedPcd]
-  gArmTokenSpaceGuid.PcdSystemMemoryBase
-  gArmTokenSpaceGuid.PcdSystemMemorySize
+[Pcd]
   gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath
-  gHiKeyTokenSpaceGuid.PcdBootImagePath
 
 [Depex]
-  AFTER gFaultTolerantWriteGuid
+  TRUE
diff --git a/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxeInternal.h b/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxeInternal.h
deleted file mode 100644
index 1922a9c..0000000
--- a/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxeInternal.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2015, Linaro Ltd. All rights reserved.
-*  Copyright (c) 2015, Hisilicon Ltd. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __HIKEY_DXE_INTERNAL_H__
-#define __HIKEY_DXE_INTERNAL_H__
-
-#include <Uefi.h>
-
-#include <Library/DebugLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#define BOOT_DEVICE_LENGTH       16
-#define USB_TYPE_LENGTH          16
-
-EFI_STATUS
-HiKeyFdtInstall (
-  IN EFI_HANDLE                            ImageHandle
-  );
-
-EFI_STATUS
-HiKeyBootMenuInstall (
-  IN VOID
-  );
-
-EFI_STATUS
-HiKeyInitPeripherals (
-  IN VOID
-  );
-
-EFI_STATUS
-HiKeyUsbPhyInit (
-  IN UINT8           Mode
-  );
-
-UINTN
-HiKeyGetUsbMode (
-  IN VOID
-  );
-#endif // __HIKEY_DXE_INTERNAL_H__
diff --git a/Platforms/Hisilicon/HiKey/HiKeyDxe/InstallBootMenu.c b/Platforms/Hisilicon/HiKey/HiKeyDxe/InstallBootMenu.c
deleted file mode 100644
index a441abc..0000000
--- a/Platforms/Hisilicon/HiKey/HiKeyDxe/InstallBootMenu.c
+++ /dev/null
@@ -1,868 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2015, Linaro Ltd. All rights reserved.
-*  Copyright (c) 2015, Hisilicon Ltd. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/BdsLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/DxeServicesLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PrintLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-
-#include <Protocol/BlockIo.h>
-#include <Protocol/DevicePathFromText.h>
-#include <Protocol/DevicePathToText.h>
-#include <Protocol/DwUsb.h>
-#include <Protocol/EmbeddedGpio.h>
-#include <Protocol/SimpleFileSystem.h>
-
-#include <Guid/Fdt.h>
-#include <Guid/FileInfo.h>
-#include <Guid/EventGroup.h>
-#include <Guid/GlobalVariable.h>
-#include <Guid/HiKeyVariable.h>
-#include <Guid/VariableFormat.h>
-
-#include "HiKeyDxeInternal.h"
-
-typedef enum {
-  HIKEY_DTB_ANDROID = 0,	/* DTB is attached at the end of boot.img */
-  HIKEY_DTB_LINUX = 1,		/* DTB is in partition */
-  HIKEY_DTB_SD = 2,		/* DTB is already in SD Card */
-} HiKeyDtbType;
-
-#define HIKEY_IO_BLOCK_SIZE      512
-
-#define MAX_BOOT_ENTRIES         16
-// Jumper on pin5-6 of J15 determines whether boot to fastboot
-#define DETECT_J15_FASTBOOT      24    // GPIO 3_0
-
-#define USER_LED1                32    // GPIO 4_0
-#define USER_LED2                33    // GPIO 4_1
-#define USER_LED3                34    // GPIO 4_2
-#define USER_LED4                35    // GPIO 4_3
-
-struct HiKeyBootEntry {
-  CHAR16    *Path;
-  CHAR16    *Args;
-  CHAR16    *Description;
-  UINT16     LoadType;
-};
-
-STATIC CONST BOOLEAN mIsEndOfDxeEvent = TRUE;
-STATIC UINT16 *mBootOrder = NULL;
-STATIC UINT16 mBootCount = 0;
-STATIC UINT16 mBootIndex = 0;
-
-#define HIKEY_BOOT_ENTRY_FASTBOOT          0
-#define HIKEY_BOOT_ENTRY_BOOT_EMMC         1    /* boot from eMMC */
-#define HIKEY_BOOT_ENTRY_BOOT_SD           2    /* boot from SD card */
-
-STATIC struct HiKeyBootEntry LinuxEntries[] = {
-  [HIKEY_BOOT_ENTRY_FASTBOOT] = {
-    L"FvFile(9588502a-5370-11e3-8631-d7c5951364c8)",
-    //L"VenHw(B549F005-4BD4-4020-A0CB-06F42BDA68C3)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E,0x7000,0x20000)/\\EFI\\BOOT\\FASTBOOT.EFI",
-    NULL,
-    L"fastboot",
-    LOAD_OPTION_CATEGORY_APP
-  },
-  [HIKEY_BOOT_ENTRY_BOOT_EMMC] = {
-    L"VenHw(B549F005-4BD4-4020-A0CB-06F42BDA68C3)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E,0x7000,0x20000)/\\EFI\\BOOT\\GRUBAA64.EFI",
-    NULL,
-    L"boot from eMMC",
-    LOAD_OPTION_CATEGORY_APP
-  },
-  [HIKEY_BOOT_ENTRY_BOOT_SD] = {
-    L"VenHw(594BFE73-5E18-4F12-8119-19DB8C5FC849)/HD(1,MBR,0x00000000,0x3F,0x21FC0)/\\EFI\\BOOT\\BOOTAA64.EFI",
-    NULL,
-    L"boot from SD card",
-    LOAD_OPTION_CATEGORY_BOOT
-  }
-};
-
-STATIC struct HiKeyBootEntry AndroidEntries[] = {
-  [HIKEY_BOOT_ENTRY_FASTBOOT] = {
-    L"FvFile(9588502a-5370-11e3-8631-d7c5951364c8)",
-    //L"VenHw(B549F005-4BD4-4020-A0CB-06F42BDA68C3)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E,0x7000,0x20000)/\\EFI\\BOOT\\FASTBOOT.EFI",
-    NULL,
-    L"fastboot",
-    LOAD_OPTION_CATEGORY_APP
-  },
-  [HIKEY_BOOT_ENTRY_BOOT_EMMC] = {
-    L"VenHw(B549F005-4BD4-4020-A0CB-06F42BDA68C3)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E,0x7000,0x20000)/Offset(0x0000,0x20000)",
-    L"console=ttyAMA3,115200 earlycon=pl011,0xf7113000 root=/dev/mmcblk0p9 rw rootwait efi=noruntime",
-    L"boot from eMMC",
-    LOAD_OPTION_CATEGORY_BOOT
-  },
-  [HIKEY_BOOT_ENTRY_BOOT_SD] = {
-    L"VenHw(594BFE73-5E18-4F12-8119-19DB8C5FC849)/HD(1,MBR,0x00000000,0x3F,0x21FC0)/Image",
-    L"dtb=hi6220-hikey.dtb console=ttyAMA3,115200 earlycon=pl011,0xf7113000 root=/dev/mmcblk1p2 rw rootwait initrd=initrd.img efi=noruntime",
-    L"boot from SD card",
-    LOAD_OPTION_CATEGORY_BOOT
-  }
-};
-
-
-STATIC
-BOOLEAN
-EFIAPI
-HiKeyVerifyBootEntry (
-  IN CHAR16          *BootVariableName,
-  IN CHAR16          *BootDevicePathText,
-  IN CHAR16          *BootArgs,
-  IN CHAR16          *BootDescription,
-  IN UINT16           LoadOptionAttr
-  )
-{
-  EFI_DEVICE_PATH_TO_TEXT_PROTOCOL   *DevicePathToTextProtocol;
-  CHAR16                             *DevicePathText;
-  UINTN                               EfiLoadOptionSize;
-  EFI_LOAD_OPTION                    *EfiLoadOption;
-  BDS_LOAD_OPTION                    *LoadOption;
-  EFI_STATUS                          Status;
-  UINTN                               DescriptionLength;
-
-  Status = GetGlobalEnvironmentVariable (BootVariableName, NULL, &EfiLoadOptionSize, (VOID**)&EfiLoadOption);
-  if (EFI_ERROR (Status)) {
-    return FALSE;
-  }
-  if (EfiLoadOption == NULL) {
-    return FALSE;
-  }
-  if (EfiLoadOptionSize < sizeof(UINT32) + sizeof(UINT16) + sizeof(CHAR16) + sizeof(EFI_DEVICE_PATH_PROTOCOL)) {
-    return FALSE;
-  }
-  LoadOption = (BDS_LOAD_OPTION*)AllocateZeroPool (sizeof(BDS_LOAD_OPTION));
-  if (LoadOption == NULL) {
-    return FALSE;
-  }
-
-  LoadOption->LoadOption         = EfiLoadOption;
-  LoadOption->Attributes         = *(UINT32*)EfiLoadOption;
-  LoadOption->FilePathListLength = *(UINT16*)(EfiLoadOption + sizeof(UINT32));
-  LoadOption->Description        = (CHAR16*)(EfiLoadOption + sizeof(UINT32) + sizeof(UINT16));
-  DescriptionLength              = StrSize (LoadOption->Description);
-  LoadOption->FilePathList       = (EFI_DEVICE_PATH_PROTOCOL*)(EfiLoadOption + sizeof(UINT32) + sizeof(UINT16) + DescriptionLength);
-  if ((UINTN)((UINTN)LoadOption->FilePathList + LoadOption->FilePathListLength - (UINTN)EfiLoadOption) == EfiLoadOptionSize) {
-    LoadOption->OptionalData     = NULL;
-    LoadOption->OptionalDataSize = 0;
-  } else {
-    LoadOption->OptionalData     = (VOID*)((UINTN)(LoadOption->FilePathList) + LoadOption->FilePathListLength);
-    LoadOption->OptionalDataSize = EfiLoadOptionSize - ((UINTN)LoadOption->OptionalData - (UINTN)EfiLoadOption);
-  }
-
-  if (((BootArgs == NULL) && (LoadOption->OptionalDataSize)) ||
-      (BootArgs && (LoadOption->OptionalDataSize == 0))) {
-    return FALSE;
-  } else if (BootArgs && LoadOption->OptionalDataSize) {
-    if (StrCmp (BootArgs, LoadOption->OptionalData) != 0)
-      return FALSE;
-  }
-  if ((LoadOption->Description == NULL) || (BootDescription == NULL)) {
-    return FALSE;
-  }
-  if (StrCmp (BootDescription, LoadOption->Description) != 0) {
-    return FALSE;
-  }
-  if ((LoadOption->Attributes & LOAD_OPTION_CATEGORY) != (LoadOptionAttr & LOAD_OPTION_CATEGORY)) {
-    return FALSE;
-  }
-
-  Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
-  ASSERT_EFI_ERROR(Status);
-  DevicePathText = DevicePathToTextProtocol->ConvertDevicePathToText(LoadOption->FilePathList, TRUE, TRUE);
-  if (StrCmp (DevicePathText, BootDevicePathText) != 0) {
-    return FALSE;
-  }
-
-  FreePool (LoadOption);
-  return TRUE;
-}
-
-STATIC
-EFI_STATUS
-EFIAPI
-HiKeyCreateBootEntry (
-  IN CHAR16          *DevicePathText,
-  IN CHAR16          *BootArgs,
-  IN CHAR16          *BootDescription,
-  IN UINT16           LoadOption
-  )
-{
-  BDS_LOAD_OPTION                    *BdsLoadOption;
-  EFI_STATUS                          Status;
-  UINTN                               DescriptionSize;
-  UINTN                               BootOrderSize;
-  CHAR16                              BootVariableName[9];
-  UINT8                              *EfiLoadOptionPtr;
-  EFI_DEVICE_PATH_PROTOCOL           *DevicePathNode;
-  UINTN                               NodeLength;
-  EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *DevicePathFromTextProtocol;
-
-  if ((DevicePathText == NULL) || (BootDescription == NULL)) {
-    DEBUG ((EFI_D_ERROR, "%a: Invalid Parameters\n", __func__));
-    return EFI_INVALID_PARAMETER;
-  }
-
-  UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", mBootCount);
-  if (HiKeyVerifyBootEntry (BootVariableName, DevicePathText, BootArgs, BootDescription, LoadOption) == TRUE) {
-    // The boot entry is already created.
-    Status = EFI_SUCCESS;
-    goto done;
-  }
-
-  BdsLoadOption = (BDS_LOAD_OPTION*)AllocateZeroPool (sizeof(BDS_LOAD_OPTION));
-  ASSERT (BdsLoadOption != NULL);
-
-  Status = gBS->LocateProtocol (
-                  &gEfiDevicePathFromTextProtocolGuid,
-                  NULL,
-                  (VOID**)&DevicePathFromTextProtocol
-                  );
-  ASSERT_EFI_ERROR(Status);
-
-  BdsLoadOption->FilePathList = DevicePathFromTextProtocol->ConvertTextToDevicePath (DevicePathText);
-  ASSERT (BdsLoadOption->FilePathList != NULL);
-  BdsLoadOption->FilePathListLength = GetDevicePathSize (BdsLoadOption->FilePathList);
-  BdsLoadOption->Attributes = LOAD_OPTION_ACTIVE | (LoadOption & LOAD_OPTION_CATEGORY);
-
-  if (BootArgs) {
-    /* Always force the BootArgs to save 512 characters. */
-    ASSERT (StrSize(BootArgs) <= 512 * sizeof (CHAR16));
-    BdsLoadOption->OptionalDataSize = 512 * sizeof (CHAR16);
-    BdsLoadOption->OptionalData = (CHAR16*)AllocateZeroPool (BdsLoadOption->OptionalDataSize);
-    ASSERT (BdsLoadOption->OptionalData != NULL);
-    StrCpy (BdsLoadOption->OptionalData, BootArgs);
-  }
-
-  BdsLoadOption->LoadOptionIndex = mBootCount;
-  DescriptionSize = StrSize (BootDescription);
-  BdsLoadOption->Description = (VOID*)AllocateZeroPool (DescriptionSize);
-  StrCpy (BdsLoadOption->Description, BootDescription);
-
-  BdsLoadOption->LoadOptionSize = sizeof(UINT32) + sizeof(UINT16) + DescriptionSize + BdsLoadOption->FilePathListLength + BdsLoadOption->OptionalDataSize;
-  BdsLoadOption->LoadOption = (EFI_LOAD_OPTION*)AllocateZeroPool (BdsLoadOption->LoadOptionSize);
-  ASSERT (BdsLoadOption->LoadOption != NULL);
-
-  EfiLoadOptionPtr = (VOID*)BdsLoadOption->LoadOption;
-
-  //
-  // Populate the EFI Load Option and BDS Boot Option structures
-  //
-
-  // Attributes fields
-  *(UINT32*)EfiLoadOptionPtr = BdsLoadOption->Attributes;
-  EfiLoadOptionPtr += sizeof(UINT32);
-
-  // FilePath List fields
-  *(UINT16*)EfiLoadOptionPtr = BdsLoadOption->FilePathListLength;
-  EfiLoadOptionPtr += sizeof(UINT16);
-
-  // Boot description fields
-  CopyMem (EfiLoadOptionPtr, BdsLoadOption->Description, DescriptionSize);
-  EfiLoadOptionPtr += DescriptionSize;
-
-  // File path fields
-  DevicePathNode = BdsLoadOption->FilePathList;
-  while (!IsDevicePathEndType (DevicePathNode)) {
-    NodeLength = DevicePathNodeLength(DevicePathNode);
-    CopyMem (EfiLoadOptionPtr, DevicePathNode, NodeLength);
-    EfiLoadOptionPtr += NodeLength;
-    DevicePathNode = NextDevicePathNode (DevicePathNode);
-  }
-
-  // Set the End Device Path Type
-  SetDevicePathEndNode (EfiLoadOptionPtr);
-  EfiLoadOptionPtr += sizeof(EFI_DEVICE_PATH);
-
-  // Fill the Optional Data
-  if (BdsLoadOption->OptionalDataSize > 0) {
-    CopyMem (EfiLoadOptionPtr, BdsLoadOption->OptionalData, BdsLoadOption->OptionalDataSize);
-  }
-
-  Status = gRT->SetVariable (
-                  BootVariableName,
-                  &gEfiGlobalVariableGuid,
-                  EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
-                  BdsLoadOption->LoadOptionSize,
-                  BdsLoadOption->LoadOption
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to set BootVariable\n", __func__));
-    return Status;
-  }
-
-done:
-  BootOrderSize = mBootCount * sizeof (UINT16);
-  mBootOrder = ReallocatePool (BootOrderSize, BootOrderSize + sizeof (UINT16), mBootOrder);
-  mBootOrder[mBootCount] = mBootCount;
-  mBootCount++;
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-EFIAPI
-HiKeyCreateBootOrder (
-  IN    VOID
-  )
-{
-  UINT16             *BootOrder;
-  UINTN               BootOrderSize;
-  UINTN               Index;
-  EFI_STATUS          Status;
-
-  Status = GetGlobalEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
-  if (EFI_ERROR(Status) == 0) {
-    if (BootOrderSize == mBootCount) {
-      for (Index = 0; Index < mBootCount; Index++) {
-        if (BootOrder[Index] != mBootOrder[Index]) {
-          break;
-        }
-      }
-      if (Index == mBootCount) {
-        // Found BootOrder variable with expected value.
-        return EFI_SUCCESS;
-      }
-    }
-  }
-
-  Status = gRT->SetVariable (
-                  (CHAR16*)L"BootOrder",
-                  &gEfiGlobalVariableGuid,
-                  EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
-                  mBootCount * sizeof(UINT16),
-                  mBootOrder
-                  );
-  return Status;
-}
-
-STATIC
-EFI_STATUS
-EFIAPI
-HiKeyCreateBootNext (
-  IN     VOID
-  )
-{
-  EFI_STATUS          Status;
-  UINT16             *BootNext;
-  UINTN               BootNextSize;
-
-  BootNextSize = sizeof(UINT16);
-  Status = GetGlobalEnvironmentVariable (L"BootNext", NULL, &BootNextSize, (VOID**)&BootNext);
-  if (EFI_ERROR(Status) == 0) {
-    if (BootNextSize == sizeof (UINT16)) {
-      if (*BootNext == mBootOrder[mBootIndex]) {
-        // Found the BootNext variable with expected value.
-        return EFI_SUCCESS;
-      }
-    }
-  }
-  BootNext = &mBootOrder[mBootIndex];
-  Status = gRT->SetVariable (
-                  (CHAR16*)L"BootNext",
-                  &gEfiGlobalVariableGuid,
-                  EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
-                  sizeof (UINT16),
-                  BootNext
-                  );
-  return Status;
-}
-
-STATIC
-VOID
-EFIAPI
-HiKeyTestLed (
-  IN     EMBEDDED_GPIO   *Gpio
-  )
-{
-  EFI_STATUS             Status;
-
-  Status = Gpio->Set (Gpio, USER_LED1, GPIO_MODE_OUTPUT_0);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to set LED1\n", __func__));
-    return;
-  }
-  Status = Gpio->Set (Gpio, USER_LED2, GPIO_MODE_OUTPUT_1);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to set LED2\n", __func__));
-    return;
-  }
-  Status = Gpio->Set (Gpio, USER_LED3, GPIO_MODE_OUTPUT_0);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to set LED3\n", __func__));
-    return;
-  }
-  Status = Gpio->Set (Gpio, USER_LED4, GPIO_MODE_OUTPUT_1);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to set LED4\n", __func__));
-    return;
-  }
-}
-
-
-#define REBOOT_REASON_ADDR		0x05F01000
-#define REBOOT_REASON_BOOTLOADER	0x77665500
-#define REBOOT_REASON_NONE		0x77665501
-STATIC
-BOOLEAN
-EFIAPI
-HiKeyDetectRebootReason (
-  IN     VOID
-  )
-{
-   UINT32 *addr = (UINT32*)REBOOT_REASON_ADDR;
-   UINT32  val;
-
-   val = *addr;
-   /* Write NONE to the reason address to clear the state */
-   *addr = REBOOT_REASON_NONE;
-   /* Check to see if "reboot booloader" was specified */
-   if (val == REBOOT_REASON_BOOTLOADER)
-     return TRUE;
-
-   return FALSE;
-}
-
-STATIC
-BOOLEAN
-EFIAPI
-HiKeyIsJumperConnected (
-  IN     VOID
-  )
-{
-  EMBEDDED_GPIO         *Gpio;
-  EFI_STATUS             Status;
-  UINTN                  Value;
-
-  Status = gBS->LocateProtocol (&gEmbeddedGpioProtocolGuid, NULL, (VOID **)&Gpio);
-  ASSERT_EFI_ERROR (Status);
-
-  Status = Gpio->Set (Gpio, DETECT_J15_FASTBOOT, GPIO_MODE_INPUT);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to set jumper as gpio input\n", __func__));
-    return FALSE;
-  }
-  Status = Gpio->Get (Gpio, DETECT_J15_FASTBOOT, &Value);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to get value from jumper\n", __func__));
-    return FALSE;
-  }
-
-  HiKeyTestLed (Gpio);
-  if (Value != 0)
-    return FALSE;
-  return TRUE;
-}
-
-STATIC
-BOOLEAN
-EFIAPI
-HiKeySDCardIsPresent (
-  IN      VOID
-  )
-{
-  UINT32    Value;
-
-  /*
-   * FIXME
-   * At first, reading GPIO pin shouldn't exist in SD driver. We need to
-   * add some callbacks to handle settings for hardware platform.
-   * In the second, reading GPIO pin should be based on GPIO driver. Now
-   * GPIO driver could only be used for one PL061 gpio controller. And it's
-   * used to detect jumper setting. As a workaround, we have to read the gpio
-   * register instead at here.
-   *
-   */
-  Value = MmioRead32 (0xf8012000 + (1 << 2));
-  if (Value)
-    return FALSE;
-  return TRUE;
-}
-
-#define BOOT_MAGIC        "ANDROID!"
-#define BOOT_MAGIC_LENGTH sizeof (BOOT_MAGIC) - 1
-
-/*
- * Check which boot type is valid for eMMC.
- */
-STATIC
-EFI_STATUS
-EFIAPI
-HiKeyCheckEmmcDtbType (
-  OUT UINTN       *DtbType
-  )
-{
-  EFI_DEVICE_PATH_PROTOCOL        *BlockDevicePath;
-  EFI_BLOCK_IO_PROTOCOL           *BlockIoProtocol;
-  EFI_HANDLE                      Handle;
-  EFI_STATUS                      Status;
-  VOID                            *DataPtr, *AlignedPtr;
-
-  /* Check boot image */
-  BlockDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdBootImagePath));
-  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &BlockDevicePath, &Handle);
-  ASSERT_EFI_ERROR (Status);
-
-  Status = gBS->OpenProtocol (
-                      Handle,
-                      &gEfiBlockIoProtocolGuid,
-                      (VOID **) &BlockIoProtocol,
-                      gImageHandle,
-                      NULL,
-                      EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                      );
-  ASSERT_EFI_ERROR (Status);
-
-  /* Read the header of boot image. */
-  DataPtr = AllocateZeroPool (HIKEY_IO_BLOCK_SIZE * 2);
-  ASSERT (DataPtr != 0);
-  AlignedPtr = (VOID *)(((UINTN)DataPtr + HIKEY_IO_BLOCK_SIZE - 1) & ~(HIKEY_IO_BLOCK_SIZE - 1));
-  InvalidateDataCacheRange (AlignedPtr, HIKEY_IO_BLOCK_SIZE);
-  /* TODO: Update 0x7000 by LBA what is fetched from partition. */
-  Status = BlockIoProtocol->ReadBlocks (BlockIoProtocol, BlockIoProtocol->Media->MediaId,
-                                        0x7000, HIKEY_IO_BLOCK_SIZE, AlignedPtr);
-  ASSERT_EFI_ERROR (Status);
-  if (AsciiStrnCmp ((CHAR8 *)AlignedPtr, BOOT_MAGIC, BOOT_MAGIC_LENGTH) != 0) {
-    /* It's debian boot image. */
-    *DtbType = HIKEY_DTB_LINUX;
-  } else {
-    /* It's android boot image. */
-    *DtbType = HIKEY_DTB_ANDROID;
-  }
-  FreePool (DataPtr);
-  return Status;
-}
-
-STATIC
-BOOLEAN
-EFIAPI
-HiKeyIsSdBoot (
-  IN struct HiKeyBootEntry    *Entry
-  )
-{
-  CHAR16                           *Path;
-  EFI_DEVICE_PATH                  *DevicePath, *NextDevicePath;
-  EFI_STATUS                        Status;
-  EFI_HANDLE                        Handle;
-  EFI_SIMPLE_FILE_SYSTEM_PROTOCOL  *FsProtocol;
-  EFI_FILE_PROTOCOL                *Fs;
-  EFI_FILE_INFO                    *FileInfo;
-  EFI_FILE_PROTOCOL                *File;
-  FILEPATH_DEVICE_PATH             *FilePathDevicePath;
-  UINTN                             Index, Size;
-  UINTN                             HandleCount;
-  EFI_HANDLE                       *HandleBuffer;
-  EFI_DEVICE_PATH_PROTOCOL         *DevicePathProtocol;
-  BOOLEAN                           Found = FALSE, Result = FALSE;
-
-  if (HiKeySDCardIsPresent () == FALSE)
-    return FALSE;
-  Path = Entry[HIKEY_BOOT_ENTRY_BOOT_SD].Path;
-  ASSERT (Path != NULL);
-
-  DevicePath = ConvertTextToDevicePath (Path);
-  if (DevicePath == NULL) {
-    DEBUG ((EFI_D_ERROR, "Warning: Couldn't get device path\n"));
-    return FALSE;
-  }
-
-  /* Connect handles to drivers. Since simple filesystem driver is loaded later by default. */
-  do {
-    // Locate all the driver handles
-    Status = gBS->LocateHandleBuffer (
-                AllHandles,
-                NULL,
-                NULL,
-                &HandleCount,
-                &HandleBuffer
-                );
-    if (EFI_ERROR (Status)) {
-      break;
-    }
-
-    // Connect every handles
-    for (Index = 0; Index < HandleCount; Index++) {
-      gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);
-    }
-
-    if (HandleBuffer != NULL) {
-      FreePool (HandleBuffer);
-    }
-
-    // Check if new handles have been created after the start of the previous handles
-    Status = gDS->Dispatch ();
-  } while (!EFI_ERROR(Status));
-
-  // List all the Simple File System Protocols
-  Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleFileSystemProtocolGuid, NULL, &HandleCount, &HandleBuffer);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Failed to list all the simple filesystem protocols (status:%r)\n", Status));
-    return FALSE;
-  }
-  for (Index = 0; Index < HandleCount; Index++) {
-    Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
-    if (EFI_ERROR(Status))
-      continue;
-    NextDevicePath = NextDevicePathNode (DevicePath);
-    Size = (UINTN)NextDevicePath - (UINTN)DevicePath;
-    if (Size <= GetDevicePathSize (DevicePath)) {
-      if ((CompareMem (DevicePath, DevicePathProtocol, Size)) == 0) {
-	Found = TRUE;
-        break;
-      }
-    }
-  }
-  if (!Found) {
-    DEBUG ((EFI_D_ERROR, "Warning: Failed to find valid device path\n"));
-    return FALSE;
-  }
-
-  Handle = HandleBuffer[Index];
-  Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid, &DevicePath, &Handle);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Couldn't locate device (status: %r)\n", Status));
-    return FALSE;
-  }
-  FilePathDevicePath = (FILEPATH_DEVICE_PATH*)DevicePath;
-
-  Status = gBS->OpenProtocol (
-                  Handle,
-                  &gEfiSimpleFileSystemProtocolGuid,
-                  (VOID**)&FsProtocol,
-                  gImageHandle,
-                  Handle,
-                  EFI_OPEN_PROTOCOL_BY_DRIVER
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Failedn't to mount as Simple Filrsystem (status: %r)\n", Status));
-    return FALSE;
-  }
-  Status = FsProtocol->OpenVolume (FsProtocol, &Fs);
-  if (EFI_ERROR (Status)) {
-    goto CLOSE_PROTOCOL;
-  }
-
-  Status = Fs->Open (Fs, &File, FilePathDevicePath->PathName, EFI_FILE_MODE_READ, 0);
-  if (EFI_ERROR (Status)) {
-    goto CLOSE_PROTOCOL;
-  }
-
-  Size = 0;
-  File->GetInfo (File, &gEfiFileInfoGuid, &Size, NULL);
-  FileInfo = AllocatePool (Size);
-  Status = File->GetInfo (File, &gEfiFileInfoGuid, &Size, FileInfo);
-  if (EFI_ERROR (Status)) {
-    goto CLOSE_FILE;
-  }
-
-  // Get the file size
-  Size = FileInfo->FileSize;
-  FreePool (FileInfo);
-  if (Size != 0) {
-    Result = TRUE;
-  }
-
-CLOSE_FILE:
-  File->Close (File);
-CLOSE_PROTOCOL:
-  gBS->CloseProtocol (
-         Handle,
-         &gEfiSimpleFileSystemProtocolGuid,
-         gImageHandle,
-         Handle);
-  return Result;
-}
-
-STATIC
-EFI_STATUS
-EFIAPI
-HiKeyInstallFdt (
-  VOID
-  )
-{
-  EFI_STATUS              Status;
-  VOID                   *Image;
-  UINTN                   ImageSize, NumPages;
-  EFI_GUID               *Guid;
-  EFI_PHYSICAL_ADDRESS    FdtConfigurationTableBase;
-
-  Guid = &gHiKeyTokenSpaceGuid;
-  Status = GetSectionFromAnyFv (Guid, EFI_SECTION_RAW, 0, &Image, &ImageSize);
-  if (EFI_ERROR (Status))
-    return Status;
-  NumPages = EFI_SIZE_TO_PAGES (ImageSize);
-  Status = gBS->AllocatePages (
-		  AllocateAnyPages, EfiRuntimeServicesData,
-		  NumPages, &FdtConfigurationTableBase
-		  );
-  if (EFI_ERROR (Status))
-    return Status;
-  CopyMem ((VOID *)(UINTN)FdtConfigurationTableBase, Image, ImageSize);
-  Status = gBS->InstallConfigurationTable (
-		  &gFdtTableGuid,
-		  (VOID *)(UINTN)FdtConfigurationTableBase
-		  );
-  if (EFI_ERROR (Status)) {
-    gBS->FreePages (FdtConfigurationTableBase, NumPages);
-  }
-  return Status;
-}
-
-STATIC
-VOID
-EFIAPI
-HiKeyOnEndOfDxe (
-  EFI_EVENT                               Event,
-  VOID                                    *Context
-  )
-{
-  EFI_STATUS          Status;
-  UINTN               VariableSize;
-  UINT16              AutoBoot, Count, Index;
-  UINTN               DtbType;
-  struct HiKeyBootEntry *Entry;
-
-  VariableSize = sizeof (UINT16);
-  Status = gRT->GetVariable (
-                  (CHAR16 *)L"HiKeyAutoBoot",
-                  &gHiKeyVariableGuid,
-                  NULL,
-                  &VariableSize,
-                  (VOID*)&AutoBoot
-                  );
-  if (Status == EFI_NOT_FOUND) {
-    AutoBoot = 1;
-    Status = gRT->SetVariable (
-                    (CHAR16*)L"HiKeyAutoBoot",
-                    &gHiKeyVariableGuid,
-                    EFI_VARIABLE_NON_VOLATILE       |
-                    EFI_VARIABLE_BOOTSERVICE_ACCESS |
-                    EFI_VARIABLE_RUNTIME_ACCESS,
-                    sizeof (UINT16),
-                    &AutoBoot
-                    );
-    ASSERT_EFI_ERROR (Status);
-  } else if (EFI_ERROR (Status) == 0) {
-    if (AutoBoot == 0) {
-      // Select boot entry by manual.
-      // Delete the BootNext environment variable
-      gRT->SetVariable (L"BootNext",
-             &gEfiGlobalVariableGuid,
-             EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
-             0,
-             NULL);
-      return;
-    }
-  }
-
-  Status = HiKeyCheckEmmcDtbType (&DtbType);
-  ASSERT_EFI_ERROR (Status);
-
-  mBootCount = 0;
-  mBootOrder = NULL;
-
-  if (DtbType == HIKEY_DTB_LINUX) {
-    Count = sizeof (LinuxEntries) / sizeof (struct HiKeyBootEntry);
-    Entry = LinuxEntries;
-  } else if (DtbType == HIKEY_DTB_ANDROID) {
-    Count = sizeof (AndroidEntries) / sizeof (struct HiKeyBootEntry);
-    Entry = AndroidEntries;
-  } else {
-    ASSERT (0);
-  }
-  ASSERT (HIKEY_DTB_SD < Count);
-  if (HiKeyIsSdBoot (Entry) == TRUE)
-    DtbType = HIKEY_DTB_SD;
-
-  for (Index = 0; Index < Count; Index++) {
-    Status = HiKeyCreateBootEntry (
-               Entry->Path,
-               Entry->Args,
-               Entry->Description,
-               Entry->LoadType
-               );
-    ASSERT_EFI_ERROR (Status);
-    Entry++;
-  }
-
-  if ((mBootCount == 0) || (mBootCount >= MAX_BOOT_ENTRIES)) {
-    DEBUG ((EFI_D_ERROR, "%a: can't create boot entries\n", __func__));
-    return;
-  }
-
-  Status = HiKeyCreateBootOrder ();
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to set BootOrder variable\n", __func__));
-    return;
-  }
-
-  if (DtbType == HIKEY_DTB_SD) {
-    mBootIndex = HIKEY_BOOT_ENTRY_BOOT_SD;
-  } else {
-    mBootIndex = HIKEY_BOOT_ENTRY_BOOT_EMMC;
-  }
-
-  if (HiKeyGetUsbMode () == USB_DEVICE_MODE) {
-    if (HiKeyIsJumperConnected () == TRUE)
-      mBootIndex = HIKEY_BOOT_ENTRY_FASTBOOT;
-    /* Set mBootIndex as HIKEY_BOOT_ENTRY_FASTBOOT if adb reboot-bootloader is specified */
-    if (HiKeyDetectRebootReason () == TRUE)
-      mBootIndex = HIKEY_BOOT_ENTRY_FASTBOOT;
-  }
-
-  Status = HiKeyCreateBootNext ();
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to set BootNext variable\n", __func__));
-    return;
-  }
-
-  /*
-   * Priority of Loading DTB file:
-   *   1. Load configured DTB file in grub.cfg.
-   *   2. Load DTB file in UEFI Fv.
-   */
-  /* Load DTB file in UEFI Fv. */
-  Status = HiKeyInstallFdt ();
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "%a: failed to install Fdt file\n", __func__));
-    return;
-  }
-}
-
-EFI_STATUS
-HiKeyBootMenuInstall (
-  IN VOID
-  )
-{
-  EFI_STATUS          Status;
-  EFI_EVENT           EndOfDxeEvent;
-
-  Status = gBS->CreateEventEx (
-                  EVT_NOTIFY_SIGNAL,
-                  TPL_CALLBACK,
-                  HiKeyOnEndOfDxe,
-                  &mIsEndOfDxeEvent,
-                  &gEfiEndOfDxeEventGroupGuid,
-                  &EndOfDxeEvent
-                  );
-  ASSERT_EFI_ERROR (Status);
-  return Status;
-}
-
diff --git a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastboot.c b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastboot.c
deleted file mode 100644
index 55ea92a..0000000
--- a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastboot.c
+++ /dev/null
@@ -1,889 +0,0 @@
-/** @file
-
-  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
-  Copyright (c) 2015, Linaro Ltd. All rights reserved.
-  Copyright (c) 2015, Hisilicon Ltd. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-/*
-  Implementation of the Android Fastboot Platform protocol, to be used by the
-  Fastboot UEFI application, for Hisilicon HiKey platform.
-*/
-
-#include <Protocol/AndroidFastbootPlatform.h>
-#include <Protocol/BlockIo.h>
-#include <Protocol/DiskIo.h>
-#include <Protocol/EraseBlock.h>
-#include <Protocol/SimpleTextOut.h>
-
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/PrintLib.h>
-#include <Library/TimerLib.h>
-
-#include <Guid/HiKeyVariable.h>
-
-#define FLASH_DEVICE_PATH_SIZE(DevPath) ( GetDevicePathSize (DevPath) - \
-                                            sizeof (EFI_DEVICE_PATH_PROTOCOL))
-
-#define PARTITION_NAME_MAX_LENGTH 72/2
-
-#define IS_ALPHA(Char) (((Char) <= L'z' && (Char) >= L'a') || \
-                        ((Char) <= L'Z' && (Char) >= L'A'))
-#define IS_HEXCHAR(Char) (((Char) <= L'9' && (Char) >= L'0') || \
-                          IS_ALPHA(Char))
-
-#define SERIAL_NUMBER_LENGTH      16
-#define BOOT_DEVICE_LENGTH        16
-
-#define HIKEY_ERASE_SIZE          4096
-
-typedef struct _FASTBOOT_PARTITION_LIST {
-  LIST_ENTRY  Link;
-  CHAR16      PartitionName[PARTITION_NAME_MAX_LENGTH];
-  EFI_HANDLE  PartitionHandle;
-  EFI_LBA     Lba;
-} FASTBOOT_PARTITION_LIST;
-
-STATIC LIST_ENTRY mPartitionListHead;
-
-STATIC EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *mTextOut;
-
-/*
-  Helper to free the partition list
-*/
-STATIC
-VOID
-FreePartitionList (
-  VOID
-  )
-{
-  FASTBOOT_PARTITION_LIST *Entry;
-  FASTBOOT_PARTITION_LIST *NextEntry;
-
-  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead);
-  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
-    NextEntry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &Entry->Link);
-
-    RemoveEntryList (&Entry->Link);
-    FreePool (Entry);
-
-    Entry = NextEntry;
-  }
-}
-/*
-  Read the PartitionName fields from the GPT partition entries, putting them
-  into an allocated array that should later be freed.
-*/
-STATIC
-EFI_STATUS
-ReadPartitionEntries (
-  IN  EFI_BLOCK_IO_PROTOCOL *BlockIo,
-  OUT EFI_PARTITION_ENTRY  **PartitionEntries
-  )
-{
-  UINTN                       EntrySize;
-  UINTN                       NumEntries;
-  UINTN                       BufferSize;
-  UINT32                      MediaId;
-  EFI_PARTITION_TABLE_HEADER *GptHeader;
-  EFI_STATUS                  Status;
-
-  MediaId = BlockIo->Media->MediaId;
-
-  //
-  // Read size of Partition entry and number of entries from GPT header
-  //
-
-  GptHeader = AllocatePool (BlockIo->Media->BlockSize);
-  if (GptHeader == NULL) {
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  Status = BlockIo->ReadBlocks (BlockIo, MediaId, 1, BlockIo->Media->BlockSize, (VOID *) GptHeader);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  // Check there is a GPT on the media
-  if (GptHeader->Header.Signature != EFI_PTAB_HEADER_ID ||
-      GptHeader->MyLBA != 1) {
-    DEBUG ((EFI_D_ERROR,
-      "Fastboot platform: No GPT on flash. "
-      "Fastboot on Versatile Express does not support MBR.\n"
-      ));
-    return EFI_DEVICE_ERROR;
-  }
-
-  EntrySize = GptHeader->SizeOfPartitionEntry;
-  NumEntries = GptHeader->NumberOfPartitionEntries;
-
-  FreePool (GptHeader);
-
-  ASSERT (EntrySize != 0);
-  ASSERT (NumEntries != 0);
-
-  BufferSize = ALIGN_VALUE (EntrySize * NumEntries, BlockIo->Media->BlockSize);
-  *PartitionEntries = AllocatePool (BufferSize);
-  if (PartitionEntries == NULL) {
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  Status = BlockIo->ReadBlocks (BlockIo, MediaId, 2, BufferSize, (VOID *) *PartitionEntries);
-  if (EFI_ERROR (Status)) {
-    FreePool (PartitionEntries);
-    return Status;
-  }
-
-  return Status;
-}
-
-
-EFI_STATUS
-HiKeyFastbootLoadPtable (
-  VOID
-  )
-{
-  EFI_STATUS                          Status;
-  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePath;
-  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePathDup;
-  EFI_DEVICE_PATH_PROTOCOL           *DevicePath;
-  EFI_DEVICE_PATH_PROTOCOL           *NextNode;
-  HARDDRIVE_DEVICE_PATH              *PartitionNode;
-  UINTN                               NumHandles;
-  EFI_HANDLE                         *AllHandles;
-  UINTN                               LoopIndex;
-  EFI_HANDLE                          FlashHandle;
-  EFI_BLOCK_IO_PROTOCOL              *FlashBlockIo;
-  EFI_PARTITION_ENTRY                *PartitionEntries;
-  FASTBOOT_PARTITION_LIST            *Entry;
-
-  // Free any entries in partitionlist
-    FreePartitionList ();
-
-  //
-  // Get EFI_HANDLES for all the partitions on the block devices pointed to by
-  // PcdFastbootFlashDevicePath, also saving their GPT partition labels.
-  // There's no way to find all of a device's children, so we get every handle
-  // in the system supporting EFI_BLOCK_IO_PROTOCOL and then filter out ones
-  // that don't represent partitions on the flash device.
-  //
-
-  FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
-
-  //
-  // Open the Disk IO protocol on the flash device - this will be used to read
-  // partition names out of the GPT entries
-  //
-  // Create another device path pointer because LocateDevicePath will modify it.
-  FlashDevicePathDup = FlashDevicePath;
-  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePathDup, &FlashHandle);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
-    // Failing to locate partitions should not prevent to do other Android FastBoot actions
-    return EFI_SUCCESS;
-  }
-
-  Status = gBS->OpenProtocol (
-                  FlashHandle,
-                  &gEfiBlockIoProtocolGuid,
-                  (VOID **) &FlashBlockIo,
-                  gImageHandle,
-                  NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Fastboot platform: Couldn't open Android NVM device (status: %r)\n", Status));
-    return EFI_DEVICE_ERROR;
-  }
-
-  // Read the GPT partition entry array into memory so we can get the partition names
-  Status = ReadPartitionEntries (FlashBlockIo, &PartitionEntries);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Warning: Failed to read partitions from Android NVM device (status: %r)\n", Status));
-    // Failing to locate partitions should not prevent to do other Android FastBoot actions
-    return EFI_SUCCESS;
-  }
-
-  // Get every Block IO protocol instance installed in the system
-  Status = gBS->LocateHandleBuffer (
-                  ByProtocol,
-                  &gEfiBlockIoProtocolGuid,
-                  NULL,
-                  &NumHandles,
-                  &AllHandles
-                  );
-  ASSERT_EFI_ERROR (Status);
-
-  // Filter out handles that aren't children of the flash device
-  for (LoopIndex = 0; LoopIndex < NumHandles; LoopIndex++) {
-    // Get the device path for the handle
-    Status = gBS->OpenProtocol (
-                    AllHandles[LoopIndex],
-                    &gEfiDevicePathProtocolGuid,
-                    (VOID **) &DevicePath,
-                    gImageHandle,
-                    NULL,
-                    EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                    );
-    ASSERT_EFI_ERROR (Status);
-
-    // Check if it is a sub-device of the flash device
-    if (!CompareMem (DevicePath, FlashDevicePath, FLASH_DEVICE_PATH_SIZE (FlashDevicePath))) {
-      // Device path starts with path of flash device. Check it isn't the flash
-      // device itself.
-      NextNode = NextDevicePathNode (DevicePath);
-      if (IsDevicePathEndType (NextNode)) {
-        // Create entry
-        Entry = AllocatePool (sizeof (FASTBOOT_PARTITION_LIST));
-        if (Entry == NULL) {
-          Status = EFI_OUT_OF_RESOURCES;
-          FreePartitionList ();
-          goto Exit;
-        }
-
-        // Copy handle and partition name
-        Entry->PartitionHandle = AllHandles[LoopIndex];
-        StrCpy (Entry->PartitionName, L"ptable");
-        InsertTailList (&mPartitionListHead, &Entry->Link);
-        continue;
-      }
-
-      // Assert that this device path node represents a partition.
-      ASSERT (NextNode->Type == MEDIA_DEVICE_PATH &&
-              NextNode->SubType == MEDIA_HARDDRIVE_DP);
-
-      PartitionNode = (HARDDRIVE_DEVICE_PATH *) NextNode;
-
-      // Assert that the partition type is GPT. ReadPartitionEntries checks for
-      // presence of a GPT, so we should never find MBR partitions.
-      // ("MBRType" is a misnomer - this field is actually called "Partition
-      //  Format")
-      ASSERT (PartitionNode->MBRType == MBR_TYPE_EFI_PARTITION_TABLE_HEADER);
-
-      // The firmware may install a handle for "partition 0", representing the
-      // whole device. Ignore it.
-      if (PartitionNode->PartitionNumber == 0) {
-        continue;
-      }
-
-      //
-      // Add the partition handle to the list
-      //
-
-      // Create entry
-      Entry = AllocatePool (sizeof (FASTBOOT_PARTITION_LIST));
-      if (Entry == NULL) {
-        Status = EFI_OUT_OF_RESOURCES;
-        FreePartitionList ();
-        goto Exit;
-      }
-
-      // Copy handle and partition name
-      Entry->PartitionHandle = AllHandles[LoopIndex];
-      StrnCpy (
-        Entry->PartitionName,
-        PartitionEntries[PartitionNode->PartitionNumber - 1].PartitionName, // Partition numbers start from 1.
-        PARTITION_NAME_MAX_LENGTH
-        );
-      Entry->Lba = PartitionEntries[PartitionNode->PartitionNumber - 1].StartingLBA;
-      InsertTailList (&mPartitionListHead, &Entry->Link);
-
-      // Print a debug message if the partition label is empty or looks like
-      // garbage.
-      if (!IS_ALPHA (Entry->PartitionName[0])) {
-        DEBUG ((EFI_D_ERROR,
-          "Warning: Partition %d doesn't seem to have a GPT partition label. "
-          "You won't be able to flash it with Fastboot.\n",
-          PartitionNode->PartitionNumber
-          ));
-      }
-    }
-  }
-
-Exit:
-  FreePool (PartitionEntries);
-  FreePool (FlashDevicePath);
-  FreePool (AllHandles);
-  return Status;
-}
-
-
-/*
-  Initialise: Open the Android NVM device and find the partitions on it. Save them in
-  a list along with the "PartitionName" fields for their GPT entries.
-  We will use these partition names as the key in
-  HiKeyFastbootPlatformFlashPartition.
-*/
-EFI_STATUS
-HiKeyFastbootPlatformInit (
-  VOID
-  )
-{
-  EFI_STATUS                          Status;
-
-  InitializeListHead (&mPartitionListHead);
-
-  Status = gBS->LocateProtocol (&gEfiSimpleTextOutProtocolGuid, NULL, (VOID **) &mTextOut);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR,
-      "Fastboot platform: Couldn't open Text Output Protocol: %r\n", Status
-      ));
-    return Status;
-  }
-  return HiKeyFastbootLoadPtable();
-}
-
-VOID
-HiKeyFastbootPlatformUnInit (
-  VOID
-  )
-{
-  FreePartitionList ();
-}
-
-EFI_STATUS
-HiKeyFastbootPlatformFlashPartition (
-  IN CHAR8  *PartitionName,
-  IN UINTN   Size,
-  IN VOID   *Image
-  )
-{
-  EFI_STATUS               Status;
-  EFI_BLOCK_IO_PROTOCOL   *BlockIo;
-  EFI_DISK_IO_PROTOCOL    *DiskIo;
-  UINT32                   MediaId;
-  UINTN                    PartitionSize;
-  FASTBOOT_PARTITION_LIST *Entry;
-  CHAR16                   PartitionNameUnicode[60];
-  BOOLEAN                  PartitionFound;
-  SPARSE_HEADER           *SparseHeader;
-  CHUNK_HEADER            *ChunkHeader;
-  UINTN                    Offset = 0;
-  UINT32                   Chunk, EntrySize, EntryOffset;
-  UINT32                  *FillVal, TmpCount, FillBuf[1024];
-  VOID                    *Buffer;
-
-
-  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
-
-  PartitionFound = FALSE;
-  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
-  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
-    // Search the partition list for the partition named by PartitionName
-    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
-      PartitionFound = TRUE;
-      break;
-    }
-
-   Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
-  }
-  if (!PartitionFound) {
-    return EFI_NOT_FOUND;
-  }
-
-  Status = gBS->OpenProtocol (
-                  Entry->PartitionHandle,
-                  &gEfiBlockIoProtocolGuid,
-                  (VOID **) &BlockIo,
-                  gImageHandle,
-                  NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for flash: %r\n", Status));
-    return EFI_NOT_FOUND;
-  }
-
-  SparseHeader=(SPARSE_HEADER *)Image;
-
-  if (SparseHeader->Magic == SPARSE_HEADER_MAGIC) {
-    DEBUG ((EFI_D_INFO, "Sparse Magic: 0x%x Major: %d Minor: %d fhs: %d chs: %d bs: %d tbs: %d tcs: %d checksum: %d \n",
-                SparseHeader->Magic, SparseHeader->MajorVersion, SparseHeader->MinorVersion,  SparseHeader->FileHeaderSize,
-                SparseHeader->ChunkHeaderSize, SparseHeader->BlockSize, SparseHeader->TotalBlocks,
-                SparseHeader->TotalChunks, SparseHeader->ImageChecksum));
-    if (SparseHeader->MajorVersion != 1) {
-        DEBUG ((EFI_D_ERROR, "Sparse image version %d.%d not supported.\n",
-                    SparseHeader->MajorVersion, SparseHeader->MinorVersion));
-        return EFI_INVALID_PARAMETER;
-    }
-
-    Size = SparseHeader->BlockSize * SparseHeader->TotalBlocks;
-  }
-
-  // Check image will fit on device
-  PartitionSize = (BlockIo->Media->LastBlock + 1) * BlockIo->Media->BlockSize;
-  if (PartitionSize < Size) {
-    DEBUG ((EFI_D_ERROR, "Partition not big enough.\n"));
-    DEBUG ((EFI_D_ERROR, "Partition Size:\t%ld\nImage Size:\t%ld\n", PartitionSize, Size));
-
-    return EFI_VOLUME_FULL;
-  }
-
-  MediaId = BlockIo->Media->MediaId;
-
-  Status = gBS->OpenProtocol (
-                  Entry->PartitionHandle,
-                  &gEfiDiskIoProtocolGuid,
-                  (VOID **) &DiskIo,
-                  gImageHandle,
-                  NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                  );
-  ASSERT_EFI_ERROR (Status);
-
-  if (SparseHeader->Magic == SPARSE_HEADER_MAGIC) {
-    CHAR16 OutputString[64];
-    UINTN ChunkPrintDensity =
-        SparseHeader->TotalChunks > 1600 ? SparseHeader->TotalChunks / 200 : 32;
-
-    Image += SparseHeader->FileHeaderSize;
-    for (Chunk = 0; Chunk < SparseHeader->TotalChunks; Chunk++) {
-      UINTN WriteSize;
-      ChunkHeader = (CHUNK_HEADER *)Image;
-
-      // Show progress. Don't do it for every packet as outputting text
-      // might be time consuming. ChunkPrintDensity is calculated to
-      // provide an update every half percent change for large
-      // downloads.
-      if (Chunk % ChunkPrintDensity == 0) {
-        UnicodeSPrint(OutputString, sizeof(OutputString),
-                      L"\r%5d / %5d chunks written (%d%%)", Chunk,
-                      SparseHeader->TotalChunks,
-                     (Chunk * 100) / SparseHeader->TotalChunks);
-        mTextOut->OutputString(mTextOut, OutputString);
-      }
-
-      DEBUG ((EFI_D_INFO, "Chunk #%d - Type: 0x%x Size: %d TotalSize: %d Offset %d\n",
-                  (Chunk+1), ChunkHeader->ChunkType, ChunkHeader->ChunkSize,
-                  ChunkHeader->TotalSize, Offset));
-      Image += sizeof(CHUNK_HEADER);
-      WriteSize=(SparseHeader->BlockSize) * ChunkHeader->ChunkSize;
-      switch (ChunkHeader->ChunkType) {
-        case CHUNK_TYPE_RAW:
-          DEBUG ((EFI_D_INFO, "Writing %d at Offset %d\n", WriteSize, Offset));
-          Status = DiskIo->WriteDisk (DiskIo, MediaId, Offset, WriteSize, Image);
-          if (EFI_ERROR (Status)) {
-            return Status;
-          }
-          Image+=WriteSize;
-          break;
-        case CHUNK_TYPE_FILL:
-          //Assume fillVal is 0, and we can skip here
-          FillVal = (UINT32 *)Image;
-          Image += sizeof(UINT32);
-          if (*FillVal != 0){
-            mTextOut->OutputString(mTextOut, OutputString);
-            for(TmpCount = 0; TmpCount < 1024; TmpCount++){
-                FillBuf[TmpCount] = *FillVal;
-            }
-            for (TmpCount= 0; TmpCount < WriteSize; TmpCount += sizeof(FillBuf)) {
-                if ((WriteSize - TmpCount) < sizeof(FillBuf)) {
-                  Status = DiskIo->WriteDisk (DiskIo, MediaId, Offset + TmpCount, WriteSize - TmpCount, FillBuf);
-                } else {
-                  Status = DiskIo->WriteDisk (DiskIo, MediaId, Offset + TmpCount, sizeof(FillBuf), FillBuf);
-                }
-                if (EFI_ERROR (Status)) {
-                    return Status;
-                }
-            }
-          }
-          break;
-        case CHUNK_TYPE_DONT_CARE:
-          break;
-        case CHUNK_TYPE_CRC32:
-          break;
-        default:
-          DEBUG ((EFI_D_ERROR, "Unknown Chunk Type: 0x%x", ChunkHeader->ChunkType));
-          return EFI_PROTOCOL_ERROR;
-      }
-      Offset += WriteSize;
-    }
-
-    UnicodeSPrint(OutputString, sizeof(OutputString),
-                  L"\r%5d / %5d chunks written (100%%)\r\n",
-                  SparseHeader->TotalChunks, SparseHeader->TotalChunks);
-    mTextOut->OutputString(mTextOut, OutputString);
-  } else {
-    if (AsciiStrCmp (PartitionName, "ptable") == 0) {
-      Buffer = Image;
-      if (AsciiStrnCmp (Buffer, "ENTRYHDR", 8) != 0) {
-        DEBUG ((EFI_D_ERROR, "unknown ptable image\n"));
-        return EFI_UNSUPPORTED;
-      }
-      Buffer += 8;
-      if (AsciiStrnCmp (Buffer, "primary", 7) != 0) {
-        DEBUG ((EFI_D_ERROR, "unknown ptable image\n"));
-        return EFI_UNSUPPORTED;
-      }
-      Buffer += 8;
-      EntryOffset = *(UINT32 *)Buffer * BlockIo->Media->BlockSize;
-      Buffer += 4;
-      EntrySize = *(UINT32 *)Buffer * BlockIo->Media->BlockSize;
-      if ((EntrySize + 512) > Size) {
-        DEBUG ((EFI_D_ERROR, "Entry size doesn't match\n"));
-        return EFI_UNSUPPORTED;
-      }
-      Buffer = Image + 512;
-      Status = DiskIo->WriteDisk (DiskIo, MediaId, EntryOffset, EntrySize, Buffer);
-      DEBUG ((EFI_D_ERROR, "Flashed Ptable hence reloading partition Entries for future flash commands\n"));
-      HiKeyFastbootLoadPtable();
-      if (EFI_ERROR (Status)) {
-        return Status;
-      }
-
-      Buffer = Image + 16 + 12;
-      if (AsciiStrnCmp (Buffer, "ENTRYHDR", 8) != 0)
-        return Status;
-      Buffer += 8;
-      if (AsciiStrnCmp (Buffer, "second", 6) != 0)
-        return Status;
-      Buffer += 8;
-      EntryOffset = *(UINT32 *)Buffer * BlockIo->Media->BlockSize;
-      Buffer += 4;
-      EntrySize = *(UINT32 *)Buffer * BlockIo->Media->BlockSize;
-      if ((EntrySize + 512) > Size) {
-        DEBUG ((EFI_D_ERROR, "Entry size doesn't match\n"));
-        return EFI_UNSUPPORTED;
-      }
-      Buffer = Image + 512;
-      Status = DiskIo->WriteDisk (DiskIo, MediaId, EntryOffset, EntrySize, Buffer);
-    } else {
-      Status = DiskIo->WriteDisk (DiskIo, MediaId, 0, Size, Image);
-    }
-    if (EFI_ERROR (Status)) {
-      return Status;
-    }
-  }
-
-  BlockIo->FlushBlocks(BlockIo);
-  MicroSecondDelay (50000);
-
-  return Status;
-}
-
-EFI_STATUS
-HiKeyFastbootPlatformErasePartition (
-  IN CHAR8 *PartitionName
-  )
-{
-  EFI_STATUS                Status;
-  EFI_BLOCK_IO_PROTOCOL    *BlockIo;
-  EFI_BLOCK_IO_PROTOCOL    *MmcBlockIo;
-  EFI_ERASE_BLOCK_PROTOCOL *EraseBlockProtocol;
-  UINT32                    MediaId;
-//  UINTN                    PartitionSize;
-  FASTBOOT_PARTITION_LIST  *Entry;
-  CHAR16                    PartitionNameUnicode[60];
-  BOOLEAN                   PartitionFound;
-  UINTN                     NumHandles;
-  EFI_HANDLE               *BufferHandle;
-
-  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
-
-  PartitionFound = FALSE;
-  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
-  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
-    // Search the partition list for the partition named by PartitionName
-    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
-      PartitionFound = TRUE;
-      break;
-    }
-
-   Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
-  }
-  if (!PartitionFound) {
-    return EFI_NOT_FOUND;
-  }
-
-  Status = gBS->OpenProtocol (
-                  Entry->PartitionHandle,
-                  &gEfiBlockIoProtocolGuid,
-                  (VOID **) &BlockIo,
-                  gImageHandle,
-                  NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for flash: %r\n", Status));
-    return EFI_NOT_FOUND;
-  }
-
-  Status = gBS->LocateProtocol (&gEfiEraseBlockProtocolGuid, NULL, (VOID **) &EraseBlockProtocol);
-  ASSERT_EFI_ERROR (Status);
-
-  Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiEraseBlockProtocolGuid, NULL, &NumHandles, &BufferHandle);
-  ASSERT_EFI_ERROR (Status);
-
-  Status = gBS->HandleProtocol (
-                  BufferHandle[0],
-                  &gEfiBlockIoProtocolGuid,
-                  (VOID **) &MmcBlockIo
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for MMC device: %r\n", Status));
-    return EFI_NOT_FOUND;
-  }
-
-  MediaId = BlockIo->Media->MediaId;
-
-
-//  PartitionSize = (BlockIo->Media->LastBlock + 1) * BlockIo->Media->BlockSize;
-//  if (AsciiStrnCmp (PartitionName, "ptable", 6) == 0) {
-    // partition table (GPT) cost 34 blocks
-//    PartitionSize = 34 * BlockIo->Media->BlockSize;
-//  }
-
-  Status = EraseBlockProtocol->EraseBlocks (MmcBlockIo, MediaId, Entry->Lba, NULL, BlockIo->Media->LastBlock);
-    if (EFI_ERROR (Status)) {
-      DEBUG ((EFI_D_ERROR, "%a: Fail to erase at address 0x%x\n", __func__, Entry->Lba));
-    }
-  return Status;
-}
-
-EFI_STATUS
-HiKeyFastbootPlatformGetVar (
-  IN  CHAR8   *Name,
-  OUT CHAR8   *Value
-  )
-{
-  EFI_STATUS               Status;
-  EFI_BLOCK_IO_PROTOCOL   *BlockIo;
-  UINT64                   PartitionSize;
-  FASTBOOT_PARTITION_LIST *Entry;
-  CHAR16                   PartitionNameUnicode[60];
-  BOOLEAN                  PartitionFound;
-  CHAR16                   DataUnicode[17];
-  UINTN                    VariableSize;
-
-  if (!AsciiStrCmp (Name, "max-download-size")) {
-    AsciiStrCpy (Value, FixedPcdGetPtr (PcdArmFastbootFlashLimit));
-  } else if (!AsciiStrCmp (Name, "product")) {
-    AsciiStrCpy (Value, FixedPcdGetPtr (PcdFirmwareVendor));
-  } else if (!AsciiStrCmp (Name, "serialno")) {
-    VariableSize = 17 * sizeof (CHAR16);
-    Status = gRT->GetVariable (
-                    (CHAR16 *)L"SerialNo",
-                    &gHiKeyVariableGuid,
-                    NULL,
-                    &VariableSize,
-                    &DataUnicode
-                    );
-    if (EFI_ERROR (Status)) {
-      *Value = '\0';
-      return EFI_NOT_FOUND;
-    }
-    DataUnicode[(VariableSize / sizeof(CHAR16)) - 1] = '\0';
-    UnicodeStrToAsciiStr (DataUnicode, Value);
-  } else if ( !AsciiStrnCmp (Name, "partition-size", 14)) {
-    AsciiStrToUnicodeStr ((Name + 15), PartitionNameUnicode);
-    PartitionFound = FALSE;
-    Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
-    while (!IsNull (&mPartitionListHead, &Entry->Link)) {
-      // Search the partition list for the partition named by PartitionName
-      if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
-        PartitionFound = TRUE;
-        break;
-      }
-
-     Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
-    }
-    if (!PartitionFound) {
-      *Value = '\0';
-      return EFI_NOT_FOUND;
-    }
-
-    Status = gBS->OpenProtocol (
-                    Entry->PartitionHandle,
-                    &gEfiBlockIoProtocolGuid,
-                    (VOID **) &BlockIo,
-                    gImageHandle,
-                    NULL,
-                    EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                    );
-    if (EFI_ERROR (Status)) {
-      DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for flash: %r\n", Status));
-      *Value = '\0';
-      return EFI_NOT_FOUND;
-    }
-
-    PartitionSize = (BlockIo->Media->LastBlock + 1) * BlockIo->Media->BlockSize;
-    DEBUG ((EFI_D_ERROR, "Fastboot platform: check for partition-size:%a 0X%llx\n", Name, PartitionSize ));
-    AsciiSPrint (Value, 12, "0x%llx", PartitionSize);
-  } else if ( !AsciiStrnCmp (Name, "partition-type", 14)) {
-      DEBUG ((EFI_D_ERROR, "Fastboot platform: check for partition-type:%a\n", (Name + 15) ));
-    if ( !AsciiStrnCmp  ( (Name + 15) , "system", 6) || !AsciiStrnCmp  ( (Name + 15) , "userdata", 8)
-            || !AsciiStrnCmp  ( (Name + 15) , "cache", 5)) {
-      AsciiStrCpy (Value, "ext4");
-    } else {
-      AsciiStrCpy (Value, "raw");
-    }
-  } else if ( !AsciiStrCmp (Name, "erase-block-size")) {
-    AsciiSPrint (Value, 12, "0x%llx", HIKEY_ERASE_SIZE);
-  } else if ( !AsciiStrCmp (Name, "logical-block-size")) {
-    AsciiSPrint (Value, 12, "0x%llx", HIKEY_ERASE_SIZE);
-  } else {
-    *Value = '\0';
-  }
-  return EFI_SUCCESS;
-}
-
-EFI_STATUS
-HiKeyFastbootPlatformOemCommand (
-  IN  CHAR8   *Command
-  )
-{
-  CHAR16     CommandUnicode[65];
-  UINTN      Index = 0, VariableSize;
-  UINT16     AutoBoot, Data;
-  EFI_STATUS Status;
-
-  if (AsciiStrCmp (Command, "Demonstrate") == 0) {
-    DEBUG ((EFI_D_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.\n"));
-    return EFI_SUCCESS;
-  } else if (AsciiStrnCmp (Command, "autoboot", AsciiStrLen ("autoboot")) == 0) {
-    Index += sizeof ("autoboot");
-    while (TRUE) {
-      if (Command[Index] == '\0')
-        goto out;
-      else if (Command[Index] == ' ')
-        Index++;
-      else
-        break;
-    }
-    Data = AsciiStrDecimalToUintn (Command + Index);
-
-    VariableSize = sizeof (UINT16);
-    Status = gRT->GetVariable (
-                    (CHAR16 *)L"HiKeyAutoBoot",
-                    &gHiKeyVariableGuid,
-                    NULL,
-                    &VariableSize,
-                    &AutoBoot
-                    );
-    if ((EFI_ERROR (Status) == 0) && (AutoBoot == Data)) {
-      return EFI_SUCCESS;
-    }
-    AutoBoot = Data;
-    Status = gRT->SetVariable (
-                    (CHAR16*)L"HiKeyAutoBoot",
-                    &gHiKeyVariableGuid,
-                    EFI_VARIABLE_NON_VOLATILE       |
-                    EFI_VARIABLE_BOOTSERVICE_ACCESS |
-                    EFI_VARIABLE_RUNTIME_ACCESS,
-                    sizeof (UINT16),
-                    &AutoBoot
-                    );
-    return Status;
-  } else {
-    AsciiStrToUnicodeStr (Command + Index, CommandUnicode);
-    DEBUG ((EFI_D_ERROR,
-      "HiKey: Unrecognised Fastboot OEM command: %s\n",
-      CommandUnicode
-      ));
-    return EFI_NOT_FOUND;
-  }
-out:
-  return EFI_NOT_FOUND;
-}
-
-EFI_STATUS
-HikeyFastbootPlatformReadPartition(
-  IN CHAR8     *PartitionName,
-  IN OUT UINTN *BufferSize,
-  OUT VOID    **Buffer
-  )
-{
-  EFI_STATUS               Status;
-  EFI_BLOCK_IO_PROTOCOL   *BlockIo;
-  UINT32                   MediaId;
-  UINTN                    PartitionSize;
-  FASTBOOT_PARTITION_LIST *Entry;
-  CHAR16                   PartitionNameUnicode[60];
-  BOOLEAN                  PartitionFound;
-
-  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
-
-  PartitionFound = FALSE;
-  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
-  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
-    // Search the partition list for the partition named by PartitionName
-    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
-      PartitionFound = TRUE;
-      break;
-    }
-
-    Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
-  }
-  if (!PartitionFound) {
-    return EFI_NOT_FOUND;
-  }
-
-  Status = gBS->OpenProtocol (
-                  Entry->PartitionHandle,
-                  &gEfiBlockIoProtocolGuid,
-                  (VOID **) &BlockIo,
-                  gImageHandle,
-                  NULL,
-                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
-                  );
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for read: %r\n", Status));
-    return EFI_NOT_FOUND;
-  }
-
-  // Check image will fit the memory
-  PartitionSize = (BlockIo->Media->LastBlock + 1) * BlockIo->Media->BlockSize;
-  if ((*BufferSize == 0) || (*BufferSize > PartitionSize))
-      *BufferSize = PartitionSize;
-  *Buffer = AllocatePages (EFI_SIZE_TO_PAGES(*BufferSize));
-  if (*Buffer == NULL) {
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  MediaId = BlockIo->Media->MediaId;
-  Status = BlockIo->ReadBlocks (BlockIo, MediaId, 0, *BufferSize, *Buffer);
-  if (EFI_ERROR (Status)) {
-    DEBUG ((EFI_D_ERROR, "Fastboot platform: Fail to read: %r\n", Status));
-  }
-  return Status;
-}
-
-FASTBOOT_PLATFORM_PROTOCOL mPlatformProtocol = {
-  HiKeyFastbootPlatformInit,
-  HiKeyFastbootPlatformUnInit,
-  HiKeyFastbootPlatformFlashPartition,
-  HiKeyFastbootPlatformErasePartition,
-  HiKeyFastbootPlatformGetVar,
-  HiKeyFastbootPlatformOemCommand,
-  HikeyFastbootPlatformReadPartition,
-};
-
-EFI_STATUS
-EFIAPI
-HiKeyFastbootPlatformEntryPoint (
-  IN EFI_HANDLE                            ImageHandle,
-  IN EFI_SYSTEM_TABLE                      *SystemTable
-  )
-{
-  return gBS->InstallProtocolInterface (
-                &ImageHandle,
-                &gAndroidFastbootPlatformProtocolGuid,
-                EFI_NATIVE_INTERFACE,
-                &mPlatformProtocol
-                );
-}
diff --git a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c
new file mode 100644
index 0000000..7e62ebb
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c
@@ -0,0 +1,653 @@
+/** @file
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/*
+  Implementation of the Android Fastboot Platform protocol, to be used by the
+  Fastboot UEFI application, for Hisilicon HiKey platform.
+*/
+
+#include <Protocol/AndroidFastbootPlatform.h>
+#include <Protocol/BlockIo.h>
+#include <Protocol/DiskIo.h>
+#include <Protocol/EraseBlock.h>
+#include <Protocol/SimpleTextOut.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UsbSerialNumberLib.h>
+#include <Library/PrintLib.h>
+#include <Library/TimerLib.h>
+
+#define PARTITION_NAME_MAX_LENGTH (72/2)
+
+#define SERIAL_NUMBER_LBA                1024
+#define RANDOM_MAX                       0x7FFFFFFFFFFFFFFF
+#define RANDOM_MAGIC                     0x9A4DBEAF
+
+#define ADB_REBOOT_ADDRESS               0x05F01000
+#define ADB_REBOOT_BOOTLOADER            0x77665500
+
+#define MMC_BLOCK_SIZE                   512
+#define HIKEY_ERASE_SIZE                 4096
+
+typedef struct _FASTBOOT_PARTITION_LIST {
+  LIST_ENTRY  Link;
+  CHAR16      PartitionName[PARTITION_NAME_MAX_LENGTH];
+  EFI_LBA     StartingLBA;
+  EFI_LBA     EndingLBA;
+} FASTBOOT_PARTITION_LIST;
+
+STATIC LIST_ENTRY                       mPartitionListHead;
+STATIC EFI_HANDLE                       mFlashHandle;
+STATIC EFI_BLOCK_IO_PROTOCOL           *mFlashBlockIo;
+STATIC EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *mTextOut;
+
+/*
+  Helper to free the partition list
+*/
+STATIC
+VOID
+FreePartitionList (
+  VOID
+  )
+{
+  FASTBOOT_PARTITION_LIST *Entry;
+  FASTBOOT_PARTITION_LIST *NextEntry;
+
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead);
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    NextEntry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &Entry->Link);
+
+    RemoveEntryList (&Entry->Link);
+    FreePool (Entry);
+
+    Entry = NextEntry;
+  }
+}
+
+/*
+  Read the PartitionName fields from the GPT partition entries, putting them
+  into an allocated array that should later be freed.
+*/
+STATIC
+EFI_STATUS
+ReadPartitionEntries (
+  IN  EFI_BLOCK_IO_PROTOCOL *BlockIo,
+  OUT EFI_PARTITION_ENTRY  **PartitionEntries,
+  OUT UINTN                 *PartitionNumbers
+  )
+{
+  EFI_STATUS                  Status;
+  UINT32                      MediaId;
+  UINTN                       BlockSize;
+  UINTN                       PageCount;
+  UINTN                       Count, EndLBA;
+  EFI_PARTITION_TABLE_HEADER *GptHeader;
+  EFI_PARTITION_ENTRY        *Entry;
+  VOID                       *Buffer;
+
+  if ((PartitionEntries == NULL) || (PartitionNumbers == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  MediaId = BlockIo->Media->MediaId;
+  BlockSize = BlockIo->Media->BlockSize;
+
+  //
+  // Read size of Partition entry and number of entries from GPT header
+  //
+
+  PageCount = EFI_SIZE_TO_PAGES (34 * BlockSize);
+  Buffer = AllocatePages (PageCount);
+  if (Buffer == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Status = BlockIo->ReadBlocks (BlockIo, MediaId, 0, PageCount * EFI_PAGE_SIZE, Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  GptHeader = (EFI_PARTITION_TABLE_HEADER *)(Buffer + BlockSize);
+
+  // Check there is a GPT on the media
+  if (GptHeader->Header.Signature != EFI_PTAB_HEADER_ID ||
+      GptHeader->MyLBA != 1) {
+    DEBUG ((EFI_D_ERROR,
+      "Fastboot platform: No GPT on flash. "
+      "Fastboot on Versatile Express does not support MBR.\n"
+      ));
+    return EFI_DEVICE_ERROR;
+  }
+
+  Entry = (EFI_PARTITION_ENTRY *)(Buffer + (2 * BlockSize));
+  EndLBA = GptHeader->FirstUsableLBA - 1;
+  Count = 0;
+  while (1) {
+    if ((Entry->StartingLBA > EndLBA) && (Entry->EndingLBA <= GptHeader->LastUsableLBA)) {
+      Count++;
+      EndLBA = Entry->EndingLBA;
+      Entry++;
+    } else {
+      break;
+    }
+  }
+  if (Count == 0) {
+    return EFI_INVALID_PARAMETER;
+  }
+  if (Count > GptHeader->NumberOfPartitionEntries) {
+    Count = GptHeader->NumberOfPartitionEntries;
+  }
+
+  *PartitionEntries = (EFI_PARTITION_ENTRY *)((UINTN)Buffer + (2 * BlockSize));
+  *PartitionNumbers = Count;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+LoadPtable (
+  VOID
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePathDup;
+  UINTN                               PartitionNumbers = 0;
+  UINTN                               LoopIndex;
+  EFI_PARTITION_ENTRY                *PartitionEntries = NULL;
+  FASTBOOT_PARTITION_LIST            *Entry;
+
+  InitializeListHead (&mPartitionListHead);
+
+  Status = gBS->LocateProtocol (&gEfiSimpleTextOutProtocolGuid, NULL, (VOID **) &mTextOut);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "Fastboot platform: Couldn't open Text Output Protocol: %r\n", Status
+      ));
+    return Status;
+  }
+
+  //
+  // Get EFI_HANDLES for all the partitions on the block devices pointed to by
+  // PcdFastbootFlashDevicePath, also saving their GPT partition labels.
+  // There's no way to find all of a device's children, so we get every handle
+  // in the system supporting EFI_BLOCK_IO_PROTOCOL and then filter out ones
+  // that don't represent partitions on the flash device.
+  //
+  FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
+
+  // Create another device path pointer because LocateDevicePath will modify it.
+  FlashDevicePathDup = FlashDevicePath;
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePathDup, &mFlashHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
+
+
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &mFlashBlockIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Fastboot platform: Couldn't open Android NVM device (status: %r)\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  // Read the GPT partition entry array into memory so we can get the partition names
+  Status = ReadPartitionEntries (mFlashBlockIo, &PartitionEntries, &PartitionNumbers);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Warning: Failed to read partitions from Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
+  for (LoopIndex = 0; LoopIndex < PartitionNumbers; LoopIndex++) {
+    // Create entry
+    Entry = AllocatePool (sizeof (FASTBOOT_PARTITION_LIST));
+    if (Entry == NULL) {
+      Status = EFI_BUFFER_TOO_SMALL;
+      FreePartitionList ();
+      goto Exit;
+    }
+    StrnCpy (
+      Entry->PartitionName,
+      PartitionEntries[LoopIndex].PartitionName,
+      PARTITION_NAME_MAX_LENGTH
+      );
+    Entry->StartingLBA = PartitionEntries[LoopIndex].StartingLBA;
+    Entry->EndingLBA = PartitionEntries[LoopIndex].EndingLBA;
+    InsertTailList (&mPartitionListHead, &Entry->Link);
+  }
+Exit:
+  FreePages (
+    (VOID *)((UINTN)PartitionEntries - (2 * mFlashBlockIo->Media->BlockSize)),
+    EFI_SIZE_TO_PAGES (34 * mFlashBlockIo->Media->BlockSize)
+    );
+  return Status;
+}
+
+/*
+  Initialise: Open the Android NVM device and find the partitions on it. Save them in
+  a list along with the "PartitionName" fields for their GPT entries.
+  We will use these partition names as the key in
+  HiKeyFastbootPlatformFlashPartition.
+*/
+EFI_STATUS
+HiKeyFastbootPlatformInit (
+  VOID
+  )
+{
+  return LoadPtable ();
+}
+
+VOID
+HiKeyFastbootPlatformUnInit (
+  VOID
+  )
+{
+  FreePartitionList ();
+}
+
+EFI_STATUS
+HiKeyFlashPtable (
+  IN UINTN   Size,
+  IN VOID   *Image
+  )
+{
+  EFI_STATUS               Status;
+  EFI_DISK_IO_PROTOCOL    *DiskIo;
+  UINT32                   MediaId;
+
+  MediaId = mFlashBlockIo->Media->MediaId;
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiDiskIoProtocolGuid,
+                  (VOID **) &DiskIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = DiskIo->WriteDisk (DiskIo, MediaId, 0, Size, Image);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  FreePartitionList ();
+  Status = LoadPtable ();
+  return Status;
+}
+
+EFI_STATUS
+HiKeyFastbootPlatformFlashPartition (
+  IN CHAR8  *PartitionName,
+  IN UINTN   Size,
+  IN VOID   *Image
+  )
+{
+  EFI_STATUS               Status;
+  UINTN                    PartitionSize;
+  FASTBOOT_PARTITION_LIST *Entry;
+  CHAR16                   PartitionNameUnicode[60];
+  BOOLEAN                  PartitionFound;
+  EFI_DISK_IO_PROTOCOL    *DiskIo;
+  UINTN                    BlockSize;
+
+  // Support the pseudo partition name, such as "ptable".
+  if (AsciiStrCmp (PartitionName, "ptable") == 0) {
+    return HiKeyFlashPtable (Size, Image);
+  }
+
+  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
+  PartitionFound = FALSE;
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    // Search the partition list for the partition named by PartitionName
+    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+      PartitionFound = TRUE;
+      break;
+    }
+
+   Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
+  }
+  if (!PartitionFound) {
+    return EFI_NOT_FOUND;
+  }
+
+  // Check image will fit on device
+  BlockSize = mFlashBlockIo->Media->BlockSize;
+  PartitionSize = (Entry->EndingLBA - Entry->StartingLBA + 1) * BlockSize;
+  if (PartitionSize < Size) {
+    DEBUG ((DEBUG_ERROR, "Partition not big enough.\n"));
+    DEBUG ((DEBUG_ERROR, "Partition Size:\t%ld\nImage Size:\t%ld\n", PartitionSize, Size));
+
+    return EFI_VOLUME_FULL;
+  }
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiDiskIoProtocolGuid,
+                  (VOID **) &DiskIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  Status = DiskIo->WriteDisk (
+                     DiskIo,
+                     mFlashBlockIo->Media->MediaId,
+                     Entry->StartingLBA * BlockSize,
+                     Size,
+                     Image
+                     );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to write %d bytes into 0x%x, Status:%r\n", Size, Entry->StartingLBA * BlockSize, Status));
+    return Status;
+  }
+
+  mFlashBlockIo->FlushBlocks(mFlashBlockIo);
+  MicroSecondDelay (50000);
+
+  return Status;
+}
+
+EFI_STATUS
+HiKeyErasePtable (
+  VOID
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_ERASE_BLOCK_PROTOCOL   *EraseBlockProtocol;
+
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiEraseBlockProtocolGuid,
+                  (VOID **) &EraseBlockProtocol,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Fastboot platform: could not open Erase Block IO: %r\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+  Status = EraseBlockProtocol->EraseBlocks (
+                                 EraseBlockProtocol,
+                                 mFlashBlockIo->Media->MediaId,
+                                 0,
+                                 NULL,
+                                 34 * mFlashBlockIo->Media->BlockSize
+                                 );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  FreePartitionList ();
+  return Status;
+}
+
+EFI_STATUS
+HiKeyFastbootPlatformErasePartition (
+  IN CHAR8 *PartitionName
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_ERASE_BLOCK_PROTOCOL   *EraseBlockProtocol;
+  UINTN                       Size;
+  BOOLEAN                     PartitionFound;
+  CHAR16                      PartitionNameUnicode[60];
+  FASTBOOT_PARTITION_LIST    *Entry;
+
+  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
+
+  // Support the pseudo partition name, such as "ptable".
+  if (AsciiStrCmp (PartitionName, "ptable") == 0) {
+    return HiKeyErasePtable ();
+  }
+
+  PartitionFound = FALSE;
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead);
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    // Search the partition list for the partition named by PartitionName
+    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+      PartitionFound = TRUE;
+      break;
+    }
+    Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &Entry->Link);
+  }
+  if (!PartitionFound) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiEraseBlockProtocolGuid,
+                  (VOID **) &EraseBlockProtocol,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Size = (Entry->EndingLBA - Entry->StartingLBA + 1) * mFlashBlockIo->Media->BlockSize;
+  Status = EraseBlockProtocol->EraseBlocks (
+                                 EraseBlockProtocol,
+                                 mFlashBlockIo->Media->MediaId,
+                                 Entry->StartingLBA,
+                                 NULL,
+                                 Size
+                                 );
+  return Status;
+}
+
+EFI_STATUS
+HiKeyFastbootPlatformGetVar (
+  IN  CHAR8   *Name,
+  OUT CHAR8   *Value
+  )
+{
+  EFI_STATUS               Status;
+  UINT64                   PartitionSize;
+  FASTBOOT_PARTITION_LIST *Entry;
+  CHAR16                   PartitionNameUnicode[60];
+  BOOLEAN                  PartitionFound;
+  CHAR16                   UnicodeSN[SERIAL_NUMBER_SIZE];
+
+  if (!AsciiStrCmp (Name, "max-download-size")) {
+    AsciiStrCpy (Value, FixedPcdGetPtr (PcdArmFastbootFlashLimit));
+  } else if (!AsciiStrCmp (Name, "product")) {
+    AsciiStrCpy (Value, FixedPcdGetPtr (PcdFirmwareVendor));
+  } else if (!AsciiStrCmp (Name, "serialno")) {
+    Status = LoadSNFromBlock (mFlashHandle, SERIAL_NUMBER_LBA, UnicodeSN);
+    if (EFI_ERROR (Status)) {
+      *Value = '\0';
+      return Status;
+    }
+    UnicodeStrToAsciiStr (UnicodeSN, Value);
+  } else if ( !AsciiStrnCmp (Name, "partition-size", 14)) {
+    AsciiStrToUnicodeStr ((Name + 15), PartitionNameUnicode);
+    PartitionFound = FALSE;
+    Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
+    while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+      // Search the partition list for the partition named by PartitionName
+      if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+        PartitionFound = TRUE;
+        break;
+      }
+
+     Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
+    }
+    if (!PartitionFound) {
+      *Value = '\0';
+      return EFI_NOT_FOUND;
+    }
+
+    PartitionSize = (Entry->EndingLBA - Entry->StartingLBA + 1) * mFlashBlockIo->Media->BlockSize;
+    DEBUG ((DEBUG_ERROR, "Fastboot platform: check for partition-size:%a 0X%llx\n", Name, PartitionSize));
+    AsciiSPrint (Value, 12, "0x%llx", PartitionSize);
+  } else if ( !AsciiStrnCmp (Name, "partition-type", 14)) {
+      DEBUG ((DEBUG_ERROR, "Fastboot platform: check for partition-type:%a\n", (Name + 15)));
+    if ( !AsciiStrnCmp  ( (Name + 15) , "system", 6) || !AsciiStrnCmp  ( (Name + 15) , "userdata", 8)
+            || !AsciiStrnCmp  ( (Name + 15) , "cache", 5)) {
+      AsciiStrCpy (Value, "ext4");
+    } else {
+      AsciiStrCpy (Value, "raw");
+    }
+  } else if ( !AsciiStrCmp (Name, "erase-block-size")) {
+    AsciiSPrint (Value, 12, "0x%llx", HIKEY_ERASE_SIZE);
+  } else if ( !AsciiStrCmp (Name, "logical-block-size")) {
+    AsciiSPrint (Value, 12, "0x%llx", HIKEY_ERASE_SIZE);
+  } else {
+    *Value = '\0';
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+HiKeyFastbootPlatformOemCommand (
+  IN  CHAR8   *Command
+  )
+{
+  EFI_STATUS   Status;
+  CHAR16       UnicodeSN[SERIAL_NUMBER_SIZE];
+
+  if (AsciiStrCmp (Command, "Demonstrate") == 0) {
+    DEBUG ((DEBUG_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.\n"));
+    return EFI_SUCCESS;
+  } else if (AsciiStrCmp (Command, "serialno") == 0) {
+    Status = GenerateUsbSN (UnicodeSN);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Failed to generate USB Serial Number.\n"));
+      return Status;
+    }
+    Status = StoreSNToBlock (mFlashHandle, SERIAL_NUMBER_LBA, UnicodeSN);
+    return Status;
+  } else if (AsciiStrCmp (Command, "reboot-bootloader") == 0) {
+    MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_BOOTLOADER);
+    WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4);
+    return EFI_SUCCESS;
+  } else {
+    DEBUG ((DEBUG_ERROR,
+      "HiKey: Unrecognised Fastboot OEM command: %s\n",
+      Command
+      ));
+    return EFI_NOT_FOUND;
+  }
+}
+
+EFI_STATUS
+HiKeyFastbootPlatformFlashPartitionEx (
+  IN CHAR8  *PartitionName,
+  IN UINTN   Offset,
+  IN UINTN   Size,
+  IN VOID   *Image
+  )
+{
+  EFI_STATUS               Status;
+  UINTN                    PartitionSize;
+  FASTBOOT_PARTITION_LIST *Entry;
+  CHAR16                   PartitionNameUnicode[60];
+  BOOLEAN                  PartitionFound;
+  UINTN                    BlockSize;
+  EFI_DISK_IO_PROTOCOL    *DiskIo;
+
+  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
+  PartitionFound = FALSE;
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    // Search the partition list for the partition named by PartitionName
+    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+      PartitionFound = TRUE;
+      break;
+    }
+
+   Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
+  }
+  if (!PartitionFound) {
+    return EFI_NOT_FOUND;
+  }
+
+  // Check image will fit on device
+  PartitionSize = (Entry->EndingLBA - Entry->StartingLBA + 1) * mFlashBlockIo->Media->BlockSize;
+  if (PartitionSize < Size) {
+    DEBUG ((DEBUG_ERROR, "Partition not big enough.\n"));
+    DEBUG ((DEBUG_ERROR, "Partition Size:\t%ld\nImage Size:\t%ld\n", PartitionSize, Size));
+
+    return EFI_VOLUME_FULL;
+  }
+
+  BlockSize = mFlashBlockIo->Media->BlockSize;
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiDiskIoProtocolGuid,
+                  (VOID **) &DiskIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = DiskIo->WriteDisk (
+                     DiskIo,
+                     mFlashBlockIo->Media->MediaId,
+                     Entry->StartingLBA * BlockSize + Offset,
+                     Size,
+                     Image
+                     );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to write %d bytes into 0x%x, Status:%r\n", Size, Entry->StartingLBA * BlockSize + Offset, Status));
+    return Status;
+  }
+  return Status;
+}
+
+FASTBOOT_PLATFORM_PROTOCOL mPlatformProtocol = {
+  HiKeyFastbootPlatformInit,
+  HiKeyFastbootPlatformUnInit,
+  HiKeyFastbootPlatformFlashPartition,
+  HiKeyFastbootPlatformErasePartition,
+  HiKeyFastbootPlatformGetVar,
+  HiKeyFastbootPlatformOemCommand,
+  HiKeyFastbootPlatformFlashPartitionEx
+};
+
+EFI_STATUS
+EFIAPI
+HiKeyFastbootPlatformEntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  return gBS->InstallProtocolInterface (
+                &ImageHandle,
+                &gAndroidFastbootPlatformProtocolGuid,
+                EFI_NATIVE_INTERFACE,
+                &mPlatformProtocol
+                );
+}
diff --git a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.inf b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.inf
index 25c09d2..ee9f52e 100644
--- a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.inf
+++ b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.inf
@@ -1,8 +1,7 @@
 #/** @file
 #
 #  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
-#  Copyright (c) 2015-2016, Linaro Ltd. All rights reserved.
-#  Copyright (c) 2015-2016, Hisilicon Ltd. All rights reserved.
+#  Copyright (c) 2015-2017, Linaro. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -15,7 +14,7 @@
 #**/
 
 [Defines]
-  INF_VERSION                    = 0x00010005
+  INF_VERSION                    = 0x00010019
   BASE_NAME                      = HiKeyFastbootDxe
   FILE_GUID                      = 8e335c38-c4e1-494e-8011-37a858d9763d
   MODULE_TYPE                    = UEFI_DRIVER
@@ -23,39 +22,38 @@
   ENTRY_POINT                    = HiKeyFastbootPlatformEntryPoint
 
 [Sources.common]
-  HiKeyFastboot.c
+  HiKeyFastbootDxe.c
 
 [LibraryClasses]
   BaseLib
   BaseMemoryLib
+  CacheMaintenanceLib
   DebugLib
   DevicePathLib
+  IoLib
   MemoryAllocationLib
   PcdLib
   UefiBootServicesTableLib
   UefiRuntimeServicesTableLib
   UefiDriverEntryPoint
+  UsbSerialNumberLib
   TimerLib
 
 [Protocols]
   gAndroidFastbootPlatformProtocolGuid
   gEfiBlockIoProtocolGuid
   gEfiDiskIoProtocolGuid
-  gEfiSimpleTextOutProtocolGuid
   gEfiEraseBlockProtocolGuid
+  gEfiSimpleTextOutProtocolGuid
 
 [Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
-  ArmPlatformPkg/ArmPlatformPkg.dec
-  ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
-  ArmPkg/ArmPkg.dec
   OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec
 
-[Guids]
-  gHiKeyVariableGuid
-
 [Pcd]
   gArmPlatformTokenSpaceGuid.PcdFirmwareVendor
   gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath
diff --git a/Platforms/Hisilicon/HiKey/HiKeyGpio/HiKeyGpio.c b/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c
index fd2c956..9e7a895 100644
--- a/Platforms/Hisilicon/HiKey/HiKeyGpio/HiKeyGpio.c
+++ b/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c
@@ -1,69 +1,68 @@
-/** @file
-*
-*  Copyright (c) 2015, Linaro Ltd. All rights reserved.
-*  Copyright (c) 2015, Hisilicon Ltd. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Protocol/EmbeddedGpio.h>
-
-GPIO_CONTROLLER gGpioDevice[]= {
-  { 0xf8011000, 0, 8 },    // GPIO0
-  { 0xf8012000, 8, 8 },    // GPIO1
-  { 0xf8013000, 16, 8 },   // GPIO2
-  { 0xf8014000, 24, 8 },   // GPIO3
-  { 0xf7020000, 32, 8 },   // GPIO4
-  { 0xf7021000, 40, 8 },   // GPIO5
-  { 0xf7022000, 48, 8 },   // GPIO6
-  { 0xf7023000, 56, 8 },   // GPIO7
-  { 0xf7024000, 64, 8 },   // GPIO8
-  { 0xf7025000, 72, 8 },   // GPIO9
-  { 0xf7026000, 80, 8 },   // GPIO10
-  { 0xf7027000, 88, 8 },   // GPIO11
-  { 0xf7028000, 96, 8 },   // GPIO12
-  { 0xf7029000, 104, 8 },  // GPIO13
-  { 0xf702a000, 112, 8 },  // GPIO14
-  { 0xf702b000, 120, 8 },  // GPIO15
-  { 0xf702c000, 128, 8 },  // GPIO16
-  { 0xf702d000, 136, 8 },  // GPIO17
-  { 0xf702e000, 144, 8 },  // GPIO18
-  { 0xf702f000, 152, 8 }   // GPIO19
-};
-
-PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = {
-  160, 20, gGpioDevice
-};
-
-EFI_STATUS
-EFIAPI
-HiKeyGpioEntryPoint (
-  IN EFI_HANDLE         ImageHandle,
-  IN EFI_SYSTEM_TABLE   *SystemTable
-  )
-{
-  EFI_STATUS  Status;
-  EFI_HANDLE  Handle;
-
-  // Install the Embedded Platform GPIO Protocol onto a new handle
-  Handle = NULL;
-  Status = gBS->InstallMultipleProtocolInterfaces(
-                  &Handle,
-                  &gPlatformGpioProtocolGuid, &gPlatformGpioDevice,
-                  NULL
-                 );
-  if (EFI_ERROR(Status)) {
-    Status = EFI_OUT_OF_RESOURCES;
-  }
-
-  return Status;
-}
+/** @file
+*
+*  Copyright (c) 2015-2017, Linaro. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/EmbeddedGpio.h>
+
+GPIO_CONTROLLER gGpioDevice[]= {
+  { 0xf8011000, 0, 8 },    // GPIO0
+  { 0xf8012000, 8, 8 },    // GPIO1
+  { 0xf8013000, 16, 8 },   // GPIO2
+  { 0xf8014000, 24, 8 },   // GPIO3
+  { 0xf7020000, 32, 8 },   // GPIO4
+  { 0xf7021000, 40, 8 },   // GPIO5
+  { 0xf7022000, 48, 8 },   // GPIO6
+  { 0xf7023000, 56, 8 },   // GPIO7
+  { 0xf7024000, 64, 8 },   // GPIO8
+  { 0xf7025000, 72, 8 },   // GPIO9
+  { 0xf7026000, 80, 8 },   // GPIO10
+  { 0xf7027000, 88, 8 },   // GPIO11
+  { 0xf7028000, 96, 8 },   // GPIO12
+  { 0xf7029000, 104, 8 },  // GPIO13
+  { 0xf702a000, 112, 8 },  // GPIO14
+  { 0xf702b000, 120, 8 },  // GPIO15
+  { 0xf702c000, 128, 8 },  // GPIO16
+  { 0xf702d000, 136, 8 },  // GPIO17
+  { 0xf702e000, 144, 8 },  // GPIO18
+  { 0xf702f000, 152, 8 }   // GPIO19
+};
+
+PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = {
+  160, 20, gGpioDevice
+};
+
+EFI_STATUS
+EFIAPI
+HiKeyGpioEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
+
+  // Install the Embedded Platform GPIO Protocol onto a new handle
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces(
+                  &Handle,
+                  &gPlatformGpioProtocolGuid, &gPlatformGpioDevice,
+                  NULL
+                 );
+  if (EFI_ERROR(Status)) {
+    Status = EFI_OUT_OF_RESOURCES;
+  }
+
+  return Status;
+}
diff --git a/Platforms/Hisilicon/HiKey/HiKeyGpio/HiKeyGpio.inf b/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf
index a619231..4d43a92 100644
--- a/Platforms/Hisilicon/HiKey/HiKeyGpio/HiKeyGpio.inf
+++ b/Platforms/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf
@@ -1,38 +1,37 @@
-#
-#  Copyright (c) 2015-2016, Linaro Ltd. All rights reserved.
-#  Copyright (c) 2015-2016, Hisilicon Ltd. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = HiKeyGpio
-  FILE_GUID                      = b51a851c-7bf7-463f-b261-cfb158b7f699
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = HiKeyGpioEntryPoint
-
-[Sources.common]
-  HiKeyGpio.c
-
-[Packages]
-  EmbeddedPkg/EmbeddedPkg.dec
-  MdePkg/MdePkg.dec
-  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec
-
-[LibraryClasses]
-  DebugLib
-  UefiDriverEntryPoint
-
-[Protocols]
-  gPlatformGpioProtocolGuid
-
-[Depex]
-  BEFORE gArmPL061GpioGuid
+#
+#  Copyright (c) 2015-2017, Linaro. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKeyGpio
+  FILE_GUID                      = b51a851c-7bf7-463f-b261-cfb158b7f699
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = HiKeyGpioEntryPoint
+
+[Sources.common]
+  HiKeyGpioDxe.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec
+
+[LibraryClasses]
+  DebugLib
+  UefiDriverEntryPoint
+
+[Protocols]
+  gPlatformGpioProtocolGuid
+
+[Depex]
+  BEFORE gArmPL061GpioGuid
diff --git a/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.c b/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.c
new file mode 100644
index 0000000..0f58697
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.c
@@ -0,0 +1,140 @@
+/** @file
+*
+*  Copyright (c) 2017, Linaro. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UsbSerialNumberLib.h>
+
+#include <Protocol/EmbeddedGpio.h>
+#include <Protocol/PlatformDwMmc.h>
+
+#include <Hi6220.h>
+
+#define DETECT_SD_CARD           8     // GPIO 1_0
+
+DW_MMC_HC_SLOT_CAP
+DwMmcCapability[2] = {
+  {
+    .Ddr50       = 1,
+    .HighSpeed   = 1,
+    .BusWidth    = 8,
+    .SlotType    = EmbeddedSlot,
+    .CardType    = EmmcCardType,
+    .BaseClkFreq = 100000
+  }, {
+    .HighSpeed   = 1,
+    .BusWidth    = 4,
+    .SlotType    = RemovableSlot,
+    .CardType    = SdCardType,
+    .Voltage30   = 1,
+    .BaseClkFreq = 100000
+  }
+};
+
+EFI_STATUS
+EFIAPI
+HiKeyGetCapability (
+  IN     EFI_HANDLE           Controller,
+  IN     UINT8                Slot,
+     OUT DW_MMC_HC_SLOT_CAP   *Capability
+  )
+{
+  if (Capability == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  if (DwMmcCapability[0].Controller == 0) {
+    DwMmcCapability[0].Controller = Controller;
+    CopyMem (Capability, &DwMmcCapability[0], sizeof (DW_MMC_HC_SLOT_CAP));
+  } else if (DwMmcCapability[0].Controller == Controller) {
+    CopyMem (Capability, &DwMmcCapability[0], sizeof (DW_MMC_HC_SLOT_CAP));
+  } else if (DwMmcCapability[1].Controller == 0) {
+    DwMmcCapability[1].Controller = Controller;
+    CopyMem (Capability, &DwMmcCapability[1], sizeof (DW_MMC_HC_SLOT_CAP));
+  } else if (DwMmcCapability[1].Controller == Controller) {
+    CopyMem (Capability, &DwMmcCapability[1], sizeof (DW_MMC_HC_SLOT_CAP));
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+  return EFI_SUCCESS;
+}
+
+BOOLEAN
+EFIAPI
+HiKeyCardDetect (
+  IN UINT8                    Slot
+  )
+{
+  EFI_STATUS            Status;
+  EMBEDDED_GPIO         *Gpio;
+  UINTN                 Value;
+
+  if (Slot == 0) {
+    return TRUE;
+  } else if (Slot == 1) {
+    Status = gBS->LocateProtocol (&gEmbeddedGpioProtocolGuid, NULL, (VOID **)&Gpio);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Failed to get GPIO protocol: %r\n", Status));
+      return FALSE;
+    }
+    Status = Gpio->Set (Gpio, DETECT_SD_CARD, GPIO_MODE_INPUT);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Failed to sed GPIO as input mode: %r\n", Status));
+      return FALSE;
+    }
+    Status = Gpio->Get (Gpio, DETECT_SD_CARD, &Value);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Failed to get GPIO value: %r\n", Status));
+      return FALSE;
+    }
+    if (Value == 0) {
+      return TRUE;
+    }
+    return FALSE;
+  } else {
+    return FALSE;
+  }
+}
+
+PLATFORM_DW_MMC_PROTOCOL mDwMmcDevice = {
+  HiKeyGetCapability,
+  HiKeyCardDetect
+};
+
+EFI_STATUS
+EFIAPI
+HiKeyMmcEntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS        Status;
+
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gPlatformDwMmcProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  &mDwMmcDevice
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return Status;
+}
diff --git a/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.inf b/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.inf
new file mode 100644
index 0000000..1b78d32
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.inf
@@ -0,0 +1,45 @@
+#/** @file
+#
+#  Copyright (c) 2017, Linaro. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKeyMmcDxe
+  FILE_GUID                      = a4f9bfb1-b3f8-4d4d-8c04-9539173fc1f2
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = HiKeyMmcEntryPoint
+
+[Sources.common]
+  HiKeyMmcDxe.c
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[Protocols]
+  gEfiDriverBindingProtocolGuid
+  gEmbeddedGpioProtocolGuid
+  gPlatformDwMmcProtocolGuid
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.dec
+
+[Depex]
+  TRUE
diff --git a/Platforms/Hisilicon/HiKey/HiKeyDxe/InitPeripherals.c b/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/HiKeyUsbDxe.c
index 9c74d02..d7baddb 100644
--- a/Platforms/Hisilicon/HiKey/HiKeyDxe/InitPeripherals.c
+++ b/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/HiKeyUsbDxe.c
@@ -1,223 +1,276 @@
-/** @file
-*
-*  Copyright (c) 2015, Linaro Ltd. All rights reserved.
-*  Copyright (c) 2015, Hisilicon Ltd. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/IoLib.h>
-#include <Library/TimerLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-
-#include <Protocol/EmbeddedGpio.h>
-#include <Protocol/DwUsb.h>
-
-#include <Hi6220.h>
-
-#include "Hi6220RegsPeri.h"
-#include "HiKeyDxeInternal.h"
-
-#define USB_SEL_GPIO0_3          3     // GPIO 0_3
-#define USB_5V_HUB_EN            7     // GPIO 0_7
-#define USB_ID_DET_GPIO2_5       21    // GPIO 2_5
-#define USB_VBUS_DET_GPIO2_6     22    // GPIO 2_6
-
-// Jumper on pin5-6 of J15 determines whether boot to fastboot
-#define DETECT_J15_FASTBOOT      24    // GPIO 3_0
-
-STATIC EMBEDDED_GPIO *mGpio;
-
-STATIC
-VOID
-HiKeyDetectUsbModeInit (
-  IN VOID
-  )
-{
-  EFI_STATUS     Status;
-
-  /* set pullup on both GPIO2_5 & GPIO2_6. It's required for inupt. */
-  MmioWrite32 (0xf8001864, 1);
-  MmioWrite32 (0xf8001868, 1);
-
-  Status = gBS->LocateProtocol (&gEmbeddedGpioProtocolGuid, NULL, (VOID **)&mGpio);
-  ASSERT_EFI_ERROR (Status);
-  Status = mGpio->Set (mGpio, USB_SEL_GPIO0_3, GPIO_MODE_OUTPUT_0);
-  ASSERT_EFI_ERROR (Status);
-  Status = mGpio->Set (mGpio, USB_5V_HUB_EN, GPIO_MODE_OUTPUT_0);
-  ASSERT_EFI_ERROR (Status);
-  MicroSecondDelay (1000);
-
-  Status = mGpio->Set (mGpio, USB_ID_DET_GPIO2_5, GPIO_MODE_INPUT);
-  ASSERT_EFI_ERROR (Status);
-  Status = mGpio->Set (mGpio, USB_VBUS_DET_GPIO2_6, GPIO_MODE_INPUT);
-  ASSERT_EFI_ERROR (Status);
-}
-
-UINTN
-HiKeyGetUsbMode (
-  IN VOID
-  )
-{
-  EFI_STATUS     Status;
-  UINTN          GpioId, GpioVbus;
-  UINTN          Value;
-
-  Status = mGpio->Get (mGpio, USB_ID_DET_GPIO2_5, &Value);
-  ASSERT_EFI_ERROR (Status);
-  GpioId = Value;
-  Status = mGpio->Get (mGpio, USB_VBUS_DET_GPIO2_6, &Value);
-  ASSERT_EFI_ERROR (Status);
-  GpioVbus = Value;
-
-  if ((GpioId == 1) && (GpioVbus == 0))
-    return USB_DEVICE_MODE;
-  else if ((GpioId == 0) && (GpioVbus == 1))
-    return USB_CABLE_NOT_ATTACHED;
-  return USB_HOST_MODE;
-}
-
-EFI_STATUS
-HiKeyUsbPhyInit (
-  IN UINT8        Mode
-  )
-{
-  UINTN         Value;
-  UINT32        Data;
-
-  HiKeyDetectUsbModeInit ();
-
-  //setup clock
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN0, BIT4);
-  do {
-       Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CLKSTAT0);
-  } while ((Value & BIT4) == 0);
-
-  //setup phy
-  Data = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
-           RST0_USBOTG | RST0_USBOTG_32K;
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, Data);
-  do {
-    Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT0);
-    Value &= Data;
-  } while (Value);
-
-  Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4);
-  Value &= ~(CTRL4_PICO_SIDDQ | CTRL4_FPGA_EXT_PHY_SEL |
-             CTRL4_OTG_PHY_SEL);
-  Value |=  CTRL4_PICO_VBUSVLDEXT | CTRL4_PICO_VBUSVLDEXTSEL;
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4, Value);
-  MicroSecondDelay (1000);
-
-  //If Mode = 1, USB in Device Mode
-  //If Mode = 0, USB in Host Mode
-  if (Mode == USB_DEVICE_MODE) {
-    DEBUG ((EFI_D_ERROR, "Set USB PHY in device mode.\n"));
-    if (HiKeyGetUsbMode () == USB_DEVICE_MODE) {
-      DEBUG ((EFI_D_ERROR, "USB PHY works in device mode.\n"));
-    } else {
-      DEBUG ((EFI_D_ERROR, "Fail to set USB PHY in device mode.\n"));
-      return EFI_INVALID_PARAMETER;
-    }
-
-     Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5);
-     Value &= ~CTRL5_PICOPHY_BC_MODE;
-     MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Value);
-     MicroSecondDelay (20000);
-  } else {
-    DEBUG ((EFI_D_ERROR, "Set USB PHY in host mode.\n"));
-    if (HiKeyGetUsbMode () == USB_HOST_MODE) {
-      DEBUG ((EFI_D_ERROR, "USB PHY works in host mode.\n"));
-    } else {
-      DEBUG ((EFI_D_ERROR, "Fail to set USB PHY in host mode.\n"));
-      return EFI_INVALID_PARAMETER;
-    }
-
-    /*CTRL5*/
-    Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5);
-    Data &= ~CTRL5_PICOPHY_BC_MODE;
-    Data |= CTRL5_USBOTG_RES_SEL | CTRL5_PICOPHY_ACAENB |
-            CTRL5_PICOPHY_VDATDETENB | CTRL5_PICOPHY_DCDENB;
-    MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Data);
-    MicroSecondDelay (20000);
-    MmioWrite32 (PERI_CTRL_BASE + 0x018, 0x70533483); //EYE_PATTERN
-
-    MicroSecondDelay (5000);
-  }
-
-  return EFI_SUCCESS;
-}
-
-STATIC
-VOID
-UartInit (
-  IN VOID
-  )
-{
-  UINT32     Val;
-
-  /* make UART1 out of reset */
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1);
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1);
-  /* make UART2 out of reset */
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2);
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2);
-  /* make UART3 out of reset */
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3);
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3);
-  /* make UART4 out of reset */
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4);
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4);
-
-  /* make DW_MMC2 out of reset */
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2);
-
-  /* enable clock for BT/WIFI */
-  Val = MmioRead32 (PMUSSI_REG(0x1c)) | 0x40;
-  MmioWrite32 (PMUSSI_REG(0x1c), Val);
-}
-
-STATIC
-VOID
-MtcmosInit (
-  IN VOID
-  )
-{
-  UINT32     Data;
-
-  /* enable MTCMOS for GPU */
-  MmioWrite32 (AO_CTRL_BASE + SC_PW_MTCMOS_EN0, PW_EN0_G3D);
-  do {
-    Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0);
-  } while ((Data & PW_EN0_G3D) == 0);
-}
-
-EFI_STATUS
-HiKeyInitPeripherals (
-  IN VOID
-  )
-{
-  UINT32     Data, Bits;
-
-  /* make I2C0/I2C1/I2C2/SPI0 out of reset */
-  Bits = PERIPH_RST3_I2C0 | PERIPH_RST3_I2C1 | PERIPH_RST3_I2C2 | \
-	 PERIPH_RST3_SSP;
-  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, Bits);
-
-  do {
-    Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT3);
-  } while (Data & Bits);
-
-  UartInit ();
-  MtcmosInit ();
-
-  return EFI_SUCCESS;
-}
+/** @file
+*
+*  Copyright (c) 2015-2017, Linaro. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UsbSerialNumberLib.h>
+
+#include <Protocol/EmbeddedGpio.h>
+#include <Protocol/DwUsb.h>
+
+#include <Hi6220.h>
+
+
+#define USB_SEL_GPIO0_3          3     // GPIO 0_3
+#define USB_5V_HUB_EN            7     // GPIO 0_7
+#define USB_ID_DET_GPIO2_5       21    // GPIO 2_5
+#define USB_VBUS_DET_GPIO2_6     22    // GPIO 2_6
+
+// Jumper on pin5-6 of J15 determines whether boot to fastboot
+#define DETECT_J15_FASTBOOT      24    // GPIO 3_0
+
+#define SERIAL_NUMBER_LBA        1024
+
+STATIC EMBEDDED_GPIO *mGpio;
+
+STATIC
+VOID
+HiKeyDetectUsbModeInit (
+  IN VOID
+  )
+{
+  EFI_STATUS     Status;
+
+  /* set pullup on both GPIO2_5 & GPIO2_6. It's required for inupt. */
+  MmioWrite32 (0xf8001864, 1);
+  MmioWrite32 (0xf8001868, 1);
+
+  Status = gBS->LocateProtocol (&gEmbeddedGpioProtocolGuid, NULL, (VOID **)&mGpio);
+  ASSERT_EFI_ERROR (Status);
+  Status = mGpio->Set (mGpio, USB_SEL_GPIO0_3, GPIO_MODE_OUTPUT_0);
+  ASSERT_EFI_ERROR (Status);
+  Status = mGpio->Set (mGpio, USB_5V_HUB_EN, GPIO_MODE_OUTPUT_0);
+  ASSERT_EFI_ERROR (Status);
+  MicroSecondDelay (1000);
+
+  Status = mGpio->Set (mGpio, USB_ID_DET_GPIO2_5, GPIO_MODE_INPUT);
+  ASSERT_EFI_ERROR (Status);
+  Status = mGpio->Set (mGpio, USB_VBUS_DET_GPIO2_6, GPIO_MODE_INPUT);
+  ASSERT_EFI_ERROR (Status);
+}
+
+UINTN
+HiKeyGetUsbMode (
+  IN VOID
+  )
+{
+#if 0
+  EFI_STATUS     Status;
+  UINTN          GpioId, GpioVbus;
+  UINTN          Value;
+
+  Status = mGpio->Get (mGpio, USB_ID_DET_GPIO2_5, &Value);
+  ASSERT_EFI_ERROR (Status);
+  GpioId = Value;
+  Status = mGpio->Get (mGpio, USB_VBUS_DET_GPIO2_6, &Value);
+  ASSERT_EFI_ERROR (Status);
+  GpioVbus = Value;
+
+DEBUG ((DEBUG_ERROR, "#%a, %d, GpioId:%d, GpioVbus:%d\n", __func__, __LINE__, GpioId, GpioVbus));
+  if ((GpioId == 1) && (GpioVbus == 0)) {
+    return USB_DEVICE_MODE;
+  } else if ((GpioId == 0) && (GpioVbus == 1)) {
+    return USB_CABLE_NOT_ATTACHED;
+  }
+  return USB_HOST_MODE;
+#else
+  return USB_DEVICE_MODE;
+#endif
+}
+
+EFI_STATUS
+HiKeyUsbPhyInit (
+  IN UINT8        Mode
+  )
+{
+  UINTN         Value;
+  UINT32        Data;
+
+  HiKeyDetectUsbModeInit ();
+
+  //setup clock
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN0, BIT4);
+  do {
+       Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CLKSTAT0);
+  } while ((Value & BIT4) == 0);
+
+  //setup phy
+  Data = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
+           RST0_USBOTG | RST0_USBOTG_32K;
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, Data);
+  do {
+    Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT0);
+    Value &= Data;
+  } while (Value);
+
+  Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4);
+  Value &= ~(CTRL4_PICO_SIDDQ | CTRL4_FPGA_EXT_PHY_SEL |
+             CTRL4_OTG_PHY_SEL);
+  Value |=  CTRL4_PICO_VBUSVLDEXT | CTRL4_PICO_VBUSVLDEXTSEL;
+  MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4, Value);
+  MicroSecondDelay (1000);
+
+  //If Mode = 1, USB in Device Mode
+  //If Mode = 0, USB in Host Mode
+  if (Mode == USB_DEVICE_MODE) {
+    if (HiKeyGetUsbMode () == USB_DEVICE_MODE) {
+      DEBUG ((DEBUG_ERROR, "usb work as device mode.\n"));
+    } else {
+      return EFI_INVALID_PARAMETER;
+    }
+
+     Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5);
+     Value &= ~CTRL5_PICOPHY_BC_MODE;
+     MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Value);
+     MicroSecondDelay (20000);
+  } else {
+    if (HiKeyGetUsbMode () == USB_HOST_MODE) {
+      DEBUG ((DEBUG_ERROR, "usb work as host mode.\n"));
+    } else {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    /*CTRL5*/
+    Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5);
+    Data &= ~CTRL5_PICOPHY_BC_MODE;
+    Data |= CTRL5_USBOTG_RES_SEL | CTRL5_PICOPHY_ACAENB |
+            CTRL5_PICOPHY_VDATDETENB | CTRL5_PICOPHY_DCDENB;
+    MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Data);
+    MicroSecondDelay (20000);
+    MmioWrite32 (PERI_CTRL_BASE + 0x018, 0x70533483); //EYE_PATTERN
+
+    MicroSecondDelay (5000);
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+HiKeyUsbGetLang (
+  OUT CHAR16            *Lang,
+  OUT UINT8             *Length
+  )
+{
+  if ((Lang == NULL) || (Length == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Lang[0] = 0x409;
+  *Length = sizeof (CHAR16);
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+HiKeyUsbGetManuFacturer (
+  OUT CHAR16            *ManuFacturer,
+  OUT UINT8             *Length
+  )
+{
+  UINTN                  VariableSize;
+  CHAR16                 DataUnicode[MANU_FACTURER_STRING_LENGTH];
+
+  if ((ManuFacturer == NULL) || (Length == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  VariableSize = MANU_FACTURER_STRING_LENGTH * sizeof (CHAR16);
+  ZeroMem (DataUnicode, MANU_FACTURER_STRING_LENGTH * sizeof(CHAR16));
+  StrCpy (DataUnicode, L"96Boards");
+  CopyMem (ManuFacturer, DataUnicode, VariableSize);
+  *Length = VariableSize;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+HiKeyUsbGetProduct (
+  OUT CHAR16            *Product,
+  OUT UINT8             *Length
+  )
+{
+  UINTN                  VariableSize;
+  CHAR16                 DataUnicode[PRODUCT_STRING_LENGTH];
+
+  if ((Product == NULL) || (Length == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  VariableSize = PRODUCT_STRING_LENGTH * sizeof (CHAR16);
+  ZeroMem (DataUnicode, PRODUCT_STRING_LENGTH * sizeof(CHAR16));
+  StrCpy (DataUnicode, L"HiKey");
+  CopyMem (Product, DataUnicode, VariableSize);
+  *Length = VariableSize;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+HiKeyUsbGetSerialNo (
+  OUT CHAR16            *SerialNo,
+  OUT UINT8             *Length
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePath;
+  EFI_HANDLE                          FlashHandle;
+
+  FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePath, &FlashHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
+
+  if ((SerialNo == NULL) || (Length == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = LoadSNFromBlock (FlashHandle, SERIAL_NUMBER_LBA, SerialNo);
+  *Length = StrSize (SerialNo);
+  return Status;
+}
+
+DW_USB_PROTOCOL mDwUsbDevice = {
+  HiKeyUsbGetLang,
+  HiKeyUsbGetManuFacturer,
+  HiKeyUsbGetProduct,
+  HiKeyUsbGetSerialNo,
+  HiKeyUsbPhyInit
+};
+
+EFI_STATUS
+EFIAPI
+HiKeyUsbEntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS        Status;
+
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gDwUsbProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  &mDwUsbDevice
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return Status;
+}
diff --git a/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.inf b/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/HiKeyUsbDxe.inf
index a258e18..09e5f64 100644
--- a/Drivers/Usb/DwUsbHostDxe/DwUsbHostDxe.inf
+++ b/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/HiKeyUsbDxe.inf
@@ -1,56 +1,50 @@
-#/** @file
-#
-#  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = DwUsbHostDxe
-  FILE_GUID                      = 4bf1704c-03f4-46d5-bca6-82fa580badfd
-  MODULE_TYPE                    = UEFI_DRIVER
-  VERSION_STRING                 = 1.0
-  ENTRY_POINT                    = DwUsbHostEntryPoint
-  UNLOAD_IMAGE			 = DwUsbHostExitPoint
-
-[Sources.common]
-  DwUsbHostDxe.c
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec
-
-[LibraryClasses]
-  MemoryAllocationLib
-  UncachedMemoryAllocationLib
-  BaseLib
-  UefiLib
-  UefiBootServicesTableLib
-  UefiDriverEntryPoint
-  BaseMemoryLib
-  DebugLib
-  PcdLib
-  ReportStatusCodeLib
-  TimerLib
-  IoLib
-
-[Guids]
-  gEfiEventExitBootServicesGuid
-
-[Protocols]
-  gEfiDriverBindingProtocolGuid
-  gEfiUsb2HcProtocolGuid
-  gDwUsbProtocolGuid
-
-[Pcd]
-  gDwUsbDxeTokenSpaceGuid.PcdDwUsbDxeBaseAddress
+#/** @file
+#
+#  Copyright (c) 2015-2017, Linaro. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKeyUsbDxe
+  FILE_GUID                      = c5c7089e-9b00-448c-8b23-a552688e2833
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = HiKeyUsbEntryPoint
+
+[Sources.common]
+  HiKeyUsbDxe.c
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UsbSerialNumberLib
+
+[Protocols]
+  gDwUsbProtocolGuid
+  gEfiDriverBindingProtocolGuid
+  gEmbeddedGpioProtocolGuid
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Drivers/Usb/DwUsbDxe/DwUsbDxe.dec
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec
+
+[Pcd]
+  gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath
+
+[Depex]
+  BEFORE gDwUsbDeviceGuid
diff --git a/Platforms/Hisilicon/HiKey/Include/ArmPlatform.h b/Platforms/Hisilicon/HiKey/Include/ArmPlatform.h
index ae2367e..e60478f 100644
--- a/Platforms/Hisilicon/HiKey/Include/ArmPlatform.h
+++ b/Platforms/Hisilicon/HiKey/Include/ArmPlatform.h
@@ -1,27 +1,26 @@
-/** @file
-*
-*  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-*  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
-
-//
-// We don't care about this value, but the PL031 driver depends on the macro
-// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet()
-// function, which just returns EFI_UNSUPPORTED.
-//
-//
-#define SYS_CFG_RTC                             0
-
-#endif	/* __PLATFORM_H__ */
+/** @file
+*
+*  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+//
+// We don't care about this value, but the PL031 driver depends on the macro
+// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet()
+// function, which just returns EFI_UNSUPPORTED.
+//
+//
+#define SYS_CFG_RTC                             0
+
+#endif /* __PLATFORM_H__ */
diff --git a/Platforms/Hisilicon/HiKey/Include/Guid/HiKeyVariable.h b/Platforms/Hisilicon/HiKey/Include/Guid/HiKeyVariable.h
index 5e6af53..32d51f9 100644
--- a/Platforms/Hisilicon/HiKey/Include/Guid/HiKeyVariable.h
+++ b/Platforms/Hisilicon/HiKey/Include/Guid/HiKeyVariable.h
@@ -1,24 +1,24 @@
-/** @file
-*
-*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
-*  Copyright (c) 2015-2016, Linaro. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __HIKEY_VARIABLE_H__
-#define __HIKEY_VARIABLE_H__
-
-#define HIKEY_VARIABLE_GUID \
-  { 0x66b8d063, 0x1daa, 0x4c60, { 0xb9, 0xf2, 0x55, 0x0d, 0x7e, 0xe1, 0x2f, 0x38 } }
-
-extern EFI_GUID gHiKeyVariableGuid;
-
-#endif /* __HIKEY_VARIABLE_H__ */
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015-2016, Linaro. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __HIKEY_VARIABLE_H__
+#define __HIKEY_VARIABLE_H__
+
+#define HIKEY_VARIABLE_GUID \
+  { 0x66b8d063, 0x1daa, 0x4c60, { 0xb9, 0xf2, 0x55, 0x0d, 0x7e, 0xe1, 0x2f, 0x38 } }
+
+extern EFI_GUID gHiKeyVariableGuid;
+
+#endif /* __HIKEY_VARIABLE_H__ */
diff --git a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c
index 8c4bd77..f4a47b2 100644
--- a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c
+++ b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c
@@ -1,160 +1,159 @@
-/** @file
-*
-*  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-*  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/IoLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-
-#include <Ppi/ArmMpCoreInfo.h>
-
-#include <Hi6220.h>
-
-ARM_CORE_INFO mHiKeyInfoTable[] = {
-  {
-    // Cluster 0, Core 0
-    0x0, 0x0,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (UINT64)0xFFFFFFFF
-  },
-  {
-    // Cluster 0, Core 1
-    0x0, 0x1,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (UINT64)0xFFFFFFFF
-  },
-  {
-    // Cluster 0, Core 2
-    0x0, 0x2,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (UINT64)0xFFFFFFFF
-  },
-  {
-    // Cluster 0, Core 3
-    0x0, 0x3,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (UINT64)0xFFFFFFFF
-  },
-  {
-    // Cluster 1, Core 0
-    0x1, 0x0,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (UINT64)0xFFFFFFFF
-  },
-  {
-    // Cluster 1, Core 1
-    0x1, 0x1,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (UINT64)0xFFFFFFFF
-  },
-  {
-    // Cluster 1, Core 2
-    0x1, 0x2,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (UINT64)0xFFFFFFFF
-  },
-  {
-    // Cluster 1, Core 3
-    0x1, 0x3,
-
-    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
-    (UINT64)0xFFFFFFFF
-  }
-};
-
-/**
-  Return the current Boot Mode
-
-  This function returns the boot reason on the platform
-
-  @return   Return the current Boot Mode of the platform
-
-**/
-EFI_BOOT_MODE
-ArmPlatformGetBootMode (
-  VOID
-  )
-{
-  return BOOT_WITH_FULL_CONFIGURATION;
-}
-
-/**
-  Initialize controllers that must setup in the normal world
-
-  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
-  in the PEI phase.
-
-**/
-RETURN_STATUS
-ArmPlatformInitialize (
-  IN  UINTN                     MpId
-  )
-{
-  return RETURN_SUCCESS;
-}
-
-/**
-  Initialize the system (or sometimes called permanent) memory
-
-  This memory is generally represented by the DRAM.
-
-**/
-VOID
-ArmPlatformInitializeSystemMemory (
-  VOID
-  )
-{
-}
-
-EFI_STATUS
-PrePeiCoreGetMpCoreInfo (
-  OUT UINTN                   *CoreCount,
-  OUT ARM_CORE_INFO           **ArmCoreTable
-  )
-{
-  // Only support one cluster
-  *CoreCount    = sizeof(mHiKeyInfoTable) / sizeof(ARM_CORE_INFO);
-  *ArmCoreTable = mHiKeyInfoTable;
-  return EFI_SUCCESS;
-}
-
-// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
-EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
-
-EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
-  {
-    EFI_PEI_PPI_DESCRIPTOR_PPI,
-    &mArmMpCoreInfoPpiGuid,
-    &mMpCoreInfoPpi
-  }
-};
-
-VOID
-ArmPlatformGetPlatformPpiList (
-  OUT UINTN                   *PpiListSize,
-  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
-  )
-{
-  *PpiListSize = sizeof(gPlatformPpiTable);
-  *PpiList = gPlatformPpiTable;
-}
+/** @file
+*
+*  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <Hi6220.h>
+
+ARM_CORE_INFO mHiKeyInfoTable[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 2
+    0x0, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 3
+    0x0, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 0
+    0x1, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 1
+    0x1, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 2
+    0x1, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 3
+    0x1, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  return RETURN_SUCCESS;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  // Only support one cluster
+  *CoreCount    = sizeof(mHiKeyInfoTable) / sizeof(ARM_CORE_INFO);
+  *ArmCoreTable = mHiKeyInfoTable;
+  return EFI_SUCCESS;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &mArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof(gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
diff --git a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S
index 2657606..0e8f1bb 100644
--- a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S
+++ b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S
@@ -1,74 +1,49 @@
-#
-#  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-#  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-
-#include <AsmMacroIoLibV8.h>
-#include <Library/ArmLib.h>
-
-.text
-.align 3
-
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
-GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
-
-GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
-
-
-PrimaryCoreMpid:  .word    0x0
-
-ASM_PFX(ArmPlatformPeiBootAction):
-  // The trusted firmware passes the primary CPU MPID through x0 register.
-  // Save it in a variable.
-  ldr  x1, =PrimaryCoreMpid
-  str  w0, [x1]
-  ret
-
-//UINTN
-//ArmPlatformIsPrimaryCore (
-//  IN UINTN MpId
-//  );
-ASM_PFX(ArmPlatformIsPrimaryCore):
-  LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)
-  ldrh  w1, [x1]
-  and   x0, x0, x1
-
-  ldr   x1, =PrimaryCoreMpid
-  ldrh  w1, [x1]
-
-  cmp   w0, w1
-  mov   x0, #1
-  mov   x1, #0
-  csel  x0, x0, x1, eq
-  ret
-
-//UINTN
-//ArmPlatformGetPrimaryCoreMpId (
-//  VOID
-//  );
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
-  ldr   x0, =PrimaryCoreMpid
-  ldrh  w0, [x0]
-  ret
-
-//UINTN
-//ArmPlatformGetCorePosition (
-//  IN UINTN MpId
-//  );
-// With this function: CorePos = (ClusterId * 4) + CoreId
-ASM_PFX(ArmPlatformGetCorePosition):
-  and   x1, x0, #ARM_CORE_MASK
-  and   x0, x0, #ARM_CLUSTER_MASK
-  add   x0, x1, x0, LSR #6
-  ret
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #6
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+  MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
+  cmp   w0, w1
+  cset  x0, eq
+  ret
diff --git a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf
index fa6f739..aa0b8b8 100644
--- a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf
+++ b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf
@@ -1,53 +1,51 @@
-#
-#  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-#  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = HiKeyLib
-  FILE_GUID                      = 1f6c5192-f35c-462d-877c-8ee3227fff01
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmPlatformLib
-
-[Packages]
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  ArmPkg/ArmPkg.dec
-  ArmPlatformPkg/ArmPlatformPkg.dec
-  OpenPlatformPkg/Chips/Hisilicon/Hi6220/Hi6220.dec
-  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec
-
-[LibraryClasses]
-  IoLib
-  ArmLib
-  HobLib
-  MemoryAllocationLib
-  SerialPortLib
-
-[Sources.common]
-  HiKey.c
-  HiKeyMem.c
-
-[Sources.AARCH64]
-  HiKeyHelper.S | GCC
-
-[FeaturePcd]
-  gEmbeddedTokenSpaceGuid.PcdCacheEnable
-
-[FixedPcd]
-  gArmTokenSpaceGuid.PcdSystemMemoryBase
-  gArmTokenSpaceGuid.PcdSystemMemorySize
-  gArmTokenSpaceGuid.PcdFvBaseAddress
-
-  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKeyLib
+  FILE_GUID                      = 1f6c5192-f35c-462d-877c-8ee3227fff01
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/Hi6220/Hi6220.dec
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+
+[Sources.common]
+  HiKey.c
+  HiKeyMem.c
+
+[Sources.AARCH64]
+  HiKeyHelper.S
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c
index 2d118e0..c388a7a 100644
--- a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c
+++ b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c
@@ -1,210 +1,204 @@
-/** @file
-*
-*  Copyright (c) 2014-2015, Linaro Limited. All rights reserved.
-*  Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-
-#include <Hi6220.h>
-
-// The total number of descriptors, including the final "end-of-table" descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
-
-// DDR attributes
-#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
-#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
-
-#define HIKEY_EXTRA_SYSTEM_MEMORY_BASE  0x40000000
-#define HIKEY_EXTRA_SYSTEM_MEMORY_SIZE  0x40000000
-
-STATIC struct HiKeyReservedMemory {
-  EFI_PHYSICAL_ADDRESS         Offset;
-  EFI_PHYSICAL_ADDRESS         Size;
-} HiKeyReservedMemoryBuffer [] = {
-  { 0x05E00000, 0x00100000 },    // MCU
-  { 0x05F01000, 0x00001000 },    // ADB REBOOT "REASON"
-  { 0x06DFF000, 0x00001000 },    // MAILBOX
-  { 0x0740F000, 0x00001000 },    // MAILBOX
-  { 0x21F00000, 0x00100000 },    // PSTORE/RAMOOPS
-  { 0x3E000000, 0x02000000 }     // TEE OS
-};
-
-STATIC
-UINT64
-EFIAPI
-HiKeyInitMemorySize (
-  IN VOID
-  )
-{
-  UINT32               Count, Data, MemorySize;
-
-  Count = 0;
-  while (MmioRead32 (MDDRC_AXI_BASE + AXI_REGION_MAP_OFFSET (Count)) != 0) {
-    Count++;
-  }
-  Data = MmioRead32 (MDDRC_AXI_BASE + AXI_REGION_MAP_OFFSET (Count - 1));
-  MemorySize = 16 << ((Data >> 8) & 0x7);
-  MemorySize += Data << 24;
-  return (UINT64) (MemorySize << 20);
-}
-
-/**
-  Return the Virtual Memory Map of your platform
-
-  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
-
-  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
-                                    Virtual Memory mapping. This array must be ended by a zero-filled
-                                    entry
-
-**/
-VOID
-ArmPlatformGetVirtualMemoryMap (
-  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
-  )
-{
-  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
-  UINTN                         Index = 0, Count, ReservedTop;
-  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
-  EFI_PEI_HOB_POINTERS          NextHob;
-  EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
-  UINT64                        ResourceLength;
-  EFI_PHYSICAL_ADDRESS          ResourceTop;
-  UINT64                        MemorySize, AdditionalMemorySize;
-
-  MemorySize = HiKeyInitMemorySize ();
-
-  ResourceAttributes = (
-      EFI_RESOURCE_ATTRIBUTE_PRESENT |
-      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
-      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
-      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
-      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
-      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
-      EFI_RESOURCE_ATTRIBUTE_TESTED
-  );
-
-  // Create initial Base Hob for system memory.
-  BuildResourceDescriptorHob (
-      EFI_RESOURCE_SYSTEM_MEMORY,
-      ResourceAttributes,
-      PcdGet64 (PcdSystemMemoryBase),
-      PcdGet64 (PcdSystemMemorySize)
-  );
-
-  NextHob.Raw = GetHobList ();
-  Count = sizeof (HiKeyReservedMemoryBuffer) / sizeof (struct HiKeyReservedMemory);
-  while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL)
-  {
-    if (Index >= Count)
-      break;
-    if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
-        (HiKeyReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) &&
-        ((HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size) <=
-         NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))
-    {
-      ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
-      ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
-      ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
-      ReservedTop = HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size;
-
-      // Create the System Memory HOB for the reserved buffer
-      BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED,
-                                  EFI_RESOURCE_ATTRIBUTE_PRESENT,
-                                  HiKeyReservedMemoryBuffer[Index].Offset,
-                                  HiKeyReservedMemoryBuffer[Index].Size);
-      // Update the HOB
-      NextHob.ResourceDescriptor->ResourceLength = HiKeyReservedMemoryBuffer[Index].Offset - NextHob.ResourceDescriptor->PhysicalStart;
-
-      // If there is some memory available on the top of the reserved memory then create a HOB
-      if (ReservedTop < ResourceTop)
-      {
-        BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
-                                    ResourceAttributes,
-                                    ReservedTop,
-                                    ResourceTop - ReservedTop);
-      }
-      Index++;
-    }
-    NextHob.Raw = GET_NEXT_HOB (NextHob);
-  }
-
-  AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize);
-  if (AdditionalMemorySize >= SIZE_1GB) {
-    // Declared the additional memory
-    ResourceAttributes =
-        EFI_RESOURCE_ATTRIBUTE_PRESENT |
-        EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
-        EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
-        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
-        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
-        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
-        EFI_RESOURCE_ATTRIBUTE_TESTED;
-
-    BuildResourceDescriptorHob (
-      EFI_RESOURCE_SYSTEM_MEMORY,
-      ResourceAttributes,
-      HIKEY_EXTRA_SYSTEM_MEMORY_BASE,
-      HIKEY_EXTRA_SYSTEM_MEMORY_SIZE);
-  }
-
-  ASSERT (VirtualMemoryMap != NULL);
-
-  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
-  if (VirtualMemoryTable == NULL) {
-      return;
-  }
-
-  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
-      CacheAttributes = DDR_ATTRIBUTES_CACHED;
-  } else {
-      CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
-  }
-
-  Index = 0;
-
-  // Hi6220 SOC peripherals
-  VirtualMemoryTable[Index].PhysicalBase    = HI6220_PERIPH_BASE;
-  VirtualMemoryTable[Index].VirtualBase     = HI6220_PERIPH_BASE;
-  VirtualMemoryTable[Index].Length          = HI6220_PERIPH_SZ;
-  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
-
-  // DDR - predefined 1GB size
-  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdSystemMemoryBase);
-  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase);
-  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemorySize);
-  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
-
-  // If DDR capacity is 2GB size, append a new entry to fill the gap.
-  if (AdditionalMemorySize >= SIZE_1GB) {
-    VirtualMemoryTable[++Index].PhysicalBase = HIKEY_EXTRA_SYSTEM_MEMORY_BASE;
-    VirtualMemoryTable[Index].VirtualBase    = HIKEY_EXTRA_SYSTEM_MEMORY_BASE;
-    VirtualMemoryTable[Index].Length         = HIKEY_EXTRA_SYSTEM_MEMORY_SIZE;
-    VirtualMemoryTable[Index].Attributes     = CacheAttributes;
-  }
-
-  // End of Table
-  VirtualMemoryTable[++Index].PhysicalBase  = 0;
-  VirtualMemoryTable[Index].VirtualBase     = 0;
-  VirtualMemoryTable[Index].Length          = 0;
-  VirtualMemoryTable[Index].Attributes      = (ARM_MEMORY_REGION_ATTRIBUTES)0;
-
-  ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
-
-  *VirtualMemoryMap = VirtualMemoryTable;
-}
+/** @file
+*
+*  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <Hi6220.h>
+
+// The total number of descriptors, including the final "end-of-table" descriptor.
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+#define HIKEY_EXTRA_SYSTEM_MEMORY_BASE  0x40000000
+#define HIKEY_EXTRA_SYSTEM_MEMORY_SIZE  0x40000000
+
+STATIC struct HiKeyReservedMemory {
+  EFI_PHYSICAL_ADDRESS         Offset;
+  EFI_PHYSICAL_ADDRESS         Size;
+} HiKeyReservedMemoryBuffer [] = {
+  { 0x05E00000, 0x00100000 },    // MCU
+  { 0x05F01000, 0x00001000 },    // ADB REBOOT "REASON"
+  { 0x06DFF000, 0x00001000 },    // MAILBOX
+  { 0x0740F000, 0x00001000 },    // MAILBOX
+  { 0x21F00000, 0x00100000 },    // PSTORE/RAMOOPS
+  { 0x3E000000, 0x02000000 }     // TEE OS
+};
+
+STATIC
+UINT64
+EFIAPI
+HiKeyInitMemorySize (
+  IN VOID
+  )
+{
+  UINT32               Data;
+  UINT64               MemorySize;
+
+  Data = MmioRead32 (MDDRC_AXI_BASE + AXI_REGION_MAP);
+  MemorySize = HIKEY_REGION_SIZE(Data);
+  return MemorySize;
+}
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  UINTN                         Index = 0, Count, ReservedTop;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+  EFI_PEI_HOB_POINTERS          NextHob;
+  EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
+  UINT64                        ResourceLength;
+  EFI_PHYSICAL_ADDRESS          ResourceTop;
+  UINT64                        MemorySize, AdditionalMemorySize;
+
+  MemorySize = HiKeyInitMemorySize ();
+  if (MemorySize == 0) {
+    MemorySize = PcdGet64 (PcdSystemMemorySize);
+  }
+
+  ResourceAttributes = (
+    EFI_RESOURCE_ATTRIBUTE_PRESENT |
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_TESTED
+  );
+
+  // Create initial Base Hob for system memory.
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_SYSTEM_MEMORY,
+    ResourceAttributes,
+    PcdGet64 (PcdSystemMemoryBase),
+    PcdGet64 (PcdSystemMemorySize)
+  );
+
+  NextHob.Raw = GetHobList ();
+  Count = sizeof (HiKeyReservedMemoryBuffer) / sizeof (struct HiKeyReservedMemory);
+  while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
+    if (Index >= Count) {
+      break;
+    }
+    if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
+        (HiKeyReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) &&
+        ((HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size) <=
+         NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength)) {
+      ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
+      ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
+      ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
+      ReservedTop = HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size;
+
+      // Create the System Memory HOB for the reserved buffer
+      BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED,
+                                  EFI_RESOURCE_ATTRIBUTE_PRESENT,
+                                  HiKeyReservedMemoryBuffer[Index].Offset,
+                                  HiKeyReservedMemoryBuffer[Index].Size);
+      // Update the HOB
+      NextHob.ResourceDescriptor->ResourceLength = HiKeyReservedMemoryBuffer[Index].Offset - NextHob.ResourceDescriptor->PhysicalStart;
+
+      // If there is some memory available on the top of the reserved memory then create a HOB
+      if (ReservedTop < ResourceTop) {
+        BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
+                                    ResourceAttributes,
+                                    ReservedTop,
+                                    ResourceTop - ReservedTop);
+      }
+      Index++;
+    }
+    NextHob.Raw = GET_NEXT_HOB (NextHob);
+  }
+
+  AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize);
+  if (AdditionalMemorySize >= SIZE_1GB) {
+    // Declared the additional memory
+    ResourceAttributes =
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+    BuildResourceDescriptorHob (
+      EFI_RESOURCE_SYSTEM_MEMORY,
+      ResourceAttributes,
+      HIKEY_EXTRA_SYSTEM_MEMORY_BASE,
+      HIKEY_EXTRA_SYSTEM_MEMORY_SIZE);
+  }
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+    return;
+  }
+
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+    CacheAttributes = DDR_ATTRIBUTES_CACHED;
+  } else {
+    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+  }
+
+  Index = 0;
+
+  // Hi6220 SOC peripherals
+  VirtualMemoryTable[Index].PhysicalBase    = HI6220_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = HI6220_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length          = HI6220_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // DDR - predefined 1GB size
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemorySize);
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+
+  // If DDR capacity is 2GB size, append a new entry to fill the gap.
+  if (AdditionalMemorySize >= SIZE_1GB) {
+    VirtualMemoryTable[++Index].PhysicalBase = HIKEY_EXTRA_SYSTEM_MEMORY_BASE;
+    VirtualMemoryTable[Index].VirtualBase    = HIKEY_EXTRA_SYSTEM_MEMORY_BASE;
+    VirtualMemoryTable[Index].Length         = HIKEY_EXTRA_SYSTEM_MEMORY_SIZE;
+    VirtualMemoryTable[Index].Attributes     = CacheAttributes;
+  }
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase  = 0;
+  VirtualMemoryTable[Index].VirtualBase     = 0;
+  VirtualMemoryTable[Index].Length          = 0;
+  VirtualMemoryTable[Index].Attributes      = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platforms/Hisilicon/HiKey960/Binary/lpm3.img b/Platforms/Hisilicon/HiKey960/Binary/lpm3.img
new file mode 100644
index 0000000..bd0243b
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Binary/lpm3.img
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.dec b/Platforms/Hisilicon/HiKey960/HiKey960.dec
new file mode 100644
index 0000000..6dea5b8
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960.dec
@@ -0,0 +1,39 @@
+#
+#  Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010019
+  PACKAGE_NAME                   = HiKey960
+  PACKAGE_GUID                   = a71a681b-3c46-4c92-9fc2-986919026362
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+  Include                        # Root include for the package
+
+[Guids.common]
+  gDwUsbDeviceGuid              =  { 0x72d78ea6, 0x4dee, 0x11e3, { 0x81, 0x00, 0xf3, 0x84, 0x2a, 0x48, 0xd0, 0xa0 } }
+  gHiKey960TokenSpaceGuid       =  { 0x73efcd58, 0x3320, 0x4043, { 0xa8, 0x87, 0xd1, 0xf9, 0xb4, 0x49, 0x48, 0x87 } }
+  gHiKey960VariableGuid         =  { 0x29727c8d, 0x3531, 0x7a41, { 0x81, 0x9c, 0x7e, 0x50, 0x4e, 0xdd, 0x24, 0x3f } }
+
+[PcdsFixedAtBuild.common]
+  gHiKey960TokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|L""|VOID*|0x00000001
+  gHiKey960TokenSpaceGuid.PcdArmFastbootFlashLimit|L""|VOID*|0x00000002
+  gHiKey960TokenSpaceGuid.PcdXloaderDevicePath|L""|VOID*|0x00000003
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.dsc b/Platforms/Hisilicon/HiKey960/HiKey960.dsc
new file mode 100644
index 0000000..ae979d5
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960.dsc
@@ -0,0 +1,546 @@
+#
+#  Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = HiKey960
+  PLATFORM_GUID                  = ce90122d-5e18-4016-9030-5376535c81b6
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/HiKey960
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.fdf
+
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+
+  ArmPlatformLib|OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Lib.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  AbootimgLib|EmbeddedPkg/Library/AbootimgLib/AbootimgLib.inf
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  UsbSerialNumberLib|OpenPlatformPkg/Library/UsbSerialNumberLib/UsbSerialNumberLib.inf
+
+  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+
+  #
+  # Allow dynamic PCDs
+  #
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+
+  # BDS Libraries
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  PlatformBootManagerLib|OpenPlatformPkg/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # UiApp dependencies
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+
+  # Network Libraries
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+
+[LibraryClasses.AARCH64]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.SEC]
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+[LibraryClasses.common.DXE_CORE]
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+
+[BuildOptions]
+  GCC:*_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/MdeModulePkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Include -I$(WORKSPACE)/EmbeddedPkg/Include
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+  #
+  # Control what commands are supported from the UI
+  # Turn these on and off to add features or save size
+  #
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+  # DEBUG_ASSERT_ENABLED       0x01
+  # DEBUG_PRINT_ENABLED        0x02
+  # DEBUG_CODE_ENABLED         0x04
+  # CLEAR_MEMORY_ENABLED       0x08
+  # ASSERT_BREAKPOINT_ENABLED  0x10
+  # ASSERT_DEADLOOP_ENABLED    0x20
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+  #  DEBUG_INIT      0x00000001  // Initialization
+  #  DEBUG_WARN      0x00000002  // Warnings
+  #  DEBUG_LOAD      0x00000004  // Load events
+  #  DEBUG_FS        0x00000008  // EFI File system
+  #  DEBUG_POOL      0x00000010  // Alloc & Free's
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free's
+  #  DEBUG_INFO      0x00000040  // Verbose
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
+  #  DEBUG_VARIABLE  0x00000100  // Variable
+  #  DEBUG_BM        0x00000400  // Boot Manager
+  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+  #  DEBUG_NET       0x00004000  // SNI Driver
+  #  DEBUG_UNDI      0x00010000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // UNDI Driver
+  #  DEBUG_EVENT     0x00080000  // Event messages
+  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
+  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
+  #  DEBUG_ERROR     0x80000000  // Error
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8008000F
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro"
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha"
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"HiKey960"
+
+  # TimerPeriod
+  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000
+
+  # System Memory (3GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0xC0000000
+
+  # HiKey960 Dual-Cluster profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|2
+
+  gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+
+  #
+  # ARM PrimeCell
+  #
+
+  ## PL011 - Serial Terminal
+  DEFINE SERIAL_BASE = 0xFFF32000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+  gArmPlatformTokenSpaceGuid.PL011UartInteger|10
+  gArmPlatformTokenSpaceGuid.PL011UartFractional|26
+
+  ## PL011 - Serial Debug UART
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|$(SERIAL_BASE)
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|19200000
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200
+
+  ## PL031 RealTimeClock
+  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xFFF05000
+
+  #
+  # ARM General Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xE82B1000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE82B2000
+
+  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+  # GUID of the UEFI Shell
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  #
+  # Ufs
+  #
+  gDwUfsHcDxeTokenSpaceGuid.PcdDwUfsHcDxeBaseAddress|0xFF3B0000
+
+  #
+  # DW USB3 controller
+  #
+  gDwUsb3DxeTokenSpaceGuid.PcdDwUsb3DxeBaseAddress|0xFF100000
+
+  #
+  #
+  # Fastboot
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x18d1
+  gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0xd00d
+  gHiKey960TokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00003BFF0000000000)/UFS(0x0,0x3)"
+  # Flash limit 128M/time, for memory concern
+  gHiKey960TokenSpaceGuid.PcdArmFastbootFlashLimit|"134217728"
+  gHiKey960TokenSpaceGuid.PcdXloaderDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00003BFF0000000000)/UFS(0x0,0x0)"
+
+  #
+  # Android Loader
+  #
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00003BFF0000000000)/UFS(0x0,0x3)/HD(7,GPT,D3340696-9B95-4C64-8DF6-E6D4548FBA41,0x12100,0x4000)"
+  gEmbeddedTokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00F037FF0000000000)/SD(0x0)/HD(1,MBR,0x00000000,0x3F,0x21FC0)"
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|1
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  #
+  # GPIO
+  #
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf
+  ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  OpenPlatformPkg/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # MMC/SD
+  #
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.inf
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf
+  MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf
+
+  #
+  # USB Host Support
+  #
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # UEFI Network Stack
+  #
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+  #
+  # AX88772 Ethernet Driver
+  #
+  OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
+
+  #
+  # Ufs
+  #
+  OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.inf
+  MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/HiKey960UsbDxe.inf
+  OpenPlatformPkg/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.inf
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.inf
+  EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
+
+  #
+  # Android Loader
+  #
+  EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf {
+    <LibraryClasses>
+      BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  }
+
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.fdf b/Platforms/Hisilicon/HiKey960/HiKey960.fdf
new file mode 100644
index 0000000..ec94e60
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960.fdf
@@ -0,0 +1,377 @@
+#
+#  Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.BL33_AP_UEFI]
+BaseAddress   = 0x1AC98000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0xF0
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x000F0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+  #
+  # GPIO
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf
+  INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
+
+  #
+  # Virtual Keyboard
+  #
+  INF OpenPlatformPkg/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
+
+  #
+  # MMC/SD
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+  INF OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf
+  INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf
+
+  #
+  # UEFI Network Stack
+  #
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+  #
+  # AX88772 Ethernet Driver for Apple Ethernet Adapter
+  #
+  INF OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
+
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Ufs
+  #
+  INF OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.inf
+  INF MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatBinPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  #
+  # USB Host Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+  #
+  # USB Mass Storage Support
+  #
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # USB Peripheral Support
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/HiKey960UsbDxe.inf
+  INF OpenPlatformPkg/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.inf
+  INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
+
+  #
+  # Fastboot
+  #
+  INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
+
+  #
+  # Android Loader
+  #
+  INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+#
+# These SEC rules are used for ArmPlatformPkg/PrePi module.
+# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the
+# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint
+#
+[Rule.ARM.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.AARCH64.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+# A shim specific rule is required to ensure the alignment is 4K.
+# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)
+[Rule.ARM.SEC.SHIM]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+  DXE_DEPEX    DXE_DEPEX              Optional |.depex
+  PE32         PE32                   |.efi
+  UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)" Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI               |.acpi
+    RAW ASL                |.aml
+  }
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c b/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c
new file mode 100644
index 0000000..6e4db11
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c
@@ -0,0 +1,699 @@
+/** @file
+*
+*  Copyright (c) 2016-2017, Linaro Ltd. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Guid/EventGroup.h>
+#include <Guid/HiKey960Variable.h>
+
+#include <Hi3660.h>
+#include <Hkadc.h>
+#include <libfdt.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+#include <Protocol/Abootimg.h>
+#include <Protocol/BlockIo.h>
+#include <Protocol/DevicePathToText.h>
+#include <Protocol/EmbeddedGpio.h>
+#include <Protocol/NonDiscoverableDevice.h>
+#include <Protocol/PlatformVirtualKeyboard.h>
+
+#define ADC_ADCIN0                       0
+#define ADC_ADCIN1                       1
+#define ADC_ADCIN2                       2
+
+#define HKADC_DATA_GRADE0                0
+#define HKADC_DATA_GRADE1                100
+#define HKADC_DATA_GRADE2                300
+#define HKADC_DATA_GRADE3                500
+#define HKADC_DATA_GRADE4                700
+#define HKADC_DATA_GRADE5                900
+#define HKADC_DATA_GRADE6                1100
+#define HKADC_DATA_GRADE7                1300
+#define HKADC_DATA_GRADE8                1500
+#define HKADC_DATA_GRADE9                1700
+#define HKADC_DATA_GRADE10               1800
+
+#define BOARDID_VALUE0                   0
+#define BOARDID_VALUE1                   1
+#define BOARDID_VALUE2                   2
+#define BOARDID_VALUE3                   3
+#define BOARDID_VALUE4                   4
+#define BOARDID_VALUE5                   5
+#define BOARDID_VALUE6                   6
+#define BOARDID_VALUE7                   7
+#define BOARDID_VALUE8                   8
+#define BOARDID_VALUE9                   9
+#define BOARDID_UNKNOW                   0xF
+
+#define BOARDID3_BASE                    5
+
+#define HIKEY960_BOARDID_V1              5300
+#define HIKEY960_BOARDID_V2              5301
+
+#define HIKEY960_COMPATIBLE_LEDS_V1      "gpio-leds_v1"
+#define HIKEY960_COMPATIBLE_LEDS_V2      "gpio-leds_v2"
+#define HIKEY960_COMPATIBLE_HUB_V1       "hisilicon,gpio_hubv1"
+#define HIKEY960_COMPATIBLE_HUB_V2       "hisilicon,gpio_hubv2"
+
+#define SERIAL_NUMBER_SIZE               17
+#define SERIAL_NUMBER_BLOCK_SIZE         EFI_PAGE_SIZE
+#define SERIAL_NUMBER_LBA                20
+#define RANDOM_MAX                       0x7FFFFFFFFFFFFFFF
+#define RANDOM_MAGIC                     0x9A4DBEAF
+
+#define ADB_REBOOT_ADDRESS               0x32100000
+#define ADB_REBOOT_BOOTLOADER            0x77665500
+#define ADB_REBOOT_NONE                  0x77665501
+
+#define DETECT_SW_FASTBOOT               68        // GPIO8_4
+
+typedef struct {
+  UINT64        Magic;
+  UINT64        Data;
+  CHAR16        UnicodeSN[SERIAL_NUMBER_SIZE];
+} RANDOM_SERIAL_NUMBER;
+
+STATIC UINTN    mBoardId;
+
+STATIC EMBEDDED_GPIO   *mGpio;
+
+STATIC
+VOID
+InitAdc (
+  VOID
+  )
+{
+  // reset hkadc
+  MmioWrite32 (CRG_PERRSTEN2, PERRSTEN2_HKADCSSI);
+  // wait a few clock cycles
+  MicroSecondDelay (2);
+  MmioWrite32 (CRG_PERRSTDIS2, PERRSTEN2_HKADCSSI);
+  MicroSecondDelay (2);
+  // enable hkadc clock
+  MmioWrite32 (CRG_PERDIS2, PEREN2_HKADCSSI);
+  MicroSecondDelay (2);
+  MmioWrite32 (CRG_PEREN2, PEREN2_HKADCSSI);
+  MicroSecondDelay (2);
+}
+
+STATIC
+EFI_STATUS
+AdcGetAdc (
+  IN  UINTN         Channel,
+  OUT UINTN         *Value
+  )
+{
+  UINT32            Data;
+  UINT16            Value1, Value0;
+
+  if (Channel > HKADC_CHANNEL_MAX) {
+    DEBUG ((DEBUG_ERROR, "invalid channel:%d\n", Channel));
+    return EFI_OUT_OF_RESOURCES;
+  }
+  // configure the read/write operation for external HKADC
+  MmioWrite32 (HKADC_WR01_DATA, HKADC_WR01_VALUE | Channel);
+  MmioWrite32 (HKADC_WR23_DATA, HKADC_WR23_VALUE);
+  MmioWrite32 (HKADC_WR45_DATA, HKADC_WR45_VALUE);
+  // configure the number of accessing registers
+  MmioWrite32 (HKADC_WR_NUM, HKADC_WR_NUM_VALUE);
+  // configure delay of accessing registers
+  MmioWrite32 (HKADC_DELAY01, HKADC_CHANNEL0_DELAY01_VALUE);
+  MmioWrite32 (HKADC_DELAY23, HKADC_DELAY23_VALUE);
+
+  // start HKADC
+  MmioWrite32 (HKADC_DSP_START, 1);
+  do {
+    Data = MmioRead32 (HKADC_DSP_START);
+  } while (Data & 1);
+
+  // convert AD result
+  Value1 = (UINT16)MmioRead32 (HKADC_DSP_RD2_DATA);
+  Value0 = (UINT16)MmioRead32 (HKADC_DSP_RD3_DATA);
+
+  Data = ((Value1 << 4) & HKADC_VALUE_HIGH) | ((Value0 >> 4) & HKADC_VALUE_LOW);
+  *Value = Data;
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+AdcGetValue (
+  IN UINTN         Channel,
+  IN OUT UINTN     *Value
+  )
+{
+  EFI_STATUS       Status;
+  UINTN            Result;
+
+  Status = AdcGetAdc (Channel, Value);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // convert ADC value to micro-volt
+  Result = ((*Value & HKADC_VALID_VALUE) * HKADC_VREF_1V8) / HKADC_ACCURACY;
+  *Value = Result;
+  return EFI_SUCCESS;
+}
+
+STATIC
+UINTN
+AdcinDataRemap (
+  IN UINTN           AdcinValue
+  )
+{
+  UINTN              Result;
+
+  if (AdcinValue < HKADC_DATA_GRADE0) {
+    Result = BOARDID_UNKNOW;
+  } else if (AdcinValue < HKADC_DATA_GRADE1) {
+    Result = BOARDID_VALUE0;
+  } else if (AdcinValue < HKADC_DATA_GRADE2) {
+    Result = BOARDID_VALUE1;
+  } else if (AdcinValue < HKADC_DATA_GRADE3) {
+    Result = BOARDID_VALUE2;
+  } else if (AdcinValue < HKADC_DATA_GRADE4) {
+    Result = BOARDID_VALUE3;
+  } else if (AdcinValue < HKADC_DATA_GRADE5) {
+    Result = BOARDID_VALUE4;
+  } else if (AdcinValue < HKADC_DATA_GRADE6) {
+    Result = BOARDID_VALUE5;
+  } else if (AdcinValue < HKADC_DATA_GRADE7) {
+    Result = BOARDID_VALUE6;
+  } else if (AdcinValue < HKADC_DATA_GRADE8) {
+    Result = BOARDID_VALUE7;
+  } else if (AdcinValue < HKADC_DATA_GRADE9) {
+    Result = BOARDID_VALUE8;
+  } else if (AdcinValue < HKADC_DATA_GRADE10) {
+    Result = BOARDID_VALUE9;
+  } else {
+    Result = BOARDID_UNKNOW;
+  }
+  return Result;
+}
+
+STATIC
+EFI_STATUS
+InitBoardId (
+  OUT UINTN          *Id
+  )
+{
+  UINTN              Adcin0, Adcin1, Adcin2;
+  UINTN              Adcin0Remap, Adcin1Remap, Adcin2Remap;
+
+  InitAdc ();
+
+  // read ADC channel0 data
+  AdcGetValue (ADC_ADCIN0, &Adcin0);
+  DEBUG ((DEBUG_ERROR, "[BDID]Adcin0:%d\n", Adcin0));
+  Adcin0Remap = AdcinDataRemap (Adcin0);
+  DEBUG ((DEBUG_ERROR, "[BDID]Adcin0Remap:%d\n", Adcin0Remap));
+  if (Adcin0Remap == BOARDID_UNKNOW) {
+    return EFI_INVALID_PARAMETER;
+  }
+  // read ADC channel1 data
+  AdcGetValue (ADC_ADCIN1, &Adcin1);
+  DEBUG ((DEBUG_ERROR, "[BDID]Adcin1:%d\n", Adcin1));
+  Adcin1Remap = AdcinDataRemap (Adcin1);
+  DEBUG ((DEBUG_ERROR, "[BDID]Adcin1Remap:%d\n", Adcin1Remap));
+  if (Adcin1Remap == BOARDID_UNKNOW) {
+    return EFI_INVALID_PARAMETER;
+  }
+  // read ADC channel2 data
+  AdcGetValue (ADC_ADCIN2, &Adcin2);
+  DEBUG ((DEBUG_ERROR, "[BDID]Adcin2:%d\n", Adcin2));
+  Adcin2Remap = AdcinDataRemap (Adcin2);
+  DEBUG ((DEBUG_ERROR, "[BDID]Adcin2Remap:%d\n", Adcin2Remap));
+  if (Adcin2Remap == BOARDID_UNKNOW) {
+    return EFI_INVALID_PARAMETER;
+  }
+  *Id = BOARDID3_BASE * 1000 + (Adcin2Remap * 100) + (Adcin1Remap * 10) + Adcin0Remap;
+  DEBUG ((DEBUG_ERROR, "[BDID]boardid: %d\n", *Id));
+  return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+InitSdCard (
+  IN VOID
+  )
+{
+  UINT32        Data;
+
+  // LDO16
+  Data = MmioRead32 (PMU_REG_BASE + (0x79 << 2)) & 7;
+  Data |= 6;
+  MmioWrite32 (PMU_REG_BASE + (0x79 << 2), Data);
+  MmioOr32 (PMU_REG_BASE + (0x78 << 2), 2);
+  MicroSecondDelay (100);
+
+  // LDO9
+  Data = MmioRead32 (PMU_REG_BASE + (0x6b << 2)) & 7;
+  Data |= 5;
+  MmioWrite32 (PMU_REG_BASE + (0x6b << 2), Data);
+  MmioOr32 (PMU_REG_BASE + (0x6a << 2), 2);
+  MicroSecondDelay (100);
+
+  // GPIO203
+  MmioWrite32 (0xfff11000 + (24 << 2), 0); // GPIO function
+
+  // SD pinmux
+  MmioWrite32 (0xff37e000 + 0x0, 1); // SD_CLK
+  MmioWrite32 (0xff37e000 + 0x4, 1); // SD_CMD
+  MmioWrite32 (0xff37e000 + 0x8, 1); // SD_DATA0
+  MmioWrite32 (0xff37e000 + 0xc, 1); // SD_DATA1
+  MmioWrite32 (0xff37e000 + 0x10, 1); // SD_DATA2
+  MmioWrite32 (0xff37e000 + 0x14, 1); // SD_DATA3
+  MmioWrite32 (0xff37e800 + 0x0, 15 << 4); // SD_CLK float with 32mA
+  MmioWrite32 (0xff37e800 + 0x4, (1 << 0) | (8 << 4)); // SD_CMD
+  MmioWrite32 (0xff37e800 + 0x8, (1 << 0) | (8 << 4)); // SD_DATA0
+  MmioWrite32 (0xff37e800 + 0xc, (1 << 0) | (8 << 4)); // SD_DATA1
+  MmioWrite32 (0xff37e800 + 0x10, (1 << 0) | (8 << 4)); // SD_DATA2
+  MmioWrite32 (0xff37e800 + 0x14, (1 << 0) | (8 << 4)); // SD_DATA3
+
+  do {
+    MmioOr32 (CRG_REG_BASE + 0xb8, (1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
+    Data = MmioRead32 (CRG_REG_BASE + 0xb8);
+  } while ((Data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
+
+  // Unreset SD controller
+  MmioWrite32 (CRG_PERRSTDIS4, 1 << 18);
+  do {
+    Data = MmioRead32 (CRG_PERRSTSTAT4);
+  } while ((Data & (1 << 18)) == (1 << 18));
+  // Enable SD controller clock
+  MmioOr32 (CRG_REG_BASE + 0, 1 << 30);
+  MmioOr32 (CRG_REG_BASE + 0x40, 1 << 17);
+  do {
+    Data = MmioRead32 (CRG_REG_BASE + 0x48);
+  } while ((Data & (1 << 17)) != (1 << 17));
+}
+
+VOID
+InitPeripherals (
+  IN VOID
+  )
+{
+  // Enable FPLL0
+  MmioOr32 (SCTRL_SCFPLLCTRL0, SCTRL_SCFPLLCTRL0_FPLL0_EN);
+
+  InitSdCard ();
+
+  // Enable wifi clock
+  MmioOr32 (PMIC_HARDWARE_CTRL0, PMIC_HARDWARE_CTRL0_WIFI_CLK);
+  MmioOr32 (PMIC_OSC32K_ONOFF_CTRL, PMIC_OSC32K_ONOFF_CTRL_EN_32K);
+}
+
+/**
+  Notification function of the event defined as belonging to the
+  EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in
+  the entry point of the driver.
+
+  This function is called when an event belonging to the
+  EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an
+  event is signalled once at the end of the dispatching of all
+  drivers (end of the so called DXE phase).
+
+  @param[in]  Event    Event declared in the entry point of the driver whose
+                       notification function is being invoked.
+  @param[in]  Context  NULL
+**/
+STATIC
+VOID
+OnEndOfDxe (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+}
+
+EFI_STATUS
+EFIAPI
+AbootimgAppendKernelArgs (
+  IN CHAR16            *Args,
+  IN UINTN              Size
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_BLOCK_IO_PROTOCOL      *BlockIoProtocol;
+  VOID                       *DataPtr;
+  RANDOM_SERIAL_NUMBER       *RandomSN;
+  EFI_DEVICE_PATH_PROTOCOL   *FlashDevicePath;
+  EFI_HANDLE                  FlashHandle;
+
+  if (Args == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePath, &FlashHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
+  Status = gBS->OpenProtocol (
+                  FlashHandle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &BlockIoProtocol,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_WARN, "Warning: Couldn't open block device (status: %r)\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  DataPtr = AllocatePages (1);
+  if (DataPtr == NULL) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+  Status = BlockIoProtocol->ReadBlocks (
+                              BlockIoProtocol,
+                              BlockIoProtocol->Media->MediaId,
+                              SERIAL_NUMBER_LBA,
+                              SERIAL_NUMBER_BLOCK_SIZE,
+                              DataPtr
+                              );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_WARN, "Warning: Failed on reading blocks\n"));
+    goto Exit;
+  }
+  RandomSN = (RANDOM_SERIAL_NUMBER *)DataPtr;
+  if (RandomSN->Magic != RANDOM_MAGIC) {
+    UnicodeSPrint(
+      RandomSN->UnicodeSN, SERIAL_NUMBER_SIZE * sizeof (CHAR16),
+      L"0123456789abcdef"
+      );
+  }
+  if (mBoardId == HIKEY960_BOARDID_V1) {
+    UnicodeSPrint (
+      Args + StrLen (Args), Size - StrLen (Args),
+      L" earlycon=pl011,0xfdf05000,115200 console=ttyAMA5 androidboot.serialno=%s",
+      RandomSN->UnicodeSN
+      );
+  } else {
+    UnicodeSPrint (
+      Args + StrLen (Args), Size - StrLen (Args),
+      L" earlycon=pl011,0xfff32000,115200 console=ttyAMA6 androidboot.serialno=%s",
+      RandomSN->UnicodeSN
+      );
+  }
+  FreePages (DataPtr, 1);
+  return EFI_SUCCESS;
+Exit:
+  FreePages (DataPtr, 1);
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+AbootimgUpdateDtb (
+  IN  EFI_PHYSICAL_ADDRESS        OrigFdtBase,
+  OUT EFI_PHYSICAL_ADDRESS       *NewFdtBase
+  )
+{
+  //UINT8            *FdtPtr;
+  UINTN             FdtSize, NumPages;
+  INTN              err, offset;
+  EFI_STATUS        Status;
+
+  //
+  // Sanity checks on the original FDT blob.
+  //
+  err = fdt_check_header ((VOID*)(UINTN)OrigFdtBase);
+  if (err != 0) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Device Tree header not valid (err:%d)\n", err));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Store the FDT as Runtime Service Data to prevent the Kernel from
+  // overwritting its data.
+  //
+  FdtSize = fdt_totalsize ((VOID *)(UINTN)OrigFdtBase);
+  NumPages = EFI_SIZE_TO_PAGES (FdtSize) + 20;
+  Status = gBS->AllocatePages (
+                  AllocateAnyPages, EfiRuntimeServicesData,
+                  NumPages, NewFdtBase);
+  if (EFI_ERROR (Status)) {
+    return EFI_BUFFER_TOO_SMALL;
+  }
+
+  CopyMem (
+    (VOID*)(UINTN)*NewFdtBase,
+    (VOID*)(UINTN)OrigFdtBase,
+    FdtSize
+    );
+
+  if (mBoardId == HIKEY960_BOARDID_V1) {
+    offset = fdt_node_offset_by_compatible (
+               (VOID*)(UINTN)*NewFdtBase, -1, HIKEY960_COMPATIBLE_LEDS_V1
+               );
+  } else {
+    offset = fdt_node_offset_by_compatible (
+               (VOID*)(UINTN)*NewFdtBase, -1, HIKEY960_COMPATIBLE_LEDS_V2
+               );
+  }
+  // Ignore it if can't find LED compatible
+  if (offset < 0) {
+    DEBUG ((DEBUG_WARN, "WARN: Failed to find node with compatible (err:%d)\n", err));
+    goto Exit;
+  }
+  err = fdt_setprop_string ((VOID*)(UINTN)*NewFdtBase, offset, "status", "ok");
+  if (err) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Failed to update status property\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+  err = fdt_set_name ((VOID*)(UINTN)*NewFdtBase, offset, "gpio-leds");
+  if (err) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Failed to update compatible name\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (mBoardId == HIKEY960_BOARDID_V1) {
+    offset = fdt_node_offset_by_compatible (
+               (VOID*)(UINTN)*NewFdtBase, -1, HIKEY960_COMPATIBLE_HUB_V1
+               );
+  } else {
+    offset = fdt_node_offset_by_compatible (
+               (VOID*)(UINTN)*NewFdtBase, -1, HIKEY960_COMPATIBLE_HUB_V2
+               );
+  }
+  // Ignore it if can't find LED compatible
+  if (offset < 0) {
+    DEBUG ((DEBUG_WARN, "WARN: Failed to find node with compatible (err:%d)\n", err));
+    goto Exit;
+  }
+  err = fdt_setprop_string ((VOID*)(UINTN)*NewFdtBase, offset, "status", "ok");
+  if (err) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Failed to update status property\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+Exit:
+  fdt_pack ((VOID*)(UINTN)*NewFdtBase);
+  err = fdt_check_header ((VOID*)(UINTN)*NewFdtBase);
+  if (err != 0) {
+    DEBUG ((DEBUG_ERROR, "ERROR: Device Tree header not valid (err:%d)\n", err));
+    gBS->FreePages (*NewFdtBase, NumPages);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
+ABOOTIMG_PROTOCOL mAbootimg = {
+  AbootimgAppendKernelArgs,
+  AbootimgUpdateDtb
+};
+
+EFI_STATUS
+EFIAPI
+VirtualKeyboardRegister (
+  IN VOID
+  )
+{
+  EFI_STATUS           Status;
+
+  Status = gBS->LocateProtocol (
+                  &gEmbeddedGpioProtocolGuid,
+                  NULL,
+                  (VOID **) &mGpio
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+VirtualKeyboardReset (
+  IN VOID
+  )
+{
+  EFI_STATUS           Status;
+
+  if (mGpio == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  // Configure GPIO68 as GPIO function
+  MmioWrite32 (0xe896c108, 0);
+  Status = mGpio->Set (mGpio, DETECT_SW_FASTBOOT, GPIO_MODE_INPUT);
+  return Status;
+}
+
+BOOLEAN
+EFIAPI
+VirtualKeyboardQuery (
+  IN VIRTUAL_KBD_KEY             *VirtualKey
+  )
+{
+  EFI_STATUS           Status;
+  UINTN                Value = 0;
+
+  if ((VirtualKey == NULL) || (mGpio == NULL)) {
+    return FALSE;
+  }
+  if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
+    goto Done;
+  } else {
+    Status = mGpio->Get (mGpio, DETECT_SW_FASTBOOT, &Value);
+    if (EFI_ERROR (Status) || (Value != 0)) {
+      return FALSE;
+    }
+  }
+Done:
+  VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE;
+  VirtualKey->Key.ScanCode = SCAN_NULL;
+  VirtualKey->Key.UnicodeChar = L'f';
+  return TRUE;
+}
+
+EFI_STATUS
+EFIAPI
+VirtualKeyboardClear (
+  IN VIRTUAL_KBD_KEY            *VirtualKey
+  )
+{
+  if (VirtualKey == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
+    MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE);
+    WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4);
+  }
+  return EFI_SUCCESS;
+}
+
+PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = {
+  VirtualKeyboardRegister,
+  VirtualKeyboardReset,
+  VirtualKeyboardQuery,
+  VirtualKeyboardClear
+};
+
+EFI_STATUS
+EFIAPI
+HiKey960EntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS            Status;
+  EFI_EVENT             EndOfDxeEvent;
+
+  Status = InitBoardId (&mBoardId);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  InitPeripherals ();
+
+  //
+  // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group.
+  // The "OnEndOfDxe()" function is declared as the call back function.
+  // It will be called at the end of the DXE phase when an event of the
+  // same group is signalled to inform about the end of the DXE phase.
+  // Install the INSTALL_FDT_PROTOCOL protocol.
+  //
+  Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_CALLBACK,
+                  OnEndOfDxe,
+                  NULL,
+                  &gEfiEndOfDxeEventGroupGuid,
+                  &EndOfDxeEvent
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  // RegisterNonDicoverableMmioDevice
+  Status = RegisterNonDiscoverableMmioDevice (
+             NonDiscoverableDeviceTypeUfs,
+             NonDiscoverableDeviceDmaTypeNonCoherent,
+             NULL,
+             NULL,
+             1,
+             FixedPcdGet32 (PcdDwUfsHcDxeBaseAddress),
+             SIZE_4KB
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Status = RegisterNonDiscoverableMmioDevice (
+             NonDiscoverableDeviceTypeSdhci,
+             NonDiscoverableDeviceDmaTypeNonCoherent,
+             NULL,
+             NULL,
+             1,
+             0xFF37F000, // SD
+             SIZE_4KB
+             );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gAbootimgProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  &mAbootimg
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gPlatformVirtualKeyboardProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  &mVirtualKeyboard
+                  );
+  return Status;
+}
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf b/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf
new file mode 100644
index 0000000..df668a8
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf
@@ -0,0 +1,64 @@
+#
+#  Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKey960Dxe
+  FILE_GUID                      = 6d824b2c-640e-4643-b9f2-9c09e8bff429
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = HiKey960EntryPoint
+
+[Sources.common]
+  HiKey960Dxe.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.dec
+  OpenPlatformPkg/Drivers/Keyboard/VirtualKeyboardDxe/VirtualKeyboardDxe.dec
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  CacheMaintenanceLib
+  DebugLib
+  DxeServicesTableLib
+  FdtLib
+  IoLib
+  NonDiscoverableDeviceRegistrationLib
+  PcdLib
+  PrintLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+  UefiRuntimeServicesTableLib
+
+[Protocols]
+  gAbootimgProtocolGuid
+  gEfiBlockIoProtocolGuid
+  gEfiDevicePathToTextProtocolGuid
+  gEmbeddedGpioProtocolGuid
+  gPlatformVirtualKeyboardProtocolGuid
+
+[Guids]
+  gEfiEndOfDxeEventGroupGuid
+  gEfiFileInfoGuid
+
+[Pcd]
+  gDwUfsHcDxeTokenSpaceGuid.PcdDwUfsHcDxeBaseAddress
+  gHiKey960TokenSpaceGuid.PcdAndroidFastbootNvmDevicePath
+
+[Depex]
+  TRUE
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.c b/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.c
new file mode 100644
index 0000000..c87040d
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.c
@@ -0,0 +1,732 @@
+/** @file
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015-2017, Linaro. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/*
+  Implementation of the Android Fastboot Platform protocol, to be used by the
+  Fastboot UEFI application, for Hisilicon HiKey platform.
+*/
+
+#include <Protocol/AndroidFastbootPlatform.h>
+#include <Protocol/BlockIo.h>
+#include <Protocol/DiskIo.h>
+#include <Protocol/EraseBlock.h>
+#include <Protocol/SimpleTextOut.h>
+
+#include <Protocol/DevicePathToText.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UsbSerialNumberLib.h>
+#include <Library/PrintLib.h>
+#include <Library/TimerLib.h>
+
+#define PARTITION_NAME_MAX_LENGTH        (72/2)
+
+#define SERIAL_NUMBER_LBA                20
+#define RANDOM_MAX                       0x7FFFFFFFFFFFFFFF
+#define RANDOM_MAGIC                     0x9A4DBEAF
+
+#define ADB_REBOOT_ADDRESS               0x32100000
+#define ADB_REBOOT_BOOTLOADER            0x77665500
+
+#define UFS_BLOCK_SIZE                   4096
+
+typedef struct _FASTBOOT_PARTITION_LIST {
+  LIST_ENTRY  Link;
+  CHAR16      PartitionName[PARTITION_NAME_MAX_LENGTH];
+  EFI_LBA     StartingLBA;
+  EFI_LBA     EndingLBA;
+} FASTBOOT_PARTITION_LIST;
+
+STATIC LIST_ENTRY                       mPartitionListHead;
+STATIC EFI_HANDLE                       mFlashHandle;
+STATIC EFI_BLOCK_IO_PROTOCOL           *mFlashBlockIo;
+STATIC EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *mTextOut;
+
+/*
+  Helper to free the partition list
+*/
+STATIC
+VOID
+FreePartitionList (
+  VOID
+  )
+{
+  FASTBOOT_PARTITION_LIST *Entry;
+  FASTBOOT_PARTITION_LIST *NextEntry;
+
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead);
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    NextEntry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &Entry->Link);
+
+    RemoveEntryList (&Entry->Link);
+    FreePool (Entry);
+
+    Entry = NextEntry;
+  }
+}
+
+/*
+  Read the PartitionName fields from the GPT partition entries, putting them
+  into an allocated array that should later be freed.
+*/
+STATIC
+EFI_STATUS
+ReadPartitionEntries (
+  IN  EFI_BLOCK_IO_PROTOCOL *BlockIo,
+  OUT EFI_PARTITION_ENTRY  **PartitionEntries,
+  OUT UINTN                 *PartitionNumbers
+  )
+{
+  UINT32                      MediaId;
+  EFI_PARTITION_TABLE_HEADER *GptHeader;
+  EFI_PARTITION_ENTRY        *Entry;
+  EFI_STATUS                  Status;
+  VOID                       *Buffer;
+  UINTN                       PageCount;
+  UINTN                       BlockSize;
+  UINTN                       Count, EndLBA;
+
+  if ((PartitionEntries == NULL) || (PartitionNumbers == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  MediaId = BlockIo->Media->MediaId;
+  BlockSize = BlockIo->Media->BlockSize;
+
+  //
+  // Read size of Partition entry and number of entries from GPT header
+  //
+
+  PageCount = EFI_SIZE_TO_PAGES (6 * BlockSize);
+  Buffer = AllocatePages (PageCount);
+  if (Buffer == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Status = BlockIo->ReadBlocks (BlockIo, MediaId, 0, PageCount * EFI_PAGE_SIZE, Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  GptHeader = (EFI_PARTITION_TABLE_HEADER *)(Buffer + BlockSize);
+
+  // Check there is a GPT on the media
+  if (GptHeader->Header.Signature != EFI_PTAB_HEADER_ID ||
+      GptHeader->MyLBA != 1) {
+    DEBUG ((DEBUG_ERROR,
+      "Fastboot platform: No GPT on flash. "
+      "Fastboot on Versatile Express does not support MBR.\n"
+      ));
+    return EFI_DEVICE_ERROR;
+  }
+
+  Entry = (EFI_PARTITION_ENTRY *)(Buffer + (2 * BlockSize));
+  EndLBA = GptHeader->FirstUsableLBA - 1;
+  Count = 0;
+  while (1) {
+    if ((Entry->StartingLBA > EndLBA) && (Entry->EndingLBA <= GptHeader->LastUsableLBA)) {
+      Count++;
+      EndLBA = Entry->EndingLBA;
+      Entry++;
+    } else {
+      break;
+    }
+  }
+  if (Count == 0) {
+    return EFI_INVALID_PARAMETER;
+  }
+  if (Count > GptHeader->NumberOfPartitionEntries) {
+    Count = GptHeader->NumberOfPartitionEntries;
+  }
+
+  *PartitionEntries = (EFI_PARTITION_ENTRY *)((UINTN)Buffer + (2 * BlockSize));
+  *PartitionNumbers = Count;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+LoadPtable (
+  VOID
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePathDup;
+  UINTN                               PartitionNumbers = 0;
+  UINTN                               LoopIndex;
+  EFI_PARTITION_ENTRY                *PartitionEntries = NULL;
+  FASTBOOT_PARTITION_LIST            *Entry;
+
+  InitializeListHead (&mPartitionListHead);
+
+  Status = gBS->LocateProtocol (&gEfiSimpleTextOutProtocolGuid, NULL, (VOID **) &mTextOut);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "Fastboot platform: Couldn't open Text Output Protocol: %r\n", Status
+      ));
+    return Status;
+  }
+
+  //
+  // Get EFI_HANDLES for all the partitions on the block devices pointed to by
+  // PcdFastbootFlashDevicePath, also saving their GPT partition labels.
+  // There's no way to find all of a device's children, so we get every handle
+  // in the system supporting EFI_BLOCK_IO_PROTOCOL and then filter out ones
+  // that don't represent partitions on the flash device.
+  //
+  FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
+
+  // Create another device path pointer because LocateDevicePath will modify it.
+  FlashDevicePathDup = FlashDevicePath;
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePathDup, &mFlashHandle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
+
+
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &mFlashBlockIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Fastboot platform: Couldn't open Android NVM device (status: %r)\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+
+  // Read the GPT partition entry array into memory so we can get the partition names
+  Status = ReadPartitionEntries (mFlashBlockIo, &PartitionEntries, &PartitionNumbers);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Warning: Failed to read partitions from Android NVM device (status: %r)\n", Status));
+    // Failing to locate partitions should not prevent to do other Android FastBoot actions
+    return EFI_SUCCESS;
+  }
+  for (LoopIndex = 0; LoopIndex < PartitionNumbers; LoopIndex++) {
+    // Create entry
+    Entry = AllocatePool (sizeof (FASTBOOT_PARTITION_LIST));
+    if (Entry == NULL) {
+      Status = EFI_OUT_OF_RESOURCES;
+      FreePartitionList ();
+      goto Exit;
+    }
+    StrnCpy (
+      Entry->PartitionName,
+      PartitionEntries[LoopIndex].PartitionName,
+      PARTITION_NAME_MAX_LENGTH
+      );
+    Entry->StartingLBA = PartitionEntries[LoopIndex].StartingLBA;
+    Entry->EndingLBA = PartitionEntries[LoopIndex].EndingLBA;
+    InsertTailList (&mPartitionListHead, &Entry->Link);
+  }
+Exit:
+  FreePages (
+    (VOID *)((UINTN)PartitionEntries - (2 * mFlashBlockIo->Media->BlockSize)),
+    EFI_SIZE_TO_PAGES (6 * mFlashBlockIo->Media->BlockSize)
+    );
+  return Status;
+}
+
+/*
+  Initialise: Open the Android NVM device and find the partitions on it. Save them in
+  a list along with the "PartitionName" fields for their GPT entries.
+  We will use these partition names as the key in
+  HiKey960FastbootPlatformFlashPartition.
+*/
+EFI_STATUS
+HiKey960FastbootPlatformInit (
+  VOID
+  )
+{
+  EFI_STATUS               Status;
+
+  Status = LoadPtable ();
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return Status;
+}
+
+VOID
+HiKey960FastbootPlatformUnInit (
+  VOID
+  )
+{
+  FreePartitionList ();
+}
+
+EFI_STATUS
+HiKey960FlashPtable (
+  IN UINTN   Size,
+  IN VOID   *Image
+  )
+{
+  EFI_STATUS               Status;
+  Status = mFlashBlockIo->WriteBlocks (
+                            mFlashBlockIo,
+                            mFlashBlockIo->Media->MediaId,
+                            0,
+                            Size,
+                            Image
+                            );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to write (status:%r)\n", Status));
+    return Status;
+  }
+  FreePartitionList ();
+  Status = LoadPtable ();
+  return Status;
+}
+
+EFI_STATUS
+HiKey960ErasePtable (
+  VOID
+  )
+{
+  EFI_STATUS                  Status;
+#if 0
+  EFI_ERASE_BLOCK_PROTOCOL   *EraseBlockProtocol;
+#endif
+
+#if 0
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiEraseBlockProtocolGuid,
+                  (VOID **) &EraseBlockProtocol,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Fastboot platform: could not open Erase Block IO: %r\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+  Status = EraseBlockProtocol->EraseBlocks (
+                                 EraseBlockProtocol,
+                                 mFlashBlockIo->Media->MediaId,
+                                 0,
+                                 NULL,
+                                 6 * mFlashBlockIo->Media->BlockSize
+                                 );
+#else
+  {
+    VOID         *DataPtr;
+    UINTN         Lba;
+
+    DataPtr = AllocatePages (1);
+    ZeroMem (DataPtr, EFI_PAGE_SIZE);
+    for (Lba = 0; Lba < 6; Lba++) {
+      Status = mFlashBlockIo->WriteBlocks (
+                          mFlashBlockIo,
+                          mFlashBlockIo->Media->MediaId,
+                          Lba,
+                          EFI_PAGE_SIZE,
+                          DataPtr
+                          );
+      if (EFI_ERROR (Status)) {
+        goto Exit;
+      }
+    }
+Exit:
+    FreePages (DataPtr, 1);
+  }
+#endif
+  FreePartitionList ();
+  return Status;
+}
+
+EFI_STATUS
+HiKey960FlashXloader (
+  IN UINTN   Size,
+  IN VOID   *Image
+  )
+{
+  EFI_STATUS                        Status;
+  EFI_DEVICE_PATH_PROTOCOL         *DevicePath;
+  EFI_HANDLE                        Handle;
+  EFI_BLOCK_IO_PROTOCOL            *BlockIo;
+  EFI_DISK_IO_PROTOCOL             *DiskIo;
+
+  DevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdXloaderDevicePath));
+
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &DevicePath, &Handle);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Warning: Couldn't locate xloader device (status: %r)\n", Status));
+    return Status;
+  }
+
+  Status = gBS->OpenProtocol (
+                  Handle,
+                  &gEfiBlockIoProtocolGuid,
+                  (VOID **) &BlockIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Fastboot platform: Couldn't open xloader device (status: %r)\n", Status));
+    return EFI_DEVICE_ERROR;
+  }
+  Status = gBS->OpenProtocol (
+                  Handle,
+                  &gEfiDiskIoProtocolGuid,
+                  (VOID **) &DiskIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = DiskIo->WriteDisk (
+                     DiskIo,
+                     BlockIo->Media->MediaId,
+                     0,
+                     Size,
+                     Image
+                     );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to write (status:%r)\n", Status));
+    return Status;
+  }
+  return Status;
+}
+
+EFI_STATUS
+HiKey960FastbootPlatformFlashPartition (
+  IN CHAR8  *PartitionName,
+  IN UINTN   Size,
+  IN VOID   *Image
+  )
+{
+  EFI_STATUS               Status;
+  UINTN                    PartitionSize;
+  FASTBOOT_PARTITION_LIST *Entry;
+  CHAR16                   PartitionNameUnicode[60];
+  BOOLEAN                  PartitionFound;
+  EFI_DISK_IO_PROTOCOL    *DiskIo;
+  UINTN                    BlockSize;
+
+  // Support the pseudo partition name, such as "ptable".
+  if (AsciiStrCmp (PartitionName, "ptable") == 0) {
+    return HiKey960FlashPtable (Size, Image);
+  } else if (AsciiStrCmp (PartitionName, "xloader") == 0) {
+    return HiKey960FlashXloader (Size, Image);
+  }
+
+  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
+  PartitionFound = FALSE;
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    // Search the partition list for the partition named by PartitionName
+    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+      PartitionFound = TRUE;
+      break;
+    }
+
+   Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
+  }
+  if (!PartitionFound) {
+    return EFI_NOT_FOUND;
+  }
+
+  // Check image will fit on device
+  BlockSize = mFlashBlockIo->Media->BlockSize;
+  PartitionSize = (Entry->EndingLBA - Entry->StartingLBA + 1) * BlockSize;
+  if (PartitionSize < Size) {
+    DEBUG ((DEBUG_ERROR, "Partition not big enough.\n"));
+    DEBUG ((DEBUG_ERROR, "Partition Size:\t%ld\nImage Size:\t%ld\n", PartitionSize, Size));
+
+    return EFI_VOLUME_FULL;
+  }
+
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiDiskIoProtocolGuid,
+                  (VOID **) &DiskIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  Status = DiskIo->WriteDisk (
+                     DiskIo,
+                     mFlashBlockIo->Media->MediaId,
+                     Entry->StartingLBA * BlockSize,
+                     Size,
+                     Image
+                     );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to write %d bytes into 0x%x, Status:%r\n", Size, Entry->StartingLBA * BlockSize, Status));
+    return Status;
+  }
+
+  mFlashBlockIo->FlushBlocks(mFlashBlockIo);
+  MicroSecondDelay (50000);
+
+  return Status;
+}
+
+EFI_STATUS
+HiKey960FastbootPlatformErasePartition (
+  IN CHAR8 *PartitionName
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_ERASE_BLOCK_PROTOCOL   *EraseBlockProtocol;
+  UINTN                       Size;
+  BOOLEAN                     PartitionFound;
+  CHAR16                      PartitionNameUnicode[60];
+  FASTBOOT_PARTITION_LIST    *Entry;
+
+  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
+
+  // Support the pseudo partition name, such as "ptable".
+  if (AsciiStrCmp (PartitionName, "ptable") == 0) {
+    return HiKey960ErasePtable ();
+  }
+
+  PartitionFound = FALSE;
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead);
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    // Search the partition list for the partition named by PartitionName
+    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+      PartitionFound = TRUE;
+      break;
+    }
+    Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &Entry->Link);
+  }
+  if (!PartitionFound) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiEraseBlockProtocolGuid,
+                  (VOID **) &EraseBlockProtocol,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  Size = (Entry->EndingLBA - Entry->StartingLBA + 1) * mFlashBlockIo->Media->BlockSize;
+  Status = EraseBlockProtocol->EraseBlocks (
+                                 EraseBlockProtocol,
+                                 mFlashBlockIo->Media->MediaId,
+                                 Entry->StartingLBA,
+                                 NULL,
+                                 Size
+                                 );
+  return Status;
+}
+
+EFI_STATUS
+HiKey960FastbootPlatformGetVar (
+  IN  CHAR8   *Name,
+  OUT CHAR8   *Value
+  )
+{
+  EFI_STATUS               Status = EFI_SUCCESS;
+  UINT64                   PartitionSize;
+  FASTBOOT_PARTITION_LIST *Entry;
+  CHAR16                   PartitionNameUnicode[60];
+  BOOLEAN                  PartitionFound;
+  CHAR16                   UnicodeSN[SERIAL_NUMBER_SIZE];
+
+  if (!AsciiStrCmp (Name, "max-download-size")) {
+    AsciiStrCpy (Value, FixedPcdGetPtr (PcdArmFastbootFlashLimit));
+  } else if (!AsciiStrCmp (Name, "product")) {
+    AsciiStrCpy (Value, FixedPcdGetPtr (PcdFirmwareVendor));
+  } else if (!AsciiStrCmp (Name, "serialno")) {
+    Status = LoadSNFromBlock (mFlashHandle, SERIAL_NUMBER_LBA, UnicodeSN);
+    UnicodeStrToAsciiStr (UnicodeSN, Value);
+  } else if ( !AsciiStrnCmp (Name, "partition-size", 14)) {
+    AsciiStrToUnicodeStr ((Name + 15), PartitionNameUnicode);
+    PartitionFound = FALSE;
+    Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
+    while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+      // Search the partition list for the partition named by PartitionName
+      if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+        PartitionFound = TRUE;
+        break;
+      }
+
+     Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
+    }
+    if (!PartitionFound) {
+      *Value = '\0';
+      return EFI_NOT_FOUND;
+    }
+
+    PartitionSize = (Entry->EndingLBA - Entry->StartingLBA + 1) * mFlashBlockIo->Media->BlockSize;
+    DEBUG ((DEBUG_ERROR, "Fastboot platform: check for partition-size:%a 0X%llx\n", Name, PartitionSize ));
+    AsciiSPrint (Value, 12, "0x%llx", PartitionSize);
+  } else if ( !AsciiStrnCmp (Name, "partition-type", 14)) {
+      DEBUG ((DEBUG_ERROR, "Fastboot platform: check for partition-type:%a\n", (Name + 15) ));
+    if ( !AsciiStrnCmp  ( (Name + 15) , "system", 6) || !AsciiStrnCmp  ( (Name + 15) , "userdata", 8)
+            || !AsciiStrnCmp  ( (Name + 15) , "cache", 5)) {
+      AsciiStrCpy (Value, "ext4");
+    } else {
+      AsciiStrCpy (Value, "raw");
+    }
+  } else if ( !AsciiStrCmp (Name, "erase-block-size")) {
+    AsciiSPrint (Value, 12, "0x%llx", UFS_BLOCK_SIZE);
+  } else if ( !AsciiStrCmp (Name, "logical-block-size")) {
+    AsciiSPrint (Value, 12, "0x%llx", UFS_BLOCK_SIZE);
+  } else {
+    *Value = '\0';
+  }
+  return Status;
+}
+
+EFI_STATUS
+HiKey960FastbootPlatformOemCommand (
+  IN  CHAR8   *Command
+  )
+{
+  EFI_STATUS   Status;
+  CHAR16       UnicodeSN[SERIAL_NUMBER_SIZE];
+
+  if (AsciiStrCmp (Command, "Demonstrate") == 0) {
+    DEBUG ((DEBUG_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.\n"));
+    return EFI_SUCCESS;
+  } else if (AsciiStrCmp (Command, "serialno") == 0) {
+    Status = GenerateUsbSN (UnicodeSN);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Failed to generate USB Serial Number.\n"));
+      return Status;
+    }
+    Status = StoreSNToBlock (mFlashHandle, SERIAL_NUMBER_LBA, UnicodeSN);
+    return Status;
+  } else if (AsciiStrCmp (Command, "reboot-bootloader") == 0) {
+    MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_BOOTLOADER);
+    WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4);
+    return EFI_SUCCESS;
+  } else {
+    DEBUG ((DEBUG_ERROR,
+      "HiKey960: Unrecognised Fastboot OEM command: %a\n",
+      Command
+      ));
+    return EFI_NOT_FOUND;
+  }
+}
+
+EFI_STATUS
+HiKey960FastbootPlatformFlashPartitionEx (
+  IN CHAR8  *PartitionName,
+  IN UINTN   Offset,
+  IN UINTN   Size,
+  IN VOID   *Image
+  )
+{
+  EFI_STATUS               Status;
+  UINTN                    PartitionSize;
+  FASTBOOT_PARTITION_LIST *Entry;
+  CHAR16                   PartitionNameUnicode[60];
+  BOOLEAN                  PartitionFound;
+  UINTN                    BlockSize;
+  EFI_DISK_IO_PROTOCOL    *DiskIo;
+
+  AsciiStrToUnicodeStr (PartitionName, PartitionNameUnicode);
+  PartitionFound = FALSE;
+  Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
+  while (!IsNull (&mPartitionListHead, &Entry->Link)) {
+    // Search the partition list for the partition named by PartitionName
+    if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
+      PartitionFound = TRUE;
+      break;
+    }
+
+   Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
+  }
+  if (!PartitionFound) {
+    return EFI_NOT_FOUND;
+  }
+
+  // Check image will fit on device
+  PartitionSize = (Entry->EndingLBA - Entry->StartingLBA + 1) * mFlashBlockIo->Media->BlockSize;
+  if (PartitionSize < Size) {
+    DEBUG ((DEBUG_ERROR, "Partition not big enough.\n"));
+    DEBUG ((DEBUG_ERROR, "Partition Size:\t%ld\nImage Size:\t%ld\n", PartitionSize, Size));
+
+    return EFI_VOLUME_FULL;
+  }
+
+  BlockSize = mFlashBlockIo->Media->BlockSize;
+
+  Status = gBS->OpenProtocol (
+                  mFlashHandle,
+                  &gEfiDiskIoProtocolGuid,
+                  (VOID **) &DiskIo,
+                  gImageHandle,
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Status = DiskIo->WriteDisk (
+                     DiskIo,
+                     mFlashBlockIo->Media->MediaId,
+                     Entry->StartingLBA * BlockSize + Offset,
+                     Size,
+                     Image
+                     );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to write %d bytes into 0x%x, Status:%r\n", Size, Entry->StartingLBA * BlockSize + Offset, Status));
+    return Status;
+  }
+  return Status;
+}
+
+FASTBOOT_PLATFORM_PROTOCOL mPlatformProtocol = {
+  HiKey960FastbootPlatformInit,
+  HiKey960FastbootPlatformUnInit,
+  HiKey960FastbootPlatformFlashPartition,
+  HiKey960FastbootPlatformErasePartition,
+  HiKey960FastbootPlatformGetVar,
+  HiKey960FastbootPlatformOemCommand,
+  HiKey960FastbootPlatformFlashPartitionEx
+};
+
+EFI_STATUS
+EFIAPI
+HiKey960FastbootPlatformEntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  return gBS->InstallProtocolInterface (
+                &ImageHandle,
+                &gAndroidFastbootPlatformProtocolGuid,
+                EFI_NATIVE_INTERFACE,
+                &mPlatformProtocol
+                );
+}
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.inf b/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.inf
new file mode 100644
index 0000000..180b624
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.inf
@@ -0,0 +1,62 @@
+#/** @file
+#
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2015-2017, Linaro. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKey960FastbootDxe
+  FILE_GUID                      = 80f046c6-d5ba-4916-a656-2e2b28d32304
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = HiKey960FastbootPlatformEntryPoint
+
+[Sources.common]
+  HiKey960FastbootDxe.c
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  CacheMaintenanceLib
+  DebugLib
+  DevicePathLib
+  IoLib
+  MemoryAllocationLib
+  PcdLib
+  UefiBootServicesTableLib
+  UefiRuntimeServicesTableLib
+  UefiDriverEntryPoint
+  UsbSerialNumberLib
+  TimerLib
+
+[Protocols]
+  gAndroidFastbootPlatformProtocolGuid
+  gEfiBlockIoProtocolGuid
+  gEfiDevicePathToTextProtocolGuid
+  gEfiDiskIoProtocolGuid
+  gEfiEraseBlockProtocolGuid
+  gEfiSimpleTextOutProtocolGuid
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dec
+
+[Pcd]
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor
+  gHiKey960TokenSpaceGuid.PcdAndroidFastbootNvmDevicePath
+  gHiKey960TokenSpaceGuid.PcdArmFastbootFlashLimit
+  gHiKey960TokenSpaceGuid.PcdXloaderDevicePath
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c b/Platforms/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c
new file mode 100644
index 0000000..7c61ff7
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c
@@ -0,0 +1,77 @@
+/** @file
+*
+*  Copyright (c) 2017, Linaro. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/EmbeddedGpio.h>
+
+GPIO_CONTROLLER gGpioDevice[]= {
+  { 0xe8a0b000, 0, 8 },    // GPIO0
+  { 0xe8a0c000, 8, 8 },    // GPIO1
+  { 0xe8a0d000, 16, 8 },   // GPIO2
+  { 0xe8a0e000, 24, 8 },   // GPIO3
+  { 0xe8a0f000, 32, 8 },   // GPIO4
+  { 0xe8a10000, 40, 8 },   // GPIO5
+  { 0xe8a11000, 48, 8 },   // GPIO6
+  { 0xe8a12000, 56, 8 },   // GPIO7
+  { 0xe8a13000, 64, 8 },   // GPIO8
+  { 0xe8a14000, 72, 8 },   // GPIO9
+  { 0xe8a15000, 80, 8 },   // GPIO10
+  { 0xe8a16000, 88, 8 },   // GPIO11
+  { 0xe8a17000, 96, 8 },   // GPIO12
+  { 0xe8a18000, 104, 8 },  // GPIO13
+  { 0xe8a19000, 112, 8 },  // GPIO14
+  { 0xe8a1a000, 120, 8 },  // GPIO15
+  { 0xe8a1b000, 128, 8 },  // GPIO16
+  { 0xe8a1c000, 136, 8 },  // GPIO17
+  { 0xff3b4000, 144, 8 },  // GPIO18
+  { 0xff3b5000, 152, 8 },  // GPIO19
+  { 0xe8a1f000, 160, 8 },  // GPIO20
+  { 0xe8a20000, 168, 8 },  // GPIO21
+  { 0xfff0b000, 176, 8 },  // GPIO22
+  { 0xfff0c000, 184, 8 },  // GPIO23
+  { 0xfff0d000, 192, 8 },  // GPIO24
+  { 0xfff0e000, 200, 8 },  // GPIO25
+  { 0xfff0f000, 208, 8 },  // GPIO26
+  { 0xfff10000, 216, 8 },  // GPIO27
+  { 0xfff1d000, 224, 8 },  // GPIO28
+};
+
+PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = {
+  232, 29, gGpioDevice
+};
+
+EFI_STATUS
+EFIAPI
+HiKey960GpioEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
+
+  // Install the Embedded Platform GPIO Protocol onto a new handle
+  Handle = NULL;
+  Status = gBS->InstallMultipleProtocolInterfaces(
+                  &Handle,
+                  &gPlatformGpioProtocolGuid, &gPlatformGpioDevice,
+                  NULL
+                 );
+  if (EFI_ERROR(Status)) {
+    Status = EFI_OUT_OF_RESOURCES;
+  }
+
+  return Status;
+}
diff --git a/Chips/TexasInstruments/Omap35xx/Gpio/Gpio.inf b/Platforms/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf
index 62073ff..9160afe 100644
--- a/Chips/TexasInstruments/Omap35xx/Gpio/Gpio.inf
+++ b/Platforms/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf
@@ -1,6 +1,6 @@
-#/** @file
 #
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#  Copyright (c) 2017, Linaro. All rights reserved.
+#
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
 #  which accompanies this distribution.  The full text of the license may be found at
@@ -9,37 +9,29 @@
 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
-#**/
 
 [Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = Gpio
-  FILE_GUID                      = E7D9CAE1-6930-46E3-BDF9-0027446E7DF2
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKey960Gpio
+  FILE_GUID                      = 6aa12592-7e36-4aec-acf8-2ac2fd13815c
   MODULE_TYPE                    = DXE_DRIVER
   VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = GpioInitialize
-
+  ENTRY_POINT                    = HiKey960GpioEntryPoint
 
 [Sources.common]
-  Gpio.c
+  HiKey960GpioDxe.c
 
 [Packages]
-  MdePkg/MdePkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dec
 
 [LibraryClasses]
-  IoLib
+  DebugLib
   UefiDriverEntryPoint
-  OmapLib
-
-[Guids]
 
 [Protocols]
-  gEmbeddedGpioProtocolGuid
-
-[Pcd]
+  gPlatformGpioProtocolGuid
 
-[depex]
+[Depex]
   TRUE
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.c b/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.c
new file mode 100644
index 0000000..3e52270
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.c
@@ -0,0 +1,125 @@
+/** @file
+*
+*  Copyright (c) 2017, Linaro. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UsbSerialNumberLib.h>
+
+#include <Protocol/EmbeddedGpio.h>
+#include <Protocol/PlatformDwMmc.h>
+
+#include <Hi3660.h>
+
+#define DETECT_SD_CARD           203     // GPIO 25_3
+
+DW_MMC_HC_SLOT_CAP
+DwMmcCapability[1] = {
+  {
+    .HighSpeed   = 1,
+    .BusWidth    = 4,
+    .SlotType    = RemovableSlot,
+    .CardType    = SdCardType,
+    .Voltage30   = 1,
+    .BaseClkFreq = 3200
+  }
+};
+
+EFI_STATUS
+EFIAPI
+HiKey960GetCapability (
+  IN     EFI_HANDLE           Controller,
+  IN     UINT8                Slot,
+     OUT DW_MMC_HC_SLOT_CAP   *Capability
+  )
+{
+  if (Capability == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+  if (DwMmcCapability[0].Controller == 0) {
+    DwMmcCapability[0].Controller = Controller;
+    CopyMem (Capability, &DwMmcCapability[0], sizeof (DW_MMC_HC_SLOT_CAP));
+  } else if (DwMmcCapability[0].Controller == Controller) {
+    CopyMem (Capability, &DwMmcCapability[0], sizeof (DW_MMC_HC_SLOT_CAP));
+  } else {
+    return EFI_INVALID_PARAMETER;
+  }
+  return EFI_SUCCESS;
+}
+
+BOOLEAN
+EFIAPI
+HiKey960CardDetect (
+  IN UINT8                    Slot
+  )
+{
+  EFI_STATUS            Status;
+  EMBEDDED_GPIO         *Gpio;
+  UINTN                 Value;
+
+  if (Slot == 0) {
+    Status = gBS->LocateProtocol (&gEmbeddedGpioProtocolGuid, NULL, (VOID **)&Gpio);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Failed to get GPIO protocol: %r\n", Status));
+      goto Exit;
+    }
+    Status = Gpio->Set (Gpio, DETECT_SD_CARD, GPIO_MODE_INPUT);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Failed to sed GPIO as input mode: %r\n", Status));
+      goto Exit;
+    }
+    Status = Gpio->Get (Gpio, DETECT_SD_CARD, &Value);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Failed to get GPIO value: %r\n", Status));
+      goto Exit;
+    }
+    if (Value == 0) {
+      return TRUE;
+    }
+  }
+Exit:
+  return FALSE;
+}
+
+PLATFORM_DW_MMC_PROTOCOL mDwMmcDevice = {
+  HiKey960GetCapability,
+  HiKey960CardDetect
+};
+
+EFI_STATUS
+EFIAPI
+HiKey960MmcEntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS        Status;
+
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gPlatformDwMmcProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  &mDwMmcDevice
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  return Status;
+}
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.inf b/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.inf
new file mode 100644
index 0000000..2d843f9
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.inf
@@ -0,0 +1,45 @@
+#/** @file
+#
+#  Copyright (c) 2017, Linaro. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKey960MmcDxe
+  FILE_GUID                      = e10d1dea-2f00-4eea-ac5d-9d6cfa7831a0
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = HiKey960MmcEntryPoint
+
+[Sources.common]
+  HiKey960MmcDxe.c
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[Protocols]
+  gEfiDriverBindingProtocolGuid
+  gEmbeddedGpioProtocolGuid
+  gPlatformDwMmcProtocolGuid
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.dec
+
+[Depex]
+  TRUE
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/HiKey960UsbDxe.c b/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/HiKey960UsbDxe.c
new file mode 100644
index 0000000..8a771b6
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/HiKey960UsbDxe.c
@@ -0,0 +1,363 @@
+/** @file
+*
+*  Copyright (c) 2017, Linaro. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UsbSerialNumberLib.h>
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/DwUsb.h>
+
+#include <Hi3660.h>
+
+#define USB_EYE_PARAM                  0x01c466e3
+#define USB_PHY_TX_VBOOST_LVL          5
+
+#define DWC3_PHY_RX_OVRD_IN_HI         0x1006
+#define DWC3_PHY_RX_SCOPE_VDCC         0x1026
+
+#define RX_SCOPE_LFPS_EN               (1 << 0)
+
+#define TX_VBOOST_LVL_MASK             7
+#define TX_VBOOST_LVL(x)               ((x) & TX_VBOOST_LVL_MASK)
+
+#define SERIAL_NUMBER_LBA              20
+
+STATIC EFI_HANDLE mFlashHandle;
+
+UINTN
+HiKey960GetUsbMode (
+  IN VOID
+  )
+{
+  return USB_DEVICE_MODE;
+}
+
+VOID
+HiKey960UsbPhyCrWaitAck (
+  VOID
+  )
+{
+  INT32                Timeout = 1000;
+  UINT32               Data;
+
+  while (TRUE) {
+    Data = MmioRead32 (USB3OTG_PHY_CR_STS);
+    if ((Data & USB3OTG_PHY_CR_ACK) == USB3OTG_PHY_CR_ACK) {
+      return;
+    }
+    MicroSecondDelay (50);
+    if (Timeout-- <= 0) {
+      DEBUG ((DEBUG_ERROR, "Wait PHY_CR_ACK timeout!\n"));
+      return;
+    }
+  }
+}
+
+VOID
+HiKey960UsbPhyCrSetAddr (
+  IN UINT32            Addr
+  )
+{
+  // set addr
+  MmioWrite32 (
+    USB3OTG_PHY_CR_CTRL,
+    USB3OTG_PHY_CR_DATA_IN (Addr)
+    );
+  MicroSecondDelay (100);
+  // cap addr
+  MmioOr32 (USB3OTG_PHY_CR_CTRL, USB3OTG_PHY_CR_CAP_ADDR);
+  HiKey960UsbPhyCrWaitAck ();
+  MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0);
+}
+
+UINT16
+HiKey960UsbPhyCrRead (
+  IN UINT32            Addr
+  )
+{
+  INT32                Timeout = 1000;
+  UINT32               Data;
+
+  HiKey960UsbPhyCrSetAddr (Addr);
+  MmioWrite32 (USB3OTG_PHY_CR_CTRL, USB3OTG_PHY_CR_READ);
+  MicroSecondDelay (100);
+
+  while (TRUE) {
+    Data = MmioRead32 (USB3OTG_PHY_CR_STS);
+    if ((Data & USB3OTG_PHY_CR_ACK) == USB3OTG_PHY_CR_ACK) {
+      DEBUG ((
+        DEBUG_INFO,
+        "Addr 0x%x, Data Out:0x%x\n",
+        Addr,
+        USB3OTG_PHY_CR_DATA_OUT(Data)
+        ));
+      break;
+    }
+    MicroSecondDelay (50);
+    if (Timeout-- <= 0) {
+      DEBUG ((DEBUG_ERROR, "Wait PHY_CR_ACK timeout!\n"));
+      break;
+    }
+  }
+  MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0);
+  return (UINT16)USB3OTG_PHY_CR_DATA_OUT(Data);
+}
+
+VOID
+HiKey960UsbPhyCrWrite (
+  IN UINT32            Addr,
+  IN UINT32            Value
+  )
+{
+  UINT32               Data;
+
+  HiKey960UsbPhyCrSetAddr (Addr);
+  Data = USB3OTG_PHY_CR_DATA_IN(Value);
+  MmioWrite32 (USB3OTG_PHY_CR_CTRL, Data);
+
+  Data = MmioRead32 (USB3OTG_PHY_CR_CTRL);
+  Data |= USB3OTG_PHY_CR_CAP_DATA;
+  MmioWrite32 (USB3OTG_PHY_CR_CTRL, Data);
+  HiKey960UsbPhyCrWaitAck ();
+
+  MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0);
+  MmioWrite32 (USB3OTG_PHY_CR_CTRL, USB3OTG_PHY_CR_WRITE);
+  HiKey960UsbPhyCrWaitAck ();
+}
+
+VOID
+HiKey960UsbSetEyeDiagramParam (
+  VOID
+  )
+{
+  UINT32               Data;
+
+  /* set eye diagram for usb 2.0 */
+  MmioWrite32 (USB3OTG_CTRL4, USB_EYE_PARAM);
+  /* set eye diagram for usb 3.0 */
+  HiKey960UsbPhyCrRead (DWC3_PHY_RX_OVRD_IN_HI);
+  HiKey960UsbPhyCrWrite (DWC3_PHY_RX_OVRD_IN_HI, BIT11 | BIT9 | BIT8 |BIT7);
+  HiKey960UsbPhyCrRead (DWC3_PHY_RX_OVRD_IN_HI);
+
+  /* enable RX_SCOPE_LFPS_EN for usb 3.0 */
+  Data = HiKey960UsbPhyCrRead (DWC3_PHY_RX_SCOPE_VDCC);
+  Data |= RX_SCOPE_LFPS_EN;
+  HiKey960UsbPhyCrWrite (DWC3_PHY_RX_SCOPE_VDCC, Data);
+  HiKey960UsbPhyCrRead (DWC3_PHY_RX_SCOPE_VDCC);
+
+  Data = MmioRead32 (USB3OTG_CTRL6);
+  Data &= ~TX_VBOOST_LVL_MASK;
+  Data = TX_VBOOST_LVL (USB_PHY_TX_VBOOST_LVL);
+  MmioWrite32 (USB3OTG_CTRL6, Data);
+  DEBUG ((
+    DEBUG_INFO,
+    "set ss phy tx vboost lvl 0x%x\n",
+    MmioRead32 (USB3OTG_CTRL6)
+    ));
+}
+
+STATIC
+VOID
+HiKey960UsbReset (
+  VOID
+  )
+{
+  MmioWrite32 (CRG_PERRSTEN4, PERRSTEN4_USB3OTG);
+  MmioWrite32 (CRG_PERRSTEN4, PERRSTEN4_USB3OTGPHY_POR);
+  MmioWrite32 (
+    CRG_PERRSTEN4,
+    PERRSTEN4_USB3OTG_MUX | PERRSTEN4_USB3OTG_AHBIF | PERRSTEN4_USB3OTG_32K
+    );
+  MmioWrite32 (
+    CRG_PERDIS4,
+    PEREN4_GT_ACLK_USB3OTG | PEREN4_GT_CLK_USB3OTG_REF
+    );
+
+  MmioAnd32 (PCTRL_CTRL24, ~PCTRL_CTRL24_USB3PHY_3MUX1_SEL);
+  // disable
+  MmioWrite32 (PCTRL_CTRL3, (PCTRL_CTRL3_USB_TXCO_EN << 16) | 0);
+  MicroSecondDelay (10000);
+}
+
+STATIC
+VOID
+HiKey960UsbRelease (
+  VOID
+  )
+{
+  /* enable USB REFCLK ISO */
+  MmioWrite32 (CRG_ISODIS, PERISOEN_USB_REFCLK_ISO_EN);
+  /* enable USB_TXCO_EN */
+  MmioWrite32 (PCTRL_CTRL3, (PCTRL_CTRL3_USB_TXCO_EN << 16) | PCTRL_CTRL3_USB_TXCO_EN);
+
+  MmioAnd32 (PCTRL_CTRL24, ~PCTRL_CTRL24_USB3PHY_3MUX1_SEL);
+
+  MmioWrite32 (
+    CRG_PEREN4,
+    PEREN4_GT_ACLK_USB3OTG | PEREN4_GT_CLK_USB3OTG_REF
+    );
+  MmioWrite32 (
+    CRG_PERRSTDIS4,
+    PERRSTEN4_USB3OTG_MUX | PERRSTEN4_USB3OTG_AHBIF | PERRSTEN4_USB3OTG_32K
+    );
+
+  MmioWrite32 (CRG_PERRSTEN4, PERRSTEN4_USB3OTG | PERRSTEN4_USB3OTGPHY_POR);
+
+  /* enable PHY REF CLK */
+  MmioOr32 (USB3OTG_CTRL0, USB3OTG_CTRL0_SC_USB3PHY_ABB_GT_EN);
+
+  MmioOr32 (USB3OTG_CTRL7, USB3OTG_CTRL7_REF_SSP_EN);
+
+  /* exit from IDDQ mode */
+  MmioAnd32 (
+    USB3OTG_CTRL2,
+    ~(USB3OTG_CTRL2_TEST_POWERDOWN_SSP | USB3OTG_CTRL2_TEST_POWERDOWN_HSP)
+    );
+  MicroSecondDelay (100000);
+
+  MmioWrite32 (CRG_PERRSTDIS4, PERRSTEN4_USB3OTGPHY_POR);
+  MmioWrite32 (CRG_PERRSTDIS4, PERRSTEN4_USB3OTG);
+  MicroSecondDelay (10000);
+  MmioOr32 (USB3OTG_CTRL3, USB3OTG_CTRL3_VBUSVLDEXT | USB3OTG_CTRL3_VBUSVLDEXTSEL);
+  MicroSecondDelay (100000);
+
+  HiKey960UsbSetEyeDiagramParam ();
+}
+
+EFI_STATUS
+HiKey960UsbPhyInit (
+  IN UINT8        Mode
+  )
+{
+  HiKey960UsbReset ();
+  MicroSecondDelay (10000);
+  HiKey960UsbRelease ();
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+HiKey960UsbGetLang (
+  OUT CHAR16            *Lang,
+  OUT UINT8             *Length
+  )
+{
+  if ((Lang == NULL) || (Length == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Lang[0] = 0x409;
+  *Length = sizeof (CHAR16);
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+HiKey960UsbGetManuFacturer (
+  OUT CHAR16            *ManuFacturer,
+  OUT UINT8             *Length
+  )
+{
+  UINTN                  VariableSize;
+  CHAR16                 DataUnicode[MANU_FACTURER_STRING_LENGTH];
+
+  if ((ManuFacturer == NULL) || (Length == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  VariableSize = MANU_FACTURER_STRING_LENGTH * sizeof (CHAR16);
+  ZeroMem (DataUnicode, MANU_FACTURER_STRING_LENGTH * sizeof(CHAR16));
+  StrCpy (DataUnicode, L"96Boards");
+  CopyMem (ManuFacturer, DataUnicode, VariableSize);
+  *Length = VariableSize;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+HiKey960UsbGetProduct (
+  OUT CHAR16            *Product,
+  OUT UINT8             *Length
+  )
+{
+  UINTN                  VariableSize;
+  CHAR16                 DataUnicode[PRODUCT_STRING_LENGTH];
+
+  if ((Product == NULL) || (Length == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  VariableSize = PRODUCT_STRING_LENGTH * sizeof (CHAR16);
+  ZeroMem (DataUnicode, PRODUCT_STRING_LENGTH * sizeof(CHAR16));
+  StrCpy (DataUnicode, L"HiKey960");
+  CopyMem (Product, DataUnicode, VariableSize);
+  *Length = VariableSize;
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+HiKey960UsbGetSerialNo (
+  OUT CHAR16            *SerialNo,
+  OUT UINT8             *Length
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_DEVICE_PATH_PROTOCOL           *FlashDevicePath;
+
+  if (mFlashHandle == 0) {
+    FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
+    Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePath, &mFlashHandle);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
+      // Failing to locate partitions should not prevent to do other Android FastBoot actions
+      return EFI_SUCCESS;
+    }
+  }
+
+  if ((SerialNo == NULL) || (Length == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Status = LoadSNFromBlock (mFlashHandle, SERIAL_NUMBER_LBA, SerialNo);
+  *Length = StrSize (SerialNo);
+  return Status;
+}
+
+DW_USB_PROTOCOL mDwUsbDevice = {
+  HiKey960UsbGetLang,
+  HiKey960UsbGetManuFacturer,
+  HiKey960UsbGetProduct,
+  HiKey960UsbGetSerialNo,
+  HiKey960UsbPhyInit
+};
+
+EFI_STATUS
+EFIAPI
+HiKey960UsbEntryPoint (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  return gBS->InstallProtocolInterface (
+                &ImageHandle,
+                &gDwUsbProtocolGuid,
+                EFI_NATIVE_INTERFACE,
+                &mDwUsbDevice
+                );
+}
diff --git a/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/HiKey960UsbDxe.inf b/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/HiKey960UsbDxe.inf
new file mode 100644
index 0000000..8f42b75
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/HiKey960UsbDxe.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+#  Copyright (c) 2015-2017, Linaro. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = HiKey960UsbDxe
+  FILE_GUID                      = 9998be97-6fb6-40f6-a98d-d797dc7b9d32
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = HiKey960UsbEntryPoint
+
+[Sources.common]
+  HiKey960UsbDxe.c
+
+[LibraryClasses]
+  DebugLib
+  IoLib
+  TimerLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UsbSerialNumberLib
+
+[Protocols]
+  gDwUsbProtocolGuid
+  gEfiBlockIoProtocolGuid
+  gEfiDriverBindingProtocolGuid
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  OpenPlatformPkg/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.dec
+  OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dec
+
+[Pcd]
+  gHiKey960TokenSpaceGuid.PcdAndroidFastbootNvmDevicePath
+
+[Depex]
+  TRUE
diff --git a/Platforms/Hisilicon/HiKey960/Include/ArmPlatform.h b/Platforms/Hisilicon/HiKey960/Include/ArmPlatform.h
new file mode 100644
index 0000000..e7772f7
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Include/ArmPlatform.h
@@ -0,0 +1,26 @@
+/** @file
+*
+*  Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+//
+// We don't care about this value, but the PL031 driver depends on the macro
+// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet()
+// function, which just returns EFI_UNSUPPORTED.
+//
+//
+#define SYS_CFG_RTC                             0
+
+#endif /* __PLATFORM_H__ */
diff --git a/Platforms/Hisilicon/HiKey960/Include/Guid/HiKey960Variable.h b/Platforms/Hisilicon/HiKey960/Include/Guid/HiKey960Variable.h
new file mode 100644
index 0000000..b9909c2
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Include/Guid/HiKey960Variable.h
@@ -0,0 +1,24 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015-2016, Linaro. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __HIKEY960_VARIABLE_H__
+#define __HIKEY960_VARIABLE_H__
+
+#define HIKEY960_VARIABLE_GUID \
+  { 0x29727c8d, 0x3531, 0x7a41, { 0x81, 0x9c, 0x7e, 0x50, 0x4e, 0xdd, 0x24, 0x3f } }
+
+extern EFI_GUID gHiKey960VariableGuid;
+
+#endif /* __HIKEY960_VARIABLE_H__ */
diff --git a/Platforms/Hisilicon/HiKey960/Include/Hi3660.h b/Platforms/Hisilicon/HiKey960/Include/Hi3660.h
new file mode 100644
index 0000000..939f7f0
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Include/Hi3660.h
@@ -0,0 +1,145 @@
+/** @file
+*
+*  Copyright (c) 2016-2017, Linaro Ltd. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __HI3660_H__
+#define __HI3660_H__
+
+#define HKADC_SSI_REG_BASE                      0xE82B8000
+
+#define PCTRL_REG_BASE                          0xE8A09000
+
+#define PCTRL_CTRL3                             (PCTRL_REG_BASE + 0x010)
+#define PCTRL_CTRL24                            (PCTRL_REG_BASE + 0x064)
+
+#define PCTRL_CTRL3_USB_TXCO_EN                 (1 << 1)
+#define PCTRL_CTRL24_USB3PHY_3MUX1_SEL          (1 << 25)
+
+#define SCTRL_REG_BASE                          0xFFF0A000
+
+#define SCTRL_SCFPLLCTRL0                       (SCTRL_REG_BASE + 0x120)
+#define SCTRL_SCFPLLCTRL0_FPLL0_EN              (1 << 0)
+
+#define USB3OTG_BC_REG_BASE                     0xFF200000
+
+#define USB3OTG_CTRL0                           (USB3OTG_BC_REG_BASE + 0x000)
+#define USB3OTG_CTRL2                           (USB3OTG_BC_REG_BASE + 0x008)
+#define USB3OTG_CTRL3                           (USB3OTG_BC_REG_BASE + 0x00C)
+#define USB3OTG_CTRL4                           (USB3OTG_BC_REG_BASE + 0x010)
+#define USB3OTG_CTRL6                           (USB3OTG_BC_REG_BASE + 0x018)
+#define USB3OTG_CTRL7                           (USB3OTG_BC_REG_BASE + 0x01C)
+#define USB3OTG_PHY_CR_STS                      (USB3OTG_BC_REG_BASE + 0x050)
+#define USB3OTG_PHY_CR_CTRL                     (USB3OTG_BC_REG_BASE + 0x054)
+
+#define USB3OTG_CTRL0_SC_USB3PHY_ABB_GT_EN      (1 << 15)
+#define USB3OTG_CTRL2_TEST_POWERDOWN_SSP        (1 << 1)
+#define USB3OTG_CTRL2_TEST_POWERDOWN_HSP        (1 << 0)
+#define USB3OTG_CTRL3_VBUSVLDEXT                (1 << 6)
+#define USB3OTG_CTRL3_VBUSVLDEXTSEL             (1 << 5)
+#define USB3OTG_CTRL7_REF_SSP_EN                (1 << 16)
+#define USB3OTG_PHY_CR_DATA_OUT(x)              (((x) & 0xFFFF) << 1)
+#define USB3OTG_PHY_CR_ACK                      (1 << 0)
+#define USB3OTG_PHY_CR_DATA_IN(x)               (((x) & 0xFFFF) << 4)
+#define USB3OTG_PHY_CR_WRITE                    (1 << 3)
+#define USB3OTG_PHY_CR_READ                     (1 << 2)
+#define USB3OTG_PHY_CR_CAP_DATA                 (1 << 1)
+#define USB3OTG_PHY_CR_CAP_ADDR                 (1 << 0)
+
+#define PMU_REG_BASE                            0xFFF34000
+#define PMIC_HARDWARE_CTRL0                     (PMU_REG_BASE + (0x0C5 << 2))
+#define PMIC_OSC32K_ONOFF_CTRL                  (PMU_REG_BASE + (0x0CC << 2))
+
+#define PMIC_HARDWARE_CTRL0_WIFI_CLK            (1 << 5)
+#define PMIC_OSC32K_ONOFF_CTRL_EN_32K           (1 << 1)
+
+
+#define CRG_REG_BASE                            0xFFF35000
+
+#define CRG_PEREN2                              (CRG_REG_BASE + 0x020)
+#define CRG_PERDIS2                             (CRG_REG_BASE + 0x024)
+#define CRG_PERCLKEN2                           (CRG_REG_BASE + 0x028)
+#define CRG_PERSTAT2                            (CRG_REG_BASE + 0x02C)
+#define CRG_PEREN4                              (CRG_REG_BASE + 0x040)
+#define CRG_PERDIS4                             (CRG_REG_BASE + 0x044)
+#define CRG_PERCLKEN4                           (CRG_REG_BASE + 0x048)
+#define CRG_PERSTAT4                            (CRG_REG_BASE + 0x04C)
+#define CRG_PERRSTEN2                           (CRG_REG_BASE + 0x078)
+#define CRG_PERRSTDIS2                          (CRG_REG_BASE + 0x07C)
+#define CRG_PERRSTSTAT2                         (CRG_REG_BASE + 0x080)
+#define CRG_PERRSTEN3                           (CRG_REG_BASE + 0x084)
+#define CRG_PERRSTDIS3                          (CRG_REG_BASE + 0x088)
+#define CRG_PERRSTSTAT3                         (CRG_REG_BASE + 0x08C)
+#define CRG_PERRSTEN4                           (CRG_REG_BASE + 0x090)
+#define CRG_PERRSTDIS4                          (CRG_REG_BASE + 0x094)
+#define CRG_PERRSTSTAT4                         (CRG_REG_BASE + 0x098)
+#define CRG_ISOEN                               (CRG_REG_BASE + 0x144)
+#define CRG_ISODIS                              (CRG_REG_BASE + 0x148)
+#define CRG_ISOSTAT                             (CRG_REG_BASE + 0x14C)
+
+#define PERI_UFS_BIT                            (1 << 12)
+#define PERI_ARST_UFS_BIT                       (1 << 7)
+
+#define PEREN2_HKADCSSI                         BIT24
+
+#define PEREN4_GT_ACLK_USB3OTG                  (1 << 1)
+#define PEREN4_GT_CLK_USB3OTG_REF               (1 << 0)
+
+#define PERRSTEN2_HKADCSSI                      BIT24
+
+#define PERRSTEN4_USB3OTG_MUX                   (1 << 8)
+#define PERRSTEN4_USB3OTG_AHBIF                 (1 << 7)
+#define PERRSTEN4_USB3OTG_32K                   (1 << 6)
+#define PERRSTEN4_USB3OTG                       (1 << 5)
+#define PERRSTEN4_USB3OTGPHY_POR                (1 << 3)
+
+#define PERISOEN_USB_REFCLK_ISO_EN              (1 << 25)
+
+#define CRG_CLKDIV16_OFFSET                     0x0E8
+#define SC_DIV_UFSPHY_CFG_MASK                  (0x3 << 9)
+#define SC_DIV_UFSPHY_CFG(x)                    (((x) & 0x3) << 9)
+
+#define CRG_CLKDIV17_OFFSET                     0x0EC
+#define SC_DIV_UFS_PERIBUS                      (1 << 14)
+
+#define UFS_SYS_REG_BASE                        0xFF3B1000
+
+#define UFS_SYS_PSW_POWER_CTRL_OFFSET           0x004
+#define UFS_SYS_PHY_ISO_EN_OFFSET               0x008
+#define UFS_SYS_HC_LP_CTRL_OFFSET               0x00C
+#define UFS_SYS_PHY_CLK_CTRL_OFFSET             0x010
+#define UFS_SYS_PSW_CLK_CTRL_OFFSET             0x014
+#define UFS_SYS_CLOCK_GATE_BYPASS_OFFSET        0x018
+#define UFS_SYS_RESET_CTRL_EN_OFFSET            0x01C
+#define UFS_SYS_MONITOR_HH_OFFSET               0x03C
+#define UFS_SYS_UFS_SYSCTRL_OFFSET              0x05C
+#define UFS_SYS_UFS_DEVICE_RESET_CTRL_OFFSET    0x060
+#define UFS_SYS_UFS_APB_ADDR_MASK_OFFSET        0x064
+
+#define BIT_UFS_PSW_ISO_CTRL                    (1 << 16)
+#define BIT_UFS_PSW_MTCMOS_EN                   (1 << 0)
+#define BIT_UFS_REFCLK_ISO_EN                   (1 << 16)
+#define BIT_UFS_PHY_ISO_CTRL                    (1 << 0)
+#define BIT_SYSCTRL_LP_ISOL_EN                  (1 << 16)
+#define BIT_SYSCTRL_PWR_READY                   (1 << 8)
+#define BIT_SYSCTRL_REF_CLOCK_EN                (1 << 24)
+#define MASK_SYSCTRL_REF_CLOCK_SEL              (3 << 8)
+#define MASK_SYSCTRL_CFG_CLOCK_FREQ             (0xFF)
+#define BIT_SYSCTRL_PSW_CLK_EN                  (1 << 4)
+#define MASK_UFS_CLK_GATE_BYPASS                (0x3F)
+#define BIT_SYSCTRL_LP_RESET_N                  (1 << 0)
+#define BIT_UFS_REFCLK_SRC_SE1                  (1 << 0)
+#define MASK_UFS_SYSCTRL_BYPASS                 (0x3F << 16)
+#define MASK_UFS_DEVICE_RESET                   (1 << 16)
+#define BIT_UFS_DEVICE_RESET                    (1 << 0)
+
+#endif /* __HI3660_H__ */
diff --git a/Platforms/Hisilicon/HiKey960/Include/Hkadc.h b/Platforms/Hisilicon/HiKey960/Include/Hkadc.h
new file mode 100644
index 0000000..93ab5db
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Include/Hkadc.h
@@ -0,0 +1,66 @@
+/** @file
+*
+*  Copyright (c) 2016-2017, Linaro Ltd. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __HKADC_H__
+#define __HKADC_H__
+
+#include <Hi3660.h>
+
+#define HKADC_DSP_START                         (HKADC_SSI_REG_BASE + 0x000)
+#define HKADC_WR_NUM                            (HKADC_SSI_REG_BASE + 0x008)
+#define HKADC_DSP_START_CLR                     (HKADC_SSI_REG_BASE + 0x01C)
+#define HKADC_WR01_DATA                         (HKADC_SSI_REG_BASE + 0x020)
+
+#define WR1_WRITE_MODE                          BIT31
+#define WR1_READ_MODE                           (0 << 31)
+#define WR1_ADDR(x)                             (((x) & 0x7F) << 24)
+#define WR1_DATA(x)                             (((x) & 0xFF) << 16)
+#define WR0_WRITE_MODE                          BIT15
+#define WR0_READ_MODE                           (0 << 15)
+#define WR0_ADDR(x)                             (((x) & 0x7F) << 8)
+#define WR0_DATA(x)                             ((x) & 0xFF)
+
+#define HKADC_WR23_DATA                         (HKADC_SSI_REG_BASE + 0x024)
+#define HKADC_WR45_DATA                         (HKADC_SSI_REG_BASE + 0x028)
+#define HKADC_DELAY01                           (HKADC_SSI_REG_BASE + 0x030)
+#define HKADC_DELAY23                           (HKADC_SSI_REG_BASE + 0x034)
+#define HKADC_DELAY45                           (HKADC_SSI_REG_BASE + 0x038)
+#define HKADC_DSP_RD2_DATA                      (HKADC_SSI_REG_BASE + 0x048)
+#define HKADC_DSP_RD3_DATA                      (HKADC_SSI_REG_BASE + 0x04C)
+
+// HKADC Internal Registers
+#define HKADC_CTRL_ADDR                         0x00
+#define HKADC_START_ADDR                        0x01
+#define HKADC_DATA1_ADDR                        0x03   // high 8 bits
+#define HKADC_DATA0_ADDR                        0x04   // low 8 bits
+#define HKADC_MODE_CFG                          0x0A
+
+#define HKADC_VALUE_HIGH                        0x0FF0
+#define HKADC_VALUE_LOW                         0x000F
+#define HKADC_VALID_VALUE                       0x0FFF
+
+#define HKADC_CHANNEL_MAX                       15
+#define HKADC_VREF_1V8                          1800
+#define HKADC_ACCURACY                          0x0FFF
+
+#define HKADC_WR01_VALUE                        ((HKADC_START_ADDR << 24) | (0x1 << 16))
+#define HKADC_WR23_VALUE                        ((0x1 << 31) | (HKADC_DATA0_ADDR << 24) | (1 << 15) | (HKADC_DATA1_ADDR << 8))
+#define HKADC_WR45_VALUE                        (0x80)
+#define HKADC_CHANNEL0_DELAY01_VALUE            ((0x0700 << 16) | 0xFFFF)
+#define HKADC_DELAY01_VALUE                     ((0x0700 << 16) | 0x0200)
+#define HKADC_DELAY23_VALUE                     ((0x00C8 << 16) | 0x00C8)
+#define START_DELAY_TIMEOUT                     2000
+#define HKADC_WR_NUM_VALUE                      4
+
+#endif /* __HKADC_H__ */
diff --git a/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/AArch64/HiKey960Helper.S b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/AArch64/HiKey960Helper.S
new file mode 100644
index 0000000..0589c53
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/AArch64/HiKey960Helper.S
@@ -0,0 +1,52 @@
+#
+#  Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+  MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
+  cmp   w0, w1
+  cset  x0, eq
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
+  ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #6
+  ret
diff --git a/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960.c b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960.c
new file mode 100644
index 0000000..efbfb5f
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960.c
@@ -0,0 +1,189 @@
+/** @file
+*
+*  Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Drivers/PL011Uart.h>
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+ARM_CORE_INFO mHiKey960InfoTable[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 2
+    0x0, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 3
+    0x0, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 0
+    0x1, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 1
+    0x1, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 2
+    0x1, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 1, Core 3
+    0x1, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (UINT64)0xFFFFFFFF
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  RETURN_STATUS       Status;
+  UINT64              BaudRate;
+  UINT32              ReceiveFifoDepth;
+  EFI_PARITY_TYPE     Parity;
+  UINT8               DataBits;
+  EFI_STOP_BITS_TYPE  StopBits;
+
+  Status = RETURN_SUCCESS;
+
+  //
+  // Initialize the Serial Debug UART
+  //
+  if (FixedPcdGet64 (PcdSerialDbgRegisterBase)) {
+    ReceiveFifoDepth = 0; // Use the default value for FIFO depth
+    Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+    DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+    StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
+
+    BaudRate = (UINTN)FixedPcdGet64 (PcdSerialDbgUartBaudRate);
+    Status = PL011UartInitializePort (
+               (UINTN)FixedPcdGet64 (PcdSerialDbgRegisterBase),
+               FixedPcdGet32 (PcdSerialDbgUartClkInHz),
+               &BaudRate,
+               &ReceiveFifoDepth,
+               &Parity,
+               &DataBits,
+               &StopBits
+               );
+  }
+
+  return Status;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  // Only support one cluster
+  *CoreCount    = sizeof(mHiKey960InfoTable) / sizeof(ARM_CORE_INFO);
+  *ArmCoreTable = mHiKey960InfoTable;
+  return EFI_SUCCESS;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &mArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof(gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
diff --git a/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Lib.inf b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Lib.inf
new file mode 100644
index 0000000..c85956b
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Lib.inf
@@ -0,0 +1,63 @@
+#
+#  Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = HiKey960Lib
+  FILE_GUID                      = 977ad020-e78c-4349-bda8-a3dedfd3aa47
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  IoLib
+  ArmLib
+  HobLib
+  MemoryAllocationLib
+  SerialPortLib
+
+[Sources.common]
+  HiKey960.c
+  HiKey960Mem.c
+
+[Sources.AARCH64]
+  AArch64/HiKey960Helper.S
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+  #
+  # PL011 Serial Debug UART
+  #
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
diff --git a/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c
new file mode 100644
index 0000000..174bac2
--- /dev/null
+++ b/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c
@@ -0,0 +1,173 @@
+/** @file
+*
+*  Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+// The total number of descriptors, including the final "end-of-table" descriptor.
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+#define HI3660_PERIPH_BASE              0xE0000000
+#define HI3660_PERIPH_SZ                0x20000000
+
+#define HIKEY960_EXTRA_SYSTEM_MEMORY_BASE  0x0000000100000000
+#define HIKEY960_EXTRA_SYSTEM_MEMORY_SIZE  0x0000000020000000
+
+#define HIKEY960_MEMORY_SIZE               0x0000000100000000
+
+#define HIKEY960_RESERVED_MEMORY
+
+STATIC struct HiKey960ReservedMemory {
+  EFI_PHYSICAL_ADDRESS         Offset;
+  EFI_PHYSICAL_ADDRESS         Size;
+} HiKey960ReservedMemoryBuffer [] = {
+  { 0x1AC00000, 0x00098000 },    // ARM-TF reserved
+  { 0x32000000, 0x00100000 },    // PSTORE/RAMOOPS
+  { 0x32100000, 0x00001000 },    // ADB REBOOT "REASON"
+  { 0x3E000000, 0x02000000 },    // TEE OS
+  { 0x89B80000, 0x00100000 },    // MCU Code reserved
+  { 0x89C80000, 0x00040000 }     // MCU reserved
+};
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+  EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
+#ifdef HIKEY960_RESERVED_MEMORY
+  UINTN                         Index = 0, Count, ReservedTop;
+  EFI_PEI_HOB_POINTERS          NextHob;
+  UINT64                        ResourceLength;
+  EFI_PHYSICAL_ADDRESS          ResourceTop;
+#endif
+
+  ResourceAttributes = (
+    EFI_RESOURCE_ATTRIBUTE_PRESENT |
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+    EFI_RESOURCE_ATTRIBUTE_TESTED
+  );
+
+  // Create initial Base Hob for system memory.
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_SYSTEM_MEMORY,
+    ResourceAttributes,
+    PcdGet64 (PcdSystemMemoryBase),
+    PcdGet64 (PcdSystemMemorySize)
+  );
+
+#ifdef HIKEY960_RESERVED_MEMORY
+  NextHob.Raw = GetHobList ();
+  Count = sizeof (HiKey960ReservedMemoryBuffer) / sizeof (struct HiKey960ReservedMemory);
+  while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL)
+  {
+    if (Index >= Count)
+      break;
+    if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
+        (HiKey960ReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) &&
+        ((HiKey960ReservedMemoryBuffer[Index].Offset + HiKey960ReservedMemoryBuffer[Index].Size) <=
+         NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))
+    {
+      ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
+      ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
+      ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
+      ReservedTop = HiKey960ReservedMemoryBuffer[Index].Offset + HiKey960ReservedMemoryBuffer[Index].Size;
+
+      // Create the System Memory HOB for the reserved buffer
+      BuildResourceDescriptorHob (
+        EFI_RESOURCE_MEMORY_RESERVED,
+        EFI_RESOURCE_ATTRIBUTE_PRESENT,
+        HiKey960ReservedMemoryBuffer[Index].Offset,
+        HiKey960ReservedMemoryBuffer[Index].Size
+      );
+      // Update the HOB
+      NextHob.ResourceDescriptor->ResourceLength = HiKey960ReservedMemoryBuffer[Index].Offset -
+                                                   NextHob.ResourceDescriptor->PhysicalStart;
+
+      // If there is some memory available on the top of the reserved memory then create a HOB
+      if (ReservedTop < ResourceTop)
+      {
+        BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
+                                    ResourceAttributes,
+                                    ReservedTop,
+                                    ResourceTop - ReservedTop);
+      }
+      Index++;
+    }
+    NextHob.Raw = GET_NEXT_HOB (NextHob);
+  }
+#endif
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+                                                        EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)
+                                                        );
+  if (VirtualMemoryTable == NULL) {
+    return;
+  }
+
+  if (FeaturePcdGet (PcdCacheEnable) == TRUE) {
+    CacheAttributes = DDR_ATTRIBUTES_CACHED;
+  } else {
+    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+  }
+
+  Index = 0;
+
+  // DDR - 3.0GB section
+  VirtualMemoryTable[Index].PhysicalBase    = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemorySize);
+  VirtualMemoryTable[Index].Attributes      = CacheAttributes;
+
+  // Hi3660 SOC peripherals
+  VirtualMemoryTable[++Index].PhysicalBase  = HI3660_PERIPH_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = HI3660_PERIPH_BASE;
+  VirtualMemoryTable[Index].Length          = HI3660_PERIPH_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase  = 0;
+  VirtualMemoryTable[Index].VirtualBase     = 0;
+  VirtualMemoryTable[Index].Length          = 0;
+  VirtualMemoryTable[Index].Attributes      = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+  ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c b/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
new file mode 100644
index 0000000..b1586a8
--- /dev/null
+++ b/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
@@ -0,0 +1,656 @@
+/** @file
+  Implementation for PlatformBootManagerLib library class interfaces.
+
+  Copyright (C) 2015-2016, Red Hat, Inc.
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016-2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DevicePathLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootManagerLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/BlockIo.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/DevicePathFromText.h>
+#include <Protocol/DevicePathToText.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/LoadedImage.h>
+#include <Guid/EventGroup.h>
+#include <Guid/TtyTerm.h>
+
+#include "PlatformBm.h"
+
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
+
+#define GRUB_FILE_NAME       L"\\EFI\\BOOT\\GRUBAA64.EFI"
+#define SD_FILE_NAME         L"\\EFI\\BOOT\\BOOTAA64.EFI"
+
+
+#pragma pack (1)
+typedef struct {
+  VENDOR_DEVICE_PATH         SerialDxe;
+  UART_DEVICE_PATH           Uart;
+  VENDOR_DEFINED_DEVICE_PATH TermType;
+  EFI_DEVICE_PATH_PROTOCOL   End;
+} PLATFORM_SERIAL_CONSOLE;
+#pragma pack ()
+
+#define SERIAL_DXE_FILE_GUID { \
+          0xD3987D4B, 0x971A, 0x435F, \
+          { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \
+          }
+
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+  //
+  // VENDOR_DEVICE_PATH SerialDxe
+  //
+  {
+    { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
+    SERIAL_DXE_FILE_GUID
+  },
+
+  //
+  // UART_DEVICE_PATH Uart
+  //
+  {
+    { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+    0,                                      // Reserved
+    FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+    FixedPcdGet8 (PcdUartDefaultDataBits),  // DataBits
+    FixedPcdGet8 (PcdUartDefaultParity),    // Parity
+    FixedPcdGet8 (PcdUartDefaultStopBits)   // StopBits
+  },
+
+  //
+  // VENDOR_DEFINED_DEVICE_PATH TermType
+  //
+  {
+    {
+      MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
+      DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
+    }
+    //
+    // Guid to be filled in dynamically
+    //
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+    END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
+
+#pragma pack (1)
+typedef struct {
+  USB_CLASS_DEVICE_PATH    Keyboard;
+  EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_USB_KEYBOARD;
+#pragma pack ()
+
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+  //
+  // USB_CLASS_DEVICE_PATH Keyboard
+  //
+  {
+    {
+      MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,
+      DP_NODE_LEN (USB_CLASS_DEVICE_PATH)
+    },
+    0xFFFF, // VendorId: any
+    0xFFFF, // ProductId: any
+    3,      // DeviceClass: HID
+    1,      // DeviceSubClass: boot
+    1       // DeviceProtocol: keyboard
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+    END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
+
+/**
+  Check if the handle satisfies a particular condition.
+
+  @param[in] Handle      The handle to check.
+  @param[in] ReportText  A caller-allocated string passed in for reporting
+                         purposes. It must never be NULL.
+
+  @retval TRUE   The condition is satisfied.
+  @retval FALSE  Otherwise. This includes the case when the condition could not
+                 be fully evaluated due to an error.
+**/
+typedef
+BOOLEAN
+(EFIAPI *FILTER_FUNCTION) (
+  IN EFI_HANDLE   Handle,
+  IN CONST CHAR16 *ReportText
+  );
+
+
+/**
+  Process a handle.
+
+  @param[in] Handle      The handle to process.
+  @param[in] ReportText  A caller-allocated string passed in for reporting
+                         purposes. It must never be NULL.
+**/
+typedef
+VOID
+(EFIAPI *CALLBACK_FUNCTION)  (
+  IN EFI_HANDLE   Handle,
+  IN CONST CHAR16 *ReportText
+  );
+
+/**
+  Locate all handles that carry the specified protocol, filter them with a
+  callback function, and pass each handle that passes the filter to another
+  callback.
+
+  @param[in] ProtocolGuid  The protocol to look for.
+
+  @param[in] Filter        The filter function to pass each handle to. If this
+                           parameter is NULL, then all handles are processed.
+
+  @param[in] Process       The callback function to pass each handle to that
+                           clears the filter.
+**/
+STATIC
+VOID
+FilterAndProcess (
+  IN EFI_GUID          *ProtocolGuid,
+  IN FILTER_FUNCTION   Filter         OPTIONAL,
+  IN CALLBACK_FUNCTION Process
+  )
+{
+  EFI_STATUS Status;
+  EFI_HANDLE *Handles;
+  UINTN      NoHandles;
+  UINTN      Idx;
+
+  Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
+                  NULL /* SearchKey */, &NoHandles, &Handles);
+  if (EFI_ERROR (Status)) {
+    //
+    // This is not an error, just an informative condition.
+    //
+    DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
+      Status));
+    return;
+  }
+
+  ASSERT (NoHandles > 0);
+  for (Idx = 0; Idx < NoHandles; ++Idx) {
+    CHAR16        *DevicePathText;
+    STATIC CHAR16 Fallback[] = L"<device path unavailable>";
+
+    //
+    // The ConvertDevicePathToText() function handles NULL input transparently.
+    //
+    DevicePathText = ConvertDevicePathToText (
+                       DevicePathFromHandle (Handles[Idx]),
+                       FALSE, // DisplayOnly
+                       FALSE  // AllowShortcuts
+                       );
+    if (DevicePathText == NULL) {
+      DevicePathText = Fallback;
+    }
+
+    if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {
+      Process (Handles[Idx], DevicePathText);
+    }
+
+    if (DevicePathText != Fallback) {
+      FreePool (DevicePathText);
+    }
+  }
+  gBS->FreePool (Handles);
+}
+
+
+/**
+  This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the
+  handle, and adds it to ConOut and ErrOut.
+**/
+STATIC
+VOID
+EFIAPI
+AddOutput (
+  IN EFI_HANDLE   Handle,
+  IN CONST CHAR16 *ReportText
+  )
+{
+  EFI_STATUS               Status;
+  EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+  DevicePath = DevicePathFromHandle (Handle);
+  if (DevicePath == NULL) {
+    DEBUG ((DEBUG_ERROR, "%a: %s: handle %p: device path not found\n",
+      __FUNCTION__, ReportText, Handle));
+    return;
+  }
+
+  Status = EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,
+      ReportText, Status));
+    return;
+  }
+
+  Status = EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,
+      ReportText, Status));
+    return;
+  }
+
+  DEBUG ((DEBUG_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,
+    ReportText));
+}
+
+STATIC
+VOID
+PlatformRegisterFvBootOption (
+  EFI_GUID                         *FileGuid,
+  CHAR16                           *Description,
+  UINT32                           Attributes
+  )
+{
+  EFI_STATUS                        Status;
+  INTN                              OptionIndex;
+  EFI_BOOT_MANAGER_LOAD_OPTION      NewOption;
+  EFI_BOOT_MANAGER_LOAD_OPTION      *BootOptions;
+  UINTN                             BootOptionCount;
+  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+  EFI_LOADED_IMAGE_PROTOCOL         *LoadedImage;
+  EFI_DEVICE_PATH_PROTOCOL          *DevicePath;
+
+  Status = gBS->HandleProtocol (
+                  gImageHandle,
+                  &gEfiLoadedImageProtocolGuid,
+                  (VOID **) &LoadedImage
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
+  DevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle);
+  ASSERT (DevicePath != NULL);
+  DevicePath = AppendDevicePathNode (
+                 DevicePath,
+                 (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+                 );
+  ASSERT (DevicePath != NULL);
+
+  Status = EfiBootManagerInitializeLoadOption (
+             &NewOption,
+             LoadOptionNumberUnassigned,
+             LoadOptionTypeBoot,
+             Attributes,
+             Description,
+             DevicePath,
+             NULL,
+             0
+             );
+  ASSERT_EFI_ERROR (Status);
+  FreePool (DevicePath);
+
+  BootOptions = EfiBootManagerGetLoadOptions (
+                  &BootOptionCount, LoadOptionTypeBoot
+                  );
+
+  OptionIndex = EfiBootManagerFindLoadOption (
+                  &NewOption, BootOptions, BootOptionCount
+                  );
+
+  if (OptionIndex == -1) {
+    Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  EfiBootManagerFreeLoadOption (&NewOption);
+  EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
+}
+
+
+STATIC
+VOID
+PlatformRegisterBootSd (
+  VOID
+  )
+{
+  EFI_STATUS                           Status;
+  CHAR16                              *BootPathStr;
+  EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL  *EfiDevicePathFromTextProtocol;
+  EFI_DEVICE_PATH                     *DevicePath;
+  EFI_DEVICE_PATH                     *FileDevicePath;
+  FILEPATH_DEVICE_PATH                *FilePath;
+  UINTN                                Size;
+  EFI_BOOT_MANAGER_LOAD_OPTION         NewOption;
+  EFI_BOOT_MANAGER_LOAD_OPTION        *BootOptions;
+  UINTN                                BootOptionCount;
+  INTN                                 OptionIndex;
+
+  //
+  // Get PcdSdBootDevicePath
+  //
+  BootPathStr = (CHAR16 *)PcdGetPtr (PcdSdBootDevicePath);
+  ASSERT (BootPathStr != NULL);
+  Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
+  ASSERT_EFI_ERROR(Status);
+  DevicePath = (EFI_DEVICE_PATH *)EfiDevicePathFromTextProtocol->ConvertTextToDevicePath (BootPathStr);
+  ASSERT (DevicePath != NULL);
+
+  Size = StrSize (SD_FILE_NAME);
+  FileDevicePath = AllocatePool (Size + SIZE_OF_FILEPATH_DEVICE_PATH + END_DEVICE_PATH_LENGTH);
+  if (FileDevicePath != NULL) {
+    FilePath = (FILEPATH_DEVICE_PATH *) FileDevicePath;
+    FilePath->Header.Type    = MEDIA_DEVICE_PATH;
+    FilePath->Header.SubType = MEDIA_FILEPATH_DP;
+    CopyMem (&FilePath->PathName, SD_FILE_NAME, Size);
+    SetDevicePathNodeLength (&FilePath->Header, Size + SIZE_OF_FILEPATH_DEVICE_PATH);
+    SetDevicePathEndNode (NextDevicePathNode (&FilePath->Header));
+
+    DevicePath = AppendDevicePath (DevicePath, FileDevicePath);
+    FreePool (FileDevicePath);
+  }
+  Status = EfiBootManagerInitializeLoadOption (
+             &NewOption,
+             LoadOptionNumberUnassigned,
+             LoadOptionTypeBoot,
+             LOAD_OPTION_ACTIVE,
+             L"Boot from SD",
+             DevicePath,
+             NULL,
+             0
+             );
+  ASSERT_EFI_ERROR (Status);
+  FreePool (DevicePath);
+
+  BootOptions = EfiBootManagerGetLoadOptions (
+                  &BootOptionCount, LoadOptionTypeBoot
+                  );
+
+  OptionIndex = EfiBootManagerFindLoadOption (
+                  &NewOption, BootOptions, BootOptionCount
+                  );
+
+  if (OptionIndex == -1) {
+    Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  EfiBootManagerFreeLoadOption (&NewOption);
+  EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
+}
+
+STATIC
+VOID
+PlatformRegisterBootGrub (
+  VOID
+  )
+{
+  EFI_STATUS                           Status;
+  CHAR16                              *BootPathStr;
+  EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL  *EfiDevicePathFromTextProtocol;
+  EFI_DEVICE_PATH                     *DevicePath;
+  EFI_DEVICE_PATH                     *FileDevicePath;
+  FILEPATH_DEVICE_PATH                *FilePath;
+  UINTN                                Size;
+  EFI_BOOT_MANAGER_LOAD_OPTION         NewOption;
+  EFI_BOOT_MANAGER_LOAD_OPTION        *BootOptions;
+  UINTN                                BootOptionCount;
+  INTN                                 OptionIndex;
+
+  //
+  // Get PcdAndroidBootDevicePath
+  //
+  BootPathStr = (CHAR16 *)PcdGetPtr (PcdAndroidBootDevicePath);
+  ASSERT (BootPathStr != NULL);
+  Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
+  ASSERT_EFI_ERROR(Status);
+  DevicePath = (EFI_DEVICE_PATH *)EfiDevicePathFromTextProtocol->ConvertTextToDevicePath (BootPathStr);
+  ASSERT (DevicePath != NULL);
+
+  Size = StrSize (GRUB_FILE_NAME);
+  FileDevicePath = AllocatePool (Size + SIZE_OF_FILEPATH_DEVICE_PATH + END_DEVICE_PATH_LENGTH);
+  if (FileDevicePath != NULL) {
+    FilePath = (FILEPATH_DEVICE_PATH *) FileDevicePath;
+    FilePath->Header.Type    = MEDIA_DEVICE_PATH;
+    FilePath->Header.SubType = MEDIA_FILEPATH_DP;
+    CopyMem (&FilePath->PathName, GRUB_FILE_NAME, Size);
+    SetDevicePathNodeLength (&FilePath->Header, Size + SIZE_OF_FILEPATH_DEVICE_PATH);
+    SetDevicePathEndNode (NextDevicePathNode (&FilePath->Header));
+
+    DevicePath = AppendDevicePath (DevicePath, FileDevicePath);
+    FreePool (FileDevicePath);
+  }
+  Status = EfiBootManagerInitializeLoadOption (
+             &NewOption,
+             LoadOptionNumberUnassigned,
+             LoadOptionTypeBoot,
+             LOAD_OPTION_ACTIVE,
+             L"Grub",
+             DevicePath,
+             NULL,
+             0
+             );
+  ASSERT_EFI_ERROR (Status);
+  FreePool (DevicePath);
+
+  BootOptions = EfiBootManagerGetLoadOptions (
+                  &BootOptionCount, LoadOptionTypeBoot
+                  );
+
+  OptionIndex = EfiBootManagerFindLoadOption (
+                  &NewOption, BootOptions, BootOptionCount
+                  );
+
+  if (OptionIndex == -1) {
+    Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  EfiBootManagerFreeLoadOption (&NewOption);
+  EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
+
+}
+
+STATIC
+VOID
+PlatformRegisterOptionsAndKeys (
+  VOID
+  )
+{
+  EFI_STATUS                           Status;
+  EFI_INPUT_KEY                        Enter;
+  EFI_INPUT_KEY                        Esc;
+  EFI_INPUT_KEY                        KeyF;
+  EFI_BOOT_MANAGER_LOAD_OPTION         BootOption;
+
+  //
+  // Register Boot on SD. OptionNumber is 1.
+  //
+  PlatformRegisterBootSd ();
+
+  //
+  // Register Boot. OptionNumber is 2.
+  //
+  PlatformRegisterBootGrub ();
+
+  //
+  // Register Android Boot. OptionNumber is 3.
+  //
+  PlatformRegisterFvBootOption (
+    PcdGetPtr (PcdAndroidBootFile), L"Android Boot", LOAD_OPTION_ACTIVE
+    );
+
+  //
+  // Register Android Fastboot. OptionNumber is 4.
+  //
+  PlatformRegisterFvBootOption (
+    PcdGetPtr (PcdAndroidFastbootFile), L"Android Fastboot", LOAD_OPTION_ACTIVE
+    );
+
+  //
+  // Register ENTER as CONTINUE key
+  //
+  Enter.ScanCode    = SCAN_NULL;
+  Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
+  Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Map ESC to Boot Manager Menu
+  //
+  Esc.ScanCode    = SCAN_ESC;
+  Esc.UnicodeChar = CHAR_NULL;
+  Status = EfiBootManagerGetBootManagerMenu (&BootOption);
+  ASSERT_EFI_ERROR (Status);
+  Status = EfiBootManagerAddKeyOptionVariable (
+             NULL, (UINT16) BootOption.OptionNumber, 0, &Esc, NULL
+             );
+  ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
+
+  //
+  // Map KeyF to Android Fastboot
+  //
+  KeyF.ScanCode    = SCAN_NULL;
+  KeyF.UnicodeChar = 'f';
+  Status = EfiBootManagerAddKeyOptionVariable (
+             NULL, 4, 0, &KeyF, NULL
+             );
+  ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
+}
+
+
+//
+// BDS Platform Functions
+//
+/**
+  Do the platform init, can be customized by OEM/IBV
+  Possible things that can be done in PlatformBootManagerBeforeConsole:
+  > Update console variable: 1. include hot-plug devices;
+  >                          2. Clear ConIn and add SOL for AMT
+  > Register new Driver#### or Boot####
+  > Register new Key####: e.g.: F12
+  > Signal ReadyToLock event
+  > Authentication action: 1. connect Auth devices;
+  >                        2. Identify auto logon user.
+**/
+VOID
+EFIAPI
+PlatformBootManagerBeforeConsole (
+  VOID
+  )
+{
+  //
+  // Signal EndOfDxe PI Event
+  //
+  EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);
+
+  //
+  // Now add the device path of all handles with GOP on them to ConOut and
+  // ErrOut.
+  //
+  FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput);
+
+  //
+  // Add the hardcoded short-form USB keyboard device path to ConIn.
+  //
+  EfiBootManagerUpdateConsoleVariable (ConIn,
+    (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);
+
+  //
+  // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
+  //
+  ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4);
+  CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid);
+
+  EfiBootManagerUpdateConsoleVariable (ConIn,
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+  EfiBootManagerUpdateConsoleVariable (ConOut,
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+  EfiBootManagerUpdateConsoleVariable (ErrOut,
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+
+  //
+  // Register platform-specific boot options and keyboard shortcuts.
+  //
+  PlatformRegisterOptionsAndKeys ();
+}
+
+/**
+  Do the platform specific action after the console is ready
+  Possible things that can be done in PlatformBootManagerAfterConsole:
+  > Console post action:
+    > Dynamically switch output mode from 100x31 to 80x25 for certain senarino
+    > Signal console ready platform customized event
+  > Run diagnostics like memory testing
+  > Connect certain devices
+  > Dispatch aditional option roms
+  > Special boot: e.g.: USB boot, enter UI
+**/
+VOID
+EFIAPI
+PlatformBootManagerAfterConsole (
+  VOID
+  )
+{
+  Print (L"Press ESCAPE for boot options ");
+
+  //
+  // Show the splash screen.
+  //
+  EnableQuietBoot (PcdGetPtr (PcdLogoFile));
+
+  //
+  // Connect the rest of the devices.
+  //
+  EfiBootManagerConnectAll ();
+
+  //
+  // Enumerate all possible boot options.
+  //
+  EfiBootManagerRefreshAllBootOption ();
+
+  //
+  // Register UEFI Shell
+  //
+  PlatformRegisterFvBootOption (
+    PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE
+    );
+}
+
+/**
+  This function is called each second during the boot manager waits the
+  timeout.
+
+  @param TimeoutRemain  The remaining timeout.
+**/
+VOID
+EFIAPI
+PlatformBootManagerWaitCallback (
+  UINT16          TimeoutRemain
+  )
+{
+  Print (L".");
+}
diff --git a/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h b/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h
new file mode 100644
index 0000000..0a3c626
--- /dev/null
+++ b/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h
@@ -0,0 +1,59 @@
+/** @file
+  Head file for BDS Platform specific code
+
+  Copyright (C) 2015-2016, Red Hat, Inc.
+  Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_BM_H_
+#define _PLATFORM_BM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+/**
+  Use SystemTable Conout to stop video based Simple Text Out consoles from
+  going to the video device. Put up LogoFile on every video device that is a
+  console.
+
+  @param[in]  LogoFile   File name of logo to display on the center of the
+                         screen.
+
+  @retval EFI_SUCCESS     ConsoleControl has been flipped to graphics and logo
+                          displayed.
+  @retval EFI_UNSUPPORTED Logo not found
+**/
+EFI_STATUS
+EnableQuietBoot (
+  IN  EFI_GUID  *LogoFile
+  );
+
+/**
+  Use SystemTable Conout to turn on video based Simple Text Out consoles. The
+  Simple Text Out screens will now be synced up with all non video output
+  devices
+
+  @retval EFI_SUCCESS     UGA devices are back in text mode and synced up.
+**/
+EFI_STATUS
+DisableQuietBoot (
+  VOID
+  );
+
+#endif // _PLATFORM_BM_H_
diff --git a/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
new file mode 100644
index 0000000..cf3d6a5
--- /dev/null
+++ b/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -0,0 +1,95 @@
+## @file
+#  Implementation for PlatformBootManagerLib library class interfaces.
+#
+#  Copyright (C) 2015-2016, Red Hat, Inc.
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2016-2017, Linaro Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+#  IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformBootManagerLib
+  FILE_GUID                      = a5a1ecfc-7c11-427a-8803-012869067095
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PlatformBootManagerLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = ARM AARCH64
+#
+
+[Sources]
+  PlatformBm.c
+  QuietBoot.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/OpenPlatformPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  DevicePathLib
+  DxeServicesLib
+  MemoryAllocationLib
+  PcdLib
+  PrintLib
+  UefiBootManagerLib
+  UefiBootServicesTableLib
+  UefiLib
+
+[FeaturePcd]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootlogoOnlyEnable
+  gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
+
+[FixedPcd]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+  gOpenPlatformTokenSpaceGuid.PcdAndroidFastbootFile
+  gOpenPlatformTokenSpaceGuid.PcdAndroidBootFile
+
+[Guids]
+  gEfiFileInfoGuid
+  gEfiFileSystemInfoGuid
+  gEfiFileSystemVolumeLabelInfoIdGuid
+  gEfiEndOfDxeEventGroupGuid
+  gEfiTtyTermGuid
+
+[Protocols]
+  gEfiDevicePathFromTextProtocolGuid
+  gEfiDevicePathProtocolGuid
+  gEfiGraphicsOutputProtocolGuid
+  gEfiLoadedImageProtocolGuid
+  gEfiOEMBadgingProtocolGuid
+  gEfiPciRootBridgeIoProtocolGuid
+  gEfiSimpleFileSystemProtocolGuid
+  gEfiDevicePathToTextProtocolGuid
+
+[Pcd]
+  gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath
+  gEmbeddedTokenSpaceGuid.PcdSdBootDevicePath
diff --git a/Platforms/Hisilicon/Library/PlatformBootManagerLib/QuietBoot.c b/Platforms/Hisilicon/Library/PlatformBootManagerLib/QuietBoot.c
new file mode 100644
index 0000000..687bda0
--- /dev/null
+++ b/Platforms/Hisilicon/Library/PlatformBootManagerLib/QuietBoot.c
@@ -0,0 +1,680 @@
+/** @file
+  Platform BDS function for quiet boot support.
+
+Copyright (C) 2016, Red Hat, Inc.
+Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Bmp.h>
+#include <Library/DxeServicesLib.h>
+#include <Protocol/BootLogo.h>
+#include <Protocol/OEMBadging.h>
+#include <Protocol/UgaDraw.h>
+
+#include "PlatformBm.h"
+
+/**
+  Convert a *.BMP graphics image to a GOP blt buffer. If a NULL Blt buffer
+  is passed in a GopBlt buffer will be allocated by this routine. If a GopBlt
+  buffer is passed in it will be used if it is big enough.
+
+  @param  BmpImage      Pointer to BMP file
+  @param  BmpImageSize  Number of bytes in BmpImage
+  @param  GopBlt        Buffer containing GOP version of BmpImage.
+  @param  GopBltSize    Size of GopBlt in bytes.
+  @param  PixelHeight   Height of GopBlt/BmpImage in pixels
+  @param  PixelWidth    Width of GopBlt/BmpImage in pixels
+
+  @retval EFI_SUCCESS           GopBlt and GopBltSize are returned.
+  @retval EFI_UNSUPPORTED       BmpImage is not a valid *.BMP image
+  @retval EFI_BUFFER_TOO_SMALL  The passed in GopBlt buffer is not big enough.
+                                GopBltSize will contain the required size.
+  @retval EFI_OUT_OF_RESOURCES  No enough buffer to allocate.
+
+**/
+STATIC
+EFI_STATUS
+ConvertBmpToGopBlt (
+  IN     VOID      *BmpImage,
+  IN     UINTN     BmpImageSize,
+  IN OUT VOID      **GopBlt,
+  IN OUT UINTN     *GopBltSize,
+     OUT UINTN     *PixelHeight,
+     OUT UINTN     *PixelWidth
+  )
+{
+  UINT8                         *Image;
+  UINT8                         *ImageHeader;
+  BMP_IMAGE_HEADER              *BmpHeader;
+  BMP_COLOR_MAP                 *BmpColorMap;
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer;
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
+  UINT64                        BltBufferSize;
+  UINTN                         Index;
+  UINTN                         Height;
+  UINTN                         Width;
+  UINTN                         ImageIndex;
+  UINT32                        DataSizePerLine;
+  BOOLEAN                       IsAllocated;
+  UINT32                        ColorMapNum;
+
+  if (sizeof (BMP_IMAGE_HEADER) > BmpImageSize) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  BmpHeader = (BMP_IMAGE_HEADER *) BmpImage;
+
+  if (BmpHeader->CharB != 'B' || BmpHeader->CharM != 'M') {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Doesn't support compress.
+  //
+  if (BmpHeader->CompressionType != 0) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Only support BITMAPINFOHEADER format.
+  // BITMAPFILEHEADER + BITMAPINFOHEADER = BMP_IMAGE_HEADER
+  //
+  if (BmpHeader->HeaderSize != sizeof (BMP_IMAGE_HEADER) - OFFSET_OF(BMP_IMAGE_HEADER, HeaderSize)) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // The data size in each line must be 4 byte alignment.
+  //
+  DataSizePerLine = ((BmpHeader->PixelWidth * BmpHeader->BitPerPixel + 31) >> 3) & (~0x3);
+  BltBufferSize = MultU64x32 (DataSizePerLine, BmpHeader->PixelHeight);
+  if (BltBufferSize > (UINT32) ~0) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if ((BmpHeader->Size != BmpImageSize) ||
+      (BmpHeader->Size < BmpHeader->ImageOffset) ||
+      (BmpHeader->Size - BmpHeader->ImageOffset !=  BmpHeader->PixelHeight * DataSizePerLine)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Calculate Color Map offset in the image.
+  //
+  Image       = BmpImage;
+  BmpColorMap = (BMP_COLOR_MAP *) (Image + sizeof (BMP_IMAGE_HEADER));
+  if (BmpHeader->ImageOffset < sizeof (BMP_IMAGE_HEADER)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (BmpHeader->ImageOffset > sizeof (BMP_IMAGE_HEADER)) {
+    switch (BmpHeader->BitPerPixel) {
+      case 1:
+        ColorMapNum = 2;
+        break;
+      case 4:
+        ColorMapNum = 16;
+        break;
+      case 8:
+        ColorMapNum = 256;
+        break;
+      default:
+        ColorMapNum = 0;
+        break;
+      }
+    //
+    // BMP file may has padding data between the bmp header section and the bmp data section.
+    //
+    if (BmpHeader->ImageOffset - sizeof (BMP_IMAGE_HEADER) < sizeof (BMP_COLOR_MAP) * ColorMapNum) {
+      return EFI_INVALID_PARAMETER;
+    }
+  }
+
+  //
+  // Calculate graphics image data address in the image
+  //
+  Image         = ((UINT8 *) BmpImage) + BmpHeader->ImageOffset;
+  ImageHeader   = Image;
+
+  //
+  // Calculate the BltBuffer needed size.
+  //
+  BltBufferSize = MultU64x32 ((UINT64) BmpHeader->PixelWidth, BmpHeader->PixelHeight);
+  //
+  // Ensure the BltBufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) doesn't overflow
+  //
+  if (BltBufferSize > DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
+    return EFI_UNSUPPORTED;
+  }
+  BltBufferSize = MultU64x32 (BltBufferSize, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
+
+  IsAllocated   = FALSE;
+  if (*GopBlt == NULL) {
+    //
+    // GopBlt is not allocated by caller.
+    //
+    *GopBltSize = (UINTN) BltBufferSize;
+    *GopBlt     = AllocatePool (*GopBltSize);
+    IsAllocated = TRUE;
+    if (*GopBlt == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+  } else {
+    //
+    // GopBlt has been allocated by caller.
+    //
+    if (*GopBltSize < (UINTN) BltBufferSize) {
+      *GopBltSize = (UINTN) BltBufferSize;
+      return EFI_BUFFER_TOO_SMALL;
+    }
+  }
+
+  *PixelWidth   = BmpHeader->PixelWidth;
+  *PixelHeight  = BmpHeader->PixelHeight;
+
+  //
+  // Convert image from BMP to Blt buffer format
+  //
+  BltBuffer = *GopBlt;
+  for (Height = 0; Height < BmpHeader->PixelHeight; Height++) {
+    Blt = &BltBuffer[(BmpHeader->PixelHeight - Height - 1) * BmpHeader->PixelWidth];
+    for (Width = 0; Width < BmpHeader->PixelWidth; Width++, Image++, Blt++) {
+      switch (BmpHeader->BitPerPixel) {
+      case 1:
+        //
+        // Convert 1-bit (2 colors) BMP to 24-bit color
+        //
+        for (Index = 0; Index < 8 && Width < BmpHeader->PixelWidth; Index++) {
+          Blt->Red    = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Red;
+          Blt->Green  = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Green;
+          Blt->Blue   = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Blue;
+          Blt++;
+          Width++;
+        }
+
+        Blt--;
+        Width--;
+        break;
+
+      case 4:
+        //
+        // Convert 4-bit (16 colors) BMP Palette to 24-bit color
+        //
+        Index       = (*Image) >> 4;
+        Blt->Red    = BmpColorMap[Index].Red;
+        Blt->Green  = BmpColorMap[Index].Green;
+        Blt->Blue   = BmpColorMap[Index].Blue;
+        if (Width < (BmpHeader->PixelWidth - 1)) {
+          Blt++;
+          Width++;
+          Index       = (*Image) & 0x0f;
+          Blt->Red    = BmpColorMap[Index].Red;
+          Blt->Green  = BmpColorMap[Index].Green;
+          Blt->Blue   = BmpColorMap[Index].Blue;
+        }
+        break;
+
+      case 8:
+        //
+        // Convert 8-bit (256 colors) BMP Palette to 24-bit color
+        //
+        Blt->Red    = BmpColorMap[*Image].Red;
+        Blt->Green  = BmpColorMap[*Image].Green;
+        Blt->Blue   = BmpColorMap[*Image].Blue;
+        break;
+
+      case 24:
+        //
+        // It is 24-bit BMP.
+        //
+        Blt->Blue   = *Image++;
+        Blt->Green  = *Image++;
+        Blt->Red    = *Image;
+        break;
+
+      default:
+        //
+        // Other bit format BMP is not supported.
+        //
+        if (IsAllocated) {
+          FreePool (*GopBlt);
+          *GopBlt = NULL;
+        }
+        return EFI_UNSUPPORTED;
+      };
+
+    }
+
+    ImageIndex = (UINTN) (Image - ImageHeader);
+    if ((ImageIndex % 4) != 0) {
+      //
+      // Bmp Image starts each row on a 32-bit boundary!
+      //
+      Image = Image + (4 - (ImageIndex % 4));
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Use SystemTable Conout to stop video based Simple Text Out consoles from going
+  to the video device. Put up LogoFile on every video device that is a console.
+
+  @param[in]  LogoFile   File name of logo to display on the center of the screen.
+
+  @retval EFI_SUCCESS     ConsoleControl has been flipped to graphics and logo displayed.
+  @retval EFI_UNSUPPORTED Logo not found
+
+**/
+EFI_STATUS
+EnableQuietBoot (
+  IN  EFI_GUID  *LogoFile
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_OEM_BADGING_PROTOCOL      *Badging;
+  UINT32                        SizeOfX;
+  UINT32                        SizeOfY;
+  INTN                          DestX;
+  INTN                          DestY;
+  UINT8                         *ImageData;
+  UINTN                         ImageSize;
+  UINTN                         BltSize;
+  UINT32                        Instance;
+  EFI_BADGING_FORMAT            Format;
+  EFI_BADGING_DISPLAY_ATTRIBUTE Attribute;
+  UINTN                         CoordinateX;
+  UINTN                         CoordinateY;
+  UINTN                         Height;
+  UINTN                         Width;
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
+  EFI_UGA_DRAW_PROTOCOL         *UgaDraw;
+  UINT32                        ColorDepth;
+  UINT32                        RefreshRate;
+  EFI_GRAPHICS_OUTPUT_PROTOCOL  *GraphicsOutput;
+  EFI_BOOT_LOGO_PROTOCOL        *BootLogo;
+  UINTN                         NumberOfLogos;
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *LogoBlt;
+  UINTN                         LogoDestX;
+  UINTN                         LogoDestY;
+  UINTN                         LogoHeight;
+  UINTN                         LogoWidth;
+  UINTN                         NewDestX;
+  UINTN                         NewDestY;
+  UINTN                         NewHeight;
+  UINTN                         NewWidth;
+  UINT64                        BufferSize;
+
+  UgaDraw = NULL;
+  //
+  // Try to open GOP first
+  //
+  Status = gBS->HandleProtocol (gST->ConsoleOutHandle, &gEfiGraphicsOutputProtocolGuid, (VOID **) &GraphicsOutput);
+  if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {
+    GraphicsOutput = NULL;
+    //
+    // Open GOP failed, try to open UGA
+    //
+    Status = gBS->HandleProtocol (gST->ConsoleOutHandle, &gEfiUgaDrawProtocolGuid, (VOID **) &UgaDraw);
+  }
+  if (EFI_ERROR (Status)) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Try to open Boot Logo Protocol.
+  //
+  BootLogo = NULL;
+  gBS->LocateProtocol (&gEfiBootLogoProtocolGuid, NULL, (VOID **) &BootLogo);
+
+  //
+  // Erase Cursor from screen
+  //
+  gST->ConOut->EnableCursor (gST->ConOut, FALSE);
+
+  Badging = NULL;
+  Status  = gBS->LocateProtocol (&gEfiOEMBadgingProtocolGuid, NULL, (VOID **) &Badging);
+
+  if (GraphicsOutput != NULL) {
+    SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
+    SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
+
+  } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {
+    Status = UgaDraw->GetMode (UgaDraw, &SizeOfX, &SizeOfY, &ColorDepth, &RefreshRate);
+    if (EFI_ERROR (Status)) {
+      return EFI_UNSUPPORTED;
+    }
+  } else {
+    return EFI_UNSUPPORTED;
+  }
+
+  Blt = NULL;
+  NumberOfLogos = 0;
+  LogoDestX = 0;
+  LogoDestY = 0;
+  LogoHeight = 0;
+  LogoWidth = 0;
+  NewDestX = 0;
+  NewDestY = 0;
+  NewHeight = 0;
+  NewWidth = 0;
+  Instance = 0;
+  Height = 0;
+  Width = 0;
+  while (1) {
+    ImageData = NULL;
+    ImageSize = 0;
+
+    if (Badging != NULL) {
+      //
+      // Get image from OEMBadging protocol.
+      //
+      Status = Badging->GetImage (
+                          Badging,
+                          &Instance,
+                          &Format,
+                          &ImageData,
+                          &ImageSize,
+                          &Attribute,
+                          &CoordinateX,
+                          &CoordinateY
+                          );
+      if (EFI_ERROR (Status)) {
+        goto Done;
+      }
+
+      //
+      // Currently only support BMP format.
+      //
+      if (Format != EfiBadgingFormatBMP) {
+        if (ImageData != NULL) {
+          FreePool (ImageData);
+        }
+        continue;
+      }
+    } else {
+      //
+      // Get the specified image from FV.
+      //
+      Status = GetSectionFromAnyFv (LogoFile, EFI_SECTION_RAW, 0, (VOID **) &ImageData, &ImageSize);
+      if (EFI_ERROR (Status)) {
+        return EFI_UNSUPPORTED;
+      }
+
+      CoordinateX = 0;
+      CoordinateY = 0;
+      if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) {
+        Attribute   = EfiBadgingDisplayAttributeCenter;
+      } else {
+        Attribute   = EfiBadgingDisplayAttributeCustomized;
+      }
+    }
+
+    if (Blt != NULL) {
+      FreePool (Blt);
+    }
+    Blt = NULL;
+    Status = ConvertBmpToGopBlt (
+              ImageData,
+              ImageSize,
+              (VOID **) &Blt,
+              &BltSize,
+              &Height,
+              &Width
+              );
+    if (EFI_ERROR (Status)) {
+      FreePool (ImageData);
+
+      if (Badging == NULL) {
+        return Status;
+      } else {
+        continue;
+      }
+    }
+
+    //
+    // Calculate the display position according to Attribute.
+    //
+    switch (Attribute) {
+    case EfiBadgingDisplayAttributeLeftTop:
+      DestX = CoordinateX;
+      DestY = CoordinateY;
+      break;
+
+    case EfiBadgingDisplayAttributeCenterTop:
+      DestX = (SizeOfX - Width) / 2;
+      DestY = CoordinateY;
+      break;
+
+    case EfiBadgingDisplayAttributeRightTop:
+      DestX = (SizeOfX - Width - CoordinateX);
+      DestY = CoordinateY;;
+      break;
+
+    case EfiBadgingDisplayAttributeCenterRight:
+      DestX = (SizeOfX - Width - CoordinateX);
+      DestY = (SizeOfY - Height) / 2;
+      break;
+
+    case EfiBadgingDisplayAttributeRightBottom:
+      DestX = (SizeOfX - Width - CoordinateX);
+      DestY = (SizeOfY - Height - CoordinateY);
+      break;
+
+    case EfiBadgingDisplayAttributeCenterBottom:
+      DestX = (SizeOfX - Width) / 2;
+      DestY = (SizeOfY - Height - CoordinateY);
+      break;
+
+    case EfiBadgingDisplayAttributeLeftBottom:
+      DestX = CoordinateX;
+      DestY = (SizeOfY - Height - CoordinateY);
+      break;
+
+    case EfiBadgingDisplayAttributeCenterLeft:
+      DestX = CoordinateX;
+      DestY = (SizeOfY - Height) / 2;
+      break;
+
+    case EfiBadgingDisplayAttributeCenter:
+      DestX = (SizeOfX - Width) / 2;
+      DestY = (SizeOfY - Height) / 2;
+      break;
+
+    case EfiBadgingDisplayAttributeCustomized:
+      DestX = (SizeOfX - Width) / 2;
+      DestY = ((SizeOfY * 382) / 1000) - Height / 2;
+      break;
+
+    default:
+      DestX = CoordinateX;
+      DestY = CoordinateY;
+      break;
+    }
+
+    if ((DestX >= 0) && (DestY >= 0)) {
+      if (GraphicsOutput != NULL) {
+        Status = GraphicsOutput->Blt (
+                            GraphicsOutput,
+                            Blt,
+                            EfiBltBufferToVideo,
+                            0,
+                            0,
+                            (UINTN) DestX,
+                            (UINTN) DestY,
+                            Width,
+                            Height,
+                            Width * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+                            );
+      } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {
+        Status = UgaDraw->Blt (
+                            UgaDraw,
+                            (EFI_UGA_PIXEL *) Blt,
+                            EfiUgaBltBufferToVideo,
+                            0,
+                            0,
+                            (UINTN) DestX,
+                            (UINTN) DestY,
+                            Width,
+                            Height,
+                            Width * sizeof (EFI_UGA_PIXEL)
+                            );
+      } else {
+        Status = EFI_UNSUPPORTED;
+      }
+
+      //
+      // Report displayed Logo information.
+      //
+      if (!EFI_ERROR (Status)) {
+        NumberOfLogos++;
+
+        if (LogoWidth == 0) {
+          //
+          // The first Logo.
+          //
+          LogoDestX = (UINTN) DestX;
+          LogoDestY = (UINTN) DestY;
+          LogoWidth = Width;
+          LogoHeight = Height;
+        } else {
+          //
+          // Merge new logo with old one.
+          //
+          NewDestX = MIN ((UINTN) DestX, LogoDestX);
+          NewDestY = MIN ((UINTN) DestY, LogoDestY);
+          NewWidth = MAX ((UINTN) DestX + Width, LogoDestX + LogoWidth) - NewDestX;
+          NewHeight = MAX ((UINTN) DestY + Height, LogoDestY + LogoHeight) - NewDestY;
+
+          LogoDestX = NewDestX;
+          LogoDestY = NewDestY;
+          LogoWidth = NewWidth;
+          LogoHeight = NewHeight;
+        }
+      }
+    }
+
+    FreePool (ImageData);
+
+    if (Badging == NULL) {
+      break;
+    }
+  }
+
+Done:
+  if (BootLogo == NULL || NumberOfLogos == 0) {
+    //
+    // No logo displayed.
+    //
+    if (Blt != NULL) {
+      FreePool (Blt);
+    }
+
+    return Status;
+  }
+
+  //
+  // Advertise displayed Logo information.
+  //
+  if (NumberOfLogos == 1) {
+    //
+    // Only one logo displayed, use its Blt buffer directly for BootLogo protocol.
+    //
+    LogoBlt = Blt;
+    Status = EFI_SUCCESS;
+  } else {
+    //
+    // More than one Logo displayed, get merged BltBuffer using VideoToBuffer operation.
+    //
+    if (Blt != NULL) {
+      FreePool (Blt);
+    }
+
+    //
+    // Ensure the LogoHeight * LogoWidth doesn't overflow
+    //
+    if (LogoHeight > DivU64x64Remainder ((UINTN) ~0, LogoWidth, NULL)) {
+      return EFI_UNSUPPORTED;
+    }
+    BufferSize = MultU64x64 (LogoWidth, LogoHeight);
+
+    //
+    // Ensure the BufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) doesn't overflow
+    //
+    if (BufferSize > DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
+      return EFI_UNSUPPORTED;
+    }
+
+    LogoBlt = AllocateZeroPool ((UINTN)BufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
+    if (LogoBlt == NULL) {
+      return EFI_OUT_OF_RESOURCES;
+    }
+
+    if (GraphicsOutput != NULL) {
+      Status = GraphicsOutput->Blt (
+                          GraphicsOutput,
+                          LogoBlt,
+                          EfiBltVideoToBltBuffer,
+                          LogoDestX,
+                          LogoDestY,
+                          0,
+                          0,
+                          LogoWidth,
+                          LogoHeight,
+                          LogoWidth * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+                          );
+    } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {
+      Status = UgaDraw->Blt (
+                          UgaDraw,
+                          (EFI_UGA_PIXEL *) LogoBlt,
+                          EfiUgaVideoToBltBuffer,
+                          LogoDestX,
+                          LogoDestY,
+                          0,
+                          0,
+                          LogoWidth,
+                          LogoHeight,
+                          LogoWidth * sizeof (EFI_UGA_PIXEL)
+                          );
+    } else {
+      Status = EFI_UNSUPPORTED;
+    }
+  }
+
+  if (!EFI_ERROR (Status)) {
+    BootLogo->SetBootLogo (BootLogo, LogoBlt, LogoDestX, LogoDestY, LogoWidth, LogoHeight);
+  }
+  FreePool (LogoBlt);
+
+  return Status;
+}
+
+/**
+  Use SystemTable Conout to turn on video based Simple Text Out consoles. The
+  Simple Text Out screens will now be synced up with all non video output devices
+
+  @retval EFI_SUCCESS     UGA devices are back in text mode and synced up.
+
+**/
+EFI_STATUS
+DisableQuietBoot (
+  VOID
+  )
+{
+
+  //
+  // Enable Cursor on Screen
+  //
+  gST->ConOut->EnableCursor (gST->ConOut, TRUE);
+  return EFI_SUCCESS;
+}
+
diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc
new file mode 100644
index 0000000..aac6b7f
--- /dev/null
+++ b/Platforms/Marvell/Armada/Armada.dsc.inc
@@ -0,0 +1,493 @@
+#Copyright (C) 2016 Marvell International Ltd.
+#
+#Marvell BSD License Option
+#
+#If you received this File from Marvell, you may opt to use, redistribute and/or
+#modify this File under the following licensing terms.
+#Redistribution and use in source and binary forms, with or without modification,
+#are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+[LibraryClasses.common]
+  ArmPlatformLib|OpenPlatformPkg/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
+  ComPhyLib|OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf
+  MppLib|OpenPlatformPkg/Platforms/Marvell/Library/MppLib/MppLib.inf
+  ParsePcdLib|OpenPlatformPkg/Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.inf
+  UtmiPhyLib|OpenPlatformPkg/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
+
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+# Basic utility libraries
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+
+# Basic UEFI services libraries
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+  # Assume everything is fixed at build. do not use runtime PCD feature
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+  # ARM Architectural Libraries
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+  # Serial port libraries
+  SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+  PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+
+  # Reset and Time libraries
+  RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
+  EfiResetSystemLib|OpenPlatformPkg/Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.inf
+
+  # Network support
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+
+  # These libraries are used by the dynamic EFI Shell commands
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+  # EBL Related Libraries
+  EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
+  EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+  EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+  EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+
+  #
+  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+  # in the debugger will show load and unload commands for symbols. You can cut and paste this
+  # into the command window to load symbols. We should be able to use a script to do this, but
+  # the version of RVD I have does not support scripts accessing system memory.
+  #
+  #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+  #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+  # SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+
+  # BDS Libraries
+  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
+[LibraryClasses.AARCH64]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.SEC]
+  DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
+  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+  # Add support for GCC stack protector
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+  #
+  # Control what commands are supported from the UI
+  # Turn these on and off to add features or save size
+  #
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+  # Use the Vector Table location in CpuDxe.
+  # We will not copy the Vector Table at PcdCpuVectorBaseAddress
+  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+  # If TRUE, Graphics Output Protocol will be installed on virtual
+  # handle created by ConsplitterDxe. It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+
+  # USB support
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsFixedAtBuild.common]
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Marvell"
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"MARVELL_EFI"
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|4
+
+  ## Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"Marvell>> "
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+
+  # Required for Intel BDS
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  # ARM Generic Interrupt Controller
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000
+
+  # ARM Architectural Timer Support
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000
+  gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+  # ARM SBSA Watchdog
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0xF0620000
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0xF0600000
+  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|34
+
+  # Serial
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xF0512000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|115200
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|200000000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4
+
+  # RamDisk
+  gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|64
+
+  # DEBUG_ASSERT_ENABLED       0x01
+  # DEBUG_PRINT_ENABLED        0x02
+  # DEBUG_CODE_ENABLED         0x04
+  # CLEAR_MEMORY_ENABLED       0x08
+  # ASSERT_BREAKPOINT_ENABLED  0x10
+  # ASSERT_DEADLOOP_ENABLED    0x20
+
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+
+  #  DEBUG_INIT      0x00000001  // Initialization
+  #  DEBUG_WARN      0x00000002  // Warnings
+  #  DEBUG_LOAD      0x00000004  // Load events
+  #  DEBUG_FS        0x00000008  // EFI File system
+  #  DEBUG_POOL      0x00000010  // Alloc & Free (pool)
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free (page)
+  #  DEBUG_INFO      0x00000040  // Informational debug messages
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE/SMM Dispatchers
+  #  DEBUG_VARIABLE  0x00000100  // Variable
+  #  DEBUG_BM        0x00000400  // Boot Manager
+  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+  #  DEBUG_NET       0x00004000  // SNP Driver
+  #  DEBUG_UNDI      0x00010000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // LoadFile
+  #  DEBUG_EVENT     0x00080000  // Event messages
+  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
+  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
+  #  DEBUG_VERBOSE   0x00400000  // Detailed debug messages that may
+  #                              // significantly impact boot performance
+  #  DEBUG_ERROR     0x80000000  // Error
+
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+!endif
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  # We want to use the Shell Libraries but don't want it to initialise
+  # automatically. We initialise the libraries when the command is called by the
+  # Shell.
+  gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+  # ARM Pcds
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+  gArmTokenSpaceGuid.PcdArmScr|0x531
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+  # PEI Phase modules
+  ArmPlatformPkg/PrePi/PeiMPCore.inf
+
+  # DXE
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  # Architectural Protocols DXE
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+  # Platform drivers
+  OpenPlatformPkg/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+  MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  OpenPlatformPkg/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
+  OpenPlatformPkg/Drivers/Spi/MvSpiDxe.inf
+  OpenPlatformPkg/Drivers/Spi/Devices/MvSpiFlash.inf
+
+  # Network support
+  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  OpenPlatformPkg/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
+  OpenPlatformPkg/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
+  OpenPlatformPkg/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
+
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  # PciEmulation
+  OpenPlatformPkg/Platforms/Marvell/PciEmulation/PciEmulation.inf
+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  # SCSI
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+  # SATA
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  OvmfPkg/SataControllerDxe/SataControllerDxe.inf
+
+  # USB
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  # SD/MMC
+  MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
+  MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
+  OpenPlatformPkg/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf
+
+  # Console packages
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Human interface:
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  # FAT filesystem + GPT/MBR partitioning
+  OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  # Application
+  EmbeddedPkg/Ebl/Ebl.inf
+
+  # Bds - Use Intel BDS
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+  # UEFI application (Shell Embedded Boot Loader)
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+      NULL|OpenPlatformPkg/Applications/EepromCmd/EepromCmd.inf
+      NULL|OpenPlatformPkg/Applications/SpiTool/SpiFlashCmd.inf
+      NULL|OpenPlatformPkg/Applications/FirmwareUpdate/FUpdate.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc
new file mode 100644
index 0000000..134ab71
--- /dev/null
+++ b/Platforms/Marvell/Armada/Armada70x0.dsc
@@ -0,0 +1,152 @@
+#Copyright (C) 2016 Marvell International Ltd.
+#
+#Marvell BSD License Option
+#
+#If you received this File from Marvell, you may opt to use, redistribute and/or
+#modify this File under the following licensing terms.
+#Redistribution and use in source and binary forms, with or without modification,
+#are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = Armada70x0
+  PLATFORM_GUID                  = f837e231-cfc7-4f56-9a0f-5b218d746ae3
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Marvell/Armada/Armada70x0.fdf
+
+!include Armada.dsc.inc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+  #MPP
+  gMarvellTokenSpaceGuid.PcdMppChipCount|2
+
+  # APN806-A0 MPP SET
+  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+  gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+  gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+  # CP110 MPP SET - Router configuration
+  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+  gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+  gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
+  gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+  # I2C
+  gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60 }
+  gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100"
+  gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 }
+  gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
+  gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+  gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+
+  #SPI
+  gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+  gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0x70
+  gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|3
+  gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536
+  gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256
+  gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18
+
+  #ComPhy
+  gMarvellTokenSpaceGuid.PcdComPhyChipCount|1
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000
+  gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4
+  gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110"
+
+  #UtmiPhy
+  gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420"
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444"
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000"
+  gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1"
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000"
+
+  #MDIO
+  gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200
+
+  #PHY
+  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x4, 0x4, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+  #NET
+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333
+  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0xf2130e00
+  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0x1000
+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 }
+  gMarvellTokenSpaceGuid.PcdPp2NumPorts|3
+  gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0xf2441000
+  gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000
+  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0xf212A200
+  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0xf2130f00
+  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0x1000
+
+  #PciEmulation
+  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+  gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
+  gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+
+  #ResetLib
+  gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084
+  gMarvellTokenSpaceGuid.PcdResetRegMask|0x1
+
+  #SATA
+  gMarvellTokenSpaceGuid.PcdSataBaseAddress|0xF2540000
diff --git a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.fdf b/Platforms/Marvell/Armada/Armada70x0.fdf
index 9728efd..10ad9f9 100644
--- a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.fdf
+++ b/Platforms/Marvell/Armada/Armada70x0.fdf
@@ -1,14 +1,13 @@
-# FLASH layout file for Beagle board.
 #
-# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
+#  Copyright (C) Marvell International Ltd. and its affiliates
 #
-#    This program and the accompanying materials
-#    are licensed and made available under the terms and conditions of the BSD License
-#    which accompanies this distribution. The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
 #
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #
 
 ################################################################################
@@ -25,13 +24,14 @@
 #
 ################################################################################
 
-
-[FD.BeagleBoard_EFI]
-BaseAddress   = 0x80008000|gArmTokenSpaceGuid.PcdFdBaseAddress  #The base address of the FLASH Device.
-Size          = 0x000B0000|gArmTokenSpaceGuid.PcdFdSize         #The size in bytes of the FLASH Device
+[FD.Armada70x0_EFI]
+BaseAddress   = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00400000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
 ErasePolarity = 1
-BlockSize     = 0x1
-NumBlocks     = 0xB0000
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0x400
 
 ################################################################################
 #
@@ -48,10 +48,12 @@ NumBlocks     = 0xB0000
 # RegionType <FV, DATA, or FILE>
 #
 ################################################################################
-0x00000000|0x000B0000
+
+0x00000000|0x000E6000
 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
+
 ################################################################################
 #
 # FV Section
@@ -63,8 +65,9 @@ FV = FVMAIN_COMPACT
 #
 ################################################################################
 
+# DXE phase firmware volume
 [FV.FvMain]
-BlockSize          = 0x1
+BlockSize          = 0x40
 NumBlocks          = 0         # This FV gets compressed so make it just big enough
 FvAlignment        = 8         # FV alignment and FV attributes setting.
 ERASE_POLARITY     = 1
@@ -82,104 +85,101 @@ READ_ENABLED_CAP   = TRUE
 READ_STATUS        = TRUE
 READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
-FvNameGuid         = d0dd3e90-343d-4cb3-8f69-772214989282
+FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
 
   INF MdeModulePkg/Core/Dxe/DxeMain.inf
 
-  #
   # PI DXE Drivers producing Architectural Protocols (EFI Services)
-  #
   INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
-
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
   INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
   INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF OpenPlatformPkg/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+  INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
+  INF OpenPlatformPkg/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
+  INF OpenPlatformPkg/Drivers/Spi/MvSpiDxe.inf
+  INF OpenPlatformPkg/Drivers/Spi/Devices/MvSpiFlash.inf
+
+  # Network support
+  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF OpenPlatformPkg/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
+  INF OpenPlatformPkg/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
+  INF OpenPlatformPkg/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
+
+  # PciEmulation
+  INF OpenPlatformPkg/Platforms/Marvell/PciEmulation/PciEmulation.inf
+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  # SCSI
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+  # SATA
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF OvmfPkg/SataControllerDxe/SataControllerDxe.inf
+
+  # USB
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
 
+  # SD/MMC
+  INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
+  INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
+  INF OpenPlatformPkg/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf
+
+  # Multiple Console IO support
   INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
   INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
   INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
-  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
   INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
 
-  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
-  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  # Human interface
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
 
-!if $(TARGET) == RELEASE
-  #
-  # Semi-hosting filesystem
-  #
-  INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
-!endif
-
-  #
-  # Nand Flash
-  #
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Flash/Flash.inf
-
-  #
-  # MMC/SD
-  #
-  INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.inf
-
-  #
-  # I2C
-  #
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.inf
-
-  #
-  # SoC Drivers
-  #
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Gpio/Gpio.inf
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/InterruptDxe/InterruptDxe.inf
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/TimerDxe/TimerDxe.inf
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
-
-  #
-  # Power IC
-  #
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.inf
-
-  #
   # FAT filesystem + GPT/MBR partitioning
-  #
+  INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
   INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
   INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   INF FatBinPkg/EnhancedFatDxe/Fat.inf
   INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
 
-  #
-  # USB Support
-  #
-
-  INF OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.inf
-
-  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
-  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
-  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+  # UEFI application (Shell Embedded Boot Loader)
+  INF EmbeddedPkg/Ebl/Ebl.inf
 
-  #
   # UEFI application (Shell Embedded Boot Loader)
-  #
-  INF ShellBinPkg/UefiShell/UefiShell.inf
+  INF ShellPkg/Application/Shell/Shell.inf
 
-  #
   # Bds
-  #
   INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-  INF ArmPlatformPkg/Bds/Bds.inf
-
-  # Legacy Linux Loader
-  INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
 
 
+# PEI phase firmware volume
 [FV.FVMAIN_COMPACT]
 FvAlignment        = 8
+FvForceRebase      = TRUE
 ERASE_POLARITY     = 1
 MEMORY_MAPPED      = TRUE
 STICKY_WRITE       = TRUE
@@ -196,7 +196,7 @@ READ_STATUS        = TRUE
 READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 
-  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
 
   FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
     SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
@@ -204,7 +204,6 @@ READ_LOCK_STATUS   = TRUE
     }
   }
 
-
 ################################################################################
 #
 # Rules are use with the [FV] section's module INF type to define
@@ -233,11 +232,18 @@ READ_LOCK_STATUS   = TRUE
 #
 ############################################################################
 
-[Rule.Common.SEC]
+[Rule.ARM.SEC]
   FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
     TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
   }
 
+# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
+# It is the reason 4K is used instead of 2K for the module alignment.
+[Rule.AARCH64.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
 [Rule.Common.PEI_CORE]
   FILE PEI_CORE = $(NAMED_GUID) {
     TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
@@ -247,7 +253,7 @@ READ_LOCK_STATUS   = TRUE
 [Rule.Common.PEIM]
   FILE PEIM = $(NAMED_GUID) {
      PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
-     PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
      UI       STRING="$(MODULE_NAME)" Optional
   }
 
@@ -266,7 +272,6 @@ READ_LOCK_STATUS   = TRUE
     UI       STRING="$(MODULE_NAME)" Optional
   }
 
-
 [Rule.Common.UEFI_DRIVER]
   FILE DRIVER = $(NAMED_GUID) {
     DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
@@ -274,6 +279,14 @@ READ_LOCK_STATUS   = TRUE
     UI           STRING="$(MODULE_NAME)" Optional
   }
 
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
 [Rule.Common.DXE_DRIVER]
   FILE DRIVER = $(NAMED_GUID) {
     DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
@@ -293,18 +306,3 @@ READ_LOCK_STATUS   = TRUE
     UI     STRING ="$(MODULE_NAME)" Optional
     PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
   }
-
-[Rule.Common.UEFI_DRIVER.BINARY]
-  FILE DRIVER = $(NAMED_GUID) {
-    DXE_DEPEX DXE_DEPEX Optional      |.depex
-    PE32      PE32                    |.efi
-    UI        STRING="$(MODULE_NAME)" Optional
-    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-  }
-
-[Rule.Common.UEFI_APPLICATION.BINARY]
-  FILE APPLICATION = $(NAMED_GUID) {
-    PE32      PE32                    |.efi
-    UI        STRING="$(MODULE_NAME)" Optional
-    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
-  }
diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 0000000..9265636
--- /dev/null
+++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,50 @@
+//Based on ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHelper.S
+//
+//  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//  Copyright (c) 2016, Marvell. All rights reserved.
+//
+//  This program and the accompanying materials are licensed and made available
+//  under the terms and conditions of the BSD License which accompanies this
+//  distribution. The full text of the license may be found at
+//  http://opensource.org/licenses/bsd-license.php
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+  ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #6
+  ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+  MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
+  ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+  MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
+  and   x0, x0, x1
+  MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
+  cmp   w0, w1
+  cset  x0, eq
+  ret
diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c
new file mode 100644
index 0000000..0ed310f
--- /dev/null
+++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c
@@ -0,0 +1,157 @@
+/**Based on ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.c
+*
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Marvell International Ltd. All rights reserved.
+*
+*  This program and the accompanying materials are licensed and made available
+*  under the terms and conditions of the BSD License which accompanies this
+*  distribution. The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/MppLib.h>
+#include <Library/MvComPhyLib.h>
+#include <Library/UtmiPhyLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+
+ARM_CORE_INFO mArmada7040MpCoreInfoTable[] = {
+  {
+    // Cluster 0, Core 0
+    0x0, 0x0,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 1
+    0x0, 0x1,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 2
+    0x0, 0x2,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (UINT64)0xFFFFFFFF
+  },
+  {
+    // Cluster 0, Core 3
+    0x0, 0x3,
+
+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (EFI_PHYSICAL_ADDRESS)0,
+    (UINT64)0xFFFFFFFF
+  }
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  if (!ArmPlatformIsPrimaryCore (MpId)) {
+    return RETURN_SUCCESS;
+  }
+
+  MvComPhyInit ();
+  UtmiPhyInit ();
+  MppInitialize ();
+  return RETURN_SUCCESS;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+  //TODO: Initialize DRAM controller here
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  if (ArmIsMpCore()) {
+    *CoreCount    = sizeof(mArmada7040MpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+    *ArmCoreTable = mArmada7040MpCoreInfoTable;
+    return EFI_SUCCESS;
+  } else {
+    return EFI_UNSUPPORTED;
+  }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  if (ArmIsMpCore()) {
+    *PpiListSize = sizeof(gPlatformPpiTable);
+    *PpiList = gPlatformPpiTable;
+  } else {
+    *PpiListSize = 0;
+    *PpiList = NULL;
+  }
+}
+
+
diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
new file mode 100644
index 0000000..23b17f0
--- /dev/null
+++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
@@ -0,0 +1,71 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Armada7040Lib
+  FILE_GUID                      = 3f29b642-4a49-4dfd-8f4a-205dd38432bb
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  ArmLib
+  ComPhyLib
+  DebugLib
+  MemoryAllocationLib
+  MppLib
+  UtmiPhyLib
+
+[Sources.common]
+  Armada70x0Lib.c
+  Armada70x0LibMem.c
+
+[Sources.AArch64]
+  AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
diff --git a/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
new file mode 100644
index 0000000..74c9956
--- /dev/null
+++ b/Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
@@ -0,0 +1,93 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+// The total number of descriptors, including the final "end-of-table" descriptor.
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+  Return the Virtual Memory Map of your platform
+
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+                                    Virtual Memory mapping. This array must be ended by a zero-filled
+                                    entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+  )
+{
+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
+  UINTN                         Index = 0;
+
+  ASSERT (VirtualMemoryMap != NULL);
+
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+  if (VirtualMemoryTable == NULL) {
+      return;
+  }
+
+  // DDR
+  VirtualMemoryTable[Index].PhysicalBase    = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdSystemMemoryBase);
+  VirtualMemoryTable[Index].Length          = PcdGet64 (PcdSystemMemorySize);
+  VirtualMemoryTable[Index].Attributes      = DDR_ATTRIBUTES_CACHED;
+
+  // Configuration space 0xF000_0000 - 0xFFFF_FFFF
+  VirtualMemoryTable[++Index].PhysicalBase  = 0xF0000000;
+  VirtualMemoryTable[Index].VirtualBase     = 0xF0000000;
+  VirtualMemoryTable[Index].Length          = 0x10000000;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+  // End of Table
+  VirtualMemoryTable[++Index].PhysicalBase  = 0;
+  VirtualMemoryTable[Index].VirtualBase     = 0;
+  VirtualMemoryTable[Index].Length          = 0;
+  VirtualMemoryTable[Index].Attributes      = 0;
+
+  ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+  *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platforms/Marvell/Include/Library/MppLib.h b/Platforms/Marvell/Include/Library/MppLib.h
new file mode 100644
index 0000000..77c6cdb
--- /dev/null
+++ b/Platforms/Marvell/Include/Library/MppLib.h
@@ -0,0 +1,42 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MPPLIB_H__
+#define __MPPLIB_H__
+
+EFI_STATUS
+MppInitialize (
+  );
+
+#endif
diff --git a/Platforms/Marvell/Include/Library/MvComPhyLib.h b/Platforms/Marvell/Include/Library/MvComPhyLib.h
new file mode 100644
index 0000000..6bd6243
--- /dev/null
+++ b/Platforms/Marvell/Include/Library/MvComPhyLib.h
@@ -0,0 +1,43 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MVCOMPHYLIB_H__
+#define __MVCOMPHYLIB_H__
+
+EFI_STATUS
+MvComPhyInit (
+  VOID
+  );
+
+#endif
diff --git a/Platforms/Marvell/Include/Library/ParsePcdLib.h b/Platforms/Marvell/Include/Library/ParsePcdLib.h
new file mode 100644
index 0000000..a255685
--- /dev/null
+++ b/Platforms/Marvell/Include/Library/ParsePcdLib.h
@@ -0,0 +1,46 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __PARSEPCDLIB_H__
+#define __PARSEPCDLIB_H__
+
+EFI_STATUS
+ParsePcdString (
+  IN  CHAR16 *PcdString,
+  IN  UINT8  Count,
+  OUT UINTN  *ValueTable,
+  OUT CHAR16 **StrTable
+  );
+
+#endif
diff --git a/Platforms/Marvell/Include/Library/UtmiPhyLib.h b/Platforms/Marvell/Include/Library/UtmiPhyLib.h
new file mode 100644
index 0000000..7c62cba
--- /dev/null
+++ b/Platforms/Marvell/Include/Library/UtmiPhyLib.h
@@ -0,0 +1,43 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __UTMIPHYLIB_H__
+#define __UTMIPHYLIB_H__
+
+EFI_STATUS
+UtmiPhyInit (
+  VOID
+  );
+
+#endif
diff --git a/Platforms/Marvell/Include/Protocol/Eeprom.h b/Platforms/Marvell/Include/Protocol/Eeprom.h
new file mode 100644
index 0000000..fbe4282
--- /dev/null
+++ b/Platforms/Marvell/Include/Protocol/Eeprom.h
@@ -0,0 +1,60 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MARVELL_EEPROM_H__
+#define __MARVELL_EEPROM_H__
+
+#define MARVELL_EEPROM_PROTOCOL_GUID { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
+
+typedef struct _MARVELL_EEPROM_PROTOCOL MARVELL_EEPROM_PROTOCOL;
+
+#define EEPROM_READ   0x1
+#define EEPROM_WRITE  0x0
+typedef
+EFI_STATUS
+(EFIAPI *EFI_EEPROM_TRANSFER) (
+  IN CONST MARVELL_EEPROM_PROTOCOL *This,
+  IN UINT16 Address,
+  IN UINT32 Length,
+  IN UINT8 *Buffer,
+  IN UINT8 Operation
+  );
+
+struct _MARVELL_EEPROM_PROTOCOL {
+  EFI_EEPROM_TRANSFER Transfer;
+  UINT32 Identifier;
+};
+
+extern EFI_GUID gMarvellEepromProtocolGuid;
+#endif
diff --git a/Platforms/Marvell/Include/Protocol/Mdio.h b/Platforms/Marvell/Include/Protocol/Mdio.h
new file mode 100644
index 0000000..10acad4
--- /dev/null
+++ b/Platforms/Marvell/Include/Protocol/Mdio.h
@@ -0,0 +1,66 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MDIO_H__
+#define __MDIO_H__
+
+#define MARVELL_MDIO_PROTOCOL_GUID { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
+
+typedef struct _MARVELL_MDIO_PROTOCOL MARVELL_MDIO_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *MARVELL_MDIO_READ) (
+  IN CONST MARVELL_MDIO_PROTOCOL *This,
+  IN UINT32 PhyAddr,
+  IN UINT32 RegOff,
+  IN UINT32 *Data
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *MARVELL_MDIO_WRITE) (
+  IN CONST MARVELL_MDIO_PROTOCOL *This,
+  IN UINT32 PhyAddr,
+  IN UINT32 RegOff,
+  IN UINT32 Data
+  );
+
+struct _MARVELL_MDIO_PROTOCOL {
+  MARVELL_MDIO_READ Read;
+  MARVELL_MDIO_WRITE Write;
+};
+
+extern EFI_GUID gMarvellMdioProtocolGuid;
+#endif
diff --git a/Platforms/Marvell/Include/Protocol/MvPhy.h b/Platforms/Marvell/Include/Protocol/MvPhy.h
new file mode 100644
index 0000000..43a9e0b
--- /dev/null
+++ b/Platforms/Marvell/Include/Protocol/MvPhy.h
@@ -0,0 +1,103 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __MV_PHY_H__
+#define __MV_PHY_H__
+
+#define MARVELL_PHY_PROTOCOL_GUID { 0x32f48a43, 0x37e3, 0x4acf, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }}
+
+typedef struct _MARVELL_PHY_PROTOCOL MARVELL_PHY_PROTOCOL;
+
+typedef enum {
+  PHY_CONNECTION_RGMII,
+  PHY_CONNECTION_RGMII_ID,
+  PHY_CONNECTION_RGMII_TXID,
+  PHY_CONNECTION_RGMII_RXID,
+  PHY_CONNECTION_SGMII,
+  PHY_CONNECTION_RTBI,
+  PHY_CONNECTION_XAUI,
+  PHY_CONNECTION_RXAUI
+} PHY_CONNECTION;
+
+typedef enum {
+  NO_SPEED,
+  SPEED_10,
+  SPEED_100,
+  SPEED_1000,
+  SPEED_2500,
+  SPEED_10000
+} PHY_SPEED;
+
+typedef struct {
+  UINT32          Addr;
+  BOOLEAN         LinkUp;
+  BOOLEAN         FullDuplex;
+  BOOLEAN         AutoNegotiation;
+  PHY_SPEED       Speed;
+  PHY_CONNECTION  Connection;
+} PHY_DEVICE;
+
+/*
+ * Before calling MARVELL_PHY_STATUS driver should request PHY_DEVICE structure by
+ * calling MARVELL_PHY_INIT. Pointer to that needs to be provided as an argument to
+ * MARVELL_PHY_STATUS.
+ */
+typedef
+EFI_STATUS
+(EFIAPI *MARVELL_PHY_STATUS) (
+  IN CONST MARVELL_PHY_PROTOCOL *This,
+  IN OUT PHY_DEVICE  *PhyDev
+  );
+
+/*
+ * MARVELL_PHY_INIT allocates PhyDev and provides driver with pointer via **PhyDev.
+ * After it becomes unnecessary, PhyDev should be freed by a driver (or it will
+ * get freed at ExitBootServices).
+ */
+typedef
+EFI_STATUS
+(EFIAPI *MARVELL_PHY_INIT) (
+  IN CONST MARVELL_PHY_PROTOCOL *This,
+  IN UINT32 PhyAddr,
+  IN PHY_CONNECTION PhyConnection,
+  IN OUT PHY_DEVICE **PhyDev
+  );
+
+struct _MARVELL_PHY_PROTOCOL {
+  MARVELL_PHY_STATUS Status;
+  MARVELL_PHY_INIT Init;
+};
+
+extern EFI_GUID gMarvellPhyProtocolGuid;
+#endif
diff --git a/Platforms/Marvell/Include/Protocol/Spi.h b/Platforms/Marvell/Include/Protocol/Spi.h
new file mode 100644
index 0000000..ae78a31
--- /dev/null
+++ b/Platforms/Marvell/Include/Protocol/Spi.h
@@ -0,0 +1,105 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __MARVELL_SPI_MASTER_PROTOCOL_H__
+#define __MARVELL_SPI_MASTER_PROTOCOL_H__
+
+extern EFI_GUID gMarvellSpiMasterProtocolGuid;
+
+typedef struct _MARVELL_SPI_MASTER_PROTOCOL MARVELL_SPI_MASTER_PROTOCOL;
+
+typedef enum {
+  SPI_MODE0, // CPOL = 0 & CPHA = 0
+  SPI_MODE1, // CPOL = 0 & CPHA = 1
+  SPI_MODE2, // CPOL = 1 & CPHA = 0
+  SPI_MODE3  // CPOL = 1 & CPHA = 1
+} SPI_MODE;
+
+typedef struct {
+  INTN Cs;
+  INTN MaxFreq;
+  SPI_MODE Mode;
+} SPI_DEVICE;
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_INIT) (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_TRANSFER) (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN SPI_DEVICE *Slave,
+  IN UINTN DataByteCount,
+  IN VOID *DataOut,
+  IN VOID *DataIn,
+  IN UINTN Flag
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI * MV_SPI_READ_WRITE) (
+  IN  MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN  SPI_DEVICE *Slave,
+  IN  UINT8 *Cmd,
+  IN  UINTN CmdSize,
+  IN  UINT8 *DataOut,
+  OUT UINT8 *DataIn,
+  IN  UINTN DataSize
+  );
+
+typedef
+SPI_DEVICE *
+(EFIAPI *MV_SPI_SETUP_DEVICE) (
+  IN MARVELL_SPI_MASTER_PROTOCOL *This,
+  IN UINTN    Cs,
+  IN SPI_MODE Mode
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_FREE_DEVICE) (
+  IN SPI_DEVICE *SpiDev
+  );
+
+struct _MARVELL_SPI_MASTER_PROTOCOL {
+  MV_SPI_INIT         Init;
+  MV_SPI_READ_WRITE   ReadWrite;
+  MV_SPI_TRANSFER     Transfer;
+  MV_SPI_SETUP_DEVICE SetupDevice;
+  MV_SPI_FREE_DEVICE  FreeDevice;
+};
+
+#endif // __MARVELL_SPI_MASTER_PROTOCOL_H__
diff --git a/Platforms/Marvell/Include/Protocol/SpiFlash.h b/Platforms/Marvell/Include/Protocol/SpiFlash.h
new file mode 100644
index 0000000..743bb87
--- /dev/null
+++ b/Platforms/Marvell/Include/Protocol/SpiFlash.h
@@ -0,0 +1,113 @@
+/*******************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __MV_SPI_FLASH__
+#define __MV_SPI_FLASH__
+
+#include <Protocol/Spi.h>
+
+#define CMD_READ_ID                     0x9f
+#define READ_STATUS_REG_CMD             0x0b
+#define CMD_WRITE_ENABLE                0x06
+#define CMD_FLAG_STATUS                 0x70
+#define CMD_WRITE_STATUS_REG            0x01
+#define CMD_READ_ARRAY_FAST             0x0b
+#define CMD_PAGE_PROGRAM                0x02
+#define CMD_BANK_WRITE                  0xc5
+#define CMD_ERASE_64K                   0xd8
+#define CMD_4B_ADDR_ENABLE              0xb7
+
+extern EFI_GUID gMarvellSpiFlashProtocolGuid;
+
+typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_FLASH_INIT) (
+  IN MARVELL_SPI_FLASH_PROTOCOL *This,
+  IN SPI_DEVICE             *SpiDev
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_FLASH_READ_ID) (
+  IN     SPI_DEVICE *SpiDev,
+  IN     UINT32     DataByteCount,
+  IN OUT UINT8      *Buffer
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_FLASH_READ) (
+  IN SPI_DEVICE *SpiDev,
+  IN UINT32     Address,
+  IN UINTN      DataByteCount,
+  IN VOID       *Buffer
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_FLASH_WRITE) (
+  IN SPI_DEVICE *SpiDev,
+  IN UINT32     Address,
+  IN UINTN      DataByteCount,
+  IN VOID       *Buffer
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_FLASH_ERASE) (
+  IN SPI_DEVICE *SpiDev,
+  IN UINTN      Address,
+  IN UINTN      DataByteCount
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *MV_SPI_FLASH_UPDATE) (
+  IN SPI_DEVICE *SpiDev,
+  IN UINT32     Address,
+  IN UINTN      DataByteCount,
+  IN UINT8      *Buffer
+  );
+
+struct _MARVELL_SPI_FLASH_PROTOCOL {
+  MV_SPI_FLASH_INIT    Init;
+  MV_SPI_FLASH_READ_ID ReadId;
+  MV_SPI_FLASH_READ    Read;
+  MV_SPI_FLASH_WRITE   Write;
+  MV_SPI_FLASH_ERASE   Erase;
+  MV_SPI_FLASH_UPDATE  Update;
+};
+
+#endif // __MV_SPI_FLASH__
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c
new file mode 100755
index 0000000..df8731d
--- /dev/null
+++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -0,0 +1,1047 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must Retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "ComPhyLib.h"
+
+#define SD_LANE_ADDR_WIDTH          0x1000
+#define HPIPE_ADDR_OFFSET           0x800
+#define COMPHY_ADDR_LANE_WIDTH      0x28
+#define SD_ADDR(base, Lane)         (base + SD_LANE_ADDR_WIDTH * Lane)
+#define HPIPE_ADDR(base, Lane)      (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
+#define COMPHY_ADDR(base, Lane)     (base + COMPHY_ADDR_LANE_WIDTH * Lane)
+
+/*
+ * For CP-110 we have 2 Selector registers "PHY Selectors"
+ * and " PIPE Selectors".
+ * PIPE selector include USB and PCIe options.
+ * PHY selector include the Ethernet and SATA options, every Ethernet option
+ * has different options, for example: serdes Lane2 had option Eth_port_0
+ * that include (SGMII0, XAUI0, RXAUI0, KR)
+ */
+COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {
+  /* Lane 0 */
+  {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1},
+    {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+  /* Lane 1 */
+  {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1},
+    {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+  /* Lane 2 */
+  {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1},
+    {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1},
+    {PHY_TYPE_SATA0, 0x4} } },
+  /* Lane 3 */
+  {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1},
+    {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1},
+    {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+  /* Lane 4 */
+  {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2},
+    {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1},
+    {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } },
+  /* Lane 5 */
+  {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1},
+    {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, {PHY_TYPE_XAUI3, 0x1},
+    {PHY_TYPE_SATA1, 0x4} } },
+};
+
+COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
+  /* Lane 0 */
+  {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE0, 0x4} } },
+  /* Lane 1 */
+  {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1},
+    {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE0, 0x4} } },
+  /* Lane 2 */
+  {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1},
+    {PHY_TYPE_PCIE0, 0x4} } },
+  /* Lane 3 */
+  {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1},
+    {PHY_TYPE_PCIE0, 0x4} } },
+  /* Lane 4 */
+  {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1},
+    {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE1, 0x4} } },
+  /* Lane 5 */
+  {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE2, 0x4} } },
+};
+
+STATIC
+VOID
+ComPhyPcieRFUConfiguration (
+  IN EFI_PHYSICAL_ADDRESS ComPhyAddr
+)
+{
+  UINT32 Mask, Data;
+
+  /* RFU configurations - hard reset ComPhy */
+  Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+  Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+  Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+  Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+  Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+  Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+  Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+  Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+  Mask |= COMMON_PHY_PHY_MODE_MASK;
+  Data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
+  RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
+
+  /* Release from hard reset */
+  Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+  Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+  Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+  Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+  RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
+
+  /* Wait 1ms - until band gap and ref clock ready */
+  MicroSecondDelay (1000);
+  MemoryFence ();
+}
+
+STATIC
+VOID
+ComPhyPciePhyConfiguration (
+  IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr
+)
+{
+  UINT32 Mask, Data, PcieClk = 0;
+
+  /* Set PIPE soft reset */
+  Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
+  Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
+
+  /* Set PHY Datapath width mode for V0 */
+  Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
+  Data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
+
+  /* Set Data bus width USB mode for V0 */
+  Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
+  Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
+
+  /* Set CORE_CLK output frequency for 250Mhz */
+  Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
+  Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
+  RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
+
+  /* Set PLL ready delay for 0x2 */
+  RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG,
+    0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
+    HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
+
+  /* Set PIPE mode interface to PCIe3 - 0x1 */
+  RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG,
+    0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET, HPIPE_CLK_SRC_HI_MODE_PIPE_MASK);
+
+  /* Config update polarity equalization */
+  RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG,
+    0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, HPIPE_CFG_UPDATE_POLARITY_MASK);
+
+  /* Set PIPE version 4 to mode enable */
+  RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG,
+    0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK);
+
+  /* Enable PIN clock 100M_125M */
+  Mask = HPIPE_MISC_CLK100M_125M_MASK;
+  Data = 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
+
+  /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */
+  Mask |= HPIPE_MISC_TXDCLK_2X_MASK;
+  Data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
+
+  /* Enable 500MHz Clock */
+  Mask |= HPIPE_MISC_CLK500_EN_MASK;
+  Data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
+
+  if (PcieClk) {
+    /* Set reference clock comes from group 1 */
+    Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
+    Data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
+  } else {
+    /* Set reference clock comes from group 2 */
+    Mask |= HPIPE_MISC_REFCLK_SEL_MASK;
+    Data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
+  }
+  RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask);
+
+  if (PcieClk) {
+    /* Set reference frequcency select - 0x2 for 25MHz*/
+    Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+    Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+  } else {
+    /* Set reference frequcency select - 0x0 for 100MHz*/
+    Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+    Data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+  }
+
+  /* Set PHY mode to PCIe */
+  Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+  Data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+  RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
+
+  /*
+   * Set the amount of time spent in the LoZ state - set
+   * for 0x7 only if the PCIe clock is output
+   */
+  if (PcieClk)
+    RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL,
+      0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
+      HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
+
+  /* Set Maximal PHY Generation Setting (8Gbps) */
+  Mask = HPIPE_INTERFACE_GEN_MAX_MASK;
+  Data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
+
+  /* Set Link Train Mode (Tx training control pins are used) */
+  Mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
+  Data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
+  RegSet (HpipeAddr + HPIPE_INTERFACE_REG, Data, Mask);
+
+  /* Set Idle_sync enable */
+  Mask = HPIPE_PCIE_IDLE_SYNC_MASK;
+  Data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
+
+  /* Select bits for PCIE Gen3(32bit) */
+  Mask |= HPIPE_PCIE_SEL_BITS_MASK;
+  Data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
+  RegSet (HpipeAddr + HPIPE_PCIE_REG0, Data, Mask);
+
+  /* Enable Tx_adapt_g1 */
+  Mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
+  Data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
+
+  /* Enable Tx_adapt_gn1 */
+  Mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
+  Data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
+
+  /* Disable Tx_adapt_g0 */
+  Mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
+  Data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
+  RegSet (HpipeAddr + HPIPE_TX_TRAIN_CTRL_REG, Data, Mask);
+
+  /* Set reg_tx_train_chk_init */
+  Mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
+  Data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
+
+  /* Enable TX_COE_FM_PIN_PCIE3_EN */
+  Mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
+  Data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
+  RegSet (HpipeAddr + HPIPE_TX_TRAIN_REG, Data, Mask);
+}
+
+STATIC
+VOID
+ComPhyPciePhyPowerUp (
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr
+)
+{
+  /* Release from PIPE soft reset */
+  RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG,
+    0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
+    HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
+
+  /* Wait 15ms - for ComPhy calibration done */
+  MicroSecondDelay (15000);
+  MemoryFence ();
+}
+
+STATIC
+EFI_STATUS
+ComPhyPcieCheckPll (
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr
+)
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  UINT32 Data;
+
+  /* Read Lane status */
+  Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG);
+  if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
+    DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
+      HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
+    DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n"));
+    Status = EFI_D_ERROR;
+  }
+
+  return Status;
+}
+
+STATIC
+EFI_STATUS
+ComPhyPciePowerUp (
+  IN UINT32 Lane,
+  IN UINT32 PcieBy4,
+  IN EFI_PHYSICAL_ADDRESS HpipeBase,
+  IN EFI_PHYSICAL_ADDRESS ComPhyBase
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
+  EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
+
+  ComPhyPcieRFUConfiguration (ComPhyAddr);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
+
+  ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
+
+  ComPhyPciePhyPowerUp (HpipeAddr);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
+
+  Status = ComPhyPcieCheckPll (HpipeAddr);
+
+  return Status;
+}
+
+STATIC
+VOID
+ComPhyUsb3RFUConfiguration (
+  IN EFI_PHYSICAL_ADDRESS ComPhyAddr
+)
+{
+  UINT32 Mask, Data;
+
+  /* RFU configurations - hard reset ComPhy */
+  Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+  Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+  Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+  Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+  Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+  Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+  Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+  Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+  Mask |= COMMON_PHY_PHY_MODE_MASK;
+  Data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
+  RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
+
+  /* Release from hard reset */
+  Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+  Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+  Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+  Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+  RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
+
+  /* Wait 1ms - until band gap and ref clock ready */
+  MicroSecondDelay (1000);
+  MemoryFence ();
+}
+
+STATIC
+VOID
+ComPhyUsb3PhyConfiguration (
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr
+)
+{
+  UINT32 Mask, Data;
+
+  /* Set PIPE soft reset */
+  Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
+  Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
+
+  /* Set PHY Datapath width mode for V0 */
+  Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
+  Data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
+
+  /* Set Data bus width USB mode for V0 */
+  Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
+  Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
+
+  /* Set CORE_CLK output frequency for 250Mhz */
+  Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
+  Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
+  RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask);
+
+  /* Set PLL ready delay for 0x2 */
+  RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG,
+    0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
+    HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
+
+  /* Set reference clock to come from group 1 - 25Mhz */
+  RegSet (HpipeAddr + HPIPE_MISC_REG, 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
+    HPIPE_MISC_REFCLK_SEL_MASK);
+
+  /* Set reference frequcency select - 0x2 */
+  Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+  Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+
+  /* Set PHY mode to USB - 0x5 */
+  Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+  Data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+  RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
+
+  /* Set the amount of time spent in the LoZ state - set for 0x7 */
+  RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL,
+    0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
+    HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
+
+  /* Set max PHY generation setting - 5Gbps */
+  RegSet (HpipeAddr + HPIPE_INTERFACE_REG,
+    0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK);
+
+  /* Set select Data width 20Bit (SEL_BITS[2:0]) */
+  RegSet (HpipeAddr + HPIPE_LOOPBACK_REG,
+    0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
+}
+
+STATIC
+VOID
+ComPhyUsb3SetAnalogParameters (
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr
+)
+{
+  UINT32 Data, Mask;
+
+  /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
+  Mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
+  Data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
+
+  /* Set Override PHY DFE control pins for 0x1 */
+  Mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
+  Data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
+
+  /* Set Spread Spectrum Clock Enable fot 0x1 */
+  Mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
+  Data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
+  RegSet (HpipeAddr + HPIPE_LANE_CFG4_REG, Data, Mask);
+}
+
+STATIC
+UINTN
+ComphyUsb3PowerUp (
+  UINT32 Lane,
+  EFI_PHYSICAL_ADDRESS HpipeBase,
+  EFI_PHYSICAL_ADDRESS ComPhyBase
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  UINT32 Data;
+  EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
+  EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
+
+  ComPhyUsb3RFUConfiguration (ComPhyAddr);
+
+  /* Start ComPhy Configuration */
+  DEBUG((DEBUG_INFO, "stage: Comphy configuration\n"));
+
+  ComPhyUsb3PhyConfiguration (HpipeAddr);
+
+  /* Start analog paramters from ETP(HW) */
+  DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));
+
+  ComPhyUsb3SetAnalogParameters (HpipeAddr);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy power up\n"));
+
+  /* Release from PIPE soft reset */
+  RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG,
+    0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
+    HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
+
+  /* Wait 15ms - for ComPhy calibration done */
+  MicroSecondDelay (15000);
+  MemoryFence ();
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
+
+  /* Read Lane status */
+  Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG);
+  if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) {
+    DEBUG((DEBUG_ERROR, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n"));
+    Status = EFI_D_ERROR;
+  }
+
+  return Status;
+}
+
+STATIC
+UINT32
+PollingWithTimeout (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT32 Val,
+  IN UINT32 Mask,
+  IN UINT64 Usec_timeout
+  )
+{
+  UINT32 Data;
+
+  do {
+    MicroSecondDelay(1);
+    Data = MmioRead32(Addr) & Mask;
+  } while (Data != Val  && --Usec_timeout > 0);
+
+  if (Usec_timeout == 0)
+    return Data;
+  return 0;
+}
+
+STATIC
+VOID
+ComPhySataMacPowerDown (
+  IN EFI_PHYSICAL_ADDRESS SataBase
+)
+{
+  UINT32 Mask, Data;
+
+  /*
+   * MAC configuration - power down ComPhy
+   * Use indirect address for vendor specific SATA control register
+   */
+  RegSet (SataBase + SATA3_VENDOR_ADDRESS,
+    SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, SATA3_VENDOR_ADDR_MASK);
+
+  /* SATA 0 power down */
+  Mask = SATA3_CTRL_SATA0_PD_MASK;
+  Data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
+
+  /* SATA 1 power down */
+  Mask |= SATA3_CTRL_SATA1_PD_MASK;
+  Data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
+
+  /* SATA SSU disable */
+  Mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
+  Data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
+
+  /* SATA port 1 disable */
+  Mask |= SATA3_CTRL_SATA_SSU_MASK;
+  Data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
+  RegSet (SataBase + SATA3_VENDOR_DATA, Data, Mask);
+}
+
+STATIC
+VOID
+ComPhySataRFUConfiguration (
+  IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
+  IN EFI_PHYSICAL_ADDRESS SdIpAddr
+)
+{
+  UINT32 Mask, Data;
+
+  /* RFU configurations - hard reset ComPhy */
+  Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+  Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+  Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+  Data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+  Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
+  Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
+  Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
+  Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
+  RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
+
+  /* Set select Data  width 40Bit - SATA mode only */
+  RegSet (ComPhyAddr + COMMON_PHY_CFG6_REG,
+    0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, COMMON_PHY_CFG6_IF_40_SEL_MASK);
+
+  /* Release from hard reset in SD external */
+  Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+  Data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+  Data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
+
+  /* Wait 1ms - until band gap and ref clock ready */
+  MicroSecondDelay (1000);
+  MemoryFence ();
+}
+
+STATIC
+VOID
+ComPhySataPhyConfiguration (
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr
+)
+{
+  UINT32 Mask, Data;
+
+  /* Set reference clock to comes from group 1 - choose 25Mhz */
+  RegSet (HpipeAddr + HPIPE_MISC_REG,
+    0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, HPIPE_MISC_REFCLK_SEL_MASK);
+
+  /* Reference frequency select set 1 (for SATA = 25Mhz) */
+  Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+  Data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+
+  /* PHY mode select (set SATA = 0x0 */
+  Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+  Data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+  RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
+
+  /* Set max PHY generation setting - 6Gbps */
+  RegSet (HpipeAddr + HPIPE_INTERFACE_REG,
+    0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK);
+
+  /* Set select Data  width 40Bit (SEL_BITS[2:0]) */
+  RegSet (HpipeAddr + HPIPE_LOOPBACK_REG,
+    0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
+}
+
+STATIC
+VOID
+ComPhySataSetAnalogParameters (
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr
+)
+{
+  /* DFE reset sequence */
+  RegSet (HpipeAddr + HPIPE_PWR_CTR_REG,
+    0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK);
+  RegSet (HpipeAddr + HPIPE_PWR_CTR_REG,
+    0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK);
+
+  /* SW reset for interupt logic */
+  RegSet (HpipeAddr + HPIPE_PWR_CTR_REG,
+    0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK);
+  RegSet (HpipeAddr + HPIPE_PWR_CTR_REG,
+    0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK);
+}
+
+STATIC
+VOID
+ComPhySataPhyPowerUp (
+  IN EFI_PHYSICAL_ADDRESS SataBase
+)
+{
+  UINT32 Data, Mask;
+
+  /*
+   * MAC configuration - power up ComPhy - power up PLL/TX/RX
+   * Use indirect address for vendor specific SATA control register
+   */
+  RegSet (SataBase + SATA3_VENDOR_ADDRESS,
+    SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, SATA3_VENDOR_ADDR_MASK);
+
+  /* SATA 0 power up */
+  Mask = SATA3_CTRL_SATA0_PD_MASK;
+  Data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
+
+  /* SATA 1 power up */
+  Mask |= SATA3_CTRL_SATA1_PD_MASK;
+  Data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
+
+  /* SATA SSU enable */
+  Mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
+  Data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
+
+  /* SATA port 1 enable */
+  Mask |= SATA3_CTRL_SATA_SSU_MASK;
+  Data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
+  RegSet (SataBase + SATA3_VENDOR_DATA, Data, Mask);
+
+  /* MBUS request size and interface select register */
+  RegSet (SataBase + SATA3_VENDOR_ADDRESS,
+    SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
+      SATA3_VENDOR_ADDR_MASK);
+
+  /* Mbus regret enable */
+  RegSet (SataBase + SATA3_VENDOR_DATA, 0x1 << SATA_MBUS_REGRET_EN_OFFSET,
+    SATA_MBUS_REGRET_EN_MASK);
+}
+
+STATIC
+EFI_STATUS
+ComPhySataCheckPll (
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr,
+  IN EFI_PHYSICAL_ADDRESS SdIpAddr
+)
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  UINT32 Data,Mask;
+  IN EFI_PHYSICAL_ADDRESS Addr;
+
+  Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
+  Data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & SD_EXTERNAL_STATUS0_PLL_RX_MASK;
+  Mask = Data;
+  Data =  PollingWithTimeout (Addr, Data, Mask, 15000);
+
+  if (Data != 0) {
+    DEBUG((DEBUG_INFO, "ComPhy: Read from reg = %p - value = 0x%x\n",
+      HpipeAddr + HPIPE_LANE_STATUS0_REG, Data));
+    DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n",
+      (Data & SD_EXTERNAL_STATUS0_PLL_TX_MASK),
+      (Data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)));
+    Status = EFI_D_ERROR;
+  }
+
+  return Status;
+}
+
+STATIC
+UINTN
+ComPhySataPowerUp (
+  IN UINT32 Lane,
+  IN EFI_PHYSICAL_ADDRESS HpipeBase,
+  IN EFI_PHYSICAL_ADDRESS ComPhyBase
+  )
+{
+  EFI_STATUS Status;
+  EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
+  EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
+  EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
+  EFI_PHYSICAL_ADDRESS SataBase;
+
+  SataBase = PcdGet32 (PcdSataBaseAddress);
+  if (SataBase == 0) {
+    DEBUG((DEBUG_INFO, "ComPhy: SATA address not defined\n"));
+    return EFI_D_ERROR;
+  }
+
+  DEBUG((DEBUG_INFO, "ComPhySataPowerUp: stage: MAC configuration - power down ComPhy\n"));
+
+  ComPhySataMacPowerDown (SataBase);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
+
+  ComPhySataRFUConfiguration (ComPhyAddr, SdIpAddr);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy configuration\n"));
+
+  ComPhySataPhyConfiguration (HpipeAddr);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));
+
+  ComPhySataSetAnalogParameters (HpipeAddr);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n"));
+
+  ComPhySataPhyPowerUp (SataBase);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n"));
+
+  Status = ComPhySataCheckPll (HpipeAddr, SdIpAddr);
+
+  return Status;
+}
+
+STATIC
+VOID
+ComPhySgmiiRFUConfiguration (
+  IN EFI_PHYSICAL_ADDRESS ComPhyAddr,
+  IN EFI_PHYSICAL_ADDRESS SdIpAddr,
+  IN UINT32 SgmiiSpeed
+)
+{
+  UINT32 Mask, Data;
+
+  Mask = COMMON_PHY_CFG1_PWR_UP_MASK;
+  Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
+  Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
+  Data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
+  RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask);
+
+  /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
+  Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
+  Data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
+  Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
+  if (SgmiiSpeed == PHY_SPEED_1_25G) {
+    Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
+    Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
+  } else {
+    /* 3.125G */
+    Data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
+    Data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
+  }
+  Mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
+  Data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
+  Data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
+  Data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
+  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, Data, Mask);
+
+  /* Release from hard reset */
+  Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+  Data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+  Data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
+  Data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
+  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
+
+  /* Release from hard reset */
+  Mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
+  Data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
+  Data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+  RegSet (SdIpAddr+ SD_EXTERNAL_CONFIG1_REG, Data, Mask);
+
+  /* Wait 1ms - until band gap and ref clock ready */
+  MicroSecondDelay (1000);
+  MemoryFence ();
+}
+
+STATIC
+VOID
+ComPhySgmiiPhyConfiguration (
+  IN EFI_PHYSICAL_ADDRESS HpipeAddr
+)
+{
+  UINT32 Mask, Data;
+
+  /* Set reference clock */
+  Mask = HPIPE_MISC_REFCLK_SEL_MASK;
+  Data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
+  RegSet (HpipeAddr + HPIPE_MISC_REG, Data, Mask);
+
+  /* Power and PLL Control */
+  Mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
+  Data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
+  Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
+  Data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
+  RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask);
+
+  /* Loopback register */
+  Mask = HPIPE_LOOPBACK_SEL_MASK;
+  Data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
+  RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, Data, Mask);
+
+  /* Rx control 1 */
+  Mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
+  Data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
+  Mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
+  Data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
+  RegSet (HpipeAddr + HPIPE_RX_CONTROL_1_REG, Data, Mask);
+
+  /* DTL Control */
+  Mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
+  Data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
+  RegSet (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, Data, Mask);
+}
+
+STATIC
+EFI_STATUS
+ComPhySgmiiRFUPowerUp (
+  IN EFI_PHYSICAL_ADDRESS SdIpAddr
+)
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  UINT32 Mask, Data;
+  EFI_PHYSICAL_ADDRESS Addr;
+
+  /* SerDes External Configuration */
+  Mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
+  Data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
+  Data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
+  Data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
+  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG0_REG, Data, Mask);
+
+  /* Check PLL rx & tx ready */
+  Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
+  Data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | SD_EXTERNAL_STATUS0_PLL_TX_MASK;
+  Mask = Data;
+  Data = PollingWithTimeout (Addr, Data, Mask, 15000);
+  if (Data != 0) {
+    DEBUG((DEBUG_ERROR, "ComPhy: Read from reg = %p - value = 0x%x\n",
+      SdIpAddr + SD_EXTERNAL_STATUS0_REG, Data));
+    DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
+      (Data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
+      (Data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)));
+    Status = EFI_D_ERROR;
+  }
+
+  /* RX init */
+  Mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
+  Data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
+  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
+
+  /* Check that RX init done */
+  Addr = SdIpAddr + SD_EXTERNAL_STATUS0_REG;
+  Data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
+  Mask = Data;
+  Data = PollingWithTimeout (Addr, Data, Mask, 100);
+  if (Data != 0) {
+    DEBUG((DEBUG_ERROR, "ComPhy: Read from reg = %p - value = 0x%x\n",
+      SdIpAddr + SD_EXTERNAL_STATUS0_REG, Data));
+    DEBUG((DEBUG_ERROR, "ComPhy: SD_EXTERNAL_STATUS0_RX_INIT is 0\n"));
+    Status = EFI_D_ERROR;
+  }
+  Mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
+  Data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
+  Mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
+  Data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
+  RegSet (SdIpAddr + SD_EXTERNAL_CONFIG1_REG, Data, Mask);
+
+  return Status;
+}
+
+STATIC
+UINTN
+ComPhySgmiiPowerUp (
+  IN UINT32 Lane,
+  IN UINT32 SgmiiSpeed,
+  IN EFI_PHYSICAL_ADDRESS HpipeBase,
+  IN EFI_PHYSICAL_ADDRESS ComPhyBase
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane);
+  EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane);
+  EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n"));
+
+  ComPhySgmiiRFUConfiguration (ComPhyAddr, SdIpAddr, SgmiiSpeed);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n"));
+
+  ComPhySgmiiPhyConfiguration (HpipeAddr);
+
+  /* Set analog paramters from ETP(HW) - for now use the default data */
+  DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n"));
+
+  RegSet (HpipeAddr + HPIPE_G1_SET_0_REG,
+    0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
+
+  DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n"));
+
+  Status = ComPhySgmiiRFUPowerUp (SdIpAddr);
+
+  return Status;
+}
+
+STATIC
+VOID
+ComPhyMuxCp110 (
+  IN CHIP_COMPHY_CONFIG *PtrChipCfg,
+  IN COMPHY_MAP *SerdesMap
+  )
+{
+  EFI_PHYSICAL_ADDRESS ComPhyBaseAddr;
+  COMPHY_MAP ComPhyMapPipeData[MAX_LANE_OPTIONS];
+  COMPHY_MAP ComPhyMapPhyData[MAX_LANE_OPTIONS];
+  UINT32 Lane, ComPhyMaxCount;
+
+  ComPhyMaxCount = PtrChipCfg->LanesCount;
+  ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
+
+  /*
+   * Copy the SerDes map configuration for PIPE map and PHY map.
+   * The ComPhyMuxInit modifies the Type of the Lane if the Type is not valid.
+   * Because we have 2 selectors, run the ComPhyMuxInit twice and after
+   * that, update the original SerdesMap.
+   */
+  for (Lane = 0; Lane < ComPhyMaxCount; Lane++) {
+    ComPhyMapPipeData[Lane].Type = SerdesMap[Lane].Type;
+    ComPhyMapPipeData[Lane].Speed = SerdesMap[Lane].Speed;
+    ComPhyMapPhyData[Lane].Type = SerdesMap[Lane].Type;
+    ComPhyMapPhyData[Lane].Speed = SerdesMap[Lane].Speed;
+  }
+  PtrChipCfg->MuxData = Cp110ComPhyMuxData;
+  ComPhyMuxInit(PtrChipCfg, ComPhyMapPhyData, ComPhyBaseAddr +
+    COMMON_SELECTOR_PHY_OFFSET);
+
+  PtrChipCfg->MuxData = Cp110ComPhyPipeMuxData;
+  ComPhyMuxInit(PtrChipCfg, ComPhyMapPipeData, ComPhyBaseAddr +
+    COMMON_SELECTOR_PIPE_OFFSET);
+
+  /* Fix the Type after check the PHY and PIPE configuration */
+  for (Lane = 0; Lane < ComPhyMaxCount; Lane++)
+    if ((ComPhyMapPipeData[Lane].Type == PHY_TYPE_UNCONNECTED) &&
+        (ComPhyMapPhyData[Lane].Type == PHY_TYPE_UNCONNECTED))
+      SerdesMap[Lane].Type = PHY_TYPE_UNCONNECTED;
+}
+
+EFI_STATUS
+ComPhyCp110Init (
+  IN CHIP_COMPHY_CONFIG *PtrChipCfg
+  )
+{
+  EFI_STATUS Status;
+  COMPHY_MAP *PtrComPhyMap, *SerdesMap;
+  EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr;
+  UINT32 ComPhyMaxCount, Lane;
+  UINT32 PcieBy4 = 1; // Indicating if first 4 lanes set to PCIE
+
+  ComPhyMaxCount = PtrChipCfg->LanesCount;
+  ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
+  HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr;
+  SerdesMap = PtrChipCfg->MapData;
+
+  /* Config Comphy mux configuration */
+  ComPhyMuxCp110(PtrChipCfg, SerdesMap);
+
+  /* Check if the first 4 Lanes configured as By-4 */
+  for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
+    if (PtrComPhyMap->Type != PHY_TYPE_PCIE0) {
+      PcieBy4 = 0;
+      break;
+    }
+  }
+
+  for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount;
+       Lane++, PtrComPhyMap++) {
+    DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane));
+    DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type));
+    switch (PtrComPhyMap->Type) {
+    case PHY_TYPE_UNCONNECTED:
+      continue;
+      break;
+    case PHY_TYPE_PCIE0:
+    case PHY_TYPE_PCIE1:
+    case PHY_TYPE_PCIE2:
+    case PHY_TYPE_PCIE3:
+      Status = ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBaseAddr);
+      break;
+    case PHY_TYPE_SATA0:
+    case PHY_TYPE_SATA1:
+    case PHY_TYPE_SATA2:
+    case PHY_TYPE_SATA3:
+      Status = ComPhySataPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);
+      break;
+    case PHY_TYPE_USB3_HOST0:
+    case PHY_TYPE_USB3_HOST1:
+      Status = ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);
+      break;
+    case PHY_TYPE_SGMII0:
+    case PHY_TYPE_SGMII1:
+    case PHY_TYPE_SGMII2:
+    case PHY_TYPE_SGMII3:
+      Status = ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAddr,
+        ComPhyBaseAddr);
+      break;
+    default:
+      DEBUG((DEBUG_ERROR, "Unknown SerDes Type, skip initialize SerDes %d\n",
+        Lane));
+      break;
+    }
+    if (EFI_ERROR(Status))
+      DEBUG((DEBUG_ERROR, "PLL is not locked - Failed to initialize Lane %d\n",
+        Lane));
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c
new file mode 100644
index 0000000..1b45bb7
--- /dev/null
+++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c
@@ -0,0 +1,288 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "ComPhyLib.h"
+
+CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2",
+                           L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3",
+                           L"SGMII0", L"SGMII1", L"SGMII2", L"SGMII3",
+                           L"QSGMII", L"USB3_HOST0", L"USB3_HOST1",
+                           L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2",
+                           L"XAUI3", L"RXAUI0", L"RXAUI1", L"KR"};
+
+CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps",
+                                L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps",
+                                L"6 Gbps", L"6.25 Gbps", L"10.31 Gbps"};
+
+CHIP_COMPHY_CONFIG ChipCfgTbl[] = {
+  {
+    .ChipType = L"Cp110",
+    .Init = ComPhyCp110Init
+  }
+};
+
+VOID
+RegSet (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT32 Data,
+  IN UINT32 Mask
+  )
+{
+  DEBUG((DEBUG_INFO, "Write to address = %10x, data = %10x (mask = %10x)"
+    "- ", Addr, Data, Mask));
+  DEBUG((DEBUG_INFO, "old value = %10x ==> ", MmioRead32 (Addr)));
+  RegSetSilent (Addr, Data, Mask);
+  DEBUG((DEBUG_INFO, "new value %10x\n", MmioRead32 (Addr)));
+}
+
+VOID
+RegSetSilent (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT32 Data,
+  IN UINT32 Mask
+  )
+{
+  UINT32 RegData;
+
+  RegData = MmioRead32 (Addr);
+  RegData &= ~Mask;
+  RegData |= Data;
+  MmioWrite32 (Addr, RegData);
+}
+
+VOID
+RegSet16 (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT16 Data,
+  IN UINT16 Mask
+  )
+{
+  DEBUG((DEBUG_INFO, "Write to address = %#010lx, Data = %#06x (mask = %#06x)"
+    "- ", Addr, Data, Mask));
+  DEBUG((DEBUG_INFO, "old value = %#06x ==> ", MmioRead16 (Addr)));
+  RegSetSilent16 (Addr, Data, Mask);
+  DEBUG((DEBUG_INFO, "new value %#06x\n", MmioRead16 (Addr)));
+}
+
+VOID
+RegSetSilent16(
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT16 Data,
+  IN UINT16 Mask
+  )
+{
+  UINT16 RegData;
+  RegData = MmioRead16(Addr);
+  RegData &= ~Mask;
+  RegData |= Data;
+  MmioWrite16 (Addr, RegData);
+}
+
+/* This function returns enum with SerDesType */
+UINT32
+ParseSerdesTypeString (
+  CHAR16* String
+  )
+{
+  UINT32 i;
+
+  if (String == NULL)
+    return PHY_TYPE_INVALID;
+
+  for (i = 0; i < PHY_TYPE_MAX; i++) {
+    if (StrCmp (String, TypeStringTable[i]) == 0) {
+      return i;
+    }
+  }
+
+  /* PCD string doesn't match any supported SerDes Type */
+  return PHY_TYPE_INVALID;
+}
+
+/* This function converts SerDes speed in MHz to enum with SerDesSpeed */
+UINT32
+ParseSerdesSpeed (
+  UINT32 Value
+  )
+{
+  UINT32 i;
+  UINT32 ValueTable [] = {0, 1250, 1500, 2500, 3000, 3125,
+                          5000, 6000, 6250, 10310};
+
+  for (i = 0; i < 10; i++) {
+    if (Value == ValueTable[i]) {
+      return i;
+    }
+  }
+
+  /* PCD SerDes speed value doesn't match any supported SerDes speed */
+  return PHY_SPEED_INVALID;
+}
+
+CHAR16 *
+GetTypeString (
+  UINT32 Type
+  )
+{
+
+  if (Type < 0 || Type > PHY_TYPE_MAX) {
+    return L"invalid";
+  }
+
+  return TypeStringTable[Type];
+}
+
+CHAR16 *
+GetSpeedString (
+  UINT32 Speed
+  )
+{
+
+  if (Speed < 0 || Speed > 10) {
+    return L"invalid";
+  }
+
+  return SpeedStringTable[Speed];
+}
+
+VOID
+ComPhyPrint (
+  IN CHIP_COMPHY_CONFIG *PtrChipCfg
+  )
+{
+  UINT32 Lane;
+  CHAR16 *SpeedStr, *TypeStr;
+
+  for (Lane = 0; Lane < PtrChipCfg->LanesCount; Lane++) {
+    SpeedStr = GetSpeedString(PtrChipCfg->MapData[Lane].Speed);
+    TypeStr = GetTypeString(PtrChipCfg->MapData[Lane].Type);
+    DEBUG((DEBUG_ERROR, "Comphy-%d: %-13s %-10s\n", Lane, TypeStr, SpeedStr));
+  }
+
+  DEBUG((DEBUG_ERROR, "\n"));
+}
+
+EFI_STATUS
+GetChipComPhyInit (
+  IN CHIP_COMPHY_CONFIG *PtrChipCfg
+  )
+{
+  UINTN i, TblSize;
+
+
+  TblSize = sizeof(ChipCfgTbl) / sizeof(ChipCfgTbl[0]);
+
+  for (i = 0; i < TblSize ; i++) {
+    if (StrCmp (PtrChipCfg->ChipType, ChipCfgTbl[i].ChipType) == 0) {
+      PtrChipCfg->Init = ChipCfgTbl[i].Init;
+      return EFI_SUCCESS;
+    }
+  }
+
+  DEBUG((DEBUG_ERROR, "ComPhy: Empty ChipType string\n"));
+  return EFI_D_ERROR;
+}
+
+STATIC
+VOID
+InitComPhyConfig (
+  IN  OUT  CHIP_COMPHY_CONFIG *ChipConfig,
+  IN  OUT  PCD_LANE_MAP       *LaneData
+  )
+{
+  /*
+   * Below macro contains variable name concatenation (used to form PCD's name)
+   * and that's why invoking it cannot be automated, e.g. using for loop.
+   * Currently up to 4 ComPhys might be configured.
+   */
+  GetComPhyPcd(ChipConfig, LaneData, 0);
+  GetComPhyPcd(ChipConfig, LaneData, 1);
+  GetComPhyPcd(ChipConfig, LaneData, 2);
+  GetComPhyPcd(ChipConfig, LaneData, 3);
+}
+
+EFI_STATUS
+MvComPhyInit (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  CHIP_COMPHY_CONFIG ChipConfig[MAX_CHIPS], *PtrChipCfg;
+  PCD_LANE_MAP LaneData[MAX_CHIPS];
+  UINT32 Lane, ChipCount, i, MaxComphyCount;
+
+  ChipCount = PcdGet32 (PcdComPhyChipCount);
+
+  InitComPhyConfig(ChipConfig, LaneData);
+
+  if (ChipCount <= 0 || ChipCount > MAX_CHIPS)
+    return EFI_INVALID_PARAMETER;
+
+  for (i = 0; i < ChipCount ; i++) {
+    PtrChipCfg = &ChipConfig[i];
+
+    /* Get the count of the SerDes of the specific chip */
+    MaxComphyCount = PtrChipCfg->LanesCount;
+    for (Lane = 0; Lane < MaxComphyCount; Lane++) {
+      /* Parse PCD with string indicating SerDes Type */
+      PtrChipCfg->MapData[Lane].Type =
+        ParseSerdesTypeString (LaneData[i].TypeStr[Lane]);
+      PtrChipCfg->MapData[Lane].Speed =
+        ParseSerdesSpeed (LaneData[i].SpeedValue[Lane]);
+      PtrChipCfg->MapData[Lane].Invert = (UINT32) LaneData[i].InvFlag[Lane];
+
+      if ((PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_INVALID) ||
+          (PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_ERROR) ||
+          (PtrChipCfg->MapData[Lane].Type == PHY_TYPE_INVALID)) {
+        DEBUG((DEBUG_ERROR, "ComPhy: No valid phy speed or type for lane %d, "
+          "setting lane as unconnected\n", Lane + 1));
+        PtrChipCfg->MapData[Lane].Type = PHY_TYPE_UNCONNECTED;
+        PtrChipCfg->MapData[Lane].Speed = PHY_SPEED_INVALID;
+      }
+    };
+
+    Status = GetChipComPhyInit (PtrChipCfg);
+    if (EFI_ERROR(Status)) {
+     DEBUG((DEBUG_ERROR, "ComPhy: Invalid Chip%dType name\n", i));
+     return Status;
+    }
+
+    ComPhyPrint (PtrChipCfg);
+
+    /* PHY power UP sequence */
+    PtrChipCfg->Init (PtrChipCfg);
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h
new file mode 100644
index 0000000..48cafc9
--- /dev/null
+++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h
@@ -0,0 +1,452 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __COMPHY_H__
+#define __COMPHY_H__
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/ParsePcdLib.h>
+
+#define MAX_LANE_OPTIONS          10
+#define MAX_CHIPS                 4
+
+/***** Parsing PCD *****/
+#define GET_TYPE_STRING(id)       PcdGetPtr(PcdChip##id##Compatible)
+#define GET_LANE_TYPE(id)         PcdGetPtr(PcdChip##id##ComPhyTypes)
+#define GET_LANE_SPEED(id)        PcdGetPtr(PcdChip##id##ComPhySpeeds)
+#define GET_LANE_INV(id)          PcdGetPtr(PcdChip##id##ComPhyInvFlags)
+#define GET_COMPHY_BASE_ADDR(id)  PcdGet64(PcdChip##id##ComPhyBaseAddress)
+#define GET_HPIPE3_BASE_ADDR(id)  PcdGet64(PcdChip##id##Hpipe3BaseAddress)
+#define GET_MUX_BIT_COUNT(id)     PcdGet32(PcdChip##id##ComPhyMuxBitCount)
+#define GET_MAX_LANES(id)         PcdGet32(PcdChip##id##ComPhyMaxLanes)
+
+#define FillLaneMap(chip_struct, lane_struct, id) { \
+  ParsePcdString((CHAR16 *) GET_LANE_TYPE(id), chip_struct[id].LanesCount, NULL, lane_struct[id].TypeStr);     \
+  ParsePcdString((CHAR16 *) GET_LANE_SPEED(id), chip_struct[id].LanesCount, lane_struct[id].SpeedValue, NULL); \
+  ParsePcdString((CHAR16 *) GET_LANE_INV(id), chip_struct[id].LanesCount, lane_struct[id].InvFlag, NULL);      \
+}
+
+#define GetComPhyPcd(chip_struct, lane_struct, id) {               \
+  chip_struct[id].ChipType = (CHAR16 *) GET_TYPE_STRING(id);       \
+  chip_struct[id].ComPhyBaseAddr = GET_COMPHY_BASE_ADDR(id);       \
+  chip_struct[id].Hpipe3BaseAddr = GET_HPIPE3_BASE_ADDR(id);       \
+  chip_struct[id].MuxBitCount = GET_MUX_BIT_COUNT(id);             \
+  chip_struct[id].LanesCount = GET_MAX_LANES(id);                  \
+  FillLaneMap(chip_struct, lane_struct, id);                       \
+}
+
+/***** ComPhy *****/
+#define PHY_SPEED_ERROR                           0
+#define PHY_SPEED_1_25G                           1
+#define PHY_SPEED_1_5G                            2
+#define PHY_SPEED_2_5G                            3
+#define PHY_SPEED_3G                              4
+#define PHY_SPEED_3_125G                          5
+#define PHY_SPEED_5G                              6
+#define PHY_SPEED_6G                              7
+#define PHY_SPEED_6_25G                           8
+#define PHY_SPEED_10_3125G                        9
+#define PHY_SPEED_MAX                             10
+#define PHY_SPEED_INVALID                         0xff
+
+#define PHY_TYPE_UNCONNECTED                      0
+#define PHY_TYPE_PCIE0                            1
+#define PHY_TYPE_PCIE1                            2
+#define PHY_TYPE_PCIE2                            3
+#define PHY_TYPE_PCIE3                            4
+#define PHY_TYPE_SATA0                            5
+#define PHY_TYPE_SATA1                            6
+#define PHY_TYPE_SATA2                            7
+#define PHY_TYPE_SATA3                            8
+#define PHY_TYPE_SGMII0                           9
+#define PHY_TYPE_SGMII1                           10
+#define PHY_TYPE_SGMII2                           11
+#define PHY_TYPE_SGMII3                           12
+#define PHY_TYPE_QSGMII                           13
+#define PHY_TYPE_USB3_HOST0                       14
+#define PHY_TYPE_USB3_HOST1                       15
+#define PHY_TYPE_USB3_DEVICE                      16
+#define PHY_TYPE_XAUI0                            17
+#define PHY_TYPE_XAUI1                            18
+#define PHY_TYPE_XAUI2                            19
+#define PHY_TYPE_XAUI3                            20
+#define PHY_TYPE_RXAUI0                           21
+#define PHY_TYPE_RXAUI1                           22
+#define PHY_TYPE_KR                               23
+#define PHY_TYPE_MAX                              24
+#define PHY_TYPE_INVALID                          0xff
+
+#define PHY_POLARITY_NO_INVERT                    0
+#define PHY_POLARITY_TXD_INVERT                   1
+#define PHY_POLARITY_RXD_INVERT                   2
+#define PHY_POLARITY_ALL_INVERT                   (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
+
+/***** SerDes IP registers *****/
+#define SD_EXTERNAL_CONFIG0_REG                   0
+#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET      1
+#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK        (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
+#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET  3
+#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK    (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
+#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET  7
+#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK    (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
+#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET       11
+#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK         (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
+#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET       12
+#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK         (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
+#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET  14
+#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK    (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
+
+#define SD_EXTERNAL_CONFIG1_REG                   0x4
+#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET       3
+#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK         (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
+#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET        4
+#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK          (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
+#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET     5
+#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK       (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
+#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET    6
+#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK      (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
+
+
+#define SD_EXTERNAL_STATUS0_REG                   0x18
+#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET         2
+#define SD_EXTERNAL_STATUS0_PLL_TX_MASK           (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
+#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET         3
+#define SD_EXTERNAL_STATUS0_PLL_RX_MASK           (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
+#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET        4
+#define SD_EXTERNAL_STATUS0_RX_INIT_MASK          (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
+
+/***** HPIPE registers *****/
+#define HPIPE_PWR_PLL_REG                         0x4
+#define HPIPE_PWR_PLL_REF_FREQ_OFFSET             0
+#define HPIPE_PWR_PLL_REF_FREQ_MASK               (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
+#define HPIPE_PWR_PLL_PHY_MODE_OFFSET             5
+#define HPIPE_PWR_PLL_PHY_MODE_MASK               (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
+
+#define HPIPE_KVCO_CALIB_CTRL_REG                 0x8
+#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET      12
+#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK        (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
+
+#define HPIPE_SQUELCH_FFE_SETTING_REG             0x018
+
+#define HPIPE_DFE_REG0                            0x01C
+#define HPIPE_DFE_RES_FORCE_OFFSET                15
+#define HPIPE_DFE_RES_FORCE_MASK                  (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
+
+
+#define HPIPE_DFE_F3_F5_REG                       0x028
+#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET             14
+#define HPIPE_DFE_F3_F5_DFE_EN_MASK               (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
+#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET           15
+#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK             (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
+
+#define HPIPE_G1_SET_0_REG                        0x034
+#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET         7
+#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK           (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
+
+#define HPIPE_G1_SET_1_REG                        0x038
+#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET       0
+#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK         (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET       3
+#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK         (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET        10
+#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK          (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
+
+#define HPIPE_G2_SETTINGS_1_REG                   0x040
+
+#define HPIPE_LOOPBACK_REG                        0x08c
+#define HPIPE_LOOPBACK_SEL_OFFSET                 1
+#define HPIPE_LOOPBACK_SEL_MASK                   (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
+
+#define HPIPE_SYNC_PATTERN_REG                    0x090
+
+#define HPIPE_INTERFACE_REG                       0x94
+#define HPIPE_INTERFACE_GEN_MAX_OFFSET            10
+#define HPIPE_INTERFACE_GEN_MAX_MASK              (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
+#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET         14
+#define HPIPE_INTERFACE_LINK_TRAIN_MASK           (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
+
+#define HPIPE_ISOLATE_MODE_REG                    0x98
+#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET          0
+#define HPIPE_ISOLATE_MODE_GEN_RX_MASK            (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
+#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET          4
+#define HPIPE_ISOLATE_MODE_GEN_TX_MASK            (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
+
+#define HPIPE_VTHIMPCAL_CTRL_REG                  0x104
+
+#define HPIPE_PCIE_REG0                           0x120
+#define HPIPE_PCIE_IDLE_SYNC_OFFSET               12
+#define HPIPE_PCIE_IDLE_SYNC_MASK                 (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
+#define HPIPE_PCIE_SEL_BITS_OFFSET                13
+#define HPIPE_PCIE_SEL_BITS_MASK                  (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
+
+#define HPIPE_LANE_ALIGN_REG                      0x124
+#define HPIPE_LANE_ALIGN_OFF_OFFSET               12
+#define HPIPE_LANE_ALIGN_OFF_MASK                 (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
+
+#define HPIPE_MISC_REG                            0x13C
+#define HPIPE_MISC_CLK100M_125M_OFFSET            4
+#define HPIPE_MISC_CLK100M_125M_MASK              (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
+#define HPIPE_MISC_TXDCLK_2X_OFFSET               6
+#define HPIPE_MISC_TXDCLK_2X_MASK                 (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
+#define HPIPE_MISC_CLK500_EN_OFFSET               7
+#define HPIPE_MISC_CLK500_EN_MASK                 (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
+#define HPIPE_MISC_REFCLK_SEL_OFFSET              10
+#define HPIPE_MISC_REFCLK_SEL_MASK                (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
+
+#define HPIPE_RX_CONTROL_1_REG                    0x140
+#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET     11
+#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK       (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
+#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET        12
+#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK          (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
+
+#define HPIPE_PWR_CTR_REG                         0x148
+#define HPIPE_PWR_CTR_RST_DFE_OFFSET              0
+#define HPIPE_PWR_CTR_RST_DFE_MASK                (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
+#define HPIPE_PWR_CTR_SFT_RST_OFFSET              10
+#define HPIPE_PWR_CTR_SFT_RST_MASK                (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
+
+#define HPIPE_PLLINTP_REG1                        0x150
+
+#define HPIPE_PWR_CTR_DTL_REG                     0x184
+#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET         0x2
+#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK           (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
+
+#define HPIPE_RX_REG3                             0x188
+
+#define HPIPE_TX_TRAIN_CTRL_REG                   0x26C
+#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET             0
+#define HPIPE_TX_TRAIN_CTRL_G1_MASK               (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
+#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET            1
+#define HPIPE_TX_TRAIN_CTRL_GN1_MASK              (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
+#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET             2
+#define HPIPE_TX_TRAIN_CTRL_G0_MASK               (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
+
+#define HPIPE_PCIE_REG1                           0x288
+#define HPIPE_PCIE_REG3                           0x290
+
+#define HPIPE_TX_TRAIN_REG                        0x31C
+#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET            4
+#define HPIPE_TX_TRAIN_CHK_INIT_MASK              (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
+#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET    7
+#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK      (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
+
+#define HPIPE_G1_SETTINGS_3_REG                   0x440
+#define HPIPE_G1_SETTINGS_4_REG                   0x444
+#define HPIPE_G2_SETTINGS_3_REG                   0x448
+#define HPIPE_G2_SETTINGS_4_REG                   0x44C
+
+#define HPIPE_DFE_CTRL_28_REG                     0x49C
+#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET            7
+#define HPIPE_DFE_CTRL_28_PIPE4_MASK              (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
+
+#define HPIPE_LANE_CONFIG0_REG                    0x604
+#define HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET         9
+#define HPIPE_LANE_CONFIG0_MAX_PLL_MASK           (0x1 << HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET)
+#define HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET        10
+#define HPIPE_LANE_CONFIG0_GEN2_PLL_MASK          (0x1 << HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET)
+
+#define HPIPE_LANE_STATUS0_REG                    0x60C
+#define HPIPE_LANE_STATUS0_PCLK_EN_OFFSET         0
+#define HPIPE_LANE_STATUS0_PCLK_EN_MASK           (0x1 << HPIPE_LANE_STATUS0_PCLK_EN_OFFSET)
+
+#define HPIPE_LANE_CFG4_REG                       0x620
+#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET           0
+#define HPIPE_LANE_CFG4_DFE_CTRL_MASK             (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
+#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET           6
+#define HPIPE_LANE_CFG4_DFE_OVER_MASK             (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
+#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET           7
+#define HPIPE_LANE_CFG4_SSC_CTRL_MASK             (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
+
+#define HPIPE_LANE_EQ_CFG1_REG                    0x6a0
+#define HPIPE_CFG_UPDATE_POLARITY_OFFSET          12
+#define HPIPE_CFG_UPDATE_POLARITY_MASK            (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
+
+#define HPIPE_RST_CLK_CTRL_REG                    0x704
+#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET        0
+#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK          (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
+#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET      2
+#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK        (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
+#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET      3
+#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK        (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
+#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET   9
+#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK     (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
+
+#define HPIPE_CLK_SRC_LO_REG                      0x70c
+#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET        5
+#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK          (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
+
+#define HPIPE_CLK_SRC_HI_REG                      0x710
+#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET         0
+#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK           (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
+#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET        1
+#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK          (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
+#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET       2
+#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK         (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
+#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET         7
+#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK           (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
+
+#define HPIPE_GLOBAL_MISC_CTRL                    0x718
+#define HPIPE_GLOBAL_PM_CTRL                      0x740
+#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET        0
+#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK          (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
+
+/***** COMPHY registers *****/
+#define COMMON_PHY_CFG1_REG                       0x0
+#define COMMON_PHY_CFG1_PWR_UP_OFFSET             1
+#define COMMON_PHY_CFG1_PWR_UP_MASK               (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
+#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET        2
+#define COMMON_PHY_CFG1_PIPE_SELECT_MASK          (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
+#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET       13
+#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK         (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
+#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET          14
+#define COMMON_PHY_CFG1_CORE_RSTN_MASK            (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
+#define COMMON_PHY_PHY_MODE_OFFSET                15
+#define COMMON_PHY_PHY_MODE_MASK                  (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
+
+#define COMMON_PHY_CFG6_REG                       0x14
+#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET          18
+#define COMMON_PHY_CFG6_IF_40_SEL_MASK            (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
+
+#define COMMON_SELECTOR_PHY_OFFSET                0x140
+#define COMMON_SELECTOR_PIPE_OFFSET               0x144
+
+/***** SATA registers *****/
+#define SATA3_VENDOR_ADDRESS                      0xA0
+#define SATA3_VENDOR_ADDR_OFSSET                  0
+#define SATA3_VENDOR_ADDR_MASK                    (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET)
+#define SATA3_VENDOR_DATA                         0xA4
+
+#define SATA_CONTROL_REG                          0x0
+#define SATA3_CTRL_SATA0_PD_OFFSET                6
+#define SATA3_CTRL_SATA0_PD_MASK                  (1 << SATA3_CTRL_SATA0_PD_OFFSET)
+#define SATA3_CTRL_SATA1_PD_OFFSET                14
+#define SATA3_CTRL_SATA1_PD_MASK                  (1 << SATA3_CTRL_SATA1_PD_OFFSET)
+#define SATA3_CTRL_SATA1_ENABLE_OFFSET            22
+#define SATA3_CTRL_SATA1_ENABLE_MASK              (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET)
+#define SATA3_CTRL_SATA_SSU_OFFSET                23
+#define SATA3_CTRL_SATA_SSU_MASK                  (1 << SATA3_CTRL_SATA_SSU_OFFSET)
+
+#define SATA_MBUS_SIZE_SELECT_REG                 0x4
+#define SATA_MBUS_REGRET_EN_OFFSET                7
+#define SATA_MBUS_REGRET_EN_MASK                  (0x1 << SATA_MBUS_REGRET_EN_OFFSET)
+
+/***************************/
+
+typedef struct _CHIP_COMPHY_CONFIG CHIP_COMPHY_CONFIG;
+
+typedef struct {
+  UINT32 Type;
+  UINT32 MuxValue;
+} COMPHY_MUX_OPTIONS;
+
+typedef struct {
+  UINT32 MaxLaneValues;
+  COMPHY_MUX_OPTIONS MuxValues[MAX_LANE_OPTIONS];
+} COMPHY_MUX_DATA;
+
+typedef struct {
+  UINT32 Type;
+  UINT32 Speed;
+  UINT32 Invert;
+} COMPHY_MAP;
+
+typedef struct {
+  CHAR16 *TypeStr[MAX_LANE_OPTIONS];
+  UINTN SpeedValue[MAX_LANE_OPTIONS];
+  UINTN InvFlag[MAX_LANE_OPTIONS];
+} PCD_LANE_MAP;
+
+typedef
+EFI_STATUS
+(*COMPHY_CHIP_INIT) (
+  IN CHIP_COMPHY_CONFIG *PtrChipCfg
+  );
+
+struct _CHIP_COMPHY_CONFIG {
+  CHAR16* ChipType;
+  COMPHY_MAP MapData[MAX_LANE_OPTIONS];
+  COMPHY_MUX_DATA *MuxData;
+  EFI_PHYSICAL_ADDRESS ComPhyBaseAddr;
+  EFI_PHYSICAL_ADDRESS Hpipe3BaseAddr;
+  COMPHY_CHIP_INIT Init;
+  UINT32 LanesCount;
+  UINT32 MuxBitCount;
+};
+
+VOID
+ComPhyMuxInit (
+  IN CHIP_COMPHY_CONFIG *PtrChipCfg,
+  IN COMPHY_MAP *ComPhyMapData,
+  IN EFI_PHYSICAL_ADDRESS SelectorBase
+  );
+
+EFI_STATUS
+ComPhyCp110Init (
+  IN CHIP_COMPHY_CONFIG * First
+  );
+
+VOID
+RegSet (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT32 Data,
+  IN UINT32 Mask
+  );
+
+VOID
+RegSetSilent (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT32 Data,
+  IN UINT32 Mask
+  );
+
+VOID
+RegSet16 (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT16 Data,
+  IN UINT16 Mask
+  );
+
+VOID
+RegSetSilent16(
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT16 Data,
+  IN UINT16 Mask
+  );
+#endif // __COMPHY_H__
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf
new file mode 100644
index 0000000..a7ee1f8
--- /dev/null
+++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf
@@ -0,0 +1,109 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+#   this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+#   used to endorse or promote products derived from this software without
+#   specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MarvellComPhyLib
+  FILE_GUID                      = 3314541a-9647-4a37-b8c6-24e000900e4e
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ComPhyLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+  MemoryAllocationLib
+  PcdLib
+  IoLib
+  ParsePcdLib
+
+[Sources.common]
+  ComPhyLib.c
+  ComPhyCp110.c
+  ComPhyMux.c
+
+[FixedPcd]
+  gMarvellTokenSpaceGuid.PcdComPhyChipCount
+
+  #Chip0
+  gMarvellTokenSpaceGuid.PcdChip0Compatible
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress
+  gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
+
+  #Chip1
+  gMarvellTokenSpaceGuid.PcdChip1Compatible
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress
+  gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes
+
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes
+  gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags
+
+  #Chip2
+  gMarvellTokenSpaceGuid.PcdChip2Compatible
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress
+  gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes
+
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes
+  gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags
+
+  #Chip3
+  gMarvellTokenSpaceGuid.PcdChip3Compatible
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress
+  gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes
+
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes
+  gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags
+
+  #SATA
+  gMarvellTokenSpaceGuid.PcdSataBaseAddress
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c
new file mode 100644
index 0000000..595745b
--- /dev/null
+++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c
@@ -0,0 +1,132 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "ComPhyLib.h"
+
+STATIC
+VOID
+ComPhyMuxCheckConfig (
+  IN COMPHY_MUX_DATA *MuxData,
+  IN COMPHY_MAP *ComPhyMapData,
+  IN UINTN ComPhyMaxLanes
+  )
+{
+  COMPHY_MUX_OPTIONS *PtrMuxOpt;
+  UINTN Lane, Opt, Valid;
+
+  for (Lane = 0; Lane < ComPhyMaxLanes; Lane++, ComPhyMapData++, MuxData++) {
+    PtrMuxOpt = MuxData->MuxValues;
+    for (Opt = 0, Valid = 0; Opt < MuxData->MaxLaneValues; Opt++, PtrMuxOpt++) {
+      if (PtrMuxOpt->Type == ComPhyMapData->Type) {
+        Valid = 1;
+        break;
+      }
+    }
+    if (Valid == 0) {
+      DEBUG((DEBUG_INFO, "Lane number %d, had invalid Type %d\n", Lane,
+        ComPhyMapData->Type));
+      DEBUG((DEBUG_INFO, "Set Lane %d as Type %d\n", Lane,
+        PHY_TYPE_UNCONNECTED));
+      ComPhyMapData->Type = PHY_TYPE_UNCONNECTED;
+    } else {
+      DEBUG((DEBUG_INFO, "Lane number %d, has Type %d\n", Lane,
+        ComPhyMapData->Type));
+    }
+  }
+}
+
+STATIC
+UINT32
+ComPhyMuxGetMuxValue (
+  IN COMPHY_MUX_DATA *MuxData,
+  IN UINT32 Type,
+  IN UINTN Lane
+  )
+{
+  COMPHY_MUX_OPTIONS *PtrMuxOpt;
+  UINTN Opt;
+  UINT32 Value = 0;
+
+  PtrMuxOpt = MuxData->MuxValues;
+  for (Opt = 0 ; Opt < MuxData->MaxLaneValues; Opt++, PtrMuxOpt++)
+    if (PtrMuxOpt->Type == Type) {
+      Value = PtrMuxOpt->MuxValue;
+      break;
+    }
+
+  return Value;
+}
+
+STATIC
+VOID
+ComPhyMuxRegWrite (
+  IN COMPHY_MUX_DATA *MuxData,
+  IN COMPHY_MAP *ComPhyMapData,
+  IN UINTN ComPhyMaxLanes,
+  IN EFI_PHYSICAL_ADDRESS SelectorBase,
+  IN UINT32 BitCount
+  )
+{
+  UINT32 Lane, Value, Offset, Mask;
+
+  for (Lane = 0; Lane < ComPhyMaxLanes; Lane++, ComPhyMapData++, MuxData++) {
+    Offset = Lane * BitCount;
+    Mask = (((1 << BitCount) - 1) << Offset);
+    Value = (ComPhyMuxGetMuxValue (MuxData, ComPhyMapData->Type, Lane) <<
+      Offset);
+    RegSet (SelectorBase, Value, Mask);
+  }
+}
+
+VOID
+ComPhyMuxInit (
+  IN CHIP_COMPHY_CONFIG *PtrChipCfg,
+  IN COMPHY_MAP *ComPhyMapData,
+  IN EFI_PHYSICAL_ADDRESS SelectorBase
+  )
+{
+  COMPHY_MUX_DATA *MuxData;
+  UINT32 MuxBitCount;
+  UINT32 ComPhyMaxLanes;
+
+  ComPhyMaxLanes = PtrChipCfg->LanesCount;
+  MuxData = PtrChipCfg->MuxData;
+  MuxBitCount = PtrChipCfg->MuxBitCount;
+
+  /* Check if the configuration is valid */
+  ComPhyMuxCheckConfig (MuxData, ComPhyMapData, ComPhyMaxLanes);
+  /* Init COMPHY selectors */
+  ComPhyMuxRegWrite (MuxData, ComPhyMapData, ComPhyMaxLanes, SelectorBase,
+    MuxBitCount);
+}
diff --git a/Platforms/Marvell/Library/MppLib/MppLib.c b/Platforms/Marvell/Library/MppLib/MppLib.c
new file mode 100644
index 0000000..c09acf9
--- /dev/null
+++ b/Platforms/Marvell/Library/MppLib/MppLib.c
@@ -0,0 +1,216 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+
+#define MPP_PIN_VAL(pin,func)    (((func) & 0xf) << ((pin) * 4))
+#define MPP_MAX_REGS             8
+#define MPP_PINS_PER_REG         8
+#define PCD_PINS_PER_GROUP       10
+
+#define SD_MMC_PHY_AP_MPP_OFFSET   0x100
+#define SD_MMC_PHY_CP0_MPP_OFFSET  0x424
+#define MPP_ON_SDPHY_ENABLE        (1 << 0)
+
+#define MAX_CHIPS                4
+
+#define GET_PCD_PTR(id,num)      PcdGetPtr(PcdChip##id##MppSel##num)
+#define GET_PIN_COUNT(id)        PcdGet32(PcdChip##id##MppPinCount)
+#define GET_BASE(id)             PcdGet64(PcdChip##id##MppBaseAddress)
+#define GET_REV_FLAG(id)         PcdGetBool(PcdChip##id##MppReverseFlag)
+
+/* We get chip number */
+#define GetMppPcd(id) {                 \
+  PinCount[id] = GET_PIN_COUNT(id);     \
+  MppRegPcd[id][7] = GET_PCD_PTR(id,7); \
+  MppRegPcd[id][6] = GET_PCD_PTR(id,6); \
+  MppRegPcd[id][5] = GET_PCD_PTR(id,5); \
+  MppRegPcd[id][4] = GET_PCD_PTR(id,4); \
+  MppRegPcd[id][3] = GET_PCD_PTR(id,3); \
+  MppRegPcd[id][2] = GET_PCD_PTR(id,2); \
+  MppRegPcd[id][1] = GET_PCD_PTR(id,1); \
+  MppRegPcd[id][0] = GET_PCD_PTR(id,0); \
+  BaseAddr[id] = GET_BASE(id);          \
+  ReverseFlag[id] = GET_REV_FLAG(id);   \
+}
+
+STATIC
+VOID
+SetRegisterValue (
+  UINT8 RegCount,
+  UINT8 **MppRegPcd,
+  UINTN BaseAddr,
+  BOOLEAN ReverseFlag
+  )
+{
+  UINT32 i, j, CtrlVal;
+  INTN Sign;
+
+  Sign = ReverseFlag ? -1 : 1;
+
+  for (i = 0; i < RegCount; i++) {
+    CtrlVal = 0;
+    for (j = 0; j < MPP_PINS_PER_REG; j++) {
+      CtrlVal |= MPP_PIN_VAL(7 * (UINTN) ReverseFlag + j * Sign,
+        MppRegPcd[i][7 * (UINTN) ReverseFlag + j * Sign]);
+    }
+    MmioWrite32 (BaseAddr + 4 * i * Sign, CtrlVal);
+  }
+}
+
+STATIC
+/* Transform PCD MPP group format into hardware register format */
+UINT8
+PcdToMppRegs (
+  UINTN PinCount,
+  UINT8 **MppRegPcd
+  )
+{
+  UINT8 MppRegPcdTmp[MPP_MAX_REGS][MPP_PINS_PER_REG];
+  UINT8 PcdGroupCount, MppRegCount;
+  UINTN i, j, k, l;
+
+  if (PinCount == 0) {
+    return 0;
+  }
+
+  PcdGroupCount = PinCount / PCD_PINS_PER_GROUP;
+  if ((PinCount % PCD_PINS_PER_GROUP) != 0) {
+    PcdGroupCount += 1;
+  }
+
+  MppRegCount = PinCount / MPP_PINS_PER_REG;
+  if ((PinCount % MPP_PINS_PER_REG) != 0) {
+    MppRegCount += 1;
+  }
+
+  /* Fill temporary table with data from PCD groups in HW format */
+  for (i = 0; i < PcdGroupCount; i++) {
+    for (j = 0; j < PCD_PINS_PER_GROUP; j++) {
+      k = (PCD_PINS_PER_GROUP * i + j) / MPP_PINS_PER_REG;
+      l = (PCD_PINS_PER_GROUP * i + j) % MPP_PINS_PER_REG;
+      MppRegPcdTmp[k][l] = MppRegPcd[i][j];
+    }
+  }
+
+  /* Update input table */
+  for (i = 0; i < MppRegCount; i++) {
+    for (j = 0; j < MPP_PINS_PER_REG; j++) {
+      MppRegPcd[i][j] = MppRegPcdTmp[i][j];
+    }
+  }
+
+  return MppRegCount;
+}
+
+STATIC
+VOID
+SetSdMmcPhyMpp (
+  UINTN  BaseAddr,
+  UINT32 Index
+  )
+{
+  UINTN  Size, Offset;
+  UINT8 *Ptr;
+  UINT32 Reg;
+
+  Size = PcdGetSize(PcdPciESdhci);
+  Ptr = (UINT8 *) PcdGetPtr(PcdPciESdhci);
+
+  if (Ptr == NULL || Index >= Size) {
+    return;
+  }
+
+  /* Check if SDHCI controller is enabled on the HW block */
+  if (Ptr[Index] != 1) {
+    return;
+  }
+
+  /* Choose adequate Offset */
+  switch (Index) {
+  case 0:
+    Offset = SD_MMC_PHY_AP_MPP_OFFSET;
+    break;
+  case 1:
+    Offset = SD_MMC_PHY_CP0_MPP_OFFSET;
+    break;
+  default:
+    return;
+  }
+
+  /*
+   * If there is SDHCI controller on platform, connect SD/MMC PHY to
+   * SD/MMC controller insted of using it as MPP multiplexer
+   */
+  Reg = MmioRead32 (BaseAddr + Offset);
+  Reg &= ~MPP_ON_SDPHY_ENABLE;
+  MmioWrite32 (BaseAddr + Offset, Reg);
+}
+
+EFI_STATUS
+MppInitialize (
+  )
+{
+  UINTN BaseAddr[MAX_CHIPS], PinCount[MAX_CHIPS], RegCount;
+  BOOLEAN ReverseFlag[MAX_CHIPS];
+  UINT8 *MppRegPcd[MAX_CHIPS][MPP_MAX_REGS];
+  UINT32 i, ChipCount;
+
+  ChipCount = PcdGet32 (PcdMppChipCount);
+
+  /* Read all needed PCD for MPP configuration */
+  GetMppPcd(0);
+  GetMppPcd(1);
+  GetMppPcd(2);
+  GetMppPcd(3);
+
+  for (i = 0; i < MAX_CHIPS; i++) {
+    if (i == ChipCount)
+      break;
+    RegCount = PcdToMppRegs (PinCount[i], MppRegPcd[i]);
+    SetRegisterValue (RegCount, MppRegPcd[i], BaseAddr[i], ReverseFlag[i]);
+
+    /*
+     * eMMC PHY IP has its own MPP configuration.
+     */
+    SetSdMmcPhyMpp (BaseAddr[i], i);
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/Marvell/Library/MppLib/MppLib.inf b/Platforms/Marvell/Library/MppLib/MppLib.inf
new file mode 100644
index 0000000..82716f4
--- /dev/null
+++ b/Platforms/Marvell/Library/MppLib/MppLib.inf
@@ -0,0 +1,108 @@
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute
+# and/or modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MarvellMppLib
+  FILE_GUID                      = 3f19b642-4a49-4dfd-8f4a-205dd38432bb
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = MppLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+  MemoryAllocationLib
+  PcdLib
+  IoLib
+
+[Sources.common]
+  MppLib.c
+
+[FixedPcd]
+  gMarvellTokenSpaceGuid.PcdMppChipCount
+
+  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
+  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
+  gMarvellTokenSpaceGuid.PcdChip0MppPinCount
+  gMarvellTokenSpaceGuid.PcdChip0MppSel0
+  gMarvellTokenSpaceGuid.PcdChip0MppSel1
+  gMarvellTokenSpaceGuid.PcdChip0MppSel2
+  gMarvellTokenSpaceGuid.PcdChip0MppSel3
+  gMarvellTokenSpaceGuid.PcdChip0MppSel4
+  gMarvellTokenSpaceGuid.PcdChip0MppSel5
+  gMarvellTokenSpaceGuid.PcdChip0MppSel6
+  gMarvellTokenSpaceGuid.PcdChip0MppSel7
+
+  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag
+  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress
+  gMarvellTokenSpaceGuid.PcdChip1MppPinCount
+  gMarvellTokenSpaceGuid.PcdChip1MppSel0
+  gMarvellTokenSpaceGuid.PcdChip1MppSel1
+  gMarvellTokenSpaceGuid.PcdChip1MppSel2
+  gMarvellTokenSpaceGuid.PcdChip1MppSel3
+  gMarvellTokenSpaceGuid.PcdChip1MppSel4
+  gMarvellTokenSpaceGuid.PcdChip1MppSel5
+  gMarvellTokenSpaceGuid.PcdChip1MppSel6
+  gMarvellTokenSpaceGuid.PcdChip1MppSel7
+
+  gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag
+  gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress
+  gMarvellTokenSpaceGuid.PcdChip2MppPinCount
+  gMarvellTokenSpaceGuid.PcdChip2MppSel0
+  gMarvellTokenSpaceGuid.PcdChip2MppSel1
+  gMarvellTokenSpaceGuid.PcdChip2MppSel2
+  gMarvellTokenSpaceGuid.PcdChip2MppSel3
+  gMarvellTokenSpaceGuid.PcdChip2MppSel4
+  gMarvellTokenSpaceGuid.PcdChip2MppSel5
+  gMarvellTokenSpaceGuid.PcdChip2MppSel6
+  gMarvellTokenSpaceGuid.PcdChip2MppSel7
+
+  gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag
+  gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress
+  gMarvellTokenSpaceGuid.PcdChip3MppPinCount
+  gMarvellTokenSpaceGuid.PcdChip3MppSel0
+  gMarvellTokenSpaceGuid.PcdChip3MppSel1
+  gMarvellTokenSpaceGuid.PcdChip3MppSel2
+  gMarvellTokenSpaceGuid.PcdChip3MppSel3
+  gMarvellTokenSpaceGuid.PcdChip3MppSel4
+  gMarvellTokenSpaceGuid.PcdChip3MppSel5
+  gMarvellTokenSpaceGuid.PcdChip3MppSel6
+  gMarvellTokenSpaceGuid.PcdChip3MppSel7
+
+  gMarvellTokenSpaceGuid.PcdPciESdhci
diff --git a/Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.c b/Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.c
new file mode 100644
index 0000000..9a4be8e
--- /dev/null
+++ b/Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.c
@@ -0,0 +1,228 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must Retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#define CHAR_NULL 0x0000
+
+#include <Library/BaseLib.h>
+#include <Uefi.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+
+STATIC
+CHAR16
+CharToUpper (
+  IN CHAR16 Char
+  )
+{
+
+  if (Char >= L'a' && Char <= L'z') {
+    return (CHAR16) (Char - (L'a' - L'A'));
+  }
+
+  return Char;
+}
+
+STATIC
+BOOLEAN
+IsDecimalDigitChar (
+  IN CHAR16 Char
+  )
+{
+
+  return (BOOLEAN) (Char >= L'0' && Char <= L'9');
+}
+
+
+STATIC
+UINTN
+HexCharToUintn (
+  IN CHAR16 Char
+  )
+{
+  if (IsDecimalDigitChar (Char)) {
+    return Char - L'0';
+  }
+
+  return (UINTN) (10 + CharToUpper (Char) - L'A');
+}
+
+STATIC
+BOOLEAN
+IsHexDigitCharacter (
+  CHAR16 Char
+  )
+{
+
+  return (BOOLEAN) ((Char >= L'0' && Char <= L'9') || (Char >= L'A' &&
+    Char <= L'F') || (Char >= L'a' && Char <= L'f'));
+}
+
+STATIC
+UINTN
+HexStrToUintn (
+  CHAR16 *String
+  )
+{
+  UINTN Result = 0;
+
+  if (String == NULL || StrSize(String) == 0) {
+    return (UINTN)(-1);
+  }
+
+  // Ignore spaces and tabs
+  while ((*String == L' ') || (*String == L'\t')) {
+    String++;
+  }
+
+  // Ignore leading zeros after spaces
+  while (*String == L'0') {
+    String++;
+  }
+
+  if (CharToUpper (*String) != L'X') {
+    return (UINTN)(-1);
+  }
+
+  // Skip 'x'
+  String++;
+
+  while (IsHexDigitCharacter (*String)) {
+    Result <<= 4;
+    Result += HexCharToUintn (*String);
+    String++;
+  }
+
+  return (UINTN) Result;
+}
+
+STATIC
+UINTN
+DecimalStrToUintn (
+  CHAR16 *String
+  )
+{
+  UINTN Result = 0;
+
+  while (IsDecimalDigitChar (*String)) {
+    Result = 10 * Result + (*String - L'0');
+    String++;
+  }
+
+  return Result;
+}
+
+STATIC
+UINTN
+StrToUintn (
+  CHAR16 *String
+  )
+{
+  CHAR16 *Walker;
+
+  // Chop off leading spaces
+  for (Walker = String; Walker != NULL && *Walker != CHAR_NULL && *Walker == L' '; Walker++);
+
+  if (StrnCmp(Walker, L"0x", 2) == 0 || StrnCmp(Walker, L"0X", 2) == 0) {
+    return HexStrToUintn (Walker);
+  } else {
+    return DecimalStrToUintn (Walker);
+  }
+}
+
+EFI_STATUS
+ParsePcdString (
+  IN  CHAR16 *PcdString,
+  IN  UINT8  Count,
+  OUT UINTN  *ValueTable,
+  OUT CHAR16 **StrTable
+  )
+{
+  BOOLEAN ValueFlag = FALSE;
+  CHAR16 *Walker;
+  UINTN i, Tmp = 0;
+
+  if (ValueTable != NULL) {
+    ValueFlag = TRUE;
+  }
+
+  // Set pointer at the end of PCD string
+  Walker = PcdString + StrLen (PcdString);
+  for (i = 0; i < Count; i++) {
+    while ((--Walker) >= PcdString) {
+      if (*Walker == L';') {
+        // Cut off parsed chunk from PCD string by replacing ';' with
+        // null-terminator
+        *Walker = '\0';
+        if (ValueFlag) {
+          Tmp = StrToUintn ((Walker + 1));
+          if ((UINTN)(-1) == Tmp) {
+            return EFI_INVALID_PARAMETER;
+          }
+          // Entry is parsed from the end to the beginning
+          // so fill table in the same manner
+          ValueTable[Count - (i + 1)] = Tmp;
+        } else {
+          StrTable[Count - (i + 1)] = Walker + 1;
+        }
+        Walker--;
+        break;
+      }
+      if (Walker == PcdString) {
+        if (ValueFlag) {
+          Tmp = StrToUintn ((Walker));
+          if (Tmp == (UINTN)(-1)) {
+            return EFI_INVALID_PARAMETER;
+          }
+        }
+        // Last device's entry should be added to the table here.
+        // If not, return error
+        if (i != (Count - 1)) {
+          DEBUG((DEBUG_ERROR, "ParsePcdLib: Please set PCD value for every "
+            "device\n"));
+          return EFI_INVALID_PARAMETER;
+        }
+        // We parse from the end to the beginning
+        // so fill table in the same manner
+        if (ValueFlag) {
+          ValueTable[Count - (i + 1)] = Tmp;
+        } else {
+          StrTable[Count - (i + 1)] = Walker;
+        }
+        // End both loops
+        return EFI_SUCCESS;
+      }
+    }
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.inf b/Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.inf
new file mode 100644
index 0000000..b4db621
--- /dev/null
+++ b/Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.inf
@@ -0,0 +1,50 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+#   this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+#   used to endorse or promote products derived from this software without
+#   specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ParsePcdLib
+  FILE_GUID                      = 698d85a0-a952-453e-b8a4-1d6ea338a38e
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ParsePcdLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+
+[Sources.common]
+  ParsePcdLib.c
diff --git a/Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.c b/Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.c
new file mode 100644
index 0000000..c0787ac
--- /dev/null
+++ b/Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.c
@@ -0,0 +1,159 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#include <PiDxe.h>
+#include <Uefi.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+#include <Guid/EventGroup.h>
+
+STATIC EFI_EVENT mResetSystemVirtualAddrChangeEvent;
+STATIC UINT64    mAddress;
+
+STATIC
+VOID
+EFIAPI
+LibResetSystemVirtualNotifyEvent (
+  IN EFI_EVENT        Event,
+  IN VOID             *Context
+  )
+{
+  //
+  // Convert physical address to virtual address.
+  //
+  EfiConvertPointer (0x0, (VOID**)&mAddress);
+  return;
+}
+
+/**
+  Resets the entire platform.
+
+  @param  ResetType             The type of reset to perform.
+  @param  ResetStatus           The status code for the reset.
+  @param  DataSize              The size, in bytes, of WatchdogData.
+  @param  ResetData             For a ResetType of EfiResetCold, EfiResetWarm,
+                                or EfiResetShutdown the data buffer starts with
+                                a Null-terminated Unicode string, optionally
+                                followed by additional binary data.
+**/
+EFI_STATUS
+EFIAPI
+LibResetSystem (
+  IN EFI_RESET_TYPE   ResetType,
+  IN EFI_STATUS       ResetStatus,
+  IN UINTN            DataSize,
+  IN VOID             *ResetData OPTIONAL
+  )
+{
+  UINT32   Data;
+
+  switch (ResetType) {
+  case EfiResetCold:
+  case EfiResetWarm:
+    Data = MmioRead32 (mAddress);
+    Data &= ~PcdGet32 (PcdResetRegMask);
+    MmioWrite32 (mAddress, Data);
+    break;
+  case EfiResetShutdown:
+  //
+  // Currently there is no support for power-off platform
+  //
+    break;
+  default:
+    break;
+  }
+
+  return EFI_DEVICE_ERROR;
+}
+
+EFI_STATUS
+EFIAPI
+LibInitializeResetSystem (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  UINT64 Alignment;
+  EFI_STATUS  Status;
+
+  mAddress = PcdGet64 (PcdResetRegAddress);
+
+  Alignment = ~(SIZE_64KB - 1);
+  //
+  // Add 64KB aligned and 64KB long memory space
+  //
+  Status = gDS->AddMemorySpace (
+                  EfiGcdMemoryTypeMemoryMappedIo,
+                  mAddress & Alignment, SIZE_64KB,
+                  EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+                  );
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  //
+  // Mark 64KB aligned and 64KB long memory space as runtime
+  //
+  Status = gDS->SetMemorySpaceAttributes (mAddress & Alignment, SIZE_64KB,
+    EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  //
+  // Register for the virtual address change event
+  //
+  Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  LibResetSystemVirtualNotifyEvent,
+                  NULL,
+                  &gEfiEventVirtualAddressChangeGuid,
+                  &mResetSystemVirtualAddrChangeEvent
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.inf b/Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.inf
new file mode 100644
index 0000000..87fff57
--- /dev/null
+++ b/Platforms/Marvell/Library/ResetSystemLib/MvResetSystemLib.inf
@@ -0,0 +1,58 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+#  * Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+#  * Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+#  * Neither the name of Marvell nor the names of its contributors may be
+#    used to endorse or promote products derived from this software without
+#    specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = Reset
+  FILE_GUID                      = 9d1373c0-6fac-432c-88e7-818744dc45d9
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = EfiResetSystemLib
+
+[Sources.common]
+  MvResetSystemLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  DebugLib
+  DxeServicesTableLib
+  IoLib
+  UefiBootServicesTableLib
+  UefiLib
+  UefiRuntimeLib
+
+[Pcd]
+  gMarvellTokenSpaceGuid.PcdResetRegAddress
+  gMarvellTokenSpaceGuid.PcdResetRegMask
diff --git a/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c
new file mode 100644
index 0000000..95b5698
--- /dev/null
+++ b/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c
@@ -0,0 +1,353 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must Retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "UtmiPhyLib.h"
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESS UtmiBaseAddr;
+  EFI_PHYSICAL_ADDRESS UsbCfgAddr;
+  EFI_PHYSICAL_ADDRESS UtmiCfgAddr;
+  UINT32 UtmiPhyPort;
+} UTMI_PHY_DATA;
+
+STATIC
+VOID
+RegSetSilent (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT32 Data,
+  IN UINT32 Mask
+  )
+{
+  UINT32 RegData;
+
+  RegData = MmioRead32 (Addr);
+  RegData &= ~Mask;
+  RegData |= Data;
+  MmioWrite32 (Addr, RegData);
+}
+
+STATIC
+VOID
+RegSet (
+  IN EFI_PHYSICAL_ADDRESS Addr,
+  IN UINT32 Data,
+  IN UINT32 Mask
+  )
+{
+  DEBUG((DEBUG_INFO, "Write to address = %10x, data = %10x (mask = %10x)-\n",
+    Addr, Data, Mask));
+  DEBUG((DEBUG_INFO, "old value = %10x ==>\n", MmioRead32 (Addr)));
+  RegSetSilent (Addr, Data, Mask);
+  DEBUG((DEBUG_INFO, "new value %10x\n", MmioRead32 (Addr)));
+}
+
+STATIC
+VOID
+UtmiPhyPowerDown (
+  IN UINT32 UtmiIndex,
+  IN EFI_PHYSICAL_ADDRESS UtmiBaseAddr,
+  IN EFI_PHYSICAL_ADDRESS UsbCfgAddr,
+  IN EFI_PHYSICAL_ADDRESS UtmiCfgAddr,
+  IN UINT32 UtmiPhyPort
+  )
+{
+  UINT32 Mask, Data;
+
+  DEBUG((DEBUG_INFO, "UtmiPhy: stage: UTMI %d - Power down transceiver(power down Phy)\n",
+    UtmiIndex));
+  DEBUG((DEBUG_INFO, "UtmiPhy: stage: Power down PLL, and SuspendDM\n"));
+  /* Power down UTMI PHY */
+  RegSet (UtmiCfgAddr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, UTMI_PHY_CFG_PU_MASK);
+  /* Config USB3 Device UTMI enable */
+  Mask = UTMI_USB_CFG_DEVICE_EN_MASK;
+
+  /*
+   * Prior to PHY init, configure mux for Device
+   * (Device can be connected to UTMI0 or to UTMI1)
+   */
+  if (UtmiPhyPort == UTMI_PHY_TO_USB_DEVICE0) {
+    Data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
+    /* Config USB3 Device UTMI MUX */
+    Mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
+    Data |= UtmiIndex << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
+  } else {
+    Data = 0x0 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
+  }
+
+  /* Set Test suspendm mode */
+  Mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
+  Data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
+  /* Enable Test UTMI select */
+  Mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
+  Data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
+  RegSet (UtmiBaseAddr + UTMI_CTRL_STATUS0_REG, Data, Mask);
+
+  /* Wait for UTMI power down */
+  MicroSecondDelay (1000);
+}
+
+STATIC
+VOID
+UtmiPhyConfig (
+  IN UINT32 UtmiIndex,
+  IN EFI_PHYSICAL_ADDRESS UtmiBaseAddr,
+  IN EFI_PHYSICAL_ADDRESS UsbCfgAddr,
+  IN EFI_PHYSICAL_ADDRESS UtmiCfgAddr,
+  IN UINT32 UtmiPhyPort
+  )
+{
+  UINT32 Mask, Data;
+
+  DEBUG((DEBUG_INFO, "UtmiPhy: stage: Configure UTMI PHY %d registers\n",
+    UtmiIndex));
+  /* Reference Clock Divider Select */
+  Mask = UTMI_PLL_CTRL_REFDIV_MASK;
+  Data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
+  /* Feedback Clock Divider Select - 90 for 25Mhz */
+  Mask |= UTMI_PLL_CTRL_FBDIV_MASK;
+  Data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
+  /* Select LPFR - 0x0 for 25Mhz/5=5Mhz */
+  Mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
+  Data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
+  RegSet (UtmiBaseAddr + UTMI_PLL_CTRL_REG, Data, Mask);
+
+  /* Impedance Calibration Threshold Setting */
+  RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG,
+    0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
+    UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
+
+  /* Set LS TX driver strength coarse control */
+  Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
+  Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
+  /* Set LS TX driver fine adjustment */
+  Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
+  Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
+  RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask);
+
+  /* Enable SQ */
+  Mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
+  Data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
+  /* Enable analog squelch detect */
+  Mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
+  Data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+  RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask);
+
+  /* Set External squelch calibration number */
+  Mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
+  Data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
+  /* Enable the External squelch calibration */
+  Mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
+  Data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
+  RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL1_REG, Data, Mask);
+
+  /* Set Control VDAT Reference Voltage - 0.325V */
+  Mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
+  Data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
+  /* Set Control VSRC Reference Voltage - 0.6V */
+  Mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
+  Data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
+  RegSet (UtmiBaseAddr + UTMI_CHGDTC_CTRL_REG, Data, Mask);
+}
+
+STATIC
+UINTN
+UtmiPhyPowerUp (
+  IN UINT32 UtmiIndex,
+  IN EFI_PHYSICAL_ADDRESS UtmiBaseAddr,
+  IN EFI_PHYSICAL_ADDRESS UsbCfgAddr,
+  IN EFI_PHYSICAL_ADDRESS UtmiCfgAddr,
+  IN UINT32 UtmiPhyPort
+  )
+{
+  EFI_STATUS Status;
+  UINT32 Data;
+
+  DEBUG((DEBUG_INFO, "UtmiPhy: stage: UTMI %d - Power up transceiver(Power up Phy)\n",
+    UtmiIndex));
+  DEBUG((DEBUG_INFO, "UtmiPhy: stage: exit SuspendDM\n"));
+  /* Power up UTMI PHY */
+  RegSet (UtmiCfgAddr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, UTMI_PHY_CFG_PU_MASK);
+  /* Disable Test UTMI select */
+  RegSet (UtmiBaseAddr + UTMI_CTRL_STATUS0_REG,
+    0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
+    UTMI_CTRL_STATUS0_TEST_SEL_MASK);
+
+  DEBUG((DEBUG_INFO, "UtmiPhy: stage: Wait for PLL and impedance calibration done, and PLL ready\n"));
+
+  /* Delay 10ms */
+  MicroSecondDelay (10000);
+
+  Data = MmioRead32 (UtmiBaseAddr + UTMI_CALIB_CTRL_REG);
+  if ((Data & UTMI_CALIB_CTRL_IMPCAL_DONE_MASK) == 0) {
+    DEBUG((DEBUG_ERROR, "UtmiPhy: Impedance calibration is not done\n"));
+    Status = EFI_D_ERROR;
+  }
+  if ((Data & UTMI_CALIB_CTRL_PLLCAL_DONE_MASK) == 0) {
+    DEBUG((DEBUG_ERROR, "UtmiPhy: PLL calibration is not done\n"));
+    Status = EFI_D_ERROR;
+  }
+  Data = MmioRead32 (UtmiBaseAddr + UTMI_PLL_CTRL_REG);
+  if ((Data & UTMI_PLL_CTRL_PLL_RDY_MASK) == 0) {
+    DEBUG((DEBUG_ERROR, "UtmiPhy: PLL is not ready\n"));
+    Status = EFI_D_ERROR;
+  }
+
+  return Status;
+}
+
+/*
+ * Cp110UtmiPhyInit initializes the UTMI PHY
+ * the init split in 3 parts:
+ * 1. Power down transceiver and PLL
+ * 2. UTMI PHY configure
+ * 3. Power up transceiver and PLL
+ */
+STATIC
+VOID
+Cp110UtmiPhyInit (
+  IN UINT32 UtmiPhyCount,
+  IN UTMI_PHY_DATA *UtmiData
+  )
+{
+  UINT32 i;
+
+  for (i = 0; i < UtmiPhyCount; i++) {
+    UtmiPhyPowerDown(i, UtmiData[i].UtmiBaseAddr,
+      UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr,
+      UtmiData[i].UtmiPhyPort);
+  }
+
+  /* Power down PLL */
+  DEBUG((DEBUG_INFO, "UtmiPhy: stage: PHY power down PLL\n"));
+  RegSet (UtmiData[0].UsbCfgAddr, 0x0 << UTMI_USB_CFG_PLL_OFFSET,
+    UTMI_USB_CFG_PLL_MASK);
+
+  for (i = 0; i < UtmiPhyCount; i++) {
+    UtmiPhyConfig(i, UtmiData[i].UtmiBaseAddr,
+      UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr,
+      UtmiData[i].UtmiPhyPort);
+  }
+
+  for (i = 0; i < UtmiPhyCount; i++) {
+    if (EFI_ERROR(UtmiPhyPowerUp(i, UtmiData[i].UtmiBaseAddr,
+        UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr,
+        UtmiData[i].UtmiPhyPort))) {
+      DEBUG((DEBUG_ERROR, "UtmiPhy: Failed to initialize UTMI PHY %d\n", i));
+      continue;
+    }
+    DEBUG((DEBUG_ERROR, "UTMI PHY %d initialized to ", i));
+
+    if (UtmiData[i].UtmiPhyPort == UTMI_PHY_TO_USB_DEVICE0)
+      DEBUG((DEBUG_ERROR, "USB Device\n"));
+    else
+      DEBUG((DEBUG_ERROR, "USB Host%d\n", UtmiData[i].UtmiPhyPort));
+  }
+
+  /* Power up PLL */
+  DEBUG((DEBUG_INFO, "UtmiPhy: stage: PHY power up PLL\n"));
+  RegSet (UtmiData[0].UsbCfgAddr, 0x1 << UTMI_USB_CFG_PLL_OFFSET,
+    UTMI_USB_CFG_PLL_MASK);
+}
+
+EFI_STATUS
+UtmiPhyInit (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  UTMI_PHY_DATA UtmiData[PcdGet32 (PcdUtmiPhyCount)];
+  EFI_PHYSICAL_ADDRESS RegUtmiUnit[PcdGet32 (PcdUtmiPhyCount)];
+  EFI_PHYSICAL_ADDRESS RegUsbCfg[PcdGet32 (PcdUtmiPhyCount)];
+  EFI_PHYSICAL_ADDRESS RegUtmiCfg[PcdGet32 (PcdUtmiPhyCount)];
+  UINTN UtmiPort[PcdGet32 (PcdUtmiPhyCount)];
+  UINTN i, Count;
+
+  Count = PcdGet32 (PcdUtmiPhyCount);
+  if (Count == 0) {
+    /* No UTMI PHY on platform */
+    return EFI_SUCCESS;
+  }
+
+  DEBUG((DEBUG_INFO, "UtmiPhy: Initialize USB UTMI PHYs\n"));
+  /* Parse UtmiPhy PCDs */
+  Status = ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUtmiUnit),
+    Count, RegUtmiUnit, NULL);
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUtmiUnit format\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUsbCfg),
+    Count, RegUsbCfg, NULL);
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUsbCfg format\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUtmiCfg),
+    Count, RegUtmiCfg, NULL);
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUtmiCfg format\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyUtmiPort),
+    Count, UtmiPort, NULL);
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyUtmiPort format\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  for (i = 0 ; i < Count ; i++) {
+    /* Get base address of UTMI phy */
+    UtmiData[i].UtmiBaseAddr = RegUtmiUnit[i];
+
+    /* Get usb config address */
+    UtmiData[i].UsbCfgAddr = RegUsbCfg[i];
+
+    /* Get UTMI config address */
+    UtmiData[i].UtmiCfgAddr = RegUtmiCfg[i];
+
+    /*
+     * Get the usb port number, which will be used to check if
+     * the utmi connected to host or device
+     */
+    UtmiData[i].UtmiPhyPort = UtmiPort[i];
+  }
+
+  /* Currently only Cp110 is supported */
+  Cp110UtmiPhyInit (Count, UtmiData);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h
new file mode 100644
index 0000000..f9b4933
--- /dev/null
+++ b/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h
@@ -0,0 +1,110 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+  used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#ifndef __UTMIPHY_H__
+#define __UTMIPHY_H__
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/ParsePcdLib.h>
+
+#define UTMI_USB_CFG_DEVICE_EN_OFFSET             0
+#define UTMI_USB_CFG_DEVICE_EN_MASK               (0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET)
+#define UTMI_USB_CFG_DEVICE_MUX_OFFSET            1
+#define UTMI_USB_CFG_DEVICE_MUX_MASK              (0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET)
+#define UTMI_USB_CFG_PLL_OFFSET                   25
+#define UTMI_USB_CFG_PLL_MASK                     (0x1 << UTMI_USB_CFG_PLL_OFFSET)
+
+#define UTMI_PHY_CFG_PU_OFFSET                    5
+#define UTMI_PHY_CFG_PU_MASK                      (0x1 << UTMI_PHY_CFG_PU_OFFSET)
+
+#define UTMI_PLL_CTRL_REG                         0x0
+#define UTMI_PLL_CTRL_REFDIV_OFFSET               0
+#define UTMI_PLL_CTRL_REFDIV_MASK                 (0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET)
+#define UTMI_PLL_CTRL_FBDIV_OFFSET                16
+#define UTMI_PLL_CTRL_FBDIV_MASK                  (0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET)
+#define UTMI_PLL_CTRL_SEL_LPFR_OFFSET             28
+#define UTMI_PLL_CTRL_SEL_LPFR_MASK               (0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET)
+#define UTMI_PLL_CTRL_PLL_RDY_OFFSET              31
+#define UTMI_PLL_CTRL_PLL_RDY_MASK                (0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET)
+
+#define UTMI_CALIB_CTRL_REG                       0x8
+#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET         8
+#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK           (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
+#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET        23
+#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK          (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
+#define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET        31
+#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK          (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
+
+#define UTMI_TX_CH_CTRL_REG                       0xC
+#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET          12
+#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK            (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
+#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET         16
+#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK           (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
+
+#define UTMI_RX_CH_CTRL0_REG                      0x14
+#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET            15
+#define UTMI_RX_CH_CTRL0_SQ_DET_MASK              (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
+#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET        28
+#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK          (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
+
+#define UTMI_RX_CH_CTRL1_REG                      0x18
+#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET        0
+#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK          (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
+#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET     3
+#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK       (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
+
+#define UTMI_CTRL_STATUS0_REG                     0x24
+#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET         22
+#define UTMI_CTRL_STATUS0_SUSPENDM_MASK           (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
+#define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET         25
+#define UTMI_CTRL_STATUS0_TEST_SEL_MASK           (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
+
+#define UTMI_CHGDTC_CTRL_REG                      0x38
+#define UTMI_CHGDTC_CTRL_VDAT_OFFSET              8
+#define UTMI_CHGDTC_CTRL_VDAT_MASK                (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
+#define UTMI_CHGDTC_CTRL_VSRC_OFFSET              10
+#define UTMI_CHGDTC_CTRL_VSRC_MASK                (0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET)
+
+#define UTMI_PHY_TO_USB_HOST0                     0
+#define UTMI_PHY_TO_USB_HOST1                     1
+#define UTMI_PHY_TO_USB_DEVICE0                   2
+#define UTMI_PHY_INVALID                          0xff
+
+#endif
diff --git a/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
new file mode 100644
index 0000000..21de609
--- /dev/null
+++ b/Platforms/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
@@ -0,0 +1,64 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+#   this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+#   used to endorse or promote products derived from this software without
+#   specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = MarvellUtmiPhyLib
+  FILE_GUID                      = e9adaac2-0443-4921-9367-5d575c3c91bc
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = UtmiPhyLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+  IoLib
+  MemoryAllocationLib
+  ParsePcdLib
+  PcdLib
+
+[Sources.common]
+  UtmiPhyLib.c
+
+[FixedPcd]
+  gMarvellTokenSpaceGuid.PcdUtmiPhyCount
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit
+  gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort
diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec
new file mode 100644
index 0000000..313eaa6
--- /dev/null
+++ b/Platforms/Marvell/Marvell.dec
@@ -0,0 +1,228 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+#* Redistributions of source code must retain the above copyright notice,
+#  this list of conditions and the following disclaimer.
+#
+#* Redistributions in binary form must reproduce the above copyright
+#  notice, this list of conditions and the following disclaimer in the
+#  documentation and/or other materials provided with the distribution.
+#
+#* Neither the name of Marvell nor the names of its contributors may be
+#  used to endorse or promote products derived from this software without
+#  specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = OpenPlatformMarvellPkg
+  PACKAGE_GUID                   = c372916e-83ad-4b2a-8410-bbc31bd9e68f
+  PACKAGE_VERSION                = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Includes]
+  Include
+
+[Guids.common]
+  gMarvellTokenSpaceGuid = { 0xf995c6c8, 0xbc9b, 0x4e93, { 0xbd, 0xcf, 0x49, 0x90, 0xc6, 0xe7, 0x8c, 0x7f } }
+
+  gShellEepromHiiGuid = { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce, 0x7b, 0x91, 0x7f, 0x5f, 0x2f } }
+  gShellFUpdateHiiGuid = { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } }
+  gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } }
+
+[PcdsFixedAtBuild.common]
+#MPP
+  gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001
+
+  gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE|BOOLEAN|0x30000002
+  gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0|UINT64|0x30000003
+  gMarvellTokenSpaceGuid.PcdChip0MppPinCount|0|UINT32|0x30000004
+  gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0 }|VOID*|0x30000005
+  gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0 }|VOID*|0x30000006
+  gMarvellTokenSpaceGuid.PcdChip0MppSel2|{ 0x0 }|VOID*|0x30000007
+  gMarvellTokenSpaceGuid.PcdChip0MppSel3|{ 0x0 }|VOID*|0x30000008
+  gMarvellTokenSpaceGuid.PcdChip0MppSel4|{ 0x0 }|VOID*|0x30000009
+  gMarvellTokenSpaceGuid.PcdChip0MppSel5|{ 0x0 }|VOID*|0x30000010
+  gMarvellTokenSpaceGuid.PcdChip0MppSel6|{ 0x0 }|VOID*|0x30000011
+  gMarvellTokenSpaceGuid.PcdChip0MppSel7|{ 0x0 }|VOID*|0x30000012
+
+  gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE|BOOLEAN|0x30000013
+  gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0|UINT64|0x30000014
+  gMarvellTokenSpaceGuid.PcdChip1MppPinCount|0|UINT32|0x30000015
+  gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x0 }|VOID*|0x30000016
+  gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x0 }|VOID*|0x30000017
+  gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0 }|VOID*|0x30000018
+  gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x0 }|VOID*|0x30000019
+  gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0 }|VOID*|0x30000020
+  gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0 }|VOID*|0x30000021
+  gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0x0 }|VOID*|0x30000022
+  gMarvellTokenSpaceGuid.PcdChip1MppSel7|{ 0x0 }|VOID*|0x30000023
+
+  gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE|BOOLEAN|0x30000024
+  gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0|UINT64|0x30000025
+  gMarvellTokenSpaceGuid.PcdChip2MppPinCount|0|UINT32|0x30000026
+  gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0 }|VOID*|0x30000027
+  gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0 }|VOID*|0x30000028
+  gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0 }|VOID*|0x30000029
+  gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0 }|VOID*|0x30000030
+  gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0 }|VOID*|0x30000031
+  gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0 }|VOID*|0x30000032
+  gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0 }|VOID*|0x30000033
+  gMarvellTokenSpaceGuid.PcdChip2MppSel7|{ 0x0 }|VOID*|0x30000034
+
+  gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE|BOOLEAN|0x30000035
+  gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0|UINT64|0x30000036
+  gMarvellTokenSpaceGuid.PcdChip3MppPinCount|0|UINT32|0x30000037
+  gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0 }|VOID*|0x30000038
+  gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0 }|VOID*|0x30000039
+  gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0 }|VOID*|0x30000040
+  gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0 }|VOID*|0x30000041
+  gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0 }|VOID*|0x30000042
+  gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0 }|VOID*|0x30000043
+  gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0x0 }|VOID*|0x30000044
+  gMarvellTokenSpaceGuid.PcdChip3MppSel7|{ 0x0 }|VOID*|0x30000045
+
+#I2C
+  gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x0 }|VOID*|0x3000046
+  gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x3000184
+  gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x0 }|VOID*|0x3000050
+  gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0 }|VOID*|0x3000185
+  gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|{ 0x0 }|VOID*|0x3000047
+  gMarvellTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048
+  gMarvellTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049
+  gMarvellTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183
+
+#SPI
+  gMarvellTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051
+  gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052
+  gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053
+
+  gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0|UINT32|0x3000052
+  gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|0|UINT32|0x3000053
+  gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054
+  gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055
+  gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056
+
+#ComPhy
+  #Chip0
+  gMarvellTokenSpaceGuid.PcdComPhyChipCount|0|UINT32|0x30000098
+
+  gMarvellTokenSpaceGuid.PcdChip0Compatible|{ 0x0 }|VOID*|0x30000064
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0|UINT64|0x30000065
+  gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0|UINT64|0x30000066
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|0|UINT32|0x30000067
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|0|UINT32|0x30001267
+
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0x0 }|VOID*|0x30000068
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x0 }|VOID*|0x30000069
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0x0 }|VOID*|0x30000070
+
+  #Chip1
+  gMarvellTokenSpaceGuid.PcdChip1Compatible|{ 0x0 }|VOID*|0x30000100
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyBaseAddress|0|UINT64|0x30000101
+  gMarvellTokenSpaceGuid.PcdChip1Hpipe3BaseAddress|0|UINT64|0x30000102
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyMuxBitCount|0|UINT32|0x30000103
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyMaxLanes|0|UINT32|0x30001304
+
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0x0 }|VOID*|0x30000105
+  gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0x0 }|VOID*|0x30000106
+  gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0x0 }|VOID*|0x30000107
+
+  #Chip2
+  gMarvellTokenSpaceGuid.PcdChip2Compatible|{ 0x0 }|VOID*|0x30000135
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyBaseAddress|0|UINT64|0x30000136
+  gMarvellTokenSpaceGuid.PcdChip2Hpipe3BaseAddress|0|UINT64|0x30000137
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyMuxBitCount|0|UINT32|0x30000138
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyMaxLanes|0|UINT32|0x30000139
+
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0x0 }|VOID*|0x30000140
+  gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0x0 }|VOID*|0x30000141
+  gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0x0 }|VOID*|0x30000142
+
+  #Chip3
+  gMarvellTokenSpaceGuid.PcdChip3Compatible|{ 0x0 }|VOID*|0x30000170
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyBaseAddress|0|UINT64|0x30000171
+  gMarvellTokenSpaceGuid.PcdChip3Hpipe3BaseAddress|0|UINT64|0x30000172
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyMuxBitCount|0|UINT32|0x30000173
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyMaxLanes|0|UINT32|0x30000174
+
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0x0 }|VOID*|0x30000175
+  gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000176
+  gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177
+
+#SATA
+  gMarvellTokenSpaceGuid.PcdSataBaseAddress|0|UINT32|0x4000052
+
+#UtmiPhy
+  gMarvellTokenSpaceGuid.PcdUtmiPhyCount|0|UINT32|0x30000205
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|{ 0x0 }|VOID*|0x30000206
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|{ 0x0 }|VOID*|0x30000207
+  gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|{ 0x0 }|VOID*|0x30000208
+  gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|{ 0x0 }|VOID*|0x30000209
+
+#MDIO
+  gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0|UINT64|0x3000043
+
+#PHY
+  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0 }|VOID*|0x3000044
+  gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }|VOID*|0x3000095
+  gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE|BOOLEAN|0x3000070
+
+#NET
+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024
+  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026
+  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0|UINT64|0x3000027
+  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0|UINT32|0x3000028
+  gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
+  gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D
+  gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
+  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0|UINT64|0x300002E
+  gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F
+  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0|UINT64|0x3000030
+  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0|UINT64|0x3000031
+  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0|UINT32|0x3000032
+
+#PciEmulation
+  gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033
+  gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034
+  gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035
+
+#ResetLib
+  gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050
+  gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051
+
+[Protocols]
+  gMarvellEepromProtocolGuid               = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
+  gMarvellMdioProtocolGuid                 = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
+  gMarvellPhyProtocolGuid                  = { 0x32f48a43, 0x37e3, 0x4acf, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }}
+  gMarvellSpiMasterProtocolGuid            = { 0x23de66a3, 0xf666, 0x4b3e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }}
+  gMarvellSpiFlashProtocolGuid             = { 0x9accb423, 0x5bd2, 0x4fca, { 0x9b, 0x4c, 0x2e, 0x65, 0xfc, 0x25, 0xdf, 0x21 }}
+
diff --git a/Platforms/Marvell/PciEmulation/PciEmulation.c b/Platforms/Marvell/PciEmulation/PciEmulation.c
new file mode 100644
index 0000000..491b886
--- /dev/null
+++ b/Platforms/Marvell/PciEmulation/PciEmulation.c
@@ -0,0 +1,230 @@
+/********************************************************************************
+Copyright (C) 2016 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+  * Neither the name of Marvell nor the names of its contributors may be
+    used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include <PiDxe.h>
+
+#include <Library/DebugLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/EmbeddedExternalDevice.h>
+
+//
+// Platform description
+//
+typedef struct {
+  // XHCI
+  UINT8 XhciDevCount;
+  UINTN XhciBaseAddresses[4];
+  UINTN XhciMemSize[4];
+  NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType[4];
+  // AHCI
+  UINT8 AhciDevCount;
+  UINTN AhciBaseAddresses[4];
+  UINTN AhciMemSize[4];
+  NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType[4];
+  // SDHCI
+  UINT8 SdhciDevCount;
+  UINTN SdhciBaseAddresses[4];
+  UINTN SdhciMemSize[4];
+  NON_DISCOVERABLE_DEVICE_DMA_TYPE SdhciDmaType[4];
+} PCIE_PLATFORM_DESC;
+
+STATIC PCIE_PLATFORM_DESC mA70x0PlatDescTemplate = {
+  2, // XHCI
+  { 0xF2500000, 0xF2510000 },
+  { SIZE_16KB, SIZE_16KB },
+  { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCoherent },
+  1, // AHCI
+  { 0xF2540000 },
+  { SIZE_8KB },
+  { NonDiscoverableDeviceDmaTypeCoherent },
+  2, // SDHCI
+  { 0xF06E0000, 0xF2780000 },
+  { SIZE_1KB, SIZE_1KB },
+  { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCoherent }
+};
+
+//
+// Tables with used devices
+//
+STATIC UINT8 * CONST XhciDeviceTable = FixedPcdGetPtr (PcdPciEXhci);
+STATIC UINT8 * CONST AhciDeviceTable = FixedPcdGetPtr (PcdPciEAhci);
+STATIC UINT8 * CONST SdhciDeviceTable = FixedPcdGetPtr (PcdPciESdhci);
+
+#define DEV_ENABLED(type, index) (type ## DeviceTable[index])
+
+//
+// NonDiscoverable devices registration
+//
+STATIC
+EFI_STATUS
+PciEmulationInitXhci (
+  )
+{
+  PCIE_PLATFORM_DESC *Desc = &mA70x0PlatDescTemplate;
+  EFI_STATUS Status;
+  UINT8 i;
+
+  if (PcdGetSize (PcdPciEXhci) < Desc->XhciDevCount) {
+    DEBUG((DEBUG_ERROR, "PciEmulation: Wrong PcdPciEXhci format\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  for (i = 0; i < Desc->XhciDevCount; i++) {
+    if (!DEV_ENABLED(Xhci, i)) {
+      continue;
+    }
+
+    Status = RegisterNonDiscoverableMmioDevice (
+                     NonDiscoverableDeviceTypeXhci,
+                     Desc->XhciDmaType[i],
+                     NULL,
+                     NULL,
+                     1,
+                     Desc->XhciBaseAddresses[i], Desc->XhciMemSize[i]
+                   );
+
+    if (EFI_ERROR(Status)) {
+      DEBUG((DEBUG_ERROR, "PciEmulation: Cannot install Xhci device %d\n", i));
+      return Status;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+PciEmulationInitAhci (
+  )
+{
+  PCIE_PLATFORM_DESC *Desc = &mA70x0PlatDescTemplate;
+  EFI_STATUS Status;
+  UINT8 i;
+
+  if (PcdGetSize (PcdPciEAhci) < Desc->AhciDevCount) {
+    DEBUG((DEBUG_ERROR, "PciEmulation: Wrong PcdPciEAhci format\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  for (i = 0; i < Desc->AhciDevCount; i++) {
+    if (!DEV_ENABLED(Ahci, i)) {
+      continue;
+    }
+
+    Status = RegisterNonDiscoverableMmioDevice (
+                     NonDiscoverableDeviceTypeAhci,
+                     Desc->AhciDmaType[i],
+                     NULL,
+                     NULL,
+                     1,
+                     Desc->AhciBaseAddresses[i], Desc->AhciMemSize[i]
+                   );
+
+    if (EFI_ERROR(Status)) {
+      DEBUG((DEBUG_ERROR, "PciEmulation: Cannot install Ahci device %d\n", i));
+      return Status;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+PciEmulationInitSdhci (
+  )
+{
+  PCIE_PLATFORM_DESC *Desc = &mA70x0PlatDescTemplate;
+  EFI_STATUS Status;
+  UINT8 i;
+
+  if (PcdGetSize (PcdPciESdhci) < Desc->SdhciDevCount) {
+    DEBUG((DEBUG_ERROR, "PciEmulation: Wrong PcdPciESdhci format\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  for (i = 0; i < Desc->SdhciDevCount; i++) {
+    if (!DEV_ENABLED(Sdhci, i)) {
+      continue;
+    }
+
+    Status = RegisterNonDiscoverableMmioDevice (
+                     NonDiscoverableDeviceTypeSdhci,
+                     Desc->SdhciDmaType[i],
+                     NULL,
+                     NULL,
+                     1,
+                     Desc->SdhciBaseAddresses[i], Desc->SdhciMemSize[i]
+                   );
+
+    if (EFI_ERROR(Status)) {
+      DEBUG((DEBUG_ERROR, "PciEmulation: Cannot install Sdhci device %d\n", i));
+      return Status;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+//
+// Entry point
+//
+EFI_STATUS
+EFIAPI
+PciEmulationEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS Status;
+
+  Status = PciEmulationInitXhci();
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = PciEmulationInitAhci();
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  Status = PciEmulationInitSdhci();
+  if (EFI_ERROR(Status)) {
+    return Status;
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platforms/Marvell/PciEmulation/PciEmulation.inf b/Platforms/Marvell/PciEmulation/PciEmulation.inf
new file mode 100644
index 0000000..5d569b9
--- /dev/null
+++ b/Platforms/Marvell/PciEmulation/PciEmulation.inf
@@ -0,0 +1,61 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# Marvell BSD License Option
+#
+# If you received this File from Marvell, you may opt to use, redistribute and/or
+# modify this File under the following licensing terms.
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+#  * Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+#  * Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+#  * Neither the name of Marvell nor the names of its contributors may be
+#    used to endorse or promote products derived from this software without
+#    specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+[Defines]
+  INF_VERSION                     = 0x00010019
+  BASE_NAME                       = PciEmulation
+  FILE_GUID                       = 3dfa08da-923b-4841-9435-c77a604d7493
+  MODULE_TYPE                     = DXE_DRIVER
+  VERSION_STRING                  = 1.0
+
+  ENTRY_POINT                     = PciEmulationEntryPoint
+
+[Sources.common]
+  PciEmulation.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Platforms/Marvell/Marvell.dec
+
+[LibraryClasses]
+  NonDiscoverableDeviceRegistrationLib
+  UefiDriverEntryPoint
+
+[Pcd]
+  gMarvellTokenSpaceGuid.PcdPciEXhci
+  gMarvellTokenSpaceGuid.PcdPciEAhci
+  gMarvellTokenSpaceGuid.PcdPciESdhci
+
+[Depex]
+  TRUE
diff --git a/Platforms/TexasInstruments/BeagleBoard/Bds/Bds.inf b/Platforms/TexasInstruments/BeagleBoard/Bds/Bds.inf
deleted file mode 100644
index 2b20a09..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Bds/Bds.inf
+++ /dev/null
@@ -1,65 +0,0 @@
-
-#/** @file
-#
-#    Component description file for Bds module
-#
-#  Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardBds
-  FILE_GUID                      = 934431fe-5745-402e-913d-17b4434eb0f3
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-
-  ENTRY_POINT                    = BdsInitialize
-
-[Sources.common]
-  BdsEntry.c
-  FirmwareVolume.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-
-[LibraryClasses]
-  DevicePathLib
-  BaseLib
-  HobLib
-  UefiRuntimeServicesTableLib
-  ReportStatusCodeLib
-  PerformanceLib
-  DxeServicesTableLib
-  MemoryAllocationLib
-  UefiLib
-  UefiBootServicesTableLib
-  BaseMemoryLib
-  DebugLib
-  PrintLib
-  UefiDriverEntryPoint
-
-[Guids]
-
-
-[Protocols]
-  gEfiBdsArchProtocolGuid
-  gEfiSimpleTextInProtocolGuid
-  gEfiSimpleTextOutProtocolGuid
-  gEfiSerialIoProtocolGuid
-  gEfiDevicePathProtocolGuid
-  gEfiSimpleFileSystemProtocolGuid
-  gEfiUsbIoProtocolGuid
-  gEfiFirmwareVolume2ProtocolGuid
-
-[Depex]
-  TRUE
diff --git a/Platforms/TexasInstruments/BeagleBoard/Bds/BdsEntry.c b/Platforms/TexasInstruments/BeagleBoard/Bds/BdsEntry.c
deleted file mode 100644
index f2f1ae3..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Bds/BdsEntry.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/** @file
-  The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements
-  of the UEFI specification as it is designed to implement an embedded systmes
-  propriatary boot scheme.
-
-  This template assume a DXE driver produces a SerialIo protocol not using the EFI
-  driver module and it will attempt to connect a console on top of this.
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BdsEntry.h"
-
-
-BOOLEAN     gConsolePresent = FALSE;
-
-EFI_BDS_ARCH_PROTOCOL  gBdsProtocol = {
-  BdsEntry,
-};
-
-
-
-
-/**
-  This function uses policy data from the platform to determine what operating
-  system or system utility should be loaded and invoked.  This function call
-  also optionally make the use of user input to determine the operating system
-  or system utility to be loaded and invoked.  When the DXE Core has dispatched
-  all the drivers on the dispatch queue, this function is called.  This
-  function will attempt to connect the boot devices required to load and invoke
-  the selected operating system or system utility.  During this process,
-  additional firmware volumes may be discovered that may contain addition DXE
-  drivers that can be dispatched by the DXE Core.   If a boot device cannot be
-  fully connected, this function calls the DXE Service Dispatch() to allow the
-  DXE drivers from any newly discovered firmware volumes to be dispatched.
-  Then the boot device connection can be attempted again.  If the same boot
-  device connection operation fails twice in a row, then that boot device has
-  failed, and should be skipped.  This function should never return.
-
-  @param  This             The EFI_BDS_ARCH_PROTOCOL instance.
-
-  @return None.
-
-**/
-VOID
-EFIAPI
-BdsEntry (
-  IN EFI_BDS_ARCH_PROTOCOL  *This
-  )
-{
-  EFI_STATUS                Status;
-  UINTN                     NoHandles;
-  EFI_HANDLE                *Buffer;
-  EFI_HANDLE                FvHandle;
-  EFI_HANDLE                ImageHandle;
-  EFI_HANDLE                UsbDeviceHandle;
-  EFI_GUID                  NameGuid;
-  UINTN                     Size;
-  UINTN                     HandleCount;
-  UINTN                     OldHandleCount;
-  EFI_HANDLE                *HandleBuffer;
-  UINTN                     Index;
-  EFI_DEVICE_PATH_PROTOCOL  *LoadImageDevicePath;
-  EFI_DEVICE_PATH_PROTOCOL  *FileSystemDevicePath;
-
-  PERF_END   (NULL, "DXE", NULL, 0);
-  PERF_START (NULL, "BDS", NULL, 0);
-
-
-  //
-  // Now do the EFI stuff
-  //
-  Size = 0x100;
-  gST->FirmwareVendor = AllocateRuntimePool (Size);
-  ASSERT (gST->FirmwareVendor != NULL);
-
-  UnicodeSPrint (gST->FirmwareVendor, Size, L"BeagleBoard EFI %a %a", __DATE__, __TIME__);
-
-  //
-  // Now we need to setup the EFI System Table with information about the console devices.
-  // This code is normally in the console spliter driver on platforms that support multiple
-  // consoles at the same time
-  //
-  Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextOutProtocolGuid, NULL, &NoHandles, &Buffer);
-  if (!EFI_ERROR (Status)) {
-    // Use the first SimpleTextOut we find and update the EFI System Table
-    gST->ConsoleOutHandle = Buffer[0];
-    gST->StandardErrorHandle = Buffer[0];
-    Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextOutProtocolGuid, (VOID **)&gST->ConOut);
-    ASSERT_EFI_ERROR (Status);
-
-    gST->StdErr = gST->ConOut;
-
-    gST->ConOut->OutputString (gST->ConOut, L"BDS: Console Started!!!!\n\r");
-    FreePool (Buffer);
-
-    gConsolePresent = TRUE;
-  }
-
-
-  Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextInProtocolGuid, NULL, &NoHandles, &Buffer);
-  if (!EFI_ERROR (Status)) {
-    // Use the first SimpleTextIn we find and update the EFI System Table
-    gST->ConsoleInHandle = Buffer[0];
-    Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextInProtocolGuid, (VOID **)&gST->ConIn);
-    ASSERT_EFI_ERROR (Status);
-
-    FreePool (Buffer);
-  }
-
-  //
-  // We now have EFI Consoles up and running. Print () will work now. DEBUG () and ASSERT () worked
-  // prior to this point as they were configured to use a more primative output scheme.
-  //
-
-  //
-  //Perform Connect
-  //
-  HandleCount = 0;
-  while (1) {
-    OldHandleCount = HandleCount;
-    Status = gBS->LocateHandleBuffer (
-                    AllHandles,
-                    NULL,
-                    NULL,
-                    &HandleCount,
-                    &HandleBuffer
-                    );
-    if (EFI_ERROR (Status)) {
-      break;
-    }
-
-    if (HandleCount == OldHandleCount) {
-      break;
-    }
-
-    for (Index = 0; Index < HandleCount; Index++) {
-      gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);
-    }
-  }
-
-  EfiSignalEventReadyToBoot ();
-
-  //Locate handles for SimpleFileSystem protocol
-  Status = gBS->LocateHandleBuffer (
-                  ByProtocol,
-                  &gEfiSimpleFileSystemProtocolGuid,
-                  NULL,
-                  &HandleCount,
-                  &HandleBuffer
-                  );
-  if (!EFI_ERROR(Status)) {
-    for (Index = 0; Index < HandleCount; Index++) {
-      //Get the device path
-      FileSystemDevicePath = DevicePathFromHandle(HandleBuffer[Index]);
-      if (FileSystemDevicePath == NULL) {
-        continue;
-      }
-
-      //Check if UsbIo is on any handles in the device path.
-      Status = gBS->LocateDevicePath(&gEfiUsbIoProtocolGuid, &FileSystemDevicePath, &UsbDeviceHandle);
-      if (EFI_ERROR(Status)) {
-        continue;
-      }
-
-      //Check if Usb stick has a magic EBL file.
-      LoadImageDevicePath = FileDevicePath(HandleBuffer[Index], L"Ebl.efi");
-      Status = gBS->LoadImage (TRUE, gImageHandle, LoadImageDevicePath, NULL, 0, &ImageHandle);
-      if (EFI_ERROR(Status)) {
-        continue;
-      }
-
-      //Boot to Shell on USB stick.
-      Status = gBS->StartImage (ImageHandle, NULL, NULL);
-      if (EFI_ERROR(Status)) {
-        continue;
-      }
-    }
-  }
-
-  //
-  // Normal UEFI behavior is to process Globally Defined Variables as defined in Chapter 3
-  // (Boot Manager) of the UEFI specification. For this embedded system we don't do this.
-  //
-
-  //
-  // Search all the FVs for an application with a UI Section of Ebl. A .FDF file can be used
-  // to control the names of UI sections in an FV.
-  //
-  Status = FindApplicationMatchingUiSection (L"Ebl", &FvHandle, &NameGuid);
-  if (!EFI_ERROR (Status)) {
-
-    //Boot to Shell.
-    Status = LoadPeCoffSectionFromFv (FvHandle, &NameGuid);
-
-    if (EFI_ERROR(Status)) {
-      DEBUG((EFI_D_ERROR, "Boot from Shell failed. Status: %r\n", Status));
-    }
-  }
-
-  //
-  // EFI does not define the behaviour if all boot attemps fail and the last one returns.
-  // So we make a policy choice to reset the system since this BDS does not have a UI.
-  //
-  gRT->ResetSystem (EfiResetShutdown, Status, 0, NULL);
-
-  return ;
-}
-
-
-EFI_STATUS
-EFIAPI
-BdsInitialize (
-  IN EFI_HANDLE                            ImageHandle,
-  IN EFI_SYSTEM_TABLE                      *SystemTable
-  )
-{
-  EFI_STATUS  Status;
-
-  //
-  // Install protocol interface
-  //
-  Status = gBS->InstallMultipleProtocolInterfaces (
-                  &ImageHandle,
-                  &gEfiBdsArchProtocolGuid, &gBdsProtocol,
-                  NULL
-                  );
-  ASSERT_EFI_ERROR (Status);
-
-  return Status;
-}
-
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Bds/BdsEntry.h b/Platforms/TexasInstruments/BeagleBoard/Bds/BdsEntry.h
deleted file mode 100644
index 646f7b2..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Bds/BdsEntry.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __BDS_ENTRY_H__
-#define __BDS_ENTRY_H__
-
-#include <PiDxe.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PrintLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/HobLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/PcdLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PrintLib.h>
-#include <Library/PerformanceLib.h>
-
-#include <Protocol/Bds.h>
-#include <Protocol/SerialIo.h>
-#include <Protocol/FirmwareVolume2.h>
-#include <Protocol/SimpleTextIn.h>
-#include <Protocol/SimpleTextOut.h>
-#include <Protocol/EmbeddedDevice.h>
-#include <Protocol/DevicePath.h>
-#include <Protocol/SimpleFileSystem.h>
-#include <Protocol/UsbIo.h>
-
-
-EFI_STATUS
-LoadPeCoffSectionFromFv (
- IN  EFI_HANDLE   FvHandle,
- IN  EFI_GUID     *NameGuid
- );
-
-EFI_STATUS
-FindApplicationMatchingUiSection (
-  IN  CHAR16      *UiString,
-  OUT EFI_HANDLE  *FvHandle,
-  OUT EFI_GUID    *NameGuid
-  );
-
-VOID
-EFIAPI
-BdsEntry (
-  IN EFI_BDS_ARCH_PROTOCOL  *This
-  );
-
-#endif
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Bds/FirmwareVolume.c b/Platforms/TexasInstruments/BeagleBoard/Bds/FirmwareVolume.c
deleted file mode 100644
index 31e1c51..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Bds/FirmwareVolume.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/** @file
-  The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements
-  of the UEFI specification as it is designed to implement an embedded systmes
-  propriatary boot scheme.
-
-  This template assume a DXE driver produces a SerialIo protocol not using the EFI
-  driver module and it will attempt to connect a console on top of this.
-
-
-  Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BdsEntry.h"
-
-
-EFI_STATUS
-FindApplicationMatchingUiSection (
-  IN  CHAR16      *UiString,
-  OUT EFI_HANDLE  *FvHandle,
-  OUT EFI_GUID    *NameGuid
-  )
-{
-  EFI_STATUS                    Status;
-  EFI_STATUS                    NextStatus;
-  UINTN                         NoHandles;
-  EFI_HANDLE                    *Buffer;
-  UINTN                         Index;
-  EFI_FV_FILETYPE               FileType;
-  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
-  VOID                          *Key;
-  EFI_FV_FILE_ATTRIBUTES        Attributes;
-  UINTN                         Size;
-  UINTN                         UiStringLen;
-  CHAR16                        *UiSection;
-  UINT32                        Authentication;
-
-
-  UiStringLen = 0;
-  if (UiString != NULL) {
-    DEBUG ((DEBUG_ERROR, "UiString %s\n", UiString));
-    UiStringLen = StrLen (UiString);
-  }
-
-  Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiFirmwareVolume2ProtocolGuid, NULL, &NoHandles, &Buffer);
-  if (!EFI_ERROR (Status)) {
-    for (Index = 0; Index < NoHandles; Index++) {
-      Status = gBS->HandleProtocol (Buffer[Index], &gEfiFirmwareVolume2ProtocolGuid, (VOID **)&Fv);
-      if (!EFI_ERROR (Status)) {
-        Key = AllocatePool (Fv->KeySize);
-        ASSERT (Key != NULL);
-        ZeroMem (Key, Fv->KeySize);
-
-        FileType = EFI_FV_FILETYPE_APPLICATION;
-
-        do {
-          NextStatus = Fv->GetNextFile (Fv, Key, &FileType, NameGuid, &Attributes, &Size);
-          if (!EFI_ERROR (NextStatus)) {
-            if (UiString == NULL) {
-              //
-              // If UiString is NULL match first application we find.
-              //
-              *FvHandle = Buffer[Index];
-              FreePool (Key);
-              return Status;
-            }
-
-            UiSection = NULL;
-            Status = Fv->ReadSection (
-                          Fv,
-                          NameGuid,
-                          EFI_SECTION_USER_INTERFACE,
-                          0,
-                          (VOID **)&UiSection,
-                          &Size,
-                          &Authentication
-                          );
-            if (!EFI_ERROR (Status)) {
-              if (StrnCmp (UiString, UiSection, UiStringLen) == 0) {
-                //
-                // We found a UiString match.
-                //
-                *FvHandle = Buffer[Index];
-                FreePool (Key);
-                FreePool (UiSection);
-                return Status;
-              }
-              FreePool (UiSection);
-            }
-          }
-        } while (!EFI_ERROR (NextStatus));
-
-        FreePool (Key);
-      }
-    }
-
-    FreePool (Buffer);
-   }
-
-  return EFI_NOT_FOUND;
-}
-
-
-EFI_DEVICE_PATH *
-FvFileDevicePath (
-  IN  EFI_HANDLE   FvHandle,
-  IN  EFI_GUID     *NameGuid
-  )
-{
-  EFI_DEVICE_PATH_PROTOCOL          *DevicePath;
-  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH NewNode;
-
-  DevicePath = DevicePathFromHandle (FvHandle);
-
-  EfiInitializeFwVolDevicepathNode (&NewNode, NameGuid);
-
-  return AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&NewNode);
-}
-
-
-
-EFI_STATUS
-LoadPeCoffSectionFromFv (
- IN  EFI_HANDLE   FvHandle,
- IN  EFI_GUID     *NameGuid
- )
-{
-  EFI_STATUS                    Status;
-  EFI_DEVICE_PATH_PROTOCOL      *DevicePath;
-  EFI_HANDLE                    ImageHandle;
-
-  DevicePath = FvFileDevicePath (FvHandle, NameGuid);
-
-  Status = gBS->LoadImage (TRUE, gImageHandle, DevicePath, NULL, 0, &ImageHandle);
-  if (!EFI_ERROR (Status)) {
-    PERF_END (NULL, "BDS", NULL, 0);
-    Status = gBS->StartImage (ImageHandle, NULL, NULL);
-  }
-
-  return Status;
-}
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc b/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc
deleted file mode 100644
index 73c8d6a..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc
+++ /dev/null
@@ -1,482 +0,0 @@
-#/** @file
-# Beagle board package.
-#
-# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-#
-#    This program and the accompanying materials
-#    are licensed and made available under the terms and conditions of the BSD License
-#    which accompanies this distribution. The full text of the license may be found at
-#    http://opensource.org/licenses/bsd-license.php
-#
-#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
-  PLATFORM_NAME                  = BeagleBoardPkg
-  PLATFORM_GUID                  = 91fa6c28-33df-46ac-aee6-292d6811ea31
-  PLATFORM_VERSION               = 0.1
-  DSC_SPECIFICATION              = 0x00010005
-  OUTPUT_DIRECTORY               = Build/BeagleBoard
-  SUPPORTED_ARCHITECTURES        = ARM
-  BUILD_TARGETS                  = DEBUG|RELEASE
-  SKUID_IDENTIFIER               = DEFAULT
-  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.fdf
-
-
-[LibraryClasses.common]
-  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
-  ArmPlatformLib|OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardLib.inf
-  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
-  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
-  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
-
-  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
-  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
-
-!if $(TARGET) == RELEASE
-  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
-  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
-!else
-  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
-#  UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
-!endif
-  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
-
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-
-  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
-  BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
-
-  EfiResetSystemLib|OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Library/ResetSystemLib/ResetSystemLib.inf
-
-  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
-  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
-  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
-
-  EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
-
-  # These libraries are used by the dynamic EFI Shell commands
-  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
-  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
-  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
-
-  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
-
-  #
-  # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
-  # in the debugger will show load and unload commands for symbols. You can cut and paste this
-  # into the command window to load symbols. We should be able to use a script to do this, but
-  # the version of RVD I have does not support scipts accessing system memory.
-  #
-#  PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
-  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
-#  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
-
-
-  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
-  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
-  CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
-  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
-
-  SerialPortLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/SerialPortLib/SerialPortLib.inf
-  SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
-
-  RealTimeClockLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/RealTimeClockLib/RealTimeClockLib.inf
-
-  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
-
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
-  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
-  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
-  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
-  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
-
-  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
-  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
-
-#
-# Assume everything is fixed at build
-#
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-
-  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
-
-  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
-
-  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
-
-  TimerLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
-  OmapLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapLib/OmapLib.inf
-  OmapDmaLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/OmapDmaLib.inf
-  DebugAgentTimerLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
-
-  GdbSerialLib|OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/GdbSerialLib/GdbSerialLib.inf
-  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
-  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
-  DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
-
-  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
-  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
-  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
-
-[LibraryClasses.common.SEC]
-  ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
-
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
-  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
-  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
-  LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
-
-  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
-
-  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
-  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
-  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
-  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
-  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
-  MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
-
-  # 1/123 faster than Stm or Vstm version
-  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-
-  # Uncomment to turn on GDB stub in SEC.
-  #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
-
-[LibraryClasses.common.PEI_CORE]
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
-
-[LibraryClasses.common.DXE_CORE]
-  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
-  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
-  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
-  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
-  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
-#  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
-  PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
-
-  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
-
-
-[LibraryClasses.common.DXE_DRIVER]
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
-  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
-  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
-
-[LibraryClasses.common.UEFI_APPLICATION]
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
-  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
-  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
-
-[LibraryClasses.common.UEFI_DRIVER]
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
-  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
-  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
-  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
-
-[LibraryClasses.common.DXE_RUNTIME_DRIVER]
-  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
-  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-  ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
-  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
-#  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
-  PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
-
-
-[LibraryClasses.ARM]
-  #
-  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
-  # This library provides the instrinsic functions generate by a given compiler.
-  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
-  #
-  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
-
-  # Add support for GCC stack protector
-  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
-
-[BuildOptions]
-  XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
-
-  GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
-
-  RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8
-
-################################################################################
-#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
-#
-################################################################################
-
-[PcdsFeatureFlag.common]
-  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
-
-  #
-  # Control what commands are supported from the UI
-  # Turn these on and off to add features or save size
-  #
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
-
-  gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
-
-  # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
-  gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
-
-  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
-  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
-
-  gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
-
-  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
-  #  It could be set FALSE to save size.
-  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
-
-[PcdsFixedAtBuild.common]
-  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Beagle Board"
-
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"BeagleEdk2"
-  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
-  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
-  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
-  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
-  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
-  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
-  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
-  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
-
-# DEBUG_ASSERT_ENABLED       0x01
-# DEBUG_PRINT_ENABLED        0x02
-# DEBUG_CODE_ENABLED         0x04
-# CLEAR_MEMORY_ENABLED       0x08
-# ASSERT_BREAKPOINT_ENABLED  0x10
-# ASSERT_DEADLOOP_ENABLED    0x20
-!if $(TARGET) == RELEASE
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
-!else
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
-!endif
-
-#  DEBUG_INIT      0x00000001  // Initialization
-#  DEBUG_WARN      0x00000002  // Warnings
-#  DEBUG_LOAD      0x00000004  // Load events
-#  DEBUG_FS        0x00000008  // EFI File system
-#  DEBUG_POOL      0x00000010  // Alloc & Free's
-#  DEBUG_PAGE      0x00000020  // Alloc & Free's
-#  DEBUG_INFO      0x00000040  // Verbose
-#  DEBUG_DISPATCH  0x00000080  // PEI/DXE Dispatchers
-#  DEBUG_VARIABLE  0x00000100  // Variable
-#  DEBUG_BM        0x00000400  // Boot Manager
-#  DEBUG_BLKIO     0x00001000  // BlkIo Driver
-#  DEBUG_NET       0x00004000  // SNI Driver
-#  DEBUG_UNDI      0x00010000  // UNDI Driver
-#  DEBUG_LOADFILE  0x00020000  // UNDI Driver
-#  DEBUG_EVENT     0x00080000  // Event messages
-#  DEBUG_ERROR     0x80000000  // Error
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
-
-  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
-
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
-
-#
-# Optional feature to help prevent EFI memory map fragments
-# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
-# Values are in EFI Pages (4K). DXE Core will make sure that
-# at least this much of each type of memory can be allocated
-# from a single memory range. This way you only end up with
-# maximum of two fragements for each type in the memory map
-# (the memory used, and the free memory that was prereserved
-# but not used).
-#
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
-  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
-
-
-#
-# Beagle board Specific PCDs
-#
-  gArmTokenSpaceGuid.PcdVFPEnabled|1
-
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x08000000
-
-  # Size of the region used by UEFI in permanent memory (Reserved 16MB)
-  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x01000000
-
-  # Size of the region reserved for fixed address allocations (Reserved 32MB)
-  gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x02000000
-
-  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80008000
-  gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
-
-  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds|77
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|13000000
-
-  # We want to use the Shell Libraries but don't want it to initialise
-  # automatically. We initialise the libraries when the command is called by the
-  # Shell.
-  gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
-
-  #
-  # ARM Pcds
-  #
-  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
-
-  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SD"
-  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(B615F1F5-5088-43CD-809C-A16E52487D00)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/Image"
-  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=tty0 console=ttyS2,115200n8 root=UUID=a4af765b-c2b5-48f4-9564-7a4e9104c4f6 rootwait ro earlyprintk"
-  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10
-
-  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(E68088EF-D1A4-4336-C1DB-4D3A204730A6)"
-  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
-
-################################################################################
-#
-# Components Section - list of all EDK II Modules needed by this Platform
-#
-################################################################################
-[Components.common]
-
-  #
-  # SEC
-  #
-  ArmPlatformPkg/PrePi/PeiUniCore.inf
-
-  #
-  # DXE
-  #
-  MdeModulePkg/Core/Dxe/DxeMain.inf {
-    <LibraryClasses>
-      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
-      NULL|EmbeddedPkg/Library/LzmaHobCustomDecompressLib/LzmaHobCustomDecompressLib.inf
-  }
-
-  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
-
-  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
-  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
-  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
-
-  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
-  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
-  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
-  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
-  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
-#
-# This version uses semi-hosting console
-#  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf {
-#    <LibraryClasses>
-#      SerialPortLib|ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
-#  }
-
-  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
-  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
-
-  #
-  # Semi-hosting filesystem
-  #
-  ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
-
-  #
-  # FAT filesystem + GPT/MBR partitioning
-  #
-  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
-  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
-  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-
-  #
-  # USB
-  #
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/PciEmulation/PciEmulation.inf
-
-  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf {
-    <PcdsFixedAtBuild>
-      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800fffff
-  }
-
-  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
-  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-
-  #
-  # Nand Flash
-  #
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Flash/Flash.inf
-
-  #
-  # MMC/SD
-  #
-  EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MmcHostDxe/MmcHostDxe.inf
-
-  #
-  # I2C
-  #
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/SmbusDxe/Smbus.inf
-
-  #
-  # SoC Drivers
-  #
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Gpio/Gpio.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/InterruptDxe/InterruptDxe.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/TimerDxe/TimerDxe.inf
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
-
-  #
-  # Power IC
-  #
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/TPS65950Dxe/TPS65950.inf
-
-  #
-  # Bds
-  #
-  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-  ArmPlatformPkg/Bds/Bds.inf
-
-  # Legacy Linux Loader
-  ArmPkg/Application/LinuxLoader/LinuxLoader.inf
-
-  #
-  # Example Application
-  #
-  MdeModulePkg/Application/HelloWorld/HelloWorld.inf
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/ConfigurationHeader.dat b/Platforms/TexasInstruments/BeagleBoard/ConfigurationHeader.dat
deleted file mode 100644
index 5f6897e..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/ConfigurationHeader.dat
+++ /dev/null
@@ -1,41 +0,0 @@
-PRM_CLKSRC_CTRL=0x00000080
-PRM_CLKSEL=0x00000003
-CM_CLKSEL1_EMU=0x03020A50
-CM_CLKSEL_CORE=0x0000030A
-CM_CLKSEL_WKUP=0x00000015
-CM_CLKEN_PLL_DPLL3=0x00370037
-CM_AUTOIDLE_PLL_DPLL3=0x00000000
-CM_CLKSEL1_PLL=0x094C0C00
-CM_CLKEN_PLL_DPLL4=0x00370037
-CM_AUTOIDLE_PLL_DPLL4=0x00000000
-CM_CLKSEL2_PLL=0x0001B00C
-CM_CLKSEL3_PLL=0x00000009
-CM_CLKEN_PLL_MPU=0x00000037
-CM_AUTOIDLE_PLL_MPU=0x00000000
-CM_CLKSEL1_PLL_MPU=0x0011F40C
-CM_CLKSEL2_PLL_MPU=0x00000001
-CM_CLKSTCTRL_MPU=0x00000000
-SDRC_SYSCONFIG_LSB=0x0000
-SDRC_CS_CFG_LSB=0x0001
-SDRC_SHARING_LSB=0x0100
-SDRC_ERR_TYPE_LSB=0x0000
-SDRC_DLLA_CTRL=0x0000000A
-SDRC_POWER=0x00000081
-MEMORY_TYPE_CS0=0x0003
-SDRC_MCFG_0=0x02D04011
-SDRC_MR_0_LSB=0x0032
-SDRC_EMR1_0_LSB=0x0000
-SDRC_EMR2_0_LSB=0x0000
-SDRC_EMR3_0_LSB=0x0000
-SDRC_ACTIM_CTRLA_0=0xBA9DC4C6
-SDRC_ACTIM_CTRLB_0=0x00012522
-SDRC_RFRCTRL_0=0x0004E201
-MEMORY_TYPE_CS1=0x0003
-SDRC_MCFG_1=0x02D04011
-SDRC_MR_1_LSB=0x0032
-SDRC_EMR1_1_LSB=0x0000
-SDRC_EMR2_1_LSB=0x0000
-SDRC_EMR3_1_LSB=0x0000
-SDRC_ACTIM_CTRLA_1=0xBA9DC4C6
-SDRC_ACTIM_CTRLB_1=0x00012522
-SDRC_RFRCTRL_1=0x0004E201
diff --git a/Platforms/TexasInstruments/BeagleBoard/Contributions.txt b/Platforms/TexasInstruments/BeagleBoard/Contributions.txt
deleted file mode 100644
index f87cbd7..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Contributions.txt
+++ /dev/null
@@ -1,218 +0,0 @@
-
-======================
-= Code Contributions =
-======================
-
-To make a contribution to a TianoCore project, follow these steps.
-1. Create a change description in the format specified below to
-   use in the source control commit log.
-2. Your commit message must include your "Signed-off-by" signature,
-   and "Contributed-under" message.
-3. Your "Contributed-under" message explicitly states that the
-   contribution is made under the terms of the specified
-   contribution agreement.  Your "Contributed-under" message
-   must include the name of contribution agreement and version.
-   For example: Contributed-under: TianoCore Contribution Agreement 1.0
-   The "TianoCore Contribution Agreement" is included below in
-   this document.
-4. Submit your code to the TianoCore project using the process
-   that the project documents on its web page.  If the process is
-   not documented, then submit the code on development email list
-   for the project.
-5. It is preferred that contributions are submitted using the same
-   copyright license as the base project. When that is not possible,
-   then contributions using the following licenses can be accepted:
-   * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
-   * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
-   * MIT: http://opensource.org/licenses/MIT
-   * Python-2.0: http://opensource.org/licenses/Python-2.0
-   * Zlib: http://opensource.org/licenses/Zlib
-
-   Contributions of code put into the public domain can also be
-   accepted.
-
-   Contributions using other licenses might be accepted, but further
-   review will be required.
-
-=====================================================
-= Change Description / Commit Message / Patch Email =
-=====================================================
-
-Your change description should use the standard format for a
-commit message, and must include your "Signed-off-by" signature
-and the "Contributed-under" message.
-
-== Sample Change Description / Commit Message =
-
-=== Start of sample patch email message ===
-
-From: Contributor Name <contributor@example.com>
-Subject: [PATCH] CodeModule: Brief-single-line-summary
-
-Full-commit-message
-
-Contributed-under: TianoCore Contribution Agreement 1.0
-Signed-off-by: Contributor Name <contributor@example.com>
----
-
-An extra message for the patch email which will not be considered part
-of the commit message can be added here.
-
-Patch content inline or attached
-
-=== End of sample patch email message ===
-
-=== Notes for sample patch email ===
-
-* The first line of commit message is taken from the email's subject
-  line following [PATCH]. The remaining portion of the commit message
-  is the email's content until the '---' line.
-* git format-patch is one way to create this format
-
-=== Definitions for sample patch email ===
-
-* "CodeModule" is a short idenfier for the affected code.  For
-  example MdePkg, or MdeModulePkg UsbBusDxe.
-* "Brief-single-line-summary" is a short summary of the change.
-* The entire first line should be less than ~70 characters.
-* "Full-commit-message" a verbose multiple line comment describing
-  the change.  Each line should be less than ~70 characters.
-* "Contributed-under" explicitely states that the contribution is
-  made under the terms of the contribtion agreement.  This
-  agreement is included below in this document.
-* "Signed-off-by" is the contributor's signature identifying them
-  by their real/legal name and their email address.
-
-========================================
-= TianoCore Contribution Agreement 1.0 =
-========================================
-
-INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
-INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
-PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
-TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
-TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
-REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
-CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
-OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
-BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
-AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
-AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
-USE THE CONTENT.
-
-Unless otherwise indicated, all Content made available on the TianoCore
-site is provided to you under the terms and conditions of the BSD
-License ("BSD"). A copy of the BSD License is available at
-http://opensource.org/licenses/bsd-license.php
-or when applicable, in the associated License.txt file.
-
-Certain other content may be made available under other licenses as
-indicated in or with such Content. (For example, in a License.txt file.)
-
-You accept and agree to the following terms and conditions for Your
-present and future Contributions submitted to TianoCore site. Except
-for the license granted to Intel hereunder, You reserve all right,
-title, and interest in and to Your Contributions.
-
-== SECTION 1: Definitions ==
-* "You" or "Contributor" shall mean the copyright owner or legal
-  entity authorized by the copyright owner that is making a
-  Contribution hereunder. All other entities that control, are
-  controlled by, or are under common control with that entity are
-  considered to be a single Contributor. For the purposes of this
-  definition, "control" means (i) the power, direct or indirect, to
-  cause the direction or management of such entity, whether by
-  contract or otherwise, or (ii) ownership of fifty percent (50%)
-  or more of the outstanding shares, or (iii) beneficial ownership
-  of such entity.
-* "Contribution" shall mean any original work of authorship,
-  including any modifications or additions to an existing work,
-  that is intentionally submitted by You to the TinaoCore site for
-  inclusion in, or documentation of, any of the Content. For the
-  purposes of this definition, "submitted" means any form of
-  electronic, verbal, or written communication sent to the
-  TianoCore site or its representatives, including but not limited
-  to communication on electronic mailing lists, source code
-  control systems, and issue tracking systems that are managed by,
-  or on behalf of, the TianoCore site for the purpose of
-  discussing and improving the Content, but excluding
-  communication that is conspicuously marked or otherwise
-  designated in writing by You as "Not a Contribution."
-
-== SECTION 2: License for Contributions ==
-* Contributor hereby agrees that redistribution and use of the
-  Contribution in source and binary forms, with or without
-  modification, are permitted provided that the following
-  conditions are met:
-** Redistributions of source code must retain the Contributor's
-   copyright notice, this list of conditions and the following
-   disclaimer.
-** Redistributions in binary form must reproduce the Contributor's
-   copyright notice, this list of conditions and the following
-   disclaimer in the documentation and/or other materials provided
-   with the distribution.
-* Disclaimer. None of the names of Contributor, Intel, or the names
-  of their respective contributors may be used to endorse or
-  promote products derived from this software without specific
-  prior written permission.
-* Contributor grants a license (with the right to sublicense) under
-  claims of Contributor's patents that Contributor can license that
-  are infringed by the Contribution (as delivered by Contributor) to
-  make, use, distribute, sell, offer for sale, and import the
-  Contribution and derivative works thereof solely to the minimum
-  extent necessary for licensee to exercise the granted copyright
-  license; this patent license applies solely to those portions of
-  the Contribution that are unmodified. No hardware per se is
-  licensed.
-* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
-  CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
-  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-  CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
-  CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-  DAMAGE.
-
-== SECTION 3: Representations ==
-* You represent that You are legally entitled to grant the above
-  license. If your employer(s) has rights to intellectual property
-  that You create that includes Your Contributions, You represent
-  that You have received permission to make Contributions on behalf
-  of that employer, that Your employer has waived such rights for
-  Your Contributions.
-* You represent that each of Your Contributions is Your original
-  creation (see Section 4 for submissions on behalf of others).
-  You represent that Your Contribution submissions include complete
-  details of any third-party license or other restriction
-  (including, but not limited to, related patents and trademarks)
-  of which You are personally aware and which are associated with
-  any part of Your Contributions.
-
-== SECTION 4: Third Party Contributions ==
-* Should You wish to submit work that is not Your original creation,
-  You may submit it to TianoCore site separately from any
-  Contribution, identifying the complete details of its source
-  and of any license or other restriction (including, but not
-  limited to, related patents, trademarks, and license agreements)
-  of which You are personally aware, and conspicuously marking the
-  work as "Submitted on behalf of a third-party: [named here]".
-
-== SECTION 5: Miscellaneous ==
-* Applicable Laws. Any claims arising under or relating to this
-  Agreement shall be governed by the internal substantive laws of
-  the State of Delaware or federal courts located in Delaware,
-  without regard to principles of conflict of laws.
-* Language. This Agreement is in the English language only, which
-  language shall be controlling in all respects, and all versions
-  of this Agreement in any other language shall be for accommodation
-  only and shall not be binding. All communications and notices made
-  or given pursuant to this Agreement, and all documentation and
-  support to be provided, unless otherwise noted, shall be in the
-  English language.
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_boot_from_ram.inc b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_boot_from_ram.inc
deleted file mode 100644
index a4e9674..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_boot_from_ram.inc
+++ /dev/null
@@ -1,21 +0,0 @@
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-error = continue
-unload
-error = abort
-
-setreg @CP15_CONTROL = 0x0005107E
-setreg @pc=0x80008208
-setreg @cpsr=0x000000D3
-dis/D
-readfile,raw,nowarn "ZZZZZZ/FV/BEAGLEBOARD_EFI.fd"=0x80008000
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_convert_symbols.sh b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_convert_symbols.sh
deleted file mode 100755
index 67fdfe1..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_convert_symbols.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/bin/sh
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#  
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http:#opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-
-IN=`/usr/bin/cygpath -u $1`
-OUT=`/usr/bin/cygpath -u $2`
-
-/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \
-             -e 's:\\:/:g' \
-             -e "s/^/load\/a\/ni\/np \"/g" \
-             -e "s/dll /dll\" \&/g" \
-              $IN | /usr/bin/sort.exe --key=3 --output=$OUT
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_dummy.axf b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_dummy.axf
deleted file mode 100755
index 17fabaa..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_dummy.axf
+++ /dev/null
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_hw_setup.inc b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_hw_setup.inc
deleted file mode 100644
index dbce4df..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_hw_setup.inc
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-error = continue
-unload
-error = abort
-
-setreg @CP15_CONTROL = 0x0005107E
-setreg @cpsr=0x000000D3
-
-; General clock settings.
-setmem /32 0x48307270=0x00000080
-setmem /32 0x48306D40=0x00000003
-setmem /32 0x48005140=0x03020A50
-
-;Clock configuration
-setmem /32 0x48004A40=0x0000030A
-setmem /32 0x48004C40=0x00000015
-
-;DPLL3 (Core) settings
-setmem /32 0x48004D00=0x00370037
-setmem /32 0x48004D30=0x00000000
-setmem /32 0x48004D40=0x094C0C00
-
-;DPLL4 (Peripheral) settings
-setmem /32 0x48004D00=0x00370037
-setmem /32 0x48004D30=0x00000000
-setmem /32 0x48004D44=0x0001B00C
-setmem /32 0x48004D48=0x00000009
-
-;DPLL1 (MPU) settings
-setmem /32 0x48004904=0x00000037
-setmem /32 0x48004934=0x00000000
-setmem /32 0x48004940=0x0011F40C
-setmem /32 0x48004944=0x00000001
-setmem /32 0x48004948=0x00000000
-
-;RAM setup.
-setmem /16 0x6D000010=0x0000
-setmem /16 0x6D000040=0x0001
-setmem /16 0x6D000044=0x0100
-setmem /16 0x6D000048=0x0000
-setmem /32 0x6D000060=0x0000000A
-setmem /32 0x6D000070=0x00000081
-setmem /16 0x6D000040=0x0003
-setmem /32 0x6D000080=0x02D04011
-setmem /16 0x6D000084=0x0032
-setmem /16 0x6D00008C=0x0000
-setmem /32 0x6D00009C=0xBA9DC4C6
-setmem /32 0x6D0000A0=0x00012522
-setmem /32 0x6D0000A4=0x0004E201
-setmem /16 0x6D000040=0x0003
-setmem /32 0x6D0000B0=0x02D04011
-setmem /16 0x6D0000B4=0x0032
-setmem /16 0x6D0000BC=0x0000
-setmem /32 0x6D0000C4=0xBA9DC4C6
-setmem /32 0x6D0000C8=0x00012522
-setmem /32 0x6D0000D4=0x0004E201
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_load_symbols.inc b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_load_symbols.inc
deleted file mode 100644
index 33e3eac..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_load_symbols.inc
+++ /dev/null
@@ -1,23 +0,0 @@
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-include 'ZZZZZZ/rvi_symbols_macros.inc'
-
-macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000)
-
-host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc"
-include 'ZZZZZZ/rvi_symbols.inc'
-load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata
-unload rvi_dummy.axf
-delfile rvi_dummy.axf
-
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_symbols_macros.inc b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_symbols_macros.inc
deleted file mode 100755
index 0fc2c64..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_symbols_macros.inc
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-define /R int compare_guid(guid1, guid2)
-    unsigned char *guid1;
-    unsigned char *guid2;
-{
-    return strncmp(guid1, guid2, 16);
-}
-.
-
-define /R unsigned char * find_system_table(mem_start, mem_size)
-    unsigned char *mem_start;
-    unsigned long mem_size;
-{
-    unsigned char *mem_ptr;
-
-    mem_ptr = mem_start + mem_size;
-
-    do
-    {
-        mem_ptr -= 0x400000; // 4 MB
-
-        if (strncmp(mem_ptr, "IBI SYST", 8) == 0)
-        {
-            return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase
-        }
-
-    } while (mem_ptr > mem_start);
-
-    return 0;
-}
-.
-
-define /R unsigned char * find_debug_info_table_header(system_table)
-    unsigned char *system_table;
-{
-    unsigned long configuration_table_entries;
-    unsigned char *configuration_table;
-    unsigned long index;
-    unsigned char debug_table_guid[16];
-
-    // Fill in the debug table's guid
-    debug_table_guid[ 0] = 0x77;
-    debug_table_guid[ 1] = 0x2E;
-    debug_table_guid[ 2] = 0x15;
-    debug_table_guid[ 3] = 0x49;
-    debug_table_guid[ 4] = 0xDA;
-    debug_table_guid[ 5] = 0x1A;
-    debug_table_guid[ 6] = 0x64;
-    debug_table_guid[ 7] = 0x47;
-    debug_table_guid[ 8] = 0xB7;
-    debug_table_guid[ 9] = 0xA2;
-    debug_table_guid[10] = 0x7A;
-    debug_table_guid[11] = 0xFE;
-    debug_table_guid[12] = 0xFE;
-    debug_table_guid[13] = 0xD9;
-    debug_table_guid[14] = 0x5E;
-    debug_table_guid[15] = 0x8B;
-
-    configuration_table_entries = *(unsigned long *)(system_table + 64);
-    configuration_table         = *(unsigned long *)(system_table + 68);
-
-    for (index = 0; index < configuration_table_entries; index++)
-    {
-        if (compare_guid(configuration_table, debug_table_guid) == 0)
-        {
-            return *(unsigned long *)(configuration_table + 16);
-        }
-
-        configuration_table += 20;
-    }
-
-    return 0;
-}
-.
-
-define /R int valid_pe_header(header)
-        unsigned char *header;
-{
-    if ((header[0x00] == 'M') &&
-        (header[0x01] == 'Z') &&
-        (header[0x80] == 'P') &&
-        (header[0x81] == 'E'))
-    {
-        return 1;
-    }
-
-    return 0;
-}
-.
-
-define /R unsigned long pe_headersize(header)
-        unsigned char *header;
-{
-    unsigned long *size;
-
-    size = header + 0x00AC;
-
-    return *size;
-}
-.
-
-define /R unsigned char *pe_filename(header)
-        unsigned char *header;
-{
-    unsigned long *debugOffset;
-    unsigned char *stringOffset;
-
-    if (valid_pe_header(header))
-    {
-        debugOffset  = header + 0x0128;
-        stringOffset = header + *debugOffset + 0x002C;
-
-        return stringOffset;
-    }
-
-    return 0;
-}
-.
-
-define /R int char_is_valid(c)
-        unsigned char c;
-{
-    if (c >= 32 && c < 127)
-    	return 1;
-
-    return 0;
-}
-.
-
-define /R write_symbols_file(filename, mem_start, mem_size)
-    unsigned char *filename;
-    unsigned char *mem_start;
-    unsigned long mem_size;
-{
-    unsigned char *system_table;
-    unsigned char *debug_info_table_header;
-    unsigned char *debug_info_table;
-    unsigned long debug_info_table_size;
-    unsigned long index;
-    unsigned char *debug_image_info;
-    unsigned char *loaded_image_protocol;
-    unsigned char *image_base;
-    unsigned char *debug_filename;
-    unsigned long header_size;
-    int           status;
-
-    system_table = find_system_table(mem_start, mem_size);
-    if (system_table == 0)
-    {
-        return;
-    }
-
-    status = fopen(88, filename, "w");
-
-    debug_info_table_header = find_debug_info_table_header(system_table);
-
-    debug_info_table      = *(unsigned long *)(debug_info_table_header + 8);
-    debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4);
-
-    for (index = 0; index < (debug_info_table_size * 4); index += 4)
-    {
-        debug_image_info = *(unsigned long *)(debug_info_table + index);
-
-        if (debug_image_info == 0)
-        {
-            break;
-        }
-
-        loaded_image_protocol = *(unsigned long *)(debug_image_info + 4);
-
-        image_base = *(unsigned long *)(loaded_image_protocol + 32);
-
-        debug_filename = pe_filename(image_base);
-        header_size    = pe_headersize(image_base);
-
-        $fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$;
-    }
-
-
-    fclose(88);
-}
-.
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_unload_symbols.inc b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_unload_symbols.inc
deleted file mode 100755
index b00a132..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/rvi_unload_symbols.inc
+++ /dev/null
@@ -1,118 +0,0 @@
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-error = continue
-
-unload
-
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-delfile 1
-
-error = abort
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/trace32_load_symbols.cmm b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/trace32_load_symbols.cmm
deleted file mode 100644
index 1bae172..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/trace32_load_symbols.cmm
+++ /dev/null
@@ -1,211 +0,0 @@
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//  
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-  ENTRY &ram_start &ram_size
-  
-  ;If system is running then stop the execution so we can load symbols.
-  break
-  
-  ;Reset all windows
-  WINPAGE.RESET
-  
-  ;Create AREA to display the symbols we are loading.
-  AREA.Reset
-  AREA.Create SYMBOL 300. 100.
-  AREA.View SYMBOL
-  AREA.Select SYMBOL
-  SYS.Option BE OFF
- 
-  ;Added based on suggestion from Lauterbach support.
-  MMU.TABLEWALK ON
-  MMU.ON
-
-  ;Load symbols.
-  GOSUB load_symbols &ram_start &ram_size
-
-  ;Open some windows and enable semihosting.
-  TOOLBAR ON
-  STATUSBAR ON
-  WINPAGE.RESET
-   
-  WINCLEAR
-  WINPOS 0.0 17.0 72. 13. 0. 0. W000
-  SYStem
-   
-  WINPOS 0.0 0.0 110. 55. 13. 1. W001
-  WINTABS 10. 10. 25. 62.
-  Data.List
-   
-  WINPAGE.SELECT P000
-
-  //Enable semihosting
-  System.Option.BigEndian OFF
-
-  tronchip.set swi on		// ARM9/10/11 variant
-
-  // configure and open semihosting channel
-  winpos 50% 50% 50% 50%
-  term.heapinfo 0 0x20000 0x30000 0x20000
-  term.method armswi
-  term.mode string
-  term.gate
-
-  WINPOS 115.0 0. 70. 35. 0. 1. W002
-  Var.Local %HEX
-  
-  WINPOS 115.10 45. 48. 9. 0. 0. W003
-  Register
-    
-  END
-
-find_system_table:
-  ENTRY &mem_start &mem_size
-  &mem_ptr=&mem_start+&mem_size
-  RPT    
-  (
-    &mem_ptr=&mem_ptr-0x400000  // 4 MB
-    &word1=Data.LONG(D:&mem_ptr)
-    &word2=Data.LONG(D:&mem_ptr+0x04)
-    IF &word1==0x20494249
-    (
-      IF &word2==0x54535953
-      (
-        &result=Data.LONG(D:&mem_ptr+0x08)
-        RETURN &result
-      )
-    )
-  )
-  WHILE &mem_ptr>&mem_start
-  &result=0
-  RETURN &result
-
-compare_guid:
-  ENTRY &guid
-  IF Data.LONG(D:&guid)==0x49152E77
-  (
-    IF Data.LONG(D:&guid+0x04)==0x47641ADA
-    (
-      IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7
-      (
-        IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE
-        (
-          RETURN 0
-        )
-      )
-    )
-  )
-  RETURN 1  
-
-find_debug_info_table_header:
-  ENTRY &system_table
-  &config_table_entries=Data.LONG(D:&system_table+0x40)
-  &config_table_pointer=Data.LONG(D:&system_table+0x44)
-  RPT &config_table_entries
-  (
-    GOSUB compare_guid &config_table_pointer
-    ENTRY &result
-    IF &result==0
-    (
-      &result=Data.LONG(D:&config_table_pointer+0x10)
-      RETURN &result
-    )  
-    &config_table_pointer=&config_table_pointer+0x14
-  )
-  RETURN 0;
-
-valid_pe_header:
-  ENTRY &header
-  IF Data.BYTE(D:&header+0x00)==0x4D
-  (
-    IF Data.BYTE(D:&header+0x01)==0x5A
-    (
-      IF Data.BYTE(D:&header+0x80)==0x50
-      (
-        IF Data.BYTE(D:&header+0x81)==0x45
-        (
-          RETURN 1
-        )
-      )
-    )
-  )
-  RETURN 0
-
-get_file_string:
-  ENTRY &stringOffset
-
-  local &string
-
-  &more_string=data.string(d:&stringOffset)
-
-  if (string.len("&more_string")>=128.)
-  (
-    &string="&string"+"&more_string"
-    &stringOffset=&stringOffset+string.len("&more_string")
-
-    //Get remaining file string
-    GOSUB get_file_string &stringOffset
-    ENTRY &more_string
-    &string="&string"+"&more_string"
-  )
-  else
-  (
-    &string="&string"+"&more_string"
-    &more_string=""
-  )
-  RETURN &string
- 
-load_symbol_file:
-  ENTRY &header &load_address
-  GOSUB valid_pe_header &header
-  ENTRY &result
- 
-  IF &result==1
-  (
-    &debugOffset=Data.LONG(D:&header+0x0128)
-    &stringOffset=&header+&debugOffset+0x002C
-    
-    GOSUB get_file_string &stringOffset
-    ENTRY &filestring
-        
-    PRINT "&filestring 0x" &load_address
-    TDIAG Data.load.elf &filestring &load_address /nocode /noclear
-  )
-  RETURN
-
-pe_headersize:
-  ENTRY &header;
-  RETURN Data.LONG(D:&header+0x00AC)
-
-load_symbols:
-  ENTRY &mem_start &mem_size
-  GOSUB find_system_table &mem_start &mem_size
-  ENTRY &system_table
-  GOSUB find_debug_info_table_header &system_table
-  ENTRY &debug_info_table_header
-  &debug_info_table=Data.LONG(D:&debug_info_table_header+0x08)
-  &debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04)
-  &index=0
-  RPT &debug_info_table_size
-  (
-    &debug_image_info=Data.LONG(D:&debug_info_table+&index)
-    IF &debug_image_info==0
-      RETURN        
-    &loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04);
-    &image_base=Data.LONG(D:&loaded_image_protocol+0x20);
-    GOSUB pe_headersize &image_base
-    ENTRY &header_size
-    &image_load_address=&image_base+&header_size
-    GOSUB load_symbol_file &image_base &image_load_address
-    &index=&index+0x4
-  )
-    
-  RETURN
diff --git a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/trace32_load_symbols_cygwin.cmm b/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/trace32_load_symbols_cygwin.cmm
deleted file mode 100644
index db9ff4e..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts/trace32_load_symbols_cygwin.cmm
+++ /dev/null
@@ -1,188 +0,0 @@
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//  
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-  ENTRY &ram_start &ram_size
-
-  ;If system is running then stop the execution so we can load symbols.
-  break
-  
-  ;Reset all windows
-  WINPAGE.RESET
-  
-  AREA.Reset
-  AREA.Create SYMBOL 300. 100.
-  AREA.View SYMBOL
-  AREA.Select SYMBOL
-  SYS.Option BE OFF
- 
-  ; Added based on suggestion from Lauterbach support.
-  MMU.TABLEWALK ON
-  MMU.ON
-
-  GOSUB load_symbols &ram_start &ram_size
-
-  ;Open some windows.
-  WINPOS 83.125 29.063 48. 9. 0. 0. W003
-  Register
-
-  WINPOS 83.25 10. 48. 9. 0. 1. W002
-  Var.Local
-  
-  END
-
-find_system_table:
-  ENTRY &mem_start &mem_size
-  &mem_ptr=&mem_start+&mem_size
-  RPT    
-  (
-    &mem_ptr=&mem_ptr-0x400000  // 4 MB
-    &word1=Data.LONG(D:&mem_ptr)
-    &word2=Data.LONG(D:&mem_ptr+0x04)
-    IF &word1==0x20494249
-    (
-      IF &word2==0x54535953
-      (
-        &result=Data.LONG(D:&mem_ptr+0x08)
-        RETURN &result
-      )
-    )
-  )
-  WHILE &mem_ptr>&mem_start
-  &result=0
-  RETURN &result
-
-compare_guid:
-  ENTRY &guid
-  IF Data.LONG(D:&guid)==0x49152E77
-  (
-    IF Data.LONG(D:&guid+0x04)==0x47641ADA
-    (
-      IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7
-      (
-        IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE
-        (
-          RETURN 0
-        )
-      )
-    )
-  )
-  RETURN 1  
-
-find_debug_info_table_header:
-  ENTRY &system_table
-  &config_table_entries=Data.LONG(D:&system_table+0x40)
-  &config_table_pointer=Data.LONG(D:&system_table+0x44)
-  RPT &config_table_entries
-  (
-    GOSUB compare_guid &config_table_pointer
-    ENTRY &result
-    IF &result==0
-    (
-      &result=Data.LONG(D:&config_table_pointer+0x10)
-      RETURN &result
-    )  
-    &config_table_pointer=&config_table_pointer+0x14
-  )
-  RETURN 0;
-
-valid_pe_header:
-  ENTRY &header
-  IF Data.BYTE(D:&header+0x00)==0x4D
-  (
-    IF Data.BYTE(D:&header+0x01)==0x5A
-    (
-      IF Data.BYTE(D:&header+0x80)==0x50
-      (
-        IF Data.BYTE(D:&header+0x81)==0x45
-        (
-          RETURN 1
-        )
-      )
-    )
-  )
-  RETURN 0
-
-get_file_string:
-  ENTRY &stringOffset
-
-  local &string
-  
-  &more_string=data.string(d:&stringOffset)
-
-  if (string.len("&more_string")>=128.)
-  (
-    &string="&string"+"&more_string"
-    &stringOffset=&stringOffset+string.len("&more_string")
-
-    //Get remaining file string
-    GOSUB get_file_string &stringOffset
-    ENTRY &more_string
-    &string="&string"+"&more_string"
-  )
-  else
-  (
-    &string="&string"+"&more_string"
-    &more_string=""
-  )
-  RETURN &string
- 
-load_symbol_file:
-  ENTRY &header &load_address
-  GOSUB valid_pe_header &header
-  ENTRY &result
- 
-  IF &result==1
-  (
-    &debugOffset=Data.LONG(D:&header+0x0128)
-    &stringOffset=&header+&debugOffset+0x002C
-    
-    &stringOffset=&stringOffset+11.
-
-    GOSUB get_file_string &stringOffset
-    ENTRY &filestring
-  
-    &filestring="c:"+"&filestring"
-
-    PRINT "&filestring 0x" &load_address
-    Data.load.elf &filestring &load_address /nocode /noclear
-  )
-  RETURN
-
-pe_headersize:
-  ENTRY &header;
-  RETURN Data.LONG(D:&header+0x00AC)
-
-load_symbols:
-  ENTRY &mem_start &mem_size
-  GOSUB find_system_table &mem_start &mem_size
-  ENTRY &system_table
-  GOSUB find_debug_info_table_header &system_table
-  ENTRY &debug_info_table_header
-  &debug_info_table=Data.LONG(D:&debug_info_table_header+0x08)
-  &debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04)
-  &index=0
-  RPT &debug_info_table_size
-  (
-    &debug_image_info=Data.LONG(D:&debug_info_table+&index)
-    IF &debug_image_info==0
-      RETURN        
-    &loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04);
-    &image_base=Data.LONG(D:&loaded_image_protocol+0x20);
-    GOSUB pe_headersize &image_base
-    ENTRY &header_size
-    &image_load_address=&image_base+&header_size
-    GOSUB load_symbol_file &image_base &image_load_address
-    &index=&index+0x4
-  )
-    
-  RETURN
-  
-\ No newline at end of file
diff --git a/Platforms/TexasInstruments/BeagleBoard/Include/BeagleBoard.h b/Platforms/TexasInstruments/BeagleBoard/Include/BeagleBoard.h
deleted file mode 100755
index f9955b0..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Include/BeagleBoard.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/** @file
-*  Header defining the BeagleBoard constants (Base addresses, sizes, flags)
-*
-*  Copyright (c) 2011, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __BEAGLEBOARD_PLATFORM_H__
-#define __BEAGLEBOARD_PLATFORM_H__
-
-// DDR attributes
-#define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
-#define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
-
-// SoC registers. L3 interconnects
-#define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000
-#define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000
-#define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
-
-// SoC registers. L4 interconnects
-#define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000
-#define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000
-#define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
-
-
-#if 0
-/*******************************************
-// Platform Memory Map
-*******************************************/
-
-// Can be NOR, DOC, DRAM, SRAM
-#define ARM_EB_REMAP_BASE                     0x00000000
-#define ARM_EB_REMAP_SZ                       0x04000000
-
-// Motherboard Peripheral and On-chip peripheral
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE     0x10000000
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ       0x00100000
-#define ARM_EB_BOARD_PERIPH_BASE              0x10000000
-//#define ARM_EB_CHIP_PERIPH_BASE             0x10020000
-
-// SMC
-#define ARM_EB_SMC_BASE                       0x40000000
-#define ARM_EB_SMC_SZ                         0x20000000
-
-// NOR Flash 1
-#define ARM_EB_SMB_NOR_BASE                   0x40000000
-#define ARM_EB_SMB_NOR_SZ                     0x04000000 /* 64 MB */
-// DOC Flash
-#define ARM_EB_SMB_DOC_BASE                   0x44000000
-#define ARM_EB_SMB_DOC_SZ                     0x04000000 /* 64 MB */
-// SRAM
-#define ARM_EB_SMB_SRAM_BASE                  0x48000000
-#define ARM_EB_SMB_SRAM_SZ                    0x02000000 /* 32 MB */
-// USB, Ethernet, VRAM
-#define ARM_EB_SMB_PERIPH_BASE                0x4E000000
-//#define ARM_EB_SMB_PERIPH_VRAM              0x4C000000
-#define ARM_EB_SMB_PERIPH_SZ                  0x02000000 /* 32 MB */
-
-// DRAM
-#define ARM_EB_DRAM_BASE                      0x70000000
-#define ARM_EB_DRAM_SZ                        0x10000000
-
-// Logic Tile
-#define ARM_EB_LOGIC_TILE_BASE                0xC0000000
-#define ARM_EB_LOGIC_TILE_SZ                  0x40000000
-
-/*******************************************
-// Motherboard peripherals
-*******************************************/
-
-// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)
-#define ARM_EB_SYS_FLAGS_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
-#define ARM_EB_SYS_FLAGS_SET_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
-#define ARM_EB_SYS_FLAGS_CLR_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
-#define ARM_EB_SYS_FLAGS_NV_REG               (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
-#define ARM_EB_SYS_FLAGS_NV_SET_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
-#define ARM_EB_SYS_FLAGS_NV_CLR_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
-#define ARM_EB_SYS_CLCD                       (ARM_EB_BOARD_PERIPH_BASE + 0x00050)
-#define ARM_EB_SYS_PROCID0_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
-#define ARM_EB_SYS_PROCID1_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
-#define ARM_EB_SYS_CFGDATA_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
-#define ARM_EB_SYS_CFGCTRL_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
-#define ARM_EB_SYS_CFGSTAT_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
-
-// SP810 Controller
-#define SP810_CTRL_BASE                       (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
-
-// SYSTRCL Register
-#define ARM_EB_SYSCTRL                        0x10001000
-
-// Uart0
-#define PL011_CONSOLE_UART_BASE               (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
-#define PL011_CONSOLE_UART_SPEED              115200
-
-// SP804 Timer Bases
-#define SP804_TIMER0_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
-#define SP804_TIMER1_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
-#define SP804_TIMER2_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
-#define SP804_TIMER3_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
-
-// PL301 RTC
-#define PL031_RTC_BASE                        (ARM_EB_BOARD_PERIPH_BASE + 0x17000)
-
-// Dynamic Memory Controller Base
-#define ARM_EB_DMC_BASE                       0x10018000
-
-// Static Memory Controller Base
-#define ARM_EB_SMC_CTRL_BASE                  0x10080000
-
-#define PL111_CLCD_BASE                       0x10020000
-//TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption
-#define PL111_CLCD_VRAM_BASE                  0x78000000
-
-#define ARM_EB_SYS_OSCCLK4                    0x1000001C
-
-
-/*// System Configuration Controller register Base addresses
-//#define ARM_EB_SYS_CFG_CTRL_BASE                0x100E2000
-#define ARM_EB_SYS_CFGRW0_REG                   0x100E2000
-#define ARM_EB_SYS_CFGRW1_REG                   0x100E2004
-#define ARM_EB_SYS_CFGRW2_REG                   0x100E2008
-
-#define ARM_EB_CFGRW1_REMAP_NOR0                0
-#define ARM_EB_CFGRW1_REMAP_NOR1                (1 << 28)
-#define ARM_EB_CFGRW1_REMAP_EXT_AXI             (1 << 29)
-#define ARM_EB_CFGRW1_REMAP_DRAM                (1 << 30)
-
-// PL301 Fast AXI Base Address
-#define ARM_EB_FAXI_BASE                        0x100E9000
-
-// L2x0 Cache Controller Base Address
-//#define ARM_EB_L2x0_CTLR_BASE                   0x1E00A000*/
-
-
-// PL031 RTC - Other settings
-#define PL031_PPM_ACCURACY                      300000000
-
-/*******************************************
-// Interrupt Map
-*******************************************/
-
-// Timer Interrupts
-#define TIMER01_INTERRUPT_NUM                34
-#define TIMER23_INTERRUPT_NUM                35
-
-
-/*******************************************
-// EFI Memory Map in Permanent Memory (DRAM)
-*******************************************/
-
-// This region is allocated at the bottom of the DRAM. It will be used
-// for fixed address allocations such as Vector Table
-#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB
-
-// This region is the memory declared to PEI as permanent memory for PEI
-// and DXE. EFI stacks and heaps will be declared in this region.
-#define ARM_EB_EFI_MEMORY_REGION_SZ             0x1000000
-#endif
-
-typedef enum {
-  REVISION_XM,
-  REVISION_UNKNOWN0,
-  REVISION_UNKNOWN1,
-  REVISION_UNKNOWN2,
-  REVISION_UNKNOWN3,
-  REVISION_C4,
-  REVISION_C123,
-  REVISION_AB,
-} BEAGLEBOARD_REVISION;
-
-#endif
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoard.c b/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoard.c
deleted file mode 100755
index 3b02440..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoard.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/IoLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-
-#include <Omap3530/Omap3530.h>
-#include <BeagleBoard.h>
-
-VOID
-PadConfiguration (
-  BEAGLEBOARD_REVISION Revision
-  );
-
-VOID
-ClockInit (
-  VOID
-  );
-
-/**
-  Detect board revision
-
-  @return Board revision
-**/
-BEAGLEBOARD_REVISION
-BeagleBoardGetRevision (
-  VOID
-  )
-{
-  UINT32 OldPinDir;
-  UINT32 Revision;
-
-  // Read GPIO 171, 172, 173
-  OldPinDir = MmioRead32 (GPIO6_BASE + GPIO_OE);
-  MmioWrite32(GPIO6_BASE + GPIO_OE, (OldPinDir | BIT11 | BIT12 | BIT13));
-  Revision = MmioRead32 (GPIO6_BASE + GPIO_DATAIN);
-
-  // Restore I/O settings
-  MmioWrite32 (GPIO6_BASE + GPIO_OE, OldPinDir);
-
-  return (BEAGLEBOARD_REVISION)((Revision >> 11) & 0x7);
-}
-
-/**
-  Return the current Boot Mode
-
-  This function returns the boot reason on the platform
-
-**/
-EFI_BOOT_MODE
-ArmPlatformGetBootMode (
-  VOID
-  )
-{
-  return BOOT_WITH_FULL_CONFIGURATION;
-}
-
-/**
-  Initialize controllers that must setup at the early stage
-
-  Some peripherals must be initialized in Secure World.
-  For example, some L2x0 requires to be initialized in Secure World
-
-**/
-RETURN_STATUS
-ArmPlatformInitialize (
-  IN  UINTN                     MpId
-  )
-{
-  BEAGLEBOARD_REVISION Revision;
-
-  Revision = BeagleBoardGetRevision();
-
-  // Set up Pin muxing.
-  PadConfiguration (Revision);
-
-  // Set up system clocking
-  ClockInit ();
-
-  // Turn off the functional clock for Timer 3
-  MmioAnd32 (CM_FCLKEN_PER, 0xFFFFFFFF ^ CM_ICLKEN_PER_EN_GPT3_ENABLE );
-  ArmDataSynchronizationBarrier ();
-
-  // Clear IRQs
-  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
-  ArmDataSynchronizationBarrier ();
-
-  return RETURN_SUCCESS;
-}
-
-/**
-  Initialize the system (or sometimes called permanent) memory
-
-  This memory is generally represented by the DRAM.
-
-**/
-VOID
-ArmPlatformInitializeSystemMemory (
-  VOID
-  )
-{
-  // We do not need to initialize the System Memory on RTSM
-}
-
-VOID
-ArmPlatformGetPlatformPpiList (
-  OUT UINTN                   *PpiListSize,
-  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
-  )
-{
-  *PpiListSize = 0;
-  *PpiList = NULL;
-}
-
-UINTN
-ArmPlatformGetCorePosition (
-  IN UINTN MpId
-  )
-{
-  return 1;
-}
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardHelper.S b/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardHelper.S
deleted file mode 100644
index f157925..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardHelper.S
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-#  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-
-#include <AsmMacroIoLib.h>
-#include <AutoGen.h>
-
-.text
-.align 2
-
-GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
-GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
-GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
-
-GCC_ASM_IMPORT(ArmReadMpidr)
-
-//UINTN
-//ArmPlatformIsPrimaryCore (
-//  IN UINTN MpId
-//  );
-ASM_PFX(ArmPlatformIsPrimaryCore):
-  // BeagleBoard has a single core. We must always return 1.
-  mov   r0, #1
-  bx    lr
-
-ASM_PFX(ArmPlatformPeiBootAction):
-  bx    lr
-
-//UINTN
-//ArmPlatformGetPrimaryCoreMpId (
-//  VOID
-//  );
-ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
-  // The BeagleBoard is a uniprocessor platform. The MPIDR of primary core is
-  // always the MPIDR of the calling CPU.
-  b   ASM_PFX(ArmReadMpidr)
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardHelper.asm b/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardHelper.asm
deleted file mode 100644
index 86906c8..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardHelper.asm
+++ /dev/null
@@ -1,53 +0,0 @@
-//
-//  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AsmMacroIoLib.h>
-#include <Base.h>
-
-#include <AutoGen.h>
-
-  INCLUDE AsmMacroIoLib.inc
-
-  EXPORT    ArmPlatformPeiBootAction
-  EXPORT    ArmPlatformIsPrimaryCore
-  EXPORT    ArmPlatformGetPrimaryCoreMpId
-
-  IMPORT    ArmReadMpidr
-
-  AREA BeagleBoardHelper, CODE, READONLY
-
-//UINTN
-//ArmPlatformIsPrimaryCore (
-//  IN UINTN MpId
-//  );
-ArmPlatformIsPrimaryCore FUNCTION
-  // BeagleBoard has a single core. We must always return 1.
-  mov   r0, #1
-  bx    lr
-  ENDFUNC
-
-ArmPlatformPeiBootAction FUNCTION
-  bx    lr
-  ENDFUNC
-
-//UINTN
-//ArmPlatformGetPrimaryCoreMpId (
-//  VOID
-//  );
-ArmPlatformGetPrimaryCoreMpId FUNCTION
-  // The BeagleBoard is a uniprocessor platform. The MPIDR of primary core is
-  // always the MPIDR of the calling CPU.
-  b     ArmReadMpidr
-  ENDFUNC
-
-  END
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardMem.c b/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardMem.c
deleted file mode 100755
index b77b069..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardMem.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2011, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/ArmPlatformLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/IoLib.h>
-
-#include <BeagleBoard.h>
-
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          4
-
-/**
-  Return the Virtual Memory Map of your platform
-
-  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
-
-  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
-                                    Virtual Memory mapping. This array must be ended by a zero-filled
-                                    entry
-
-**/
-VOID
-ArmPlatformGetVirtualMemoryMap (
-  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
-  )
-{
-  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
-  UINTN                         Index = 0;
-  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
-
-  ASSERT(VirtualMemoryMap != NULL);
-
-  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
-  if (VirtualMemoryTable == NULL) {
-    return;
-  }
-
-  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
-    CacheAttributes = DDR_ATTRIBUTES_CACHED;
-  } else {
-    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
-  }
-
-  // ReMap (Either NOR Flash or DRAM)
-  VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
-  VirtualMemoryTable[Index].VirtualBase  = PcdGet64 (PcdSystemMemoryBase);
-  VirtualMemoryTable[Index].Length       = PcdGet64 (PcdSystemMemorySize);
-  VirtualMemoryTable[Index].Attributes   = CacheAttributes;
-
-  // SOC Registers. L3 interconnects
-  VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
-  VirtualMemoryTable[Index].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;
-  VirtualMemoryTable[Index].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
-  VirtualMemoryTable[Index].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;
-
-  // SOC Registers. L4 interconnects
-  VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
-  VirtualMemoryTable[Index].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;
-  VirtualMemoryTable[Index].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
-  VirtualMemoryTable[Index].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;
-
-  // End of Table
-  VirtualMemoryTable[++Index].PhysicalBase = 0;
-  VirtualMemoryTable[Index].VirtualBase  = 0;
-  VirtualMemoryTable[Index].Length       = 0;
-  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
-
-  ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
-
-  *VirtualMemoryMap = VirtualMemoryTable;
-}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/Clock.c b/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/Clock.c
deleted file mode 100755
index 6ca48e0..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/Clock.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-
-#include <Omap3530/Omap3530.h>
-
-VOID
-ClockInit (
-  VOID
-  )
-{
-  //DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.
-
-  // Enable PLL5 and set to 120 MHz as a reference clock.
-  MmioWrite32 (CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
-  MmioWrite32 (CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
-  MmioWrite32 (CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
-
-  // Turn on functional & interface clocks to the USBHOST power domain
-  MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
-                              | CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);
-  MmioOr32(CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);
-
-  // Turn on functional & interface clocks to the USBTLL block.
-  MmioOr32(CM_FCLKEN3_CORE, CM_FCLKEN3_CORE_EN_USBTLL_ENABLE);
-  MmioOr32(CM_ICLKEN3_CORE, CM_ICLKEN3_CORE_EN_USBTLL_ENABLE);
-
-  // Turn on functional & interface clocks to MMC1 and I2C1 modules.
-  MmioOr32(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_MMC1_ENABLE
-                            | CM_FCLKEN1_CORE_EN_I2C1_ENABLE);
-  MmioOr32(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_MMC1_ENABLE
-                            | CM_ICLKEN1_CORE_EN_I2C1_ENABLE);
-
-  // Turn on functional & interface clocks to various Peripherals.
-  MmioOr32(CM_FCLKEN_PER, CM_FCLKEN_PER_EN_UART3_ENABLE
-                          | CM_FCLKEN_PER_EN_GPT4_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO2_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO3_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO4_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO5_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO6_ENABLE);
-  MmioOr32(CM_ICLKEN_PER, CM_ICLKEN_PER_EN_UART3_ENABLE
-                          | CM_ICLKEN_PER_EN_GPT3_ENABLE
-                          | CM_ICLKEN_PER_EN_GPT4_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO2_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO3_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO4_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO5_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO6_ENABLE);
-
-  // Turn on functional & inteface clocks to various wakeup modules.
-  MmioOr32(CM_FCLKEN_WKUP, CM_FCLKEN_WKUP_EN_GPIO1_ENABLE
-                           | CM_FCLKEN_WKUP_EN_WDT2_ENABLE);
-  MmioOr32(CM_ICLKEN_WKUP, CM_ICLKEN_WKUP_EN_GPIO1_ENABLE
-                           | CM_ICLKEN_WKUP_EN_WDT2_ENABLE);
-}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/PadConfiguration.c b/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/PadConfiguration.c
deleted file mode 100755
index e6f7cc5..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/PadConfiguration.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiPei.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Omap3530/Omap3530.h>
-#include <BeagleBoard.h>
-
-#define NUM_PINS_SHARED 232
-#define NUM_PINS_ABC 6
-#define NUM_PINS_XM 12
-
-PAD_CONFIGURATION PadConfigurationTableShared[] = {
-  //Pin,           MuxMode,    PullConfig,                      InputEnable
-  { SDRC_D0,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D1,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D2,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D3,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D4,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D5,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D6,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D7,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D8,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D9,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D10,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D11,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D12,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D13,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D14,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D15,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D16,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D17,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D18,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D19,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D20,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D21,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D22,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D23,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D24,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D25,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D26,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D27,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D28,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D29,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D30,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D31,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_CLK,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_DQS0,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_CKE0,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { SDRC_CKE1,     MUXMODE7,   PULL_DISABLED,                INPUT  },
-  { SDRC_DQS1,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_DQS2,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_DQS3,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_A1,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A2,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A3,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A4,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A5,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A6,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A7,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A8,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A9,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A10,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_D0,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D1,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D2,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D3,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D4,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D5,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D6,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D7,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D8,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D9,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D10,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D11,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D12,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D13,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D14,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D15,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NCS0,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NCS1,     MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { GPMC_NCS2,     MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { GPMC_NCS3,     MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { GPMC_NCS4,     MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { GPMC_NCS5,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_NCS6,     MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { GPMC_NCS7,     MUXMODE1,   PULL_UP_SELECTED,             INPUT  },
-  { GPMC_CLK,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_NADV_ALE, MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NOE,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NWE,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NBE0_CLE, MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_NBE1,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NWP,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_WAIT0,    MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { GPMC_WAIT1,    MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { GPMC_WAIT2,    MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { GPMC_WAIT3,    MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { DSS_PCLK,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_HSYNC,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_PSYNC,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_ACBIAS,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA0,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA1,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA2,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA3,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA4,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA5,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA6,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA7,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA8,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA9,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA10,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA11,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA12,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA13,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA14,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA15,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA16,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA17,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { CAM_HS,        MUXMODE0,   PULL_UP_SELECTED,             INPUT },
-  { CAM_VS,        MUXMODE0,   PULL_UP_SELECTED,             INPUT },
-  { CAM_XCLKA,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { CAM_PCLK,      MUXMODE0,   PULL_UP_SELECTED,             INPUT },
-  { CAM_FLD,       MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { CAM_D0,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D1,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D2,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D3,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D4,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D5,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D6,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D7,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D8,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D9,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D10,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D11,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_XCLKB,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { CAM_WEN,       MUXMODE4,   PULL_DISABLED,                INPUT  },
-  { CAM_STROBE,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { CSI2_DX0,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CSI2_DY0,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CSI2_DX1,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CSI2_DY1,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP2_FSX,    MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP2_CLKX,   MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP2_DR,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP2_DX,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { MMC1_CLK,      MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { MMC1_CMD,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT0,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT1,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT2,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT3,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT4,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT5,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT6,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT7,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_CLK,      MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_CMD,      MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT0,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT1,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT2,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT3,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT4,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT5,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT6,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT7,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MCBSP3_DX,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP3_DR,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP3_CLKX,   MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP3_FSX,    MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART2_CTS,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { UART2_RTS,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { UART2_TX,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { UART2_RX,      MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART1_TX,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { UART1_RTS,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART1_CTS,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART1_RX,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP4_CLKX,   MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { MCBSP4_DR,     MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { MCBSP4_DX,     MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { MCBSP4_FSX,    MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { MCBSP1_CLKR,   MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP1_FSR,    MUXMODE4,   PULL_UP_SELECTED,             OUTPUT },
-  { MCBSP1_DX,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP1_DR,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP1_CLKS,   MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MCBSP1_FSX,    MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP1_CLKX,   MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART3_CTS_RCTX,MUXMODE0,   PULL_UP_SELECTED,                 INPUT  },
-  { UART3_RTS_SD,  MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { UART3_RX_IRRX, MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { UART3_TX_IRTX, MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { HSUSB0_CLK,    MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_STP,    MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { HSUSB0_DIR,    MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_NXT,    MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA0,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA1,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA2,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA3,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA4,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA5,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA6,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA7,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { I2C1_SCL,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { I2C1_SDA,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { I2C2_SCL,      MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { I2C2_SDA,      MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { I2C3_SCL,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { I2C3_SDA,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { HDQ_SIO,       MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCSPI1_CLK,    MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI1_SIMO,   MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI1_SOMI,   MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCSPI1_CS0,    MUXMODE0,   PULL_UP_SELECTED,                 INPUT  },
-  { MCSPI1_CS1,    MUXMODE0,   PULL_UP_SELECTED,                 OUTPUT },
-  { MCSPI1_CS2,    MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCSPI1_CS3,    MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_CLK,    MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_SIMO,   MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_SOMI,   MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_CS0,    MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_CS1,    MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { SYS_NIRQ,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { SYS_CLKOUT2,   MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_CLK,       MUXMODE3,   PULL_UP_SELECTED,             OUTPUT },
-  { ETK_CTL,       MUXMODE3,   PULL_UP_SELECTED,             OUTPUT },
-  { ETK_D0,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D1,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D2,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D3,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D4,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D5,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D6,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D7,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D8,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D9,        MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D10,       MUXMODE3,   PULL_UP_SELECTED,             OUTPUT },
-  { ETK_D11,       MUXMODE3,   PULL_UP_SELECTED,             OUTPUT },
-  { ETK_D12,       MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D13,       MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D14,       MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D15,       MUXMODE3,   PULL_UP_SELECTED,             INPUT  }
-};
-
-PAD_CONFIGURATION PadConfigurationTableAbc[] = {
-  { DSS_DATA18,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA19,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA20,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA21,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA22,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA23,    MUXMODE0,   PULL_DISABLED,                OUTPUT }
-};
-
-PAD_CONFIGURATION PadConfigurationTableXm[] = {
-  { DSS_DATA18,    MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA19,    MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA20,    MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA21,    MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA22,    MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA23,    MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { SYS_BOOT0,     MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { SYS_BOOT1,     MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { SYS_BOOT3,     MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { SYS_BOOT4,     MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { SYS_BOOT5,     MUXMODE3,   PULL_DISABLED,                OUTPUT },
-  { SYS_BOOT6,     MUXMODE3,   PULL_DISABLED,                OUTPUT }
-};
-
-VOID
-PadConfiguration (
-  BEAGLEBOARD_REVISION Revision
-  )
-{
-  UINTN             Index;
-  UINT16            PadConfiguration;
-  PAD_CONFIGURATION *BoardConfiguration;
-  UINTN             NumPinsToConfigure;
-
-  for (Index = 0; Index < NUM_PINS_SHARED; Index++) {
-    // Set up Pad configuration for particular pin.
-    PadConfiguration =  (PadConfigurationTableShared[Index].MuxMode << MUXMODE_OFFSET);
-    PadConfiguration |= (PadConfigurationTableShared[Index].PullConfig << PULL_CONFIG_OFFSET);
-    PadConfiguration |= (PadConfigurationTableShared[Index].InputEnable << INPUTENABLE_OFFSET);
-
-    // Configure the pin with specific Pad configuration.
-    MmioWrite16(PadConfigurationTableShared[Index].Pin, PadConfiguration);
-  }
-
-  if (Revision == REVISION_XM) {
-    BoardConfiguration = PadConfigurationTableXm;
-    NumPinsToConfigure = NUM_PINS_XM;
-  } else {
-    BoardConfiguration = PadConfigurationTableAbc;
-    NumPinsToConfigure = NUM_PINS_ABC;
-  }
-
-  for (Index = 0; Index < NumPinsToConfigure; Index++) {
-    //Set up Pad configuration for particular pin.
-    PadConfiguration =  (BoardConfiguration[Index].MuxMode << MUXMODE_OFFSET);
-    PadConfiguration |= (BoardConfiguration[Index].PullConfig << PULL_CONFIG_OFFSET);
-    PadConfiguration |= (BoardConfiguration[Index].InputEnable << INPUTENABLE_OFFSET);
-
-    //Configure the pin with specific Pad configuration.
-    MmioWrite16(BoardConfiguration[Index].Pin, PadConfiguration);
-  }
-}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/EblCmdLib/EblCmdLib.c b/Platforms/TexasInstruments/BeagleBoard/Library/EblCmdLib/EblCmdLib.c
deleted file mode 100644
index 46204a4..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/EblCmdLib/EblCmdLib.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/** @file
-  Add custom commands for BeagleBoard development.
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-#include <Library/ArmLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/EblCmdLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiLib.h>
-#include <Library/PcdLib.h>
-#include <Library/EfiFileLib.h>
-#include <Library/ArmDisassemblerLib.h>
-#include <Library/PeCoffGetEntryPointLib.h>
-#include <Library/PerformanceLib.h>
-#include <Library/TimerLib.h>
-
-#include <Guid/DebugImageInfoTable.h>
-
-#include <Protocol/DebugSupport.h>
-#include <Protocol/LoadedImage.h>
-
-/**
-  Simple arm disassembler via a library
-
-  Argv[0] - symboltable
-  Argv[1] - Optional quoted format string
-  Argv[2] - Optional flag
-
-  @param  Argc   Number of command arguments in Argv
-  @param  Argv   Array of strings that represent the parsed command line.
-                 Argv[0] is the command name
-
-  @return EFI_SUCCESS
-
-**/
-EFI_STATUS
-EblSymbolTable (
-  IN UINTN  Argc,
-  IN CHAR8  **Argv
-  )
-{
-  EFI_STATUS                        Status;
-  EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugImageTableHeader = NULL;
-  EFI_DEBUG_IMAGE_INFO              *DebugTable;
-  UINTN                             Entry;
-  CHAR8                             *Format;
-  CHAR8                             *Pdb;
-  UINT32                            PeCoffSizeOfHeaders;
-  UINT32                            ImageBase;
-  BOOLEAN                           Elf;
-
-  // Need to add lots of error checking on the passed in string
-  // Default string is for RealView debugger or gdb depending on toolchain used.
-  if (Argc > 1) {
-    Format = Argv[1];
-  } else {
-#if __GNUC__
-    // Assume gdb
-    Format = "add-symbol-file %a 0x%x";
-#else
-    // Default to RVCT
-    Format = "load /a /ni /np %a &0x%x";
-#endif
-  }
-  Elf = (Argc > 2) ? FALSE : TRUE;
-
-  Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&DebugImageTableHeader);
-  if (EFI_ERROR (Status)) {
-    return Status;
-  }
-
-  DebugTable = DebugImageTableHeader->EfiDebugImageInfoTable;
-  if (DebugTable == NULL) {
-    return EFI_SUCCESS;
-  }
-
-  for (Entry = 0; Entry < DebugImageTableHeader->TableSize; Entry++, DebugTable++) {
-    if (DebugTable->NormalImage != NULL) {
-      if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) && (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {
-        ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
-        PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)ImageBase);
-        Pdb = PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
-        if (Pdb != NULL) {
-          if (Elf) {
-            // ELF and Mach-O images don't include the header so the linked address does not include header
-            ImageBase += PeCoffSizeOfHeaders;
-          }
-          AsciiPrint (Format, Pdb, ImageBase);
-          AsciiPrint ("\n");
-        } else {
-        }
-      }
-    }
-  }
-
-  return EFI_SUCCESS;
-}
-
-
-/**
-  Simple arm disassembler via a library
-
-  Argv[0] - disasm
-  Argv[1] - Address to start disassembling from
-  ARgv[2] - Number of instructions to disassembly (optional)
-
-  @param  Argc   Number of command arguments in Argv
-  @param  Argv   Array of strings that represent the parsed command line.
-                 Argv[0] is the command name
-
-  @return EFI_SUCCESS
-
-**/
-EFI_STATUS
-EblDisassembler (
-  IN UINTN  Argc,
-  IN CHAR8  **Argv
-  )
-{
-  UINT8   *Ptr, *CurrentAddress;
-  UINT32  Address;
-  UINT32  Count;
-  CHAR8   Buffer[80];
-  UINT32  ItBlock;
-
-  if (Argc < 2) {
-    return EFI_INVALID_PARAMETER;
-  }
-
-  Address = AsciiStrHexToUintn (Argv[1]);
-  Count   = (Argc > 2) ? (UINT32)AsciiStrHexToUintn (Argv[2]) : 20;
-
-  Ptr = (UINT8 *)(UINTN)Address;
-  ItBlock = 0;
-  do {
-    CurrentAddress = Ptr;
-    DisassembleInstruction (&Ptr, TRUE, TRUE, &ItBlock, Buffer, sizeof (Buffer));
-    AsciiPrint ("0x%08x: %a\n", CurrentAddress, Buffer);
-  } while (Count-- > 0);
-
-
-  return EFI_SUCCESS;
-}
-
-
-CHAR8 *
-ImageHandleToPdbFileName (
-  IN  EFI_HANDLE    Handle
-  )
-{
-  EFI_STATUS                  Status;
-  EFI_LOADED_IMAGE_PROTOCOL   *LoadedImage;
-  CHAR8                       *Pdb;
-  CHAR8                       *StripLeading;
-
-  Status = gBS->HandleProtocol (Handle, &gEfiLoadedImageProtocolGuid, (VOID **)&LoadedImage);
-  if (EFI_ERROR (Status)) {
-    return "";
-  }
-
-  Pdb = PeCoffLoaderGetPdbPointer (LoadedImage->ImageBase);
-  StripLeading = AsciiStrStr (Pdb, "\\ARM\\");
-  if (StripLeading == NULL) {
-    StripLeading = AsciiStrStr (Pdb, "/ARM/");
-    if (StripLeading == NULL) {
-      return Pdb;
-    }
-  }
-  // Hopefully we hacked off the unneeded part
-  return (StripLeading + 5);
-}
-
-
-CHAR8 *mTokenList[] = {
-  "SEC",
-  "PEI",
-  "DXE",
-  "BDS",
-  NULL
-};
-
-/**
-  Simple arm disassembler via a library
-
-  Argv[0] - disasm
-  Argv[1] - Address to start disassembling from
-  ARgv[2] - Number of instructions to disassembly (optional)
-
-  @param  Argc   Number of command arguments in Argv
-  @param  Argv   Array of strings that represent the parsed command line.
-                 Argv[0] is the command name
-
-  @return EFI_SUCCESS
-
-**/
-EFI_STATUS
-EblPerformance (
-  IN UINTN  Argc,
-  IN CHAR8  **Argv
-  )
-{
-  UINTN       Key;
-  CONST VOID  *Handle;
-  CONST CHAR8 *Token, *Module;
-  UINT64      Start, Stop, TimeStamp;
-  UINT64      Delta, TicksPerSecond, Milliseconds, Microseconds;
-  UINTN       Index;
-
-  TicksPerSecond = GetPerformanceCounterProperties (NULL, NULL);
-
-  Key       = 0;
-  do {
-    Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop);
-    if (Key != 0) {
-      if (AsciiStriCmp ("StartImage:", Token) == 0) {
-        if (Stop == 0) {
-          // The entry for EBL is still running so the stop time will be zero. Skip it
-          AsciiPrint ("   running     %a\n", ImageHandleToPdbFileName ((EFI_HANDLE)Handle));
-        } else {
-          Delta = Stop - Start;
-          Microseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000000), TicksPerSecond, NULL);
-          AsciiPrint ("%10ld us  %a\n", Microseconds, ImageHandleToPdbFileName ((EFI_HANDLE)Handle));
-        }
-      }
-    }
-  } while (Key != 0);
-
-  AsciiPrint ("\n");
-
-  TimeStamp = 0;
-  Key       = 0;
-  do {
-    Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop);
-    if (Key != 0) {
-      for (Index = 0; mTokenList[Index] != NULL; Index++) {
-        if (AsciiStriCmp (mTokenList[Index], Token) == 0) {
-          Delta = Stop - Start;
-          TimeStamp += Delta;
-          Milliseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000), TicksPerSecond, NULL);
-          AsciiPrint ("%6a %6ld ms\n", Token, Milliseconds);
-          break;
-        }
-      }
-    }
-  } while (Key != 0);
-
-  AsciiPrint ("Total Time = %ld ms\n\n", DivU64x64Remainder (MultU64x32 (TimeStamp, 1000), TicksPerSecond, NULL));
-
-  return EFI_SUCCESS;
-}
-
-
-GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] =
-{
-  {
-    "disasm address [count]",
-    " disassemble count instructions",
-    NULL,
-    EblDisassembler
-  },
-  {
-    "performance",
-    " Display boot performance info",
-    NULL,
-    EblPerformance
-  },
-  {
-    "symboltable [\"format string\"] [PECOFF]",
-    " show symbol table commands for debugger",
-    NULL,
-    EblSymbolTable
-  }
-};
-
-
-VOID
-EblInitializeExternalCmd (
-  VOID
-  )
-{
-  EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE));
-  return;
-}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/EblCmdLib/EblCmdLib.inf b/Platforms/TexasInstruments/BeagleBoard/Library/EblCmdLib/EblCmdLib.inf
deleted file mode 100644
index a79448c..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/EblCmdLib/EblCmdLib.inf
+++ /dev/null
@@ -1,53 +0,0 @@
-#/** @file
-# Component description file for the entry point to a EFIDXE Drivers
-#
-# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification
-# Copyright (c) 2007 - 2007, Intel Corporation. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardEblCmdLib
-  FILE_GUID                      = ea62bdc3-1063-425f-8851-98cb47f213a8
-  MODULE_TYPE                    = UEFI_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER
-
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC
-#
-
-[Sources.common]
-  EblCmdLib.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  ArmPkg/ArmPkg.dec
-
-[LibraryClasses]
-  BaseLib
-  DebugLib
-  ArmDisassemblerLib
-  PerformanceLib
-  TimerLib
-
-[Protocols]
- gEfiDebugSupportProtocolGuid
- gEfiLoadedImageProtocolGuid
-
-[Guids]
- gEfiDebugImageInfoTableGuid
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/GdbSerialLib/GdbSerialLib.c b/Platforms/TexasInstruments/BeagleBoard/Library/GdbSerialLib/GdbSerialLib.c
deleted file mode 100644
index 82a2957..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/GdbSerialLib/GdbSerialLib.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/** @file
-  Basic serial IO abstaction for GDB
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Uefi.h>
-#include <Library/GdbSerialLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Library/OmapLib.h>
-#include <Omap3530/Omap3530.h>
-
-RETURN_STATUS
-EFIAPI
-GdbSerialLibConstructor (
-  IN EFI_HANDLE        ImageHandle,
-  IN EFI_SYSTEM_TABLE  *SystemTable
-  )
-{
-  return RETURN_SUCCESS;
-}
-
-RETURN_STATUS
-EFIAPI
-GdbSerialInit (
-  IN UINT64     BaudRate,
-  IN UINT8      Parity,
-  IN UINT8      DataBits,
-  IN UINT8      StopBits
-  )
-{
-  return RETURN_SUCCESS;
-}
-
-BOOLEAN
-EFIAPI
-GdbIsCharAvailable (
-  VOID
-  )
-{
-  UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-
-  if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
-    return TRUE;
-  } else {
-    return FALSE;
-  }
-}
-
-CHAR8
-EFIAPI
-GdbGetChar (
-  VOID
-  )
-{
-  UINT32  LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-  UINT32  RBR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_RBR_REG;
-  CHAR8   Char;
-
-  while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
-  Char = MmioRead8(RBR);
-
-  return Char;
-}
-
-VOID
-EFIAPI
-GdbPutChar (
-  IN  CHAR8   Char
-  )
-{
-  UINT32  LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
-  UINT32  THR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_THR_REG;
-
-  while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
-  MmioWrite8(THR, Char);
-}
-
-VOID
-GdbPutString (
-  IN CHAR8  *String
-  )
-{
-  while (*String != '\0') {
-    GdbPutChar (*String);
-    String++;
-  }
-}
-
-
-
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/GdbSerialLib/GdbSerialLib.inf b/Platforms/TexasInstruments/BeagleBoard/Library/GdbSerialLib/GdbSerialLib.inf
deleted file mode 100644
index e219ea2..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/GdbSerialLib/GdbSerialLib.inf
+++ /dev/null
@@ -1,41 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = GdbSerialLib
-  FILE_GUID                      = E2423349-EF5D-439B-95F5-8B8D8E3B443F
-  MODULE_TYPE                    = UEFI_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = GdbSerialLib
-
-  CONSTRUCTOR                    = GdbSerialLibConstructor
-
-
-[Sources.common]
-  GdbSerialLib.c
-
-
-[Packages]
-  MdePkg/MdePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-
-[LibraryClasses]
-  DebugLib
-  IoLib
-  OmapLib
-
-[FixedPcd]
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Library/ResetSystemLib/ResetSystemLib.c b/Platforms/TexasInstruments/BeagleBoard/Library/ResetSystemLib/ResetSystemLib.c
deleted file mode 100644
index 6b7879b..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Library/ResetSystemLib/ResetSystemLib.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/** @file
-  Do a generic Cold Reset for OMAP3550 and BeagleBoard specific Warm reset
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include <Uefi.h>
-
-#include <Library/ArmLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#include <Omap3530/Omap3530.h>
-
-
-VOID
-ShutdownEfi (
-  VOID
-  )
-{
-  EFI_STATUS              Status;
-  UINTN                   MemoryMapSize;
-  EFI_MEMORY_DESCRIPTOR   *MemoryMap;
-  UINTN                   MapKey;
-  UINTN                   DescriptorSize;
-  UINTN                   DescriptorVersion;
-  UINTN                   Pages;
-
-  MemoryMap = NULL;
-  MemoryMapSize = 0;
-  do {
-    Status = gBS->GetMemoryMap (
-                    &MemoryMapSize,
-                    MemoryMap,
-                    &MapKey,
-                    &DescriptorSize,
-                    &DescriptorVersion
-                    );
-    if (Status == EFI_BUFFER_TOO_SMALL) {
-
-      Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
-      MemoryMap = AllocatePages (Pages);
-
-      //
-      // Get System MemoryMap
-      //
-      Status = gBS->GetMemoryMap (
-                      &MemoryMapSize,
-                      MemoryMap,
-                      &MapKey,
-                      &DescriptorSize,
-                      &DescriptorVersion
-                      );
-      // Don't do anything between the GetMemoryMap() and ExitBootServices()
-      if (!EFI_ERROR (Status)) {
-        Status = gBS->ExitBootServices (gImageHandle, MapKey);
-        if (EFI_ERROR (Status)) {
-          FreePages (MemoryMap, Pages);
-          MemoryMap = NULL;
-          MemoryMapSize = 0;
-        }
-      }
-    }
-  } while (EFI_ERROR (Status));
-
-  //Clean and invalidate caches.
-  WriteBackInvalidateDataCache();
-  InvalidateInstructionCache();
-
-  //Turning off Caches and MMU
-  ArmDisableDataCache ();
-  ArmDisableInstructionCache ();
-  ArmDisableMmu ();
-}
-
-typedef
-VOID
-(EFIAPI *CALL_STUB)(
-  VOID
-);
-
-
-/**
-  Resets the entire platform.
-
-  @param  ResetType             The type of reset to perform.
-  @param  ResetStatus           The status code for the reset.
-  @param  DataSize              The size, in bytes, of WatchdogData.
-  @param  ResetData             For a ResetType of EfiResetCold, EfiResetWarm, or
-                                EfiResetShutdown the data buffer starts with a Null-terminated
-                                Unicode string, optionally followed by additional binary data.
-
-**/
-EFI_STATUS
-EFIAPI
-LibResetSystem (
-  IN EFI_RESET_TYPE   ResetType,
-  IN EFI_STATUS       ResetStatus,
-  IN UINTN            DataSize,
-  IN CHAR16           *ResetData OPTIONAL
-  )
-{
-  CALL_STUB   StartOfFv;
-
-  if (ResetData != NULL) {
-    DEBUG((EFI_D_ERROR, "%s", ResetData));
-  }
-
-  ShutdownEfi ();
-
-  switch (ResetType) {
-  case EfiResetWarm:
-    //Perform warm reset of the system by jumping to the begining of the FV
-    StartOfFv = (CALL_STUB)(UINTN)PcdGet64 (PcdFvBaseAddress);
-    StartOfFv ();
-    break;
-  case EfiResetCold:
-  case EfiResetShutdown:
-  default:
-    //Perform cold reset of the system.
-    MmioOr32 (PRM_RSTCTRL, RST_DPLL3);
-    while ((MmioRead32(PRM_RSTST) & GLOBAL_COLD_RST) != 0x1);
-    break;
-  }
-
-  // If the reset didn't work, return an error.
-  ASSERT (FALSE);
-  return EFI_DEVICE_ERROR;
-}
-
-
-
-/**
-  Initialize any infrastructure required for LibResetSystem () to function.
-
-  @param  ImageHandle   The firmware allocated handle for the EFI image.
-  @param  SystemTable   A pointer to the EFI System Table.
-
-  @retval EFI_SUCCESS   The constructor always returns EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-LibInitializeResetSystem (
-  IN EFI_HANDLE        ImageHandle,
-  IN EFI_SYSTEM_TABLE  *SystemTable
-  )
-{
-  return EFI_SUCCESS;
-}
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ModuleEntryPoint.S b/Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ModuleEntryPoint.S
deleted file mode 100644
index b656c1e..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ModuleEntryPoint.S
+++ /dev/null
@@ -1,85 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-#include <Library/PcdLib.h>
-
-.text
-.align 3
-
-.globl ASM_PFX(CEntryPoint)
-GCC_ASM_EXPORT(_ModuleEntryPoint)
-
-ASM_PFX(_ModuleEntryPoint):
-
-  //Disable L2 cache
-  mrc     p15, 0, r0, c1, c0, 1   // read Auxiliary Control Register
-  bic     r0, r0, #0x00000002     // disable L2 cache
-  mcr     p15, 0, r0, c1, c0, 1   // store Auxiliary Control Register
-
-  //Enable Strict alignment checking & Instruction cache
-  mrc     p15, 0, r0, c1, c0, 0
-  bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
-  bic     r0, r0, #0x00000005     /* clear bits 0, 2 (---- -C-M) */
-  orr     r0, r0, #0x00000002     /* set bit 1 (A) Align */
-  orr     r0, r0, #0x00001000     /* set bit 12 (I) enable I-Cache */
-  mcr     p15, 0, r0, c1, c0, 0
-
-  // Enable NEON register in case folks want to use them for optimizations (CopyMem)
-  mrc     p15, 0, r0, c1, c0, 2
-  orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)
-  mcr     p15, 0, r0, c1, c0, 2
-  mov     r0, #0x40000000       // Set EN bit in FPEXC
-  mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly
-
-
-  // Set CPU vectors to start of DRAM
-  LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
-  mcr     p15, 0, r0, c12, c0, 0
-  isb                               // Sync changes to control registers
-
-  // Fill vector table with branchs to current pc (jmp $)
-  ldr     r1, ShouldNeverGetHere
-  movs    r2, #0
-FillVectors:
-  str     r1, [r0, r2]
-  adds    r2, r2, #4
-  cmp     r2, #32
-  bne     FillVectors
-
-  /* before we call C code, lets setup the stack pointer in internal RAM */
-stack_pointer_setup:
-
-  //
-  // Set stack based on PCD values. Need to do it this way to make C code work
-  // when it runs from FLASH.
-  //
-  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    /* stack base arg2  */
-  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    /* stack size arg3  */
-  add     r4, r2, r3
-
-  //Enter SVC mode and set up SVC stack pointer
-  mov     r0,#0x13|0x80|0x40
-  msr     CPSR_c,r0
-  mov     r13,r4
-
-  // Call C entry point
-  LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1)    /* memory size arg1          */
-  LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0)    /* memory size arg0         */
-  blx      ASM_PFX(CEntryPoint) /* Assume C code is thumb    */
-
-ShouldNeverGetHere:
-  /* _CEntryPoint should never return */
-  b       ShouldNeverGetHere
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ModuleEntryPoint.asm b/Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ModuleEntryPoint.asm
deleted file mode 100644
index 63174d4..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ModuleEntryPoint.asm
+++ /dev/null
@@ -1,89 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution.  The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-#include <Library/PcdLib.h>
-#include <AutoGen.h>
-  INCLUDE AsmMacroIoLib.inc
-
-  IMPORT  CEntryPoint
-  EXPORT  _ModuleEntryPoint
-
-  PRESERVE8
-  AREA    ModuleEntryPoint, CODE, READONLY
-
-
-_ModuleEntryPoint
-
-  //Disable L2 cache
-  mrc     p15, 0, r0, c1, c0, 1   // read Auxiliary Control Register
-  bic     r0, r0, #0x00000002     // disable L2 cache
-  mcr     p15, 0, r0, c1, c0, 1   // store Auxiliary Control Register
-
-  //Enable Strict alignment checking & Instruction cache
-  mrc     p15, 0, r0, c1, c0, 0
-  bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
-  bic     r0, r0, #0x00000005     /* clear bits 0, 2 (---- -C-M) */
-  orr     r0, r0, #0x00000002     /* set bit 1 (A) Align */
-  orr     r0, r0, #0x00001000     /* set bit 12 (I) enable I-Cache */
-  mcr     p15, 0, r0, c1, c0, 0
-
-  // Enable NEON register in case folks want to use them for optimizations (CopyMem)
-  mrc     p15, 0, r0, c1, c0, 2
-  orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)
-  mcr     p15, 0, r0, c1, c0, 2
-  mov     r0, #0x40000000       // Set EN bit in FPEXC
-  msr     FPEXC,r0
-
-  // Set CPU vectors to start of DRAM
-  LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
-  mcr     p15, 0, r0, c12, c0, 0
-  isb                               // Sync changes to control registers
-
-  // Fill vector table with branchs to current pc (jmp $)
-  ldr     r1, ShouldNeverGetHere
-  movs    r2, #0
-FillVectors
-  str     r1, [r0, r2]
-  adds    r2, r2, #4
-  cmp     r2, #32
-  bne     FillVectors
-
-  /* before we call C code, lets setup the stack pointer in internal RAM */
-stack_pointer_setup
-
-  //
-  // Set stack based on PCD values. Need to do it this way to make C code work
-  // when it runs from FLASH.
-  //
-  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2)    // stack base arg2
-  LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3)    // stack size arg3
-  add     r4, r2, r3
-
-  //Enter SVC mode and set up SVC stack pointer
-  mov     r5,#0x13|0x80|0x40
-  msr     CPSR_c,r5
-  mov     r13,r4
-
-  // Call C entry point
-  LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1)    // memory size arg1
-  LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0)    // memory start arg0
-  blx     CEntryPoint                                     // Assume C code is thumb
-
-ShouldNeverGetHere
-  /* _CEntryPoint should never return */
-  b       ShouldNeverGetHere
-
-  END
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Sec/Cache.c b/Platforms/TexasInstruments/BeagleBoard/Sec/Cache.c
deleted file mode 100644
index 7399eef..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Sec/Cache.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiPei.h>
-
-#include <Library/ArmLib.h>
-#include <Library/PrePiLib.h>
-#include <Library/PcdLib.h>
-
-// DDR attributes
-#define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
-#define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
-
-// SoC registers. L3 interconnects
-#define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000
-#define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000
-#define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
-
-// SoC registers. L4 interconnects
-#define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000
-#define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000
-#define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
-
-VOID
-InitCache (
-  IN  UINT32  MemoryBase,
-  IN  UINT32  MemoryLength
-  )
-{
-  UINT32                        CacheAttributes;
-  ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[5];
-  VOID                          *TranslationTableBase;
-  UINTN                         TranslationTableSize;
-
-  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
-    CacheAttributes = DDR_ATTRIBUTES_CACHED;
-  } else {
-    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
-  }
-
-  // DDR
-  MemoryTable[0].PhysicalBase = MemoryBase;
-  MemoryTable[0].VirtualBase  = MemoryBase;
-  MemoryTable[0].Length       = MemoryLength;
-  MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
-
-  // SOC Registers. L3 interconnects
-  MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
-  MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;
-  MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
-  MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;
-
-  // SOC Registers. L4 interconnects
-  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
-  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;
-  MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
-  MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;
-
-  // End of Table
-  MemoryTable[3].PhysicalBase = 0;
-  MemoryTable[3].VirtualBase  = 0;
-  MemoryTable[3].Length       = 0;
-  MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
-
-  ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
-
-  BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
-}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Sec/Clock.c b/Platforms/TexasInstruments/BeagleBoard/Sec/Clock.c
deleted file mode 100644
index 24fdc71..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Sec/Clock.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-
-#include <Omap3530/Omap3530.h>
-
-VOID
-ClockInit (
-  VOID
-  )
-{
-  //DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.
-
-  // Enable PLL5 and set to 120 MHz as a reference clock.
-  MmioWrite32 (CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
-  MmioWrite32 (CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
-  MmioWrite32 (CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
-
-  // Turn on functional & interface clocks to the USBHOST power domain
-  MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
-                              | CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);
-  MmioOr32(CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);
-
-  // Turn on functional & interface clocks to the USBTLL block.
-  MmioOr32(CM_FCLKEN3_CORE, CM_FCLKEN3_CORE_EN_USBTLL_ENABLE);
-  MmioOr32(CM_ICLKEN3_CORE, CM_ICLKEN3_CORE_EN_USBTLL_ENABLE);
-
-  // Turn on functional & interface clocks to MMC1 and I2C1 modules.
-  MmioOr32(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_MMC1_ENABLE
-                            | CM_FCLKEN1_CORE_EN_I2C1_ENABLE);
-  MmioOr32(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_MMC1_ENABLE
-                            | CM_ICLKEN1_CORE_EN_I2C1_ENABLE);
-
-  // Turn on functional & interface clocks to various Peripherals.
-  MmioOr32(CM_FCLKEN_PER, CM_FCLKEN_PER_EN_UART3_ENABLE
-                          | CM_FCLKEN_PER_EN_GPT3_ENABLE
-                          | CM_FCLKEN_PER_EN_GPT4_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO2_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO3_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO4_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO5_ENABLE
-                          | CM_FCLKEN_PER_EN_GPIO6_ENABLE);
-  MmioOr32(CM_ICLKEN_PER, CM_ICLKEN_PER_EN_UART3_ENABLE
-                          | CM_ICLKEN_PER_EN_GPT3_ENABLE
-                          | CM_ICLKEN_PER_EN_GPT4_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO2_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO3_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO4_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO5_ENABLE
-                          | CM_ICLKEN_PER_EN_GPIO6_ENABLE);
-
-  // Turn on functional & inteface clocks to various wakeup modules.
-  MmioOr32(CM_FCLKEN_WKUP, CM_FCLKEN_WKUP_EN_GPIO1_ENABLE
-                           | CM_FCLKEN_WKUP_EN_WDT2_ENABLE);
-  MmioOr32(CM_ICLKEN_WKUP, CM_ICLKEN_WKUP_EN_GPIO1_ENABLE
-                           | CM_ICLKEN_WKUP_EN_WDT2_ENABLE);
-}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Sec/LzmaDecompress.h b/Platforms/TexasInstruments/BeagleBoard/Sec/LzmaDecompress.h
deleted file mode 100644
index a79ff34..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Sec/LzmaDecompress.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/** @file
-  LZMA Decompress Library header file
-
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __LZMA_DECOMPRESS_H___
-#define __LZMA_DECOMPRESS_H___
-
-/**
-  Examines a GUIDed section and returns the size of the decoded buffer and the
-  size of an scratch buffer required to actually decode the data in a GUIDed section.
-
-  Examines a GUIDed section specified by InputSection.
-  If GUID for InputSection does not match the GUID that this handler supports,
-  then RETURN_UNSUPPORTED is returned.
-  If the required information can not be retrieved from InputSection,
-  then RETURN_INVALID_PARAMETER is returned.
-  If the GUID of InputSection does match the GUID that this handler supports,
-  then the size required to hold the decoded buffer is returned in OututBufferSize,
-  the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field
-  from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute.
-
-  If InputSection is NULL, then ASSERT().
-  If OutputBufferSize is NULL, then ASSERT().
-  If ScratchBufferSize is NULL, then ASSERT().
-  If SectionAttribute is NULL, then ASSERT().
-
-
-  @param[in]  InputSection       A pointer to a GUIDed section of an FFS formatted file.
-  @param[out] OutputBufferSize   A pointer to the size, in bytes, of an output buffer required
-                                 if the buffer specified by InputSection were decoded.
-  @param[out] ScratchBufferSize  A pointer to the size, in bytes, required as scratch space
-                                 if the buffer specified by InputSection were decoded.
-  @param[out] SectionAttribute   A pointer to the attributes of the GUIDed section. See the Attributes
-                                 field of EFI_GUID_DEFINED_SECTION in the PI Specification.
-
-  @retval  RETURN_SUCCESS            The information about InputSection was returned.
-  @retval  RETURN_UNSUPPORTED        The section specified by InputSection does not match the GUID this handler supports.
-  @retval  RETURN_INVALID_PARAMETER  The information can not be retrieved from the section specified by InputSection.
-
-**/
-RETURN_STATUS
-EFIAPI
-LzmaGuidedSectionGetInfo (
-  IN  CONST VOID  *InputSection,
-  OUT UINT32      *OutputBufferSize,
-  OUT UINT32      *ScratchBufferSize,
-  OUT UINT16      *SectionAttribute
-  );
-
-/**
-  Decompress a LZAM compressed GUIDed section into a caller allocated output buffer.
-
-  Decodes the GUIDed section specified by InputSection.
-  If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned.
-  If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned.
-  If the GUID of InputSection does match the GUID that this handler supports, then InputSection
-  is decoded into the buffer specified by OutputBuffer and the authentication status of this
-  decode operation is returned in AuthenticationStatus.  If the decoded buffer is identical to the
-  data in InputSection, then OutputBuffer is set to point at the data in InputSection.  Otherwise,
-  the decoded data will be placed in caller allocated buffer specified by OutputBuffer.
-
-  If InputSection is NULL, then ASSERT().
-  If OutputBuffer is NULL, then ASSERT().
-  If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().
-  If AuthenticationStatus is NULL, then ASSERT().
-
-
-  @param[in]  InputSection  A pointer to a GUIDed section of an FFS formatted file.
-  @param[out] OutputBuffer  A pointer to a buffer that contains the result of a decode operation.
-  @param[out] ScratchBuffer A caller allocated buffer that may be required by this function
-                            as a scratch buffer to perform the decode operation.
-  @param[out] AuthenticationStatus
-                            A pointer to the authentication status of the decoded output buffer.
-                            See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
-                            section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must
-                            never be set by this handler.
-
-  @retval  RETURN_SUCCESS            The buffer specified by InputSection was decoded.
-  @retval  RETURN_UNSUPPORTED        The section specified by InputSection does not match the GUID this handler supports.
-  @retval  RETURN_INVALID_PARAMETER  The section specified by InputSection can not be decoded.
-
-**/
-RETURN_STATUS
-EFIAPI
-LzmaGuidedSectionExtraction (
-  IN CONST  VOID    *InputSection,
-  OUT       VOID    **OutputBuffer,
-  OUT       VOID    *ScratchBuffer,        OPTIONAL
-  OUT       UINT32  *AuthenticationStatus
-  );
-
-#endif // __LZMADECOMPRESS_H__
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Sec/PadConfiguration.c b/Platforms/TexasInstruments/BeagleBoard/Sec/PadConfiguration.c
deleted file mode 100644
index 2dace3b..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Sec/PadConfiguration.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiPei.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Omap3530/Omap3530.h>
-
-#define NUM_PINS 238
-
-PAD_CONFIGURATION PadConfigurationTable[NUM_PINS] = {
-  //Pin,           MuxMode,    PullConfig,                      InputEnable
-  { SDRC_D0,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D1,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D2,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D3,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D4,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D5,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D6,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D7,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D8,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D9,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D10,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D11,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D12,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D13,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D14,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D15,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D16,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D17,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D18,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D19,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D20,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D21,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D22,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D23,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D24,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D25,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D26,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D27,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D28,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D29,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D30,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_D31,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_CLK,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_DQS0,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_CKE0,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { SDRC_CKE1,     MUXMODE7,   PULL_DISABLED,                INPUT  },
-  { SDRC_DQS1,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_DQS2,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { SDRC_DQS3,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_A1,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A2,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A3,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A4,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A5,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A6,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A7,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A8,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A9,       MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_A10,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_D0,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D1,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D2,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D3,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D4,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D5,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D6,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D7,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D8,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D9,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D10,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D11,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D12,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D13,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D14,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_D15,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NCS0,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NCS1,     MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { GPMC_NCS2,     MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { GPMC_NCS3,     MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { GPMC_NCS4,     MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { GPMC_NCS5,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_NCS6,     MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { GPMC_NCS7,     MUXMODE1,   PULL_UP_SELECTED,             INPUT  },
-  { GPMC_CLK,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_NADV_ALE, MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NOE,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NWE,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NBE0_CLE, MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { GPMC_NBE1,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_NWP,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { GPMC_WAIT0,    MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { GPMC_WAIT1,    MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { GPMC_WAIT2,    MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { GPMC_WAIT3,    MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { DSS_PCLK,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_HSYNC,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_PSYNC,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_ACBIAS,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA0,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA1,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA2,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA3,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA4,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA5,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA6,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA7,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA8,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA9,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA10,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA11,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA12,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA13,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA14,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA15,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA16,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA17,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA18,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA19,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA20,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA21,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA22,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { DSS_DATA23,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { CAM_HS,        MUXMODE0,   PULL_UP_SELECTED,             INPUT },
-  { CAM_VS,        MUXMODE0,   PULL_UP_SELECTED,             INPUT },
-  { CAM_XCLKA,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { CAM_PCLK,      MUXMODE0,   PULL_UP_SELECTED,             INPUT },
-  { CAM_FLD,       MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { CAM_D0,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D1,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D2,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D3,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D4,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D5,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D6,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D7,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D8,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D9,        MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D10,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_D11,       MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CAM_XCLKB,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { CAM_WEN,       MUXMODE4,   PULL_DISABLED,                INPUT  },
-  { CAM_STROBE,    MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { CSI2_DX0,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CSI2_DY0,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CSI2_DX1,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { CSI2_DY1,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP2_FSX,    MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP2_CLKX,   MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP2_DR,     MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP2_DX,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { MMC1_CLK,      MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { MMC1_CMD,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT0,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT1,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT2,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT3,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT4,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT5,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT6,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC1_DAT7,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_CLK,      MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_CMD,      MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT0,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT1,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT2,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT3,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT4,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT5,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT6,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MMC2_DAT7,     MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MCBSP3_DX,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP3_DR,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP3_CLKX,   MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP3_FSX,    MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART2_CTS,     MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { UART2_RTS,     MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { UART2_TX,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { UART2_RX,      MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART1_TX,      MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { UART1_RTS,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART1_CTS,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART1_RX,      MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCBSP4_CLKX,   MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { MCBSP4_DR,     MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { MCBSP4_DX,     MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { MCBSP4_FSX,    MUXMODE1,   PULL_DISABLED,                INPUT  },
-  { MCBSP1_CLKR,   MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP1_FSR,    MUXMODE4,   PULL_UP_SELECTED,             OUTPUT },
-  { MCBSP1_DX,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP1_DR,     MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP1_CLKS,   MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { MCBSP1_FSX,    MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCBSP1_CLKX,   MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { UART3_CTS_RCTX,MUXMODE0,   PULL_UP_SELECTED,                 INPUT  },
-  { UART3_RTS_SD,  MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { UART3_RX_IRRX, MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { UART3_TX_IRTX, MUXMODE0,   PULL_DISABLED,                OUTPUT },
-  { HSUSB0_CLK,    MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_STP,    MUXMODE0,   PULL_UP_SELECTED,             OUTPUT },
-  { HSUSB0_DIR,    MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_NXT,    MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA0,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA1,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA2,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA3,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA4,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA5,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA6,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { HSUSB0_DATA7,  MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { I2C1_SCL,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { I2C1_SDA,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { I2C2_SCL,      MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { I2C2_SDA,      MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { I2C3_SCL,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { I2C3_SDA,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { HDQ_SIO,       MUXMODE4,   PULL_UP_SELECTED,             OUTPUT },
-  { MCSPI1_CLK,    MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI1_SIMO,   MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI1_SOMI,   MUXMODE0,   PULL_DISABLED,                INPUT  },
-  { MCSPI1_CS0,    MUXMODE0,   PULL_UP_SELECTED,                 INPUT  },
-  { MCSPI1_CS1,    MUXMODE0,   PULL_UP_SELECTED,                 OUTPUT },
-  { MCSPI1_CS2,    MUXMODE4,   PULL_DISABLED,                OUTPUT },
-  { MCSPI1_CS3,    MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_CLK,    MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_SIMO,   MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_SOMI,   MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_CS0,    MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { MCSPI2_CS1,    MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { SYS_NIRQ,      MUXMODE0,   PULL_UP_SELECTED,             INPUT  },
-  { SYS_CLKOUT2,   MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_CLK,       MUXMODE3,   PULL_UP_SELECTED,             OUTPUT },
-  { ETK_CTL,       MUXMODE3,   PULL_UP_SELECTED,             OUTPUT },
-  { ETK_D0,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D1,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D2,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D3,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D4,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D5,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D6,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D7,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D8,        MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D9,        MUXMODE4,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D10,       MUXMODE3,   PULL_UP_SELECTED,             OUTPUT },
-  { ETK_D11,       MUXMODE3,   PULL_UP_SELECTED,             OUTPUT },
-  { ETK_D12,       MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D13,       MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D14,       MUXMODE3,   PULL_UP_SELECTED,             INPUT  },
-  { ETK_D15,       MUXMODE3,   PULL_UP_SELECTED,             INPUT  }
-};
-
-VOID
-PadConfiguration (
-  VOID
-  )
-{
-  UINTN  Index;
-  UINT16 PadConfiguration;
-  UINTN  NumPinsToConfigure = sizeof(PadConfigurationTable)/sizeof(PAD_CONFIGURATION);
-
-  for (Index = 0; Index < NumPinsToConfigure; Index++) {
-    //Set up Pad configuration for particular pin.
-    PadConfiguration =  (PadConfigurationTable[Index].MuxMode << MUXMODE_OFFSET);
-    PadConfiguration |= (PadConfigurationTable[Index].PullConfig << PULL_CONFIG_OFFSET);
-    PadConfiguration |= (PadConfigurationTable[Index].InputEnable << INPUTENABLE_OFFSET);
-
-    //Configure the pin with specific Pad configuration.
-    MmioWrite16(PadConfigurationTable[Index].Pin, PadConfiguration);
-  }
-}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Sec/Sec.c b/Platforms/TexasInstruments/BeagleBoard/Sec/Sec.c
deleted file mode 100644
index 0708396..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Sec/Sec.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/** @file
-  C Entry point for the SEC. First C code after the reset vector.
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiPei.h>
-
-#include <Library/DebugLib.h>
-#include <Library/PrePiLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/OmapLib.h>
-#include <Library/ArmLib.h>
-#include <Library/PeCoffGetEntryPointLib.h>
-#include <Library/DebugAgentLib.h>
-
-#include <Ppi/GuidedSectionExtraction.h>
-#include <Guid/LzmaDecompress.h>
-#include <Omap3530/Omap3530.h>
-
-#include "LzmaDecompress.h"
-
-VOID
-PadConfiguration (
-  VOID
-  );
-
-VOID
-ClockInit (
-  VOID
-  );
-
-
-VOID
-TimerInit (
-  VOID
-  )
-{
-  UINTN  Timer            = FixedPcdGet32(PcdOmap35xxFreeTimer);
-  UINT32 TimerBaseAddress = TimerBase(Timer);
-
-  // Set source clock for GPT3 & GPT4 to SYS_CLK
-  MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
-
-  // Set count & reload registers
-  MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
-  MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
-
-  // Disable interrupts
-  MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
-
-  // Start Timer
-  MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
-
-  //Disable OMAP Watchdog timer (WDT2)
-  MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
-  DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
-  MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
-}
-
-VOID
-UartInit (
-  VOID
-  )
-{
-  UINTN   Uart            = FixedPcdGet32(PcdOmap35xxConsoleUart);
-  UINT32  UartBaseAddress = UartBase(Uart);
-
-  // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.
-  MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);
-
-  // Put device in configuration mode.
-  MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);
-
-  // Programmable divisor N = 48Mhz/16/115200 = 26
-  MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000/FixedPcdGet64 (PcdUartDefaultBaudRate)); // low divisor
-  MmioWrite32 (UartBaseAddress + UART_DLH_REG,  0); // high divisor
-
-  // Enter into UART operational mode.
-  MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);
-
-  // Force DTR and RTS output to active
-  MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);
-
-  // Clear & enable fifos
-  MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE);
-
-  // Restore MODE_SELECT
-  MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);
-}
-
-VOID
-InitCache (
-  IN  UINT32  MemoryBase,
-  IN  UINT32  MemoryLength
-  );
-
-EFI_STATUS
-EFIAPI
-ExtractGuidedSectionLibConstructor (
-  VOID
-  );
-
-EFI_STATUS
-EFIAPI
-LzmaDecompressLibConstructor (
-  VOID
-  );
-
-
-VOID
-CEntryPoint (
-  IN  VOID  *MemoryBase,
-  IN  UINTN MemorySize,
-  IN  VOID  *StackBase,
-  IN  UINTN StackSize
-  )
-{
-  VOID *HobBase;
-
-  // Build a basic HOB list
-  HobBase      = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));
-  CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);
-
-  //Set up Pin muxing.
-  PadConfiguration ();
-
-  // Set up system clocking
-  ClockInit ();
-
-
-  // Enable program flow prediction, if supported.
-  ArmEnableBranchPrediction ();
-
-  // Initialize CPU cache
-  InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);
-
-  // Add memory allocation hob for relocated FD
-  BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);
-
-  // Add the FVs to the hob list
-  BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));
-
-  // Start talking
-  UartInit ();
-
-  InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
-  SaveAndSetDebugTimerInterrupt (TRUE);
-
-  DEBUG ((EFI_D_ERROR, "UART Enabled\n"));
-
-  // Start up a free running timer so that the timer lib will work
-  TimerInit ();
-
-  // SEC phase needs to run library constructors by hand.
-  ExtractGuidedSectionLibConstructor ();
-  LzmaDecompressLibConstructor ();
-
-  // Build HOBs to pass up our version of stuff the DXE Core needs to save space
-  BuildPeCoffLoaderHob ();
-  BuildExtractSectionHob (
-    &gLzmaCustomDecompressGuid,
-    LzmaGuidedSectionGetInfo,
-    LzmaGuidedSectionExtraction
-    );
-
-  // Assume the FV that contains the SEC (our code) also contains a compressed FV.
-  DecompressFirstFv ();
-
-  // Load the DXE Core and transfer control to it
-  LoadDxeCoreFromFv (NULL, 0);
-
-  // DXE Core should always load and never return
-  ASSERT (FALSE);
-}
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Sec/Sec.inf b/Platforms/TexasInstruments/BeagleBoard/Sec/Sec.inf
deleted file mode 100644
index 82fc2aa..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Sec/Sec.inf
+++ /dev/null
@@ -1,73 +0,0 @@
-
-#/** @file
-#  SEC - Reset vector code that jumps to C and loads DXE core
-#
-#  Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = BeagleBoardSec
-  FILE_GUID                      = d959e387-7b91-452c-90e0-a1dbac90ddb8
-  MODULE_TYPE                    = SEC
-  VERSION_STRING                 = 1.0
-
-
-[Sources.ARM]
-  Arm/ModuleEntryPoint.S   | GCC
-  Arm/ModuleEntryPoint.asm | RVCT
-
-[Sources.ARM]
-  Sec.c
-  Cache.c
-  PadConfiguration.c
-  Clock.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
-  ArmPkg/ArmPkg.dec
-  OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dec
-  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
-
-[LibraryClasses]
-  BaseLib
-  DebugLib
-  ArmLib
-  IoLib
-  ExtractGuidedSectionLib
-  LzmaDecompressLib
-  OmapLib
-  PeCoffGetEntryPointLib
-  DebugAgentLib
-  MemoryAllocationLib
-  PrePiHobListPointerLib
-
-[FeaturePcd]
-  gEmbeddedTokenSpaceGuid.PcdCacheEnable
-
-[FixedPcd]
-  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
-  gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
-  gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
-  gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
-  gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
-  gEmbeddedTokenSpaceGuid.PcdPrePiStackBase
-  gEmbeddedTokenSpaceGuid.PcdMemoryBase
-  gEmbeddedTokenSpaceGuid.PcdMemorySize
-
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart
-  gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer
-
-  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/Tools/GNUmakefile b/Platforms/TexasInstruments/BeagleBoard/Tools/GNUmakefile
deleted file mode 100644
index ed09e2b..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Tools/GNUmakefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#  
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-CC     = gcc
-CFLAGS = -g
-
-generate_image: generate_image.c
-		$(CC) $(CCFLAGS) $(LDFLAGS) -o generate_image generate_image.c
-
-clean:
-	rm -f generate_image generate_image.exe
diff --git a/Platforms/TexasInstruments/BeagleBoard/Tools/generate_image.c b/Platforms/TexasInstruments/BeagleBoard/Tools/generate_image.c
deleted file mode 100644
index 7fc3fab..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Tools/generate_image.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/** @file
- The data structures in this code come from:
- OMAP35x Applications Processor Technical Reference Manual chapter 25
- OMAP34xx Multimedia Device Technical Reference Manual chapter 26.4.8.
-
- You should use the OMAP35x manual when possible. Some things, like SectionKey,
- are not defined in the OMAP35x manual and you have to use the OMAP34xx manual
- to find the data.
-
-  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-
-
-//TOC structure as defined by OMAP35XX TRM.
-typedef struct {
-  unsigned int  Start;
-  unsigned int  Size;
-  unsigned int  Reserved1;
-  unsigned int  Reserved2;
-  unsigned int  Reserved3;
-  unsigned char Filename[12];
-} TOC_DATA;
-
-//NOTE: OMAP3430 TRM has CHSETTINGS and CHRAM structures.
-typedef struct {
-  unsigned int   SectionKey;
-  unsigned char  Valid;
-  unsigned char  Version;
-  unsigned short Reserved;
-  unsigned int   Flags;
-  unsigned int   PRM_CLKSRC_CTRL;
-  unsigned int   PRM_CLKSEL;
-  unsigned int   CM_CLKSEL1_EMU;
-  unsigned int   CM_CLKSEL_CORE;
-  unsigned int   CM_CLKSEL_WKUP;
-  unsigned int   CM_CLKEN_PLL_DPLL3;
-  unsigned int   CM_AUTOIDLE_PLL_DPLL3;
-  unsigned int   CM_CLKSEL1_PLL;
-  unsigned int   CM_CLKEN_PLL_DPLL4;
-  unsigned int   CM_AUTOIDLE_PLL_DPLL4;
-  unsigned int   CM_CLKSEL2_PLL;
-  unsigned int   CM_CLKSEL3_PLL;
-  unsigned int   CM_CLKEN_PLL_MPU;
-  unsigned int   CM_AUTOIDLE_PLL_MPU;
-  unsigned int   CM_CLKSEL1_PLL_MPU;
-  unsigned int   CM_CLKSEL2_PLL_MPU;
-  unsigned int   CM_CLKSTCTRL_MPU;
-} CHSETTINGS_DATA;
-
-typedef struct {
-  unsigned int   SectionKey;
-  unsigned char  Valid;
-  unsigned char  Reserved1;
-  unsigned char  Reserved2;
-  unsigned char  Reserved3;
-  unsigned short SDRC_SYSCONFIG_LSB;
-  unsigned short SDRC_CS_CFG_LSB;
-  unsigned short SDRC_SHARING_LSB;
-  unsigned short SDRC_ERR_TYPE_LSB;
-  unsigned int   SDRC_DLLA_CTRL;
-  unsigned short Reserved4;
-  unsigned short Reserved5;
-  unsigned int   SDRC_POWER;
-  unsigned short MEMORY_TYPE_CS0;
-  unsigned short Reserved6;
-  unsigned int   SDRC_MCFG_0;
-  unsigned short SDRC_MR_0_LSB;
-  unsigned short SDRC_EMR1_0_LSB;
-  unsigned short SDRC_EMR2_0_LSB;
-  unsigned short SDRC_EMR3_0_LSB;
-  unsigned int   SDRC_ACTIM_CTRLA_0;
-  unsigned int   SDRC_ACTIM_CTRLB_0;
-  unsigned int   SDRC_RFRCTRL_0;
-  unsigned short MEMORY_TYPE_CS1;
-  unsigned short Reserved7;
-  unsigned int   SDRC_MCFG_1;
-  unsigned short SDRC_MR_1_LSB;
-  unsigned short SDRC_EMR1_1_LSB;
-  unsigned short SDRC_EMR2_1_LSB;
-  unsigned short SDRC_EMR3_1_LSB;
-  unsigned int   SDRC_ACTIM_CTRLA_1;
-  unsigned int   SDRC_ACTIM_CTRLB_1;
-  unsigned int   SDRC_RFRCTRL_1;
-  unsigned int   Reserved8;
-  unsigned short Flags;
-  unsigned short Reserved9;
-} CHRAM_DATA;
-
-#define CHSETTINGS_START      0xA0
-#define CHSETTINGS_SIZE       0x50
-#define CHRAM_START           0xF0
-#define CHRAM_SIZE            0x5C
-#define CLOSING_TOC_ITEM_SIZE 4
-
-unsigned char gConfigurationHeader[512];
-unsigned int  gImageExecutionAddress;
-char          *gInputImageFile = NULL;
-char          *gOutputImageFile = NULL;
-char          *gDataFile = NULL;
-
-static
-void
-PrintUsage (
-  void
-  )
-{
-  printf("Usage..\n");
-}
-
-static
-void
-PopulateCHSETTINGSData (
-  FILE            *DataFile,
-  CHSETTINGS_DATA *CHSETTINGSData
-  )
-{
-  unsigned int Value;
-
-  CHSETTINGSData->SectionKey            = 0xC0C0C0C1;
-  CHSETTINGSData->Valid                 = 0x1;
-  CHSETTINGSData->Version               = 0x1;
-  CHSETTINGSData->Reserved              = 0x00;
-  CHSETTINGSData->Flags                 = 0x050001FD;
-
-  //General clock settings.
-  fscanf(DataFile, "PRM_CLKSRC_CTRL=0x%08x\n", &Value);
-  CHSETTINGSData->PRM_CLKSRC_CTRL = Value;
-  fscanf(DataFile, "PRM_CLKSEL=0x%08x\n", &Value);
-  CHSETTINGSData->PRM_CLKSEL = Value;
-  fscanf(DataFile, "CM_CLKSEL1_EMU=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSEL1_EMU = Value;
-
-  //Clock configuration
-  fscanf(DataFile, "CM_CLKSEL_CORE=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSEL_CORE = Value;
-  fscanf(DataFile, "CM_CLKSEL_WKUP=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSEL_WKUP = Value;
-
-  //DPLL3 (Core) settings
-  fscanf(DataFile, "CM_CLKEN_PLL_DPLL3=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKEN_PLL_DPLL3 = Value;
-  fscanf(DataFile, "CM_AUTOIDLE_PLL_DPLL3=0x%08x\n", &Value);
-  CHSETTINGSData->CM_AUTOIDLE_PLL_DPLL3 = Value;
-  fscanf(DataFile, "CM_CLKSEL1_PLL=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSEL1_PLL = Value;
-
-  //DPLL4 (Peripheral) settings
-  fscanf(DataFile, "CM_CLKEN_PLL_DPLL4=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKEN_PLL_DPLL4 = Value;
-  fscanf(DataFile, "CM_AUTOIDLE_PLL_DPLL4=0x%08x\n", &Value);
-  CHSETTINGSData->CM_AUTOIDLE_PLL_DPLL4 = Value;
-  fscanf(DataFile, "CM_CLKSEL2_PLL=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSEL2_PLL = Value;
-  fscanf(DataFile, "CM_CLKSEL3_PLL=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSEL3_PLL = Value;
-
-  //DPLL1 (MPU) settings
-  fscanf(DataFile, "CM_CLKEN_PLL_MPU=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKEN_PLL_MPU = Value;
-  fscanf(DataFile, "CM_AUTOIDLE_PLL_MPU=0x%08x\n", &Value);
-  CHSETTINGSData->CM_AUTOIDLE_PLL_MPU = Value;
-  fscanf(DataFile, "CM_CLKSEL1_PLL_MPU=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSEL1_PLL_MPU = Value;
-  fscanf(DataFile, "CM_CLKSEL2_PLL_MPU=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSEL2_PLL_MPU = Value;
-  fscanf(DataFile, "CM_CLKSTCTRL_MPU=0x%08x\n", &Value);
-  CHSETTINGSData->CM_CLKSTCTRL_MPU = Value;
-}
-
-static
-void
-PopulateCHRAMData (
-  FILE       *DataFile,
-  CHRAM_DATA *CHRAMData
-  )
-{
-  unsigned int Value;
-
-  CHRAMData->SectionKey         = 0xC0C0C0C2;
-  CHRAMData->Valid              = 0x1;
-
-  fscanf(DataFile, "SDRC_SYSCONFIG_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_SYSCONFIG_LSB = Value;
-  fscanf(DataFile, "SDRC_CS_CFG_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_CS_CFG_LSB    = Value;
-  fscanf(DataFile, "SDRC_SHARING_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_SHARING_LSB   = Value;
-  fscanf(DataFile, "SDRC_ERR_TYPE_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_ERR_TYPE_LSB  = Value;
-  fscanf(DataFile, "SDRC_DLLA_CTRL=0x%08x\n", &Value);
-  CHRAMData->SDRC_DLLA_CTRL     = Value;
-  fscanf(DataFile, "SDRC_POWER=0x%08x\n", &Value);
-  CHRAMData->SDRC_POWER         = Value;
-  fscanf(DataFile, "MEMORY_TYPE_CS0=0x%04x\n", &Value);
-  CHRAMData->MEMORY_TYPE_CS0    = Value;
-  fscanf(DataFile, "SDRC_MCFG_0=0x%08x\n", &Value);
-  CHRAMData->SDRC_MCFG_0        = Value;
-  fscanf(DataFile, "SDRC_MR_0_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_MR_0_LSB      = Value;
-  fscanf(DataFile, "SDRC_EMR1_0_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_EMR1_0_LSB    = Value;
-  fscanf(DataFile, "SDRC_EMR2_0_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_EMR2_0_LSB    = Value;
-  fscanf(DataFile, "SDRC_EMR3_0_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_EMR3_0_LSB    = Value;
-  fscanf(DataFile, "SDRC_ACTIM_CTRLA_0=0x%08x\n", &Value);
-  CHRAMData->SDRC_ACTIM_CTRLA_0 = Value;
-  fscanf(DataFile, "SDRC_ACTIM_CTRLB_0=0x%08x\n", &Value);
-  CHRAMData->SDRC_ACTIM_CTRLB_0 = Value;
-  fscanf(DataFile, "SDRC_RFRCTRL_0=0x%08x\n", &Value);
-  CHRAMData->SDRC_RFRCTRL_0     = Value;
-  fscanf(DataFile, "MEMORY_TYPE_CS1=0x%04x\n", &Value);
-  CHRAMData->MEMORY_TYPE_CS1    = Value;
-  fscanf(DataFile, "SDRC_MCFG_1=0x%08x\n", &Value);
-  CHRAMData->SDRC_MCFG_1        = Value;
-  fscanf(DataFile, "SDRC_MR_1_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_MR_1_LSB      = Value;
-  fscanf(DataFile, "SDRC_EMR1_1_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_EMR1_1_LSB    = Value;
-  fscanf(DataFile, "SDRC_EMR2_1_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_EMR2_1_LSB    = Value;
-  fscanf(DataFile, "SDRC_EMR3_1_LSB=0x%04x\n", &Value);
-  CHRAMData->SDRC_EMR3_1_LSB    = Value;
-  fscanf(DataFile, "SDRC_ACTIM_CTRLA_1=0x%08x\n", &Value);
-  CHRAMData->SDRC_ACTIM_CTRLA_1 = Value;
-  fscanf(DataFile, "SDRC_ACTIM_CTRLB_1=0x%08x\n", &Value);
-  CHRAMData->SDRC_ACTIM_CTRLB_1 = Value;
-  fscanf(DataFile, "SDRC_RFRCTRL_1=0x%08x\n", &Value);
-  CHRAMData->SDRC_RFRCTRL_1     = Value;
-
-  CHRAMData->Flags              = 0x0003;
-}
-
-static
-void
-PrepareConfigurationHeader (
-  void
-  )
-{
-  TOC_DATA        Toc;
-  CHSETTINGS_DATA CHSETTINGSData;
-  CHRAM_DATA      CHRAMData;
-  unsigned int    ConfigurationHdrOffset = 0;
-  FILE            *DataFile;
-
-  // Open data file
-  DataFile = fopen(gDataFile, "rb");
-  if (DataFile == NULL) {
-    fprintf(stderr, "Can't open data file %s.\n", gDataFile);
-    exit(1);
-  }
-
-  //Initialize configuration header.
-  memset(gConfigurationHeader, 0x00, sizeof(gConfigurationHeader));
-
-  //CHSETTINGS TOC
-  memset(&Toc, 0x00, sizeof(TOC_DATA));
-  Toc.Start = CHSETTINGS_START;
-  Toc.Size = CHSETTINGS_SIZE;
-  strcpy((char *)Toc.Filename, (const char *)"CHSETTINGS");
-  memcpy(gConfigurationHeader + ConfigurationHdrOffset, &Toc, sizeof(TOC_DATA));
-
-  //Populate CHSETTINGS Data
-  memset(&CHSETTINGSData, 0x00, sizeof(CHSETTINGS_DATA));
-  PopulateCHSETTINGSData(DataFile, &CHSETTINGSData);
-  memcpy(gConfigurationHeader + Toc.Start, &CHSETTINGSData, Toc.Size);
-
-  //Adjust ConfigurationHdrOffset to point to next TOC
-  ConfigurationHdrOffset += sizeof(TOC_DATA);
-
-  //CHRAM TOC
-  memset(&Toc, 0x00, sizeof(TOC_DATA));
-  Toc.Start = CHRAM_START;
-  Toc.Size = CHRAM_SIZE;
-  strcpy((char *)Toc.Filename, (const char *)"CHRAM");
-  memcpy(gConfigurationHeader + ConfigurationHdrOffset, &Toc, sizeof(TOC_DATA));
-
-  //Populate CHRAM Data
-  memset(&CHRAMData, 0x00, sizeof(CHRAM_DATA));
-  PopulateCHRAMData(DataFile, &CHRAMData);
-  memcpy(gConfigurationHeader + Toc.Start, &CHRAMData, Toc.Size);
-
-  //Adjust ConfigurationHdrOffset to point to next TOC
-  ConfigurationHdrOffset += sizeof(TOC_DATA);
-
-  //Closing TOC item
-  memset(gConfigurationHeader + ConfigurationHdrOffset, 0xFF, CLOSING_TOC_ITEM_SIZE);
-  ConfigurationHdrOffset += CLOSING_TOC_ITEM_SIZE;
-
-  // Close data file
-  fclose(DataFile);
-}
-
-static
-void
-ConstructImage (
-  void
-  )
-{
-  FILE         *InputFile;
-  FILE         *OutputFile;
-  unsigned int InputImageFileSize;
-  struct       stat FileStat;
-  char         Ch;
-  unsigned int i;
-
-  InputFile = fopen(gInputImageFile, "rb");
-  if (InputFile == NULL) {
-    fprintf(stderr, "Can't open input file.\n");
-    exit(0);
-  }
-
-  // Get the size of the input image.
-  fstat(fileno(InputFile), &FileStat);
-  InputImageFileSize = FileStat.st_size;
-
-  OutputFile = fopen(gOutputImageFile, "wb");
-  if (OutputFile == NULL) {
-    fprintf(stderr, "Can't open output file %s.\n", gOutputImageFile);
-    exit(0);
-  }
-
-  // Write Configuration header
-  fwrite(gConfigurationHeader, 1, sizeof(gConfigurationHeader), OutputFile);
-
-  // Write image header (Input image size, execution address)
-  fwrite(&InputImageFileSize, 1, 4, OutputFile);
-  fwrite(&gImageExecutionAddress, 1, 4, OutputFile);
-
-  // Copy input image to the output file.
-  for (i = 0; i < InputImageFileSize; i++) {
-    fread(&Ch, 1, 1, InputFile);
-    fwrite(&Ch, 1, 1, OutputFile);
-  }
-
-  fclose(InputFile);
-  fclose(OutputFile);
-}
-
-
-int
-main (
-  int    argc,
-  char** argv
-  )
-{
-  char          Ch;
-  unsigned char *ptr;
-  int           i;
-  int           TwoArg;
-
-  if (argc == 1) {
-    PrintUsage ();
-    exit(1);
-  }
-
-  for (i=1; i < argc; i++) {
-    if (argv[i][0] == '-') {
-      // TwoArg TRUE -E 0x123, FALSE -E0x1234
-      TwoArg = (argv[i][2] != ' ');
-      switch (argv[i][1]) {
-        case 'E': /* Image execution address */
-          gImageExecutionAddress = strtoul (TwoArg ? argv[i+1] : &argv[i][2], (char **)&ptr, 16);
-          break;
-
-        case 'I': /* Input image file */
-          gInputImageFile = TwoArg ? argv[i+1] : &argv[i][2];
-          break;
-
-        case 'O': /* Output image file */
-          gOutputImageFile = TwoArg ? argv[i+1] : &argv[i][2];
-          break;
-
-        case 'D': /* Data file */
-          gDataFile = TwoArg ? argv[i+1] : &argv[i][2];
-          break;
-
-        default:
-          abort ();
-      }
-    }
-  }
-
-
-  //Prepare configuration header
-  PrepareConfigurationHeader ();
-
-  //Build image with configuration header + image header + image
-  ConstructImage ();
-
-  return 0;
-}
diff --git a/Platforms/TexasInstruments/BeagleBoard/Tools/makefile b/Platforms/TexasInstruments/BeagleBoard/Tools/makefile
deleted file mode 100755
index cf50b8f..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Tools/makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#  
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-all: GenerateImage replace
-
-GenerateImage: generate_image.c
-		$(CC) $(CCFLAGS) $(LDFLAGS) -o GenerateImage.exe generate_image.c
-
-replace: replace.c
-		$(CC) $(CCFLAGS) $(LDFLAGS) -o replace.exe replace.c
-
-clean:
-	del GenerateImage.exe generate_image.obj replace.exe replace.obj
diff --git a/Platforms/TexasInstruments/BeagleBoard/Tools/replace.c b/Platforms/TexasInstruments/BeagleBoard/Tools/replace.c
deleted file mode 100644
index 00f4249..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/Tools/replace.c
+++ /dev/null
@@ -1,146 +0,0 @@
-//
-// Quick hack to work around not having sed, or any other reasonable
-// way to edit a file from a script on Windows......
-//
-// Copyright (c) 2010, Apple Inc. All rights reserved.<BR>
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <limits.h>
-
-#define TRUE  1
-#define FALSE 0
-
-typedef struct {
-  char  *Match;
-  int   MatchSize;
-  char  *Replace;
-} MATCH_PAIR;
-
-void
-Usage (char *Name)
-{
-  printf ("\n%s OldFile NewFile MatchString ReplaceString [MatchString2 ReplaceString2]*\n", Name);
-  printf ("    OldFile - Must be arg[1] File to search for MatchStrings\n");
-  printf ("    NewFile - Must be arg[2] File where MatchString has been replaced with ReplaceString\n");
-  printf ("    MatchString & ReplaceString. Required arguments.\n");
-  printf ("    More MatchString/ReplaceString pairs are supported.\n");
-}
-
-//
-// argv[1] - Old File
-// argv[2] - New File
-// argv[3+n] - Match String
-// argv[4+n] - Replace string
-int
-main (int argc, char **argv)
-{
-  FILE *In, *Out;
-  char *Key, *Replace;
-  int  c, i, n, Len, MaxLenKey = 0, MinLenKey = INT_MAX;
-  unsigned long  InFileSize, InFilePos;
-  MATCH_PAIR *Match;
-  int MaxMatch;
-  int ReadCount;
-  int Found;
-
-  if (argc < 5) {
-    fprintf (stderr, "Need at least two files and one Match/Replacement string pair\n");
-    Usage (argv[0]);
-    return -1;
-  } else if ((argc % 2) == 0) {
-    fprintf (stderr, "Match and Replace string must come in pairs\n");
-    return -4;
-  }
-
-  In  = fopen (argv[1], "r");
-  fseek (In, 0, SEEK_END);
-  InFileSize = ftell (In);
-  if (InFileSize == 0) {
-    fprintf (stderr, "Could not open %s\n", argv[1]);
-    return -6;
-  }
-  fseek (In, 0, SEEK_SET);
-
-
-  Out = fopen (argv[2], "w+");
-  if ((In == NULL) || (Out == NULL)) {
-    fprintf (stderr, "Could not open %s\n", argv[2]);
-    return -2;
-  }
-
-  MaxMatch = (argc - 2)/2;
-  Match = calloc (MaxMatch, sizeof (MATCH_PAIR));
-  if (Match == NULL) {
-    return -7;
-  }
-
-  for (n=0; n < MaxMatch; n++) {
-    Match[n].Match   = argv[3 + n*2];
-    Match[n].MatchSize = strlen (argv[3 + n*2]);
-    Match[n].Replace = argv[3 + n*2 + 1];
-    if (Match[n].MatchSize > MaxLenKey) {
-      // Max size of match/replace string pair
-      MaxLenKey = Match[n].MatchSize;
-    }
-    if (Match[n].MatchSize < MinLenKey) {
-      MinLenKey = Match[n].MatchSize;
-    }
-  }
-
-  Key = malloc (MaxLenKey);
-  if (Key == NULL) {
-    return -5;
-  }
-
-  // Search for a match by reading every possition of the file
-  // into a buffer that is as big as the maximum search key size.
-  // Then we can search the keys for a match. If no match
-  // copy the old file character to the new file. If it is a match
-  // then copy the replacement string into the output file.
-  // This code assumes the file system is smart and caches the
-  // file in a buffer. So all the reads don't really hit the disk.
-  InFilePos = 0;
-  while (InFilePos < (InFileSize - MinLenKey)) {
-    fseek (In, InFilePos, SEEK_SET);
-    ReadCount = fread (Key, 1, MaxLenKey, In);
-    for (i = 0, Found = FALSE;i < MaxMatch; i++) {
-      if (ReadCount >= Match[i].MatchSize) {
-        if (!memcmp (Key, Match[i].Match, Match[i].MatchSize)) {
-          InFilePos += (Match[i].MatchSize - 1);
-          fputs (Match[i].Replace, Out);
-          Found = TRUE;
-          break;
-        }
-      }
-    }
-    if (!Found) {
-      fputc (Key[0], Out);
-    }
-
-    InFilePos++;
-  }
-
-  // We stoped searching when we got to the point that we could no longer match.
-  // So the last few bytes of the file are not copied in the privous loop
-  fseek (In, InFilePos, SEEK_SET);
-  while ((c = fgetc (In)) != EOF) {
-    fputc (c, Out);
-  }
-
-  fclose (In);
-  fclose (Out);
-  free (Key);
-  free (Match);
-  return 0;
-}
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/b.bat b/Platforms/TexasInstruments/BeagleBoard/b.bat
deleted file mode 100755
index 76ddea6..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/b.bat
+++ /dev/null
@@ -1,68 +0,0 @@
-@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-@REM This program and the accompanying materials
-@REM are licensed and made available under the terms and conditions of the BSD License
-@REM which accompanies this distribution.  The full text of the license may be found at
-@REM http://opensource.org/licenses/bsd-license.php
-@REM
-@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-@REM
-
-@REM Example usage of this script. default is a DEBUG build
-@REM b
-@REM b clean
-@REM b release 
-@REM b release clean
-@REM b -v -y build.log
-
-ECHO OFF
-@REM Setup Build environment. Sets WORKSPACE and puts build in path
-CALL ..\edksetup.bat
-
-@REM Set for tools chain. Currently RVCT
-SET TARGET_TOOLS=RVCT
-SET TARGET=DEBUG
-
-@if /I "%1"=="RELEASE" (
-  @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it 
-  SET TARGET=RELEASE
-  shift /1
-)
-
-SET BUILD_ROOT=%WORKSPACE%\Build\BeagleBoard\%TARGET%_%TARGET_TOOLS%
-
-@REM Build the Beagle Board firmware and creat an FD (FLASH Device) Image.
-CALL build -p BeagleBoardPkg\BeagleBoardPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8
-@if ERRORLEVEL 1 goto Exit
-
-@if /I "%1"=="CLEAN" goto Clean
-
-@REM
-@REM Ram starts at 0x80000000
-@REM OMAP 3530 TRM defines 0x80008208 as the entry point
-@REM The reset vector is caught by the mask ROM in the OMAP 3530 so that is why this entry 
-@REM point looks so strange. 
-@REM OMAP 3430 TRM section 26.4.8 has Image header information. (missing in OMAP 3530 TRM)
-@REM
-@cd Tools
-
-ECHO Building tools...
-CALL nmake 
-
-ECHO Patching image with ConfigurationHeader.dat
-CALL GenerateImage -D ..\ConfigurationHeader.dat -E 0x80008208 -I %BUILD_ROOT%\FV\BEAGLEBOARD_EFI.fd -O %BUILD_ROOT%\FV\BeagleBoard_EFI_flashboot.fd
-
-ECHO Patching ..\Debugger_scripts ...
-SET DEBUGGER_SCRIPT=..\Debugger_scripts
-@for /f %%a IN ('dir /b %DEBUGGER_SCRIPT%\*.inc %DEBUGGER_SCRIPT%\*.cmm') do (
-  @CALL replace %DEBUGGER_SCRIPT%\%%a %BUILD_ROOT%\%%a ZZZZZZ %BUILD_ROOT% WWWWWW  %WORKSPACE%
-)
-
-cd ..
-:Exit
-EXIT /B
-
-:Clean
-cd Tools
-CALL nmake clean
-cd ..
diff --git a/Platforms/TexasInstruments/BeagleBoard/ba.bat b/Platforms/TexasInstruments/BeagleBoard/ba.bat
deleted file mode 100755
index 24a60e4..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/ba.bat
+++ /dev/null
@@ -1,68 +0,0 @@
-@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-@REM This program and the accompanying materials
-@REM are licensed and made available under the terms and conditions of the BSD License
-@REM which accompanies this distribution.  The full text of the license may be found at
-@REM http://opensource.org/licenses/bsd-license.php
-@REM
-@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-@REM
-
-@REM Example usage of this script. default is a DEBUG build
-@REM b
-@REM b clean
-@REM b release 
-@REM b release clean
-@REM b -v -y build.log
-
-ECHO OFF
-@REM Setup Build environment. Sets WORKSPACE and puts build in path
-CALL ..\edksetup.bat
-
-@REM Set for tools chain. Currently ARMGCC
-SET TARGET_TOOLS=ARMGCC
-SET TARGET=DEBUG
-
-@if /I "%1"=="RELEASE" (
-  @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it 
-  SET TARGET=RELEASE
-  shift /1
-)
-
-SET BUILD_ROOT=%WORKSPACE%\Build\BeagleBoard\%TARGET%_%TARGET_TOOLS%
-
-@REM Build the Beagle Board firmware and creat an FD (FLASH Device) Image.
-CALL build -p BeagleBoardPkg\BeagleBoardPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8
-@if ERRORLEVEL 1 goto Exit
-
-@if /I "%1"=="CLEAN" goto Clean
-
-@REM
-@REM Ram starts at 0x80000000
-@REM OMAP 3530 TRM defines 0x80008208 as the entry point
-@REM The reset vector is caught by the mask ROM in the OMAP 3530 so that is why this entry 
-@REM point looks so strange. 
-@REM OMAP 3430 TRM section 26.4.8 has Image header information. (missing in OMAP 3530 TRM)
-@REM
-@cd Tools
-
-ECHO Building tools...
-CALL nmake 
-
-ECHO Patching image with ConfigurationHeader.dat
-CALL GenerateImage -D ..\ConfigurationHeader.dat -E 0x80008208 -I %BUILD_ROOT%\FV\BEAGLEBOARD_EFI.fd -O %BUILD_ROOT%\FV\BeagleBoard_EFI_flashboot.fd
-
-ECHO Patching ..\Debugger_scripts ...
-SET DEBUGGER_SCRIPT=..\Debugger_scripts
-@for /f %%a IN ('dir /b %DEBUGGER_SCRIPT%\*.inc %DEBUGGER_SCRIPT%\*.cmm') do (
-  @CALL replace %DEBUGGER_SCRIPT%\%%a %BUILD_ROOT%\%%a ZZZZZZ %BUILD_ROOT% WWWWWW  %WORKSPACE%
-)
-
-cd ..
-:Exit
-EXIT /B
-
-:Clean
-cd Tools
-CALL nmake clean
-cd ..
diff --git a/Platforms/TexasInstruments/BeagleBoard/build.sh b/Platforms/TexasInstruments/BeagleBoard/build.sh
deleted file mode 100755
index 32b22f0..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/build.sh
+++ /dev/null
@@ -1,150 +0,0 @@
-#!/bin/bash
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-set -e
-shopt -s nocasematch
-
-function process_debug_scripts {
-  if [[ -d $1 ]]; then
-    for filename in `ls $1`
-    do
-      sed -e "s@ZZZZZZ@$BUILD_ROOT@g" -e "s@WWWWWW@$WORKSPACE@g" \
-            "$1/$filename" \
-            > "$BUILD_ROOT/$filename"
-
-      #For ARMCYGWIN, we have to change /cygdrive/c to c:
-      if [[ $TARGET_TOOLS == RVCT31CYGWIN ]]
-      then
-        mv "$BUILD_ROOT/$filename" "$BUILD_ROOT/$filename"_temp
-        sed -e "s@/cygdrive/\(.\)@\1:@g" \
-              "$BUILD_ROOT/$filename"_temp \
-              > "$BUILD_ROOT/$filename"
-        rm -f "$BUILD_ROOT/$filename"_temp
-      fi
-    done
-  fi
-}
-
-
-#
-# Setup workspace if it is not set
-#
-if [ -z "${WORKSPACE:-}" ]
-then
-  echo Initializing workspace
-  cd ..
-# Uses an external BaseTools project 
-#  export EDK_TOOLS_PATH=`pwd`/../BaseTools
-# Uses the BaseTools in edk2
-  export EDK_TOOLS_PATH=`pwd`/BaseTools
-  source edksetup.sh BaseTools
-else
-  echo Building from: $WORKSPACE
-fi
-
-#
-# Pick a default tool type for a given OS if no toolchain already defined
-#
-if [ -z "${TARGET_TOOLS:-}" ]
-then
-  case `uname` in
-    CYGWIN*) 
-      TARGET_TOOLS=RVCT31CYGWIN 
-      ;;
-    Linux*)  
-      if [[ ! -z `locate arm-linux-gnueabi-gcc` ]]; then
-        TARGET_TOOLS=ARMLINUXGCC
-      else 
-        TARGET_TOOLS=ARMGCC 
-      fi
-      ;;
-    Darwin*) 
-      Major=$(uname -r | cut -f 1 -d '.')
-      if [[ $Major == 9 ]]
-      then
-        # Not supported by this open source project
-        TARGET_TOOLS=XCODE31
-      else 
-        TARGET_TOOLS=XCODE32
-      fi  
-      ;;
-  esac
-fi
-
-TARGET=DEBUG
-for arg in "$@"
-do
-  if [[ $arg == RELEASE ]]; 
-  then
-    TARGET=RELEASE
-  fi
-done
-
-BUILD_ROOT=$WORKSPACE/Build/BeagleBoard/"$TARGET"_"$TARGET_TOOLS"
-GENERATE_IMAGE=$WORKSPACE/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Tools/generate_image
-FLASH_BOOT=$BUILD_ROOT/FV/BeagleBoard_EFI_flashboot.fd
-
-if  [[ ! -e $EDK_TOOLS_PATH/Source/C/bin ]];
-then
-  # build the tools if they don't yet exist
-  echo Building tools: $EDK_TOOLS_PATH
-  make -C $EDK_TOOLS_PATH
-else
-  echo using prebuilt tools
-fi
-
-#
-# Build the edk2 BeagleBoard code
-#
-if [[ $TARGET == RELEASE ]]; then
-  build -p $WORKSPACE/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc -a ARM -t $TARGET_TOOLS -b $TARGET -D DEBUG_TARGET=RELEASE ${2:-} ${3:-} ${4:-} ${5:-} ${6:-} ${7:-} ${8:-}
-else
-  build -p ${WORKSPACE:-}/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc -a ARM -t $TARGET_TOOLS -b $TARGET ${1:-} ${2:-} ${3:-} ${4:-} ${5:-} ${6:-} ${7:-} ${8:-}
-fi
-
-
-for arg in "$@"
-do
-  if [[ $arg == clean ]]; then
-    # no need to post process if we are doing a clean
-    exit
-  elif [[ $arg == cleanall ]]; then
-    make -C $EDK_TOOLS_PATH clean
-    make -C $WORKSPACE/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Tools clean
-    exit
-    
-  fi
-done
-
-
-#
-#  Build the tool used to patch the FLASH image to work with the Beagle board ROM
-#
-if [[ ! -e $GENERATE_IMAGE ]];
-then
-  make -C $WORKSPACE/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Tools
-fi
-
-echo Patching FD to work with BeagleBoard ROM
-rm -f $FLASH_BOOT
-
-#
-# Ram starts at 0x80000000
-# OMAP 3530 TRM defines 0x80008000 as the entry point
-# The reset vector is caught by the mask ROM in the OMAP 3530 so that is why this entry 
-# point looks so strange. 
-# OMAP 3430 TRM section 26.4.8 has Image header information. (missing in OMAP 3530 TRM)
-#
-$GENERATE_IMAGE -D $WORKSPACE/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/ConfigurationHeader.dat -E 0x80008000 -I $BUILD_ROOT/FV/BEAGLEBOARD_EFI.fd -O $FLASH_BOOT
-
-echo Creating debugger scripts
-process_debug_scripts $WORKSPACE/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Debugger_scripts
-
diff --git a/Platforms/TexasInstruments/BeagleBoard/readme.txt b/Platforms/TexasInstruments/BeagleBoard/readme.txt
deleted file mode 100644
index d15b1fb..0000000
--- a/Platforms/TexasInstruments/BeagleBoard/readme.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-On Ubuntu 10.04, in your $(WORKROOT) directory (eg: ~/dev/)
-
-Build UEFI for the BeagleBoard :
-================================
-# Requirements
-sudo apt-get install uuid-dev
-
-# Get the arm-none-eabi Toolchain:
-cd $(WORKROOT)
-wget http://www.codesourcery.com/sgpp/lite/arm/portal/package7813/public/arm-none-eabi/arm-2010.09-51-arm-none-eabi-i686-pc-linux-gnu.tar.bz2
-tar xjf arm-2010.09-51-arm-none-eabi-i686-pc-linux-gnu.tar.bz2
-Add the arm-none-eabi toolchain to your path
-
-# Build UEFI
-svn co https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2 edk2 --username guest
-cd $(WORKROOT)/edk2
-svn co https://edk2-fatdriver2.svn.sourceforge.net/svnroot/edk2-fatdriver2/trunk/FatPkg FatPkg --username guest
-patch -p1 < ArmPlatformPkg/Documentation/patches/BaseTools-Pending-Patches.patch
-cd OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/
-./build.sh
-
-# To Build a Release verion of UEFI
-./build.sh RELEASE
-
-
-Test UEFI on qEmu :
-===================
-
-Installing Linaro qEmu:
------------------------
-cd $(WORKROOT)
-git clone git://git.linaro.org/qemu/qemu-linaro.git
-cd $(WORKROOT)/qemu-linaro
-./configure --target-list=arm-softmmu,arm-linux-user,armeb-linux-user
-make
-
-Installing Linaro image Creator:
---------------------------------
-wget http://launchpad.net/linaro-image-tools/trunk/0.4.8/+download/linaro-image-tools-0.4.8.tar.gz
-tar xzf linaro-image-tools-0.4.8.tar.gz
-cd $(WORKROOT)/linaro-image-tools-0.4.8/
-sudo apt-get install parted dosfstools uboot-mkimage python-argparse python-dbus python-debian python-parted qemu-arm-static btrfs-tools command-not-found
-
-Creating u-boot + Linux Linaro image:
--------------------------------------
-mkdir $(WORKROOT)/beagle_image && cd $(WORKROOT)/beagle_image
-wget http://releases.linaro.org/platform/linaro-m/hwpacks/final/hwpack_linaro-omap3_20101109-1_armel_supported.tar.gz
-wget http://releases.linaro.org/platform/linaro-m/headless/release-candidate/linaro-m-headless-tar-20101101-0.tar.gz
-sudo $(WORKROOT)/linaro-image-tools-0.4.8/linaro-media-create --image_file beagle_sd.img --dev beagle --binary linaro-m-headless-tar-20101101-0.tar.gz --hwpack hwpack_linaro-omap3_20101109-1_armel_supported.tar.gz
-sudo chmod a+rw beagle_sd.img
-
-Test u-boot + Linux Linaro image on qEmu:
------------------------------------------
-$(WORKROOT)/qemu-linaro/arm-softmmu/qemu-system-arm -M beagle -sd $(WORKROOT)/beagle_image/beagle_sd.img -serial stdio -clock unix
-# in u-boot:
-boot
-
-Start UEFI from NOR Flash :
----------------------------
-# Adding zImage to beagle_sd.img
-mkdir /tmp/beagle_img1
-sudo mount -o loop,offset=$[63*512] $(WORKROOT)/beagle_image/beagle_sd.img /tmp/beagle_img1
-cp zImage /tmp/beagle_img1
-sudo umount /tmp/beagle_img1
-
-./qemu-system-arm -M beagle -mtdblock /work/tianocore/Build/BeagleBoard/DEBUG_ARMGCC/FV/BeagleBoard_EFI_flashboot.fd -serial stdio -sd /work/linaro-image-tools-0.4.8/beagle_sd.img
-
-Start UEFI from SD card :
--------------------------
-# To replace u-boot by uefi in the SD card
-1) Build the BeagleBoard UEFI firmware without the OMAP353x header
-cd $(WORKROOT)/edk2/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/
-./build.sh -D EDK2_SECOND_STAGE_BOOTOLADER=1
-
-2) Replace u-boot by UEFI
-sudo mount -o loop,offset=$[63*512] $(WORKROOT)/beagle_image/beagle_sd.img /tmp/beagle_img1
-sudo cp ../Build/BeagleBoard/DEBUG_ARMGCC/FV/BEAGLEBOARD_EFI.fd /tmp/beagle_img1/u-boot.bin
-sudo umount /tmp/beagle_img1
diff --git a/README b/README
index 5ae4b52..702b1cb 100644
--- a/README
+++ b/README
@@ -1,2 +1,5 @@
-This is still work in progress, but from this point onwards, the master branch
-of OpenPlatformPkg will not be rebased. 
+This repository holds support for UEFI ports for various platforms,
+until such a time as a complete solution for platform support in
+Tianocore EDK2 is available.
+
+The "upstream" for this project is https://git.linaro.org/uefi/OpenPlatformPkg.git
author	Haojian Zhuang <haojian.zhuang@linaro.org>	2017-11-09 10:38:31 +0800
committer	GitHub <noreply@github.com>	2017-11-09 10:38:31 +0800
commit	afdc321b862b4279e8faca4e20c99c7981c93897 (patch)
tree	0169d848937191cf10d3432ba578659062e8738d
parent	473e79955da9c1ba38a63fd3eefe5fd04f5cab35 (diff)
parent	cf17095317ae5a2704c439e93459595e8f249579 (diff)
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