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authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>2019-07-22 13:32:48 (GMT)
committerAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>2019-07-22 15:20:34 (GMT)
commite8dca7e1e161cdb2c648d5711a0a9bca963e9ad3 (patch)
treee036ab9d55b52821496804da241b1173e17b69b2
parent055aa9b1f48728eb566b26d197d41068a8acaf84 (diff)
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pan/midgard: Report spills:fills to shader-db
Route this info through so we can track how we're doing on register spilling. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
-rw-r--r--src/panfrost/midgard/compiler.h4
-rw-r--r--src/panfrost/midgard/midgard_compile.c6
-rw-r--r--src/panfrost/midgard/midgard_schedule.c4
3 files changed, 12 insertions, 2 deletions
diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index 2ea0cc6..186ee7d 100644
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -197,6 +197,10 @@ typedef struct compiler_context {
/* Number of bytes used for Thread Local Storage */
unsigned tls_size;
+ /* Count of spills and fills for shaderdb */
+ unsigned spills;
+ unsigned fills;
+
/* Current NIR function */
nir_function *func;
diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index 822cc6a..7d6bd31 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -2741,12 +2741,14 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl
fprintf(stderr, "shader%d - %s shader: "
"%u inst, %u bundles, %u quadwords, "
- "%u registers, %u threads, %u loops\n",
+ "%u registers, %u threads, %u loops, "
+ "%d:%d spills:fills\n",
SHADER_DB_COUNT++,
gl_shader_stage_name(ctx->stage),
nr_ins, nr_bundles, nr_quadwords,
nr_registers, nr_threads,
- ctx->loop_count);
+ ctx->loop_count,
+ ctx->spills, ctx->fills);
}
diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index 84b7b1b..a53ba7e 100644
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -720,6 +720,8 @@ schedule_program(compiler_context *ctx)
midgard_instruction st = v_load_store_scratch(ins->ssa_args.dest, spill_slot, true, ins->mask);
mir_insert_instruction_before(mir_next_op(ins), st);
+
+ ctx->spills++;
}
/* Insert a load from TLS before the first consecutive
@@ -759,6 +761,8 @@ schedule_program(compiler_context *ctx)
/* Rewrite to use */
mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
+
+ ctx->fills++;
}
}
}