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authorMarek Olšák <marek.olsak@amd.com>2019-07-17 01:30:57 (GMT)
committerMarek Olšák <marek.olsak@amd.com>2019-07-20 00:16:54 (GMT)
commit47f41af06c7eb1cc7e99b3d384a089cf94fd3728 (patch)
tree23b696e50ce35a034ee3f115dfb01e847980f515
parent7a764b963a50cfab4a684b492c377d31a669d747 (diff)
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radeonsi: return success from vi_dcc_clear_level to simplify callers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
-rw-r--r--src/gallium/drivers/radeonsi/si_blit.c12
-rw-r--r--src/gallium/drivers/radeonsi/si_clear.c40
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.h2
3 files changed, 26 insertions, 28 deletions
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 63601ec..eb9e2bb 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1127,18 +1127,10 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
* This is still the fastest codepath even with this clear.
*/
if (vi_dcc_enabled(dst, info->dst.level)) {
- /* TODO: Implement per-level DCC clears for GFX9. */
- if (sctx->chip_class >= GFX9 &&
- info->dst.resource->last_level != 0)
+ if (!vi_dcc_clear_level(sctx, dst, info->dst.level,
+ DCC_UNCOMPRESSED))
goto resolve_to_temp;
- /* This can happen with mipmapping. */
- if (sctx->chip_class == GFX8 &&
- !dst->surface.u.legacy.level[info->dst.level].dcc_fast_clear_size)
- goto resolve_to_temp;
-
- vi_dcc_clear_level(sctx, dst, info->dst.level,
- 0xFFFFFFFF);
dst->dirty_level_mask &= ~(1 << info->dst.level);
}
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 00884b4..0e8808b 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -231,7 +231,7 @@ static bool vi_get_fast_clear_parameters(struct si_screen *sscreen,
return true;
}
-void vi_dcc_clear_level(struct si_context *sctx,
+bool vi_dcc_clear_level(struct si_context *sctx,
struct si_texture *tex,
unsigned level, unsigned clear_value)
{
@@ -250,21 +250,28 @@ void vi_dcc_clear_level(struct si_context *sctx,
if (sctx->chip_class >= GFX9) {
/* Mipmap level clears aren't implemented. */
- assert(tex->buffer.b.b.last_level == 0);
+ if (tex->buffer.b.b.last_level > 0)
+ return false;
+
/* 4x and 8x MSAA needs a sophisticated compute shader for
* the clear. See AMDVLK. */
- assert(tex->buffer.b.b.nr_storage_samples <= 2);
+ if (tex->buffer.b.b.nr_storage_samples >= 4)
+ return false;
+
clear_size = tex->surface.dcc_size;
} else {
unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
/* If this is 0, fast clear isn't possible. (can occur with MSAA) */
- assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
+ if (!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
+ return false;
+
/* Layered 4x and 8x MSAA DCC fast clears need to clear
* dcc_fast_clear_size bytes for each layer. A compute shader
* would be more efficient than separate per-layer clear operations.
*/
- assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
+ if (tex->buffer.b.b.nr_storage_samples >= 4 && num_layers > 1)
+ return false;
dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
@@ -273,6 +280,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
&clear_value, 4, SI_COHERENCY_CB_META, false);
+ return true;
}
/* Set the same micro tile mode as the destination of the last MSAA resolve.
@@ -483,11 +491,6 @@ static void si_do_fast_color_clear(struct si_context *sctx,
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
- /* This can happen with mipmapping or MSAA. */
- if (sctx->chip_class == GFX8 &&
- !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
- continue;
-
if (!vi_get_fast_clear_parameters(sctx->screen,
tex->buffer.b.b.format,
fb->cbufs[i]->format,
@@ -498,21 +501,24 @@ static void si_do_fast_color_clear(struct si_context *sctx,
if (eliminate_needed && too_small)
continue;
+ /* TODO: This DCC+CMASK clear doesn't work with MSAA. */
+ if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer &&
+ eliminate_needed)
+ continue;
+
+ if (!vi_dcc_clear_level(sctx, tex, 0, reset_value))
+ continue;
+
+ tex->separate_dcc_dirty = true;
+
/* DCC fast clear with MSAA should clear CMASK to 0xC. */
if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
- /* TODO: This doesn't work with MSAA. */
- if (eliminate_needed)
- continue;
-
uint32_t clear_value = 0xCCCCCCCC;
si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
tex->cmask_offset, tex->surface.cmask_size,
&clear_value, 4, SI_COHERENCY_CB_META, false);
fmask_decompress_needed = true;
}
-
- vi_dcc_clear_level(sctx, tex, 0, reset_value);
- tex->separate_dcc_dirty = true;
} else {
if (too_small)
continue;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 6798606..8e2bd83 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1280,7 +1280,7 @@ void si_init_buffer_functions(struct si_context *sctx);
/* si_clear.c */
enum pipe_format si_simplify_cb_format(enum pipe_format format);
bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
-void vi_dcc_clear_level(struct si_context *sctx,
+bool vi_dcc_clear_level(struct si_context *sctx,
struct si_texture *tex,
unsigned level, unsigned clear_value);
void si_init_clear_functions(struct si_context *sctx);