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authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>2019-07-19 23:27:39 (GMT)
committerAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>2019-07-22 15:20:34 (GMT)
commit055aa9b1f48728eb566b26d197d41068a8acaf84 (patch)
tree684174faff3edaa7b2d2d9b44a43548da9d96284
parentf0d0061b18aa39179552fe6f6c49e3f0ad63a9c1 (diff)
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panfrost/midgard: Reenable pipeline register creation
This was disabled to permit regression-free RA work. Now that the spill code is in place, we can reenable, with some caveats about efficacy. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
-rw-r--r--src/panfrost/midgard/midgard_schedule.c19
1 files changed, 9 insertions, 10 deletions
diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index 862b930..84b7b1b 100644
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -769,19 +769,18 @@ schedule_program(compiler_context *ctx)
g = allocate_registers(ctx, &spilled);
} while(spilled && ((iter_count--) > 0));
- /* We would like to run RA after scheduling, but spilling can
- * complicate this */
+ /* After RA finishes, we schedule all at once */
- mir_foreach_block(ctx, block) {
- schedule_block(ctx, block);
- }
-#if 0
-
- /* Pipeline registers creation is a prepass before RA */
- mir_create_pipeline_registers(ctx);
-#endif
+ mir_foreach_block(ctx, block) {
+ schedule_block(ctx, block);
+ }
+ /* Finally, we create pipeline registers as a peephole pass after
+ * scheduling. This isn't totally optimal, since there are cases where
+ * the usage of pipeline registers can eliminate spills, but it does
+ * save some power */
+ mir_create_pipeline_registers(ctx);
if (iter_count <= 0) {
fprintf(stderr, "panfrost: Gave up allocating registers, rendering will be incomplete\n");