From 6677876181cc8772bca8a372479a500d160f3993 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 20 Jan 2009 11:56:11 -0600 Subject: 83xx: Use the proper sequence for updating IMMR. This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha Signed-off-by: Scott Wood Signed-off-by: Kim Phillips --- cpu/mpc83xx/start.S | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index beebc9951c..26e31061f4 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -200,9 +200,23 @@ boot_cold: /* time t 3 */ nop boot_warm: /* time t 5 */ mfmsr r5 /* save msr contents */ + + /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ + bl 1f +1: mflr r7 + lis r3, CONFIG_SYS_IMMR@h ori r3, r3, CONFIG_SYS_IMMR@l + + lwz r6, IMMRBAR(r4) + isync + stw r3, IMMRBAR(r4) + lwz r6, 0(r7) /* Arbitrary external load */ + isync + + lwz r6, IMMRBAR(r3) + isync /* Initialise the E300 processor core */ /*------------------------------------------*/ @@ -212,9 +226,7 @@ boot_warm: /* time t 5 */ * is loaded. Wait for the rest before branching * to another flash page. */ - addi r7, r3, 0x50b0 -1: dcbi 0, r7 - lwz r6, 0(r7) +1: lwz r6, 0x50b0(r3) andi. r6, r6, 1 beq 1b #endif -- cgit v1.2.3