aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-ppc/fsl_lbc.h
Commit message (Collapse)AuthorAgeFilesLines
* ppc/p4080: Add p4080 platform immap definitionsKumar Gala2009-09-241-0/+4
| | | | | | | | | | | | | | | The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix LCRR_CLKDIV definesKumar Gala2009-09-241-0/+8
| | | | | | | | | | | | | | | | | | | | | For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com>
* 83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]xPeter Tyser2009-06-121-2/+2
| | | | | | | | Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Add LSDMR (SDRAM Mode Register) definition on localbusKumar Gala2009-03-301-0/+27
| | | | | | | The masks for various bit defines of LSDMR are common and thus we can define them in one place rather than replicating them in each config.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Handle eLBC difference w/36-bit physicalKumar Gala2009-01-231-1/+7
| | | | | | | | | | | | The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-191-1/+4
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* FSL: Moved BR_PHYS_ADDR for localbus to common headerKumar Gala2008-12-041-0/+8
| | | | | | | | | | | The BR_PHYS_ADDR macro is useful on all machines that have local bus which is pretty much all 83xx/85xx/86xx chips. Additionally most 85xx & 86xx will need it if they want to support 36-bit physical addresses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-291-0/+130
| | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Fix merge problemsStefan Roese2008-08-061-0/+9
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Added the upmconfig() function for 85xx.Sergei Poselenov2008-06-111-0/+4
| | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 83xx/85xx/86xx: add more MxMR local bus definitionsWolfgang Grandegger2008-06-101-5/+38
| | | | | | | | | | | | | | | | | | | | 83xx/85xx/86xx: add more MxMR local bus definitions This patch adds more macro definitions for the UPM Machine Mode Registers They are copied from "include/mpc82xx.h" to simplify the merge of all 8xxx common local bus definitions into include/asm-ppc/fsl_lbc.h. They are required for my forthcoming FSL NAND UPM driver re-write and the support for the TQM8548 module. This patch is based on the following two patches from Anton Vorontsov: http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06511.html http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06587.html I leave coding style violation fixes, code beautification and name corrections to somebody else ;-(. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* 83xx/85xx: further localbus cleanupsAnton Vorontsov2008-06-101-2/+15
| | | | | | | Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.hAnton Vorontsov2008-06-101-0/+251
This patch moves Freescale Localbus defines out of mpc83xx.h, so we could use it on MPC85xx and MPC86xx processors. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 05:22:40 +0000