diff options
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xx/fec.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/miiphy.c | 72 |
2 files changed, 38 insertions, 38 deletions
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index d4abeb1b2f..a2d2bd6d8d 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -888,14 +888,14 @@ static int mii_discover_phy(struct eth_device *dev) udelay(10000); /* wait 10ms */ } for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type ", phytype, pass); #endif if (phytype != 0xffff) { phyaddr = phyno; phytype |= mii_send(mk_mii_read(phyno, - PHY_PHYIDR1)) << 16; + MII_PHYSID1)) << 16; #ifdef ET_DEBUG printf("PHY @ 0x%x pass %d type ",phyno,pass); diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 3b28122014..206c476648 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -89,60 +89,60 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 exsr = 0x0000; #endif - miiphy_read (devname, addr, PHY_BMSR, &bmsr); + miiphy_read (devname, addr, MII_BMSR, &bmsr); #if defined(CONFIG_PHY_GIGE) - if (bmsr & PHY_BMSR_EXT_STAT) - miiphy_read (devname, addr, PHY_EXSR, &exsr); + if (bmsr & BMSR_ESTATEN) + miiphy_read (devname, addr, MII_ESTATUS, &exsr); - if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) { + if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) { /* 1000BASE-X */ u16 anar = 0x0000; - if (exsr & PHY_EXSR_1000XF) - anar |= PHY_X_ANLPAR_FD; + if (exsr & ESTATUS_1000XF) + anar |= ADVERTISE_1000XFULL); - if (exsr & PHY_EXSR_1000XH) - anar |= PHY_X_ANLPAR_HD; + if (exsr & ESTATUS_1000XH) + anar |= ADVERTISE_1000XHALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); } else #endif { u16 anar, btcr; - miiphy_read (devname, addr, PHY_ANAR, &anar); - anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10); + miiphy_read (devname, addr, MII_ADVERTISE, &anar); + anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL | + LPA_100HALF | LPA_10FULL | LPA_10HALF); - miiphy_read (devname, addr, PHY_1000BTCR, &btcr); + miiphy_read (devname, addr, MII_CTRL1000, &btcr); btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); - if (bmsr & PHY_BMSR_100T4) - anar |= PHY_ANLPAR_T4; + if (bmsr & BMSR_100BASE4) + anar |= LPA_100BASE4; - if (bmsr & PHY_BMSR_100TXF) - anar |= PHY_ANLPAR_TXFD; + if (bmsr & BMSR_100FULL) + anar |= LPA_100FULL; - if (bmsr & PHY_BMSR_100TXH) - anar |= PHY_ANLPAR_TX; + if (bmsr & BMSR_100HALF) + anar |= LPA_100HALF; - if (bmsr & PHY_BMSR_10TF) - anar |= PHY_ANLPAR_10FD; + if (bmsr & BMSR_10FULL) + anar |= LPA_10FULL; - if (bmsr & PHY_BMSR_10TH) - anar |= PHY_ANLPAR_10; + if (bmsr & BMSR_10HALF) + anar |= LPA_10HALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); #if defined(CONFIG_PHY_GIGE) - if (exsr & PHY_EXSR_1000TF) + if (exsr & ESTATUS_1000_TFULL) btcr |= PHY_1000BTCR_1000FD; - if (exsr & PHY_EXSR_1000TH) + if (exsr & ESTATUS_1000_THALF) btcr |= PHY_1000BTCR_1000HD; - miiphy_write (devname, addr, PHY_1000BTCR, btcr); + miiphy_write (devname, addr, MII_CTRL1000, btcr); #endif } @@ -152,21 +152,21 @@ int phy_setup_aneg (char *devname, unsigned char addr) */ u16 adv; - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF | + LPA_10FULL | LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); - miiphy_read (devname, addr, PHY_1000BTCR, &adv); + miiphy_read (devname, addr, MII_CTRL1000, &adv); adv |= (0x0300); - miiphy_write (devname, addr, PHY_1000BTCR, adv); + miiphy_write (devname, addr, MII_CTRL1000, adv); #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &bmcr); - bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, bmcr); + miiphy_read (devname, addr, MII_BMCR, &bmcr); + bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, bmcr); return 0; } |